©2008 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-5624/7
1
Functional Block Diagram
IDT70V35/34S/L
IDT70V25/24S/L
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
◆◆
◆◆
◆Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆◆
◆◆
◆IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
◆◆
◆◆
◆M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆BUSY and Interrupt Flag
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆LVTTL-compatible, single 3.3V (±0.3V) power supply
◆◆
◆◆
◆Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
◆◆
◆◆
◆Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆◆
◆◆
◆Green parts available, see ordering information
NOTES:
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70V25/24.
5. I/O8x - I/O15x for IDT70V25/24.
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆◆
◆◆
◆High-speed access
IDT70V35/34
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25/24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
◆◆
◆◆
◆Low-power operation
– IDT70V35/34S – IDT70V35/34L
Active: 430mW (typ.) Active: 415mW (typ.)
Standby: 3.3mW (typ.) Standby: 660
µ
W (typ.)
– IDT70V25/24S – IDT70V25/24L
Active: 400mW (typ.) Active: 380mW (typ.)
Standby: 3.3mW (typ.) Standby: 660
µ
W (typ.)
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/WL
BUSYL
A12L
(1)
A0L
5624 drw 01
UBL
LBL
CEL
OEL
I/O9L-I/O17L
(5)
I/O0L-I/O8L
(4)
CEL
OEL
R/WL
SEML
INTLM/S
R/WR
BUSYR
UBR
LBR
CER
OER
I/O9R-I/O17R
(5)
I/O0R-I/O8R
(4)
A12R
(1)
A0R
R/WR
SEMR
INTR
CER
OER
(3)
(2,3) (2,3)
(3)
13 13
,
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K
x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de-
signed to be used as a stand-alone Dual-Port RAM or as a combination
MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 430mW (IDT70V35/34) and 400mW
(IDT70V25/24) of power.
The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin
Thin Quad Flatpack. The IDT70V25/24 is packaged in a ceramic 84-pin
PGA and 84-Pin PLCC.
Pin Configurations(1,2,3,4)
NOTES:
1. A12 is a NC for IDT70V34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 3637 38 39 40 41 42 43 44 45 46 47 48 49 50
100999897969594939291908988878685848382818079787776
IDT70V35/34PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
Vss
I/O
15L
I/O
16L
V
DD
Vss
I/O
0R
I/O
1R
I/O
2R
I/O
3R
V
DD
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
5624 drw 02
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
Vss
M/S
BUSY
R
INT
R
A
0R
N/C
N/C
N/C
N/C
BUSY
L
A
1R
A
2R
A
3R
A
4R
I/O
10L
I/O
9L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
Vss
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
I/O
7R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
Vss
I/O
16R
OE
R
R/W
R
SEM
R
CE
R
UB
R
LB
R
Vss
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
12L
(1)
A
12R
(1)
,
06/24/04
6.42
3
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3,4)(con't)
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V25/24PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
I/O
15L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
5624 drw 03
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
V
SS
M/S
BUSY
R
INT
R
A
0R
N/C
N/C
N/C
N/C
BUSY
L
A
1R
A
2R
A
3R
A
4R
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
V
SS
I/O
15R
OE
R
R/W
R
SEM
R
CE
R
UB
R
LB
R
V
SS
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
12L
(1)
A
12R
(1)
06/24/04
V
SS
V
SS
V
DD
V
DD
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
5624 drw 04
I/O
7L
63 61 60 58 55 54 51 48 46 45
66
67
69
72
75
76
79
81
82
83
125
7
8
11
10
12
14 17 20
23
26
28 29
32 31
33 35
38
41
43
IDT70V25/24
G
G84-3
(4)
84-Pin PGA
Top View
(5)
ABCDEFGHJ KL
42
59 56 49 50 40
25
27
30
36
34
37
39
84346915131618
22 24
19 21
68
71
70
77
80
UB
R
CE
R
V
SS
11
10
09
08
07
06
05
04
03
02
01
64
65
62
57 53 52
47 44
73
74
78
V
SS
V
SS
R/W
R
OE
R
LB
R
V
SS
V
SS
SEM
R
UB
L
CE
L
R/W
L
OE
L
V
SS
SEM
L
V
DD
LB
L
INT
R
BUSY
R
BUSY
L
M/S
INT
L
A
11L
Index
I/O
5L
I/O
4L
I/O
2L
I/O
0L
I/O
10L
I/O
8L
I/O
6L
I/O
3L
I/O
1L
I/O
11L
I/O
9L
I/O
13L
I/O
12L
I/O
15L
I/O
14L
I/O
0R
A
9L
A
10L
A
8L
A
7L
A
5L
A
6L
A
4L
A
3L
A
2L
A
0L
A
1L
A
0R
A
2R
A
1R
A
5R
A
3R
A
6R
A
4R
A
9R
A
7R
A
8R
A
10R
A
11R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
7R
I/O
6R
I/O
9R
I/O
8R
I/O
11R
I/O
10R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
V
DD
A
12R(1)
A
12L(1)
06/11/04
Pin Configurations(1,2,3,4)(con't)
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
5
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5624 drw 05
14
15
16
17
18
19
20
INDEX
21
22
23
24
11109876543218483
33 34 35 36 37 38 39 40 41 42 43 44 45
V
DD
V
SS
I/O
8L
A
7L
13
12
25
26
27
28
29
30
31
32 46 47 48 49 50 51 52 53
72
71
70
69
68
67
66
65
64
63
62
73
74
61
60
59
58
57
56
55
54
82 81 80 79 78 77 76 75
V
SS
BUSY
L
V
SS
IDT70V25/24J
J84-1
(4)
84-Pin PLCC
Top View
(5)
INT
L
M/S
INT
R
I/O
9L
I
/O
10L
I
/O
11L
I
/O
12L
I
/O
13L
I
/O
14L
I
/O
15L
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
BUSY
R
A
0R
A
2R
A
3R
A
4R
A
5R
A
6R
A
1R
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
11L
V
SS
I/O
1L
I/O
0L
A
10L
A
9L
A
8L
OE
L
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
V
SS
I/O
15R
V
SS
A
11R
A
10R
A
9R
A
8R
A
7R
OE
R
R/W
R
CE
R
UB
R
LB
R
A
12R(1)
A
12L(1
)
SEM
R
,
06/08/04
Pin Configurations(1,2,3,4)(con't)
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. I/O0x - I/O15x for IDT70V25/24.
3. Upper Byte Select controls pins 9-17 for IDT70V35/34 and controls pins 8-15
for IDT70V25/24.
4. Lower Byte Select controls pins 0-8 for IDT70V35/34 and controls pins 0-7
for IDT70V25/24.
NOTES:
Left Po rt Rig ht Po rt Names
CE
L
CE
R
Chip E nab le
R/W
L
R/W
R
Re ad /W rite E nab le
OE
L
OE
R
Outp ut Enable
A
0L
- A
12L
(1)
A
0R
- A
12R
(1)
Address
I/O
0L
- I/ O
17L
(2)
I/O
0R
- I/ O
17R
(2)
Da ta In p u t/ O u tp u t
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select
(3)
LB
L
LB
R
Lo we r By te S ele c t
(4)
INT
L
INT
R
Interrup t F lag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Se lec t
V
DD
Po we r (3.3V)
V
SS
Ground (0V)
5624 tb l 01
Pin Names
Truth Table II: Semaphore Read/Write Control(1)
NOTE:
1 . There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
Truth T able I: Non-Contention Read/Write Control
NOTES:
1. A0L-A12L ≠ A0R-A12R for IDT70V35/34 and A0L-A11L ≠ A0R-A11R for IDT70V25/24.
2. Outputs for IDT70V25/24 are I/O0x-I/O7x.
3. Outputs for IDT70V25/24 are I/O8x-I/O15x.
Inputs
(1)
Outputs
Mode
CE R/WOE UB LB SEM I/O
9-17
(3)
I/O
0-8
(2)
H X X X X H Hig h-Z Hig h-Z De se le cted : Power Down
X X X H H H Hig h-Z Hig h-Z B oth B ytes Des elected
LLXLHHDATA
IN
High-Z Write to Upper Byte Only
L L X H L H High-Z DATA
IN
Wr i te to L o wer B yte O nly
LLXLLHDATA
IN
DATA
IN
Wr i te to B oth B y te s
LHLLHHDATA
OUT
Hig h-Z Read Up pe r By te Onl y
LHLHLHHigh-ZDATA
OUT
Re ad Lo we r By te Onl y
LHLLLHDATA
OUT
DATA
OUT
Re ad Bo th Byte s
XXHXXXHigh-ZHigh-ZOutputs Disabled
5624 t bl 02
Inputs Outputs
Mode
CE R/WOE UB LB SEM I/O
9-17
(1)
I/O
0-8
(1)
HHLXXLDATA
OUT
DATA
OUT
Re ad Data in Se map hore Flag
XHLHHLDATA
OUT
DATA
OUT
Re ad Data in Se map hore Flag
H↑XXXLDATA
IN
DATA
IN
Wri te I/ O
0
into Semaphore Fl ag
X↑XHHLDATA
IN
DATA
IN
Wri te I/ O
0
into Semaphore Fl ag
LXXLXL
____ ____
No t Al lo we d
LXXXLL
____ ____
No t Al lo we d
5 624 tb l 03
6.42
7
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1) Maximum Operating Temperature
and Supply Voltage(1)
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Recommended DC Operating
Conditions
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
NOTE:
1. At VDD < 2.0V leakages are undefined.
Symbol Rating Commercial
& I ndu stri al Unit
V
TERM
(2)
Terminal Volt age
wi th Re s p e c t
to G ND
-0.5 to + 4.6 V
T
BIAS
Temperature
Under Bia s -55 to +125
o
C
T
STG
Storage
Temperature -65 to +150
o
C
T
JN
J unc tio n Tem p er ature + 150
o
C
I
OUT
DC O utpu t
Current 50 mA
5624 tb l 04
Grade Ambient
Temperature GND V
DD
Commercial 0
O
C to + 70
O
C0V3.3V
+
0.3V
Industrial -40
O
C to + 85
O
C0V 3.3V
+
0.3V
5624 tb l 0 5
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltag e 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Vo ltage 2.0
____
V
DD
+0.3
(2)
V
V
IL
Inp ut Lo w Vo ltag e -0. 3
(1)
____
0.8 V
5624 tb l 06
Symbol Parameter Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 0V 9 pF
C
OUT
(2)
Outp ut Cap acitanc e V
OUT
= 0V 10 pF
5624 tb l 07
S ymb ol P arameter Test Co ndi tio ns
70V35/34/25/24S 70V35/34/25/24L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Le akag e Curre nt
(1)
V
DD
= 3.6V, V
IN
= 0V to V
DD
___
10
___
5µA
|I
LO
| Outp ut Le ak ag e Curre ntt
(1)
CE = V
IH
, V
OUT
= 0V to V
DD
___
10
___
5µA
V
OL
Outp ut Lo w Voltag e I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output Hig h Vo ltage I
OH
= -4mA 2.4
___
2.4
___
V
5624 tb l 08
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range for 70V35/34(1) (VDD = 3.3V ± 0.3V)
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
70V35/34X15
Com'l Only 70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
S ymbol P ar ameter Test Condition Versi on Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
DD
Dy nami c O pe rating
Current
(Bo th P orts Ac tive)
CE = V
IL
, Outp uts Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L150
140 215
185 140
130 200
175 130
125 190
165 mA
IND S
L
____
____
____
____
140
130 225
195
____
____
____
____
I
SB1
Stand b y Current
(Bo th P orts - TTL
Le ve l Inp u ts)
CE
R
and CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L25
20 35
30 20
15 30
25 16
13 30
25 mA
MIL &
IND S
L
____
____
____
____
20
15 45
40
____
____
____
____
I
SB2
Stand b y Current
(One Po rt - TTL
Le ve l Inp u ts)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Ac tiv e Po rt Outputs Disable d ,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L85
80 120
110 80
75 110
100 75
72 110
95 mA
MIL &
IND S
L
____
____
____
____
80
75 130
115
____
____
____
____
I
SB3
Full Standb y Curre nt
(Bo th P orts -
CM OS Lev e l Inp u ts)
Bo th Po rts CE
L
and
CE
R
> V
DD
- 0. 2V,
V
IN
> V
DD
- 0. 2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0. 2V
COM'L S
L1.0
0.2 5
2.5 1.0
0.2 5
2.5 1.0
0.2 5
2.5 mA
MIL &
IND S
L
____
____
____
____
1.0
0.2 15
5
____
____
____
____
I
SB4
Full Standb y Curre nt
(One Po rt -
CM OS Lev e l Inp u ts)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0. 2V
(5)
SEM
R
= SEM
L
> V
DD
- 0. 2V
V
IN
> V
DD
- 0. 2V o r V
IN
< 0. 2V
Ac tiv e Po rt Outputs Disable d ,
f = f
MAX
(3)
COM'L S
L85
80 125
105 80
75 115
100 75
70 105
90 mA
MIL &
IND S
L
____
____
____
____
80
75 130
115
____
____
____
____
5624 t bl 09
AC Test Conditions
Figure 1. AC Output Test Load
Input Pulse Levels
Inp ut Ris e /Fall Time s
Inp ut Timi ng Refere nc e Lev els
Outp ut Re fe re nc e Le ve ls
Outp ut Load
GND to 3. 0V
3ns Max .
1.5V
1.5V
Fi gures 1 and 2
5624 tbl 10
Figure 2. Output Test
Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
5624 drw 06
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
,
Timing of Power-Up Power-Down
CE
5624 drw 07
t
PU
I
CC
I
SB
t
PD
50% 50%
,
6.42
9
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range for 70V25/24(1) (VDD = 3.3V ± 0.3V)
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
70V25/24X15
Com 'l Only 70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& I nd
Symb ol Param eter Test Conditi on Versi on Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
DD
Dy nam ic Ope rati ng
Current
(Bo th Po rts A ctiv e)
CE = V
IL
, Outp uts Op e n
SEM = V
IH
f = f
MAX
(3)
COM'L S
L150
140 215
185 140
130 200
175 130
125 190
165 mA
IND S
L
____
____
____
____
140
130 225
195
____
125
____
180
I
SB1
Standby Current
(Bo th Po rts - TTL
Le v e l Inp uts )
CE
R
and CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L25
20 35
30 20
15 30
25 16
13 30
25 mA
MIL &
IND S
L
____
____
____
____
20
15 45
40
____
13
____
40
I
SB2
Standby Current
(One P o rt - TTL
Le v e l Inp uts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Open,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L85
80 120
110 80
75 110
100 75
72 110
95 mA
MIL &
IND S
L
____
____
____
____
80
75 130
115
____
72
____
110
I
SB3
Full Standby Current
(Bo th Po rts -
CMOS Leve l Inputs)
Both Ports CE
L
and
CE
R
> V
DD
- 0. 2V,
V
IN
> V
DD
- 0. 2V o r
V
IN
< 0. 2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0. 2V
COM'L S
L1.0
0.2 5
2.5 1.0
0.2 5
2.5 1.0
0.2 5
2.5 mA
MIL &
IND S
L
____
____
____
____
1.0
0.2 15
5
____
0.2
____
5
I
SB4
Full Standby Current
(One P o rt -
CMOS Leve l Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
SEM
R
= SEM
L
> V
DD
- 0. 2V
V
IN
> V
DD
- 0. 2V o r V
IN
< 0.2V
Active Port Outputs Open,
f = f
MAX
(3)
COM'L S
L85
80 125
105 80
75 115
100 75
70 105
90 mA
MIL &
IND S
L
____
____
____
____
80
75 130
115
____
70
____
105
5624 t b l 09a
70V25/24X35
Com'l Only 70V25/24X55
Com'l Only
S ymbo l P aram eter Test Co ndi tio n Ve rsion Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
DD
Dy nami c O pe rating
Current
(Bo th P orts Ac tive)
CE = V
IL
, Outputs Open
SEM = V
IH
f = f
MAX
(3)
COM'L S
L120
115 180
155 120
115 180
155 mA
IND S
L
____
____
____
____
____
____
____
____
I
SB1
Stand b y Current
(Bo th P orts - TTL
Le ve l Inp u ts)
CE
R
and CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L13
11 25
20 13
11 25
20 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB2
Stand b y Current
(One Po rt - TTL
Le ve l Inp u ts)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Ac tiv e Po rt Outputs Ope n,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L70
65 100
90 70
65 100
90 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB3
Full Standb y Curre nt
(Bo th P orts -
CM OS Lev e l Inp u ts)
Bo th Po rts CE
L
and
CE
R
> V
DD
- 0. 2V,
V
IN
> V
DD
- 0. 2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0. 2V
COM'L S
L1.0
0.2 5
2.5 1.0
0.2 5
2.5 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB4
Full Standb y Curre nt
(One Po rt -
CM OS Lev e l Inp u ts)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
SEM
R
= SEM
L
> V
DD
- 0. 2V
V
IN
> V
DD
- 0. 2V o r V
IN
< 0. 2V
Ac tiv e Po rt Outputs Ope n,
f = f
MAX
(3)
COM'L S
L65
60 100
85 65
60 100
85 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
5624 tb l 09 b
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
t
RC
R/W
CE
ADDR
t
AA
OE
UB,LB
5624 drw 08
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
70V35/34X15
Com'l Only 70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cyc le Time 15
____
20
____
25
____
ns
t
AA
Address Acce ss Time
____
15
____
20
____
25 ns
t
ACE
Chip Enable Acce ss Time
(3)
____
15
____
20
____
25 ns
t
ABE
Byte Enable Access Time
(3)
____
15
____
20
____
25 ns
t
AOE
Output Enable Access Time
(3)
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
PU
Chip Enab le to Power Up Time
(1,2)
0
____
0
____
0
____
ns
t
PD
Chi p Disab le to Po wer Do wn Ti me
(1,2)
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
ns
t
SAA
Semaphore Address Access
(3)
____
15
____
20
____
25 ns
5 624 tb l 1
1
6.42
11
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
70V25/24X15
Com'l Only 70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& I nd
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCL E
t
RC
Re ad Cyc le Time 15
____
20
____
25
____
ns
t
AA
Address Acce ss Time
____
15
____
20
____
25 ns
t
ACE
Chip Enable Acce ss Time
(3)
____
15
____
20
____
25 ns
t
ABE
Byte Enable Access Time
(3)
____
15
____
20
____
25 ns
t
AOE
Outp ut Enable Acce ss Time
(3)
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
O u t pu t L ow - Z Ti me
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output Hi gh-Z Ti me
(1,2)
____
10
____
12
____
15 ns
t
PU
Chi p E nab l e to P o we r Up Tim e
(1,2)
0
____
0
____
0
____
ns
t
PD
Chip Dis ab le to Powe r Do wn Time
(1,2)
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
ns
t
SAA
Se map ho re Ad dre ss Acce ss
(3)
____
15
____
20
____
25 ns
5624 tbl 11a
70V25/24X35
Com'l Only 70V25/24X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max.
RE AD CYCL E
t
RC
Re ad Cyc l e Ti me 35
____
55
____
ns
t
AA
Add ress Access Time
____
35
____
55 ns
t
ACE
Chip Enable Acce ss Time
(3)
____
35
____
55 ns
t
ABE
Byte Enable Acce ss Time
(3)
____
35
____
55 ns
t
AOE
Output Enable Access Time
(3)
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Outp ut Lo w-Z Tim e
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25 ns
t
PU
Ch ip Enab le to P o wer Up Time
(1,2)
0
____
0
____
ns
t
PD
Chip Disab le to Po we r Do wn Time
(1,2)
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Ad dre ss Acce ss
(3)
____
35
____
55 ns
5624 tbl 11b
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V35/34 (5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
Symbol Parameter
70V35/34X15
Com'l Only 70V35/34X20
Com'l
& I nd
70V35/34X25
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI T E CYCL E
t
WC
Write Cycle Time 15
____
20
____
25
____
ns
t
EW
Chip Enab le to End-of-Write
(3)
12
____
15
____
20
____
ns
t
AW
Address Valid to End -of-Write 12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
ns
t
WR
Write Reco ve ry Time 0
____
0
____
0
____
ns
t
DW
Da ta Val id to E nd-o f-Write 10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
DH
Data Ho ld Ti me
(4)
0
____
0
____
0
____
ns
t
WZ
Wri te E nab l e to Outp ut in Hig h-Z
(1,2)
____
10
____
12
____
15 ns
t
OW
Ou tp ut A c tiv e fro m E nd -o f-Wri te
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Fl ag W rite to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM F lag Co nte ntio n Windo w 5
____
5
____
5
____
ns
5624 tbl 12
6.42
13
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V25/24 (5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
Symbol Parameter
70V25/24X15
Com'l Only 70V25/24X20
Com'l
& I nd
70V25/24X25
Com'l
& I nd
UnitMin. Max. Min. Max. Min. Max.
WRI T E CYCL E
t
WC
Write Cycle Time 15
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
ns
t
WR
Write Reco very Time 0
____
0
____
0
____
ns
t
DW
Data Valid to E nd -of-Write 10
____
15
____
15
____
ns
t
HZ
Outp ut High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write E nab le to Output in Hig h-Z
(1,2)
____
10
____
12
____
15 ns
t
OW
O utp ut Acti v e fro m End -o f-Wri te
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Fl ag Write to Re ad Ti me 5
____
5
____
5
____
ns
t
SPS
SEM Fl ag Co ntentio n Wi ndo w 5
____
5
____
5
____
ns
5624 tb l 12a
Symbol Parameter
70V25/24X35
Com'l Only 70V25/24X55
Com'l O nly
UnitMin. Max. Min. Max.
WR I TE C YC L E
t
WC
Write Cycle Time 35
____
55
____
ns
t
EW
Chip Enab le to End-of-Write
(3)
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
ns
t
DW
Da ta Vali d to End -o f-Write 15
____
30
____
ns
t
HZ
Outp ut Hig h-Z Time
(1,2)
____
15
____
25 ns
t
DH
Data Ho l d Time
(4)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
25 ns
t
OW
Ou tp ut A c tiv e fro m En d -o f-Wri te
(1,2,4)
0
____
0
____
ns
t
SWRD
SEM F lag Wri te to Re ad Time 5
____
5
____
ns
t
SPS
SEM Flag Co nte ntion Windo w 5
____
5
____
ns
5624 tbl 12b
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
Timing Wa vef orm of Write Cyc le No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = V IL. tEW must be met for either condition.
Timing Wa vef orm of Write Cyc le No. 2, CE, UB, LB Controlled Timing(1,5)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
CE or SEM
5624 drw 09
(9)
CE or SEM
(9)
(7)
(3)
5624 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB or LB
(3)
(2)(6)
CE or SEM
(9)
(9)
6.42
15
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24) equal to the semaphore value.
SEM
5624 drw 11
t
AW
t
EW
t
SOP
I/O
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
SEM
"A"
5624 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
,
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
5624 drw 13
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
t
BAA
t
DW
Timing Wa vef orm of Write Port-to-Port R ead and BUSY(2,4,5) (M/S = VIH)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(6)
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
70V35/34X15
Com ' l Ony 70V35/34X20
Com'l
& I nd
70V35/34X25
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMI NG (M/S = V
IH
)
t
BAA
BUSY Access Time fro m Addre ss Match
____
15
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable LOW
____
15
____
20
____
20 ns
t
BDC
BUSY Di sab le Time fro m Ch ip E nab l e HIGH
____
15
____
17
____
17 ns
t
APS
Arbitration Prio rity Set-up Ti me
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Di s ab l e to Valid Data
(3)
____
18
____
30
____
30 ns
t
WH
Wri te Ho l d Aft e r BUSY
(5)
12
____
15
____
17
____
ns
BUSY TIMI NG (M/S = V
IL
)
t
WB
BUSY In p ut to Write
(4)
0
____
0
____
0
____
ns
t
WH
Wri te Ho l d Aft e r BUSY
(5)
12
____
15
____
17
____
ns
PORT -TO-PORT DELAY TIMI NG
t
WDD
Wri te Pul s e to Dat a De l ay
(1)
____
30
____
45
____
50 ns
t
DDD
Wri te Dat a Val id to Re a d Data De l ay
(1)
____
25
____
35
____
35 ns
5624 tbl 13
6.42
17
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(6)
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
70V25/24X15
Com ' l Ony 70V25/24X20
Com'l
& I nd
70V25/24X25
Com'l
& I nd
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TI MING (M/ S = V
IH
)
t
BAA
BUSY Access Time from Addre ss Match
____
15
____
20
____
20 ns
t
BDA
BUSY Disable Time from Addre ss Not Matched
____
15
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable LOW
____
15
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable HIGH
____
15
____
17
____
17 ns
t
APS
A rb i tratio n P ri o ri ty Set-up Ti me
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
17
____
ns
BUSY TI MING (M/ S = V
IL
)
t
WB
BUSY Input to W rite
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
17
____
ns
P ORT-TO -PORT DE LAY TIMING
t
WDD
Write P ulse to Data Delay
(1)
____
30
____
45
____
50 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____
25
____
35
____
35 ns
5624 tb l 13a
70V25/24X35
Co m ' l O n l y 70V25/24X55
Com'l Only
Symbol Parameter Min. Max. Min. Max. Unit
BUSY TI MING (M/ S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
40 ns
t
BAC
BUSY Access Time from Chip Enable LOW
____
20
____
40 ns
t
BDC
BUSY Dis ab l e Tim e fro m Chip En ab l e HIG H
____
20
____
35 ns
t
APS
A rb i tra tio n Prio rity S e t-u p Tim e
(2)
5
____
5
____
ns
t
BDD
BUSY Dis ab l e to Vali d Data
(3)
____
35
____
40 ns
t
WH
Write Hold After BUSY
(5)
25
____
25
____
ns
BUSY TI MING (M/ S = V
IL
)
t
WB
BUSY Input to W rite
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write P ulse to Data De lay
(1)
____
60
____
80 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____
45
____
65 ns
5624 tb l 13b
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
Timing Waveform of Write with BUSY
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
5624 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(2)
(3)
(1)
,
NOTES:
1. tWH must be met for both master BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version.
5624 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
5624 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
6.42
19
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(1)
NOTES:
1. 'X' in part number indicates power rating (S or L).
70V35/34X15
Co m'l Onl y 70V35/34X20
Com'l
& In d
70V35/34X25
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TI MING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
0
____
ns
t
INS
In te rru p t Set Ti me
____
15
____
20
____
20 ns
t
INR
Inte rrup t Re s e t Time
____
15
____
20
____
20 ns
5624 t bl 1 4
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(1)
70V25/24X15
Co m' l O nl y 70V25/24X20
Com'l
& I nd
70V25/24X25
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TI MING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
0
____
ns
t
INS
In terr u pt Set Tim e
____
15
____
20
____
20 ns
t
INR
In terr u pt R es et Tim e
____
15
____
20
____
20 ns
5624 tbl 14a
70V25/24X35
Com'l Only 70V25/24X55
Com'l Only
Symbol Parameter Min.Max.Min.Max.Unit
INTERRUPT TI MING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
ns
t
INS
In terr u pt Set Tim e
____
25
____
40 ns
t
INR
In terr u pt R es et Tim e
____
25
____
40 ns
5624 tb l 14b
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
20
Wa v eform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5624 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
5624 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
6.42
21
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
T ruth T able III — Interrupt Flag(1)
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE.
Left P ort Ri ght P ort
FunctionR/W
L
CE
L
OE
L
A
12L
-A
0L
(4)
INT
L
R/W
R
CE
R
OE
R
A
12R
-A
0R
(4)
INT
R
LLX1FFF
(4)
XXXX X L
(2)
S e t Ri g h t INT
R
Fl ag
XXX X XXLL1FFF
(4)
H
(3)
Re s et R ight INT
R
Flag
XXX X L
(3)
LLX1FFE
(4)
XSet Left INT
L
Flag
XLL1FFE
(4)
H
(2)
X X X X X Reset Left INT
L
Flag
5624 tbl 15
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A0 - A11.
Inputs Outputs
Function
CE
L
CE
R
A
12L
-A
0L
(4)
A
12R
-A
0R
BUSY
L
(1)
BUSY
R
(1)
XXNO MATCHHHNormal
H X MATCH H H Normal
X H MATCH H H Normal
LL MATCH Note
(2)
Note
(2)
Write Inhibit
(3)
56 24 t bl 16
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24).
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
Functions D
0
- D
17
Left
(2)
D
0
- D
17
Ri ght
(2)
Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left P ort Wri te s "0" to Semapho re 1 0 No chang e. Le ft p ort has no wri te ac ce ss to semapho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
56 24 tb l 17
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
22
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs.
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V35/34 (IDT70V25/24) SRAM in
master mode, are push-pull type outputs and do not require pull up
resistors to operate. If these SRAMs are being expanded in depth, then
the BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V35/34 (IDT70V25/24) SRAM array in
width while using BUSY logic, one master part is used to decide which side
of the SRAM array will receive a BUSY indication, and to output that
indication. Any number of slaves to be addressed in the same address
range as the master, use the BUSY signal as a write inhibit signal. Thus
on the IDT70V35/34 (IDT70V25/24) SRAM the BUSY pin is an output if
the part is used as a master (M/S pin = VIH), and the BUSY pin is an input
if the part used as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT70V35/34 (IDT70V25/24) is an extremely fast Dual-Port 8/
4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address
locations dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port SRAM to claim a privilege
over the other processor for functions defined by the system designer’s
Functional Description
The IDT70V35/34 (IDT70V25/24) provides two ports with separate
control, address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT70V35/34 (IDT70V25/24) has
an automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE HIGH). When a port is enabled,
access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX) (FFE for IDT70V34 and IDT70V24), where a write is defined as
the CER = R/WR = VIL per Truth Table III. The left port clears the interrupt
on the IDT70V35 and IDT70V25 by an address location 1FFE (FFE for
IDT70V34 and IDT70V24) access when CEL = OEL = VIL, R/WL is a "don't
care". Likewise, the right port interrupt flag (INTR) is set when the left port
writes to memory location 1FFF for IDT70V35 and IDT70V25 (HEX) (FFF
for IDT70V34 and IDT70V24) and to clear the interrupt flag (INTR), the
right port must read the memory location 1FFF for IDT70V35 and
IDT70V25 (FFF for IDT70V34 and IDT70V24). The message (16 bits)
at 1FFE or 1FFF for IDT70V35 and IDT70V25 (FFE or FFF for
IDT70V34 and IDT70V24) is user-defined, since it is an addressable
SRAM location. If the interrupt function is not used, address locations 1FFE
and 1FFF for IDT70V35 and IDT70V25 (FFE and FFF for IDT70V34 and
IDT70V24) are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the SRAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the SRAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
5624 drw 19
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
DECODER
,
6.42
23
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
software. As an example, the semaphore can be used by one processor
to inhibit the other from accessing a portion of the Dual-Port SRAM or any
other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be accessed
at the same time with the only possible conflict arising from the simultaneous
writing of, or a simultaneous READ/WRITE of, a non-semaphore location.
Semaphores are protected against such ambiguous situations and may
be used by the system program to avoid any conflicts in the non-
semaphore portion of the Dual-Port SRAM. These devices have an
automatic power-down feature controlled by CE, the Dual-Port SRAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT70V35/34 (IDT70V25/24) contain
multiple processors or controllers and are typically very high-speed
systems which are software controlled or software intensive. These
systems can benefit from a performance increase offered by the IDT70V35/
34 (IDT70V25/24)'s hardware semaphores, which provide a lockout
mechanism without requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V35/34 (IDT70V25/24) does not use its sema-
phore flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70V35/34 (IDT70V25/
24) in a separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts as
a chip select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing a standard
static RAM. Each of the flags has a unique address which can be accessed
by either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
6.42
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
24
semaphore request latch. The critical case of semaphore timing is when
both sides request a single token by attempting to write a zero into it at the
same time. The semaphore logic is specially designed to resolve this
problem. If simultaneous requests are made, the logic guarantees that only
one side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be arbitrarily made
to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70V35/34 (IDT70V25/24)’s Dual-Port
SRAM. Say the 8K x 18 SRAM was to be divided into two 4K x 18 blocks
which were to be dedicated at any one time to servicing either the left or
right port. Semaphore 0 could be used to indicate the side which would
control the lower section of memory, and Semaphore 1 could be defined
as the indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port SRAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 4K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 4K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port SRAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
D
5624 drw 20
0DQ
WRITE D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
L
P
O
R
T
RPORT
SEMAPHORE
READ SEMAPHORE
READ
,
Figure 4. IDT70V35/34 (IDT70V25/24) Semaphore Logic
6.42
25
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
Ordering Information
5624 drw 21a
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
100-pin TQFP (PN100-1) 70V35/34/25/24
84-Pin PGA (G84-3) 70V25/24
84-Pin PLCC (J84-1) 70V25/24
Standard Power
Low Power
144K (8K x 18-Bit) 3.3V Dual-Port RAM
72K (4K x 18-Bit) 3.3V Dual-Port RAM
128K (8K x 16-Bit) 3.3V Dual-Port RAM
64K (4K x 16-Bit) 3.3V Dual-Port RAM
Speed in Nanosecond
s
Commercial Only - 70V35/34/25/24
Commercial & Industrial - 70V35/34/25/24
Commercial Only - 70V35/34
Commercial & Industrial - 70V25/24
Commercial Only - 70V25/24
Commercial Only - 70V25/24
,
Blank
I
(1)
PF
G
J
S
L
70V35
70V34
70V25
70V24
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
XXXXX
Device
Type
15
20
25
25
35
55
A
Step
Blank
TNo stepping designation
Current Stepping
A
G
(2)
Green
Datasheet Document History
06/08/00: Initial Public Offering
08/09/01: Page 1 Corrected I/O numbering
Page 5-7, 10 & 12 Removed Industrial temperature range offering for 25ns from DC & AC Electrical Characteristics
Page 17 Removed Industrial temperature range offering for 25ns speed from the ordering information
Added Industrial temperature offering footnote
07/02/02: Page 2 Added date revision for pin configuration
Added 70V34 to datasheet (4K x 18)
06/22/04: Consolidated 70V25/24 datasheets (8/4K x 16) into 70V35/34 (8/4K x 18) datasheet
Removed Preliminary status from datasheet
Page 2 & 3 Changed naming convention from VCC to VDD and from GND to VSS for PN100 packages
Page 7 Updated Conditions in Capacitance table
Page 7 Added Junction Temperature to Absolute Maximum Ratings table
Page 9, 11, 13, 17 &, 19 Added DC and AC Electrical Characteristics tables for 70V25/24 data
Page 21 & 22 Changed Interrupt flag table, footnotes and Interrupts text to reflect 70V25/24 data
Page 1 & 15 Replaced old ® logo with new TM logo
10/28/04: Page 25 Added stepping indicator to ordering information
04/05/05: Page 1 Added green availability to features
Page 25 Added green indicator to ordering information
10/23/08: Page 25 Removed "IDT" from orderable part number
NOTES:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
