ATL50/60-BGA49 - Atmel Corporation

Features

•0.5 µm Drawn Gate Length (0.45µm Leff) Sea-of-Gates Architecture With

Triple Level Metal

•3.3V Operation

•5.0V Compatible Input Buffers

•On-chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to 150 MHz

and Manage Chip-to-Chip Clock Skew

•Compiled (gate level) and Embedded (custom) SRAMs, ROM and CAMs Available

•3.3V PCI, SCSI and High Speed (250 MHz) Buffers Available

•Easy Alternative Sourcing of Existing ASIC, FPGA and PLD Designs

•Design-for-Test methods — Including JTAG, Serial and Boundary Scan and ATPG

Description

Atmel’s next generation ATL50 Series CMOS Gate Arrays are fabricated using a

0.5µm drawn gate, oxide isolated, triple level metal process. Extensive cell libraries

are available and support the major CAD software tools. As with all Atmel gate array

families, customer involvement and satisfaction is integral to all steps of the design

flow. A variety of Design for Testability techniques are supported by the libraries, and

a wide range of packaging options are available.

Note: 1. Nominal 2 Input NAND Gate at 3.3 volts

ATL50 Array Organization

Device

Number

Raw

Gates

Routable

Gates

Max Pin

Count

Max I/O

Pins

Gate(1)

Speed

ATL50/4 4,000 3,000 44 36 200 ps

ATL50/15 15,000 10,000 68 60 200 ps

ATL50/25 25,000 16,900 84 76 200 ps

ATL50/40 38,000 25,400 100 92 200 ps

ATL50/60 58,000 34,600 120 112 200 ps

ATL50/85 86,000 51,900 144 136 200 ps

ATL50/110 110,000 65,900 160 152 200 ps

ATL50/150 149,000 89,300 184 176 200 ps

ATL50/200 195,000 116,900 208 200 200 ps

ATL50/235 232,000 139,500 226 218 200 ps

ATL50/300 301,000 181,000 256 248 200 ps

ATL50/435 430,000 260,000 304 296 200 ps

ATL50/550 545,000 288,000 340 332 200 ps

ATL50/700 693,000 363,000 380 372 200 ps

ATL50/870 870,000 456,000 424 416 200 ps

ATL50/1100 1,119,000 590,000 480 472 200 ps

Gate Arrays/

Embedded

Arrays

ATL50 Series

Preliminary

Rev. 0753B–11/99

ATL50

Design

Design Systems Supported

Atmel supports several major software systems for design

with complete macro cell libraries, as well as utilities for

checking the netlist and accurate pre-route delay

simulations.

Design Flow

Atmel provides three methods for implementing a gate

array design, while maintaining the same basic design flow

for each of them. This flow involves both the Customer and

Atmel at all critical review and acceptance steps, as can be

seen from the chart on the following page. Database

Acceptance occurs when Atmel receives and accepts the

complete design database.

Atmel performs physical place-and-route. Functional and

timing simulations are performed, based on the physical

design, including the generation of a back annotation report

to provide the customer with the most accurate timing

information available. Final Design Review (FDR) is the

last step of the design flow prior to generation of masks.

After FDR, masks are generated, wafers fabricated, and

prototype parts are delivered.

The following design systems are supported:

System Version Tools

Cadence®

4.4.3

2.1.p2

4.1-s051

2.5

3.4B

2.3

Opus™ - Schematic and Layout

NC Verilog™ - Verilog Simulator

Pearl™ - Static Path

Ver ilog-XL™ - Verilog Simulator

Logic Design Planner™ - Floorplanner

BuildGates™ - Synthesis (Ambit)

Mentor/Model Tech™5.2e

B2 and Later

Modelsim Verilog and VHDL (VITAL) Simulator

QuickVHDL™

Synopsys™

98.08, 98.05

5.0.1A

VSS™ - VHDL Simulator

Design Compiler™ - Synthesis

Tes t C o m p i l e r ™ - Scan Insertion and ATPG

Primetime™ - Static Path

VCS™ - Verilog Simulator

Exemplar™1998.2f Leonardo Spectrum™ - Synthesis

Syntest

V2.2

V1.6

TurboCheck - Gate

TurboScan

TurboFault

ATL50

ATL50 Gate Array Design Flow

Notes: 1. Performed by the customer or optionally by Atmel

2. ISO 9001 Milestone

Synthesis, Translation or Conversion

Customer(1) Atmel(1)

Kickoff Meeting(2)

Customer Atmel

Database Submission

Customer(1) Atmel(1)

Database Acceptance(2)

Customer Atmel

Physical Design and Verification Atmel

Final Design Review(2)

Customer Atmel

Prototype Delivery(2)

Customer

ATL50

Pin Definition Requirements

Within the Physical Design Step (i.e., layout) certain

restrictions apply during pin definition. The corner pins on

each die are reserved and programmable for Power and

Ground only. All other buffer pins are fully programmable

as Input, Output, Bidirectional, Clock-into-Array, Power or

Ground.

Design Options

Logic Synthesis

Atmel can accept Register Transfer Level (RTL) designs

for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL™

format. Atmel fully supports Synopsys for VHDL™

simulation as well as synthesis. VHDL or Verilog-HDL is

Atmel’s preferred method of performing a gate array

design.

ASIC Design Translation

Atmel has successfully translated dozens of existing

designs from most major ASIC vendors (LSI Logic®,

Motorola®, SMOS™, Oki®, NEC®, Fujitsu®, AMI® and

others) into our gate arrays. These designs have been

optimized for speed and gate count and modified to add

logic or memory, or replicated for a pin-for-pin compatible,

drop-in replacement.

FPGA and PLD Conversions

Atmel has successfully translated existing FPGA/PLD

designs from most major vendors (Xilinx®, Actel®, Altera®,

AMD® and Atmel) into Atmel ASICs. There are four

primary reasons to convert from an FPGA/PLD to an

ASIC. Conversion of high volume devices for a single or

combined design is cost effective. Performance can often

be optimized for speed or low power consumption. Several

FPGA/PLDs can be combined onto a single chip to

minimize cost while reducing on-board space

requirements. Finally, in situations where an FPGA/PLD

was used for fast cycle time prototyping, an ASIC may

provide a lower cost answer for long-term volume

production.

ATL50 Embedded Array

ATL50

ATL50 Series Cell Library

Atmel’s ATL50 Series gate arrays make use of an

extensive library of cell structures, including logic cells,

buffers and inverters, multiplexers, decoders and I/O

options. Soft macros are also available.

The ATL50 Series PLL operates at frequencies of up to

150 MHz with minimal phase error and jitter, making it ideal

for frequency synthesis of high speed on-chip clocks and

chip-to-chip synchronization. Output buffers are

programmable to meet the voltage and current

requirements of both PCI and SCSI.

These cells are well characterized by use of SPICE

modeling at the transistor level, with performance verified

on manufactured test arrays. Characterization is performed

over the military temperature and voltage ranges to ensure

that the simulation accurately predicts the performance of

the finished product.

Cell Index

Signal Name Description Site Count(1)

ADD3X 1-bit Full Adder with Buffered Outputs 10

AND2 2-input AND 2

AND2H 2-input AND - High-drive 3

AND3 3-input AND 3

AND3H 3-input AND - High-drive 4

AND4 4-input AND 3

AND4H 4-input AND - High-drive 4

AND5 5-input AND 5

AOI22 2-input AND into 2-input NOR 2

AOI22H 2-input AND into 2-input NOR - High-drive 4

AOI222 Two, 2-input ANDs into 2-input NOR 4

AOI222H Two, 2-input ANDs into 2-input NOR - High-drive 8

AOI2223 Three, 2-input ANDs into 3-input NOR 4

AOI2223H Three, 2-input ANDs into 3-input NOR - High-drive 7

AOI23 2-input AND into 3-input NOR 2

BUF1 1x Buffer 2

BUF2 2x Buffer 2

BUF2T 2x Tri-state Bus Driver with Active-high Enable 4

BUF2Z 2x Tri-state Bus Driver with Active-low Enable 4

BUF3 3x Buffer 3

BUF4 4x Buffer 3

BUF4T 4x Tri-state Bus Driver with Active-high Enable 5

BUF8 8x Buffer 5

BUF12 12x Buffer 8

BUF16 16x Buffer 10

CLA7X 7-input Carry Lookahead 5

DEC4 2:4 Decoder 7

DEC4N 2:4 Decoder with Active-low Enable 9

DEC8N 3:8 Decoder with Active-low Enable 24

ATL50

DFF D Flip-flop 8

DFFBCPX D Flip-flop with Asynchronous Clear and Preset

with Complementary Outputs 16

DFFBSRX D Flip-flop with Asynchronous Set and Reset

with Complementary Outputs 16

DFFC D Flip-flop with Asynchronous Clear 9

DFFR D Flip-flop with Asynchronous Reset 11

DFFS D Flip-flop with Asynchronous Set 9

DFFSR D Flip-flop with Asynchronous Set and Reset 12

DLY1500 Delay Buffer 1.5 ns 6

DLY2000 Delay Buffer 2.1 ns 10

DLY3000 Delay Buffer 3.0 ns 10

DLY6000 Delay Buffer 6.0 ns 24

DSS Set Scan Flip-flop 11

DSSBCPY Set Scan Flip-flop with Clear and Preset 16

DSSBR Set Scan Flip-flop with Reset 13

DSSBS Set Scan Flip-flop with Set 13

DSSR Set Scan D Flip-flop with Reset 13

DSSS Set Scan D Flip-flop with Set 12

DSSSR Set Scan D Flip-flop with Set and Reset 14

HLD1 Bus Hold Cell 4

INV1 1x Inverter 1

INV1D Dual 1x Inverters 2

INV1Q Quad 1x Inverters 4

INV1TQ Quad Tri-state Inverter 7

INV2 2x Inverter 2

INV2T 2x Tri-state Inverter with Active-high Enable 3

INV3 3x Inverter 2

INV4 4x Inverter 2

INV8 8x Inverter 4

INV10 10x Inverter 8

JKF JK Flip-flop 10

JKFBCPX Clear Preset JK Flip-flop with Asynchronous

Clear and Preset and Complementary Outputs 16

JKFC JK Flip-flop with Asynchronous Clear 12

LAT LATCH 4

LATBG LATCH with Complementary Outputs and Inverted Gate Signal 6

Cell Index (Continued)

Signal Name Description Site Count(1)

ATL50

LATBH LATCH with High-drive Complementary Outputs 7

LATR LATCH with Reset 4

LATS LATCH with Set 6

LATSR LATCH with Set and Reset 8

MUX2 2:1 MUX 4

MUX2H 2:1 MUX - High-drive 5

MUX2I 2:1 MUX with Inverted Output 3

MUX2IH 2:1 MUX with Inverted Output - High-drive 4

MUX2N 2:1 MUX with Active-low Enable 4

MUX2NQ Quad 2:1 MUX with Active-low Enable 18

MUX2Q Quad 2:1 MUX 14

MUX3I 3:1 MUX with Inverted Output 6

MUX3IH 3:1 MUX with Inverted Output - High-drive 8

MUX4 4:1 MUX 9

MUX4X 4:1 MUX with Transmission Gate Data Inputs 10

MUX4XH 4:1 MUX with Transmission Gate Data Inputs - High-drive 10

MUX5H 5:1 MUX - High-drive 14

MUX8 8:1 MUX 18

MUX8N 8:1 MUX with Active-low Enable 20

MUX8XH 8:1 MUX with Transmission Gate Data Inputs - High-drive 18

NAN2 2-input NAND 2

NAN2D Dual 2-input NAND 3

NAN2H 2-input NAND - High-drive 2

NAN3 3-input NAND 2

NAN3H 3-input NAND - High-drive 3

NAN4 4-input NAND 3

NAN4H 4-input NAND - High-drive 4

NAN5 5-input NAND 5

NAN5H 5-input NAND - High-drive 6

NAND5S 5-input NAND - Single Stage 3

NAN6 6-input NAND 6

NAN6H 6-input NAND - High-drive 7

NAN8 8-input NAND 7

NAN8H 8-input NAND - High-drive 7

NOR2 2-input NOR 2

NOR2D Dual 2-input NOR 3

Cell Index (Continued)

Signal Name Description Site Count(1)

ATL50

Note: 1. A single ATL50 routing site contains 4 transistors, two N-channel and two P-channel, aligned in columns. The number of

sites used per gate varies according to the specific isolation and power requirements. Percent utilization varies from 50% to

70%, with more accurate utilization figures generated by DoubleCheck™, Atmel’s proprietary netlist checker.

NOR2H 2-input NOR - High-drive 2

NOR3 3-input NOR 2

NOR3H 3-input NOR - High-drive 3

NOR4 4-input NOR 3

NOR4H 4-input NOR - High-drive 4

NOR5 5-input NOR 5

NOR5S 5-input NOR - Single Stage 3

NOR8 8-input NOR 7

OAI22 2-input OR into 2-input NAND 2

OIA22H 2-input OR into 3-input NAND - High-drive 4

OAI222 Two, 2-input ORs into 2-input NAND 2

OAI222H Two, 2-input ORs into 2-input NAND - High-drive 4

OAI22224 Four, 2-input ORs into 4-input NAND 6

OAI23 2-input OR into 3-input NAND 3

ORR2 2-input OR 2

ORR2H 2-input OR - High-drive 3

ORR3 3-input OR 3

ORR3H 3-input OR - High-drive 4

ORR4 4-input OR 3

ORR4H 4-input OR - High-drive 4

ORR5 5-input OR 5

XNR2 2-input Exclusive NOR 4

XNR2H 2-input Exclusive NOR - High-drive 4

XOR2 2-input Exclusive OR 4

XOR2H 2-input Exclusive OR - High-drive 4

Cell Index (Continued)

Signal Name Description Site Count(1)

ATL50

I/O Buffer Cell Index

Signal Name Description

PBD2C 4 mA Bidi CMOS Buffer

PBC3C 6 mA Bidi CMOS Buffer

PBD5C 10 mA Bidi TTL Buffer with Schmitt Trigger

PBS1C 2 mA Bidi CMOS Buffer

PBS1CS 2 mA Bidi CMOS Buffer with Schmitt Trigger

PBS2C 4 mA Bidi CMOS Input Buffer

PBS2CS 4 mA Bidi CMOS Input Buffer with Schmitt Trigger

PBS3C 6 mA Bidi CMOS Buffer

PBS3CS 6 mA with Schmitt Trigger

PBS4C 8 mA Bidi CMOS Buffer

PBS4CS 8 mA Bidi CMOS Buffer with Schmitt Trigger

PBS5C 10 mA Bidi CMOS Buffer

PBS5CS 10 mA Bidi with Schmitt Trigger

PBS6C 12 mA Bidi CMOS Buffer

PBS6CS 12 mA Bidi Schmitt Trigger

PIC CMOS Input Buffer

PICI CMOS Inverting Input Buffer

PICS CMOS Input Buffer with Schmitt Trigger

PK6 12 mA Clock Driver

PO1 2 mA Output Buffer

PO2 4 mA Output Buffer

PO2B 4 mA Inverting Output Buffer

PO3 6 mA Output Buffer

PO4 8 mA Output Buffer

PO5 10 mA Output Buffer

PTD2 4 mA Tri-state Output Buffer

PTD3 6 mA Tri-state Output Buffer

PTD5 10 mA Tri-state Output Buffer

PTS1 2 mA Tri-state Output Buffer

PTS2 4 mA Tri-state Output Buffer

PTS3 6 mA Tri-state Output Buffer

PTS4 8 mA Tri-state Output Buffer

PTS5 10 mA Tri-state Output Buffer

PTS6 12 mA Tri-state Output Buffer

PX2CL 4 mA Crystal Oscillator Buffer (left side normalized input)

PX2CR 4 mA Crystal Oscillator Buffer (right side normalized input)

PX4CL 8 mA Crystal Oscillator Buffer (left side normalized input

PX4CR 8 mA Crystal Oscillator Buffer (right side normalized input)

ATL50

Absolute Maximum Ratings*

Operating Ambient

Temperature................................................-55°C to +125°C

Storage Temperature ..................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground ..............................-2.0 V to +5.0V 1

Maximum Operating Voltage .........................................3.7V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only

and functional operation of the device at these or

any other conditions beyond those indicated in

the operational sections of this specification is

not implied. Exposure to absolute maximum

rating conditions for extended periods may affect

device reliability.

Note: 1. Minimum voltage is -0.6V dc which may under-

shoot to -2.0 V for pulses of less than 20 ns.

Maximum output pin voltage is VDD + 0.75V dc

which may overshoot to +5.0V for pulses of less

than 20 ns.

3.3 Volt DC Characteristics

Applicable over recommended operating range unless otherwise noted.

Symbol Parameter Buffer Test Condition Min Typ Max Units

Operating Temperature All -55 125 °C

VDD Supply Voltage All 3.0 3.3 3.6 V

IIH High-level Input Current TTL, CMOS VIN = VDD, VDD = VDD(max) 5 µA

PCI 5

IIL Low-level Input Current

TTL, CMOS VIN = VSS, VDD = VDD(max)), No pull up -5

µATTL, CMOS VIN = VSS, VDD = VDD(max), U2 pull up

(33k Ω)-25 -100

PCI -5

IOZ

High-impedance State

Output Current All VIN = VDD or VSS, VDD = VDD(max),

No pull up -5 5 µA

IOS

Output Short-circuit

Current

4 mA Buffer VOUT = VDD, VDD = VDD(max) 17 mA

4 mA Buffer VOUT = VSS, VDD = VDD(max) -40 mA

VIH High-level Input Voltage

TTL, CMOS 2.0

VPCI 0.475VDD

CMOS Schmitt 2.0 1.7

VIL Low-level Input Voltage

TTL, CMOS 0.8

VPCI 0.325VDD

CMOS Schmitt 1.1 0.8

VHYS Hysteresis TTL, CMOS 0.6 V

VOH

High-level Output

Voltage

TTL, CMOS IOH = as rated, VDD = VDD(min) 0.7VDD

PCI IOH = -500 µA 0.9VDD

VOL

Low-level Output

Voltage

TTL, CMOS IOL = as rated, VDD = VDD(min) 0.4

PCI IOL = 1.5 mA 0.1VDD

ATL50

I/O Buffers

•Programmable output drive(1 to 12 mA IOL, -1 to -12 mA

IOH at 3.3V)

•2,000 to 5,000 volts ESD protection

•Programmable slew rate control

•Built-in configurable test logic

Design for Testability

Atmel supports a wide range of Design for Testability

techniques to improve the percentage of a design that can

be fully tested. By achieving a high degree of testability, a

designer can reduce design and prototype debug time,

minimize production test time, and improve board and

system level test and diagnostic capability.

Synopsys Test Compiler software is fully supported by

Atmel. By use of this system during design, the computer

will create and add a set of scan chains to the design, and

test vectors will be generated to provide greater than 95%

fault coverage. This method requires only 1 or 2 added pins

for Test Enable and Test Mode. This is the easiest and

least expensive method of designing testability into a gate

array design.

Ad Hoc means of increasing testability of a gate array are

also available. Partitioning, memory array isolation, and

test point insertion are encouraged and supported by the

ATL50 Series gate arrays. Atmel also encourages the

inclusion of Built In Self-Test (BIST) techniques whenever

possible. Each of these methods is discussed in detail in

the Atmel CMOS Gate Array Design Manual.

In addition to all of the above, the ATL50 Series gate arrays

also support the Joint Test Action Group (JTAG) boundary

scan architecture and Test Access Port (TAP) require-

ments. The required soft and hard macros to implement

IEEE 1149.1 compliant architecture are available in Atmel's

cell library. Use of JTAG architecture requires an additional

4-5 pins for test mode, data, and clock signals.

I/O Buffer DC Characteristics

Symbol Parameter Test Condition Typ Units

CIN Capacitance, Input Buffer (die) 3.3V 2.4 pF

COUT Capacitance, Output Buffer (die) 3.3V 5.6 pF

CI/O Capacitance, Bidirectional 3.3V 6.6 pF

ATL50

Advanced Packaging

The ATL50 Series gate arrays are offered in a wide variety

of standard packages, including plastic and ceramic quad

flatpacks, thin quad flatpacks, ceramic pin grid arrays, and

ball grid arrays. High volume on-shore and off-shore

contractors provide assembly and test for commercial

product, with prototype capability in Colorado Springs.

Custom package designs are also available as required to

meet a customer’s specific needs, and are supported

through Atmel’s package design center. When a standard

package cannot meet a customer's need, a package can

be designed to precisely fit the application and to maintain

the performance obtained in silicon. Atmel has delivered

custom-designed packages in a wide variety of

configurations.

Note: 1. Partial list

Packaging Options

Package Type Pin Count

PQFP 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304

Power Quad 144, 160, 208, 240, 304

L/TQFP 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216

PLCC 20, 28, 32, 44, 52, 68, 84

CPGA 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391

CQFP 64, 68, 84, 100, 120, 132, 144, 160, 224, 340

PBGA 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456

Super BGA 168, 204, 240, 256, 304, 352, 432, 560, 600

Low-profile Mini BGA 132, 144, 160, 180, 208

Chip-scale BGA(1) 40, 49, 56, 64, 81, 84, 96, 100, 128

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

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0753B–11/99/xM

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