AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
71M6541D/F/G and 71M6542F/G
Energy Meter ICs
DATA SHEET
GENERAL DESCRIPTION
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are
Teridian™ 4th-generation single-phase metering SoCs with a 5MHz
8051-compatible MPU core, low-power RTC with digital temperature
compensation, flash memory, and LCD driver. Our Single Converter
Technology® with a 22-bit delta-sigma ADC, three or four analog
inputs, digital temperature compensation, precision voltage reference,
and a 32-bit computation engine (CE) supports a wide range of
metering applications with very few external componen ts.
The 71M6541/2 devices support optional interfaces to the Teridian
71M6x01 series of isola t ed sensors, which offer BOM cost redu ction,
immunity to magnetic tamper, and enhanced reliability. Other
features include an SPI interface, advanced power management,
ultra-low-power operat io n in act ive and batte ry modes, 3/5 KB share d
RAM and 32/64/128KB of flash memory that can be programmed in
the field wit h code and/or data during meter operation and the ability
to drive up to six LCD segments per SEG driver pin. High
processing and sampling rates combined with d ifferential inputs offer
a powerful metering platform for residential meters.
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certif icat ion of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
MPU
RTC
TIMERS
IAP
VA
IBP
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
LINE
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
Shunt
POWER SUPPLY
TERIDIAN
71M6541D/F
TEMPERATURE
SENSOR
VREF
BATTERY
PWR MODE
CONTROL
WAKE-UP
NEUTRAL
I
2
C or µWire
EEPROM
IAN
IBN
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Divider
Pulse
Trans-
former
TERIDIAN
71M6xx1
Shunt
LINE
LINE
Note:
This system is referenced to LINE
11/5/2010
FEATURES
• 0.1% Acc ur acy Over 2000:1 Current Range
• Exceeds IEC 62053/ANSI C12.20 Standards
• Tw o Current S ensor Inp uts with S electable
Dif fer ential M od e
• Selectable Gain of 1 or 8 for One Current Input to
Support Shunts
• High-Speed Wh/VA R h Pu l se Outputs w i th
Programmable Width
• 32KB Fl as h, 3KB RAM ( 71M6541D)
• 64KB Fl as h, 5KB RAM ( 71M6541F/42F)
• 128KB F lash, 5KB RAM (71M6541G/42G)
• Up to Four Pulse Outputs with Pulse Count
• Four-Quad rant M eter ing
• Digital Tem pera ture C ompen sation:
- Metr ol ogy Compensation
- Accurate RTC for TOU Functions wit h
Automatic Temperature Com pensation f or
Crystal in All Power Modes
• Independent 32-Bit Comp ute E ngin e
• 46-64Hz Line Frequency Range with the Same
Calibration
• Pha se Compensation (±10°)
• Th ree Ba ttery-Backup Modes:
- Brownout Mode (BRN)
- LCD Mode (L CD)
- Sleep Mode (SLP)
• Wake-Up on Pin Ev ents an d Wake-On Timer
• 1µA in Sleep Mode
• Flas h Sec urit y
• In-Sy s tem Pro g ram Upd ate
• 8-Bit MPU (80515), Up t o 5 MI PS
• Full-Sp eed MPU C lock in Bro wno ut Mode
• LCD Driv er:
- Up to 6 Com m ons/Up to 56 Pi ns
• 5V LC D Dri ver wit h DA C
• Up to 51 Multifunction DIO Pins
• Hardware Watchdog Timer ( WDT)
• I2C/MICROWIRE® EEPROM Interfa c e
• SPI Interface with Flash P rogram Capability
• Two UARTs for IR and AMR
• IR LED Driver with Modulation
• Industria l Te mpe rature Range
• 64-Pi n (71M6541D/F /G) and 100-pin
(71M6542F/G) Lead(Pb) -Free LQF P Packa ge
19-5376; Rev 2; 11/11
Teridian is a trademark and Sin gl e Conv ert er Tec hnology is a registered trademark of
Max i m Int egrat ed P roducts, Inc.
MIC ROWIRE i s a registered trademark of National S emiconduc tor Corp.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table of Contents
1 Introduction ................................................................................................................................. 10
2 Hardware Descript io n .................................................................................................................. 11
2.1 Hardwar e Overv iew............................................................................................................... 11
2.2 Analog F r ont End (AF E ) ........................................................................................................ 12
2.2.1 Signal Input Pins ....................................................................................................... 14
2.2.2 Input M ultiplex er ........................................................................................................ 15
2.2.3 Delay Com pensation ................................................................................................. 19
2.2.4 ADC Pre-Amplifier ..................................................................................................... 20
2.2.5 A/D Converter (ADC) ................................................................................................. 20
2.2.6 FIR Filter ................................................................................................................... 20
2.2.7 Vol tage Referenc es ................................................................................................... 20
2.2.8 71M6x01 Isolated Sensor Interface (Rem ote Sensor I nterface) .................................. 22
2.3 Digital Com putation Engine (CE) ........................................................................................... 24
2.3.1 CE Progra m Me mory ................................................................................................. 24
2.3.2 CE Data M em ory ....................................................................................................... 24
2.3.3 CE Communicati on with t he MPU .............................................................................. 25
2.3.4 Meter E quations ........................................................................................................ 25
2.3.5 Real-Time Monitor (RTM) .......................................................................................... 25
2.3.6 Pul se Gener ators ...................................................................................................... 27
2.3.7 CE Functional Overview ............................................................................................ 28
2.4 80515 MP U Cor e .................................................................................................................. 31
2.4.1 Memory Or ganization and Addressing ....................................................................... 31
2.4.2 Special Function Registers (SF Rs) ............................................................................ 33
2.4.3 Generic 80515 Speci al Functi on Register s ................................................................ 34
2.4.4 Instruc tion S et ........................................................................................................... 36
2.4.5 UARTs ...................................................................................................................... 36
2.4.6 Timers and Counter s ................................................................................................. 39
2.4.7 WD Timer (Software Watchdog Timer) ...................................................................... 40
2.4.8 Interrupts ................................................................................................................... 40
2.5 On-Chip Resources ............................................................................................................... 48
2.5.1 Physical Memory ....................................................................................................... 48
2.5.2 Oscillator ................................................................................................................... 50
2.5.3 PLL and Internal Cl ocks............................................................................................. 50
2.5.4 Real-Time Clock (RTC) ............................................................................................. 51
2.5.5 71M654x Temperature Sensor .................................................................................. 56
2.5.6 71M654x Ba ttery Monitor ........................................................................................... 57
2.5.7 UART and Opti c al Interface ....................................................................................... 58
2.5.8 Digital I/O and LCD Segment Drivers ......................................................................... 59
2.5.9 EEPROM Interface .................................................................................................... 70
2.5.10 SPI S la ve Port ........................................................................................................... 73
2.5.11 Hardware Watchdog Timer ........................................................................................ 78
2.5.12 Test Por ts (TMUXOUT and TMUX2OUT Pi ns)........................................................... 78
3 Functio nal Descrip tion ................................................................................................................ 80
3.1 Theory of Operation .............................................................................................................. 80
3.2 Battery Modes ....................................................................................................................... 81
3.2.1 BRN Mode ................................................................................................................ 83
3.2.2 LCD Mode ................................................................................................................. 83
3.2.3 SLP Mode ................................................................................................................. 84
71M6541D/F/G and 71M6542F/G Dat a S heet
3.3 Fault and Reset B ehav ior ...................................................................................................... 85
3.3.1 Events at Power-Down .............................................................................................. 85
3.3.2 IC Behav ior at Low Batter y Volt age ........................................................................... 86
3.3.3 Reset Sequence ........................................................................................................ 86
3.3.4 W atchdog Timer Reset .............................................................................................. 86
3.4 Wake Up Behavior ................................................................................................................ 87
3.4.1 Wake on Hardware Events ........................................................................................ 87
3.4.2 Wake on Timer .......................................................................................................... 90
3.5 Dat a Flow and MPU/CE Communication ............................................................................... 91
4 Application Information ............................................................................................................... 92
4.1 Connecti ng 5 V Devices ........................................................................................................ 92
4.2 Direct Connection of Sensors ................................................................................................ 92
4.3 71M6541D/F/G Using Local Sensors..................................................................................... 93
4.4 71M6541D/F/G Using 71M6x01and Current Shunts .............................................................. 94
4.5 71M6542F/G Using Local Sensors ........................................................................................ 95
4.6 71M6542F/G Using 71M6x01 and Cur r ent Shunts ................................................................. 96
4.7 Metrology Temperat ur e Com pensation .................................................................................. 97
4.7.1 Voltage Re ference Precision ..................................................................................... 97
4.7.2 Temper ature Coefficient s for the 71M 654x ................................................................ 97
4.7.3 Temper ature Compensation for VREF wit h Loc al S ensors ......................................... 98
4.7.4 Temper ature Compensation for VREF wit h Rem ote Sensor ....................................... 99
4.8 Connecti ng I2C EEPROMs .................................................................................................. 100
4.9 Connecti ng Three-Wire EEPROMs ..................................................................................... 101
4.10 UART0 (TX/RX) .................................................................................................................. 101
4.11 Opti c al Interfac e ( UA RT1) ................................................................................................... 101
4.12 Connecti ng the Reset Pin .................................................................................................... 102
4.13 Connecti ng the Emulator Por t Pins ...................................................................................... 102
4.14 F lash Programming ............................................................................................................. 104
4.14.1 Flash Programming v ia the I CE Port ........................................................................ 104
4.14.2 Flash Programming v ia the SP I Por t ........................................................................ 104
4.15 MP U Firmware Li br ar y ........................................................................................................ 104
4.16 Cry stal O scillator ................................................................................................................. 104
4.17 Meter Calibration ................................................................................................................. 104
5 Firmware Interface ..................................................................................................................... 105
5.1 I /O RAM Map –Functiona l Order ......................................................................................... 105
5.2 I /O RAM Map – Alphabetic al Order ..................................................................................... 111
5.3 CE Interface Descripti on ..................................................................................................... 125
5.3.1 CE Program ............................................................................................................ 125
5.3.2 CE Data Format ...................................................................................................... 125
5.3.3 Constants ................................................................................................................ 125
5.3.4 Environment ............................................................................................................ 126
5.3.5 CE Cal c ulations ....................................................................................................... 126
5.3.6 CE Fr ont End Data (Raw Data)................................................................................ 127
5.3.7 FCE Status and Control ........................................................................................... 127
5.3.8 CE Tr ansfer Variabl es ............................................................................................. 129
5.3.9 Pul se Gener ation..................................................................................................... 132
5.3.10 Ot her CE Param eters .............................................................................................. 134
5.3.11 CE Cali br ation Parameters ...................................................................................... 135
5.3.12 CE Flow Diagr am s .................................................................................................. 136
6 Electrical Specificati on s ............................................................................................................ 138
71M6541D/F/G and 71M6542F/G Dat a S heet
6.1 Absol ute Maximum Ratings ................................................................................................. 138
6.2 Recom mended Ext er nal Com ponents ................................................................................. 139
6.3 Recommended Operating Conditions .................................................................................. 139
6.4 Perform anc e S pecificati ons ................................................................................................. 140
6.4.1 Input Logic Level s ................................................................................................... 140
6.4.2 Out put Logic Levels ................................................................................................. 140
6.4.3 Battery Monitor ........................................................................................................ 141
6.4.4 Temper ature Monit or ............................................................................................... 141
6.4.5 Suppl y Cur r ent ........................................................................................................ 142
6.4.6 V3P3D Switch ......................................................................................................... 143
6.4.7 Int er nal Power F ault Comparators ........................................................................... 143
6.4.8 2.5 V V oltage Regulator – System Power ................................................................ 143
6.4.9 2.5 V V oltage Regulator – Battery Power ................................................................. 144
6.4.10 Crystal Oscill ator ..................................................................................................... 144
6.4.11 Phase-Locked Loo p ( P LL) ....................................................................................... 144
6.4.12 LCD Drivers ............................................................................................................ 145
6.4.13 VLCD Gener ator...................................................................................................... 146
6.4.14 VREF ...................................................................................................................... 148
6.4.15 ADC Converter ........................................................................................................ 149
6.4.16 Pre-A mplifier for IAP-IAN ......................................................................................... 150
6.5 Timing Specifications .......................................................................................................... 151
6.5.1 Flash Memory ......................................................................................................... 151
6.5.2 SPI Slav e ................................................................................................................ 151
6.5.3 EEPROM Interface .................................................................................................. 151
6.5.4 RESET Pi n .............................................................................................................. 152
6.5.5 RTC ........................................................................................................................ 152
6.6 Pac k age Outline Dr awings .................................................................................................. 153
6.6.1 64-Pi n LQF P Outline Package Dr awing ................................................................... 153
6.6.2 100-Pi n LQF P Package Outline Drawing ................................................................. 154
6.7 Pac k age M ar k ings .............................................................................................................. 155
6.8 Pinout Diagr am s ................................................................................................................. 156
6.8.1 71M6541D/F/G LQFP-64 Package Pinout ............................................................... 156
6.8.2 71M6542F/G LQFP-100 Pack age Pi nout ................................................................. 157
6.9 Pin Descriptions .................................................................................................................. 158
6.9.1 Power and Ground Pins........................................................................................... 158
6.9.2 Anal og Pi ns ............................................................................................................. 159
6.9.3 Digital Pins .............................................................................................................. 160
6.9.4 I/ O Equivalent Circuits ............................................................................................. 162
7 Orderin g I nformation ................................................................................................................. 163
7.1 71M6541D/F/G and 71M6542F/ G ....................................................................................... 163
8 Related In format ion ................................................................................................................... 163
9 Contact Information ................................................................................................................... 163
Appendix A: Acronyms ..................................................................................................................... 164
Appendi x B: Revisio n Hi sto ry ........................................................................................................... 165
71M6541D/F/G and 71M6542F/G Dat a S heet
Figures
Figure 2. 71M6541D/ F/ G AFE Bl oc k Di agr am (Local S ensors) ............................................................... 12
Figure 3. 71M6541D/ F/ G AFE Bl oc k Di agr am with 71M6x01.................................................................. 13
Figure 4. 71M6542F /G AFE Block Diagr am ( Loc al S ensors) .................................................................. 13
Figure 5. 71M6542F /G AFE Block Diagr am with 71M6x01 ..................................................................... 14
Figure 6: States i n a Multiplexer Fr am e (MUX_DIV[3:0] = 3) .................................................................. 17
Figure 7: States i n a Multiplexer Fr am e (MUX_DIV[3:0] = 4) .................................................................. 17
Figure 8: General Topology of a Chopped Amplifier ............................................................................... 21
Figure 9: CROSS Signal with CHOP_E = 00 ........................................................................................... 21
Figure 10: RTM Timi ng .......................................................................................................................... 26
Figure 11: Timi ng r elationship bet ween ADC MUX, CE, and RT M Serial Transf er .................................. 26
Figure 12. Pulse Generator FIFO Timing ............................................................................................... 28
Figure 13: Acc um ulation Interv al ............................................................................................................ 29
Figure 14: Samples fr om Multiplexer Cycle (MUX_DIV[3:0] = 3) ............................................................. 30
Figure 15: Samples fr om Multiplexer Cycle (MUX_DIV[3:0] = 4) ............................................................. 30
Figure 16: Interr upt Structure ................................................................................................................. 47
Figure 17: Aut om atic Temper ature Compensation ................................................................................. 54
Figure 18: Optical Interfac e .................................................................................................................... 58
Figure 19: Optical Interfac e ( UA RT1) ..................................................................................................... 59
Figure 20: Connect ing an Exter nal Load to DIO Pi ns ............................................................................. 60
Figure 21: LCD Wavef orms ................................................................................................................... 68
Figure 22: 3-wire I nterface. Write Command, HiZ=0. ............................................................................. 72
Figure 23: 3-wire I nterface. Write Command, HiZ=1 .............................................................................. 72
Figure 24: 3-wire I nterface. Read Command. ........................................................................................ 72
Figure 25: 3-Wir e Int erfac e. Write Command when CNT=0 ................................................................... 73
Figure 26: 3-wire I nterface. Write Command when HiZ= 1 and WF R=1. ................................................. 73
Figure 27: SPI Slav e Port - Typica l Multi-Byte Read and Wri te operati ons .............................................. 75
Figure 28: Volt age, Current, Moment ar y and Accum ulated Ener gy ......................................................... 80
Figure 29: Oper ation Modes State Diagram ........................................................................................... 81
Figure 30: MPU/CE Data Flow ............................................................................................................... 91
Figure 31: Resistive Voltage Divider (Volt age S ensi ng) .......................................................................... 92
Figure 32. CT with Si ngle-Ended Input Connec tion (Current Sensi ng) .................................................... 92
Figure 33: CT with Differential Input Connection (Current Sensi ng) ........................................................ 92
Figure 34: Differenti al Resi stive Shunt Connections (Current S ensi ng) ................................................... 92
Figure 35. 71M6541D/ F/G with Local Sensors ....................................................................................... 93
Figure 36: 71M6541D/ F/G with 71M6x01 isol ated Sensor ...................................................................... 94
Figure 39: I2C EEPROM Connec tion .................................................................................................... 101
Figure 40: Connect ions for UART0 ...................................................................................................... 101
Figure 41: Connect ion for Optic al Com ponents .................................................................................... 102
Figure 42: Exter na l Comp onents for the RESET Pin: Push-Button (Left), Production Circuit (Right) ......... 102
Figure 43: External Components for the Emulator Interface ................................................................. 103
Figure 44: CE Data Flow: Multipl ex er and ADC .................................................................................... 136
Figure 45: CE Data Flow: Sc aling, Gain Control, Intermediate Variables .............................................. 136
Figure 46: CE Data Flow: Squar ing and Summati on Stages ................................................................. 137
Figure 47: 64-pi n LQFP Pac k age Outli ne ............................................................................................. 153
Figure 48: 100-pi n LQF P Pack age Outli ne ........................................................................................... 154
Figure 49. Pack age M arkings (Examples) ............................................................................................ 155
Figure 50: Pinout for the 71M6541D/F/G ( LQF P-64 Package) .............................................................. 156
Figure 52: I/O Equivalent Ci rcuit s ......................................................................................................... 162
71M6541D/F/G and 71M6542F/G Dat a S heet
Tables
Table 1. Requir ed CE Code and Set tings for Local S ensors ................................................................... 15
Table 2. Requir ed CE Code and Set tings for 71M6x 01 isolated S ensor ................................................. 16
Table 3: ADC Input Configurati on ......................................................................................................... 17
Table 4: Multi plexer and A DC Configurati on Bits ................................................................................... 19
Table 5. RCMD[4:0] Bits ........................................................................................................................ 22
Table 6: Remote Interf ac e Read Commands ........................................................................................ 23
Table 7: I /O RAM Cont r ol Bits for Isolated Sensor ................................................................................. 23
Table 8: Input s Selected in Multi plex er Cy cl es ....................................................................................... 25
Table 9: CKMPU Clock Frequenc ies ...................................................................................................... 31
Table 10: Memory Map .......................................................................................................................... 32
Table 11: Int er nal Data Memory Map ..................................................................................................... 33
Table 12: Special F unc tion Regi ster Map ............................................................................................... 33
Table 13: Generic 80515 SFRs - Locati on and Reset V alues ................................................................. 34
Table 14: PSW Bit Functions (SFR 0xD0) ................................................................................................. 35
Table 15: Port Regi ster s (SE GDIO0-15) ................................................................................................ 36
Table 16: Str etch M em ory Cycl e Width .................................................................................................. 36
Table 17: Baud Rate Generati on............................................................................................................ 37
Table 18: UART Modes ......................................................................................................................... 37
Table 19: The S0CON (UART0) Register (SFR 0x 98) ............................................................................. 38
Table 20: The S1CON (UART1) Register (SFR 0x 9B ) ............................................................................. 38
Table 21: PCON Register Bi t Description (SFR 0x 87) ............................................................................ 39
Table 22: Timer s/Counters Mode Descri ption ........................................................................................ 39
Table 23: All owed Timer /Counter Mode Combinations ........................................................................... 39
Table 24: TMOD Regi ster Bit Descripti on (SF R 0x 89) ............................................................................ 40
Table 25: The TCON Register Bit Functions (SFR 0x 88) ........................................................................ 40
Table 26: The IEN0 Bit Functi ons (SFR 0xA 8) ........................................................................................ 41
Table 27: The IEN1 Bit Functi ons (SFR 0xB 8) ........................................................................................ 41
Table 28: The IEN2 Bit Functions (SFR 0x9A) ........................................................................................ 42
Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 42
Table 30: The T2CON Bit F unctions (SFR 0xC8) ................................................................................... 42
Table 31: The IRCON Bit F unc tions (SFR 0xC0) .................................................................................... 42
Table 32: External MPU Interrupts ......................................................................................................... 44
Table 33: Interrupt Enable and Flag Bits ............................................................................................... 44
Table 34: Int er r upt Pri ori ty Level Groups ................................................................................................ 45
Table 35: Int er r upt Pri ori ty Levels .......................................................................................................... 45
Table 36: Int er r upt Pri ori ty Registers (IP0 and IP1) ................................................................................. 45
Table 37: Int er r upt Polling Sequence ..................................................................................................... 46
Table 38: Int er r upt Vector s .................................................................................................................... 46
Table 39: Flash Memory Access ............................................................................................................ 48
Table 40: Flash Security ........................................................................................................................ 49
Table 41: Clock Sy stem Summ ar y ......................................................................................................... 51
Table 42: RTC Control Registers ........................................................................................................... 52
Table 43: I/O RAM Registers for RTC Temperature Compensation ........................................................ 53
Table 44: NV RAM T em per ature Tabl e Str uc ture ................................................................................... 54
Table 45: I/O RAM Registers for RTC Inter r upts .................................................................................... 55
Table 46: I/O RAM Registers for Temper ature and Battery Measurement .............................................. 56
Table 47: Select able Resourc es using the DIO_Rn[2:0] Bits................................................................... 59
Table 48: Data/ Dir ec tion Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G ) .................................. 61
Table 49: Data/ Dir ec tion Registers for SEGDIO19 to SEGDIO 27 ( 71M 6541D/F/G ) ................................ 62
Table 50: Data/ Dir ec tion Registers for SEGDIO36-39 to SEGDIO44 -45 (71M6541D/F/G) ...................... 62
Table 51: Data/ Dir ec tion Registers for SEGDIO51 and SEG DIO 55 ( 71M 6541D/F/G ) ............................. 62
Table 52: Data/ Dir ec tion Registers for SEGDIO0 to SEGDIO15 (71M6542F/G) ..................................... 63
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 53: Data/ Dir ec tion Registers for SEGDIO16 to SEGDIO 31 ( 71M 6542F/G) ................................... 64
Table 54: Data/ Dir ec tion Registers for SEGDIO32 to SEGDIO 45 ( 71M 6542F/G) ................................... 64
Table 55: Data/ Dir ec tion Registers for SEGDIO51 to SEGDIO 55 ( 71M 6542F/G) ................................... 64
Table 56: LCD_VMODE[1:0] Configurations .......................................................................................... 65
Table 57: LCD Configurations ............................................................................................................... 67
Table 58: 71M6541D/F/G LCD Data Regi ster s for SEG46 to S EG50 ..................................................... 69
Table 59: 71M6542F/G LCD Data Registers for SEG 46 to SEG50 ......................................................... 70
Table 60: EECTRL Bits for 2-pin Interface ............................................................................................... 71
Table 61: EECTRL Bits for the 3-wire I nterface ....................................................................................... 71
Table 62: SPI Transaction Fields ........................................................................................................... 74
Table 63: SPI Command Sequences ..................................................................................................... 75
Table 64: SPI Regi ster s ......................................................................................................................... 76
Table 65: TMUX[5:0] Selections ............................................................................................................ 79
Table 66: TMUX2[4:0] Selections ........................................................................................................... 79
Table 67: Available Circuit F unc tions ..................................................................................................... 82
Table 68: VSTAT[2:0] (SFR 0xF9[2:0]) .................................................................................................... 85
Table 69: Wak e Enabl es and Flag Bi ts .................................................................................................. 87
Table 70: Wak e Bits .............................................................................................................................. 89
Table 71: Clear Events for WAKE fl ags .................................................................................................. 90
Table 72: GAIN_ADJ n Com pensation Channels .................................................................................... 98
Table 73: GAIN_ADJ n Com pensation Channels .................................................................................. 100
Table 74: I/O RAM Map – Func tional Order , Basi c Configurati on ......................................................... 105
Table 75: I/O RAM Map – Functional Order ......................................................................................... 107
Table 76: I/O RAM Map – Functional Order ......................................................................................... 111
Table 77. Standar d CE Codes ............................................................................................................. 125
Table 78: CE EQU Equations and Element Input Mapping ................................................................... 126
Table 79: CE Raw Data Access Locations ........................................................................................... 127
Table 80: CESTATUS Register .............................................................................................................. 127
Table 81: CESTATUS (C E RAM 0x8 0 ) Bit Defin itions .............................................................................. 128
Table 82: CECONFIG Register ............................................................................................................. 128
Table 83: CECONFIG (CE RAM 0x20) Bit Definiti ons ............................................................................. 128
Table 84: Sag Threshold and G ain Adjust Control ................................................................................ 129
Table 85: CE Transf er Variables (with Loc al S ensors).......................................................................... 130
Table 86: CE Transf er Variables (with Rem ote Sensor) ....................................................................... 130
Table 87: CE Energy Measurement Variables (with Local Sensors) ..................................................... 131
Table 88: CE Energy Measurement Variables (with Remote Sensor) ................................................... 131
Table 89: Other Transfer Vari ables ...................................................................................................... 132
Table 90: CE Pulse Generation Param eters......................................................................................... 133
Table 91: CE Param eters for Noise Suppres si on and Code V er si on..................................................... 134
Table 92: CE Calibrat ion Paramet er s ................................................................................................... 135
Table 93: Absolut e M aximum Ratings .................................................................................................. 138
Table 95: Recommended Operati ng Conditions ................................................................................... 139
Table 96: Input Logic Lev els ................................................................................................................ 140
Table 97: Output Logic Level s ............................................................................................................. 140
Table 98: Battery M onitor Performance Specifications (TEMP_BAT= 1) ................................................ 141
Table 99. Temper ature Monitor ............................................................................................................ 141
Table 100: Suppl y Current Perform anc e S pecificati ons ........................................................................ 142
Table 101: V3P3D Switch Performance Specifications ......................................................................... 143
Table 102. Int er nal P ower Fault Comparator Specifications ................................................................. 143
Table 103: 2.5 V Voltage Regulat or Performance Specif ications .......................................................... 143
Table 104: Low-Power Voltage Regulat or Performanc e Specif ic ations ................................................. 144
Table 105: Crystal Oscillat or P erformance Specificati ons ..................................................................... 144
Table 106: PLL Performance Specifications ......................................................................................... 144
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 107: LCD Driver Performance S pecificati ons .............................................................................. 145
Table 108: LCD Driver Performance S pecificati ons .............................................................................. 146
Table 109: VREF Performance Specifications ...................................................................................... 148
Table 110. ADC Converter Performance Specifications ....................................................................... 149
Table 111: Pre-Am plifier Performance Specificati ons ........................................................................... 150
Table 112: Flash Memory Timing Specific ations .................................................................................. 151
Table 113. SPI Slave Timing Specific ations ......................................................................................... 151
Table 114: EEPROM Int erface Timing ................................................................................................. 151
Table 115: RESET Pin Timing ............................................................................................................. 152
Table 116: RTC Range f or Date........................................................................................................... 152
Table 117. 71M6541 Pack age M ar ki ngs .............................................................................................. 155
Table 118. 71M6542 Pack age M ar ki ngs .............................................................................................. 155
Table 119: Power and Ground Pins ..................................................................................................... 158
Table 120: Anal og Pi ns ........................................................................................................................ 159
Table 121: Digital Pins ......................................................................................................................... 160
Table 122. Orderi ng Informati on .......................................................................................................... 163
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 1: IC Functional Block Diagram
71M6541D/F/G and 71M6542F/G Dat a S heet
1 Introduction
This data sheet cover s the 71M 6541D ( 32K B ) , 71M6541F (64KB ), 71M6541G ( 128K B ), 71M6542F
(64KB), and 71M6542G (128KB) fourth generation Teridian energy measurement SoCs. T he term
“71M654x” is used when discu ssing a device feature or behavi or that is applicable to all four part
num ber s. The appropriate part number is i ndic ated when a device feat ur e or behav ior is bei ng discussed
that applies only to a specific part num ber. This data sheet also cover s basic detail s about the c om panion
71M6x01 isolated c ur r ent sensor device. For more compl ete information on the 71M6x 01 sensors, r efer
to t he 71M 6xxx Data Sheet.
This document covers the use of the 71M654x wit h local ly connect ed sensors as well when it is used in
conj unc tion with the 71M6x01 isol ated current sensor. T he 71M654x and 71M6x01 chipset m ak e it
possible to use one non-i sol ated and one i sol ated shunt current sensor t o c r eate single-phase and two-
phase energy meters using inexpensive shunt resi stor s , whil e ac hiev ing unprecedented performance wi th
this type of sensor technol ogy . The 71M 654x SoCs also support conf igurati ons i nvolv ing one loc ally
connect ed shunt and one locally c onnec ted Current Transformer (CT), or two CTs.
To f acil itate doc um ent navigati on, hyper links are often used t o r eference figur es, tables and section
headings that are locat ed in other par ts of t he doc um ent. All hy perli nk s i n this document ar e highlight ed in
blue. Hyperlinks are used extensively to inc rease the level of det ail and cl ar ity prov ided within each
secti on by r eferencing other relev ant parts of the document. To f urther facilit ate document navigation, this
document is publi shed as a PDF docum ent with bookmark s enabl ed.
The reader is also encouraged to obt ain and rev iew the document s listed i n 8 Related Infor mation on
page 163 of this docu ment.
71M6541D/F/G and 71M6542F/G Dat a S heet
2 Hardware Description
2.1 Hardware Overview
The Teridian 71M6541D/F/G and 71M6542F/G single-chip ener gy meter ICs integrate all primar y
functi onal bloc k s required t o impl em ent a solid-state residential electricity meter. Included on the chip
are:
• An analog front end (AFE) feat uri ng a 22-bit second-order sigma-delta ADC
• An independent 32-bi t digital comput ation engine ( CE) to implement DSP functions
• An 8051-compati ble mi c r opr oc essor (MPU) whic h ex ecutes one i nstr uc ti on per cl oc k cycl e (80515)
• A precision volt age r eference ( V REF)
• A tem per ature sensor f or di gital temperat ur e c om pensation:
- Metrology digital temperat ur e c om pensation (MPU)
- Autom atic RTC digital temperature compensati on oper ational in all power states
• LCD driv er s
• RAM and Flash memory
• A real time clock (RT C)
• A variety of I/O pi ns
• A power failure interr upt
• A zero-crossing interrupt
• Selec table curr ent sensor interfaces for l oc ally-c onnec ted sensors as well as isol ated sensors (i.e.,
using the 71M 6x01 companion IC with a shunt resi stor sensor)
• Resistive Shunt and Cur r ent Transf ormers are supported
Resistive Shunts and Current Transform er s (CT ) current sensors are supported. Resistive shunt current
sensors may be connected directly to t he 71M 654x devi c e or i sol ated using a companion 71M6x01
isolator IC in order to implement a vari ety of single-phase / split-phase (71M6541D/F/G) or two-phase
(71M6542F/G) metering configurations . An inexpensive, sm all si z e pulse tr ansform er i s used to isolat e
the 71M 6x01 isol ated sensor fr om the 71M 654x . T he 71M654x performs di gital comm unic ations bi-
dir ec tionall y with t he 71M6x01 and also provides power to the 71M6x01 t hr ough the isolati ng pulse
transformer. Isolated (remote) shunt curr ent sensors ar e c onnec ted to the differenti al input of the
71M6x01. Included on the 71M6x01 c om panion isolat or chip are:
• Digit al isolation communi cations interf ac e
• An analog front end (AFE)
• A precision voltage ref er enc e (VREF)
• A temperature sensor (f or di gital temperat ur e c om pensation)
• A fully differ ential shunt resistor sensor input
• A pre-amplifi er to optimize shunt current sensor performanc e
• Isolated power c ircuitry obtains dc power from pulses sent by t he 71M 654x
In a typical application, the 32-bit compute engine (CE) of the 71M654x sequenti ally processes the samples
from the voltage inputs on analog input pins and from the external 71M6x01 isolated sensors and pe rforms
calculations to measure active ener gy (Wh) and reactive ener gy ( V A Rh) , as wel l as A2h, and V 2h for four-
quadrant metering. These measurements are t hen ac cessed by the M P U, processed fur ther and output
using the per ipher al devices availabl e to the MPU.
In add ition to ad vanc ed meas ure me nt fu nc tions , the c loc k func t ion allows the 71M6541D/F/G and
71M6542F/G to record time-of-use (TOU) metering info rma tion for mu lti-rate applications and to tim e-
stamp tamper or other events. Measurements can be displayed on 3.3 V LCDs commonly used in low-tem-
perature environments. An on-chip charge pum p is availabl e to driv e 5 V LCDs. Flexi ble mapping of LCD
displ ay segments faci litate integration of existing custom LCDs. Desi gn trade-off bet ween the number of
LCD segment s and DIO pins can be im plem ented in software to ac c ommodate various requir ements.
In addition to the temperature-t rimmed ultra-preci si on vol tage ref er enc e, t he on-c hip digital temper ature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temperature effe cts on measurement and RTC acc ur acy, e.g., to meet the require ments of ANSI and IEC
71M6541D/F/G and 71M6542F/G Dat a S heet
standards. Temperature-depe nde nt external components such as crystal oscillator, re sis tive s hun ts, current
transform er s (CT s) and t heir c or r espondi ng si gnal conditioning ci rcuit s can be char ac terized and their
correc ti on factors can be programmed to produce electricit y met er s with ex c eptional accur ac y over the
industria l temperat ure range.
One o f the two interna l UAR Ts is adap ted to suppor t an Infrared L ED with interna l dr ive and s ens e con figurat ion
and can als o fu nct ion a s a stand ard UART . The optical output can be modulated at 38 kHz. This flexib ilit y
m ak es it possible to im plem ent AM R met er s with an IR int erface. A bl oc k diagr am of t he IC is shown in
Figure 1.
2.2 Analog Front End (AFE)
The AFE functi ons as a data acquisiti on system, control led by the MPU. When used wi th locally
connect ed sen sors, as seen in Figure 2, the analog input signal s (IAP-IAN, VA and IBP-IBN) are
m ultiplexed t o the ADC input and sampled by the A DC. The ADC output is decimated by the FIR filter
and stored i n CE RAM where it can be acc essed and proc es sed by t he CE .
See Figure 6 f or the m ultiplexer sequence corr esponding to Figure 2. See Figure 35 for the meter
configuration corr espondi ng to Figure 2.
∆Σ ADC
CONVERTER
VREF
MUX
VREF
VREF
VADC 22
FIR
IBP
IAP
VADC10 (VA)
IAN
IBN
71M6541D/F
CE RAM
*IN = Optional Neutral Current
Local
Shunt
IN*
CT
I
LINE
or
CT
11/5/2010
I
LINE
Figure 2. 71M6541D/F/G AFE Blo ck Diag ram (Local Sensors)
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 3 shows the 71M6541D/F/G multiplexer int erface with one local and one rem ote resi stive shunt
sensor. As seen in Figure 3, when a r emote isolat ed shunt sensor is connected v ia the 71M6x01, t he
samples associat ed with this curr ent channel are not routed to the multiplexer, and ar e instead
transferred digitally to the 71M6541D/F/G via the digital isolation interface and are dir ectly stor ed in CE
RAM.
See Figure 6 f or the m ultiplexer timing sequence cor r es ponding t o Figure 3. See Figure 36 for the meter
configurations corresponding to Figure 3.
∆Σ ADC
CONVERTER
VREF
MUX
VREF
VREF
VADC 22
FIR
IBP
IAP
VADC10 (VA)
IAN
IBN
71M6541D/F
CE RAM
71M6x01
SP
SN
INP
INN
Remote
Shunt
IN*
Digital
Isolation
Interface
Local
Shunt
I
LINE
22
11/5/2010
* IN = Optional Neutral Current
Figure 3. 71M6541D/F/G AFE Blo ck Diag ram with 71M6x01
Figure 4 shows the 71M6542F/G AFE with loc ally c onnected sensors. The anal og input signal s (I A P-IAN,
VA, IBP-IBN and VB) are m ultiplexed t o the ADC input and sampl ed by the ADC. The ADC out put is
decimated by the FIR filter and stored i n CE RAM where it can be acc essed and processed by the CE.
See Figure 7 for the multip lexer timing sequence cor r es ponding t o Figure 4. See Figure 37 for the meter
configuration corr espondi ng to Figure 4.
∆Σ ADC
CONVERTER
VREF
MUX
VREF
VREF
VADC 22
FIR
IBP
IAP
VADC10 (VA)
IAN
IBN
71M6542F
CE RAM
Local
Shunt
IB
CT
IA
or
CT
11/5/2010
IA
VADC9 (VB)
Figure 4. 71M6542F/G AFE Blo ck Diag ram (Local Sensors)
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 5 shows t he 71M6542F/G multipl ex er i nterf ac e with one local and one rem ote resistiv e shunt
sensor. As seen in Figure 5, when a r emote isolat ed shunt sensor is connected v ia the 71M6x01, t he
samples associat ed with this curr ent channel are not routed to the multiplexer, and ar e instead
transferred digitally to the 71M6542F/G via the digit al isol ation i nterface and are dir ectly st or ed in CE
RAM.
See Figure 6 f or the m ultiplexer timing sequence cor r es ponding t o Figure 5. See Figure 38 for the meter
configurations corresponding to Figure 5.
∆Σ ADC
CONVERTER
VREF
MUX
VREF
VREF
VADC
22
FIR
IBP
VADC9 (VB)
IAP
VADC10 (VA)
IAN
IBN
71M6542F
CE RAM
71M6x01
SP
SN
INP
INN
Remote
Shunt
IB
Digital
Isolation
Interface
Local
Shunt
IA
22
11/5/2010
Figure 5. 71M6542F/G AFE Blo ck Diag ram wi th 71M6x01
2.2.1 Signal Input Pin s
The 71M6541D/F/G features five ADC inputs. The 71M6542F/G features six A DC input s.
IAP-IAN and IBP-IBN are intended for use as cu rrent sens or inpu ts . Thes e fou r curr en t sens or inputs can be
configure d as fou r s ingle-ended inputs, or can be paired to form two differential inputs. For best
perfor manc e , it is recom men ded to con figu re the cu rre n t sensor inputs as differential inputs (i.e., IAP-IAN
and IBP-IBN). The first differential input (IAP-IAN) features a pre-ampli fier with a selectabl e gain of 1 or 8,
and is intended for direc t connection to a shun t resistor sens or , and can also be us ed with a Cur ren t
Transformer (CT). The remaining differential pair (i.e., IBP-IBN) may be used with CT s, or may be enabled
to i nterface to a remot e 71M6x01 isolated c urrent s enso r providing i s olat ion for a shu nt re sisto r s en s or using
a low cos t pulse transformer .
The remaining input in the 71M6541D/F/G (VA) is single-end ed , and is intended for se ns ing the line voltage
in a single-phase me te r app lica tion using Equa t ion 0 or 1 (see 2.3.4 M eter Equations on page 25). The
71M6542F/G features an additional single-ended vo lt ag e sensing input (VB) to suppo r t bi -phase
applications usi ng Equation 2. These si ngle-ended inputs are referenced to the V3P3A pin.
All analog si gnal input pins measure voltage. In the case of shunt current sensors, currents are sensed as a
voltage drop in the s hun t resistor sensor. Referring to Figure 3, shunt sens ors ca n be conne c ted dire c t ly to
the 71M654x (re fe rred t o as a ‘loc a l’ shun t sensor ) or co nnec ted via an iso lated 71M6x01 (referred to as a
‘remote’ shunt sensor). In the case of C urren t Transforme rs (CT), the cu rrent is measur ed as a voltage
across a bur den resistor that is connected to the secondary winding of the CT. Meanwhile, line voltages are
sensed through resistive voltage dividers. The VA and VB pins (VB is available in the 71M6542F/G only)
are single-ended and their co mmon return is the V3P3A pin.
Pins IAP-IAN can be programmed individually to be differential or single-ended as determi ned by the
DIFFA_E (I/O RAM 0x210C[4]) co ntrol bit. Howe ver, for most applicati ons, IAP-IAN are configur ed as a
differential input t o work wit h a shunt or CT directly interfaced to the IAP-IAN differential input with the
appropriate ex ternal signal conditioning components (see 4.2 Direct Connection of Sensors on page 92).
71M6541D/F/G and 71M6542F/G Dat a S heet
The performanc e of t he IAP-IAN pins can be enhanced by enabling a pre-am plifi er with a f ixed gain of 8,
using the I/O RAM cont r ol bit PRE_E (I/O RAM 0x2704 [5 ]) . When PRE_E = 1, IAP-IAN become the inputs
to t he 8x pre-amplifi er, and the output of this amplif ier is su ppli ed to the multi plex er . T he 8x amplification
is usef ul when current sensor s with low sen si tivity, such as shunt resi stor s, ar e used. With PRE_E set, the
IAP-IAN input si gnal am plitude is restricted t o 31.25 mV peak.
For the 71M654x application utilizing two shunt res istor s ens ors (Figure 3), the IAP-IAN pi ns ar e c onfig ured
for differential mode to interface to a local shunt by setting the DIFFA_E cont ro l b it. Mea nw hile, the IBP-IBN
pins are re-configured as digital balanced pair to communicate w ith a Teridian 71M6x01 Isolated Sensor
interface by s etting the RMT_E control bi t (I/O RA M 0x27 09[3 ]). The 71M6x01 communicates w ith the
71M654x using a bi-directional digi tal data s tream through an iso la t ing low -cost pulse transformer. The
71M654 x a lso su pp lies power to the 71M6 x01 through t he iso la t ing transforme r . This type of interface is
further des c r ibed at th e end of th is chap te r (see 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor
Interface)).
For use with Cur r ent Transf ormers (CTs), as sho wn in Figure 2, the RMT_E control bit is reset, so that the
IBP-IBN pins are c onfi gur ed as l oc al analog inputs. The IAP-IAN pins cannot be c onfigured as a remote
sensor interf ac e.
2.2.2 Inp ut Mu lt iple x e r
When operating with local sensors, the input multiplexer sequentially applies the input signals fro m the analog
input pins to the input of the ADC (see Figure 2 and Figure 4). One complete sampling sequence is called a
multiplexer frame. The multiplexer of the 71M6541D/F/G can sel ec t up to three input signals (IAP-IAN, VA,
and IBP-IBN) per multiplexer frame as controlled by the I/O RAM contr ol field MUX_DIV[3:0] (I/O RAM
0x2100[7:4]) (see Figure 6). The multiplex er of t he 71M6542F/G ad ds t he VB sig nal to achieve a total
of four inputs (see Figure 7). T he m ult i plex er alway s s tar t s at stat e 1 and pr oc ee d s until as m a ny
states as determined by MUX_DIV[3:0] have been conver ted.
The 71M 65 4 1D/F /G and 71M6542F/G e ac h r eq ui re a uni qu e CE code that is wri tten for the specifi c
applicat io n. Mo r eover, each CE code r equire s spec ific AF E and MU X set ti ngs in or der to func tion
properly. Table 1 provi des th e CE code and s ettin gs c or responding to t he local sensor configurations
sho wn in Figure 2 and Figure 4. Table 2 provides the CE code and sett ings corresponding to the
loc al/remote sensor configuration utilizi ng the 71M6x 01 as shown in Figure 3 and Figure 5.
Table 1. Required CE Cod e and Settin gs for Local Sensors
I/O RAM
Mnemonic I/O RAM
Location 71M6541D/F/G
(hex)
71M6542F/G
(hex)
Eq. 0 or 1
Eq. 2
FIR_LEN[1:0]
210C[2:1]
1
1
2
ADC_DIV
2200[5]
1
1
0
PLL_FAST
2200[4]
1
1
1
MUX_DIV[3:0]
2100[7:4]
3
3
4
MUX0_SEL[3:0]
2105[3:0]
0
0
0
MUX1_SEL[3:0]
2105[7:4]
A
A
A
MUX2_SEL[3:0]
2104[3:0]
2
2
2
MUX3_SEL[3:0]
2104[7:4]
1
1
9
RMT_E
2709[3]
0
0
0
DIFFA_E
210C[4]
1
1
1
DIFFB_E
210C[5]
1
1
1
EQU[2:0]
2106[7:5]
0 or 1
0 or 1
2
CE Code
--
CE41A01
CE41A01
CE41A04
Equations
--
0 or 1
0 or 1
2
Current S ensor T y pes
--
1 Shunt and 1 CT
or
2 CTs
1 Shunt and 1 CT
or
2 CTs
1 Shunt and 1 CT
or
2 CTs
Applicable Figure
--
Figure 2
Figure 4
Figure 4
Notes:
Teridian updates the CE code periodically. Please c ontact y our l oc al Teridian repre sentative to obtain the late st CE
code and th e assoc i at ed s ett in gs . The co nfiguration presented in this table is set by the MPU demonstration code
during initialization.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 2. Required CE Cod e and Settings for 71M6x01 isolated Sensor
I/O RAM
Mnemonic
I/O RAM
Location
71M6541D/F/G
(hex)
71M6542F/G
(hex)
FIR_LEN[1:0]
210C[2:1]
1
1
ADC_DIV
2200[5]
1
1
PLL_FAST
2200[4]
1
1
MUX_DIV[3:0]
2100[7:4]
3
3
MUX0_SEL[3:0]
2105[3:0]
0
0
MUX1_SEL[3:0]
2105[7:4]
A
A
MUX2_SEL[3:0]1
2104[3:0]
1
9
MUX3_SEL[3:0]1
2104[7:4]
1
1
RMT_E
2709[3]
1
1
DIFFA_E
210C[4]
1
1
DIFFB_E
210C[5]
0
0
EQU[2:0]
2106[7:5]
0 or 1
0, 1 or 2
CE Code --
CE41B0162012
CE41B016601
3
Equations
--
0, 1
0, 1 and 2
Current S ensor T y pe --
1 Local Shunt
and
1 Rem ote Shunt
1 Local Shunt
and
1 Rem ote Shunt
Applicable Figure
--
Figure 3
Figure 5
Notes:
1. Although not used, set to 1 (the sample data is ignored by the CE)
2. 71M654x with 71M6201 remote sensor (200 Amps)
3. 71M654x with 71M6601 remote sensor (60 Amps)
Teridian updates the CE code periodically. Please c ontact y our l oc al Teridian representative to
obtain the latest CE code and the associated settings. The configuratio n presented in this table is
set by the MPU demonstration code during initialization.
Using settings for the I/ O RAM Mnemoni cs listed in Table 1 and Table 2 that do n ot matc h
those req uired by the corresponding CE co de being used re sul ts in un de sira bl e si de ef f ec ts
and must n ot b e selected by the MPU. Consul t your l ocal Teridian re presentative to obtain
the correct CE code and AFE / MU X s et t i ngs corre s pondi ng to t he applicat io n.
For a basi c single-phase application, the IAP-IAN c ur r ent input is configured for differential mode,
whereas the VA pin i s single-ended and is typically connected to the phase voltage via a resistor div ider.
The IBP-IBN dif feren t ial inpu t may be optiona lly used to s ens e the Neutral current. This configuration
implies t hat t he m ultiplexer applies a total of three inputs t o the ADC. For this configuration, the
m ultiplexer sequence is as shown in Figure 6. In this co nfiguration IAP-IAN, IBP-IBN and VA are
sampled, the extra conversion time slot (i.e., slot 2) is the opti onal Neutral cur r ent, and the physical
current sensor for the Neutral curr ent measurement m ay be omit ted if not requir ed.
For a standar d si ngle-phase application with tamper sensor in the neutral path, two current inputs can be
configured for d iffe ren tial mode , us ing the pi n pairs IAP-IAN and IBP-IBN. This means that the multiplexer
applies a total of three inputs to the ADC. In this application, the system design may use two locally
connec ted cu rrent se nsors via IAP-IAN and IBP-IBN, as s how n in Figure 2, and configured as differential
inputs. Alternately, t he IAP-IAN p in pair is configure d as a differen t ia l input and connected to a local current
shunt, and IBP-IBN is configured t o connect to an isolated 71M6x01 isolated sensor (i.e., RMT_E = 1) , as
show n in Figure 3. The VA p in is typically connected to the phase voltage via r esi stor div iders. For this
configuration, the mu ltiplexer frame is also as shown in Figure 6 and tim e sl ot 2 is unused and ignored by
the CE, as the sampl es corr espondi ng to the rem ote sensor (IBP-IBN) do not pass through t he
m ultiplexer and ar e stor ed directly in CE RAM. The remote cur r ent sensor c hannel i s sampled during the
second half of t he multiplexer fr am e and its timing relationship to the VA volt age is precisely k nown so
that delay compensation can be proper ly applied.
The 71M6542F adds the ability to sam ple a second phase voltage (applied at the VB pin), whic h m ak es it
suitable f or met er s with two voltage and two current sensors, such as meter s implementing Equation 2 for
dual-phase operat ion (P = VA*IA+VB*IB). Figure 7 shows the multi plex er sequence when four inputs are
71M6541D/F/G and 71M6542F/G Dat a S heet
processed with l oc ally c onnec ted sensors, as sho wn in Figure 3. When usi ng one local and one r em ote
sensor (Figure 5), the multi plex er sequence is also as shown in Figure 7.
For both mu ltiplexer sequences shown in Figure 6 and Figure 7, the frame duration is 13 CK32 cycles
(where CK32 = 32768 Hz ) , therefore, the resulti ng sample rate is 32768 Hz / 13 = 2520.6 Hz .
Table 3 su mmarizes the various AFE input configu rations.
CK32
MUX STATE 00 1 2
MUX_DIV[3:0] = 3 Conversions
Settle
Multiplexer Frame
S
CROSS
MUX_SYNC
0S
11/5/2010
Fig. 2: IA VA IB
Fig. 3: IA VA Not Used
Fig. 5: IA VA VB
Figure 6: Stat es in a Multip lexer Frame (MUX_DIV[3:0] = 3)
CK32
MUX STATE 0123
MUX_DIV = 4 Conversions
Settle
Multiplexer Frame
S
CROSS
MUX_SYNC
0S
11/5/2010
Fig. 4: IA VA IB VB
Figure 7: Stat es in a Multip lexer Frame (MUX_DIV[3:0] = 4)
Table 3: ADC Input Configuration
Pin ADC
Channel
Required
Setting Comment
IAP ADC0 DIFFA_E = 1
Differential mode must be selected with DIFFA_E = 1 (I/O
R AM 0x21 0C[4]). The ADC result s are stored in CE RAM
location ADC0 (CE RAM 0 x0), and ADC1 (CE RAM 0x1) is not
disturbed.
IAN
ADC1
IBP ADC2
DIFFB_E = 1
or
RMT_E = 1
For locally connected sensors ( Figure 2 and Figure 4), the
diff erential input must be enabled by setti ng DIFFB_E (I/O
R AM 0x21 0C[5].
For the remote connect ed sensor (Figure 3 and Figure 5)
with a remote shunt sensor, RMT_E (I/O RAM 0x2709[3])
m ust be set.
In bot h cases , the ADC results are stored in RAM location
ADC2 (CE RAM 0x2 ), and ADC3 (CE RAM 0x3 ) is not
disturbed.
IBN
ADC3
VA ADC10 --
Single-ended m ode only . The ADC resul t is stor ed in RAM
location ADC10 (CE RAM 0 xA).
VB ADC9 --
Single-ended m ode only ( 71M 6542F only). The ADC result
is stored in RAM locati on ADC9 (C E R AM 0x9).
71M6541D/F/G and 71M6542F/G Dat a S heet
Multiplexer adv anc e, FIR initi ation and chopping of the ADC reference voltage (using t he internal CROSS
signal , see 2.2.7 V oltage Refer enc es) are controlled by the int ernal M UX_CTRL circuit. Additionally,
MUX_CTRL l aunc hes each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by
CK32, the 3276 8 Hz clock from the PLL bloc k . The behavior of the MUX_CTRL circuit is governed by:
• CHOP_E[1:0] (I/O RAM 0x2106 [3 :2])
• MUX_DIV[3:0] (I/O RAM 0x21 00[7:4])
• FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
• ADC_DIV (I/O RAM 0x220 0[5])
The durati on of each multiplexer state depends on the num ber of ADC samples processed by the FI R as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the
ri si ng edge of CK32, the 32-kHz clock.
It i s recomm ended t hat MUX_DIV[3:0] (I/O RAM 0x220 0[ 2:0]) b e set to zero while c hanging t he ADC
configur ati on. A lt ho ugh not required , it minimizes system transien ts tha t migh t be caused by momen tary
shorts between the AD C inputs , especially when changi ng the DIFFn_E control bits (I/O RAM 0x210C[5:4]).
After the c onfiguration bits are set, MUX_DIV[3:0] should be set t o the requir ed value.
Addi tionall y , t he ADC can be configured t o operate at ½ r ate (32768*75= 2.46MHz). In thi s mode, the
bias curr ent to the ADC am plifiers is reduced and ov er all system power is reduced. The ADC_DIV (I/O
R AM 0x22 00[5]) bit selects full speed or half speed. At half speed, if FIR_LEN[1:0] i s set to 01 (288),
each conversion r equir es 4 XTAL cy cl es, r esul ting in a 2520Hz sampl e r ate when MUX_DIV[3:0] = 3.
Note that in or der to work wit h these power-reducing settings, a c or r espondi ng CE c ode is requir ed.
The durati on of each time sl ot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Durati on (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * ( ADC_DIV+1)
Time_Slot_Durati on (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in CK32 cycle s is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Sl ot_Durati on * MUX_DIV[3:0]
The durati on of a multiplexer frame in CK_FIR c ycle s is:
M UX frame duration ( CK _FI R c ycles) =
[3-2*PLL_FAST + Time_Slot_Durati on * MUX_DIV] * ( 48+PLL_FAST*102)
The ADC co nversion seq uence is p r ogrammable through t he MUXx_SEL control fields (I/O RAM 0x2100
to 0x2105). As stated above, ther e are three ADC time sl ots in t he 71M 6541D/F/G and four ADC time
slots i n the 71M6542F/G, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression
MUXx_SEL[3:0] = n, ‘x’ refers to the multiplexer frame time slot number and n refers to the desired ADC input
number or ADC handle (i.e., ADC0 to ADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid
ADC handles in the 71M654x devices. For exa mple, if MUX0_SEL[3:0] = 0, then ADC0, corresponding to the
sample from the IAP-IAN input (configured as a differential input), is positioned in the multiplexer frame during
time slot 0. See Table 1 and Table 2 for the appropriate MUXx_SEL[3:0] sett ing s and ot h er set ti ng s
applica ble t o a par ti cular CE co de.
Note that when the r emot e sen s or interface is ena bled, an d even thou gh t he s ample s corre s ponding to
the remot e sens or cur rent ( IBP-IBN) do not p ass through the mult ipl exer , the MUX2_SEL[3:0] and
MUX3_SEL[3:0] cont rol fi elds m ust be writte n with a valid ADC ha ndle that is not bei ng used. Typically,
ADC1 is us ed for t his pu r pose (see Table 2). In this manne r , the ADC1 handle, whi ch is not used i n the
71M6541D/F/G or 71M6542F/G, is us ed a s a plac e holder in the mul tiplexer fr ame, in order t o gener ate
the correc t m ult ipl exer fram e sequ ence and the correct s ample rate. The r es ult i ng sam pl e dat a stor ed
in CE RAM 0x1 i s un defined and is ignored by the CE code. Mea nwhile, the digit al i s olat ion interface
takes c are of automat icall y sto r ing the samples for th e remot e interface c ur r ent (IBP-IBN) in CE RAM
0x2.
71M6541D/F/G and 71M6542F/G Dat a S heet
Delay c om pensation and ot her functions in t he CE code requir e the sett ings for MUX_DIV[3:0],
MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_D IV and PLL_FAST to be f ixed for a giv en CE code.
Refer to Table 1 and Table 2 for the settings that ar e applicable to t he 71M 6541D/F/G and
71M6542F/G.
Table 4 summarizes t he I/ O RAM registers used for c onfiguring the m ultiplexer, signals pins, and ADC.
Al l listed registe rs are 0 after r eset and wa k e fr om battery mode s , an d are readable and writable.
Table 4: Multipl exer and ADC Configuration Bits
Name Location Description
MUX0_SEL[3:0]
2105[3:0]
Selects the ADC input conver ted during time slot 0.
MUX1_SEL[3:0]
2105[7:4]
Selects the ADC input conv er ted during tim e slot 1.
MUX2_SEL[3:0]
2104[3:0]
Selects the ADC input converted duri ng time slot 2.
MUX3_SEL[3:0]
2104[7:4]
Selects the ADC input conv er ted during tim e slot 3.
MUX4_SEL[3:0]
2103[3:0]
Selects the ADC input conv er ted during tim e slot 4.
MUX5_SEL[3:0]
2103[7:4]
Selects the ADC input conv er ted during tim e slot 5.
MUX6_SEL[3:0]
2102[3:0]
Selects the ADC input conv er ted during tim e slot 6.
MUX7_SEL[3:0]
2102[7:0]
Selects the ADC input conv er ted during tim e slot 7.
MUX8_SEL[3:0]
2101[3:0]
Selects the ADC input conv er ted during tim e slot 8.
MUX9_SEL[3:0]
2101[7:0]
Selects the ADC input conv er ted during tim e slot 9.
MUX10_SEL[3:0]
2100[3:0]
Selects the ADC input conver ted during time slot 10.
ADC_DIV
2200[5]
Controls the rate of t he A DC and FI R cl oc k s.
MUX_DIV[3:0]
2100[7:4]
The number of ADC time slots in each multiplexer frame (maximum = 11).
PLL_FAST
2200[4]
Controls the speed of the PLL and MCK.
FIR_LEN[1:0]
210C[1]
Determ ines the num ber of ADC cycles i n the ADC decima tion FIR filter.
DIFFA_E
210C[4]
Enables the differential c onfigurat ion for analog input pins IAP-IAN.
DIFFB_E
210C[5]
Enables the differential c onfigurat ion for analog input pins IBP-IBN.
RMT_E 2709[3]
Enabl es the r em ote sensor int erface transforming pins IBP-IBN into a
digital bal anc ed differ ential pair f or communic ations wi th the 71M6x 01
sensor.
PRE_E
2704[5]
Enabl es the 8x pr e-amplifier.
Refer to Table 76 start ing on page 111 f or more complet e detail s about these I/O RAM locations.
2.2.3 Delay Compensation
When measuring the ener gy of a phase (i .e., Wh and VARh) i n a servic e, t he v oltage and curr ent f or that
phase must be sampled at t he same instant . Otherwise , the phase diff er enc e, Ф, introduces errors.
o
delay
o
delay ft
T
t360360 ⋅⋅=⋅=
φ
Where f is the frequency of t he input signal, T = 1 /f and tdelay is the sampli ng delay between current and
voltage.
Traditional ly, sampling is accompli shed by using two A/D converters per phase (one for voltage and the
other one for cur r ent) c ontrolled t o sample sim ultaneously. Maxim’s Teridian Single-Converter
Technology, however , exploit s the 32-bit signal proc essing capabili ty of its CE to implement “c onstant
delay ” all-pass filters. The all-pass filter corrects for the conversion time difference betw een the voltage
and the cor r espondi ng c ur r ent samples that are obt ained with a single multiplexed A/D conver ter.
The “c onstant del ay ” all -pass fi lter provides a broad-band delay 360o – θ, which is precisely m atched to
the dif ference in sample time between the voltage and the current of a given phase. This digital filter
does not affect the amplitude of the signal, but prov ides a precisely cont r olled phase response.
The rec ommended ADC multiplexer sequence sam ples the curr ent fi r st, immediately foll owed by
sampling of the cor r espondi ng phase vol tage, thus the voltage is delayed by a phase angle Ф relative to
71M6541D/F/G and 71M6542F/G Dat a S heet
the cur r ent. The delay c om pensation implem ented in the CE ali gns the v oltage samples with t heir
correspondi ng c ur r ent samples by fir st delay ing the current samples by one f ull sampl e interv al (i .e.,
360o), then routi ng the voltage samples through t he all-pass filter, thus delay ing the volt age samples by
360o - θ, resulting in t he residual phase error between the cur r ent and its corr espondi ng volt age of θ – Ф.
The resi dual phase error is negligible, and is typi c ally less than ±1. 5 mil li-degrees at 100Hz, thus it does
not contribut e to errors in the energy m easurements.
When usi ng r em ote sensors, the CE perform s the same delay c om pensation descri bed above to align
each voltage sample with its correspondi ng c ur r ent sample. Even though the remot e c urrent samples do
not pass through the 71M 654x multiple xer, their timing relationship to their corresponding voltages is
fixed and preci sel y known, provided that t he MUXn_SEL[3:0] slot assi gnment fields are programm ed as
shown in Table 1 and Table 2.
2.2.4 ADC Pre -Amplifier
The ADC pr e-amplifier is a low-noise differential amplifier wit h a fixed gain of 8 available only on the IAP-
IAN sensor input pins. A gain of 8 is enabl ed by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled,
the supply c ur r ent of the pre-am plifier is <10 nA and the gain is unity. With proper setti ngs of the PRE_E
and DIFFA_E (I/O RAM 0x 210C[4]) bits, the pr e-am pl i fier c an be u sed wh et he r dif f erential mode is
select ed or not. For best performance, the differential mode is recommended. In order to save power, the
bias curre nt of the pre -ampli fier and ADC i s adjusted acco rding to the ADC_DIV control bit (I/O RAM
0x2200[5]).
2.2.5 A/D Converter ( ADC)
A single 2nd order delta-sigma A /D converter di gitizes the voltage and current inputs to the device. The
resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 1, I/O RAM 0x21 0C[2:1]), or 22 bits
(FIR_LEN[1:0] = 2). The A DC is clocked by CKADC.
Initiation of each ADC convers ion is con tro lled by MUX_CTRL internal circuit as described above. At the
end of each ADC conv er si on, the FIR filt er output data is stor ed int o the CE RAM locati on determined by
the multiplexer selection. FIR data is stored LSB justified, but shifted l eft 9 bits.
2.2.6 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiple xer.
The purpose of the FIR fil ter is to dec imate the ADC output to the desired resol ution. At the end of eac h
ADC conversi on, t he output data is stored i nto t he fixed CE RAM l oc ation determi ned by the multipl ex er
selection as shown in Table 1 and Table 2.
2.2.7 Voltage References
A bandgap c ircu it provides the re ferenc e voltage to the ADC. The amplifier within the reference is chopper
stabilized, i.e., the chopper ci r c uit can be enabled or disabled by t he M P U usi ng the I/O RAM control field
CHOP_E[1:0] ( I/O RA M 0x2106 [3 :2]). The two bits in the CHOP_E[1:0] field enable the MPU to operate the
chopper c ircuit in regular or i nvert ed oper ati on, or in toggl in g mode s (recommended). When the
cho pper circui t i s toggled in between multiplexer cycles, dc offsets on VREF are automatically be
av er aged out, therefore the chopper ci r c uit should always be configured for one of the toggling modes.
Since the VREF band-gap a mp lifier is cho ppe r-stabilized, the dc offset v oltage, whi c h is the most
significant long-term drift mechanism in the voltage references (VREF), is automatical ly rem ov ed by the
chopper circ uit. B oth the 71M654x and the 71M6x01 feature c hopper c ircuits for their respective VREF
v oltage ref er enc e.
The general topol ogy of a chopped am plifi er i s shown in Figure 8. The CROSS signal is an i nternal on-
chi p si gnal and is not accessibl e on any pin or register .
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 8: General Topology of a Chopped Amplifier
It is as s umed that an offset voltage V off appears at the positive am plif ier inp ut. W ith all switches, as
controlled by CROSS (an internal signal) , in the A position, the out put voltage is:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
With all swi tches set to the B posi tion by applying the inverted CRO S S signal, the output voltage is:
Voutn – Voutp = G (Vinn – Vi np + Voff ) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS is toggled, e.g., after eac h m ultiplexer cycle, the offset alternat ely appears on t he
output as posit ive and negative, whic h r esults i n the offset effectively being eliminat ed, regardless of its
polarity or magnitude.
When CROSS i s hi gh, the connection o f the a mp lifier input de vices is re versed. T his pr eserves the overall
polarity of that amplifier gain; it inve rts its inp u t o ffse t. By alternately re versing the connection, the amplifier’s
offset is averaged to zero. This rem ov es the most significant long-term drift mechani sm in the voltage
reference. The CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field controls th e beh avio r of CROSS . The
CROSS s ignal reverses the amplifi er connec t ion in the voltage re ferenc e in orde r to negate th e e ffec ts o f its
offset. On th e firs t CK3 2 rising edge after the last multi plex er state of i ts sequence, the m ultiplex er wait s
one additi onal CK 32 cycle before beginning a new frame. At the beginning of this cycl e, t he v alue of
CROSS is updated ac c or ding to the CHOP_E[1:0] field. The extra CK32 cycle allows t ime for the
cho pped VRE F to settle. During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates
a pass through the CE program sequence. The beginning of the sequence is the serial readout of the f our
RTM words.
CHOP_E[1:0] has four states: posit ive, rever se, and two toggle states. In the positive state, CHOP_E[1:0]
= 01, CRO S S is held low . In the reverse state, CHOP_E[1:0] = 10, CROSS is held high.
Figure 9: CROSS Signal with CHOP_E = 00
Figure 9 shows CROS S ov er two accumulation interval s when CHOP_E[1:0] = 00: At the end of the
first interval, CROSS is hi gh, at t he end of the second interval, CROSS is low. O per a t i o n wi th
CHOP_E[1:0] = 00 does not require cont rol of t he choppi ng mec hanism by the MPU .
In t he second t oggle state, CHOP_E[1:0] = 11, CRO S S does not toggle at the end of the last multiple xer
cycle in an accumulation interv al.
A second, low-power voltage ref er enc e is used in t he LCD syst em and for the com par ators that support
transi ti ons to and from the bat tery modes.
G
-
+V
inp
V
outp
V
outn
V
inn
CROSS
A
B
A
B
A
B
A
B
71M6541D/F/G and 71M6542F/G Dat a S heet
2.2.8 71M6x01 Isola te d Sensor Interface (Remote Sensor Interface)
2.2.8.1 General Description
Non-isol ati ng sensors, such as shunt resistors, can be connec ted to the inputs of the 71M654x via a
combination of a pulse transf ormer and a 71M6x01 IC (a top-level bloc k diagr am of t his sensor i nterfac e
is shown in Figure 36). The 71M6x01 receives power directly from the 71M654x via a pulse transformer
and does not require a dedicated power supply circuit. The 71M6x01 establishes 2-way c om munic ation
with t he 71M654x, suppl yi ng c ur r ent samples and auxiliary inf ormati on such as sensor temperat ur e v ia a
serial data str eam .
One 71M6x01 Isolate d S ensor can b e supported by the 71M6541D/F/G and 71M6542F/G. When
remote interface IBP-IBN is enabled, the two analog current inputs pins IBP and IBN becom e a digital
balanc ed differ ential interface to the r em ote sensor. See Table 3 f or details.
Each 71M6x01 Isol ated Sensor consists of the following buil ding bloc k s:
• Power supply for power pulses received fr om the 71M654x
• Digit al c ommunications interface
• Shunt signal pre-amplifier
• Delta-Sigma ADC Converter with precision bandgap referenc e ( c hopping amplif ier)
• Temperature sensor
• Fuse system contai ning par t-specifi c i nformation
Duri ng an or dinary multiplexer cycle, t he 71M654x internally determines whi c h other channels are
enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4] ). At the same tim e, it decimates the modulator output
from the 71M6x01 Isolated Sensors. E ac h r esul t is wri tt en to CE RAM during one of its CE acc ess time
slots. S ee Table 3 for the CE RAM locations of t he sampled signals.
2.2.8.2 Communi cat io n b etween 71M654x and 71M6x01 Isolated Sensor
The ADC of the 71M6x01 derives its timing from the p ower puls es generated by the 71M654x and as a
res u lt , operates its ADC slaved to the frequency of the power pulses. The generation of power puls es, as
well as the communication protocol between the 71M654x and 71M6x01 Isolated Sensor is automatic and
transparent to the user. Details are not covered in this data sheet.
2.2.8.3 Control of the 71M6x01 Isolated Sensor
The 71M654x can read or write certain types of information from each 71M6x01 isolated sensor.
The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read
transaction from one of the 71M6x01 devices, the MPU firs t writes the TMUXRn[2:0] field ( where n = 2, 4, 6,
loc ated at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes
RCMD[4:0] (SFR 0xFC[ 4:0]) with the desired command and phase select ion. When the RCMD[4:2] bits
have c leare d to zer o, the transac tion has bee n completed and th e reque s ted dat a is availabl e in
RMT_RD[15:0] (I/O RAM 0x260 2[ 7:0] i s the MSB and 0x2603[7:0] is the LSB). The read parity error bit,
PERR_RD (SFR 0xFC[6]) is also updated during the trans action. If the MPU writes to RCMD[4:0] before a
previously initi ated read transaction is completed, the command is ignored. T her efore, the MPU must wait
for RCMD[4:2]=0 before pr oc eeding to issue t he next remot e sensor read command.
The RCMD[4:0] field is divided into tw o sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as
shown in Table 5.
Table 5. RCMD[4:0] Bits
Command
RCMD[4:2]
Phase S electo r
RCMD[1:0]
Associated TMUXRn
Contr ol Field
000
Invalid
00
Invalid
---
001
Command 1
01
IBP-IBN
TMUXRB [2:0]
100
Reserved
101
Invalid
110
Reserved
71M6541D/F/G and 71M6542F/G Dat a S heet
111
Reserved
Notes:
1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relev ant f or normal
operation. T hese are RCMD[4:2] = 001 and 010. Codes 000 and 101
are i nv alid and wi ll be ignored if used. The remaining codes are
reserved and m ust not be used.
2. F or the RCMD[1:0] cont r ol field, codes 01, 10 and 11 are valid and 00
is i nv alid and must not be used.
Table 6 shows t he allowable combinati ons of v alues in RCMD[4:2] and TMUXRn[2:0], and t he
correspondi ng data ty pe and format sent back by the 71M6x01 isolated sensor and how the data i s stored
in RMT_RD[15:8] and RMT_RD[7:0]. The MP U select s which of the three phases is read by asserting the
proper code in the RCMD[1:0] field, as shown in Table 5.
Table 6: Remote Interf ace Read Co mmand s
RCMD[4:2] TMUXRn[2:0] Read Op era tion
RMT_RD
[15:8]
RMT_RD
[7:0]
001 00X
TRIMT[7:0]
(trim fuse for all 71M6x01)
TRIMT[7]=RMT_RD[8] TRIMT[6:0]=RMT_RD[7:1]
010 00X
STEMP[10:0]
(sensed 71M6x01 temperature)
STEMP[10:8]=RMT_RD[10:8]
(RMT_RD[15:11] a re si gn ext en ded)
STEMP[7:0]
010 01X
VSENSE[7:0]
(sen sed 71M6x01 s upply voltage)
All zeros VSENSE[7:0]
010 10X
VERSION[7:0]
(chip version)
VERSION[7:0] All zeros
Notes:
1. TRIMT[7:0] is the VREF trim value for all 71M6x01 devices. Not e that t he TRIMT[7:0] 8-bit v alue i s f ormed
by RMT_RD[8] and RMT_RD[7:1]. See the 7 1M6xx x Dat a shee t f or more information on TRIMT[7:0]
2. See the 71M6 x xx Data Sheet for the equation to calculate temperature from the STEMP[7:0] value read from
the 71M6x0 1.
3. See the 71M6 x xx Data Sheet for the equation to calculate temperature from the VSENSE[7:0] value read from
the 71M6x0 1.
With hardware and trim-related informati on on each c onnected 71M6x01 I sol ated Sensor available to t he
71M6541D/F/G, the MPU can implement temperature compensation of the energy measurement based on
the individual temperat ur e c har ac teristics of the 71M6x01 Isolat ed S ensor. S ee 4.7 Metrology
Temper ature Compensation on page 97 for detail s.
Table 7 shows all I/O RAM regi sters used f or c ontrol of the ext er nal 71M 6x 01 Isolated S ensors. See the
71M6xxx Data Sheet for addi tional details.
Table 7: I/O RAM Con trol Bits for Isolated Sensor
Name Address
RST
Default
WAKE
Default
R/W Description
RCMD[4:0] SFR
FC[4:0] 0 0 R/W
When the MPU writes a non -zero value to RCMD,
the 71M654x issues a command to the cor-
respondi ng isol ated sensor select ed wit h
RCMD[1:0]. When the command is co mplete, the
71M654x clears RCMD[4:2]. The c ommand code
itself is in RCMD[4:2].
PERR_RD
PERR_WR SFR FC[6]
SFR FC[5]
0 0 R/W
The 71M654x sets t hese bi ts to indicate that a
pari ty error on the i sol ated sensor has been de-
tecte d. Once set, the bits are remember ed until
they ar e cl ear ed by the MP U.
CHOPR[1:0] 2709[7:6] 00 00 R/W
The CHOP settings for the isolated sensors.
00 – Auto chop. Change every multiplexer fra me.
01 – Positive
10 – Negative
11 – Same as 00
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Address
RST
Default
WAKE
Default
R/W Description
TMUXRB[2:0]
270A[2:0]
000
000
R/W
The T M UX bits for control of the is olated sensor.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0 0 R The read buffer for 71M6x01 read operations.
RFLY_DIS 210C[3] 0 0 R/W
Controls how the 71M654x drives the 71M6x01
power pul se. When set, the power pulse i s driven
high and low. When cleared, it is driven high
followed by an open cir c uit flyback interval.
RMTB_E 2709[3] 0 0 R/W
Enabl es the isolated remote sensor interface and
re-configures pins IBP-IBN as a balanced pair
digital remote interface.
Refer to Table 76 start ing on page 111 f or more complet e detail s about these I/O RAM locations.
2.3 Digital Computation Engine (CE)
Th e CE , a de dicate d 32-bit signal proce s s or, performs the precision computat ions necessary to ac curately
m easure energy . The CE calc ulations and processes inc lude:
• Multiplicati on of each current sample with its associated v oltage sampl e to obt ain the energy per
sample (when multipli ed with t he constant sampl e time).
• Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the mult iplexing scheme).
• 90° phase shifter (for VAR calc ulations).
• Pulse generat ion.
• Monitoring of the input signal f r equenc y (for frequenc y and phase i nformati on) .
• Monitoring of the input signal amplitude (for sag detec tion).
• Scali ng of the processed samples based on cali br ation coeffic ient s.
• Scali ng of samples based on temperat ur e compensation i nformation.
2.3.1 CE Pro gram Me mor y
The CE program resides in flash memory. Co mmon access to flash me mory by the CE and MPU is controlled
by a memor y share ci r c uit. Each CE instr uc tion word is two bytes long. Allocat ed flash space for the CE
program cannot exc eed 4096 16-bi t words (8 KB). The CE program c ounter begins a pass thr ough the
CE code each time multiplexer state 0 begins. The code pass ends when a HA LT instruction is executed.
For pr oper oper ation, the code pass m ust be c om pleted before the multi plex er c ycle ends.
The CE pr ogr am must begi n on a 1 KB boundary of the fl ash address. The I/O RAM con trol field
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) def i nes whic h 1 KB boundary contains the CE code. Thu s, the first
CE i nstruction is l oc ated at 1024*CE_LCTN[5:0].
2.3.2 CE Data Memory
Th e CE and MPU share d ata m emory ( RAM ) . Common acces s to XRA M by the CE and MPU is con trolled
by a memor y share ci r c uit. The CE can access up to 3 KB of the 3 KB data RAM (XRAM), i.e., from RAM
address 0x 0000 to 0x0C00.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.
The MPU reads and writes the XRAM shared between the CE and M P U as the primary m eans of data
communication between the t wo processors.
Table 3 shows t he CE addr esses in XRAM alloc ated t o analog input s from the AFE.
The CE is ai ded by support hardware t o facilit ate implem entat ion of equati ons, pulse count ers, and
accumulators. This hardware is controlled through the I/O RAM con t r ol field EQU[2:0], equation assist
(I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[ 6] ), bit DIO_PW, pulse count assist (I/O RAM
0x2457[7]), and SUM_SAMPS[12:0], accumulation assist (I/O RAM 0x2107[4:0] and 0x2108[7:0]).
71M6541D/F/G and 71M6542F/G Dat a S heet
SUM_SAMPS[12:0] supports an accumulation scheme where the increment a l energy valu es from up to
SUM_SAMPS[12:0] multiplexer frames are added up over one accumulation int erval. The integration time
for each energy out put is, for example, SUM_SAMPS[12:0]/2520. 6 ( with MUX_DIV[3:0] = 011, I/O RAM
0x2100[7:4] and FIR_LEN[1:0] = 10, I/O RAM 0x210C[2:1]). CE hardware issues the XFER_BUSY interrupt
when the accumulation is com plete.
2.3.3 CE Communication with the MPU
The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY , XPULSE, YPULSE, WPULSE and
VPULSE. These are connected t o the MPU inter r upt service. CE_BUSY indicates that the CE is actively
processi ng data. This signal occurs once e very multiplexer frame. XFER_BUSY indicates t hat t he CE is
updat ing to th e ou t pu t region of th e CE RA M , which occ urs whenever an accumulation cycle has been
completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction.
XPULSE, YPULSE, VPULSE and WP ULS E c an be configur ed to interrupt the MP U and indic ate sag
failures, zero crossings of the mains voltage, or other signifi c ant event s. Additionally, t hese signals can
be connect ed direc tly to DIO pins to prov ide dir ec t out puts for the CE. I nterrupt s associat ed with these
signal s al way s occur on the leadi ng edge ( see “Ex ternal” interrupt source No. 2 in Figure 16).
2.3.4 Meter Equations
The 71M6541D/F/G and 71M6542F/G provide hardware assistance to the CE in order to support various
meter equations. Th is assis t an ce is contro lled t hr ou gh I/O R A M register EQU[2:0] (equation assist). The
Compute Engine (CE ) firmw are for indus t r ial con figura t io ns can implement the equa t ions lis ted in Table 8.
EQU[2:0] specifies the equation to be used based on the meter c onfigurati on and on the number of
phases used for metering.
Table 8: Inpu t s Selected in Multiplexer Cycles
EQU Description
Wh and VARh formula
Recommended
Multiplexer
Sequence
Element 0 Elemen t 1 Element 2
0 1-elem ent, 2-W, 1 φ with
neutral cur r ent sense
VA ∙ IA VA ∙ IB1 N/A I A VA IB1
1
1-element, 3-W, 1
φ
VA(IA-IB)/2
N/A
N/A
IA VA IB
2 †
2-elemen t, 3-W, 3
φ
Delta
VA ∙ IA
VB ∙ IB
N/A
IA VA IB VB
Note:
1. O ptionall y , I B may be used to m easure neut r al c ur r ent
† 71M6542F/G only
2.3.5 Real-Time Monitor (RTM)
The CE c ontains a Real-Time Monitor (RTM), which c an be programmed to monitor four selectable
XRAM loc ations at full sample rat e. The four monitor ed loc ations, as sel ec ted by t he I/O RAM register s
RTM0[9:8], R TM0[ 7:0], R TM1[9:8], RTM1[7:0] , R TM2[ 9:8], R TM2[7:0], RTM3[9:8] , and RTM3[7:0], are
seriall y output to the TMUXOUT pin via t he digital output multiplex er at the beginning of eac h CE code
pas s . The RTM can b e enabled and disabled with c o ntr ol bi t RTM_E (I/O RA M 0x 2106[1]). The RTM
output is clocked by CKTE ST. Eac h RTM word is clocked out in 35 CKCE cycles (1 CKCE cycle is
equivalent to 203 ns) and contains a leading fl ag bit. See Figure 10 for the RTM output format. RTM is
low when not in use.
Figure 11 summari z es the timing relati onshi ps between t he input MUX states, the CE _B USY signal, and
the RT M serial output str eam . In this example, MUX_DIV[3:0] = 4 ( I/O RAM 0x2100 [7: 4]) and
FIR_LEN[1:0] = 10 ( I/O RAM 0x210C [1]), (384), resul ting in 4 ADC conversions. A n ADC conver si on
always consumes an int eger num ber of CK32 cl oc k s. Followed by the conversions is a singl e CK 32
cycle.
Figure 11 also shows that the RTM serial data stream begins tr ansmitti ng at t he beginning of state S .
RTM, consi sting of 140 CK cycl es, always f inishes before the next CE c ode pass st ar ts.
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 10: R TM Timing
CK32
MUX STATE 0
MUX_DIV Convers i ons, MUX_DIV=4 is shown Settle
ADC MUX Frame
ADC EXECUTION
S
MUX_SYNC
S
CE_EXECUTION
RTM 140
MAX CK COUNT
0450
150
900 1350 1800
ADC0 ADC1 ADC2 ADC3
CK COUNT = CE_CYCLES + 1CK for each ADC tran sfer
NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNT S.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY SUM_SAMPS CODE PASSES.
CE_BUSY
XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
ADC TIMING
CE TIMING
RTM TIMING
1 2 3
Figure 11: T iming relation shi p b etween ADC MUX, CE, and RTM Serial Transfer
CKTEST
RTM
FLAG
RTM DATA0 (32 bits)
LSB
SIGN
LSB
SIGN
RTM DATA1 (32 bits)
LSB
LSB
SIGN
SIGN
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31
FLAG FLAG FLAG
MUX_STATE S
MUX_SYNC
CK32
71M6541D/F/G and 71M6542F/G Dat a S heet
2.3.6 Pulse Generators
The 71M6541D/F/G and 71M6542F/G provide four pulse generators, VPULSE, WPULSE, XPULSE and
YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generat or s. T he pulse
generator s can be used to output CE st atus indi c ators, SAG for example, to DIO pins. All pulses can be
configured to generate i nterr upts to the MPU.
The polarit y of the pulses may be i nverted with control bit PLS_INV (I/O RAM 0x210C[0] ). When t his bit is
set, the pulses are active high, rather than the more usual active low. PLS_INV inverts all four pulse
outputs.
The f unc tion of each pul se generat or is determi ned by the CE code and t he MPU code m ust c onfigure the
correspondi ng pulse output s in agr eement with the CE code. For example, standard CE c ode pr oduc es a
mains zero-crossing pulse on XPULSE and a S A G pulse on YPULSE.
A comm on use of the zero-crossing pulses is to generate interrupt in order to drive real-time clock software
in plac es where the mai ns fr equenc y is sufficiently accurate to do so and al so to adjust for crystal aging.
A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about
to f ail, so that the MPU code can stor e ac c um ulated energy and other data t o E E P ROM befor e the
V3P3SYS supply voltage actually dr ops.
2.3.6.1 XPULSE and YPULSE
Pul ses generated by the CE may be ex ported to the XPULSE and YPULS E pul se output pins. Pins
SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE
outpu ts can be up dated once on each pass of the CE cod e.
See 5.3 CE Interface Description on page 125 for details.
2.3.6.2 VPULSE and WPULSE
Referring to Figure 12, during each CE code pass the ha r dware store s exported WPULS E and VPULSE sign
bits i n an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the
VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them
over the multiplexer frame. As seen in Figure 12, the FIFO is reset at t he beginning of each multiplex er
frame. As also seen in Figure 12, the I/O RAM register PLS_INTERVAL[ 7:0] (I/O RAM 0x210B[7:0])
controls the d elay to th e first puls e up date and the interval between s ubsequ ent updates. The LSB of
the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if
PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in
Table 76.) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.
The MUX fr am e dur ation in units of CK_FIR cloc k cycles is given by:
If PLL_FAST=1:
MU X frame d uration i n CK_F IR cyc les = [ 1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)]
If PLL_FAST=0:
MU X frame d uration in CK_FIR cycl es = [3 + 3* (FIR_LEN+1) * ( ADC_DIV+1 ) * (MUX_DIV) ] * [48 / (ADC_DIV+1)]
PLS_INTERVAL[7:0] in units of C K_ FIR clo ck cycles is calculated b y:
PLS_INTERVAL[7:0] = floor (Mux frame dur ation i n CK_F IR cyc les / CE pulse u pd ates per Mux frame / 4 )
Si nc e the FIFO r esets at the beginni ng of each multiplexer fr am e, t he user must specify
PLS_INTERVAL[7:0] so that all of the possible pulse updates occurr ing in one CE ex ec ution are out put
before the multiplexer frame completes. For instance, the 71M654x CE code outputs six updat es per
multiplexer interval, and if the multiplexer interval is 1950 CK_FIR clock cycl es l ong, t he ideal value for
the interval is 1950/6/4 = 81.25. How ever, if PLS_INTERVAL[7:0] = 82, the sixth out put occ urs too late and
would be lost. In this case, the proper v alue for PLS_INTERVAL[7:0] is 81 (i. e., r ound down the resul t).
Since one LSB of PLS_INTERVAL[7:0] is equ al to 4 CK_FIR c lo ck cy cles, the p ulse t ime interval TI i n units of
CK_F IR clo ck cyc le s is:
TI = 4*PLS_INTERVAL[7:0]
71M6541D/F/G and 71M6542F/G Dat a S heet
If the FIFO is e nab led ( i.e., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximum pulse width feature
in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative
puls es ( i.e., low level p u lses, designed t o s ink current through an LE D). PLS_MAXWIDTH[7:0] determines the
maximu m negative p ul se wi d th TMAX in uni t s of CK_F IR cl oc k cy c le s ba se d o n th e p ul s e interv al TI
acc ordi ng to the formula:
TMAX = (2 * PLS_MAXWIDTH[7:0] + 1) * TI
If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse width chec k ing is performed, and the pulses
default to 50% dut y cycl e. TMAX is typic ally programmed to 10 ms., which works well with most cali br ation
systems.
The polarit y of the pulses may be i nverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When
PLS_INV is set, the pulses are ac tive high. The def ault value f or PLS_INV is zero, which selec ts active low
pulses.
The WPULSE and VPULSE pulse generator outputs are avail able on pins SEG DIO 0/W P ULSE and
SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53
(see OPT_TXE[1:0], I/O RAM 0x245 6[ 3:2] f or details).
Figure 12. Pu ls e Ge ne r a t or FI FO Timing
2.3.7 CE Functional Overview
The 71M654x pr ov ides an ADC and multi plex er to sampl e the analog currents and voltages as seen i n
Figure 2 and Figure 3. The VA and VB v oltage sensors are formed by resistive volt age dividers di r ectly
connect ed to the 71M 654x dev ic e, and t her efore always use the ADC and multiplexer facilities in t he
71M654x device. Current sensors, however, m ay be connected directly to the 71M654x or r em otely
connected through an isolated 71M6x01 device. The remote 71M6x01 sensor ha s i ts own separat e A DC
and v oltage ref er enc e. When a cur r ent sensor is connected v ia a 71M6 x01 isolated sensor, t he 71M 654x
plac es the sampl e data rec eiv ed digitall y ov er the isol ation interface (v ia the pulse transformer ) i n the
appropriate CE RAM location, as shown in Figure 3. The ADCs (i.e., ADC in the 71M 654x and the ADC in
the 71M6x01) process t heir cor r espondi ng sen sor channels provi ding one sampl e per channel per
multiplexer cycle.
Figure 14 (71M6541D/F/G) and Figure 15 (71M6542F/G) show the sam pling sequence when both cur r ent
sensors (IA and IB) are connected directl y to the 71M6541D/F/G as seen i n Figure 2. However , when the
CK32
MUX_DIV Conversions (MUX_DIV=4 is s hown) Settle
ADC MUX Frame
MUX_SYNC 150
WPULSE
S
0
S
1
S
2
S
3
S
4
S
5
CE CODE
RST
W_FIFO
S
0
S
1
S
2
S
3
S
4
S
5
S
0
S
1
S
2
S
3
S
4
S
5
4*PLS_INTERVAL
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.
71M6541D/F/G and 71M6542F/G Dat a S heet
IB c hannel is a 71M6x01 isolated sensor, the sample data does not pass through t he 71M 6541D/F/G
m ultiplexer, as seen in Figure 3. In this case, the sample is taken duri ng the second half of the multiplex er
cycle and the data is di r ectly stor ed in the corr espondi ng CE RA M l oc ation as indicat ed in Figure 3. The
timing relationship bet ween the remote current sensor c hannel and its corr espondi ng voltage i s precisel y
defined so that delay c om pensation can be pr operl y applied by the CE.
Referring to Figure 15, the 71M6542F/G features an additi onal voltage input (VB) permitting the
im plem entation of a t wo-phase met er . As wit h VA, t he VB voltage divider is directly connected t o the
71M6542F/G and uses the ADC and multiplex er faci lities in t he 71M6542F/G. MUX_DIV[3:0] = 4
configures the m ultipl ex er to pr ov ide an additional time slot to accommodat e the additional VB voltage
sample. As with t he 71M6541D/F/G, IA samples are obtai ned from a current sensor that is directly
connect ed to the 71M6542F/G, whil e IB samples may be obtained from a di r ec tly connected CT or a
remotely connected shunt using a 71M6x01 isolated device as seen in Figure 2 and Figure 3.
The number o f samp les pro ces s ed dur ing one ac cu mu lation c yc le is con tro lled by the I/ O R AM regis ter
SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0 ]). The integration time for each energy output is:
SUM_SAMPS / 2520.6, where 2520.6 is the sam ple r ate in Hz
Fo r example, SUM_SAMPS = 2100 establi shes 2100 sa mples per acc um ulation cycle, which has a
duration of 833 ms. After an accum ulation cycle is completed, the XFER_B US Y i nterr upt signals to t he
MPU t hat acc um ulated data ar e availabl e.
The end of each multiplexer c y c le is sig naled to the MPU by th e CE_BUSY interrupt. At the en d of e ach
multiplexer cycle, status information, such as sag data and the digitized input signal, is a vailable to the MPU.
Figure 13 shows the accum ulati on interval resul ting from SUM_SAMPS = 2100, consi sting of 2100
samples of 397 µs each, followed by the XFER_BUSY interr upt. The sampli ng in this ex am ple is applied
to a 50 Hz signal . There is no correlati on between the line si gnal frequency and the choice of
SUM_SAMPS. Furthermor e, sam pling does not have to st ar t when the line volt age crosses the zero line,
and the length of t he accumulati on interval need not be an integer multi ple of the signal cycles.
Figure 13: Accumulation Interval
XFER_BUSY
Interrupt to MPU
20ms
833ms
71M6541D/F/G and 71M6542F/G Dat a S heet
MUX STATE
CK32
(32768 Hz) 0 1 2
MUX_DIV[3:0] = 3 Conversions Settle
Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz)
SS
IA
VA
IB
30.5
µs
122.07 µs 122.07 µs 122.07 µs
Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3)
MUX STATE
CK32
(32768 Hz) 0 31 2
MUX_DIV[3:0] = 4 Conversions Settle
Multiplexer Frame (13 x 30.518 µs = 396 µs à2520Hz)
S
S
IA
VA
IB
30.5 µs
91.5 µs 91.5 µs 91.5 µs 91.5 µs
VB
Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4)
71M6541D/F/G and 71M6542F/G Dat a S heet
2.4 80515 MPU Core
The 71M6541D/F/G and 71M6542F/G include an 80515 MPU (8-bit, 8051-c om patibl e) that proc esses
most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS.
The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and
execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte
instructions ar e perform ed i n a si n gl e machine cycle (MPU clock c ycle). This leads to an 8x average
performance improvement (i n term s of MIPS) ov er the Int el 8051 devic e r unning at the same cloc k
frequency.
Table 9 shows t he CK M P U frequenc y as a func tion of the MCK clock (19.6608 M Hz ) div ided by the MPU
clock divider which is set in the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]). Actual processor
cl oc ki ng speed can be adjusted to the total processing demand of the application (metering calculati ons,
AMR management, me mory management, LCD driver management and I/O management) using
MPU_DIV[2:0], as shown in Table 9.
Table 9: CKMP U Clock Frequ enci es
MPU_DIV [2:0]
CKMPU F requ ency
000
4.9152 MHz
001
2.4576 MHz
010
1.2288 MHz
011
614.4 kHz
100
307.2 kHz
101
110
111
Typical measurem ent and metering f unc tions based on the resul ts provided by the internal 32-bit compute
engine (C E ) are avai lable for the MPU as part of the Teridian st andard library. T e ri di a n pr ovide s
demonst r ati on s ource code to help reduce the desi gn cycle.
2.4.1 Memory Organization and Addre ssing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
organ ization in the 80515 is s imila r to that o f the industry standard 8051. There are three me mory areas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM). Table 10 shows the memory map.
Program Memory
The 80515 can addr es s up to 64 K B of progr am memory space (0x0000 to 0xFFFF). Program memory is
read when the M P U fetches instruc tions or perform s a MOVC operation.
After reset, t he MPU starts program exec ution f r om pr ogram mem or y loc ation 0x0000. The lower part of
th e pro gram memory inc ludes reset a nd i nt errupt vectors. The inter rupt vectors are s pace d at 8 -byte
intervals, starting fro m 0x0003.
MPU Ext ernal Data Memory (XRAM)
Both internal and external mem or y is physic ally located on the 71M654x device. The external memory
referr ed in this documentation is only exter nal to the 80515 MPU c or e.
3 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, l eav ing 2 KB f or the MPU. Different versi ons of the CE c ode use varying am ounts. Consult the
documentation for the specif ic c ode v er si on being used for the exac t limit.
If the MPU overwrites t he CE’s working RAM , the CE ’s output may be corrupted. If t he CE is
disabled, the fi r st 0x 40 bytes of RA M are still unusable while MUX_DIV[3:0] ≠ 0 because the
71M654x ADC writes to t hese l oc ations. Setting MUX_DIV[3:0] = 0 di sabl es the A DC output
preventing the CE from writi ng the fi r st 0x 40 by tes of RAM .
In addition, MUXn_SEL[3:0] val ues must be writt en only after writing MUX_DIV[3:0].
71M6541D/F/G and 71M6542F/G Dat a S heet
The 80515 writes int o exter nal dat a memory when the MPU exec utes a MO V X @Ri,A or MOVX
@DP TR, A instr uc tion. The MPU reads exter nal data memory by exec uting a MOVX A,@ Ri or MOV X
A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes f or the MOV X A,@ Ri instr uc tion).
Internal and External Memory Map
Table 10 shows the address, t y pe, use and si z e of the various memory components.
Table 10: M emory Map
Address
(hex)
Memory
Technology
Memory
Type
Name Typical Usage Memory Size
(bytes)
0000-7FFF Flash Memory Non-volatile Pro gra m memory
for MPU and CE
MPU Pr ogr am and
non-v olatil e data
64/32 KB †
CE program ( on 1
KB boundary )
3 KB ma x.
0000-0BFF Static RAM Volatile
Ext er nal RA M
(XRAM)
Shared by CE and
MPU
5/3 KB †
2000-27FF Static RAM Volatile Configuration
RAM (I/O RAM)
Hardware control 2 KB
2800-287F Static RAM
Non-volatile
(battery)
Configuration
RAM (I/O RAM)
Battery-buffered
memory
128
0000-00FF
Static RAM
Volatile
Int er nal RAM
Part of 80515 Core
256
† Memory si z e depends on IC. See 2.5.1 Phys ica l Memory for detail s.
MOV X Addressi ng
There ar e two types of instructi ons differing in whether they provide an 8-bit or 16-bit indirect addr ess to
the external dat a RA M.
In t he first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank pr ov ide the eight
lower-ordered bit s of addr es s. The eight high-order ed bits of the address are specifi ed with the PDATA
SFR. Thi s met hod allows t he user paged acc ess (256 page s of 256 by tes each) to all r anges of the
ex ternal dat a RAM.
In t he second t y pe of MOVX i nstr uc tion, MOV X A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and mor e eff icient when accessing v er y large dat a arrays (up t o 64 KB), since no
additi onal instr uc tions are needed to set up t he eight high ordered bits of the addres s.
It is possible to mix the t wo MOVX types. Thi s provides t he user with four separat e data pointer s, two
with direct acc ess and two with paged ac c es s, to the entire external mem or y range.
Dual Dat a Poin t er
The Dual Data Pointer ac c eler ates the block m oves of data. The standard DPTR i s a 16-bit r egister that
is used to address exter nal m em or y or peripherals. In the 80515 core, the standar d data pointer is called
DPTR, the second data pointer i s called DPTR1. The data point er select bit, located in the LSB of the DPS
regi ster ( DPS[0], SFR 0x92), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is
select ed when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by t he LSB of the DPS regis ter. A ll DPTR related ins t ruct ions us e the cu rr en t ly selec ted
DPTR f or any activ ity.
The second data point er may not be supported by c er tain compilers.
DPTR1 is useful for copy routines , where it can make the inner loop of the routine two instructions faster
compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and
restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
By selecting the R80515 core in the Keil compiler project s ettings and by using the compiler directive
“MODC2”, dual data pointers are enabled in certain library routines.
71M6541D/F/G and 71M6542F/G Dat a S heet
An al ternative data pointer is availabl e in the f orm of the PDATA register (S FR 0 xBF), sometimes referr ed
to as USR2). It defin es the high byte of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @Ri,A.
In t ernal Data Memory Map and Access
The I nternal dat a memory pr ov ides 256 byt es (0x00 to 0xFF) of data mem or y. The internal data memory
address is al way s 1 byt e wide. Table 11 shows the internal data m em ory map.
The Spec ial F unc tion Reg isters ( S FR) oc cup y the upper 128 bytes . The SFR area of internal data memory
is availabl e only by di r ect addr essing. Indirect addres si ng of this area acc esses the upper 128 bytes of
Int er nal RAM. The lower 128 byt es cont ain working r egisters and bi t addressable memory. The low er 32
bytes for m four banks of eight registers (R0-R7). Two bits on the program memory statu s wo rd (PSW, SFR
0xD0 ) selec t which bank is in use. The next 16 bytes form a block of bit addr essable memor y space at
addresses 0x00-0x7F. All of the bytes in the lower 128 byt es are acc essible through direct or indir ec t
addressing.
Table 11: In t ernal Data Memory Map
Address Range
Direct Add ressing
Indirect Addressing
0x80 0xFF Speci al Functi on Register s (SFRs) RAM
0x30 0x7F Byt e addr essable area
0x20
0x2F
Bi t addressable area
0x00
0x1F
Register bank s R0…R7
2.4.2 Spe cial Function Registers (SFRs)
A map of the S peci al Function Regi ster s i s shown in Table 12.
Only a few addresses in the SFR memory space are occupi ed, the others are not implemented. A read
access to unimplem ented addresses returns undefined data, while a wri te access ha s no effect. SFRs
specific to the 71M654x are shown in bold print on a shaded field. The registers at 0x80, 0x88, 0x 90,
etc., are bit addressable, all other s are byte addressable.
Table 12: Special Function Regi st er Map
Hex/
Bin
Bit
Addressable Byte Addressable Bin/
Hex
X000 X001 X010 X011 X100 X101 X110 X111
F8
INTBITS
VSTAT
RCMD
SPI_CMD
FF
F0
B
F7
E8
IFLAGS
EF
E0
A
E7
D8
WDCON
DF
D0
PSW
D7
C8
T2CON
CF
C0
IRCON
C7
B8
IEN1
IP1
S0RELH
S1RELH
PDATA
BF
B0
P3 (DIO12:15)
FLSHCTL
FLSHPG
B7
A8
IEN0
IP0
S0RELL
AF
A0
P2 (DIO8:11)
A7
98
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
EEDATA
EECTRL
9F
90
P1(DIO4:7)
DPS
ERASE
97
88
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
8F
80
P0 (DIO0:3)
SP
DPL
DPH
DPL1
DPH1
PCON
87
71M6541D/F/G and 71M6542F/G Dat a S heet
2.4.3 Generic 80515 Special Function Registers
Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs. A dd it io nal
descripti ons of the registers can be found at the page numbers listed in the table.
Table 13: G eneri c 80515 S FRs - Location and Reset Valu es
Name
Address
(Hex)
Reset value
(Hex)
Description Page
P0
0x80
0xFF
Port 0
36
SP
0x81
0x07
Stac k Pointer
35
DPL
0x82
0x00
Data Pointer Low 0
35
DPH
0x83
0x00
Data Pointer High 0
35
DPL1
0x84
0x00
Data Pointer Low 1
35
DPH1
0x85
0x00
Data Pointer High 1
35
PCON
0x87
0x00
UART Speed Control
39
TCON
0x88
0x00
Timer /Counter Contr ol
42
TMOD
0x89
0x00
Timer Mode Control
40
TL0
0x8A
0x00
Timer 0, low byte
39
TL1
0x8B
0x00
Timer 1, high byte
39
TH0
0x8C
0x00
Timer 0, low byte
39
TH1
0x8D
0x00
Timer 1, high byte
39
CKCON
0x8E
0x01
Cloc k Contr ol ( Str etch=1)
36
P1
0x90
0xFF
Port 1
36
DPS
0x92
0x00
Data Pointer selec t Register
32
S0CON
0x98
0x00
Serial Port 0, Contr ol Register
38
S0BUF
0x99
0x00
Serial Port 0 , Data Buffer
36
IEN2
0x9A
0x00
Int er r upt Enable Register 2
42
S1CON
0x9B
0x00
Serial Port 1, Contr ol Register
38
S1BUF
0x9C
0x00
Serial Port 1 , Data Buffer
36
S1RELL
0x9D
0x00
Serial Port 1, Reload Regi ster , low byte
36
P2
0xA0
0xFF
Port 2
36
IEN0
0xA8
0x00
Int er r upt Enable Register 0
41
IP0
0xA9
0x00
Int er r upt Pri or ity Register 0
45
S0RELL
0xAA
0xD9
Serial Port 0, Reload Regi ster , low byte
36
P3
0xB0
0xFF
Port 3
36
IEN1
0xB8
0x00
Int er r upt Enable Register 1
41
IP1
0xB9
0x00
Int er r upt Pri or ity Register 1
45
S0RELH
0xBA
0x03
Serial Port 0, Reload Regi ster , high byt e
36
S1RELH
0xBB
0x03
Serial Port 1, Reload Regi ster , high byt e
36
PDATA
0xBF
0x00
High addr ess byte for MOVX@Ri - also called USR2
32
IRCON
0xC0
0x00
Int er r upt Request Cont r ol Register
42
T2CON
0xC8
0x00
Pol ari ty for INT2 and INT3
42
PSW
0xD0
0x00
Program Status Word
35
WDCON
0xD8
0x00
Baud Rate Control Register (only WDCON[7] bit used)
36
A
0xE0
0x00
Accumulator
35
B
0xF0
0x00
B Regi ster
35
71M6541D/F/G and 71M6542F/G Dat a S heet
Accumulat or (ACC, A, S FR 0 x E0):
ACC i s the accumul ator register . Most i nst r uctions use the a c c umulator to hold the opera nd. The
mnemonics for accumulat or -specif ic instr uc tions ref er to accumulat or as A, not ACC.
B Register (SFR 0xF0):
The B regi ster is used during multiply and divide instructions. I t can also be used a s a scratch-pad register
to hold temporar y data.
Program Status Wo rd (PSW, SFR 0xD0 ):
This register c ontains vari ous flags and cont r ol bit s for the select ion of the register bank s (see Table 14).
Table 14: PSW Bit F unc tions (SFR 0xD0)
PSW Bit Symbol Function
7
CV
Carry flag.
6
AC
Auxili ary Carr y flag for BCD operations.
5
F0
General purpose Flag 0 available for user.
F0 is not t o be confused with the F0 flag in the CESTATUS register.
4
RS1
Register bank sel ec t cont r ol bits. The contents of RS1 and RS0 sel ec t t he
working register bank :
RS1/RS0
Bank sel ect ed
Location
00
Bank 0
0x00 – 0x07
01
Bank 1
0x08 – 0x0F
10
Bank 2
0x10 – 0x17
11
Bank 3
0x18 – 0x1F
3
RS0
2
OV
Overflow fl ag.
1
–
User defined flag.
0
P
Parity flag, affected by hardware to indicat e odd or even number of one bits in
the Ac c um ulator, i.e., even parit y.
Stack Po in t er (SP, SFR 0x81):
The stack point er is a 1-byte register initi aliz ed to 0x07 after r eset. This regi ster is i nc r em ented before
PUSH and CALL instr uc ti ons, c ausi ng the stack to begin at loc ation 0x08.
Data Po in t er:
The dat a pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (SFR
0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data pointer s
can be l oaded as two regi ster s (e.g., MOV DPL,#data8). They are generally used to access external
code or dat a space (e.g., MOVC A,@A+DPTR or MO VX A,@ DPTR r espect ively).
Program Counter:
The program counter (PC) is 2 by t es wide and initialized to 0x0000 after reset. This register is incremented
when fetchi ng oper ation code or when operat ing on data fro m program memory.
Port Regi st ers:
SEGDIO0 through SEGDIO15 ar e contr olled by Special Function Registers P0, P1, P2 and P3 as shown in
Table 15. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since the direction bits
are contained in the upper nibble of each SFR Pn register and the DIO bits are contained in the lower nibble,
it is possible to configure the direction of a given DIO pin and set its output value wit h a si ngle write operat ion,
thus facilit ating the im plem entation of bit-banged interfaces. Writing a 1 to a DIO_DIR bit configures the
correspon ding DIO as an output, while writing a 0 configures it as an input. Writing a 1 to a DIO bit causes
the cor r espondi ng pin t o be at high level (V3P3), while writing a 0 causes the corresponding pin to be held
at a low level (GND). See 2.5.8 Digital I/O for additional details.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 15: Port Registers (SEGDIO0-15)
SFR
Name SFR
Address D7 D6 D5 D4 D3 D2 D1 D0
P0
0x80
DIO_DIR[3:0]
DIO[3:0]
P1
0x90
DIO_DIR[7:4]
DIO[7:4]
P2
0xA0
DIO_DIR[11:8]
DIO[11:8]
P3
0xB0
DIO_DIR[15:12]
DIO[15:11]
Ports P0-P3 on the c hip ar e bi-directional and control SEGDIO 0-15. Each port consists of a Latch ( SFR
P0 to P3), an output driver and an input buf fer, theref ore the M P U can output or read data through any of
these ports. Even if a DIO pin is configur ed as an output, the state of the pin can still be r ead by the
MPU, for ex am ple when counting pulses issue d v ia DIO pins that are under CE contr ol.
At power-up SEGDIO0-15 are c onfigured as inputs. I t is nece ssary to writ e PORT_E = 1 (I/O RAM
0x270C[5]) to enable SEGDIO0-15. The default PORT_E = 0 blocks any m om entary output
transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up.
Clo ck S t ret chi ng (CKCON)
The three low order bits of the CKCON[2:0] (SFR 0x8E) regi ster def i ne the stretch m emory cy cl e s t hat
are used f or MOVX instructions when accessing exter nal peri pher als. The practical value of t his register
for the 71M6541D/F/G and 71M6542F/G i s to guarantee access t o XRAM between CE, M P U, and SPI.
The def ault setting of CKCON[2:0] (001) shoul d not be changed.
Table 16 shows how the signal s of the External Mem ory I nterf ace change when st r etch values are set
from 0 to 7. The widths of t he si gnals are count ed in MPU clock cycles. The post-reset state of the
CKCON[2:0] (001), which is shown in bold in the t able, performs the MOVX instruc tions with a stret c h
v alue equal to 1.
Table 16: S t ret ch Memory Cycle Width
CKCON[2:0] Stretch
Value Read Signal Width Write Signal Width
memaddr memrd memaddr memwr
000
0
1
1
2
1
001
1
2
2
3
1
010
2
3
3
4
2
011
3
4
4
5
3
100
4
5
5
6
4
101
5
6
6
7
5
110
6
7
7
8
6
111
7
8
8
9
7
2.4.4 Instruc tion Set
All instr uc tions of the gener ic 8051 microc ontroller are supported. A complet e list of the instr uc tion set
and of t he associated op-codes is cont ained in t he 71M654X Softw ar e Us er ’s Guide ( S UG).
2.4.5 UARTs
The 71M6541D/F/G and 71M6542F/G include a UART (UA RT0) that c an be pr ogr ammed to
communicate wit h a v ari ety of AM R modules and other ext er nal dev ic es. A second UA RT (UART1) is
connect ed to the optical port, as descri bed in 2.5.7 UART and Optical Int erface.
Th e UA RTs ar e dedic at ed 2-wir e s erial int er faces, wh ich can communicat e with an extern al host processor
at up t o 38,400 bits/s (wit h MPU cloc k = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
71M6541D/F/G and 71M6542F/G Dat a S heet
• UART0 RX: Serial input data are applied at this pi n. C onforming to RS-232 standard, the bytes are
input LSB first.
• UART0 TX: T his pin is used to output the serial data. The bytes are output LS B first.
Sever al UART-r elated registers are available for the c ontrol and buffering of serial data.
A single SFR register serves as both the t r ansmit buffer and rec eive buff er (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x 9 C for UART1). When w ritten by the MPU, SxBUF ac ts as the transmi t buffer, and
when read by t he M P U, it act s as the receive buf fer. Writing data to t he transmit buf fer start s the
transmi ssion by the associated UART. Received data ar e available by reading from the rec eive buf fer.
Both UA RTs can simult aneousl y transmit and r ec eiv e data.
WDCON[7] (S FR 0xD 8) sel e ct s wh et h er t im er 1 or t he i nt er n al ba u d ra te ge ner ator i s us ed. A ll UA RT
transfers are programmable for parity enable, pa ri ty , 2 st op bi t s/1 sto p bi t a n d XON/ X OF F o ptions f o r
var iable communic ati on b aud rates fr om 300 to 38400 bps. Table 17 shows ho w th e ba ud rates are
calculated. Table 18 shows t he sel ec tabl e UA RT operation modes.
Table 17: Baud Rat e Gen erat io n
Using Timer 1
(WDCON[7] = 0) Usin g Int ernal Baud Rate Generat or
(WDCON[7] = 1)
UART0 2
smod
* fCKMPU/ (384 * (256-TH1)) 2
smod
* fCKMPU/(64 * (2
10
-S0REL))
UART1 N/A fCKMPU/(32 * (2
10
-S1REL))
S0REL and S1REL are 10-bit values derived by combining bit s fr om the r espect ive timer rel oad r egister s.
(S0RELL, S 0RE LH, S1RELL, S1RELH are SFR 0x AA, S FR 0x BA, S FR 0 x9 D and SFR 0 xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SF R 0x87 ). TH1(SFR 0x8D) is the high byt e of timer 1.
Table 18: UART Mod es
UART 0
UART 1
Mode 0 N/A
Star t bit, 8 data bits, par ity, stop bit, variable
baud rate ( internal baud rat e generator )
Mode 1
Star t bit, 8 data bits, stop bit , variable
baud rate ( internal baud rat e generator
or tim er 1)
Star t bit, 8 data bits, stop bit, variable baud
rate (i nternal baud rate generat or )
Mode 2
Star t bit, 8 data bits, par ity, stop bit,
fixed baud rate 1/ 32 or 1/64 of fCKMPU
N/A
Mode 3
Star t bit, 8 data bits, par ity, stop bit,
v ari able baud rate (internal baud rate
generator or timer 1)
N/A
Parity of serial data is available through the P flag of t he accumulat or. 7-bit serial modes with
pari ty, such as those used by the F LAG pr otocol, can be si mulated by set ting and readi ng bit 7 of
8-bit output data. 7-bit serial modes wi thout par it y can be sim ulated by set ting bit 7 t o a constant
1. 8-bit serial m odes with pari ty can be simulat ed by setting and r eading the 9th bit, usi ng the
contr ol bit s TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (S FR 0x 9B )
registers for trans mit and RB81 bit in S1CON[2] for receive operations.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communicati on in multi-p ro cessor syst ems. In this case, t he sl av e pr oc essors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART 1, s et to 1. When the mast er processor outputs
the slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the sl av es. The
slave processors compare the rec eived byte wit h their address. If there is a matc h, t he addr essed slave
clears SM20 or SM21 and recei ve the r est of the message. Th e rest of the sl ave’ s i gn or es the
message. After addr essing t he sl ave, the host output s the r est of the message with the 9th bit set to 0, so
no additi onal serial port receive i nterrupts are generated.
71M6541D/F/G and 71M6542F/G Dat a S heet
UART Cont rol Regi st ers:
The functions of UART0 and UART 1 depend on the sett ing of the Seri al Port Control Registers S0CON
and S1CON shown in Table 19 and Table 20, respectively, and the PCON register shown i n Table 21.
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable by te, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operati ons as a byte wide read-modify-wr ite har dware macr o. If an interrupt occ ur s after
the read, but before the write, its fl ag is c leared uninten tionally.
The proper way to cl ear these fl ag bits is to wri te a byte mask consi sting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones w ritten to them.
Table 19: The S0CON (UART0) Regist er (SF R 0x98)
Bit Symbol Function
S0CON[7]
SM0
The SM0 and SM1 bits set the UART 0 mode:
Mode
Description
SM0
SM1
0
N/A
0
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
1
S0CON[6]
SM1
S0CON[5]
SM20
Enabl es the inter-processor commun ication feature.
S0CON[4]
REN0
If set, enables serial r ec eption. Clear ed by software to disable r ec eption.
S0CON[3]
TB80
The 9t h transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it perf orms (parity check , multipr oc essor
communication etc.)
S0CON[2]
RB80
In Modes 2 and 3 it is the 9th data bit received. I n M ode 1, SM20 is 0 ,
RB80 is the stop bi t. In mode 0, thi s bit is not used. M ust be cl ear ed by
software.
S0CON[1]
TI0
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software (see Caut ion above).
S0CON[0]
RI0
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software (see Caut ion above).
Table 20: The S1CON (UART1) Register (SFR 0x9B)
Bit
Symbol
Function
S1CON[7]
SM
Sets the baud r ate and mode for UART1.
SM
Mode
Description
Baud Rat e
0
A
9-bit UART
variable
1
B
8-bit UART
variable
S1CON[5]
SM21
Enabl es the int er -process or commun ication feature.
S1CON[4]
REN1
If set, enables serial r ec eption. Cleared by software to disable r ec eption.
S1CON[3]
TB81
The 9
th
transmi tte d d ata bit in M od e A . Set or c leared by the MPU,
depending on the function it perform s (parity c hec k, m ultiprocessor
communication etc.)
S1CON[2]
RB81
In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bi t. Must be cleared by software
S1CON[1]
TI1
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software (see Caut ion above).
S1CON[0]
RI1
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software (see Caut ion above).
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 21: PCON Register Bit Descript io n (SFR 0x87)
Bit
Symbol
Function
PCON[7]
SMOD
The SMOD bit doubles the baud r ate when set
2.4.6 T imers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. T hese registers can be configured
for counter or tim er operat ions.
In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods
of t he MPU cloc k. In counter mode, the register is inc remented when the falling edge is observed at th e
correspondi ng input si gnal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins,
see 2.5.8 Digit al I/ O). Si nc e it takes 2 machine cycles to recogniz e a 1-to-0 event, the maximum input
cou nt rate is 1/2 of t he clock frequency (CKMPU). There are n o restrictions on t he d uty cycle, however
to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four oper ati ng modes can be select ed for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The
TMOD (SFR 0x89) Regi ster , shown in Table 24, is used to sel ec t the appropri ate mode. The timer/counter
operation is controlled by the TCON (SF R 0x88 ) Register, which is shown in Table 25. Bits TR1 (TCON[6])
and TR0 (TCON[4]) in the TCON register star t t heir assoc iat ed timer s when set.
Table 22: Timers/Counters Mode Description
M1 M0
Mode
Function
0
0
Mode 0
13-bit Counter/Timer mode w ith 5 lower b its in the TL0 or TL1 (SFR
0x8A or SFR 0x8B) register and the remaining 8 bits i n the TH0 or TH1
(SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively).
The 3 high order bits of TL0 and TL1 are held at zero.
0
1
Mode 1
16-bit Counter /Timer mode.
1 0 Mode 2
8-bit auto-reload Count er /Timer. The rel oad value is kept in TH0 or
TH1, while TL0 or TL1 i s i nc r em ented every machine cycle. When
TL(x) overflow s , a value from TH(x) is copied to TL(x) (where x is 0
for counter/t im er 0 or 1 for count er /t im er 1.
1
1
Mode 3
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 i s affect ed by TR0 and gate control bit s, and sets the TF0 f lag on overflow, whil e TH0
is affect ed by the TR1 bit, and the TF1 fl ag is set on overfl ow.
Table 23 specifies the com binations of operation modes all owed for Timer 0 and Timer 1.
Table 23: Allowed Timer /Counter Mode Combinations
Ti mer 1
Mode 0 Mode 1 Mode 2
Ti mer 0 - mode 0
Yes
Yes
Yes
Ti mer 0 - mode 1
Yes
Yes
Yes
Ti mer 0 - mode 2
Not allowed
Not allowed
Yes
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 24: TMOD Reg ister Bit Descri ption (SFR 0x89)
Bit
Symbol
Function
Ti mer/Counter 1
TMOD[7]
Gate
If TMOD[7] is set , exter nal input signal control is enabled for Counter 1. The
TR1 bit in the TCON register (SFR 0x88) must a lso be set in order for Counter 1 to
increment. With these sett ings , Counter 1 increments on ever y falling edge of the
logic signal applied to one or more of the SEGDIO 2-11 pins, as specified by the
contents of the DIO_R2 through DIO_R11 register s. S ee 2.5.8 Digital I/O and
LCD Segment Drivers and Table 47.
TMOD[6]
C/T
Selects timer or counter operation. When set to 1, a counter operation is performed.
When cleared to 0, the corresponding register functions as a timer.
TMOD[5:4]
M1:M0
Sel ec ts the mode for Timer/Counter 1, as shown in Table 22.
Ti mer/Counter 0:
TMOD[3]
Gate
If TMOD[3] is set , exter nal input signal control is enabled for Counter 0. The
TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to
increment. With these sett ings , Counter 0 is incremented on every falling edge of
the logic signal applied t o one or more of the SEGDIO2-11 pins, as spec if ied by
the contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
LCD Segment Drivers and Table 47.
TMOD[2]
C/T
Selects tim er or count er oper ation. When set to 1, a counter oper ati on is
performed. When cleared to 0, the c or r espondi ng r egister functions as a timer.
TMOD[1:0]
M1:M0
Sel ec ts the mode for Timer/Counter 0 as shown in Table 22.
Table 25: The TCON Register Bit Functions (SFR 0x88)
Bit
Symbol
Function
TCON[7]
TF1
The Timer 1 overfl ow flag is set by har dware when Tim er 1 overf lows. This flag
can be c leare d by so ftwa re and is automatica lly c leared w hen an interrup t is
processed.
TCON[6]
TR1
Timer 1 run control bit . If cl ear ed, Timer 1 st ops.
TCON[5]
TF0
Timer 0 overflow flag set by har dware when Timer 0 overflows. T his f lag can be
cl ear ed by software and is automatically cl ear ed when an int er r upt is processed.
TCON[4]
TR0
Timer 0 Run control bit. If cl ear ed, Timer 0 st ops.
TCON[3]
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is
observed. Cleared when an interrupt is processed.
TCON[2]
IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input pin
to cause an i nterrupt.
TCON[1]
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is
observed. Cleared when an int er r upt is processed.
TCON[0]
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input pin
to cause i nterrupt.
2.4.7 WD Timer (Software Watchdog Timer)
There is no internal software watc hdog timer. Use t he standar d hardware wat c hdog tim er instead (see
2.5.11 Hardware Watchdog Timer).
2.4.8 Interrupts
The 8051 5 provides 11 in terru pt sou rces with four pr ior it y le vels . Each source has its own interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each i nterrupt requested by
71M6541D/F/G and 71M6542F/G Dat a S heet
the c or r espondi ng interrupt flag can be indiv idually enabled or disabled by the interrupt enabl e bits in the
IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x 9A).
Figure 16 shows the device inter r upt struc ture.
Referring to Figure 16, interrupt sources can originate fr om withi n the 80515 MP U core (r ef erred t o as
Internal Sources) or can ori ginat e from other par ts of t he 71M654x SoC (referr ed to as Ext er nal S our c es).
There ar e seven ext er nal interrupt sources, as seen i n the lef tmost part of Figure 16, and in Table 26 and
Table 27 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown i n Table 38. Once
the int er rup t service has begun , it can be inte rrupted only by a higher pr iority interrupt. The interrupt service
is terminated b y a return from interrupt instr uction, RETI. When a R E TI instruction is perform ed, th e
processor returns to the instruc tion that would have been next when the i nterrupt occ ur r ed.
When the inter r upt condition occurs, the processor also indicat es this by setting a fl ag bit. T his bit i s set
regardless of whether t he int er r upt is enabled or disabled. Each interrup t flag is sampled once per
m ac hine c y cl e, and t hen samples are polled by the hardware. If the sample indicates a pending int er r upt
when the interr upt is enabled, then t he interrupt request fl ag is set. On t he next instruc ti on c yc le, the
interrupt is acknowledged by har dware forc ing an LCALL to the appr opr iate vector addr ess, if the
following conditions are met:
• No int er r upt of equal or higher pri or ity is alr eady in pr ogress.
• An instr uc tion is current ly being executed and is not c om pleted.
• T he inst ruct io n in progr ess is not RETI o r any write ac cess to the register s IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Regi st ers f or In t errupts
The foll owing SFR r egister s cont r ol the interr upt functions:
• The i nterr upt enabl e regi ster s: IEN0, IEN1 and IEN2 (see Table 26, Table 27 and Table 28).
• The Tim er/Counter control register s, TCON and T2CON (see
• Table 29 and Table 30).
• The interrupt r equest register, IRCON (see Table 31).
• The i nterr upt priority register s: IP0 and IP1 (see Table 36).
Table 26: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol
Function
IEN0[7]
EAL
EAL = 0 disabl es all interrupts .
IEN0[6]
WDT
Not used for int errupt c ontrol.
IEN0[5]
–
Not Used.
IEN0[4]
ES0
ES0 = 0 disables serial c hannel 0 interrupt.
IEN0[3]
ET1
ET1 = 0 disables timer 1 overfl ow interrupt.
IEN0[2]
EX1
EX1 = 0 disables externa l interrupt 1: DIO status change
IEN0[1]
ET0
ET0 = 0 disables timer 0 overfl ow interrupt.
IEN0[0]
EX0
EX0 = 0 disables external interrupt 0: DIO status change
Table 27: The IEN1 Bit Functions (SFR 0xB8)
Bit
Symbol
Function
IEN1[7]
–
Not used.
IEN1[6]
–
Not used.
IEN1[5]
EX6
EX6 = 0 disables external interrupt 6:
XFER_BUSY , RTC_1S, RTC_1M or RTC_T
IEN1[4]
EX5
EX5 = 0 disables external interrupt 5: EEPROM or SPI
IEN1[3]
EX4
EX4 = 0 disables external interrupt 4: VSTAT
71M6541D/F/G and 71M6542F/G Dat a S heet
IEN1[2]
EX3
EX3 = 0 disables external interrupt 3: CE_BUSY
IEN1[1]
EX2
EX2 = 0 disables external interrupt 2:
XPULSE, YPULSE, WPULSE or VPULSE
IEN1[0]
–
Not Used.
Table 28: The IEN2 Bit Functions (SFR 0x9A)
Bit
Symbol
Function
IEN2[0]
ES1
ES1 = 0 disables the serial c hannel 1 interrupt .
Table 29: TCON Bit Functions (SFR 0x88)
Bit
Symbol
Function
TCON[7]
TF1
Timer 1 overflow flag.
TCON[6]
TR1
Not used for int errupt c ontrol.
TCON[5]
TF0
Timer 0 overflow flag.
TCON[4]
TR0
Not used for int errupt c ontrol.
TCON[3]
IE1
Ext er nal interrupt 1 flag: DIO stat us changed
TCON[2]
IT1
Ext er nal interrupt 1 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
TCON[1]
IE0
Ext er nal interrupt 0 flag: DIO stat us changed
TCON[0]
IT0
Ext er nal interrupt 0 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
Table 30: The T2CON Bit Fu nc t i ons (SFR 0xC8)
Bit
Symbol
Function
T2CON[7]
–
Not used.
T2CON[6]
I3FR
Pol ar ity control for external interrupt 3: CE_BUSY
0 = falling edge.
1 = ri si ng edge.
T2CON[5]
I2FR
Pol ar ity control for e xternal interrupt 2:
XPULSE, YPULSE, WPULSE and VPULSE
0 = falling edge.
1 = ri si ng edge.
T2CON[4:0]
–
Not used.
Table 31: The IRCON Bit Functions (SFR 0xC0)
Bit
Symbol
Function
IRCON[7]
–
Not used
IRCON[6]
–
Not used
IRCON[5]
IEX6
1 = Ext er nal interrupt 6 occur r ed and has not been c leared:
XFER_BUSY , RTC_1S, RTC_1M or RTC_T
IRCON[4]
IEX5
1 = Ext er nal interrupt 5 occur r ed and has not been c leared:
EEPROM or SPI
IRCON[3]
IEX4
1 = Ext er nal interrupt 4 occur r ed and has not been c leared:
VSTAT
IRCON[2]
IEX3
1 = Ext er nal interrupt 3 occur r ed and has not been c leared:
CE_BUSY
71M6541D/F/G and 71M6542F/G Dat a S heet
IRCON[1]
IEX2
1 = Ext er nal interrupt 2 occur r ed and has not been c leared:
XPULSE, YPULSE, WPULSE or VPULSE
IRCON[0]
–
Not used.
TF0 and TF1 ( Timer 0 and Timer 1 ov erflow flags) are automatically cleared by hardware when the
service routine is call ed (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
71M6541D/F/G and 71M6542F/G Dat a S heet
External MPU Interrupts
The sev en ex ternal int er r upts are the interrupts external to the 80515 cor e, i.e., signals that ori ginate in
other par ts of the 71M654x, for example t he CE, DIO, RTC, or EEPROM inter face.
The external interr upts are connected as shown in Table 32. The polarity of i nterrupts 2 and 3 i s
programmable i n th e M PU via t he I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4
through 6 ar e defined as ri sing-edge sensitive. T hus, the hardware signals att ached to interr upts 5
and 6 are invert ed to achieve the edge polarity shown i n Table 32.
Table 32: E xt ernal MPU In t errupt s
External
Interrupt
Connection Polarity F lag Reset
0
Digital I/O
see 2.5.8
automatic
1
Digital I/O
see 2.5.8
automatic
2
CE_PULSE
rising
automatic
3
CE_BUSY
falling
automatic
4
VSTAT (VSTAT[2:0] changed)
rising
automatic
5
EEPROM busy (falling), SPI (risi ng)
automatic
6
XFER_BUSY (falling), RTC_1SE C, RTC_1MI N, RTC_T
falling
manual
Ext er nal interrupt 0 and 1 can be mapped to pins on the devi c e usi ng DIO resource maps. See 2.5.8
Digital I/O for mo re information.
SFR enable bit s m ust be set to permit any of these interrupts to occur. Likewise, each interru pt h as its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrup t hand ler . XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRIS E and PLLFALL have their own enable and flag bit s in
addition to the interrupt 6, 4 and enabl e and flag bits (see Table 33: Int er r upt Enable and Flag Bits).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.
Si nc e these bits are in an SFR bit addressable byte, c ommon practice would be t o cl ear them
with a bit oper ation, but t his must be avoided. The hardware implement s bi t operations as a
byte wide r ead-modify-wri te hardware m ac r o. If an i nterrupt oc c ur s aft er t he r ead, but before
the write, its flag cleared unintentionally.
The proper way to cl ear the flag bits is to wri te a byte m ask consi sting of all ones ex c ept f or a
zero in the location of the bit to be clear ed. The flag bits are conf igured in hardware t o ignore
ones w ritten to them.
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable Inte r r u pt Flag In t errup t Description
Name
Location
Name
Location
EX0
SFR 0xA8[[0]
IE0
SFR 0x88[1]
Ext er nal interrupt 0
EX1
SFR 0xA8[2]
IE1
SFR 0x88[3]
Ext er nal interrupt 1
EX2
SFR 0xB8[1]
IEX2
SFR 0xC0[1]
Ext er nal interrupt 2
EX3
SFR 0xB8[2]
IEX3
SFR 0xC0[2]
Ext er nal interrupt 3
EX4
SFR 0xB8[3]
IEX4
SFR 0xC0[3]
Ext er nal interrupt 4
EX5
SFR 0xB8[4]
IEX5
SFR 0xC0[4]
Ext er nal interrupt 5
EX6
SFR 0xB8[5]
IEX6
SFR 0xC0[5]
Ext er nal interrupt 6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
0x2700[0]
0x2700[1]
0x2700[2]
0x2700[4]
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
SFR 0xE8[0]
SFR 0xE8[1]
SFR E 0x8[2]
SFR 0xE8[4]
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T a larm cloc k interrupt (int 6)
71M6541D/F/G and 71M6542F/G Dat a S heet
Interrupt Enable Inte r r u pt Flag In t errup t Description
Name
Location
Name
Location
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR 0xF8[7]
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[4]
SFR 0xF8[3]
SPI interrupt
EEPROM interrupt
CE_XPULSE inter r upt (int 2)
CE_YPULSE int er r upt (int 2)
CE_WPULSE int errupt (int 2)
CE_VPULSE int er r upt (int 2)
In t errup t P rio rity Level Stru cture
All interrupt sources are combined in groups, as shown i n Table 34.
Table 34: Interrupt Priority Level Groups
Group Group Members
0
Ext er nal interrupt 0
Serial channel 1 interrupt
–
1
Timer 0 interrupt
–
Ext er nal interrupt 2
2
Ext er nal interrupt 1
–
Ext er nal interrupt 3
3
Timer 1 interrupt
–
Ext er nal interrupt 4
4
Serial channel 0 interrupt
–
Ext er nal interrupt 5
5
–
–
Ext er nal interrupt 6
Each group of inter r upt sources can be program med individually t o one of four priority levels (as sho wn in
Table 35) by set ti ng or clearing one bit in the SFR int errupt pr iority r egister IP0 (SFR 0x A9) and one in IP1
(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling
sequence as sho wn in Table 37 det ermines whi c h r equest i s serv iced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before int errupts are enabled.
Table 35: In t errupt Priori t y Level s
IP1
[x]
IP0
[x]
Priorit y Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
Table 36: In t errupt Priori t y Regi st ers ( IP0 and IP1)
Register
Address
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
IP0
SFR 0x A9
–
–
IP0[5]
IP0[4]
IP0[3]
IP0[2]
IP0[1]
IP0[0]
IP1
SFR 0x B9
–
–
IP1[5]
IP1[4]
IP1[3]
IP1[2]
IP1[1]
IP1[0]
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 37: Interrupt Polling Sequence
Ext er nal interrupt 0
Polling sequence
Serial channel 1 interrupt
Timer 0 interrupt
Ext er nal interrupt 2
Ext er nal interrupt 1
Ext er nal interrupt 3
Timer 1 interrupt
Ext er nal interrupt 4
Serial channel 0 interrupt
Ext er nal interrupt 5
Ext er nal interrupt 6
In t errup t Sources and Vectors
Table 38 shows the interrupts wit h their associ ated flags and vector addr esses.
Table 38: In t errupt Vectors
Interrupt
Request Flag
Description Interrupt V ector
Address
IE0
Ext er nal interrupt 0
0x0003
TF0
Timer 0 interrupt
0x000B
IE1
Ext er nal interrupt 1
0x0013
TF1
Timer 1 interrupt
0x001B
RI0/TI0
Serial channel 0 interrupt
0x0023
RI1/TI1
Serial channel 1 interrupt
0x0083
IEX2
Ext er nal interrupt 2
0x004B
IEX3
External interrupt 3
0x0053
IEX4
Ext er nal interrupt 4
0x005B
IEX5
Ext er nal interrupt 5
0x0063
IEX6
Ext er nal interrupt 6
0x006B
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 16: Interrupt Structure
TCON.1 (IE0 )
Individual
Enable Bits
S1CON.0 (RI1 )
S1CON.1 (TI1 )
Individual Flags
Internal
Source
>=1
TCON.5 (TF0 )
TCON.3 (IE1 )
TCON.7 (TF1 )
S0CON.0 (RI0 )
S0CON.0 (TI0 ) >=1
IRCON.1
(IEX2)
I2FR
IRCON.2
(IEX3)
I3FR
IRCON.3
(IEX4)
IRCON.4
(IEX5)
IRCON.5
(IEX6)
IEN0.7
(EAL)
IP1.0/
IP0.0
IP1.1/
IP0.1
IP1.2/
IP0.2
IP1.3/
IP0.3
IP1.4/
IP0.4
IP1.5/
IP0.5
Interrupt
Flags Priority
Assignment
Interrupt
Vector
Polling Sequence
Interrupt Enable
Logic and Polarity
Selection
DIO
Timer 0
DIO
Timer 1
CE_BUSY
UART0
EEPROM
XFER_BUSY
RTC_1S EX_RTC1S
VSTAT
RTC_T EX_RTCT
XPULSE
External
Source
DIO_Rn
DIO_Rn
SPI
>=1
EX_VPULSE
VPULSE
>=1
IEN2.0
(ES1)
IEN0.1
(ET0)
IEN0.0
(EX0)
IEN1.1
(EX2)
IEN0.2
(EX1)
IEN1.2
(EX3)
IEN0.3
(ET1)
IEN1.3
(EX4)
IEN0.4
(ES0)
IEN1.4
(EX5)
IEN1.5
(EX6)
IE_XFER
IE_RTC1S
IE_RTCT
EX_XFER
>=1
EX_EEX
EX_SPI
IE_EEX
IE_SPI
IT0
IE_XPULSE
IE_VPULSE
EX_XPULSE
RTC_1M EX_RTC1M IE_RTC1M
UART1
(optical)
0
2
1
3
4
5
6
No.
Flag=1
means that
an interrupt
has occurred
and has not
been cleared
EX0 – EX6 are cleared
automaticallywhen the
hardware vectors to the
interrupt handler
byte received
byte transmitted
overflow occurred
overflow occurred
byte received
byte transmitted
accumulation
cycle completed
alarm clock
Supply status changed
CE completed code run and
has new status information
DIO status
changed
DIO status
changed
CE detected sag
every second
every minute
BUSY fell
command
received
WPULSE
YPULSE
EX_WPULSE
EX_YPULSE IE_YPULSE
IE_WPULSE
CE detected zero
crossing
Wh pulse
VARh pulse
3/19/2010
“Internal Source” refers to interrupt sources originating within the 80515 MPU core.
“External S ource” refers to interrupt sources outside the 80515 MPU core originating from other parts of the 71M654x SoC.
71M6541D/F/G and 71M6542F/G Dat a S heet
2.5 On-Chip Resources
2.5.1 Physical Memory
2.5.1.1 Flash Memory
The dev ice incl udes 128KB (71M6541G, 71M6542G), 64KB (71M 6542F, 71M6541F) or 32KB
(71M6541D) of on-chip fl ash memor y. The fl ash memory prim ar ily contains MPU and CE pr ogr am code.
It also cont ains im ages of the CE RAM and I/O RAM. On power-up , before enabling the CE, the MPU
copies these imag es to their res pec tive locat ions .
Flash space allocated for the CE program i s limit ed to 4096 16-bit words (8 KB). The CE program must
begin on a 1-K B boundary of the f lash address space. The CE_LCTN[5:0] field (I /O RAM 0x2109[5:0 ])
defines whi c h 1 K B boundar y c ontains the CE code. Thus, the first CE inst r uc tion i s locat ed at
1024*CE_LCTN[5:0].
Flash memory can be acc essed by the MP U, t he CE, and by the S PI interface (R/W).
Table 39: Fl ash Memory Access
Access by Access
Type Condition
MPU
R/W/E
W/E only if CE i s di sabl ed.
CE
R
SPI
R/W/E
Access only when SFM is invoked ( M P U halted).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4] key is correct ly pr ogr ammed, the MPU may write to the
flash memory . Thi s is one of the non-volatile storage options availabl e to the user in addition to external
EEPROM.
The fl ash program write enable bit, FLSH_PWE (S F R 0 x B2[0]), dif ferenti ates 80515 data store instructi ons
(MOVX@DPTR,A) bet we e n Fl a sh a n d XRA M wri t e s. T hi s bit i s a ut om ati c al l y cleared by hardware
af t er ea c h byt e wr ite o p er ation. Write operations t o this bit are inhibited when int er r upts are enabled.
If the CE bit is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless
FLSH_PSTWR (S FR 0xB2[2]) is se t. This bit enables the “posted fl ash writ e” c apabilit y. FLSH_PSTWR has
no eff ec t when CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash wri te unt il the time
interval between the CE code passes. During this delay time, the FLSH_PEND bit (SFR 0xB2[3]) is high, and
the MPU continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND
bit falls and the write operati on occurs. The MPU can query the FLSH_PEND bit to determine when the
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.
Updating Indiv idual Bytes i n Flash Memory
The original stat e of a fl ash byt e is 0xF F (all bits are 1). Once a value other than 0xFF is writ ten to a f lash
memo r y cell, ove r wri ti ng with a dif ferent value usually requires that the cell be erased first. Since cell s
cannot be er ased i ndividually, t he page has to be c opied to RAM, followed by a page erase. After this,
the page can be updated i n RAM and then writ ten back to the flash memory.
Flash Erase Procedures
Flash eras ur e is in it iated by wr it ing a spe c ific da ta patte r n to spe c ific S FR reg is ters in the pro per seq uence .
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
• Write 1 to the FLSH_MEEN bit (SF R 0xB2[1]).
• Write the pattern 0 xAA to the FLSH_ERASE register (SFR 0x94).
The mass erase cyc le can only be i nitiated when the I CE port is enabl ed.
71M6541D/F/G and 71M6542F/G Dat a S heet
The page erase sequence is:
• W rite the page addres s to FLSH_PGADR[5:0] (S FR 0x B7[ 7:2]).
• Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94).
Program Security
When e nabl ed, the sec urity featu r e lim it s the ICE to global flash erase oper ations only . All oth er ICE
operations are bl oc k ed. This guarant ees the security of t he user’s MPU and CE progr am c ode. Sec urity
is enabl ed by M P U code that is ex ec uted in a 64 CKMPU cycle pre-boot int erval befor e the prim ar y boot
sequence begins. Onc e security is enabled, the only way to disabl e it is to perf orm a global erase of the
flash, followed by a chi p r eset.
The first 64 cycl es of the MP U boot code ar e call ed the pre-boot phase because duri ng thi s phase the
ICE is i nhibit ed. A read-onl y status bi t, PREBOOT (SFR 0xB2[7]), identifi es these cyc les to t he MPU.
Upon completion of pre-boot, the ICE can be enabl ed and is permitted to t ak e contr ol of t he MPU.
The security enable bit , SECURE (S FR 0xB 2[6]), is reset whenever the chip is reset. Hardware as sociated
with the bit permits only ones t o be written to it. Thus, pre-bo ot cod e ma y set SECURE to enable t he security
feature but may not reset it. O nc e SECURE i s set, the pre-boot code is protect ed and no ext er nal r ead of
program code is possibl e.
Specif ically , when the SECURE bit is se t, the following a pplies:
• The ICE i s limit ed to bulk flash erase only.
• Page zero of flash memory, t he prefer r ed loc ation for the user’s pre-boot c ode, may not be
page-era sed by either MPU or ICE. Page z er o may only be erased wi th gl obal fl ash erase.
• Write operations t o page z er o, whether by MP U or ICE are inhibited.
The 71M6541D/F/G and 71M6542F/G also incl ude hardware to protect against unintentional Flash write
and erase. To enable fl ash writ e and er ase operat ions, a 4-bit har dware key that must be writ ten to the
FLSH_UNLOCK[3:0] field. The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, t he
Flash erase and wr it e operation is inhibited by hardware. Proper oper ation of this security key requi r es
that there be no firm ware function that writes ‘0010’ to FLSH_UNLOCK[3:0]. The key shoul d be wri tt en by
the external SPI m aster , in the case of SPI fl ash program m ing (SFM mode), or through the ICE interface
in the case of ICE flash programming. When a boot loader i s used, t he k ey shoul d be sent to the boot
load c ode whic h then writ es it to FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not autom atically reset. It
should be cleared when the SPI or ICE has f inished changing the Flash. Table 40 summ ari z es the I/ O
RAM registers used f or flash securit y.
Table 40: Fl ash Security
Name
Location
Rst
Wk
Dir
Description
FLSH_UNLOCK[3:0]
2702[7:4]
0
0
R/W
Must be a 2 to enable any f lash modification.
S ee the d escri ption of Fla sh security for
m or e details.
SECURE
SFR B 2[6]
0
0
R/W
Inhibits erasure of page 0 and flash addresses
above the beginning of CE code as defined by
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]). Also
inhibits the read of flash via the ICE and SPI
ports.
SPI Flash Mode
In norm al oper ati on, the SPI slave interface cannot r ead or writ e the fl ash memory. However, the
71M6541D/F/G and 71M6542F/G contain a Special F las h Mode (SFM) that facilitates initial
(production) programming of the flash memory. When the 71M654x is in SFM mode, the SPI interface can
erase, read, and write the f lash. Other memory elements such as XRAM and I/O RA M a r e not
accessible to the SPI in this mode. In order to protect the flash contents, sever al oper ations are requi r ed
before the SFM mode is successfully i nv ok ed.
Detail s on the SFM are in 2.5.10 (SPI Slave Port).
71M6541D/F/G and 71M6542F/G Dat a S heet
2.5.1.2 MPU/CE RAM
The 71M6541D incl udes 3 KB of stat ic RAM m em or y on-chip (XRAM) plus 256 byt es of internal RAM in
the MPU core. The 71M6541D/F/G and t he 71M6542F/G incl ude 5 KB of static RAM m em or y on-chip
(XRAM) plus 256 bytes of int er nal RA M in the MP U core. T he static RAM is used for data storage f or
both MP U and CE operat ions.
2.5.1.3 I/O RAM (Configuration RAM)
The I /O RAM can be seen as a series of hardware registers that c ontrol basic hardware functions. I/O
RAM address space star ts at 0x2000. The registers of the I /O RAM are listed in Table 74.
The 71M6541D/F/G and 71M6542F/G include 128 bytes non-volatile RA M memor y on-chip in the I/O
RAM address space (addresse s 0x2800 to 0x287F). This memory section is supported by t he v oltage
applied at VBAT_RTC and the data in it are preserved in BRN, LCD, and SLP modes as long as the
voltage at VBAT_RTC is wi thin specification.
2.5.2 Oscillator
The o scil l ato r dri v es a st anda rd 32. 7 68 kHz watch crystal . This type of crystal is accurate an d does not
req uire a high-current o s c illator circuit. The oscillator has been designed s pecifically to ha n dl e watc h
crystals and is compatible with their hi gh impedance and limited power handling c apability. The oscillator
power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Osci llat or calibrati on can improve the accuracy of bot h the RTC and met eri ng. Ref er to 2.5.4, Real-Time
Cloc k ( RTC) for more information.
The o scil l ato r is p ower ed from the V3P3SYS pin or from the VBAT_RTC pin, de pe ndi ng o n the V3OK
internal bit (i.e., V3OK = 1 if V 3P 3SYS ≥ 2.8 VDC and V3OK = 0 if V 3P 3S Y S < 2.8 VDC). T he oscillator
requi r es approximately 100 nA, which is negligible compared t o the inter nal leakage of a batter y .
2.5.3 PLL a nd Internal Clocks
Timing for the device is derived f r om the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to produce 19.660800 MHz, the mas ter clock (MC K). All on-chi p timing, except f or the RTC cloc k, is
derived from MCK. Table 41 prov ides a summary of the cl oc k functions and thei r cont r ols.
The t wo general -pur pose count er /timers cont ained in the MPU are controlled by CKMPU (see 2.4.6
Timers and Counters).
The master cl oc k c an be boosted to 19. 66 M Hz by setting the PLL_FAST bit = 1 (I/O RAM 0x22 00[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CK M P U is determined by
another divider contr olled by the I/O RAM c ontrol fiel d MPU_DIV[ 2:0] (I/O RAM 0x2200[2:0]) and can be
set to MCK *2-(MPU_DIV+2) , where MPU_DIV[2:0] may var y from 0 to 4. The 71M654x V3P 3SYS suppl y
current is reduced by reduc ing t he MPU cloc k fr equency. When the ICE_E pin is high, the circ uit also
generates the 9.83 MHz clock for use by t he em ulator.
The PLL is onl y turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
v alue depends on the setti ng of the LCD_VMODE [1:0 ] field (see Table 56).
When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the PLL
frequency is not be accurate until the PLL_OK flag (SFR 0xF9[4]) rises. Due to potential overshoot, the MPU
should not c hange the value of PLL_FAST until PLL_OK is true.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 41: Clo ck S yst em Summary
Clock Derived
From
Fi xed F requ ency or Range
Function
PLL_FAST=1
PLL_FAST=0
Contr olled by
OSC
Crystal
32.768 kHz
–
Crystal clock
MCK Crystal/PLL
19.660800 MHz
(600*CK32)
6.291456 MHz
(192*CK32)
PLL_FAST Master clock
CKCE
MCK
4.9152 MHz
1.5728 MHz
–
CE clock
CKADC MCK 4.9152 MHz ,
2.4576 MHz
1.572864 MHz ,
0.786432 MHz
ADC_DIV ADC cl ock
CKMPU MCK
4.9152 MHz …
307.2 kHz
1.572864 MHz…
98.304 kHz
MPU_DIV[2:0] MPU clock
CKICE MCK 9.8304 MHz…
614.4 kHz
3.145728 MHz …
196.608 kHz
MPU_DIV[2:0] ICE clock
CKOPTMOD MCK 38. 40 k Hz 38.6 kHz –
Optical
UART
Modulation
CK32
MCK
32.768 kHz
–
32 kHz cloc k
2.5.4 Real-Time Clock (RTC)
2.5.4.1 RTC G eneral Description
The RT C is driven directly by the c rystal oscillator and is po wered by ei ther t he V3P3SY S pi n or the
VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a c ounter chain and out put
registers. The c ounter chain consists of registers for seconds, m inutes, hours , day of week, day of
m onth, month, a nd year. The chai n registers are supported by a s hadow r egister that facili tates read
and write oper ati ons.
Table 42 shows the I/O RA M registers for accessing the RTC.
2.5.4.2 Acc essing the RTC
Two bi ts, RTC_RD (I/O RA M 0x2890[6]) and RTC_WR (I/O RAM 0x 2890[ 7]), contr ol the behavi or of the
shadow regi ster .
When RTC_RD is low, the shadow register is updated by t he RTC after eac h two m illiseconds. When
RTC_RD is high, this update is halted and t he shadow register content s become st ationary and are suit able
to be read by the MP U. Thus, when the MPU wishes to r ead the RTC, it freezes the shado w regi ster by
setting the RTC_RD bit, reads the shadow regi ster , and then lowers the RTC_RD bit to let updates to t he
shado w regi ster r esume. Since t he RTC cloc k i s only 500Hz, t her e m ay be a delay of approximatel y 2 ms
from when the RTC_RD bit is lowered until the shadow register r ec eives its fir st update. Reads t o RTC_RD
continue t o retur n a one until the f irst shadow update oc c ur s.
When RTC_WR is high, t he update of the shadow regi ster is also i nhibited. Duri ng this time, the MPU may
overwrite the contents of the shadow register. When RTC_WR is low ered , the sha dow reg is ter is written into
the RTC counter on the next 500Hz RTC cloc k . A chan ge bit is included for each word in the shadow
regi ster to ensure that only pr ogr amm ed words are updated when the MPU writes a zero to RTC_WR.
Reads of RTC_WR returns one until the counter has actual ly been updated by the register.
The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), c an be read by t he MPU after the one
second interrupt and before r eac hing the next one second boundary. The RTC_SBSC register is expressed
as a count of 1/128 second periods remaining until the next one second boundary. W r iting 0x00 t o
RTC_SBSC resets the c ounter re-starting the count from 0 to 127. Readi ng and r esetting the sub-second
counter c an be used as part of an algorithm to accurately set the RT C.
The RT C is capable of processing l eap y ear s. Each counter has i ts own output regi ster. The RTC chain
registers are not affected by the reset pin, watchdog timer resets, or by transitions between the batter y
m odes and mission mode.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 42: RTC Cont rol Regi st ers
Name
Location
Rst
Wk
Dir
Description
RTC_ADJ[6:0]
2504[6:0]
00
–
R/W
Register for analog RTC f r equenc y adjustment .
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
R/W
Register s for digital RTC adjustm ent.
0x0FFBF ≤ RTC_P ≤ 0x10040
RTC_Q[1:0]
289D[1:0]
0
0
R/W
Register for digit al RTC adjustment.
RTC_RD 2890[6] 0 0 R/W
Freez es the RTC shadow register so it is suit able for
MPU reads. When RTC_RD is read, it returns the
status of the shadow register: 0 = up to date, 1 = frozen.
RTC_WR 2890[7] 0 0 R/W
Freez es the RTC shadow register so it is suit able for
MPU write operati ons. When RTC_WR is cleared,
the contents of the shadow regi ster wri tten t o the RT C
counter on the next RTC cl ock (~500 Hz). When
RTC_WR is read, it ret ur ns 1 as long as RTC_WR is
set. It c ontinues
to return one until the RT C counter is
updated.
RTC_FAIL 2890[4] 0 0 R/W
Indicat es that a count error has occurred in the RTC
and that the time is not t r ustworthy . T his bi t can be
cl ear ed by wri ting a 0.
RTC_SBSC[7:0] 2892[7:0] R
Time remaining since the last 1 second boundary.
LSB = 1/ 128 second.
2.5.4.3 RT C Rate Control
Two rate adjustmen t mechanisms are available:
• The first rate adjustment me chanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0] (I/O RAM 0x2504 [6:0]) , t hat t rims the crystal load capacitanc e.
• The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is proces sed i n the RTC.
Setting RTCA_ADJ[6:0] to 00 min imizes th e load cap ac it ance , ma xim iz ing the oscillator freq uency. Se tting
RTCA_ADJ[6:0] to 7F maximizes t he load cap ac it anc e, min imiz ing th e os c illator frequency. Th e adjus table
capacitance is approximately:
pF
ADJRTCA
CADJ 5.16
128
_⋅=
The precise amount of adjustment depends on the crysta l prop er ties , the PCB lay ou t and the value of the
external crystal capacitors. Th e ad jus t men t may oc cur at any time, and the res u lt ing c lock frequency should
be m easured over a one-second int erval.
The second rat e adjustment is digit al, and can be used to adjust the clock rate up to ±988ppm, with a
resolut ion of 3.8 ppm (±1.9 ppm). Note that 3. 8 ppm corre s pond s to 1-LS B of t he 19-bi t q uantit y form ed
by 4*RTCP+RTCQ and 1.9 ppm c orrespo nds t o ½ -LSB. T he rate adjustment is implemented starting at
the nex t seco nd -boundary following t he adjustment. Since t he LSB resul ts in an adjustment every four
seconds, t he frequency shoul d be m easured over an interval that is a multi ple of f our seconds.
The cloc k r ate is adjusted by wri ti ng the appropr iat e values to RTC_P[16:0] (I/O RAM 0x 289B[2:0] , 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]) . Updates to RT C r ate adjust regi ster s, RTC_P and
RTC_Q, are done thr ough the shadow register de scribed above. The new values are loaded into the
counter s when RTC_WR (I/O RAM 0x2890[ 7]) is l owered.
The def ault frequency is 32,768 RT CLK cycl es per second. T o shift t he cl oc k fr equenc y by ∆ ppm,
RTC_P and RTC_Q are calculated using the following equation:
71M6541D/F/G and 71M6542F/G Dat a S heet
+
⋅∆+
⋅
=+⋅ −5.0
101 832768
RTC_QRTC_P4 6
floor
Conv er sel y , the amount of ppm shift f or a giv en v alue of 4RTC_P+RTC_Q is:
() = 󰇧32768 8
4+1󰇨10
For ex am ple, for a shift of -988 ppm, 4 ⋅RTC_P + RTC_Q = 262403 = 0x 40103. RTC_P = 0x10040, and
RTC_Q = 0x03. The default values of RTC_P and RTC_Q, c or r espondi ng to zero adjustment, ar e 0x10000
and 0x 0, respect ively .
Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S , are available for measuring and
cal ibrating the RT C cl oc k frequenc y . T hese are waveforms of approximately 25% duty cycl e with 1s or 4s
period.
Default values for RTCA_ADJ, RTC_P and RTC_Q shoul d be nominal values, at the center of
the adjustment range. Un-calibrated extreme values (zero, for example) can cause incorrect
operation.
If the cr y stal temperature coeffi ci ent is known, the MPU can integrate tem per ature and c or r ec t t he RTC
time as neces sary. Alt er natively, the char ac teristics can be loaded i nto an NV RAM and the OSC_COMP
bit (I/O RAM 0x28A0[5]) may be set . In this case, the oscil lator is adjusted autom aticall y, ev en in S LP
m ode. See the Real Time RTC T em per ature Compensation section for details.
2.5.4.4 RTC Temperature Compensatio n
The 71M6541D/F/G and 71M6542F/G can be conf igured to regularly measure die temperature, including
in SLP and LCD modes and whi le t he M P U is halt ed. If enabled by the OSC_COMP bit, the temperature
information is automatically used to correct for the temperature variati on of th e c rystal. A table look-up
m ethod is used which gener ates the requir ed digital compensation without in volvement from the MPU.
Storage for the look-up table is in a dedicated 128 by te NV RA M .
Table 43 shows the I/O RAM registers involv ed in automati c RTC temper ature compensati on.
Table 43: I/ O RAM Regi st ers f or RT C Temperature Compensation
Name Location Rst Wk Dir Description
OSC_COMP
28A0[5]
0 0 R/W
Enabl es the automati c update of RTC_P and RTC_Q
ev er y tim e the t em per ature is measured.
STEMP[10:3]
STEMP[2:0] 2881[7:0]
2882[7:5] – – R
The result of t he temperature measurement (10-bits of
m agnitude data plus a sign bit).
The com plete STEMP[10:0] value can be read and
shifted right in a si ngle 16-bit read operation as sho wn
in the fo llow ing code fragmen t.
v olatil e int16_t x data STEMP _at_0x 2881;
fa = (float) (ST EMP/32);
LKPADDR[6:0]
2887[6:0]
0
0
R/W
The address for reading and w riting the RTC lookup RAM.
LKPAUTOI 2887[7] 0 0 R/W
Auto-incr em ent fl ag. When set, LKPADDR[6:0] auto
increments every time LKP_RD or LKP_WR is pulsed.
The increment ed addr ess can be read at
LKPADDR[6:0].
LKPDAT[7:0]
2888[7:0]
0
0
R/W
The dat a for reading and wri ting t he RTC lookup RAM.
LKP_RD
LKP_WR 2889[1]
2889[0] 0
0 0
0 R/W
R/W
Str obe bits for the RT C look up RA M read and write.
When set, the LKPADDR and LKPDAT registers are
used in a read or wri te operati on. When a strobe is
set, it stays set until t he oper ation completes, at whi c h
time the strobe is cleared and LKPADDR is
incremented if
LKPAUTOI
is set.
71M6541D/F/G and 71M6542F/G Dat a S heet
Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value i n STEMP[10:0] right-
shifted by two bits to obtain an 8-bit plus s ign va lue (i.e., NV RAM Address = STEMP/4). A limiter ensures
that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM
content poi nted to by the address is added as a 2’s complement value to 0x40000, the nominal value of
4*RTC_P + RTC_Q.
Refer to 2.5.4.3 RTC Rate Control for inf ormati on on the rate adj ustm ents perform ed by registers
RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C, 0x289D[ 7:2]) and RTC_Q[1:0] (I/O RAM 0x2891[ 1:0]. The 8-bit
values loa ded in to NV RA M mu st be s caled correctly to pro duce r ate adjustment s that are c onsi stent
with the eq uat ions given in 2.5.4.3 RTC R ate Control for RTC_P and RTC_Q. Note that the sum of the
8-bit 2’s compl em ent value looked-up and 0x40000 form a 19-bit value, which is equal to
4*RTC_P+RTC_Q, as shown in Figure 17. T he output of the Tem per ature Com pensation is automati c ally
loaded int o the RTC_P[16:0] and RTC_Q[1:0] locations after each look-up and summati on operation.
Σ
0x40000
19
10+S
STEMP >>2
63
-64
-64 63 255-256
LIMIT Look Up
RAM
ADDR
6+S
8+S Q7+S 4*RTC_P+RTC_Q
19
Figure 17: A utomatic Temperature Compensation
The 128 NV RAM locations are organi z ed in 2’s complement f ormat as sho wn in Table 44. As mentioned
above, the STEMP[10:0] digi tal temper ature val ues ar e scaled su c h that the c orr espon din g NV RA M
addresses are equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See 2.5.5 71M654x Temperature
Sensor on pa ge 56 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
The temperature equation is used to calculate the two temperatur e col um ns in Table 44 (the second
col um n and the rightmost column). The second column uses the full 11-bit values of STEMP[10:0], while
the values in the rightmost colum n ar e cal c ulated using the post-limiter (6+S) values multiplied by 4.
Si nc e eac h look-up table addr ess st ep c or r esponds to a 4 x 0.325 °C temperature step, two is added to
the post-limiter 6+S value after m ultiplying by 4 to calc ulate the temper ature v alues in the rightmost
colu mn. This method ensures that the c om pensation dat a is l oaded int o the look-up table in a manner
that mi nimi z es quantization error . Table 44 shows the numeri c al v alues correspondi ng to each node in
Figure 17. The values of STEMP[10:0] outside the -256 to + 255 r ange ar e not shown in this tabl e. The
lim iter out put is confined to the range of -64 to +63, which i s di r ectly the desir ed addr es s of the 128-byte
look-up table. The rightmost colum n giv es the nomi nal temperature corresponding t o eac h addr es s cell i n
the 128-byte compensation t able
Table 44: NV RAM Temperature Table Structure
STEMP[10:0]
(10+S)
(decimal)
Temp (oC)
(Equation)
STEMP[10:0]>>2
(8+S)
(decimal)
Limiter Output
(6+S)
(decimal)
Temp (oC)
(LU Table)
-256
-61.71
-64 -64 -61.06
-255 -61.39
-254 -61.06
-253
-60.73
…
…
…
…
…
-4 20.69
-1 -1 21.35
-3 21.02
-2 21.35
-1 21.67
71M6541D/F/G and 71M6542F/G Dat a S heet
0 22.00
0 0 22.65
1 22.33
2 22.65
3 22.98
4 23.31
1 1 23.96
5 23.64
6 23.96
7 24.29
…
…
…
…
…
252 104.40
63 63 105.06
253 104.73
254 105.06
255 105.39
For pr oper oper ation, the MPU must load the look up table wit h v alues that reflect the cr y stal pr oper ti es
with respect to tem per ature, which is ty pic ally done once during initializati on. Since the lookup table is
not directly addr essable, the MPU uses the foll owing pr oc edur e to load the entire NV RAM table:
1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
3. Write the 8-bit dat um i nto I/O RAM register LKPDAT (I/O RAM 0x2888).
4. Set the LKP_WR bit (I /O RAM 0 x2889[0]) to write the 8-bit datum into NV_RAM
5. Wait fo r LKP_WR to cl ear (LKP_WR auto-clears when the data has been copi ed to NV RAM).
6. Repeat steps 3 thr ough 5 unti l all data has been wr it ten to NV RAM.
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The pro c ess of
reading from and writi ng to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] auto-incremented every tim e LKP_RD or LKP_WR is pulsed. I t is
also possible t o perfo r m random acces s of the NV RAM by writing a 0 to the LKPAUTOI bit and loading the
desired address into LKPADDR[6:0].
If the oscillator tem per ature compensati on featur e is not being used, it is possible to use the NV
RAM storage area as ordin ar y NV storage space using t he procedure de scrib ed above t o re ad and
wri te NV RAM data. In this case, keep the OSC_COMP bit (I/O RAM 0x28A0[5]) reset to disable the
automatic oscill ator temperature compensation feature.
2.5.4.5 RT C Interrupts
The R TC gener at es inter rup ts each second and eac h mi nute. Thes e interrup ts are ca lled RTC_1SEC and
RTC_1MIN. In add ition, the RTC functions as an alarm clock by generating an interrupt when the minutes
and hour s registers both equal their respective t ar get counts as defined i n Table 45. The alarm clock
interrupt is called RTC_T. All three interrupts appear in t he MPU’s external interrupt 6. See Ta bl e 3 3
in the interrupt secti on for the enabl e bits and fl ags for these interr upts.
The target registers for mi nutes and hours are listed in Table 45.
Table 45: I/ O RAM Regi st ers f or RT C Interru pts
Name
Location
Rst
Wk
Dir
Description
RTC_TMIN[5:0]
289E[5:0]
0
0
R/W
The t ar get minutes register . See RTC_THR[4:0] below.
RTC_THR[4:0]
289F[4:0]
0
0
R/W
The target hours register. The RTC_T interrupt occurs
when RTC_MIN becomes equal to RTC_TMIN and
RTC_HR becomes equal to RTC_THR.
71M6541D/F/G and 71M6542F/G Dat a S heet
2.5.5 71M654x Temperature Sensor
The 71M654x includes an on-c hip temperature s ensor for d eter mining the temp erature of its bandgap
reference. Th e p ri m ar y u se of the t em p er atur e d at a is t o de te rm i ne t h e m a g nit u de of c om pen sa t i on
required to offset the thermal drift in the s ys tem fo r the compensation of current, voltage and energy
measurement and the RTC. See 4.7 Metrology Temperature Compens ation on page 97. Also see 2.5.4.4
RTC T em per ature Compensation on page 53.
Unlike ea r lier generation Teridi an SoC s, the 71M654x does not use t he ADC to rea d the temp er ature
sensor. Instead, it uses a technique t hat i s operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor c an be used to c ompensate f or the f r equenc y v ari ation
of the c rystal, even in SLP mode whil e the MP U is halted. See 2.5.4.4 RTC Temperature Compensation
on page 53.
In MS N and BRN modes, t he temperature sensor is awakened on com mand from the MP U by setting t he
TEMP_START (I/O R AM 0x28B4[6]) control bit. The MPU must wait for the TEMP_START bit to clear before
reading STEMP[10:0] and bef or e setting t he TEMP_START bit onc e again. In SLP and LCD modes, it is
awakened at a r egular r ate set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The resul t of the temperature measurement can be read from the two I/O RAM locati ons STEMP[10:3]
(I/O RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/ O RAM locations must
be read and properly c om bined to form the STEMP[10:0] 11-bit value (see STEMP in Table 46). The
result ing 11-bit v alue is i n 2’s complement f orm and ranges fr om -1024 to +1023 (decimal) . T he equations
below are used t o c alculate the sensed temperature from the 11-bit STEMP[10:0] reading.
The equat ions below are used to calculat e the sensed t emperature. The first equati on applies when the
71M654x is in MSN mode and TEMP_PWR = 1. The second equation applies when the 71M 654x is in
BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must both be set to the sam e value, so
that the battery that supplies the t em per ature sensor is also the battery that is measured and report ed in
BSENSE. Thus, the second equation requires reading STEMP and BSENSE. In the second equation,
BSENSE (the sensed battery voltage) is used t o obtai n a mor e ac c ur ate t em per ature reading when the I C
is in BRN mode.
For the 71M654 x in MSN Mode (with TEMP_PWR = 1) :
22325.0)( +⋅=° STEMPCTemp
For the 71M654x in BRN Mode, (wit h TEMP_PWR=TEMP_BSEL):
4.64609.000218.0325.0)( 2+⋅−⋅+⋅= BSENSEBSENSESTEMPCTemp o
Table 46 shows the I/O RA M registers used for temperatur e and batter y measurem ent.
If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature
measurement may not fi nish. I n this case, firm ware may complete the measurement by selecting
V3P3D (TEMP_PWR = 1).
Table 46: I/ O RAM Regi st ers f or T emperature and Battery Measu rement
Name
Location
Rst
Wk
Dir
Description
TBYTE_BUSY 28A0[3] 0 0 R
Indicat es that hardware i s sti ll writing the 0x28A0
byte. Additi onal wri tes to this byt e are locked out
while it is one. Write duration could be as long as 6 ms.
TEMP_PER[2:0] 28A0[2:0] 0 – R/W
Sets the period between temperature measurements.
Automatic m easurement s can be enabled in any
m ode (MSN, BRN, LCD, or SLP).
TEMP_PER
Time
0
Manual updates (see TEMP_START)
1-6
2 ^ (3+TEMP_PER) (seconds)
7
Continuous
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location Rst Wk Dir Description
TEMP_BAT 28A0[4] 0 – R/W
Causes VBAT to be measured whenever a
temperature measurement is performed.
TEMP_START 28B4[6] 0 – R/W
TEMP_PER[2:0] must be zero in order for TEMP_START
to fu ncti on. I f TEMP_PER[2:0] = 0, then setting
TEMP_START st ar ts a temperat ur e measurement.
Ignored in SLP and LCD modes. Hardware clears
TEMP_START when the temperature measurement i s
complete. The MPU must w ait for TEMP_START to
clear be fore reading STEMP[10:0] and before setting
TEMP_START again.
TEMP_PWR 28A0[6] 0 – R/W
Sel ec ts the power sourc e for the t em perature sensor:
1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in
SLP and LCD modes, where the temperature sensor is
always powered by V B A T_RTC.
TEMP_BSEL 28A0[7] 0 – R/W
Sel ec ts whi c h batter y is monit or ed by the
temperature sensor: 1 = VBA T, 0 = VBAT_RTC
TEMP_TEST[1:0] 2500[1:0] 0 – R/W
Test bits for the temperature monitor VCO.
TEMP_TEST m ust be 00 in regul ar oper ation. Any
other value causes t he V CO to run continuousl y with
the control voltage descri bed below.
TEMP_TEST
Function
00
Normal operati on
01
Reserved for factory test
1X
Reserved for factory test
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
R
R
The resul t of the temperature measurement.
To correctly form STEMP[10:0], the MPU must read
0x 2881[7:0], shift it left by t hr ee bit positions (padding
LSBs with zer os), then read 0x2882[7:5], shift it right
by 5-bi ts (padding the 5 MSBs with z er os), and then
logically OR the two quantities together.
BSENSE[7:0]
2885[7:0]
–
–
R
The resul t of the batter y measurem ent.
BCURR 2704[3] 0 0 R/W
Connects a 100 µA load to the battery sel ec ted by
TEMP_BSEL.
Refer to the 71M6xxx Data S heet for inf ormati on on r eading the tem per ature sensor in the 71M6x01
devices.
2.5.6 71M654x Battery Monitor
The 71M654x temperature measurement circ uit can also monitor the batt er ies at the VBAT and
VBAT_RTC pins. The bat tery to be tested (i. e., V BAT or VBAT_RTC pin) is selected by TEMP_BSEL (I/O
R AM 0x28A 0[7] ).
When TEMP_BAT (I/O R A M 0x2 8A0[4]) is set, a batter y measurement is perfor med as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885). The following equa t ion is used to ca lcu late the voltage meas ur ed on the V BAT pin (o r VBA T_R TC
pin) fro m the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts.
VSTEMPVBSENSEVRTCorVBATVBAT 000276.0]0:10[0246.0)142]0:7[(293.3)_( ⋅+⋅−+=
In MSN mode, a 100 µA de-passivation load can be applied to the selected battery (i.e., selected by the
TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Ba tte ry impedance can be measured by
taking a bat te r y m easurement wi th and with out BCURR. Regardless of the BCURR bit s etting, the battery
load is never applied in BRN, LCD, and SLP modes.
71M6541D/F/G and 71M6542F/G Dat a S heet
Refer to the 71M6xxx Data S heet for inf ormati on on r eading the VCC sensor in t he 71M 6x 01 dev ic es.
2.5.7 UART an d Optical Interface
The 71M6541D/F/G and 71M6542F/G provide two asy nc hr onous int erfaces, UA RT0 and UART1. Both
can be used to conne c t to AMR modu les , use r inte r face s , etc ., and also supp ort a me chan is m for
programming the on-chip flash me mory .
Referring to Figure 19, UART1 incl udes an i nterf ace to im plem ent an IR/optic al por t. The pin OPT_TX is
designed t o direc tly drive an exter nal LE D for transmitting dat a on an optical link. The pin OPT_RX has
the sam e threshold as the R X pin, but c an also be used to sense the input from an external photo detector
used as the rec e iver for the optical link. OPT_TX and OPT_RX are connected to a dedic ated UART port
(UART1).
The O PT_TX and OP T_RX pins can be inverted with configur ation bits OPT_TXINV (I/O RAM 0x2456[0])
and OPT_RXINV ( I/O RA M 0x2457 [1 ]), respectively. Additionall y , t he OPT_T X output may be modulated at
38 kHz. Modulation is available in MSN and BRN modes (see Table 67). The OPT_TXMOD bit (I/O RAM
0x2456[1]) enables modulation. The duty c y cl e is cont rol led by OPT_FDC[1:0] (I/O RAM 0x2457[5:4] ) ,
which can selec t 50%, 25%, 12. 5%, and 6.25% duty cycle. A 6.25% duty cycle means that OPT_TX is
low for 6.25% of the period.
When not needed for UART1, OPT_T X can alt er natively be configured as SEGDIO51. Configuration is
via the OPT_TXE[1:0] (I/O RAM 0x 2456[3:2] ) field and LCD_MAP[51] (I/O RA M 0x24 05[0]). The
OPT_TXE[1:0] f ield allows the MP U to sel ec t VPULSE, WPULSE, SEGDIO 51 or the out put of t he pulse
m odulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be c onfigured
as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).
B
A
OPT_TXMOD = 0 OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
B
A
1/38kHz
OPT_TXINV
from
OPT_TX UART MOD
EN DUTY
OPT_TX
OPT_TXMOD
OPT_FDC
OPT_TXE[1:0]
1
2
V3P3
Internal
AB0
2
3
DIO2
WPULSE
VARPULSE
Figure 18: Optical Interface
Bit Bang ed Opt ical UART (Thi rd UART )
As shown in Figure 19, t he 71M654x can also be conf igur ed to drive the optical UA RT wit h a DIO signal
in a bit banged confi gur ation. When control bit OPT_BB (I/O RAM 0x2022[ 0]) is set, the optic al port is
driven by DIO 5 and the SEGDIO 5 pin is driven by UART1_TX. Thi s confi gur ation is typically used when
the t wo dedic ated UART s must be connec ted to high speed clients and a slower optical UART is
permissible.
71M6541D/F/G and 71M6542F/G Dat a S heet
OPT_TXINV
UART1_TX MOD
EN DUTY
SEGDIO51/
OPT_TX
OPT_TXMOD
OPT_FDC
OPT_TXE[1:0]
0
2
V3P3
Internal
A B
OPT_TXMOD=0 OPT_TXMOD=1,
OPT_FDC=2 (25%)
B
A
1/38kHz
1
2
3
DIO51
WPULSE
VARPULSE SEG51
LCD_MAP[51]
1
0
SEGDIO55/
OPT_RX
SEG55
LCD_MAP[55]
1
0
DIO55
1
0
OPT_RXDIS
UART1_RX
DIO5
SEGDIO5/TX2
SEG5
1
0
LCD_MAP[5]
OPT_BB
0
0
1
1
Figure 19: Optical Interface (UART1)
2.5.8 Digita l I/O and LCD Se gment Drivers
2.5.8.1 General Information
The 71M6541D/F/G and 71M6542F/G combine most DIO pi ns wi th LCD segment drivers. Each
SEG/DIO pin can be configured as a DIO pin or as a segment (SEG) driver pin.
On reset or power-up, all DIO pins are DI O input s (except for SEGDIO0-15, see caution not e below) until
they ar e c onfigured as desired under M P U c ontrol. The pin f unction c an be c onfigured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). S etti ng the bit cor r espondi ng to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 con figures it for DIO.
After reset or power up, pi ns SEGDIO0 through SE GDIO15 ar e initi ally DIO outputs, but are
disabl ed by PORT_E = 0 ( I/O RAM 0x270C[5 ]) to avoid unwanted pulses during r eset. After
configuring pins SEGDIO0 thr ough S EGDIO 15 the MPU must enable these pins by setti ng
PORT_E.
Once a pin is conf igured as DIO, it can be c onfigured independentl y as an i nput or output. For SEGDIO0
to SEGDIO15, thi s i s done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
The PB pin is a dedi c ated digital input and is not par t of the S EGDIO system.
The CE features pulse counting registers and each pulse counter inter r upt output is internally
routed to the pulse i nterrupt logic. Thus, no r outi ng of pulse signal s to ex ternal pins is requir ed in
order t o gener ate pul se i nterr upts. See int er r upt source No. 2 in Figure 16.
A 3-bit confi gur ation word, I/O RAM register DIO_Rn (I/O RA M 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SE GDIO11 (when configured as DIO) and PB to indiv idually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0] , I/O R AM 0x2450[2:0] , configures
the PB pin) . Thi s way, DIO pins can be trac ked even if they ar e configured as outputs. T abl e 47 lists
the internal resources which can be assigned usi ng DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0].
If more tha n one input is con nec ted to the sa me resou rc e, the resources are co mbined us ing a logical O R.
Table 47: S electable Resources using the DIO_Rn[2:0] Bits
Value in DIO_Rn[2:0]
Resou rce S elected fo r SEGDIOn or PB Pin
0
None
1
Reserved
2
T0 (c ounter0 cloc k )
3
T1 (c ounter1 cloc k )
4
High priority I/O interrupt (IN T0)
71M6541D/F/G and 71M6542F/G Dat a S heet
Value in DIO_Rn[2:0]
Resou rce S elected fo r SEGDIOn or PB Pin
5
Low priority I/O interrupt (IN T1)
Note:
Resources are selec tabl e only on SEGDIO 2 through SEG DIO 11 and the
PB pin. See Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
When driving LE Ds, r elay coil s etc ., the DIO pins should sink the current into GNDD (as
shown in Figure 20, right), not source it from V3P3D (as sh own in Figur e 20, le ft). This is due
to t he r esi stanc e of the internal switc h that connect s V3P3D to either V 3P3SYS or VBAT. See
6.4.6 V3P3D Switch on page 143.
S ourcing curren t in or out of DIO pins othe r than tho s e dedicate d for wa ke functions , for
exam ple with pull -up or pull -down resistors, must be avoided. Violati ng this rule leads to
inc r eased qui escent c ur r ent i n sleep and LCD modes.
Figure 20: Connecting an External Load to DIO Pins
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
Not recommended Recommended
71M6541D/F/G and 71M6542F/G Dat a S heet
2.5.8.2 Digital I/O for the 71M6541D/F/G
A total of 32 combined SEG/DI O pins plus 5 SEG outputs are available for the 71M6541D/F/G. These
pins can be categorized as follows:
17 combined SEG/DIO segment pins:
o SEG DIO 4… SEG DIO 5 ( 2 pins)
o SEGDIO9…SEG DIO 14 (6 pins)
o SEGDIO19…SEGDIO25 (7 pins)
o SEG DIO 44… S EGDIO 45 ( 2 pins)
15 combined SEG/DIO segm ent pins shared wit h other functi ons:
o SEG DIO 0/W P ULS E, SEG DIO 1/VP ULS E ( 2 pins)
o SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
o SEG DIO 6/XPULSE, SEGDIO7/ Y P ULS E (2 pins)
o SEG DIO 8/DI (1 pin)
o SEG DIO 26/COM5, SEGDIO 27/CO M 4 (2 pins)
o SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
o SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
5 dedicated SEG segment pins are available:
o ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E _RST ( 3 pins)
o Test Port pins: SEG46/TM UX2OUT, SEG47/TMUXOUT ( 2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that ar e listed under c om bined SEG/DIO shared pins (SEG DIO 26/COM5,
SEGDIO27/COM4).
Thus, in a confi gur ation where none of these pi ns are used as DIOs, ther e c an be up to 37 LCD segment
pins with 4 c ommons, or 35 LCD segment pins with 6 commons. And in a conf iguration where LCD
segment pins are not used, there can be up to 32 DIO pins.
The configurat ion for pins SEGDIO19 to SEGDIO27 is shown in Table 49, and t he c onfigurati on for pins
SEGDIO36-39 and SEGDIO44-45 i s shown in Table 50. SEG 46 to SEG50 c annot be configured for DIO.
The configurat ion for pins SEGDIO51 and SEGDIO55 is shown in Table 51.
Table 48: Dat a/Directio n Regist ers f or SEGDIO0 to SE GDIO14 (71M6541D/F/G)
SEGDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin #
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
–
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
–
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_MAP[14:8] ( I/O R AM 0 x24 0 A)
SEG Data Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
–
LCD_SEG0[5:0] to LCD_SEG14[5:0] (I/O RAM 0x2410[5:0] to 0x241E[5:0]
DIO Data Register
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
–
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (S FR 0xA0)
P3 (S FR 0xB0)
Dir ection Register:
0 = input, 1 = output
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
–
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (S FR 0xA0)
P3 (S FR 0xB0)
Int er nal Resources
Configurable
(see Table 47)
– – Y Y Y Y Y Y Y Y Y Y – – – –
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 49: Dat a/Directio n Regist ers f or SEGDIO19 to SEGDI O 27 (71M6541D/F/G)
SEGDIO
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
Pin #
–
–
–
16
15
14
13
12
11
10
9
8
–
–
–
–
Configuration:
0 = DIO, 1 = LCD
–
–
–
3
4
5
6
7
0
1
2
3
–
–
–
–
LCD_MAP[23:19] ( I/O R AM 0x24 09)
LCD_MAP[27:24] (I/O R AM 0x2408)
SEG Data Register
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
LCD_SEGDIO19[5:0] to LCD_SEGDIO27[5:0]
(I/O RAM 0x2423[5:0]
to
0x242C[5:0])
DIO Data Register
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
LCD_SEGDIO19[0] to LCD_SEGDIO27[0]
(I/O RAM 0x2423[0] to 0x242C[0])
Dir ec tion Register:
0 = input, 1 = output
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
LCD_SEGDIO19[1] to LCD_SEGDIO27[1]
(I/O RAM 0x2423[1] to 0x242C[1])
Table 50: Dat a/Directio n Regist ers f or SEGDIO36-39 to SEGDIO44-45 (71M6541D/F/G)
SEGDIO
–
–
–
–
36
37
38
39
–
–
–
–
44
45
Pin #
–
–
–
–
3
2
1
64
–
–
–
–
63
62
Configuration:
0 = DIO, 1 = LCD
–
–
–
–
4
5
6
7
–
–
–
–
4
5
LCD_MAP[39:36]
(I/O R AM 0 x2407)
LCD_MAP[45:44]
(I/O R AM 0 x2406)
SEG Data Register
–
–
–
–
36
37
38
39
–
–
–
–
44
45
LCD_SEGDIO36[5:0]
to
LCD_SEGDIO45[5:0]
(I/O RAM 0x2434-2437[5:0] to 0x243C-243D[5:0])
DIO Data Register
–
–
–
–
36
37
38
39
–
–
–
–
44
45
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2434-2437[0] to 0x243C-243D[0])
Dir ec tion Register:
0 = input, 1 = output
–
–
–
–
36
37
38
39
–
–
–
–
44
45
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2434-2437[1] to 0x243C-243D[1])
Table 51: Dat a/Directio n Regist ers f or SEGDIO51 and SEGDIO55 ( 71M 6541D/ F/G)
SEGDIO
51
–
–
–
55
–
–
–
Pin # 33 – – – 32 – – –
Configuration:
0 = DIO, 1 = LCD
3
–
–
–
7
–
–
–
LCD_MAP[55], LDC_MAP[51]
(I/O R AM 0 x2405)
SEG Data Register 51 – – – 55 – – –
LCD_SEGDIO51[5:0], LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] and 0x2447[5:0])
DIO Data Register 51
–
–
–
55
–
–
–
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] and 0x2447[0])
Dir ec tion Register:
0 = input, 1 = output
51 – – – 55 – – –
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] and 0x2447[1])
71M6541D/F/G and 71M6542F/G Dat a S heet
2.5.8.3 Digital I/O for the 71M6542F/G
A total of 55 combined SEG/DI O pins are available for the 71M6542D/F. These pins can be categori z ed
as follows:
35 combined DIO/LCD segment pins:
o SEGDIO4…SEG DIO 5 ( 2 pins)
o SEGDIO9…SEGDIO25 (17 pins)
o SEGDIO28…SEGDIO35 (8 pins)
o SEGDIO40…SEGDIO45 (6 pins)
o SEG DIO 52… S EGDIO 53 ( 2 pins)
15 combined DIO/LCD segment pins shared with other functions :
o SEG DIO 0/W P ULS E, SEG DIO 1/VP ULS E ( 2 pins)
o SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
o SEG DIO 6/XPULSE, SEGDIO7/ Y P ULS E (2 pins)
o SEG DIO 8/DI (1 pin)
o SEG DIO 26/COM5, SEGDIO 27/CO M 4 (2 pins)
o SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
o SEG DIO 51/O P T_TX, SEGDIO55/OPT_RX (2 pins)
5 dedi c ated SEG segment pins are available:
o ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E _RST ( 3 pins)
o Test Port pins: SEG46/TM UX2OUT, SEG47/TMUXOUT ( 2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that ar e listed under c om bined S EG/DIO shared pins (SEG DIO 26/COM5,
SEGDIO27/COM4).
Thus, in a confi gur ation where none of these pi ns are used as DIOs, ther e c an be up to 55 LCD segm ent
pins with 4 c ommons, or 53 LCD segment pins with 6 commons. And in a conf iguration where LCD
segment pins are not used, there can be up to 50 DIO pins.
Example: SEGDIO12 (see pin 32 in Table 52) is confi gured as a DIO output pin with a value of 1 (high) by
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is confi gur ed as
an LCD driver by writi ng 1 to bi t 4 of LCD_MAP[15:8]. The di spl ay inf ormation i s written to bits 0 to 5 of
LCD_SEG12.
The configurat ion for pins SEGDIO16 to SEGDIO31 is shown in Table 53, the c onfiguration for pi ns
SEGDIO32 to SEGDIO45 is shown in Table 54. SEG46 through S E G50 cannot be confi gur ed as DIO
pins. The configuration for pins SEGDIO51 to SEGDIO55 i s shown in Table 55.
Table 52: Dat a/Directio n Regist ers f or SEGDIO0 to SEGDIO15 (71M6542F/G)
SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29
Configuration:
0 = DIO, 1 = LCD 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
LCD_MAP[7:0] (I/O RAM 0x240B) LCD_MAP[15:8] ( I/O R AM 0 x 240 A)
SEG Data Regi ster 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RA M 0x2410[5:0] to 0x241F[5:0]
DIO Data Register
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
P0 (SFR 0x80) P1 (SFR 0x90) P2 (SFR 0xA0) P3 (SFR 0xB0)
Dir ection Register:
0 = input, 1 = output
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
7
P0 (SFR 0x80) P1
(
SFR 0x0) P2 (SFR 0xA0) P3 (SFR 0xB0)
Int er nal Resources
Configurable
(see Table 47)
– – Y Y Y Y Y Y Y Y Y Y – – – –
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 53: Dat a/Directio n Regist ers f or SEGDIO16 to SEGDIO31 (71M6542F/G)
SEGDIO
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin #
28
27
25
24
23
22
21
20
19
18
17
16
11
10
9
8
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[23:16] ( I/O R AM 0 x2409)
LCD_MAP[31:24] ( I/O R AM 0 x2408)
SEG Data Regi ster
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
DIO Data Register
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
Dir ec tion Register:
0 = input, 1 = output
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
Table 54: Dat a/Directio n Regist ers f or SEGDIO32 to SEG DIO 45 (71M6542F/G)
SEGDIO
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Pin #
7
6
5
4
3
2
1
100
99
98
97
96
95
94
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
LCD_MAP[39:32]
(I/O R AM 0 x2407)
LCD_MAP[45:40]
(I/O RAM 0x2406[5:0])
SEG Data Register
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LCD_SEGDIO32[5:0]
to
LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
DIO Data Register
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
Dir ec tion Register:
0 = input, 1 = output
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
Table 55: Dat a/Directio n Regist ers f or SEGDIO51 to SEG DIO 55 (71M6542F/G)
SEGDIO
51
52
53
54
55
–
–
–
Pin #
53
52
51
47
46
–
–
–
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
–
–
–
LCD_MAP[55:51]
(I/O RAM 0x2405[7:3])
SEG Data Register
51
52
53
54
55
–
–
–
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
DIO Data Register
51
52
53
54
55
–
–
–
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
Dir ec tion Register:
0 = input, 1 = output
51
52
53
54
55
–
–
–
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
71M6541D/F/G and 71M6542F/G Dat a S heet
2.5.8.4 LCD Drivers
The LCD drivers are grouped i nto up to six commons (COM 0 – COM5) and up to 56 segment drivers.
The LCD interfac e is flexi ble and can driv e 7-segment digits, 14-segments di gits or enunciator symbols.
A volt age doubler and a contr ast DA C gener ate VLCD from either V BAT or V3P 3S YS, depending on the
V3P3SYS voltage. The voltage doubler, w hile capable of driving into a 500 kΩ load, is abl e to generate a
m aximum LCD voltage that is within 1 V of twic e the supply voltage. T he doubler and DAC operate fro m
a trimmed low-power referenc e.
The configur ati on of the VLCD generati on is contr olled by the I/ O RAM field LCD_VMODE[1:0] (I /O RAM
0x2401[7:6]). It is decoded int o the LCD_EXT, LDAC_E, and LCD_BSTE i nternal signals. Table 56
detail s the LCD_VMODE[1:0] configurations.
Table 56: LCD_VMODE[1:0] Configurations
LCD_VMODE [1:0] LCD_EXT
LDAC_E LCD_BSTE Description
11
1
0
0
Ext er nal V LCD c onnec ted to the VLCD pin.
10 0 1 1
See note 2 below for the definiti on of V3P 3L.
LCD boost is enabl ed. The maximu m VLCD pin
voltage is 2*V3P3L-1.
In general, the V LCD pin v oltage is as follows:
VLCD = max(2*V3P3L-1, 2.5(1+
LCD_DAC[4:0]
/31)
01 0 1 0
LCD boost is dis abled. The maxi mum VLCD
volt ag e is V3P 3L.
VLCD = max(V3P3L, 2.5V+2.5*LCD_DAC[4:0]/31)
00 0 0 0
VLCD=V3P3L, LCD DAC and LCD boost are
disabled. In LCD m ode, t his setting causes the
lowest battery current.
Notes:
1. LCD_EXT, LDAC_E and LCD_BSTE are 71M654x internal si gnals whi c h ar e dec o d ed f rom
the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded
signals, when as sert ed, has the effect indic ated in the descri pti on c olum n abov e, and as
summar ized below.
LCD_E X T : When s et, the V LCD pin expect s an external supply v oltage
LD A C_ E : Wh e n set , LCD DA C i s en a bl ed
LCD_BSTE : When set, t he LCD boost ci rcuit is enabled
2. V3P3L is an int ernal supply rail that is su ppl ied from either the VBAT pin or the V3P3SYS
pin, depending on t he V3P3SYS pin v oltage. Whe n t he V 3P 3S Y S pin dr op s b el ow 3.0 V DC,
the 7 1M 65 4x swi t ch e s to BRN mo de and V 3P3L is sourc ed from the VBAT pin, othe rwise
V 3P3L is sourc ed fr om the V3P3S Y S pin whil e in M S N mo de.
When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0])
value to ensure that the LCD manufacturer’s recommended operating voltage specification is not
exceeded.
The voltage doubl er is active in all LCD modes incl uding the LCD mode when LCD_BSTE = 1. Curr ent
dissipat ion in LCD mode c an be r educ ed if t he boost ci rcuit is disabled and t he LCD system is operated
directly from VBAT.
The LCD DAC uses a low-power referenc e and, within the constrai nts of VBAT and the volt age doubler,
generates a VLCD voltage of 2.5 VDC + 2.5 * LCD_DAC[4:0]/31.
The LCD_BAT bit (I/O RAM 0x2402[7]) causes the LCD system to use the batt ery voltage in all power
modes. This may be usef ul when an ext ernal s up ply is availa ble for th e LCD system. Th e advan ta ge of
connecting t he external supply t o VBAT, rather than VLCD is that the LCD DA C is still active.
If LCD_EXT = 1, the VLCD pin m ust be driven fr om an ext er nal source. In this case, the LCD DA C has
no eff ec t.
71M6541D/F/G and 71M6542F/G Dat a S heet
The LCD sys te m has th e abilit y to dr ive up to six segments per SEG driver. If the display i s configured with
six back planes , the 6-way multiplexing co mpres s es the number of SEG pi ns r equired t o drive a dis pla y and
therefore enhance the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field
(I/O RAM 0x2400[ 6:4]) settings (Table 57) f or th e different LCD mul ti plexi ng choice s. If 5-state
multiplexing is selec te d, S E GD IO27 is converted to COM4. If 6-state multiple xing is selected, SEGDIO26
is con verted to COM5. These conversions override the SEG/DIO mapping of SEGDIO26 and SEGDIO27.
Addi ti onally , i nde pen dent of LCD_MODE[2:0], if LCD_ALLCOM = 1, then SE GDIO26 and S E GDIO27
becom e COM4 and COM5 if their LCD_MAP[ ] bits are set.
The LCD_ON (I/O RAM 0x2 40C[0]) and LCD_BLANK (I/O RAM 0x240C [1 ]) bit s are an easy way to either
blank the LCD display or tur n it f ully on. Neit her bit affects the cont ents of the LCD data stored in t he
LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) cl ear s all LCD data t o zero.
LCD_RST aff ec ts only pins that are c onfigured as LCD.
A small am ount of power c an be saved by progr amming the LCD frequenc y to t he lowest value
that provides satisfactory LCD visibilit y over the required temperature range.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 57 shows all I/O RAM register s that cont r ol the operation of the LCD interface.
Table 57: LCD Configurations
Name Location Rst Wk Dir Description
LCD_ALLCOM 2400[3] 0 – R/W
Configures all 6 SEG/COM pins as COM. Has no effect
on pins whose LCD_MAP bit is zero.
LCD_BAT
2402[7]
0
–
R/W
Connects the LCD power suppl y to VBAT in all m odes.
LCD_E 2400[7] 0 – R/W
Enabl es the LCD display . When disabled, VLC2,
VLC1, and V LC0 ar e gr ound as are t he COM and S EG
outputs if their LCD_MAP b it is 1.
LCD_ON
LCD_BLANK 240C[0]
240C[1] 0
0 – R/W
R/W
LCD_ON = 1 turns on al l LCD segments without
aff ec ting the LCD data. Similarly, LCD_BLANK = 1
turns off all LCD segments wi thout affecting t he LCD
data. If both bits are set, all LCD segm ents are tur ned
on.
LCD_RST 240C[2] 0 – R/W
Clear all bits of LCD data. These bit s affect SEGDIO
pins that are configured as LCD drivers.
LCD_DAC[4:0] 240D[4:0] 0 – R/W
This register c ontrols the LCD contrast DA C, which
adjusts the V LCD voltage and has an output r ange of
2.5 VDC to 5 VDC. The VLCD voltage is
VLCD = 2. 5 + 2.5 * LCD_DAC[4:0]/31
Thus, t he LS B of the DAC is 80.6 mV. The maximum
DAC output volt age is limited by V3P3S YS, VBAT, and
whether LCD_BSTE is se t.
LCD_CLK[1:0] 2400[1:0] 0 – R/W
Sets the LCD clo ck frequency (1/T) . See de finit ion of T
in Figure 21. Note: fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
LCD_MODE[2:0] 2400[6:4] 0 – R/W
The LCD bias and mu ltiplex mode.
LCD_MODE
Output
000
4 states, 1/ 3 bias
001
3 states, 1/ 3 bias
010
2 states, ½ bias
011
3 states, ½ bias
100
Static display
101
5 states, 1/ 3 bias
110
6 states, 1/ 3 bias
LCD_VMODE[1:0] 2401[7:6] 00 00 R/W
This register specif ies how VLCD is generated.
LCD_VMODE
Description
11
Ext er nal V LCD
10
LCD boost and LCD DAC
enabled
01
LCD DAC enabl ed
00
No boost and no DAC. VLCD
= VBAT or V3P3SYS
The LCD can be driven in static , ½ bias, and 1/3 bias modes. Figure 21 defin es the COM waveforms.
Note t hat COM pins that are not r equir ed in a specif ic mode maint ain a ‘segment of f’ state rather than
GND, V CC, or high im pedanc e.
T h e se gm ent d river s SEGDIO22 and SE GDIO23 c a n be co nf i gu r ed t o bli n k at either 0.5 Hz or 1 Hz .
Th e bl ink rate is contr olled by LCD_Y (I/O RAM 0x240 0[2]). There c an be up to six pixels/segments
connect ed to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x240 2[5:0])
and LCD_BLKMAP23[5:0] (I/O RAM 0x240 1[5:0]) identify whic h pixels, if any, are to bli nk.
LCD_BLKMAP22[5:0] and LCD_B LKMAP23[5:0] are non-volatile.
71M6541D/F/G and 71M6542F/G Dat a S heet
The LCD bias may be compensated for temper ature using t he LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]).
The bias may be adjusted fr om 1.4 V below the 3. 3 V supply ( V 3P 3S YS in MSN mode and VBAT i n BRN
and LCD mode s) . When the LCD_DAC[4:0] f ield is set to 0 00, the DAC is bypas s ed and powe r ed
down. T his can be used to reduc e c ur r ent in LCD mode.
STATI C (LCD_MODE=100)
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(1/2)
(1/2)
(1/2)
(1/2)
(1/2)
1/2 BIA S , 2 STATES (LCD_MODE = 010 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(1/2)
(1/2)
(1/2)
(1/2)
0 1 1/2 BIA S , 3 STATES (LCD_MODE = 011 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(1/2)
(1/2)
(1/2)
012
1/3 BIA S , 3 STATES (LCD_MODE = 011 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(2/3)
012
(1/3)
1/3 BIA S , 4 STATES (LCD_MODE = 000 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
0 1 2 1/3 BIA S , 6 STATES (LCD_MODE = 110 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
012
3 3 4 5
T
Figure 21: LCD Waveforms
71M6541D/F/G and 71M6542F/G Dat a S heet
LCD Dri vers ( 71M 6541D/F/G)
With a maximum of 35 LCD driver pins available, t he 71M6541D/F/G is capable of driving up to 6 x 35 =
210 pixels of an LCD displ ay when using the 6 x multiplex mode. At eight pix els per digit, this
correspond s to 26 digit s.
LCD segment data is written t o the LCD_SEGn[5:0] I/O RAM r egisters as descr ibed i n 2.5.8.2 and 2.5.8.3.
SEG 46 through S E G50 cannot be confi gur ed as DIO pins. Display data f or these pins are written to I/O
RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 58). When the I CE _E pi n is pull ed
high, it overri des the S E G func tionality, and pins E_RXTX/SEG 48, E_TCLK/SEG49 and E_RST/ S EG50
functi on as ICE interface pins.
LCD_MAP[46] and LCD_MAP[47] (I/O RAM 0x 2406[6] and 0x2407[7] ) m ust be set to 1 in order to permit
TMUX2OUT/SEG 46 and TMUXOUT/ S EG47 to operate as SEG drivers, otherwise. If LCD_MAP[46] and
LCD_MAP[47] are 0, these pins operat e as TM U2XOUT and TMUXOUT ( see 2.5.12 Test Ports
(TM UXOUT and T M UX2OUT Pins) on page 78).
Table 58: 71M 6541D/F/G LCD Data Registers for S EG46 t o SEG50
SEG
46
47
48
49
50
Pin #
61
60
38
37
36
Configuration Al ways LCD pins, except
when used for ICE interface
or TM UXOUT/ TMUX2OUT.
SEG Data Register
LCD_SEG46[5:0]
LCD_SEG47[5:0]
LCD_SEG48[5:0]
LCD_SEG49[5:0]
LCD_SEG50[5:0]
71M6541D/F/G and 71M6542F/G Dat a S heet
LCD Dri vers ( 71M6542F/G)
With a maximum of 56 LCD driver pins available, t he 71M6542D/F is capable of driving up to 6 x 56 = 336
pixels of an LCD displ ay when us ing the 6 x multiplex mode. At eight pix els per digit, this corr espond s to
42 digits.
LCD segment data is written t o the LCD_SEGn[5:0] I/O RAM r egisters as descr ibed i n 2.5.8.3 Digital I/ O
for the .
SEG 46 through S E G50 cannot be confi gur ed as DIO pins. Display data f or these pins are written to I/O
RAM fields LCD_SEG46[5:0] (I/O RA M 0x243 E [5:0 ]) through LCD_SEG50[5:0] (I/O RAM 0x2442 [5:0 ]); see
Table 59. The associated pins function as ICE interface pi ns, and the ICE functionality overrides the LCD
functi on whenever ICE_E is pulled high.
Table 59: 71M6542F/G LCD Data Regi st ers f or SEG46 to SEG 50
SEG
46
47
48
49
50
Pin # 93 92 58 57 56
Configuration: Always LCD pins, except
when used for ICE interface
or TM UXOUT/ TMUX2OUT.
SEG Data Register
LCD_SEGDIO46[5:0]
LCD_SEGDIO47[5:0]
LCD_SEGDIO48[5:0]
LCD_SEGDIO49[5:0]
LCD_SEGDIO50[5:0]
2.5.9 EEPROM Interface
The 71M6541D/F/G prov ides hardware supp or t for either a two-pi n or a three-wire (µ-wire) type of
EEPROM interface . T he interfaces use the SFR EECTRL (SFR 0x9F) and EEDATA (SFR 0x 9E )
registers for communication.
2.5.9.1 Two-pin EEPROM Interface
The de di cat ed 2-pin s er ial inter face communicat es with ext ernal EEPROM devices and is intended for
use wit h I2C devices. The inter face is multiplexed ont o the SEGDIO2 (SDCK) and SEGDIO3 (SDATA)
pins and i s selected by setti ng DIO_EEX[1:0] = 01 (I /O RAM 0x2456[7:6 ]). The MPU communic ates with
the in terface through the SFR registers EEDATA and EECTRL. If the MPU wishes t o wri te a byte of dat a
to the EEPROM, it places the data in EEDATA and then wri tes the Transmit c ode to EECTRL. This
initi ates the t r ansmit oper ation which is finished when the BUSY b it falls. INT 5 is also asserted when
BUSY falls. The MPU can then chec k the RX_ACK bit t o see if the EE P ROM acknowledged t he trans-
mission.
A byt e is read by wri ting the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive cl oc k is 78 kHz duri ng eac h
transm ission, an d then holds in a high st ate unt il the n ext transm ission. The EECTRL bits when the
two-pin i nterface is select ed ar e shown i n Table 60.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 60: EECTRL Bits for 2-pin Interf ace
Status
Bit
Name Read/
Write
Reset
State
Polarity Description
7
ERROR
R
0
Positive
1 when an il legal comm and is receiv ed.
6
BUSY
R
0
Positive
1 when serial data bus i s busy.
5
RX_ACK
R
1
Positive
1 indic ates that the E E P ROM sent an ACK bit.
4 TX_ACK R 1 Positive
1 indicates that an ACK bit has been sent to the
EEPROM.
3:0 CMD[3:0] W 0000 Positive
CMD[3:0]
Operation
0000
No-op command.
0010
Receive a byte fr om the EEPROM
and send ACK.
0011
Transmit a byte to t he EEPROM.
0101
Issue a ST OP sequence.
0110
Receive the last by te from the
EEPROM and do not send ACK.
1001
Issue a ST A RT sequence.
Others
No operation, set the ERROR bit.
The EE P ROM i nterf ac e c an also be operat ed by c ontrolling the DIO2 and DIO3 pins directly. The
dir ec tion of the DIO line c an be changed from input to out put and an output v alue c an be written
with a single write operati on, t hus avoiding collisions (see Table 15 Port Registers (SEG DIO0-15)).
Therefore, no r esi stor is required in series SDATA to protec t against c ollisions.
2.5.9.2 Three-wire ( µ-Wire) EEPROM Interface with Single Data Pin
A 500 kHz three-wire int erfac e, using S DA TA, SDCK, and a DIO pin for CS is available. The interface is
selected by sett ing DIO_EEX[1:0] = 10. The EECTRL bits when the thr ee-wire interface is selected are
shown in Table 61. When EECTRL is written, up to 8 bits from EEDATA are either writt en to the EEPROM
or read f r om the E EPRO M, depending on the values of t he EECTRL bits.
2.5.9.3 Three-wi re ( µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins
If DIO_EEX[1:0]=11, the three-wire interface is the same as abov e, exc ept DI and DO are separate pi ns.
In t his case, SE GDIO3 becom es DO and SEGDIO8 becomes DI. The timing diagr am s are t he same as
for DIO_EEX[1:0]=10 ex c ept that all out put dat a appear s on DO and all input data is expected on DI. I n
this mode, DI is ignor ed while data is bei ng received on DO. T his mode is compati ble with SPI modes 0,0
and 1,1 where data is shifted out on the falling edge of the cl ock and is strobed i n on the rising edge of
the clock.
Table 61: EECTRL Bits for the 3-wire In t erf ace
Control
Bit Name Read/
Write Description
7 WFR W
Wait fo r Ready . If this bit is set, the trailing edge of BUSY is delayed until
a rising edge is seen on the data line. This bit can be used during the
last by te of a Wri te command to cause the INT5 interrupt to occur when
the EE P ROM has finished its internal write sequence. Thi s bit is i gnor ed
if Hi-Z=0.
6 BUSY R A sserted whil e the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
5 HiZ W
Indicates that the SD signal is to be floated to high impedance immediately
aft er the last SDCK rising edge.
71M6541D/F/G and 71M6542F/G Dat a S heet
4
RD
W
Indicat es that EEDATA (S FR 0x9E) i s to be filled w ith data from EEPR OM.
3:0 CNT[3:0] W
Specif ies the number of cloc k s to be issued. Allowed val ues are 0
through 8. If RD=1, CNT bits of data are read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits are sent
MSB first to the EE P ROM, shift ed out of the MSB of EEDATA. If
CNT[3:0] i s zero, SDATA simply obeys the HiZ bit.
The timing diagrams in Figure 22 through Figure 26 describe t he 3-wir e E E P ROM interface behavior. All
commands begin when the EECTRL (SFR 0x9F) register is written. Transactions start by first raising the
DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 22
through Figure 26 are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read tr ansact ion, the EE P ROM is
drivi ng SDATA, but transi ti ons to Hi-Z (h igh impedance) when CS falls. The firmware should then
immediately issue a write c om mand wi th CNT=0 and HiZ= 0 to take control of SDATA and force it t o a
low-Z state.
Figure 22: 3-wire Interface. Write Command, Hi Z=0.
Figure 23: 3-wire Interface. Write Command, Hi Z=1
Figure 24: 3-wire Interface. Read Command.
SCLK (output )
BUSY (bit)
CNT Cycles (6 s hown)
SDATA (output)
Wr ite -- No HiZ
D2D3D4D5D6D7
EECTRL Byt e Wri t ten INT5
SDATA output Z
(LoZ)
CNT Cycles (6 s hown)
Wr ite -- With HiZ
INT5
EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (output) D2D3D4D5D6D7
(HiZ)(LoZ)
SDATA output Z
CNT Cycles (8 s hown)
READ
D0D1D2D3D4D5
INT5
D6D7
EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (i nput)
SDATA output Z
(HiZ)
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 25: 3-W ire Interface. Write Command whe n CNT=0
Figure 26: 3-wire Interface. Write Command wh en HiZ=1 and WF R=1.
2.5.10 SPI Slave Port
The slave SPI port comm unic ates directly with t he M PU data bus and i s abl e to read and write Dat a RAM
and I/ O R AM locations. I t is also abl e to send commands t o the MPU. The interface to t he slave por t
consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. T he s e pin s are multiplexed with the
combined DIO/ LCD segment driver pins SEG DIO36 to SEGDIO39.
Addi tionall y , t he SPI i nterface allows flash mem or y to be read and to be progr ammed. To fac ilitate flash
programming, cycling power or asserting RE S E T causes the SPI port pins to default to SPI m ode. The
SPI port is disabl ed by cl ear ing the SPI_E bit (I/O RAM 0x 27 0C[4]).
Possible applications for the SPI interface are:
1) An external host reads data from CE l oc ations to obtain meteri ng information. This can be used in
applications where t he 71M654x functi on as a smart front-end with pr epr oc essing capability. Sinc e
the addres se s are in 16-bit form at, any type of XRAM dat a c an be ac c essed: CE, MPU, I/O RAM, but
not SFRs or t he 80515-int er nal r egister bank.
2) A communication link can be established via the SPI interface: By w riting into MPU memory locations,
the external host can initi ate and control proc esses in the 71M654x MPU. Writing to a CE or MPU
loc ation normally generates an i nterrupt, a function that can be used to si gnal to the MPU that the
byte that had just been wri tt en by the external host must be read and pr oc essed. Data can also be
insert ed by the external host without generating an interrupt.
3) An external DSP can access f r ont -end data generat ed by the A DC. Thi s mode of operat ion uses the
71M654x as an analog f r ont-end (AFE).
4) Flash programm ing by the external host (S P I Fl ash Mode).
SPI Transactions
A ty pic al S PI transact ion is as follows. While SPI_CSZ is high, the port is hel d in an initialized/r eset state.
Duri ng this st ate, S PI_DO is held in Hi-Z st ate and all transi tions on SPI_CLK and SPI_DI are ignored.
When SPI_CSZ fall s, the port begins the transact ion on the fir st ri si ng edge of SP I_CLK. As shown in
Tabl e 62, a tr an sa ct ion c on si st s of an opti o nal 16 bit a ddr e ss, a n 8 bit com m and, an 8 bi t status byte,
follow ed by one or more bytes of dat a . The transa c t ion ends when SP I_CS Z is ra ised . Some trans ac tions
m ay consist of a command only.
CNT Cycles (0 s hown)
Wr ite -- No HiZ
D7
INT5 not issued CNT Cycles (0 s hown)
Wr ite -- HiZ
INT5 not issued
EECTRL Byt e Wri t ten EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (output)
SCLK (output )
BUSY (bit)
SDATA (output)
(HiZ)
SDATA output ZSDATA output Z
(LoZ)
CNT Cycles (6 shown)
Write -- With HiZ and WFR
EECTRL Byte Writte n
SCLK (output)
BUSY
(bit)
SDATA (out/in)
D2
D3
D4
D5
D6
D7
BUSY
READY
(From EEPROM)
INT5
(From 654x)
SDATA output Z
(HiZ)
(LoZ)
71M6541D/F/G and 71M6542F/G Dat a S heet
When SPI_CSZ rises , SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR
0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was
a singl e by te. I n this case, the SPI_CMD byte is always updated and the i nterr upt issued. SPI_CMD is not
cl ear ed when SPI _CS Z is high.
The SP I port supports data transfers up to 10 Mb/ s. A serial r ead or write operation requires at least 8
cl oc k s per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring t hat SPI
access to DRA M is al ways possibl e.
Table 62: SPI Transac tion Fields
Field
Name Required Size
(bytes) Description
Address Yes, except for
single-byte
transaction
2 16-bit address. The address field is not required if t he
transaction is a simple SPI command.
Command Yes 1 8-bit command. This byte c an be used as a command to t he
MPU. In multi-byte transactions, t he M SB is the R/W bit.
Unless the transaction is multi-byte and SPI_CMD is exactly
0x 80 or 0x 00, t he SPI_CMD register is updated and an S P I
interrupt is is s ued. Otherwis e, the SPI_CMD register is
unchanged and the i nterrupt is not issued.
Status
Yes, if transaction
includes DATA
1
8-bit status field, indicating t h e st at u s of th e pr evi ou s
transaction. This byte is also available in the MPU me mory
map as SPI_STAT (I/O RAM 0x2708) register. See Table 64
for the contents.
Data
Yes, if transaction
inc ludes DATA
1 or
more
The read or wri te data. Address is auto incremented for
each new byte.
The SPI_STAT byte is output on ev er y SPI transaction and i ndicates the parity of the pr ev ious tr ansact ion
and the err or status of the pr ev ious tr ansact ion. Potential error sources are:
• 71M654x not ready.
• Transaction not ending on a by te boundary.
SPI Safe Mode
Sometim es it is desirable to prevent t he S PI interface from writing to ar bitrary RAM l oc ations and thus
distur bing MP U and CE operati on. This is especially true in AFE applications. For this reason, t he S P I
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer
regi on at address 0x400 t o 0x 40F. If the SPI host needs to writ e to other addresses, i t must use the
SPI_CMD register to request the writ e operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/ O RAM 0x270C[3]).
Single-Byte Transaction
If a transact ion is a singl e byte, the byte is inter pr eted as SPI _CM D. Regardless of the byte value, single-
byte transactions always update the SPI_CMD register and cause an SPI i nterr upt to be generated.
Multi-Byte Transaction
As shown in Figure 27, multi-byte operations consist of a 16 bit address f ield, an 8 bit CMD, a stat us byt e,
and a sequence of data byt es. A multi byt e transact ion is three or more bytes.
71M6541D/F/G and 71M6542F/G Dat a S heet
A15 A14 A1 A0 C0
0 31
x
D6 D1 D0 D7 D6 D1 D0
C5C6C7
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 654x) SPI_DO
8 bit CMD
16 bit Address DATA[ADDR] DATA[ADDR+1]
15 16 23 24 32 39 Extended Read . . .
SERIAL READ
A15 A14 A1 A0 C0
C5C6C7
x
8 bit CMD16 bit Address DATA[ADDR] DATA[ADDR+1]
Extended Write . . .
SERIAL WRITE
D6 D1 D0 D7 D6 D1 D0 x
HI Z
HI Z
Status Byte
ST7 ST6 ST5 ST0 D7
40 47
0 31
15 16 23 24 32 39 40 47
Status Byte
D7
ST7 ST6 ST5 ST0
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 654x) SPI_DO
Figure 27: SP I Slave Port - Typical Multi-Byte Read and Write operations
Table 63: SPI Command Sequences
Command Sequ ence Description
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
Read data starti ng at ADDR. ADDR auto-increments u ntil SPI_CSZ is
rai sed. Upon c om pletion, SPI_CMD (SFR 0xFD) is updated to 1 xxx xxxx
and an SPI interrupt is generated. T he excepti on is if the command byte
is 1000 0000. In this case, no MP U interr upt is generated and SPI_CMD
is not updated.
0xxx xxxx ADDR Byte0 ...
ByteN
Write data starting at ADDR. ADDR auto-increments until SPI_CSZ is
rai sed. Upon c om pletion, SPI_CMD is updat ed to 0xxx xxxx and an SPI
interrupt is generated. The exc eption is if the command byte is 0000
0000. I n this case, no MPU interrupt is generated and SPI_CMD is not
updated.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 64: SPI Regi st ers
Name
Location
Rst
Wk
Dir
Description
EX_SPI
2701[7]
0
0
R/W
SPI interrupt enable bit.
SPI_CMD
SFR FD[7 :0]
–
–
R
SPI command. The 8-bit command from the bus master.
SPI_E 270C[4] 1 1 R/W
SPI por t enable bit. It enables the SPI interf ac e on pins
SEGDIO36 – SEGDIO39.
IE_SPI
SFR F8[7]
0
0
R/W
SPI interrupt flag. Set by hardw ar e, c leare d by wr it ing a 0.
SPI_SAFE 270C[3] 0 0 R/W
Limits SP I writes to SPI_CMD and a 16 byte region in
DRAM when set . No ot her wr ite operations are per mitted.
SPI_STAT 2708[7:0] 0 0 R
SPI_STAT contains the status result s from the pr ev ious
SPI transaction.
Bit 7: Ready error : The 71M654x was not r eady to read
or writ e as di r ec ted by the previous comm and.
Bit 6: Read data parity: This bit is the pari ty of all byt es
read from the 71M654x in t he pr ev ious comm and. Does
not include t he SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the
bytes writ ten to the 71M654x i n the previous command.
It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not includ e
A DDR and CMD b y tes. One, two, an d three byte
instructions retur n 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST
pin is zero.
Bit 0: SPI F LASH mode r eady : Used in SPI FLAS H
m ode. I ndic ates that the fl ash i s ready to receiv e
another wri te i nstr uc tion.
71M6541D/F/G and 71M6542F/G Dat a S heet
SPI Flash Mode (SFM)
In norm al oper ati on, the SPI slave interface cannot r ead or writ e the fl ash memory. However, the
71M6541D/F/G and 71M6542F/G support an SPI Flash Mode (SFM) which facilitates initial program m ing
of the flas h memory. When in SFM mode, the SPI can erase, read, and wri te the flash memory. Other
m em ory elements such as XRAM and I /O RA M are not accessible in this mode. In order to protect the
flash content s, several operations are requir ed before the SF M mode is successf ully invok ed.
In SFM mod e, n by te reads and dual-byte writes to flash memory are supported. See the SPI Transac t ions
description on Page 73 for the format of read and write commands. Since the flash write operation is always
base d on a two-by te word, the initi al addr ess must always be even. Data is writ ten to the 16-b it flash
memory bus after the odd word is writ ten.
In SFM m ode, t he MPU is completely halted. For this reason, the interr upt feature described in t he SPI
Transact ion section above is not av ailable in SFM mode. The 71M6541D/F/G and 71M6542F/G m ust be
reset by t he WD timer or by the RESET pin in or der to exit SFM m ode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
• Pin ICE_E = 1. T his di sabl es the watchdog and adds anot her layer of protecti on against inadvertent
Flash corrupti on.
• The ext er nal power source (V3P3SYS, V3P3A) is at the proper lev el (> 3.0 VDC).
• PREBOOT = 0 (SFR 0xB2[7]). Thi s validates the state of the SECURE bit (SFR 0xB2[6]).
• SECURE = 0. Thi s I/O RAM register indicat es that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
• FLSH_UNLOCK[3:0] (I/O RAM 0x2702[ 7:4]) = 0010.
The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to in voke SFM. Only
the SP I int erface has access to these two regi sters. T his eliminates an i ndir ec t path from the MPU f or
disabl ing t he watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
se que ntial write proc ess prevents i nadvertent entering of SFM.
The sequence for inv oki ng SFM is:
• Firs t, w rite to the SFMM (I /O RAM 0x2080) register. The value wri tt en to this register defines the SF M
mode.
o 0x D1: Mass Erase mode. A Fl ash Mass erase cycle is invoked upon entering SFM.
o 0x2E: Flash Read back mode. SFM is ent er ed f or Flash read back purposes. Fl ash writ es
are not be blocked and it is up to the user to guar antee that only pr ev iously unwrit ten
loc ations are writ ten. This mode i s not accessibl e when S P I secure mode is set.
o SFM is not invok ed if any other patter n is writ ten to the SFMM register.
• Next , write 0x96 to the SFMS (I /O RAM 0x2081) register. This action invokes SF M provi ded that the
prev ious write oper ation to SFMM met the requirements. Writing any other pattern to this register does
not in voke SFM. Additionally, any write operati ons to this register automatic ally r eset the previousl y
written SFMM register values to zero.
71M6541D/F/G and 71M6542F/G Dat a S heet
SFM details
The following occurs upon entering SFM.
• The CE is disabled.
• The MPU is halted. Once the MP U is halt ed it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by c y cli ng power (wit hout batt er y at the
VBAT pin).
• The Flash cont r ol logic is reset in case the MPU was i n the middle of a Flash writ e operation or Erase
cycle.
• Mass erase is in voked if specified in the SFMM register, I/O RAM 0x2080 (see I nv oki ng SFM , above).
The SECURE bit (SFR 0xB2[6]) is cl ear ed at t he end of thi s and al l M ass Erase cycles.
• All SPI read and writ e operations now refer to Fl ash i nstead of XRAM space.
The SP I host can ac c ess the curr ent state of t he pending multi-cycle Flash access by performing a 4-byte
S PI write of any address and check ing the status field.
All SPI write operations in SF M m ode must be 6-byt e wri te transacti on that writes t wo bytes to an ev en
address. T he wri te transactions must c ontain a command byte of the form 0xxx xxxx. Auto increm enting
is di sabl ed for write operations.
SPI r ead transact ions can make use of auto increm ent and may access si ngle bytes. The command byte
m ust always be of the form 1xxx xxxx in SFM read transacti ons.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is described in
the SP I T r ansact ions description on Page 73.
2.5.11 Hardw are Wat chd o g Ti mer
An independent, r obust, fix ed-dur ation, watchdog timer (WDT) is incl uded in the 71M6541D/F/G and
71M6542F/G. It uses the RTC c rystal oscillator as its time base and m ust be ref reshed by the MPU
firmware at least every 1.5 second s. When not refr eshed on time, the WDT overflows and t he par t is
reset as if the RESET pin were pulled high, ex c ept t hat the I/O RAM bit s are in the same stat e as after a
wake-up from SLP or LCD modes (see the I/O RAM descript ion in 5.2 I/O RAM Map – Alphabetical Or der
for a li st of I/O RAM bit stat es after RESET and wake-up) . After 4100 CK32 cycles (or 125 ms) following
the WDT overflow , the MPU is launched fro m progra m address 0x0000.
The watchdog t imer i s al so reset when the internal signal WAKE=0 ( see 3.4 Wak e Up B ehav ior).
For detail s, see 3.3.4 Watchdog Timer Reset.
2.5.12 Test P o r ts (TMUXOUT and TMUX2OUT Pins)
Two independent multipl ex er s all ow the selec tion of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I /O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or anal og si gnals listed in
Table 65 can be select ed to be out put on the TMUXOUT pin. The function o f the multip lexer is controlled
with t he I/ O RAM register TMUX[5:0 ] (I/O RAM 0x25 02[5:0], as shown in
Table 65.
One of the digital or anal og si gnals listed in Table 66 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
show n in Table 66.
The TMUX[5:0] and TMUX2[4:0] I/O RAM locations are non-volatile and their contents are preserved
by battery power and across resets.
71M6541D/F/G and 71M6542F/G Dat a S heet
The TMUXOUT and TMUX2OUT pins may be us ed for diagnos tics purposes during t he pr oduc t
dev elopment cy cl e or in the production test. The RTC 1-second out put m ay be used to c alibr ate the
crystal oscil lator. The RTC 4-second output provides higher precision for RTC calibration. R TCLK may
also be used to cali br ate the RTC.
Table 65: TMUX[5:0] Selections
TMUX[5:0] S ign al Nam e Description
1
RTCLK
32. 76 8 kHz clock waveform
9 WD_RST Indicat es wh en the MPU h as res et t h e watc h d og tim er. C an b e
monitored to determine spare time in the watchdog timer.
A
CKMPU
MPU clock – see Table 9
D V3AOK bit
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P 3SYS pi ns are exp ec ted to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
E V 3O K bit
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P 3SYS pi ns are exp ec ted to be tied tog eth er at th e PCB l evel .
The 71M654x monitors the V3P3A pin v oltag e on ly.
1B MUX_SYNC Internal multiplexer frame SYNC signal. See Figure 6 and Figure
7.
1C
CE_BUSY interrupt
See 2.3.3 on p age 25 and Figure 16 on pag e 47
1D
CE_XFER interrupt
1F RTM output from CE See 2.3.5 on pag e 25
Note:
All TMUX[5:0] v alues whi ch are not shown are reserved.
Table 66: TMUX2[4:0] Selections
TMUX2[4:0] Signal N ame Description
0 WD_OVF Ind icat es when the w atc h dog ti m er h as e xp ired (ov er f l ow ed).
1 PULSE_1S
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC fro m an ideal 1 se cond
interval. Multiple cycles should be averaged togethe r to filter out
jitter.
2 PULSE_4S
Four second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 4 se cond
interval. Multiple cycles should be averaged togethe r to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 seco nd pulse.
3
RTCLK
32. 76 8 kHz cl oc k wav eform
8
SPARE[1] bit – I/O RA M
0x2704[1]
Copies the value o f the bit sto red in 0x2704[1]. For general
purpose use.
9 SPARE[ 2] bit –
I/O RA M
0x2704[2] Copies the value of the bit stored in 0x2704[2]. For general
purpose use.
A
WAKE
Indicates when a WAKE event has occurred.
B MUX_SYNC
Internal multiplexer frame SYNC signal. See Figure 6 and Figure
7.
C
MCK
See 2.5.3 on p age 50
E
GNDD
Digital GND. Use this signal to make the TMUX2OUT pin static.
12 INT0 – DIG I/O
Int err u pt 0. S ee 2.4.8 on page 40. Also see Figure 16 on page 47.
13
INT1 – DIG I/O
14
INT2 – CE_PULSE
15 INT3 – CE_BUSY
16
INT4 - VSTAT
17
INT5 – EEPROM/SPI
18
INT6 – XFER, RTC
1F RTM_CK (flash) See 2.3.5 on p ag e 25.
Note:
All TMUX2[4:0] valu es w hic h are not s h ow n are res er v ed.
71M6541D/F/G and 71M6542F/G Dat a S heet
3 Functional Description
3.1 Theory of Operation
The energy deliver ed by a power source int o a load can be expr essed as:
∫
=
t
dttItVE
0
)()(
Assum ing phase angles are constant, the following f ormulae appl y:
P = Real Energy [W h] = V * A * cos φ* t
Q = Reactive Energy [VARh] = V * A * sin φ * t
S = Apparent Energy [VAh] =
22 QP +
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic cont ent
may change constant ly. Thus , s imp le RM S meas ure me nts are inhe ren tly inac cur ate. A modern solid-state
elec tricity meter IC such as the Teridian 71M654x functions by emul ating the integral oper ation abov e,
i.e., i t proc esses current and voltage samples thr ough an ADC at a constant frequency. As long as the
ADC resoluti on is hi gh enough and the sample frequenc y is beyond t he har monic range of interest, the
current and voltage samples, m ultipli ed with the time period of sampli ng yi eld an ac c ur ate quant ity f or the
m om entary ener gy . S umming up the momentary ener gy quantiti es over time results in very accurat e
result s for accumulated energy.
Figure 28: Voltage, Current, Moment ary and Accumul at ed Energ y
Figure 28 shows the shapes of V(t), I(t) , t he m omentar y power and the accumulated power, resulting from
50 samples of the voltage and c ur r ent signals over a peri od of 20 ms. The applic ation of 240 VAC and
100 A results in an ac cumulation of 480 Ws (= 0.1 33 Wh) over the 20 ms period, as i ndicate d by the
accumulated pow er c ur ve. The described sampling method works reliably, even in the presence of dynamic
phase shift and harmonic distor tion.
-500
-400
-300
-200
-100
0
100
200
300
400
500
0 5 10 15 20
Current [A ]
V oltage [V]
Energy per I nterval [Ws]
A ccumulated Energy [Ws]
71M6541D/F/G and 71M6542F/G Dat a S heet
3.2 Battery Modes
Short ly aft er system power (V3P 3S Y S ) is applied, the part is in mission mode (MSN mode). MSN mode
m eans that the part is operat ing wi th syst em power and that the i nternal PLL is stabl e. This mode is the
normal operati ng m ode where the par t is capable of measuring energy .
When system power is not available, the 71M654x is in one of thre e ba t tery modes:
• BRN mode (br ownout mode)
• LCD mode ( LCD-only mode)
• SLP mode (sleep mode).
An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are
typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 3.0 VDC, the
c omparator resets an internal power status bit called V3OK . As s oon as system po wer is rem oved and
V3OK = 0, the 71M654x switches to ba ttery power (VB A T pin) , notifies the MP U by issuing an inte rrupt and
updates the VSTAT[2:0] regis ter (SFR 0xF9[2:0], see Table 68). T he MPU continues to execute code when
the system transit ions from MSN to BRN mode. Refer to 3.2.1 BRN Mode for the setti ngs that result in the
lowest pos si ble power duri ng B RN m ode. Depending on the M P U code, the MP U can choose to stay in
BRN mode, or transi tion to LCD or to SLP mode (via the I/O RAM bits LCD_ONLY, I/O RAM 0x28B2[6] and
SLEEP, I/O RAM 0x28B2[7]). BRN mode is similar to MSN mode except that resources powered by V3P3A
power, such as the ADC are inaccur ate. In BRN mode the CE conti nues to r un and shoul d be turned off
to conserve VBAT power. Also, the PLL continues to f unc ti on at t he same f r equenc y as i n MSN mode
and its frequenc y shoul d be r educ ed to save power (CKGN = 0x24 (I/O RAM 0x2200).
When system power is restored, the 71M654x automatically transitions from any of the batt er y m odes
(BRN, LCD, SLP ) back to MSN m ode, switches back to using system power (V3P3SYS , V3P3A), i ssues
an interrupt and updat es VSTAT[1:0]. T he MPU software shoul d r estor e MSN m ode oper ation by issuing
a soft reset to restore system setti ngs to v alues approp r iat e for MSN mode.
Figure 29 shows a state diagram of the various operating modes, with the possible transitions betw een modes .
When the part wakes-up under batter y power, the part automatic ally enters BRN mode (see 3.4 Wake Up
Behavior). From BRN mod e, the p ar t may enter eithe r LCD mod e or SLP mode, as contr olled by the MPU.
Figure 29: O peration Mod es State Diagram
V3P3SYS
rises
V3P3SYS
falls
MSN
BRN
LCD
SLEEP or
VBAT
insufficient
System Power
Battery Power
LCD_ONLY
RESET &
VBAT
sufficient
RESET
Wake Flags
Wake
event
RESET &
VBAT
insufficient
V3P3SYS
rises
V3P3SYS
rises
SLP
Wake
event
VBAT
insufficient
VBAT
insufficient
VSTAT=001VSTAT=00X
71M6541D/F/G and 71M6542F/G Dat a S heet
Transi ti ons fr om both LCD and SLP mode to BRN mode can be initiated by the following e vents:
• Wake-up timer timeout.
• Pushbutton (PB) is activated.
• A rising edge on SEGDIO4, SEGDIO52 (71M6542F/G only) or SEGDIO 55.
• Activ ity on the RX or OPT_RX pi ns.
The MP U has access to a variety of registers that si gnal the event t hat caused the wake up. See 3.4
Wake Up Behavior for detail s.
Table 67 shows the ci r c uit f unc tions available in each operating mode.
Table 67: Available Circuit Functions
Cir c uit Funct io n
System Pow er
Battery Power
MSN (M is s ion Mode )
BRN (Br ownout Mode)
LCD SLEEP
PLL_FAST=1
PLL_FAST=0
PLL_FAST=1
PLL_FAST=0
CE (Computation Engine)
Yes
Yes
Note 1
Note 1
--2
--
FIR
Yes
Yes
--
--
--
--
ADC, VREF
Yes
Yes
--
--
--
--
PLL
Yes
Yes
Yes
Yes
Boost2
--
B attery M eas urem en t
Yes
Yes
Yes
Yes
--
--
Temperature senso r
Yes
Yes
Yes
Yes
Yes
Yes
Max MPU clock rate
4.92MHz
(from PLL)
1.57MHz
(from PLL)
4.92MHz
(from PLL)
1.57MHz
(from PLL)
-- --
MPU_DIV clk. divide r
Yes
Yes
Yes
Yes
--
--
ICE
Yes
Yes
Yes
Yes
--
--
DIO Pins
Yes
Yes
Yes
Yes
--
--
Watchdog Timer
Yes
Yes
Yes
Yes
--
--
LCD
Yes
Yes
Yes
Yes
Yes
--
LCD Boost
Yes
Yes
Yes
Yes
Yes
EEPROM Interface (2-wire)
Yes
Yes
Yes
Yes
--
--
EEPROM Interface (3-wire)
Yes
Yes
Yes
Yes
--
--
UART (full speed)
Yes
Yes
Yes
Yes
--
--
Optical TX modulation
38.4kHz
38.9kHz
38.4kHz
38.9kHz
--
--
Flash Read
Yes
Yes
Yes
Yes
--
--
Flash Page Erase
Yes
Yes
Yes
Yes
--
--
Flash Wri te
Yes
Yes
Yes
Yes
--
--
RAM Read and Write
Yes
Yes
Yes
Yes
--
--
Wakeup Timer
Yes
Yes
Yes
Yes
Yes
Yes
OSC and RTC
Yes
Yes
Yes
Yes
Yes
Yes
DRAM data preservation
Yes
Yes
Yes
Yes
--
--
NV RAM data pre servation
Yes
Yes
Yes
Yes
Yes
Yes
Notes:
1. The CE is active in BRN mode, but ADC data is inaccurate . The MPU should halt the CE to conse rve power (CE_E = 0,
I/ O RAM 0x2106[0]).
2. “--“ indicates that the c orresponding circuit is not active
3. “Boost” implie s that the LCD boost c ircuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6]). The LCD b oos t
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is a ctive wh ile in
LCD m od e, other wise t h e PLL is de-activated.
71M6541D/F/G and 71M6542F/G Dat a S heet
3.2.1 BRN Mod e
In BRN mode, most non-metering digital functions are activ e (as shown in Table 67) incl uding ICE, UART,
EEPROM, LCD and RTC. In BRN mode, the PLL continues to f unc tion at the same frequency as MSN
m od e. I t i s up t o th e MP U to s c al e do wn t h e PL L ( u sin g P LL_FA ST, I/ O RA M 0x220 0[ 4] ) or the MPU
frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order t o save power .
From BRN mode, the MPU can choose to enter LCD or SLP modes. When system power is restored
while the 71M654x is in BRN mode, the part automati cal ly transitions to MSN mode.
The rec ommended minimum power conf iguration for BRN mode is as follows:
• RCE0 = 0x 00 ( I/O RAM 0x270 9[7:0]) - remot e sensors disabled
• LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT
• LCD_VMODE[1:0] = 0 (I/O RAM 0x24 01[7:6]) - 5V LCD boost disabled
• CE6 = 0x00 (I/O RAM 0x2106) - CE, RTM and CHOP are disabl ed
• MUX_DIV[3:0] = 0 (I/O RAM 0x2100[ 7:4]) - the ADC multiplexer is disabled
• ADC_E = 0 ( I/O RAM 0x27 04[4]) - ADC disabled
• VREF_CAL = 0 (I/O RAM 0x2704[7]) – Vref not driven out
• VREF_DIS = 1 (I/O RAM 0x2704[6]) - Vref disabl ed
• PRE_E = 0 (I /O RA M 0x27 04[ 5] - pre-am p disabl ed
• BCURR = 0 (I/O RAM 0x2704[3]) - battery 100µA current load OFF
• TMUX[5:0] = 0x0E (I/ O RAM 0x2502[5:0]) – TMUXOUT output set to a dc value
• TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set to a dc val ue
• CKGN = 0x24 (I/O RAM 0x2200) - PLL s et slo w, MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum
• TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - temp measurement set to aut om atic ev er y 512 s
• TEMP_BSEL = 1 (I/O R AM 0x28 A0 [7 ]) - temperature sensor monitor s VBA T
• PCON = 1 (SFR 0x87) - at the end of the main BRN loop, halt the MPU and wait for an interr upt
• The baud rat e r egister s are adjusted as desired
• All unused i nterrupts are disabl ed
3.2.2 LCD Mode
LCD m ode m ay be commanded by t he MPU at any time by setting the LCD_ONLY control bit ( I/O RAM
0x28B2[6]). However, it is recommended that the LCD_ONLY cont r ol bit be set by the MPU only a fter the
71M654x has entered BRN m ode. For example, if the 71M654x i s i n MSN mode when LCD_ONLY is set,
the durati on of LCD mode is v er y bri ef and t he 71M654x imm ediatel y 'wakes'.
In LCD mode, V3P3D is disabled, thus removing al l current leakage from the VBAT pin. Bef or e assert ing
LCD_ONLY mode, i t is recommended t hat t he MPU minimi z e P LL current by reduci ng the out put
frequency of the PLL to 6.2 MHz (i.e., write PLL_FAST = 0, I/O RAM 0x2200[4]). The LCD boost system
requi r es a clock from the PLL for its operation. T hus, if the LCD boost system is enabl ed (i .e.,
LCD_VMODE[1:0] = 10, I/O RAM 0x2401 [7:6 ]), then the PLL is automatically kept active during LCD
mode, otherwise the PLL is de-activated.
In LCD mode, the data contained in the LCD_SEG registers is di spl ay ed usi ng the segment driver pins.
Up to two LCD segment s connected to the pins SEGDIO22 and SEGDIO 23 c an be m ade to blink without
the involvem ent of the MP U, which is di sabl ed in LCD m ode. To minimize battery power consumption,
only segments that are used should be enabled.
After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x0000, the
XRAM is i n an undefined state, and configuration I/O RAM bits are reset (see Table 76 for I/O RAM state
upon wake). T he data stored in non-volatile I/O RAM lo cations is preserved in LCD mode (the shaded
locations in Table 76 are non-volatile).
71M6541D/F/G and 71M6542F/G Dat a S heet
3.2.3 SLP Mode
When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x ent er s BRN mode and the V3P3D
pin obtai ns power f r om the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may
inv ok e S LP mode by setting the SLEEP bit (I/ O RAM 0x 28B2[7]). The purpose of SLP mo de is to
consume the least amount po wer whi le s ti l l maintaining the RTC (Rea l Time Cloc k ), temperature
compensation of the RTC, and the non-volat ile por tions of the I/ O RAM .
In SLP mode, the V3P3D pin is disconnected, rem ov ing all sources of current leakage from the VBAT pin.
The non-volatile I/O RAM locations and the SLP mode functions, such as the temper ature sensor,
oscill ator, RTC, and the RTC tem per ature c om pensation are powered by the VBA T_RT C pin. SLP mode
can be exit ed only by a system power-up event or one of the wake met hods descri bed in 3.4 Wake Up
Behavior.
If the SLEEP bit is as s erted w hen V3P3SYS pin power is present (i.e., w hile in MSN mode), t he 71M654x
enters SLP mode, resetting the internal WAKE signal, at whic h point the 71M 654x begins the standard
wake fr om sl eep pr oc edur es as described i n 3.4 Wake Up Behavior.
When power is restored t o the V3P3S Y S pi n, the 71M654x transitions from SLP mode to MSN mode and
the MPU PC (P r ogr am Counter) is initialized to 0x 0000. At this poi nt, the XRAM is in an undefined stat e,
but non-volatile I/O RAM loc ations are preserved (the shaded locat ions in Table 76 ar e non-volatile).
71M6541D/F/G and 71M6542F/G Dat a S heet
3.3 Fault and Reset Behavior
3.3.1 Events at Power-Down
Power f ault detection is performed by internal co mparators that monitor the voltage at the V3P3A pin and
also monitor the internally generat ed VDD pin voltage (2.5 VDC). The V3P 3SYS and V 3P 3A pins must be
tied together at the PCB l evel, so that the com par ators, whi c h ar e internall y c onnec ted only to the V3P3A
pin, are able to simultaneously m onitor the common V3P3SY S and V 3P 3A pin voltage. The following
discussi on as sumes that the V3P3A and V3P3S Y S pi ns are ti ed together at the PCB level.
Duri ng a power failure, as V3P3A falls , two thresholds are detected:
• The first threshold, at 3. 0 VDC (VSTAT[2:0] = 001), warns t he M P U that the analog modules are no
longer ac c ur ate. O ther than warning t he M P U, t he hardware take s no act ion when thi s thr eshol d is
crossed.
• The second threshol d, at 2.8 VDC, causes the 71M654x t o switc h to battery power. This switching
happens while the FLASH and RAM systems are still able to read and writ e.
The power qualit y i s refl ec ted by the SFR VSTAT[2:0] field, as shown in Table 68. The VSTAT[2:0] field is
loc ated at SFR address 0xF 9 and oc c upies bits [2:0], and it i s read-only.
In addition to t he state of t he m ain power, the VSTAT[2:0] register provides information about the internal
VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the
71M6541D/F/G and 71M6542F/G always switch fr om battery to system power.
Table 68: VSTAT[2:0] (S FR 0xF9[2:0])
VSTAT[2:0] Description
000
System Power OK. V3P3A > 3.0 VDC. Anal og m odules are f unc tional and accurate.
001
System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Anal og m odules not accur ate.
Switc h ov er to bat tery power is imminent.
010
The I C is on battery power and V DD is OK. VDD > 2.25 VDC. The IC has full digital
functionality.
011
The I C is on battery power and 2. 25 V DC > VDD > 2.0 VDC. Flash wri te operations are
inhibited.
101
The I C is on battery power and V DD < 2.0, whic h m eans that the MPU is nearly out of
voltage. A reset oc c ur s i n 4 cycles of the cr ystal cl oc k CK32.
The respon se to a system power fault is almost entir ely cont r olled by f irm ware. Duri ng a power failure,
system power slowly f alls. Th is is monitored by internal comparators that cause the hardware to
automati c ally switc h ov er to t aki ng power fr om the VBAT input. An inter r upt notifies the MP U that the par t
is now battery powered. A t this poi nt, it is the MPU’s respon si bility to r educ e power by slowing the clock
rate, disabling the PLL, etc.
Precision analo g compone nts such a s the bandgap reference, th e ba ndgap buff er , an d the ADC are
powered only by the V3P3A pin and becom e inac c ur ate and ultim ately unavailable as the V3P 3A pin
voltage c ontinues t o drop (i.e., ci rcuits powered by the V3P3A pin are not back e d by the VBAT pin).
When the V3P3A pin falls below 2.8 VDC, the AD C c lo cks are halte d a nd the amplifiers are unbiased.
Meanwhil e, cont r ol bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O R AM
storage i s po wered from the V DD pin ( 2.5 VDC). The VDD pin is suppli ed with power through an internal
2.5 VDC r egulator t hat is connect ed to the V3P3D pin. In turn, the V3P 3D pin is swi tched to r ec eive
power fr om the VBAT pin when the V3P3SYS pin drops below 3.0 VDC. Not e that the V3P3SYS and
V3P3A pins are typically tied t ogether at the P CB level.
71M6541D/F/G and 71M6542F/G Dat a S heet
3.3.2 IC Behavior at Low Batter y Voltage
When system power is not pr esent, the 71M6541D/F/G and 71M6542F/G rely on the VBAT pin for power.
If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate
reliably. Low VBAT voltage c an occur while the part i s operati ng in BRN mode, or whil e it is dormant in
SLP or LCD mode. Two cases can be distingui shed, depending on MP U c ode:
• Case 1: System power is not pr esent, and the part is waking f r om SLP or LCD mode. I n this case,
the hardware check s the value of VDD to determine if proces sor operati on is possi ble. If it is not
possible, the part confi gur es itself for BRN operation, and holds the processor in reset (WA K E=0) . In
this mode, VBAT powers the 1.0 VDC reference for the LCD syst em, the VDD regulator, the PLL, and
the fault comparator. The part remains i n this wait ing mod e unt il VDD bec omes hig h due to s ystem
power bei ng applied or the VBAT battery being r eplaced or recharged.
• Case 2: The part is operat ing under VBAT power an d VSTAT[2:0] (SFR 0xF9[2:0]) becom es 101,
indicating that VDD f alls bel ow 2.0 VDC. In this case, the firm ware has two choices:
1) One c hoice is to a s s ert the SLEEP bit (I/O RAM 0x28B2[ 7]) i m mediately. This assertion
preserves t he remaining charge in VBAT. Of course, if the battery voltage is not increased, the
71M654x enters Case 1 as soon as it tries to wake up.
2) The alternative choice is to enter the waiting mode described in Case 1 immediately. Specifically, if the
firmware does not assert the SLEEP bit, the hardware resets the processor four CE32 clock cycles (i.e.,
122 µs) after VSTAT[2:0] becomes 101 and, as described in Case 1, it begins waiting for VDD to
become great er than 2.0 VDC. The MPU wakes up when system power r eturns, or when VDD
becomes greater than 2.0 VDC.
In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2])
can be read t o determine that the proc essor is recover ing from a bad VBAT conditi on. The WF_BADVDD
flag remains set until the next time WA KE f alls. This flag is independent of the other WF flags.
In all cases, low VBAT v oltage does not corrupt RTC operati on, t he state of NV memory , o r the state of
non-volatile memory. These circuits depend on the VBAT_RTC pin f or power.
3.3.3 Reset Sequence
When the RESET pin is pulled high, all di gital activit y i n the chip stops, with the exc eption of the oscillator
and RTC. Additiona lly, all I/O RA M bits are f or c ed to t heir RST state. Rel iable reset does not oc c ur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC do not reset unless the TEST pin
is pul led high while RESET is high.
The RESET control bit (I/ O RAM 0x 2200[3]) performs an i dentical reset to t he RE SET pi n except that a
significantly shorter r eset timer is used.
Once initiated, the reset sequence w aits until t he r eset timer times out. The time-out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences f r om
address 0x0000. S ee 2.5.1.1 Hardware Watchdog Timer for a detailed descri ption of the pre-boot and
boot sequences.
If system power i s not pr esent, the r eset timer duration is two CE32 cy c les, at which time the MPU begins
ex ec uting in BRN mode, star ting at address 0x0000.
A softer form of r eset is i nit iated when t he E_RST pin of the ICE inte r fac e is pul le d low. This event
cause s the M P U and other registers i n the MP U core t o be reset but does not r eset the remainder of the
IC, for example the I/O RAM. It does no t tr igger the res e t seque nce . Th is type of reset is intended to reset
the MP U pr ogr am, but not to mak e other c hanges to the chip’s state.
3.3.4 Wat ch do g Ti mer Reset
The watchdog t imer (W DT) is described i n 2.5.11 Hardware Watchdog Time r.
A status bit, WF_OVF (I/O RAM 0x28B0[4]), is s et wh en a WDT overflow occu rs. Similar to th e other wake
flags, this b it is pow ered by the non-volat ile supply an d ca n be read by the MPU t o determine if th e part is
initial izing after a WD overflow event or after a po wer up. The WF_OVF bit is cleared by the RESET pin.
71M6541D/F/G and 71M6542F/G Dat a S heet
There is no inter nal digital state that could deactivate the WDT. For debug purposes, ho wever, t he WDT
can be di sabl ed by r aising the ICE_E pin to 3.3 VDC.
In normal operation, the WDT is re s et by perio dicall y writ ing a on e to the WD_RST control bit (I/O RAM
0x28B4[7]). The watchdog ti mer is al so reset when the 71M654x wakes from LCD or SLP mode, and
when ICE_E = 1.
3.4 Wake Up Behavior
As de scribed above, the part always wake s-up in MSN mode when system power is restor ed. As
described in 3.2 Battery Modes, trans itions from both LCD and SLP mode to BRN mode can be initia ted
by a wake-up timer timeout, when t he pushbutton (PB) input is high, a high le vel on SEG DIO 4,
SEG DIO 52 or SEG DIO 55, or by activity on the RX or OPT_RX pins.
3.4.1 Wake on H ard w ar e Ev en t s
The following pin s ignal events wake the 71M654x from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin (71M6542F/G
only), or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 69 for de-bounce
details on each pin and for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52
(71M6542F/G only), and SEGDIO 55 pins must be configured as DIO inputs and their wake enable (EW_x
bits) must be set. In SLP and LCD modes, the MPU is held in reset an d cannot poll pins or react to
interrupts. When one of t he hard ware wake events occ urs, the internal WAKE signal ris es and within
three CK3 2 c yc le s the MPU be gin s to ex ec ute. The MPU can determine which one of the pins
awakened i t by checking the WF_PB, WF_RX, WF_SEGDIO4, WF_DIO52 (71M6542F/G only), or
WF_DIO55 flags (see Table 69).
If the part is in SLP or LCD mode , it can be aw akene d by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so i t may be pulled high by a push button depr ession.
Some pins are de-bounced to r ejec t EMI noise. Detection hardware ignores all transitions after the initial
transition. Table 69 shows whi c h pins are equi pped with de-bounce circuitry.
Pi ns that do not have de-bounce cir c uits must stil l be high for at least 2 µs to be recognized.
The wake enable and fl ag bits are also shown in Table 69. T he wake fl ag bits are set by har dware when
the MP U wakes f r om a wake event. Not e that the PB flag is set whenev er the PB i s pushed, even if the
part is already awake.
Table 71 lists the events that cl ear the W F fl ags.
In addition to push butt ons and timer s, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x220 0[ 3]), the WDT, the col d s t art det e ct or, an d E_R ST. A s s ee n in Ta ble 69, each of these
m ec hanisms has a flag bi t to al ert the MPU to the s ource of the wakeu p. If the wake-up i s cau sed by
return of system power, there is no a ctive WF flag and the VSTAT[2:0] field (SFR 0x F9[2:0]) indicate that
syste m pow er is stab le .
Table 69: Wake Enables and Flag Bits
Wake Enable
Wake Fl ag
De-bounce Description
Name
Location
Name
Location
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake on Time r.
EW_PB
28B3[3]
WF_PB
28B1[3]
Yes
Wake on PB*.
EW_RX 28B3[4] WF_RX 28B1[4] 2 µs Wake on either edge of RX.
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2 µs
Wake on SEGDIO4.
EW_DIO52† 28B3[1] WF_DIO52 28B1[1] Yes Wake on SEGDIO52*.
EW_DIO55 28B3[0] WF_DIO55 28B1[0] Yes
OPT_RXDIS = 1: Wak e on DIO 55*
with 64 ms de-bounce.
OPT_RXDIS = 0: Wake on either
71M6541D/F/G and 71M6542F/G Dat a S heet
Wake Enable Wake Flag De-bounce Description
Name Location Name Location
edge of OPT_RX wit h 2 µs de-
bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Al ways Enabled
WF_RST
28B0[6]
2 µs
Wak e after RESET.
Al ways Enabled
WF_RSTBIT
28B0[5]
No
Wak e after RESET bit.
Al ways Enabled WF_ERST 28B0[3] 2 µs
Wake after E_RST.
(ICE m ust be enabled)
Al ways Enabled
WF_OVF
28B0[4]
No
Wake after WD reset.
Al ways Enabled WF_CSTART
28B0[7] No
Wake after cold star t - the first
application of power.
Al ways Enabled WF_BADVDD
28B0[2] No
Wake after insuff icient VBAT
voltage.
† 71M6542F/G only.
*This pin is sampled every 2 ms and must remai n high for 64 ms to be declared a v alid high level. T his
pin is high-level s ensitive.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 70: Wake Bi t s
Name
Location
RST
WK
Dir
Description
EW_DIO4 28B3[2] 0 – R/W
Connects SEGDIO4 to the WAK E l ogic and permits
SEGDIO4 rising to wake the part . T his bit has no effect
unless SEGDIO4 is conf igured as a digital i nput.
EW_DIO52 28B3[1] 0 – R/W
Connects DIO52 to the W AKE logic and permits DIO52
high-level to wake the part (71M6542F/G only). Thi s bit
has no effect unl ess DIO52 is conf igured as a di gital
input.
EW_DIO55 28B3[0] 0 – R/W
Connects DIO55 to the W AKE logic and permits DIO55
high-level to wake the part . Thi s bit has no effect unless
DIO 55 is conf igured as a di gital input.
WAKE_ARM 28B2[5] 0 – R/W
Arms the WAKE timer and loads i t wit h the value in the
WAKE_TMR register (I/O RAM 0x2880). When SLP
mode or LCD mode is assert ed by the MPU, the WAKE
timer becomes active.
EW_PB 28B3[3] 0 – R/W
Connects the PB pin t o the W AKE logic and permits PB
high-level to wake the part . PB is always conf igured as
an input.
EW_RX 28B3[4] 0 – R/W
Connects the RX pin t o the W AKE logic and permits RX
rising t o wake the part. See 3.4.1 for de-bounce issues.
WF_DIO4 28B1[2] 0 – R
SEGDIO4 flag bit. If SEGDIO4 is configur ed to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO 4 is not c onfigured for wakeup.
WF_DIO52 28B1[1] 0 – R
SEGDIO52 flag bit. If SEGDIO52 is configured to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not c onfigured
for wakeup (71M6542F/G only).
WF_DIO55 28B1[0] 0 – R
SEGDIO55 flag bit. If SEGDIO55 is configured to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not configur ed
for wakeup.
WF_TMR
28B1[5]
0
–
R
Indicates that the Wake timer caused the part to wake up.
WF_PB
28B1[3]
0
–
R
Indicat es that t he PB pin caused the par t to wake.
WF_RX
28B1[4]
0
–
R
Indicat es that RX pin c aused the par t to wake.
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
*
*
*
*
*
– R
Indicat es that t he RST pin, E_RST pin, RESET bit (I/O
RAM 0x2200[3]), the cold start detector, or l ow voltage
on the VBAT pin caused the part to reset.
*See Table 71 f or details.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 71: Cl ear E vents fo r WAKE flags
Flag
Wake on :
Clear Events
WF_TMR Timer expiratio n WAKE falls
WF_PB
PB pin high level WAKE falls
WF_RX
Ei ther edge RX pin
WAKE falls
WF_DIO4
SEG DIO 4 rising edge WAKE falls
WF_DIO52 SEGDIO52 high level (71M6542F/G only) WAKE falls
WF_DIO55
If OPT_RXDIS = 1 (I/O RAM 0x245 7[2 ]),
wake on SEGDI O55 high
If OPT_RXDIS = 0
wake on either edge of OPT_RX
WAKE falls
WF_RST
RESET pin driven high
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_OVF, WF_BADVDD
WF_RSTBIT RESET bi t is set (I/O RAM 0x2200[3]) WAKE falls, WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
WF_ERST
E_RST pin driven high and the ICE
interface m ust be enabled by driving the
ICE_E pin high.
WAKE falls, WF_CSTART, WF_RST,
WF_ OVF , WF_R S TBIT
WF_OVF
Watchdog (WD) reset
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
WF_CSTART Coldstart (i .e., after the applicati on of fi r st
power) WAKE falls, WF_RSTBIT, WF_OVF,
WF_BADVDD, WF_RST
Note:
“WA K E falls” implies that the internal WAKE signal has been reset, whic h happens automatic ally upon
entry into LCD mode or SLEEP mode (i .e., when the MPU sets the LCD_ONLY bit (I/O RAM 0x28B2[6]) o r
the SLE E P (I/O RAM 0x28B2[7]) bit). W hen the int er nal WAKE si gnal resets, all wake flags are reset.
Si nc e the vari ous wake f lags are autom atically r eset when WAK E falls, it is not necessary f or the MP U to
reset these flags before ent eri ng LCD m ode or SLEE P mode. Also, ot her wake events can cause the
wake flag to reset, as indi c ated above (e.g. , t he WF_RST fl ag can al so be reset by any of the following
flags set ti ng: WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD)
3.4.2 Wake on Timer
If the part is i n S LP or LCD mode, it c an be awakened by t he Wak e T imer. Until this timer times out, the
MPU is in r eset due to the internal WAKE signal bei ng low. W hen the Wake Timer times out, WAKE rises
and within thr ee CK32 cycl es, the MPU begins to ex ecute. The MPU can determine that the timer woke it
by checking the WF_TMR wake flag (I/O RAM 0x28B1[2]).
The Wake Timer begins timing when the part enters LCD or SLP mode. Its durati on is cont r olled by the
va lue in the WAKE_TMR[7:0] register (I/O RAM 0x2880) . The timer duration is WAKE_TMR +1 seconds.
The Wake T imer i s armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2[5]). It must be armed at least
three RTC cycles bef or e either SLP or LCD mode s are i nit iated. S ettin g WAKE_ARM presets the t imer
with the value in WAKE_TMR and r eadies the t imer to start when the MPU writ es to the SLEEP (I/O RAM
0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. T he timer is nei ther reset nor di sarmed when the
MPU wakes-up. Thus, once armed and set, t he MPU continues to be awakened WAKE_TMR[7:0]
seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds
its value and does not have to be re-writt en eac h time the MPU enters SLP or LCD mode. Al so, si nc e
WAKE_TMR[7:0] is non-volatil e, it al so hol ds its value through r esets and power fail ur es).
71M6541D/F/G and 71M6542F/G Dat a S heet
3.5 Data Flow and MPU/CE Communication
The data flow between the Compute Engi ne (CE) and the MPU is sh own in Figure 30. I n a ty pic al
application, the 32-bit CE sequenti al l y pr o cesses the samples from the voltage inputs on pins IA, VA,
IB, etc., performing calculations to measure activ e power (Wh), reactive power (VARh), A2h, and V 2h
for fou r -quadrant metering. T hese measurements are then acces sed by t he M P U, proc essed further and
output usi ng the peripheral devic es availabl e to t he MPU.
Both the CE and multiplexer are cont r olled by the MP U via shared registers in the I/O RAM and in RAM.
The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts:
• CE_BUSY
• XFER_BUSY
• W PULSE, VP ULSE (pulses for active and reactive energy)
• XPULSE, YP ULS E (auxiliary pulses)
These interrupts are conn ec ted to th e M PU interrupt ser vi c e inputs as ext er nal int errupts. CE_BUSY
indicates that the CE is actively proce s s ing data. This signal occ urs on c e every m ultiplexer c ycle (typicall y
396 µs), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80).
XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This indication
occurs whenever the CE has finished generating a sum by completing an accum ulation interv al
determined by SUM_SAMPS[12:0], I/O RAM 0x 2107[4:0], 2108[7:0], (ty pic ally every 1000 m s). Interr upts to
the MP U occur on the fal ling edges of t he XFE R_B USY and CE_B US Y si gnals.
WPULSE and VPULSE are typic ally used to signal energy acc um ulation of r eal (Wh) and r eactive (VARh)
energy. Tying WPULSE and VP ULS E into the MPU interr upt system c an support pulse counting.
XPULSE and YPULS E ca n be used to s ignal e ven ts suc h as sags and zero cr os s ings of the ma ins voltage
to t he MPU. Tying these output s i nto the MPU int er r upt system r elieves the MPU from having to read the
CESTATUS register at ever y occurr enc e of the CE_BUSY i nterr upt in order to det ect sag or zer o c r ossing
events.
Figure 30: MP U/CE Data Flow
Refer to 5.3 CE Interface Description for additi onal information on setting up the device using the MPU
firmware.
MPU
CE
I/O RAM (Configuration RAM)
Pulses
Samples
WPULSE
VPULSE
XPULSE
YPULSE
Control
Processed
Metering
Data
MUX
Control
Control
Interrupts
CECONFIG
CESTATUS
XRAM
CE_BUSY
XFER_BUSY
71M6541D/F/G and 71M6542F/G Dat a S heet
4 Application Information
4.1 Connecting 5 V Devices
All digital i nput pins of the 71M654x are c om patible with exter nal 5 V devices. I/O pins configured as
inputs do not require current-limi ting resistor s when they ar e c onnec ted to exter nal 5 V devices.
4.2 Direct Connection of Sensor s
Figure 31 through Figure 34 show voltage-sensing resi stive div iders, c ur r ent-sensing curr ent transform er s
(CTs) and cur r ent-sensing resistive shunts and how they are connec ted to the voltage and curr ent input s
of t he 71M 654x . All input signals to the 71M654x sensor inputs are volt age si gnals providing a scaled
representat ion of either a sensed voltage or curr ent.
The analog input pins of the 71M654x ar e designed for sensor s with low source impedance.
RC filt er s with r esi stanc e values hi gher than those implement ed in the T eri dian Dem o B oar ds
m ust not be used. Please refer to the Demo Board schematics for complet e sensor input
ci r c uits and corresponding c omponent values.
R
IN
V
IN
R
OUT
V3P3A
VA
Figure 31: Resistive Vol t age Di vid er ( Voltage Sensing )
IIN
IAP
V3P3A
V
OUT
IOUT
R
BURDEN
CT
1:N Noise Filter
Figure 32. CT wit h Single-Ended Input Connection (Current Sensing)
I
IN
IAP
IAN
V3P3A
V
OUT
I
OUT
R
BURDEN
CT
1:N Bias Network and Noise Filter
Figure 33: CT with Differential Input Connection (Current Sensing)
I
IN
R
SHUNT
IAP
IAN
V3P3A
V
OUT
Bias Network and Noise Filter
Figure 34: Differential Resi stive S hunt Connect ions (Curren t Sen sin g)
71M6541D/F/G and 71M6542F/G Dat a S heet
4.3 71M6541D/F/G Using Local Sensors
Figure 35 shows a 71M6541D/F/G confi gur ati on using locally connected current sensor s. The IA P-IAN
current channel may be directl y connected to either a shunt r esi stor or a CT, while the IBP-I B N c hannel is
connect ed to a CT and is therefore is olated. Thi s confi guration implements a singl e-phase measurement
with t am per -detecti on usi ng one c ur r ent sensor t o m easure the neutr al curr ent. This configur ation can
also be used to create a split phase meter (e. g., ANSI Form 2S). For best perform anc e, bot h the I AP-IAN
and IBP -IBN c ur r ent sensor inputs are configur ed for diff er ential mode (i.e., DIFFA_E = 1 and DIFFB_E =
1, I/O RAM 0 x210C[4] and 0x210C[5]). The IBP-IBN input must be configured as an analog dif ferential
input disabling the remot e sensor interfac e (i.e., RMT_E = 0, I/O RAM 0x270 9[ 3]) . See Figure 2 for the AFE
configuration corr espondi ng to Figure 35.
MPU
RTC
TIMERS
IAP
VA
IBP
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
LINE
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
CT
POWER SUPPLY
TERIDIAN
71M6541D/F
TEMPERATURE
SENSOR
VREF
BATTERY
PWR MODE
CONTROL
WAKE-UP
NEUTRAL
I
2
C or µWire
EEPROM
IAN
IBN
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Divider
CT
LINE
LINE
Note:
This system is referenced to LINE
Shunt
or
11/5/2010
Figure 35. 71M6541D/F/G with Local Sensors
71M6541D/F/G and 71M6542F/G Dat a S heet
4.4 71M6541D/F/G Using 71M6x01and Current Shunts
Figure 36 shows a typical connection for one isol ated and one non-isolated shunt sensor, usi ng the
71M6x01 Isolat ed Sensor Int erface. T his conf igurati on im plem ents a single-phase measurem ent wit h
tamper-detection using t he second cur r ent sensor. Thi s conf igurati on c an also be used to create a split
phase meter (e. g., ANSI Form 2S) . F or best perf ormance, the IAP-IAN current sensor input i s confi gur ed
for differ ential mode (i.e. , DIFFA_E = 1, I/O RAM 0x210C[4]). T he outputs of the 71M6x01 Isol ated Sensor
Int erface ar e routed through a pulse transformer, wh ich is connec ted to the pins IBP-IBN. The IBP-IBN
pins must be configured f or remote sensor communi c ation (i.e., RMT_E =1, I/O RAM 0x2709[3] ). See
Figure 3 for the AFE c onfigurati on c or r espondi ng to Figure 36.
Figure 36: 71M6541D/F/G with 71M 6x01 isolated Senso r
71M6541D/F/G and 71M6542F/G Dat a S heet
4.5 71M6542F/G Using Local Sensors
Figure 38 shows a 71M6542F/G confi gur ation using locally connected c ur r ent sensors. T he IAP-IAN
current channel may be directl y connected to either a shunt r esi stor or a CT, while the IBP-I B N c hannel is
connect ed to a CT and is theref or e isol ated. Thi s confi guration implem ents a dual-phase measurement
utilizing Equation 2. For best perform anc e, bot h the IAP-IAN and IBP-IBN c ur r ent sensor input s are
configured for differential mode (i.e., DIFFA_E = 1 and DIFFB_E = 1, I/O RAM 0 x2 10C[4] and 0x210C[5]).
The I B P-IB N input must be c onfigured as an analog differential input disabling the remote sensor
interf ac e (i.e., RMT_E = 0 , I/ O RAM 0x2709[ 3]) . See Figure 4 for the AFE c onfigurati on c or r espondi ng to
Figure 38.
MPU
RTC
TIMERS
IAP
VA
IBP
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
PHASE A
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
Shunt
POWER SUPPLY
TERIDIAN
71M6542F
TEMPERATURE
SENSOR
VREF
BATTERY
PWR MODE
CONTROL
WAKE-UP
PHASE A
I
2
C or µWire
EEPROM
IAN
IBN
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Dividers
PHASE B
LOAD
VB
NEUTRAL
PHASE A
Shunt
Note:
This system is referenced to PHASE A
11/5/2010
CT or
Figure 37: 71M6542F/G with Local Sensors
71M6541D/F/G and 71M6542F/G Dat a S heet
4.6 71M6542F/G Using 71M6x01 and Current Shunts
Figure 38 shows a typical two -pha s e conn ec tion for the 71M6542F/G using one isolated and o ne no n-
isolated sensor. For best performanc e, t he IAP -IAN current s ensor input is configured for d ifferentia l mode
(i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The 71M6x01 Isolated Sensor Interface is used to isolate phase B.
The outputs of the 71M6x01 Isolated Sensor Interface are routed through a pulse transformer, which is
connected to t he pins IBP-IBN. The IBP-IB N pins must be confi gur ed for remote sensor communication
(i.e., RMT_E =1, I/O RAM 0x2709[ 3]). See Figure 5 f or the AFE confi gur ation correspondi ng to Figure 38.
MPU
RTC
TIMERS
IAP
VA
IBP
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
PHASE A
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
Shunt
POWER SUPPLY
TERIDIAN
71M6542F
TEMPERATURE
SENSOR
VREF
BATTERY
PWR MODE
CONTROL
WAKE-UP
PHASE A
I
2
C or µWire
EEPROM
IAN
IBN
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Dividers
Pulse
Trans-
former
TERIDIAN
71M6XX1
PHASE B
LOAD
VB
NEUTRAL
PHASE A
Shunt
Note:
This system is referenced to PHASE A
Figure 38: 71M6542F/G with 71M6x01 Iso la te d S e nsor
71M6541D/F/G and 71M6542F/G Dat a S heet
4.7 Metrology Temperature Compensation
4.7.1 Vol t ag e Reference Precis ion
Since the VREF band-gap a mp lifier is cho ppe r-stabi liz ed, a s s et by the CH O P_E[1:0] (I/ O RAM 0x210 6[ 3:2])
control field, t he dc offset voltage, which is the mos t significant long-term drift mechanism in the voltage
references (VREF), is autom atically rem ov ed by the chopper cir c uit. B oth the 71M654x and the 71M6x01
feature chopper ci r c uits for thei r respective V REF volt age r efer enc e.
Teridia n impl ements a trim m ing proced ure of the V REF voltage refer ence d ur ing the devi c e
m anuf act ur ing pr oc e ss.
The reference voltage (VREF) is trimmed to a target value of 1. 195V . During thi s trimming process, the
TRIMT[7:0] (I/O RAM 0x2309) value is st or ed in non-volatile fuses . TRIMT[7:0] is trimm ed to a val ue that
result s i n mi nimum VREF variat ion with tem per ature.
For th e 71M65 4x devic e ( ±0.5% ener gy ac c ur acy), th e TRIMT[7:0] value ca n be re ad by the M PU
during initi ali z ati on in or der to c alcul ate parabolic tem perature c ompen s ati on coefficients s uit abl e for
eac h indi vidual 71M65 4x devic e. The resulting temperature coefficient for V RE F i n the 71M6 54x is ±40
ppm/°C.
Considerin g the factory cali bration temperature of V REF to be +22°C and the i nd ustrial temperatu r e
ran ge (-40°C to +85 °C), the VRE F er ror at th e temperat ure extr emes f or th e 71M65 4x devic e c an be
cal c ulated a s :
%252.02520/40)2285(+=+=⋅− ppmCppmCC
ooo
and
%248.02480/40)2240(−=−=⋅−− ppmCppmCC
ooo
The ab ove calcul ati on im plies that both the voltage a nd the current mea su r ements are indivi dually
subjec t to a the oreti c al maxi mum er r or of approx imately ± 0.25%. When the volt age sample and current
sampl e are multipl ied togethe r to obtain the en ergy pe r sam ple, the voltage erro r and current error
combi ne resultin g in appr oximately ±0.5% maximum energy me asurement err or. However , this
theoretical ± 0.5 % error conside rs only the vol tage r eference (VRE F) as an e r r or source. In p r ac tice,
oth er err or sou rc e s ex ist i n the sy st em . The princip al rem ai ni ng er ror so urc e s ar e t he cur r ent se n sor s
( sh unts or CTs) an d their correspon ding si gnal c onditioni ng circuits, and the re sistor voltage divi der
use d to measure t he voltage. The 71M654x 0. 5% g r ade devices s hould be use d in Class 1% de sign s,
allowi ng s uf fi ci ent m ar gin for the ot her error source s in the sy stem.
4.7.2 Temperature Coefficients for the 71M654x
The equations provided below for calculating TC1 and TC2 apply to the 71M654x (0.5% energy accuracy). In
order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2
equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting
trac k ing of the reference voltage (VREF) is within ±40 ppm/°C, corresponding to a ±0.5% energy
meas ureme nt a ccuracy. See 4.7.1 Voltage Reference Precision.
]0:7[95.42751TRIMTTC ⋅−
=
]0:7[108.2557.02
4
TRIMTTC ⋅⋅+−=
−
14632.221
195.15
2
7
21
TCTCPPMC ⋅=⋅
⋅
=
2116.11502
195.15
2
2
8
29
TCTCPPMC ⋅=⋅
⋅
=
The coeff icients multiplying TC1 and TC2 to obt ain PPMC and PPMC2 ar e derived from the 1.195V ADC
v oltage ref er enc e and scaling performed in the CE, as sho wn above.
71M6541D/F/G and 71M6542F/G Dat a S heet
See 4.7.3 and 4.7.4 below for further temperat ur e c ompensat ion det ails.
4.7.3 Tempera ture Compensation for VREF with Local Sensors
This secti on discusses metr ology temper ature com pensation for the met er designs where l oc al sensors
are used, as shown in Figure 35 and Figure 37.
In these configurations where all sensors are di r ec tly connected to the 71M 654x , each sensor channel’s
accuracy is affected by the voltage variation in the 71M654x VREF due to temperature. The VREF in the
71M654x can be compensated digitally using a second-order polynomial functi on of t em per ature. The
71M654x features an on-chip t em per ature sensor for the purpose of temperature compensati ng its VREF.
There ar e also error sources exter nal to t he 71M 654x . The volt age sensor re si stor dividers and the shunt
current sensor an d/or CT and th eir corr espon ding sign al c onditi oning circ uits also have a temperature
dependency, whic h also may requi re compensation, depending on t he required accuracy class. The
compensation for these ext er nal error s ources may be optionally lumped with the compensation for VREF by
incorporating their compensation into the PPMC and PPMC2 coefficients for each corresponding channel.
The MPU has the responsib ility of compu ting the nec es s ary co mpe ns at ion values requ ired fo r each sens or
channel based on the sen sed temper ature. Teridian provides demonstrati on code that implement s the
GAIN_ADJn com pensation equat ion shown bel ow. The result ing GAIN_ADJn v alues are stored by the
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (CE RAM 0x40-0x42). The de monstration code
thus provides a suitable implementation of temperature compensation, but ot her methods are possi ble in
M P U fi r mware by ut il izing the o n-chip tempe r ature sensors and the CE RAM GAIN_ADJn storage locations.
The demonstr ati on c ode m aintains three separate se t s of PPMC and PPMC2 coefficient s and computes
three separat e GAIN_ADJn v alues based on the sensed t em per ature using the equation below:
23
2
14 2
2_100
2
_10
16385_ PPMCXTEMPPPMCXTEMP
ADJGAIN ⋅⋅
+
⋅⋅
+=
Where, TEMP_X i s the deviat ion from nominal or cali br ation t emperature exp r ess ed i n multiples of
0.1 °C. F or ex am ple, since the 71M654x c alibr ation (reference) tem per ature is 22 oC and the measured
temperature is 27 oC, then TEMP_X = ( 27-22) x 10 = 50 (decim al) , which r epr esents a +5 oC deviation
from 22 oC.
Table 73 shows the three GAIN_ADJn equation output values and the voltage or curr ent measurement s
for whi c h they compensate.
• GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) vo ltage measurements in the
71M654x and is used to compensate the VREF in the 71M654x. T he desi gner m ay optionally add
compensation for the resist ive voltage dividers into the PPMC and PPMC2 coefficients for this
channel.
• GAIN_ADJ1 provides compensation for the IA current channel and compe nsates for the 71M654x
VREF. The designer may optionall y add compensation for the shunt or CT and it s corr espondi ng
signal c onditi oning ci r c uit into the PPMC and PPMC2 c oeff ic ient s for this channel.
• GAIN_ADJ2 pro vides compensation for the IB current channel and compensates for the 71M654x VREF.
The designer m ay optionall y add co mpensation for the CT and its signal conditioning circuit into the
PPMC and PPMC2 c oefficients for t his channel.
Table 72: GAIN_ADJn Compensation Channels
Gain Adjustment Output
CE RAM Address
71M6541D/F/G
71M6542F/G
GAIN_ADJ0
0x40
VA
VA, VB
GAIN_ADJ1
0x41
IA
IA
GAIN_ADJ2
0x42
IB
IB
In t he dem onstr ation code, temper ature com pensation behavior is determi ned by the values stored in the
PPMC and PPMC2 coefficients for eac h of t he three c hannels, whic h ar e setup by the MPU demo code at
initi aliz ation tim e from values that ar e previously stored in EEPROM.
71M6541D/F/G and 71M6542F/G Dat a S heet
To disable temperature com pensation in the demonstration c ode, PPMC and PPMC2 ar e both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set wit h values that match the expec ted t em per ature variation of each corr espondi ng
sensor channel .
For VRE F co mpens a t ion, both the linea r coe fficient PPMC and the quadr atic coe f ficien t PPMC2, are
determined as described i n 4.7.2 Tem per ature Coefficients f or the 71M654x .
The compens ati on for the ext ernal er ror sources i s a cc ompli s hed by s umm ing the PPMC value
as s oc iated wi th V RE F with th e PPMC value as s ociated with the exter nal error source to obtain the fi nal
PPMC value for the s ensor channel. S imi larly, the PPMC2 value a s s oc iated with VREF is summed with
the PPMC2 val ue ass oc iated wi th the ext ernal e r ror source.
To deter mine th e c ont r ibutio n of t he current s hunt sen s or or CT to the PPMC and PPMC2 coefficients,
the de signer mu st either know the temperature co effi c ients of the s hunt or the CT from its data sheet or
obtai n them by la boratory measurement. The designer must consider component variation across mass
pro duction t o en s ure that the product will meet its accuracy requi rement across production.
4.7.4 Tempera ture Compensation for VREF with Remote Sensor
This secti on discusses metr ology temper ature com pensation for the met er designs where curr ent shunt
sensors are used in conjuncti on with the Teridian 71M 6x 01 isol ated sensors, as shown in Figure 36 and
Figure 38.
Any sensors that ar e direc tly connected to t he 71M 654x are affected by the voltage variation in the
71M654x VREF due to tem per ature. O n the ot her hand, sensors that ar e c onnec ted to the 71M6x01
isolated sensor, are affe cted by the VREF in the 71M6x01. The VREF in both the 71M654x and
71M6x01 can be compensated digitally using a second-order polynomi al function of t em per ature. The
71M654x and 71M6x01 feature temperature sensors for the purposes of temperature compensating their
corresponding VREF.
Referring to Figure 36 and Figure 38, t he VA volt age sensor i s avail able in both the 71M 6541D/F/G and
71M6542F/G and is directly c onnec ted to the 71M654x. The VB voltage sensor is avail able only in the
71M6542F/G and is al so di rec tly connected to it. Thus, the preci si on of these directly connected voltage
sensors is affected by VREF in the 71M654x. The 71M654x also has on e s hunt current sensor (IA) which is
connect ed direc tly to it, and theref or e is al so affected by the V REF in the 71M654x. The external current
sensor a nd i t s c or re sp on di ng si g nal c ondi t i o ni ng c ir c ui t also h as a temp erature d epe ndenc y , which
also may require com pensation, depending on the required accuracy class. Finally, the second current
sensor (IB) is isolated by the 71M6x01 and depends on the VREF of the 71M6x01, plus the variation of the
corresponding shunt resistance w ith temperature.
The MPU has the responsib ility of compu ting the nec es s ary co mpe ns at ion values requ ired fo r each sens or
channel based on the sen sed temper ature. Teridian provi des demonstrat ion code that im plem ents the
GAIN_ADJn compensation equation shown bel ow. The resulting GAIN_ADJn values are stored by t he
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (C E RAM 0x40-0x42). The de monstration code
thus provides a suitable implementation of temper ature compensation, but ot her methods are possi ble in
MPU firmware by uti lizing the on-chip temper atur e sensors an d th e CE RAM GAIN_ADJn storage locations.
The demonstr ati on c ode m aintains three separate sets of PPMC and PPMC2 c oeff icients and computes
three separat e GAIN_ADJn v alues based on the sensed t em per ature using the equation below:
23
2
14 2
2_100
2
_10
16385_ PPMCXTEMPPPMCXTEMP
ADJGAIN ⋅⋅
+
⋅⋅
+=
Where, TEMP_X i s the deviat ion from nominal or cali br ation t emperature exp r ess ed i n multiples of
0.1 °C. For example, s ince the 71M654x calibrati on ( r eference) temper ature is 22 oC and the measured
temperature is 27 oC, then TEMP_X = ( 27-22) x 10 = 50 (decim al) , which r epr esents a +5 oC dev iation
from 22 oC.
Table 73 shows the three GAIN_ADJn equation out put v alues and the voltage or curr ent measurements
for whi c h they compensate.
• GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) vo ltage measurements in the
71M654x and is used t o c ompensate the VREF in the 71M654x. T he desi gner m ay optionally add
71M6541D/F/G and 71M6542F/G Dat a S heet
compensation for the resist ive voltage dividers into the PPMC and PPMC2 coe fficients for this
channel.
• GAIN_ADJ1 provides compensation for the IA current channel and compe nsates for the 71M654x
VREF. The designer may optionall y add compensation for the shunt and its corresponding si gnal
condi tioni ng ci r c uit into the PPMC and PPMC2 coef fi ci ents for this channel.
• GAIN_ADJ2 pro vides compensation for the remotely connected IB shunt current sensor and compensates
for the 71M6x01 VREF. The designer m ay optionally add compensation f or the shunt connec ted to t he
71M6x01 into the PPMC and PPMC2 coef fici ents for this channel.
Table 73: GAIN_ADJn Compensation Channels
Gain Adjustment Output
CE RAM Address
71M6541D/F/G
71M6542F/G
GAIN_ADJ0
0x40
VA
VA, VB
GAIN_ADJ1
0x41
IA
IA
GAIN_ADJ2
0x42
IB
IB
In t he demonstration code, temperature compensation behavior is determi ned by the v alues stored in the
PPMC and PPMC2 coefficients, whic h ar e setup by the M P U demo code at initialization time from values
that ar e previously stored i n EEPROM.
To disable temperature com pensation in the demonstration c ode, PPMC and PPMC2 ar e both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set wit h values that match the expec ted temperature variation of the corresponding
channel.
For VRE F co mpens a t ion, both the linea r coe fficient PPMC and the quadratic coefficient PPMC2, are
determined for t he 71M65 4x as de scribed i n 4.7.2 Temperat ur e Coeffic ient s for the 71M 654x. For
inform ati on on d eterm ining the PPMC and PPMC2 coefficients for t he 7 1M 6x01 VREF , r efer to the
71M 6xxx Dat a S heet .
The compens ati on for the ext ernal er ror sources i s a cc ompli s hed by s umm ing the PPMC value
as s oc iated wi th V RE F with th e PPMC v al ue ass oci at e d wit h t he ex t er nal err or sou rc e to obt ai n the final
PPMC v alue for the s ensor cha nnel. S imi larly, the PPMC2 value associated with VRE F i s s ummed with
the PPMC2 value assoc iated with the ex ternal error sourc e.
To deter mine th e c ont r ibutio n of t he current s hunt sen s or to th e PPMC and PPMC2 coefficients, the
designer must eit her know the temperature coefficients of the s hunt fr om its d ata sheet or o btai n it by
laborator y mea s ur ement. The d esign er must con sider compo nent variation acro s s mas s product ion to
ens ure that the product will meet its ac c uracy requi r ement ac ross product ion.
4.8 Connecting I2C EEPROMs
I2C EEPROMs or ot her I2C c om patible devices should be connec ted to t he DIO pi ns SEGDIO2 and
SEGDIO3, as shown in Figure 39.
Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation i n BRN mode) should be used f or both
SDCK and SDATA signals. The DIO_EEX[1:0] (I/O RAM 0x 2456[7:6]) field in I/O RAM must be set to 01
in or der to conv er t t he DIO pi ns SEGDI O2 and SEG DIO 3 to I2C pi ns SDCK and SDATA.
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 39: I2C EEPROM Connection
4.9 Connecting Three-Wire EEPROMs
µWir e E E P ROMs and other c om patible devices should be connec ted to t he DIO pi ns SEGDIO2/SDCK
and SEGDIO3/SDATA, a s described i n 2.5.9 EEPROM Interfac e.
4.10 UART 0 (TX/RX)
The UART0 RX pi n sh ould b e pul led do wn by a 10 kΩ resistor an d addi ti on ally protec ted by a 100 pF
ceram ic capacit or , as shown in Figure 40.
Figure 40: C onnec t i ons f or UART0
4.11 Optical Interface (UART1)
The O P T_TX and OP T_RX pins ca n be u sed for a re g ul ar serial int er face (by c onne ct ing a RS _2 32
transceiver for example), or they can be used to directly operate optical components (for example, an infrared
diode and phototr ansi stor implem enting a F LA G int erface). Figure 41 shows the basi c c onnec ti ons for
UART1. The OPT_TX pin becomes active when the I/O RAM control field OPT_TXE (I /O R AM 0x24 56[3:2])
is set to 00.
The polarit y of the OPT _TX and OPT_RX pins can be inverted wit h the configur ation bits, OPT_TXINV
(I/O RAM 0x2456[0]) and OPT_RXINV (I/O RAM 0x2457[1] ), respectively.
The O PT_TX output may be modul ated at 38 k Hz when system power i s present. Modulation i s not
ava ila ble in BRN mode. The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The dut y cycl e is
contr olled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4 ]), whic h c an sel ec t 50%, 25%, 12. 5%, and 6. 25% duty
cycle. A 6.25% duty c y cl e means OPT _TX is l ow for 6.25% of the peri od. The OPT_RX pin uses digital
signal thresholds. It may need an anal og filter when receiving modulated optic al si gnals.
With modulati on, an optical emitter can be operated at higher curr ent than nominal, enabling it to
inc r ease the distance along the optic al path.
TX
RX
71M654x
10 k
Ω
100 pF
RX
TX
SEGDIO2/SDCK
EEPROM
SDCK
SDATA
V3P3D
10 k
Ω
10 k
Ω
71M654x
SEGDIO3/SDATA
71M6541D/F/G and 71M6542F/G Dat a S heet
If operation in BRN mode is desired, the external components shoul d be c onnec ted to V3P3D. However,
it is recommended to limit the current t o a few mA.
Figure 41: Connection for Optical Components
4.12 Connecting the Reset Pin
Even though a functional meter does not nec es saril y need a reset swit c h, it is usef ul to have a r eset
pushbutton for pro to typing as shown in Figure 42, left side. The RE S E T signa l may be sour ced fro m
V3P3SYS (funct ional in MSN m ode only ) , V3P 3D (MSN and BRN modes), or V BAT (all modes, if a
batt er y is present), or f r om a combination of these sources, depending on the application.
For a pr oduc tion meter, the RES ET pin should be pr otected by the ext er nal c om ponents sho wn in
Figure 42, right side. R1 should be in the range of 100Ω and mounted as closely as possible to the IC.
Since the 71M6541D/F/G and 71M6542F/G generate their own power-on reset, a reset button or circuitry, as
s hown in Figure 42, is onl y required for test uni ts and prot otypes.
Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)
4.13 Connecting t he Emulator Port Pi ns
Even when t he emulat or i s not used, small shunt capacit ors to ground (22 pF ) shoul d be used f or
protection from EMI as illustr ated in Figure 43. Production boar ds should have t he ICE_E pi n connect ed
to ground.
R
1
RESET
71M654x
GNDD
V3P3D
R
2
VBAT/
V3P3D
Reset
Switch
1k
Ω
0.1µF
10kΩ
OPT_TX
R
2
R
1
OPT_RX
71M654x
V3P3SYS
Phototransistor
LED
10 kΩ
100 pF
V3P3SYS
71M654x
GNDD
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 43: Ext ernal Components for the Emulator Interface
E_RST
71M654x
E_TCLK
62
Ω
62 Ω
62 Ω
22 pF
22 pF
22 pF
LCD Segments
ICE_E
V3P3D
E_RXT
(optional)
71M6541D/F/G and 71M6542F/G Dat a S heet
4.14 Flash Programming
4.14.1 Flash Programming via the ICE Port
Operati onal or test code c an be pr ogr ammed into the flash mem or y usi ng either an in-circuit emulator or
the Fl ash Progr am mer Module (TF P -2) available fro m Teridian. The flash programming procedur e uses
the E_RS T, E _RXTX, and E _TCLK pins.
4.14.2 Flash Programming via the SPI Port
It is possible to erase, read and pr ogr am the flash memory of the via the SPI por t. See 2.5.10 SPI Slav e
Port for a detailed descr iption.
4.15 MPU Firmware Library
All application-specif ic MPU functi ons mentioned in 4 Applica tion Information are featured in the
dem onstr ati on C source code supplied by T eri dian. The code is availabl e as part of the Demonstration Kit
for the 71M6541D/F/G and 71M6542F/G. The Demon s tration Kits come with the prep rogramme d with
demo firmware and mounted on a functional sample meter Demo Board. The D emo Boar ds all ow for quick
and eff ic ient evaluation of t he IC wit hout having to write firm ware or having to supply an in-circuit
em ulator (ICE).
4.16 Crysta l Os c illa tor
The oscillator of the 71M6541D/F/G and 71M6542F/G drives a standard 32.768 kHz watch crystal. The
oscillator has been desi gned sp ec ifi c ally to handl e these crystals and is compatibl e with t heir high
im pedanc e and lim it ed power handling capabi lity. The oscill ator power di ssipat ion is very low to
m aximize the lifetime of any batter y bac k up devi c e att ached to the VBAT_RTC pin.
Board layout s with mi nim um capacitanc e from XIN to XOUT requir e less batter y c ur r ent. G ood lay outs
hav e XIN and XOUT shielded f r om each other and fr om LCD and di gital signal s.
Since the oscillator is self-bias ing, an externa l resistor must not be connected across the crystal.
4.17 Meter Calibration
Once the Teridian 71M654x energy m eter dev ic e has been i nstalled in a met er system , it must be
calibrated. A c om plete calibration includes the f ollowing:
• Establis hment of the reference temperature (e.g., typically 22 ⁰C)
• Calibratio n of the metrolo gy secti on, i.e., cali brat ion for t olera nc es of the c urr ent sensors, volt age
div iders and signal conditioning com ponents as well as of the internal re ference voltage (VRE F) at
the reference temperature ( e.g., typically 22 ⁰C).
• Calibrati on of t he oscillator fr equenc y usi ng the RTCA_ADJ[7:0] I/O RAM register (I/ O RAM 0x2504).
The metrology section can be calibrated using the gai n and phase adjustment factors accessibl e to t he
CE. The gain adjustmen t is us ed to comp ens at e for to leran ces of components used fo r s ignal co nd it ioning ,
especi ally the resistiv e component s. Phase adjustment i s provided to compensat e for phase shif ts
introduced by the current sensors or by t he eff ec ts of react ive power suppli es.
Due to t he flexibilit y of t he MPU firmware, any c alibration met hod, such as calibrati on based on energy, or
current and volt age can be impl emented. It is also possible to i mplement segment-wise cali b rati o n
(depending on c ur r ent range).
The 71M6541D/F/G and 71M6542F/G support common industry standard calibration t echni ques, such
as si n gle-poi nt (ener gy -only), multi-poi nt (ener gy , Vrms, I rms), and auto-calibration.
Teridian prov ides a calibrati on spreadsheet file to facilitat e the calibration process. Contact your Teridian
representative to obtain a copy o f the latest calibration spreadsheet file for the 71M654x.
71M6541D/F/G and 71M6542F/G Dat a S heet
5 Firmware Interface
5.1 I/O RAM Map –Func tional O r der
In Table 74 and Table 75, unimplemented (U) and reserved (R) bits ar e shaded i n light gray. Unimplem ented bits are ident ified with a ‘U’.
Unim plemented bit s have no memory storage, writi ng them has no ef fect, and reading t hem always returns zero. Reserved bits are i dentif ied wit h
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may hav e undesirable side effects and must be
avoided. Non-volatil e bits are shaded in dark gr ay. Non-volatil e bits are backed-up during pow er failures if the syst em includes a batt er y connect ed
to t he VBAT pin.
The I /O RAM loc ations listed in Table 74 have sequential addr esses to facilitate readi ng by the MP U (e.g., in order t o v erify their c ontent s). These
I/ O RAM l oc ations are usually m odifi ed only at boot -up. The addresses shown in Table 74 are an alter native sequential addr ess to the addr esses
from Table 75 whic h ar e used throughout document. For instance, EQU[2:0] can be acc essed at I/O RAM 0x2000[7:5] or at I/O RAM 0x2106[7:5].
Table 74: I/O RAM Map – F unc tiona l Or de r , Basic Co nfiguration
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CE6
2000
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE5
2001
U
SUM_SAMPS[12:8]
CE4
2002
SUM_SAMPS[7:0]
CE3
2003
U
U
CE_LCTN[5:0]
CE2
2004
PLS_MAXWIDTH[7:0]
CE1
2005
PLS_INTERVAL[7:0]
CE0
2006
R
R
DIFFB_E
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
RCE0
2007
CHOPR[1:0]
R
R
RMT_E
R
R
R
RTMUX
2008
U
TMUXRB[2:0]
U
TMUXRA[2:0]
Reserved
2009
U
U
R
U
U
U
U
U
MUX5
200A
MUX_DIV[3:0]
MUX10_SEL
MUX4
200B
MUX9_SEL
MUX8_SEL
MUX3
200C
MUX7_SEL
MUX6_SEL
MUX2
200D
MUX5_SEL
MUX4_SEL
MUX1
200E
MUX3_SEL
MUX2_SEL
MUX0
200F
MUX1_SEL
MUX0_SEL
TEMP
2010
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT
TBYTE_BUSY
TEMP_PER[2:0]
LCD0
2011
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD1
2012
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD2
2013
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD_MAP6
2014
LCD_MAP[55:48]
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LCD_MAP5
2015
LCD_MAP[47:40]
LCD_MAP4
2016
LCD_MAP[39:32]
LCD_MAP3
2017
LCD_MAP[31:24]
LCD_MAP2
2018
LCD_MAP[23:16]
LCD_MAP1
2019
LCD_MAP[15:8]
LCD_MAP0
201A
LCD_MAP[7:0]
DIO_R5
201B
U
U
U
U
U
DIO_RPB[2:0]
DIO_R4
201C
U
DIO_R11[2:0]
U
DIO_R10[2:0]
DIO_R3
201D
U
DIO_R9[2:0]
U
DIO_R8[2:0]
DIO_R2
201E
U
DIO_R7[2:0]
U
DIO_R6[2:0]
DIO_R1
201F
U
DIO_R5[2:0]
U
DIO_R4[2:0]
DIO_R0
2020
U
DIO_R3[2:0]
U
DIO_R2[2:0]
DIO0
2021
DIO_EEX[1:0]
U
U
OPT_TXE[1:0]
OPT_TXMOD
OPT_TXINV
DIO1
2022
DIO_PW
DIO_PV
OPT_FDC[1:0]
U
OPT_RXDIS
OPT_RXINV
OPT_BB
DIO2
2023
DIO_PX
DIO_PY
U
U
U
U
U
U
INT1_E
2024
EX_EEX
EX_XPULSE
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_RTC1S
EX_XFER
INT2_E
2025
EX_SPI
EX_WPULSE
EX_VPULSE
WAKE_E
2026
EW_RX
EW_PB
EW_DIO4
EW_DIO52†
EW_DIO55
SFMM
2080
SFMM[7:0]*
SFMS
2081
SFMS[7:0]*
Notes:
*
SFMM and SFMS are ac c essible only through t he S PI slave port. See Invoking SFM (page 77) for details.
†
71M6542F/G only.
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have light er gr ay backgr ound, and non-volatile bits
hav e a dar k er gray bac k gr ound.
Table 75: I/O RAM Map – F unc tiona l Or de r
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CE and ADC
MUX5
2100
MUX_DIV[3:0]
MUX10_SEL[3:0]
MUX4
2101
MUX9_SEL[3:0]
MUX8_SEL[3:0]
MUX3
2102
MUX7_SEL[3:0]
MUX6_SEL[3:0]
MUX2
2103
MUX5_SEL[3:0]
MUX4_SEL[3:0]
MUX1
2104
MUX3_SEL[3:0]
MUX2_SEL[3:0]
MUX0
2105
MUX1_SEL[3:0]
MUX0_SEL[3:0]
CE6
2106
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE5
2107
U
U
U
SUM_SAMPS[12:8]
CE4
2108
SUM_SAMPS[7:0]
CE3
2109
U
U
CE_LCTN[5:0]
CE2
210A
PLS_MAXWIDTH[7:0]
CE1
210B
PLS_INTERVAL[7:0]
CE0
210C
R
R
DIFFB_E
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
RTM0
210D
U
U
U
U
U
U
RTM0[9:8]
RTM0
210E
RTM0[7:0]
RTM1
210F
RTM1[7:0]
RTM2
2110
RTM2[7:0]
RTM3
2111
RTM3[7:0]
CLO CK GENERATIO N
CKGN
2200
U
U
ADC_DIV
PLL_FAST
RESET
MPU_DIV[2:0]
LCD/DIO
VREF TRIM FUSES
TRIMT
2309
TRIMT[7:0]
LCD/DIO
LCD0
2400
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD1
2401
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD2
2402
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD_MAP6
2405
LCD_MAP[55:48]
LCD_MAP5
2406
LCD_MAP[47:40]
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LCD_MAP4
2407
LCD_MAP[39:32]
LCD_MAP3
2408
LCD_MAP[31:24]
LCD_MAP2
2409
LCD_MAP[23:16]
LCD_MAP1
240A
LCD_MAP[15:8]
LCD_MAP0
240B
LCD_MAP[7:0]
LCD4
240C
U
U
U
U
U
LCD_RST
LCD_BLANK
LCD_ON
LCD_DAC
240D
U
U
U
LCD_DAC[4:0]
SEGDIO0
2410
U
U
LCD_SEG0[5:0]
…
…
U
U
…
SEGDIO15
241F
U
U
LCD_SEG15[5:0]
SEGDIO16
2420
U
U
LCD_SEGDIO 16[5:0]
…
…
U
U
…
SEGDIO45
243D
U
U
LCD_SEGDIO45[5:0]
SEGDIO46
243E
U
U
LCD_SEG46[5:0]
…
…
U
U
…
SEGDIO50
2442
U
U
LCD_SEG50[5:0]
SEGDIO51
2443
U
U
LCD_SEGDIO51[5:0]
…
…
U
U
…
SEGDIO55
2447
U
U
LCD_SEGDIO55[5:0]
DIO_R5
2450
U
U
U
U
U
DIO_RPB[2:0]
DIO_R4
2451
U
DIO_R11[2:0]
U
DIO_R10[2:0]
DIO_R3
2452
U
DIO_R9[2:0]
U
DIO_R8[2:0]
DIO_R2
2453
U
DIO_R7[2:0]
U
DIO_R6[2:0]
DIO_R1
2454
U
DIO_R5[2:0]
U
DIO_R4[2:0]
DIO_R0
2455
U
DIO_R3[2:0]
U
DIO_R2[2:0]
DIO0
2456
DIO_EEX[1:0]
U
U
OPT_TXE[1:0]
OPT_TXMOD
OPT_TXINV
DIO1
2457
DIO_PW
DIO_PV
OPT_FDC[1:0]
U
OPT_RXDIS
OPT_RXINV
OPT_BB
DIO2
2458
DIO_PX
DIO_PY
U
U
U
U
U
U
NV BITS
RESERVED
2500
U
U
U
U
R
R
R
R
RESERVED
2501
U
U
R
U
U
U
U
U
TMUX
2502
U
U
TMUX[5:0]
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TMUX2
2503
U
U
U
TMUX2[4:0]
RTC1
2504
U
RTCA_ADJ[6:0]
71M6x01 Interface
REMOTE2
2602
RMT_RD[15:8]
REMOTE1
2603
RMT_RD[7:0]
RBITS
INT1_E
2700
EX_EEX
EX_XPULSE
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_RTC1S
EX_XFER
INT2_E
2701
EX_SPI
EX_WPULSE
EX_VPULSE
U
U
U
U
U
SECURE
2702
FLSH_UNLOCK[3:0]
R
FLSH_RDE
FLSH_WRE
R
Analog0
2704
VREF_CAL
VREF_DIS
PRE_E
ADC_E
BCURR
SPARE[2:0]
VERSION
2706
VERSION[7:0]
INTBITS
2707
U
INT6
INT5
INT4
INT3
INT2
INT1
INT0
FLAG0
SFR E8
IE_EEX
IE_XPULSE
IE_YPULSE
IE_RTCT
U
IE_RTC1M
IE_RTC1S
IE_XFER
FLAG1
SFR F8
IE_SPI
IE_WPULSE
IE_VPULSE
U
U
U
U
PB_STATE
STAT
SFR F9
U
U
U
PLL_OK
U
VSTAT[2:0]
REMOTE0
SFR FC
PERR_RD
PERR_WR
RCMD[4:0]
SPI1
SFR FD
SPI_CMD[7:0]
SPI0
2708
SPI_STAT[7:0]
RCE0
2709
CHOPR[1:0]
R
R
RMT_E
R
R
R
RTMUX
270A
U
R
R
R
U
TMUXRA[2:0]
INFO_PG
270B
U
U
U
U
U
U
U
INFO_PG
DIO3
270C
U
U
PORT_E
SPI_E
SPI_SAFE
U
U
U
NV RAM and RTC
NVRAMxx
2800-
287F
NVRAM[0] – NVRAM[7F] – Dire ct Access
WAKE
2880
WAKE_TMR[7:0]
STEMP1
2881
STEMP[10:3]
STEMP0
2882
STEMP[2:0]
U
U
U
U
U
BSENSE
2885
BSENSE[7:0]
LKPADDR
2887
LKPAUTOI
LKPADDR[6:0]
LKPDATA
2888
LKPDAT[7:0]
LKPCTRL
2889
U
U
U
U
U
U
LKP_RD
LKP_WR
RTC0
2890
RTC_WR
RTC_RD
U
RTC_FAIL
U
U
U
U
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RTC2
2892
RTC_SBSC[7:0]
RTC3
2893
U
U
RTC_SEC[5:0]
RTC4
2894
U
U
RTC_MIN[5:0]
RTC5
2895
U
U
U
RTC_HR[4:0]
RTC6
2896
U
U
U
U
U
RTC_DAY[2:0]
RTC7
2897
U
U
U
RTC_DATE[4:0]
RTC8
2898
U
U
U
U
RTC_MO[3:0]
RTC9
2899
RTC_YR[7:0]
RTC10
289B
U
U
U
U
U
RTC_P[16:14]
RTC11
289C
RTC_P[13:6]
RTC12
289D
RTC_P[5:0]
RTC_Q[1:0]
RTC13
289E
U
U
RTC_TMIN[5:0]
RTC14
289F
U
U
U
RTC_THR[4:0]
TEMP
28A0
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT
TBYTE_BUSY
TEMP_PER[2:0]
WF1
28B0
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
WF2
28B1
U
U
WF_TMR
WF_RX
WF_PB
WF_DIO4
WF_DIO52
WF_DIO55
MISC
28B2
SLEEP
LCD_ONLY
WAKE_ARM
WAKE_E
28B3
U
U
U
EW_RX
EW_PB
EW_DIO4
EW_DIO52 †
EW_DIO55
WDRST
28B4
WD_RST
TEMP_START
U
U
U
U
U
U
MPU PORTS
P3
SFR B0
DIO_DIR[15:12]
DIO[15:12]
P2
SFR A0
DIO_DIR[11:8]
DIO[11:8]
P1
SFR 90
DIO_DIR[7:4]
DIO[7:4]
P0
SFR 80
DIO_DIR[3:0]
DIO[3:0]
FLASH
ERASE
SFR 94
FLSH_ERASE[7:0]
FLSHCTL
SFR B2
PREBOOT
SECURE
U
U
FLSH_PEND
FLSH_PSTWR
FLSH_MEEN
FLSH_PWE
PGADR
SFR B7
FLSH_PGADR[5:0]
U
U
I2C
EEDATA
SFR 9E
EEDATA[7:0]
EECTRL
SFR 9F
EECTRL[7:0]
† 71M6542F/G only
71M6541D/F/G and 71M6542F/G Dat a S heet
5.2 I/O RAM Map – Alphabetical Order
Table 76 lists I/O RAM bits and registers i n alphabeti c al order.
B its wit h a write direction (W i n column Dir ) ar e wri tt en by the M P U into configurati on RA M. Typic ally , they are initially stored i n flash memory and
copi ed to the configur ation RAM by the MPU. Some of the more frequently programmed bits are mapped to the MP U SFR m em ory space. The
remai ning bits are m apped to the a ddress space 0x2XXX. Bits with R (read) dir ection can be read by the MPU. C olumn s l abeled Rst and Wk
describe the bit v alues upon reset and wake, respectiv ely. No ent ry in one of these columns means the bi t is ei ther read-only or is powered by the
NV supply and is not initi alized. Write-only bits return zero when they ar e r ead.
Locations that ar e shaded i n gr ey ar e non-volatile (i.e., battery-backed).
Table 76: I/O RAM Map – F unc tiona l Or de r
Name Location
Rst
Wk
Dir Description
ADC_E
2704[4]
0
0
R/W
Enabl es ADC and VRE F. When disabled, reduces bias curr ent.
ADC_DIV 2200[5] 0 0 R/W
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting det ermines whether M CK is divi ded by 4 or 8:
0 = MCK/4
1 = MCK/8
The resul ting ADC and FIR cl oc k is as shown below.
PLL_FAST = 0
PLL_FAST = 1
MCK
6.291456 MHz
19.660800 MHz
ADC_DIV = 0
1.572864 MHz
4.9152 MHz
ADC_DIV = 1
0.786432 MHz
2.4576 MHz
BCURR
2704[3]
0
0
R/W
Connects a 100 µA load to the battery sel ec ted by TEMP_BSEL.
BSENSE[7:0]
2885[7:0]
–
–
R
The resul t of the batter y measurem ent. See 2.5.6 71M654x B att er y Monit or .
CE_E
2106[0]
0
0
R/W
CE enabl e.
CE_LCTN[5:0] 2109[5:0] 31
31
R/W
CE program loc ation. The starting address for the CE program is
1024*CE_LCTN.
CHIP_ID[15:8]
CHIP_ID[7:0]
2300[7:0]
2301[7:0]
0
0
0
0
R
R
These bytes cont ain t he ch ip identification.
CHOP_E[1:0] 2106[3:2] 0 0 R/W
Chop enable for t he refer enc e bandgap c ircuit. The value of CHO P changes
on the rising edge of MUXSYNC ac c or ding to the value i n CHOP_E:
00 = toggle1 01 = positive 10 = rev er sed 11 = toggle
1
except at the mux sync edge at the end of an accum ulation interval.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
CHOPR[1:0] 2709[7:6] 00
00
R/W
The CHO P settings for the rem ote sensor.
00 = Aut o c hop. Change every MUX fram e.
01 = Positive
10 = Negative
11 = Aut o c hop. Same as 00.
DIFFA_E
210C[4]
0
0
R/W
Enabl es differential configurati on for the IA current input (IAP-IAN).
DIFFB_E
210C[5]
0
0
R/W
Enables differentia l configuration for the IB current input (IBP-IBN).
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
0
0
0
0
0
0
0
0
0
0
0
– R/W
Connec ts PB and dedicated I/O pins D IO2 through DI O11 to intern al resources
.
If m or e than one input is connec ted t o th e same resour c e, the MULTIPLE
col umn below specifi es how they are com bined.
DIO_Rx
Resource
MULTIPLE
0
NONE
–
1
Reserved
OR
2
T0 ( Timer0 clock or gate)
OR
3
T1 (Timer1 clock or gate)
OR
4
IO interrupt (int0)
OR
5
IO interrupt (int1)
OR
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
SFR B 0[7: 4]
SFR A 0[7: 4]
SFR 90[7:4]
SFR 80[7:4]
F F R/W
Programs the dir ec tion of the first 16 DIO pins. 1 indic ates output . Ignored if
the pin is not confi gur ed as I/O . See DIO_PV and DIO_PW f or special option
for the SEGDIO0 and SEGDIO1 outputs. S ee DIO_EEX for special opti on for
SEGDIO2 and SEGDIO3. Note that the direction of DIO pins above 15 is set by
SEGDIOx[1]. See PORT_E to avoid p owe r-up spi k es.
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
SFR B 0[3: 0]
SFR A 0[3: 0] SFR 90[3:0]
SFR 80[3:0] F F R/W
The value on the fir st 16 DIO pi ns. Pins configured as LCD reads zer o.
When wr it ten, changes data on pi ns conf igured as output s. Pi ns conf igured
as LCD or input ignor e wri tes. Note that the dat a for DIO pins above 15 is
set by SEGDIOx[0].
DIO_EEX[1:0] 2456[7:6] 0 – R/W
When set, conver ts pins SEGDIO3/SEGDIO2 to interface with external
EEPROM. SEG DIO 2 bec om es SDCK and S EGDIO 3 becomes bi-directional
SDAT A, but only if LCD_MAP[2] and LCD_MAP[3] are cleared.
DIO_EEX[1:0]
Function
00
Disable EEPROM interface
01
2-Wire EEPRO M interf ace
10
3-Wire EEPRO M interface
11
3-Wire E E P ROM interface wit h separate DO ( DIO 3)
and DI (DIO 8) pins.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
DIO_PV
2457[6]
0
–
R/W
Causes VARPULSE to be output on p in S E GDIO1, if LCD_MAP[1] = 0.
DIO_PW
2457[7]
0
–
R/W
Causes WPULSE to be output on pin SEGDIO0, if LCD_MAP[0] = 0.
DIO_PX
2458[7]
0
–
R/W
Causes XPULSE to be output on pin SEGDIO6 , if LCD_MAP[6] = 0.
DIO_PY
2458[6]
0
–
R/W
Causes YPULSE to be output on pin SEGDIO7 , if LCD_MAP[7] = 0.
EEDATA[7:0]
SFR 9E
0
0
R/W
Serial EEPROM interface data.
EECTRL[7:0] SF R 9F 0 0 R/W
Serial EEPROM interface control.
Status
Bit
Name
Read/
Write
Reset
State
Polarity Description
7 ERROR R 0 Positive
1 when an illegal command
is received.
6
BUSY
R
0
Positive
1 when serial data bus i s
busy.
5 RX_ACK R 1 Positive
1 indic ates that the
EEPROM sent an A CK bit.
EQU[2:0] 2106[7:5] 0 0 R/W
Specif ies the power equation.
EQU Watt & V AR Fo rmul a
(WSUM/VARSUM)
Inputs Used for Energy/Current
Calculation
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQ
SUM
I1SQ
SUM
0
VA*IA
1 elem ent, 2W 1
φ
VA*IA VA*IB1 IA IB1
1
VA*(IA-IB)/2
1 elem ent, 3W 1
φ
VA*(IA-IB)/2 – IA-IB IB
2†
VA*IA + VB*IB
2 element, 3W 3φ Delta
VA*IA VB*IB IA IB
Note:
1. O ptionall y , I B may be used to m easure neut r al c ur r ent.
†
71M6542F/G only
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0 0 R/W
Int er r upt enabl e bits. These bit s enabl e the XFER_BUSY, the RT C_1S E C,
etc. The bits are set by har dware and cannot be set by wri ting a 1. The bits
are reset by wri ti ng 0. Note that if one of these interrupts is to enabl ed, it s
corresponding 8 051 EX e nabl e bi t must also be set. S ee 2.4.8 Interrupts for
details.
EW_DIO4 28B3[2] 0 – R/W
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake
the part. T his bit has no ef fect unless DIO4 is configur ed as a di gital input.
EW_DIO52 28B3[1] 0 – R/W
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 ri si ng to
wake the part. This bit has no effect unless SEGDIO52 is conf igured as a
digital i nput.
The S EGDIO52 pi n is on ly av a ilable in the 71M6542F/G.
EW_DIO55 28B3[0] 0 – R/W
Connects SEGDIO55 to the WAKE logic and permits SEGDIO55 ri si ng to
wake the part. This bit has no effect unless SEGDIO55 is conf igured as a
digital i nput.
EW_PB 28B3[3] 0 – R/W
Connects PB to the WAKE logic and permits PB risi ng to wake t he par t. PB
is al ways confi gur ed as an input.
EW_RX 28B3[4] 0 – R/W Connects RX to the WA K E logi c and permits RX rising to wake the part . See
the W AKE descripti on on page 87 for de-bounce i ssues.
FIR_LEN[1:0] 210C[2:1] 0 0 R/W
Determ ines the num ber of ADC cycles i n the ADC decima tion FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0]
ADC Cycles
00
141
01
288
10
384
PLL_FAST = 0:
FIR_LEN[1:0]
ADC Cycles
00
135
01
276
10
Not Allowed
The ADC LS B size and full-scale v alues depend on the FIR_LEN[1:0] setting.
Refer to 6.4.15 ADC Conv er ter on page 149.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
FLSH_ERASE[7:0] SFR 94[7:0] 0 0 W
Flash Erase Initiate
FLSH_ERASE is used to i nitiate either the Flash Mass Erase cycl e or the Fl ash
Pag e E rase cyc le. Specific pat terns are expe c te d for FLSH_ERASE in or de r
to ini ti ate t he appr opr iate Erase cycl e.
(default = 0x00).
0x55 = I nitiate Flash Page Erase cyc le. Must be proceeded by a writ e to
FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
0xAA = Initiat e Flash Mass Erase cycle. Must be proc eeded by a writ e to
FLSH_MEEN and the ICE port must be enabled.
Any ot her patt er n wri tten to FLSH_ERASE has no effect.
FLSH_MEEN SFR B 2[1] 0 0 W
Mass Erase Enabl e
0 = Mass Erase di sabl ed ( default).
1 = Mass Erase enabl ed.
Must be re-writt en for each new Mass Erase cycl e.
FLSH_PEND S FR B2[3] 0 0 R
Indicates that a timed flash write is pending. If another flash write is attempted,
it is ignored.
FLSH_PGADR[5:0] SFR B7[7:2] 0 0 W
Flash Page Erase Address
FLSH_PGADR[5:0] – Flash Page Address (page 0 thru 63) that is erased during
the Page E r ase cyc le. (default = 0x 00) .
Must be re-writt en for each new Page E rase cycle.
FLSH_PSTWR SF R B 2[2] 0 0 R/W
Enabl es timed flash wri tes. When 1, and if CE_E = 1, flash wri te requests are
stored in a one-element deep FIFO and ar e ex ec uted when CE _B US Y falls.
FLSH_PEND can be read to determine the stat us of the FIFO. If
FLSH_PSTWR
= 0 or if
CE_E
= 0, fl ash writ es are immediat e.
FLSH_PWE SFR B2[0] 0 0 R/W
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal oper ation (default).
1 = MOVX @DPTR,A moves A to External Program Space (Fl ash) @ DPTR.
This bit is automati c ally reset after each byte writt en to fl ash. Wri tes to this bit
are i nhibit ed when interrupts are enabled.
FLSH_RDE 2702[2] – – R
Indicat es that t he flash may be read by ICE or SPI slave. FLSH_RDE =
(!SECURE)
FLSH_UNLOCK[3:0] 2702[7:4] 0 0 R/W
Must be a ‘2’ to enable any flash modification. See the description of Flash
securit y for mo re details .
FLSH_WRE
2702[1]
–
–
R
Indicat es that t he flash may be written through ICE or SPI slave por ts.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E 8[0]
SFR E 8[1]
SFR E 8[2]
SFR E 8[4]
SFR F8[7]
SFR E 8[7]
SFR E 8[6]
SFR E 8[5]
SFR F8[4]
SFR F8[3]
0 0 R/W
Interrupt flags for exter nal interrupts 2 and 6. These flags monitor the source
of the int6 and int2 interrupts (ex ternal interrupts to the MPU core) . These
flags are set by hardware and m ust be cl ear ed by the software int er r upt
handler. The IEX2 (SFR 0xC 0[1]) and IEX6 (SFR 0xC0[5]) interrupt f lags are
automati c ally cl ear ed by the MPU cor e when it vec tors t o the inter r upt
handler. IEX2 and IEX6 must be cleared by wri ting zero to thei r correspondi ng
bit positi ons i n SFR 0xC0, while writing ones to t he other bit positi ons that are
not being cleared.
INTBITS 2707[6:0] – – R
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, I NT1, up to I NT6. These bits do not have any memory and
are primarily intended for debug use.
LCD_ALLCOM 2400[3] 0 – R/W
Configures SEG /COM bits as COM . Has no eff ec t on pins whose LCD_MAP
bit is zero.
LCD_BAT
2402[7]
0
–
R/W
Connects the LCD power suppl y to VBAT in all m odes.
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
2401[5:0]
2402[5:0] 0 – R/W Identifies which segments connected to SEG23 and SEG22 should blink. 1
m eans ‘blink.’ T he most significant bit c orresponds to CO M5, the least
significant, to COM0.
LCD_CLK[1:0] 2400[1:0] 0 – R/W
Sets the LCD cl oc k frequenc y . Note: f
w
= 32768 Hz
LCD_CLK
LCD C lock Fre que ncy
LCD_CLK
LCD Clock Frequency
00
9
2W
f
= 64 Hz 10
7
2W
f
= 256 Hz
01
8
2W
f
= 128 Hz
11
6
2W
f
= 512 Hz
LCD_DAC[4:0] 240D[4:0] 0 – R/W
The LCD contrast DAC. Thi s DAC controls the VLCD voltage and has an
output r ange of 2.5 V to 5 V. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is
limited by V 3P 3SYS, VB AT, and whether LCD_BSTE = 1.
LCD_E 2400[7] 0 – R/W
Enabl es the LCD display . When disabled, VLC2, V LC1, and VLC0 ar e
ground as are the CO M and S EG output s if their LCD_MAP bit is 1.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enabl es LCD segment driver mode of combined SEGDIO pins. Pins that
cannot be c onfi gur ed as outputs (SEG48 thr ough S EG50) become inputs with
internal pull ups when their LCD_MAP bit is zero. Also, note that SEG 48
through SEG50 are multiplexed with the in-circuit e mulator signals. When the
ICE_E pin i s hi gh, the ICE interface is enabled, and SEG 48 through SEG50
become E_RXTX, E_TCLK and E _RST, respectiv ely .
LCD_MODE[2:0] 2400[6:4] 0 – R/W
Sel ec ts the LCD bias and multiplex mode.
LCD_MODE
Output
LCD_MODE
Output
000
4 states, 1/ 3 bias
100
Static display
001
3 states, 1/ 3 bias
101
5 states, 1/ 3 bias
010
2 states, ½ bias
110
6 states, 1/ 3 bias
011
3 states, ½ bias
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
R/W
R/W
Turns on or off all LCD segm ents without changi ng LCD data. If both bits are
set, t he LCD display is tur ned on.
LCD_ONLY 28B2[6] 0 0 W
Puts the IC to sleep, but wit h LCD displ ay still active. Ignored if system power
is present. It awakens when Wake Timer times out, when certain DIO pi ns
are raised, or when system power returns. S ee 3.2 Batt er y M odes.
LCD_RST 240C[2] 0 – R/W Cl ear all bits of LCD data. These bits affect SEGDIO pins that are c onfigured
as LCD drivers. This bit does not aut o cl ear .
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
2410[5: 0] to
241F[5:0] 0 – R/W SEG Data f or SEG0 t hr ough SEG 15. DIO data for t hese pi ns i s i n SFR
space.
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
2420[5:0] to
243D[5:0] 0 – R/W
SEG and DIO data for SEGDIO16 thr ough S EGDIO 45. If configur ed as DIO,
bit 1 is di r ec tion (1 is output , 0 is input), bit 0 is data, and t he other bits are
ignor ed.
LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
243E[5:0] to 2442[ 5:0] 0 – R/W SEG data for SEG46 thr ough S EG50. These pins cannot be configured as
DIO.
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0] 2443[5:0] to 2447[5:0] 0 – R/W
SEG and DIO data for SEGDIO51 thr ough S EGDIO 55. If configur ed as DIO,
bit 1 is di r ec tion (1 is output , 0 is input), bit 0 is data, and t he other bits are
ignor ed.
SEG DIO 52 th rou gh SEDIO54 are avai lable only on the 71M6542F/G.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
LCD_VMODE[1:0] 2401[7:6] 00
00
R/W
Specif ies how VLCD is generated. See 2.5.8.4 for the definition of V3P3L.
LCD_VMODE
Description
11
Ext er nal V LCD
10
LCD boost and LCD DAC enabl ed
01
LCD DAC enabl ed
00
No boost and no DAC. VLCD=V3P3L.
LCD_Y 2400[2] 0 – R/W
LCD Bli nk Frequenc y (i gnor ed if bli nk i s disabled).
1 = 1 Hz, 0 = 0.5 Hz
LKPADDR[6:0]
2887[6:0]
0
0
R/W
The addres s for readi ng and wri ting the RTC lookup RAM
LKPAUTOI 2887[7] 0 0 R/W
Auto-incr em ent fl ag. When set, LKPADDR auto-increments every time
LKP_RD or LKP_WR is pulsed. The inc r em ented addres s can be read at
LKPADDR[6:0].
LKPDAT[7:0]
2888[7:0]
0
0
R/W
The dat a for reading and wri ting the RTC lookup RAM.
LKP_RD
LKP_WR 2889[1]
2889[0] 0
0 0
0 R/W
R/W
Str obe bits for the RT C look up RA M read and write. W hen set, the
LKPADDR[6:0] fi eld an d LKPDAT register is used in a r ead or write
operation. When a str obe is set , it stays set until the operation c om pletes, at
which time th e s trobe is cleared and LKPADDR[6:0] is incremented if the
LKPAUTOI bit is set .
MPU_DIV[2:0] 2200[2:0] 0 0 R/W
MPU clock rate is:
MPU Rat e = MCK Rat e * 2-(2+MPU_DIV[2:0]).
The maximu m value for MPU_DIV[2:0] is 4. Based on the default values of
the PLL_FAST bit and MPU_DIV[2:0], the power up MPU rate is 6.29 MHz
/ 4
= 1.5725 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAS T =
1.
MUX0_SEL[3:0]
2105[3:0]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted during time slot 0.
MUX1_SEL[3:0]
2105[7:4]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 1.
MUX2_SEL[3:0]
2104[3:0]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 2.
MUX3_SEL[3:0]
2104[7:4]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 3.
MUX4_SEL[3:0]
2103[3:0]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 4.
MUX5_SEL[3:0]
2103[7:4]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time sl ot 5.
MUX6_SEL[3:0]
2102[3:0]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 6.
MUX7_SEL[3:0]
2102[7:4]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 7.
MUX8_SEL[3:0]
2101[3:0]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted during time slot 8.
MUX9_SEL[3:0]
2101[7:4]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 9.
MUX10_SEL[3:0]
2100[3:0]
0
0
R/W
Sel ec ts whi c h A DC input is to be converted dur ing time slot 10.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
MUX_DIV[3:0] 2100[7:4] 0 0 R/W
MUX_DIV[3:0] is the n umbe r of A DC time s lots in each MU X fr ame. T he
maximum number of tim e slots i s 11.
OPT_BB 2457[0] 0 – R/W
Configures the input of the opt ical port to be a DIO pi n to allow it to b e
bit-banged. In t his case, DI O5 becom es a third high speed UART. Refer to
2.5.7 UART and Opti c al Int erface under the “Bit Banged Optical UART
(Third UART)” sub-heading on page 58.
OPT_FDC[1:0] 2457[5:4] 0 – R/W
Sel ec ts OPT_TX modulati on duty cycle.
OPT_FDC
Function
00
50% Low
01
25% Low
10
12.5% Low
11
6.25% Low
OPT_RXDIS 2457[2] 0 – R/W
OPT_RX can be configur ed as an i nput t o the opti c al UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55
OPT_RXINV 2457[1] 0 – R/W
Inverts result from OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX i s used as a DIO i nput.
OPT_TXE [1:0] 2456[3:2] 00
– R/W
Configures the O PT_TX output pin.
If LCD_MAP[51] = 0:
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE
If LCD_MAP[51] = 1:
xx = SEG51
OPT_TXINV
2456[0]
0
–
R/W
Invert OPT_TX when 1. This inv er si on oc c ur s befor e m odulation.
OPT_TXMOD 2456[1] 0 – R/W
Ena bles modulat ion of OP T_TX. When OPT_TXMOD is set, OPT_T X is
m odul ated when it wo uld otherwise have been zero. The modulation is applied
aft er any inv er si on c aused by OPT_TXINV.
OSC_COMP 28A0[5] 0 – R/W
Enables the automa t ic upda te of RTC_P and RTC_Q e very time th e temperat ure
is measured.
PB_STATE
SFR F8[0]
0
0
R
The de-bounced state of t he PB pin.
PERR_RD
PERR_WR SFR FC[6]
SFR FC[5] 0 0 R/W
The IC sets these bit s to indic ate that a parity error on the remote sensor has
been detected. Once set, the bits are remember ed until they are clear ed by
the MP U.
PLL_OK
SFR F9[4]
0
0
R
Indicat es that t he cl oc k generat ion PLL is settled.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
PLL_FAST 2200[4] 0 0 R/W Contr ols the speed of the PLL and MCK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] 210A[7:0] FF
FF
R/W
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going
pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pul se
width is (2*PLS_MAXWIDTH[7:0] + 1) *TI. Where TI is PLS_INTERVAL[7:0] in
units of CK_F I R clock cycle s. If PLS_INTERVAL[7:0] = 0 or
PLS_MAXWIDTH[7:0] = 255, n o pulse width checking i s perf ormed and the
output pulses have 50% duty cycle. See 2.3.6.2 VPULSE and WPULSE.
PLS_INTERVAL[7:0] 210B[7:0] 0 0 R/W
PLS_INTERVAL[7:0] determines the interva l time between pulses. The time
between output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock
cycles. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output
as soon as the CE issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0] = Flo or ( Mux frame duratio n in CK_FIR cycl es / CE pulse
updates per Mux frame / 4 )
For example, since the 71M654x CE code is written to generate 6 pulses in one
integration interval, when the FIFO is enab led (i.e ., PLS_INTERVAL[7:0] ≠ 0)
and that the frame duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0]
should be writ ten with Floor(1950 / 6 / 4) = 81 so that the five pulses are
ev enly spaced in tim e over the int egr ati on interv al and the last pulse i s issued
just pr ior to the end of the int erval. See 2.3.6.2 VPULSE and WPULSE.
PLS_INV 210C[0] 0 0 R/W
Inverts the polarity of WPULSE, VARPULSE, XPULSE and YPULSE.
Normally, these pul ses are active low. When inv er ted, t hey bec om e ac tive
high.
PORT_E 270C[5] 0 0 R/W E nables output s from the pins SEGDIO0-SEGDIO15. PORT_E = 0 aft er reset
and power-up blocks the m om entary output pulse that would occur on
SEGDIO0 to SEGDIO 15.
PRE_E
2704[5]
0
0
R/W
Enabl es the 8x pr e-amplifier.
PREBOOT
SFRB2[7]
–
–
R
Indicat es that pre-boot sequence is active.
RCMD[4:0] SFR FC [4 :0] 0 0 R/W
When the MPU writes a no n-zero value to RCMD[4:0], the IC issues a
command to the appropriate remote sensor. When the command is complete,
the IC clears
RCMD[4:0]
.
RESET
2200[3]
0
0
W
When set, writ es a one to WF_RSTBIT and then causes a reset .
RFLY_DIS 210C[3] 0 0 R/W
Controls how t he IC drives the power pulse for the 71M6x01. When set, the
power pul se i s driven high and low. When cl ear ed, it is driven high followed
by an open circuit fly-back interval.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
RMT_E 2709[3] 0 0 R/W Enabl es the r em ote digital isolation interface, which transform s the IBP-IBN
pins into a digit al balanced diff er ential pair. Thus, enabl ing t hese pi ns to
interface to the 71M6 x01 isolated sensor.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0 0 R Response from remote read request.
RTC_FAIL 2890[4] 0 0 R/W
Indicat es that a count error has occurred in the RTC and that the time is not
trustworthy. This bit can be cl ear ed by wri ting a 0.
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0 R/W RT C adjust. See 2.5.4 Real-Time Clock (RTC).
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] for m a s ingle 19-bit RTC adjus tmen t value .
RTC_Q[1:0] 289D[1:0] 0 0 R/W
RTC adjust. See 2.5.4 Real-Tim e Cloc k (RT C).
Note: RTC_P[16:0] and RTC_Q[1:0] for m a s ingle 19-bit RTC adjus tmen t value .
RTC_RD 2890[6] 0 0 R/W
Freez es the RTC shadow register so it is suit able for MPU r eads. When
RTC_RD is read, it retur ns the status of the shadow register: 0 = up to date, 1
= frozen.
RTC_SBSC[7:0]
2892[7:0]
–
–
R
Time remaining until the next 1 second boundary. LS B = 1/256 second.
RTC_TMIN[5:0]
289E[5:0]
0
–
R/W
The target minutes register. See RTC_THR below.
RTC_THR[4:0] 289F[4:0] 0 – R/W
The t ar get hours register. The RT C_T int er r upt occ urs when RTC_MIN
becomes equal to
RTC_TMIN and
RTC_HR
becomes equal to
RTC_THR
.
RTC_WR 2890[7] 0 0 R/W
Freez es the RTC shadow register so it is suit able for MPU wri tes. When
RTC_WR i s cleared, the c ontents of the shadow register are written to the
RTC counter on the next RTC cl oc k (~500 Hz). When RTC_WR is read, it
returns 1 as l ong as RTC_WR is set. It continues to return one until the RTC
counter actually updates.
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W
The RTC inter face register s. These are the year , month, day , hour, minute
and sec on d parameters for the RTC. The RTC is s et by writing to t he s e
registers. Year 00 and all other s divi sibl e by 4 are defined as a leap year .
SEC 00 to 59
MIN 00 to 59
HR 00 to 23 (00 = Midnight)
DAY 01 t o 07 (01 = Sunday)
DATE 01 to 31
MO 01 to 12
YR 00 to 99
Each write operation to one of these regi ster s must be preceded by a write to
0x20A0.
RTCA_ADJ[6:0]
2504[7:0]
40
–
R/W
Anal og RTC frequency adjust register.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
RTM_E
2106[1]
0
0
R/W
Real Time Monitor enable. When 0, the RTM output is low.
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0
0
0
0
0
0
R/W
Four RTM pr obes. B efore each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM register s are ignored when
RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume t he upper
two bit s are 00.
SECURE SFR B 2[6] 0 0 R/W Inhibits era s ure of pag e 0 and f la s h addres s es above t he be ginning of CE code
as define d by CE_LCTN[5:0].
Also inhib its the rea d o f fla s h via the SPI and ICE
port.
SLEEP 28B2[7] 0 0 W Puts the part to SLP mode. Ignored if system power is present. The part
wakes when the Wake timer times out, when push button is pushed, or when
syste m pow er returns.
SPI_CMD[7:0]
SFR FD [7 :0]
–
–
R
SPI command register for the 8-bit command from the bus master.
SPI_E 270C[4] 1 1 R/W SP I port enabl e. Enables SPI interface on pi ns SEGDIO36 – SEGDIO39.
Requires that LCD_MAP[36-39] = 0.
SPI_SAFE 270C[3] 0 0 R/W
Limi ts SPI writ es to SPI_CMD and a 16-byte region i n DRAM . No other
writes are perm itted.
SPI_STAT[7:0] 2708[7:0] 0 0 R
SPI_STAT contains the status result s from the pr ev ious SPI transaction.
Bit 7: Ready err or : The 71M654x was not r eady to read or wri te as directed
by the pr ev ious command.
Bit 6: Read data parity: This bit is the pari ty of all byt es read f r om the
71M654x in t he previous command. Does not incl ude the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the byt es writ ten to the
71M654x in t he previous command. It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte cou nt. Does no t include ADDR and CMD
by tes. On e, two, an d three byte
instructions retur n 111.
Bit 1: SPI FLASH mode: This bit is z er o when the TEST pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the
flash is ready t o receive another writ e instr uc tion.
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
–
–
–
–
R
R
The resul t of the temperature measurement.
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
2107[4:0]
2108[7:0]
0 0 R/W The number of multiplexer cycles per X FER_BUSY interrupt. Ma ximu m value
is 8191 cyc les.
TBYTE_BUSY 28A0[3] 0 0 R
Indicat es that hardware i s sti ll writing the 0x28A0 byte. Additional wri tes to
this byte are l oc k ed out while it is one. Wri te durati on coul d be as l ong as
6ms.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
TEMP_22[10:8]
TEMP_22[7:0]
230A[2:0]
230B[7:0]
0 – R Storage location for STEMP at 22C. STEMP is an 11-bit wor d.
TEMP_BAT 28A0[4] 0 – R/W
Causes VBAT to be measured whenever a temperature measurement is
performed.
TEMP_BSEL 28A0[7] 0 – R/W
S elects which b attery is monitored by the tempe ra ture sensor : 1 = VBAT ,
0 = VBAT_RTC
TBYTE_BUSY 28A0[3] 0 0 R
Indicat es that hardware i s sti ll writing the 0x28A0 byte. Additional wri tes to
this byte will be lock ed out while it is one. Write duration could be as long as
6ms.
TEMP_PER[2:0] 28A0[2:0] 0 – R/W
Sets the period between temperature measurements. Automatic measurements
can be enabl ed in any mode (MSN, BRN, LCD, or S LP). TEMP_PER = 0
disabl es automatic temperature updates, in whic h c ase TEMP_START may be
used by the MPU to initiate a one-s hot te mperature measurement.
TEMP_PER
Ti me ( secon ds)
0
No temper ature updat es
1-6
2(3+TEMP_PER)
7
Continuous update s
TEMP_PWR 28A0[6] 0 – R/W
Sel ec ts the power sourc e for the t em p sensor:
1 = V3P3D, 0 = VB AT_RTC. T his bi t is ignored in S LP and LCD modes,
where the temp sensor is always powered by V B A T_RTC.
TEMP_START 28B4[6] 0 0 R/W
When TEMP_PER = 0 aut om at i c tem p e ra tu r e me a su rem e nt s ar e disabl e d,
and TEMP_START may b e set by the MPU to initiate a on e-s hot temperature
measurement. TEMP_START is ignored in SLP and LCD modes. Hardware
clears TEMP_START when the temperature measurement is complete.
TMUX[5:0]
2502[5:0]
–
–
R/W
Sel ec ts one of 32 signals for TMUXOUT. See 2.5.12 for details.
TMUX2[4:0]
2503[4:0]
–
–
R/W
Sel ec ts one of 32 signals for TMUX2OUT. See 2.5.12 for details.
TMUXRA[2:0]
270A[2:0]
000
000
R/W
The T M UX setting for the remote isolated sensor (71M6x01).
VERSION[7:0] 2706[7:0] – – R
The sili c on versio n in dex. This word m ay be rea d by firmwar e to det ermine
the sil i con version.
VERSION[7:0]
Silicon Version
0001 0011
0010 0010
B01
B02
VREF_CAL 2704[7] 0 0 R/W
Brings the ADC reference voltage out to the VREF pin. This feature is disabled
when VREF_DIS=1.
VREF_DIS
2704[6]
0
1
R/W
Disabl es the int er nal ADC voltage refer enc e.
71M6541D/F/G and 71M6542F/G Dat a S heet
Name Location
Rst
Wk
Dir Description
VSTAT[2:0] SFR F9[2: 0] – – R
This word describes the sourc e of power and the status of the VDD.
VSTAT
Description
000
System Power OK. V3P3A>3.0v. Analog modules are functional
and accurate. [V3AOK,V3OK] = 11
001
System Power Lo w. 2.8v<V 3P 3A <3.0v. Analog mo dul es not
accurate. Switc h over to batt er y power is imminent.
[V3AOK,V3OK] = 01
010
Battery power and VDD OK. VDD>2.25v. Full digital functionality.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 11
011
Battery power and VDD>2.0. Flash writes are inhibited. If the
TRIMVDD[5] fuse is blown, PLL_FAST (I/O RAM 0x2200[4]) is
cleared.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 01
101
Battery power and VDD<2.0. When V STAT=101, processor is
nearl y out of volt age. Pr oc essor f ailur e is imminent.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 00
WAKE_ARM 28B2[5] 0 – R/W
Arms the WAKE timer and loads i t wit h WAKE_TMR[7:0]. When SLEEP or
LCD_ONLY is assert ed by the MPU, the WAK E tim er becomes active.
WAKE_TMR[7:0]
2880[7:0]
0
–
R/W
Timer duration is WAKE_TMR+1 seconds .
WD_RST 28B4[7] 0 0 W
Reset the W D timer. The WD i s reset when a 1 is written t o this bit. Writing a
one cl ear s and restarts the watch dog timer.
WF_DIO4 28B1[2] 0 – R
DIO 4 wake flag bit. If DIO4 is configur ed to wake the part, this bit is set
whenever the de-bounc ed v er si on of DIO4 ri ses. It is held in reset if DI04 is
not configured f or wakeup.
WF_DIO52 28B1[1] 0 – R
DIO52 wake flag bit. If DIO52 is configured to wake the part, this bit is set
whenever the de-bounced version of DIO52 ris es . It is held in reset if DI052 is
not configured f or wakeup.
WF_DIO55 28B1[0] 0 – R
DIO55 wake flag bit. If DIO55 is configured to wake the part, this bit is set
whenever the de-bounced version of DIO55 rises. It is held in reset if DI055 is
not configured f or wakeup.
WF_TMR
28B1[5]
0
–
R
Indicat es that t he wake tim er c aused the par t to wake up.
WF_PB
28B1[3]
0
–
R
Indicat es that t he PB caused the par t t o wake.
WF_RX
28B1[4]
0
–
R
Indicat es that RX caused the part to wake.
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
28B0[7]
28B0[6]
28B0[5]
28B0[4]
28B0[3]
28B0[2]
0
1
0
0
0
0
– R Indi c ates that the Reset pin, Reset bit, ERST pi n, Watchdog timer, the cold
start detect or , or bad V BAT caused the part to reset.
71M6541D/F/G and 71M6542F/G Dat a S heet
5.3 CE Interface Description
5.3.1 CE Pr ogram
The CE performs the precision computations necessary to accurately meas ure energy. These computations
inc lud e of f set ca nc el lat i on, ph a se com pe n sati on, prod uct smoothin g, pr odu ct summ at i on, f requ en cy
detecti on, VAR calculation, sag detection and v oltage phase m easurement . All dat a comput ed by the CE
is dependent on the selected met er equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]).
The CE pr ogr am is supplied by Teridian as a data image that c an be merged wit h the MPU operational
code for meter applications. T y pic ally, t he CE program provided with the demonstr ati on c ode covers
m ost applications and does not need to be modif ied. Other variations of CE code are ava ilable fro m
Teridian. The descriptions provided i n this secti on apply to the CE code revisions shown in Table 77.
Pl ease cont ac t the loc al Teridian representative t o obtain the appropriate CE code required for a specific
application.
Table 77. Standard CE Codes
Device L ocal Sensors Remo t e S ensor
71M6541D/F/G CE41A01 (Eq. 0 or 1) CE41B016601
CE41B016201
(Eq. 0, 1 or 2)
71M6542F/G CE41A01 (E q. 0 or 1)
CE41A04 (E q. 2)
5.3.2 CE Data Format
All CE words are 4 bytes. Unless specifi ed otherwise, they are in 32-bit two’s complement format
(-1 = 0xFFFFFFFF ). Calibration parameters are defined in flash memor y (or exter nal EEPROM) and
m ust be c opied to CE data memory by the MPU befor e enabling the CE. Internal vari ables are used in
internal CE calculations. Input variables allow the MPU to cont r ol the behavior of the CE code. Output
v ari ables are outputs of the CE calculations. The corr espondi ng M P U addr ess for the most si gnificant
byte is given by 0x 0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least signif ic ant byte.
5.3.3 Constants
Constants used in the CE Data Memory tables are:
• Sam pling Frequency : FS = 32768 Hz/13 = 2520.62 Hz.
• F0 is the fundamental frequency of t he mains phases.
• IMAX is the external rms current correspondi ng to 250 mV pk (176.8 mV rms) at the inputs IA and IB.
IMAX needs to be adjusted if the pre-amplifier is activated for the IAP-IAN inputs. For a 250 µΩ shunt
resistor, IMAX becomes 707 A (176.8 mV rms / 250 µΩ = 707.2 A rms).
• VMAX is the external rms voltage cor r espondi ng to 250 mV pk at the VA and VB inputs.
• NACC, the acc um ulation count for ener gy m easurements is SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0],
0x2108[7:0]).
• The durat ion of the accumulation i nterval for energy measurements is SUM_SAMPS[12:0] / FS.
• X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW
(see Table 83).
• Voltage LSB (for sag threshold) = VMAX * 7.879810-9 V.
The system constants IMAX and VMAX are used by the MPU to conver t internal digital quantiti es (as
used by the CE) to external, i.e., metering quantities. Their values are det ermined by the scaling of the
v oltage and curr ent sensors used i n an ac tual met er. The LSB values used in this docum ent relate digital
quantities at the CE or MP U interfac e to external m eter i nput quantiti es. For example, if a SAG thr eshol d
of 80 V rms is desired at the meter input, the di gital value that shoul d be pr ogra mmed into SAG_THR (CE
R AM 0x2 4) would be 80 Vrms * SQR T(2)/SAG_THRLSB, w here SAG_THRLSB is the LS B value in the
descripti on of SAG_THR (see Table 84).
71M6541D/F/G and 71M6542F/G Dat a S heet
The param eters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are
essenti al t o the f unction of the CE are stor ed in I/O RAM (see 5.2 I/O R AM Ma p – Alphabetical Order for
details).
5.3.4 Environment
Before st arting the CE using t he CE_E bit (I/O RAM 0x 210 6[ 0]), the M P U has to establish the pr oper
environment for the CE by implementing the f ollowing s teps:
• Locate t he CE code i n Flash m em ory usi ng CE_LCTN[5:0] (I/ O RAM 0x2109[ 5:0])
• Load the CE dat a into RAM
• Establish the equat ion to be appli ed in EQU[2:0 ] (I/O RAM 0x21 06[7:5])
• Establish the number of sam ples per accum ulati on period in SUM_SAMPS[1 2:0] ( I/O RA M 0x2107[4:0],
0x2108[7:0])
• Establish the number of cy cl es per ADC m ultiplexer frame (MUX_DIV[3:0] (I/O RAM 0x2100[7:4]))
• Apply pr oper v alues to MUXn_SEL, as well as proper sel ec tions for DIFFn_E (I/O RAM 0x210C[5:4])
and RMT_E (I/O RAM 0x2709[3]) i n order t o configur e the analog inputs
• Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or the power failure detection interrupt
• VMAX = 600 V, IMA X = 707 A, and kH = 1 Wh/pul se are assumed as default settings
When different CE codes are used, a different set of env ir onm ent parameters need to be establi shed.
The exac t values for these parameter s are listed in the Appl ic ation Notes and other doc um entation whic h
accompanies the CE c ode.
Operating CE codes w ith environment parameters deviating from the values specified by Teridian
leads to unpr edictable results. See Table 1 and Table 2.
Typically , t her e ar e thir teen 32768 Hz cycl es per ADC m ultiplexer frame (see 2.2.2 Input M ultipl ex er).
This means that the product of the num ber of cycles per slot and the number of conversions per frame
m ust be 1 2 ( plus one se t tling cy c le per frame, see Figure 6 and Figure 7). The defa ult c onfig uration is
FIR_LEN[1:0] = 01, I/O RAM 0x210C[2:1], (three cycles per conversi on) and MUX_DIV[3:0] = 3 (3
conversions per multiplexer cycle).
Sample confi gur ations can be copi ed from Dem o Code provided by Teridian with the Demo K its.
5.3.5 CE Calcu lations
Referring to Table 78, The MPU selects the desired equati on by writing the EQU[2:0] (I/O RAM
0x2106[7:5]).
Table 78: CE EQU Equations and Element Input Mapping
EQU Watt & V AR Fo rmul a
(WSUM/VARSUM)
Inputs Used for Energy/Current Calculation
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQ
SUM
I1SQ
SUM
0
VA IA – 1 element, 2W 1φ
VA*IA
VA*IB
IA
–
1
VA*(IA-IB)/2 – 1 element, 3W 1φ
VA*(IA-IB)/2
–
IA-IB
IB
2†
VA*IA + VB*IB – 2 element, 3W 3
φ
Delta
VA*IA
VB*IB
IA
IB
Note:
†
71M6542F/G only.
71M6541D/F/G and 71M6542F/G Dat a S heet
5.3.6 CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by r e ading addr es s es 0 -3, 9 and 10 (decimal) shown
in Table 79.
The MUX_SEL co lumn in Table 79 shows the MUX_SEL handles f or the v ari ous sensor i nput pins. For
example, if differential mode is enable via control bit DIFFA_E = 1 (I/O RAM 0x210C[4]), then the inputs IAP
and IAN are combined together to form a single differential input and the corresponding MUX_SEL handle is
0. Similarly, the CE RAM location column provides the CE RAM address where the sample data is stored.
Conti nuing with the same example, if DIFFA_E = 1, the corresponding CE RA M loc ation where the
samples for the IAP-IAN differenti al input are stored is 0 and CE RAM locat ion is not disturbe d.
The IB input can be configured as a direct-connected sensor (i.e., directly connected to the 71M654x) or as a
remote sensor (i.e., using a 71M6x01 Isolated Sensor). If the remote sensor is disabled by RMT_E = 0 and
differential mode is enabled by DIFFB_E = 1 (I /O R AM 0x210C[5]), then IBP and IBN form a dif ferenti al
input with a MUX_SEL handle of 2, and the corresponding samples are stored in CE RAM location 2 (CE
RAM location 3 is not disturbed). If the r emote sen s or enable bi t RMT_E = 1 and DIFFB_E = 0 or 1, then the
MUX_SEL handle is undefined (i.e., the sensor is not connected to the 71M654x, so MUX_SEL does not
apply, see 2.2 Analog Front End (AFE) on page 12), an d the sa mp les corr es po nding to this remote
differential IBP-IBN input are stored in CE RAM location 2 (CE RAM location 3 is not disturbed).
The voltage sensor inputs (VA and VB) do not have any ass oc iat ed configuration bits. VA has a MUX_SEL
handle value of 10, and its samples are stored in CE RAM location 10. VB has a MUX_SEL handle value of 9
and its samples are stored in CE RAM location 9.
Table 79: CE Raw Data Access Lo cat io ns
ADC
Location Pin MUX_SEL Handle CE RAM Lo cat ion
DIFFA_E
DIFFA_E
0
1
0
1
ADC0
IAP
0
0
0
0
ADC1
IAP
1
1
RMT_E, DIFFB_E
RMT_E, DIFFB_E
0,0
0,1
1,0
1,1
0,0
0,1
1,0
1,1
ADC2
IBP
2
2 – –
2
2 2* 2*
ADC3
IBN
3
3
There ar e no c onfigurati on bits for ADC9, 10
ADC9
VB†
9
9
ADC10
VA
10
10
Notes:
* Remo te interface data.
†
71M6542F/G only.
5.3.7 FCE Status and Control
The CE Status Word, CESTATUS, is useful for generating early warnings to the MPU (Table 80). It contains
sag wa r nings for phase A and B , as well as F0, the derived clock operating a t the fundamental input fre-
quency. The MPU can r ead the CE st atus word at every CE_B US Y i nterr upt. Since the CE_BUSY i nter-
rupt oc c ur s at 2520.6 Hz, it is desirable to minimiz e the com putation requi r ed in the interrupt handler of
the MP U.
Table 80: CESTATUS Register
CE Address
Name
Description
0x80
CESTATUS
See descri pti on of CESTATUS bits in Table 81.
CESTATUS provide s information about th e status of v olt age an d inp ut AC signal f requ ency, which are u s eful
for generating an early power fail warni ng to initiate necessary data storage. CESTATUS represents the
71M6541D/F/G and 71M6542F/G Dat a S heet
status fl ags for the pr ec eding CE code pass (CE _B US Y interrupt ) . The signific anc e of the bits in
CESTATUS is shown i n Table 81.
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions
CESTATUS
bit Name Description
31:4
Not Used
These unused bi ts are always zero.
3
F0
F0 is a square wave at the e xact fundamental input frequency.
2
Not Used
This unused bit is always zero.
1 SAG_B
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT s amples. Does not return to zero until VB rises above
SAG_THR
.
0 SAG_A
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT s amples. Does not return to zero until VA rises above
SAG_THR.
The CE is i nitialized by the MPU using CECONFIG (Table 82). This regi ster c ontains in packed form
SA G _CNT, FREQSE L[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are
given in Table 83.
Table 82: CECONFIG Register
CE
Address Name Data Description
0x20 CECONFIG
0x0030DB001
0x00B0DB00
2
See descri pti on of the CECONFIG bits i n
Table 83.
1. Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE c ode for use with local
sensors.
2. Default for CE41B 016201 and CE41B016601 codes th at support t he 71M 6x 01 remote
sensors.
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions
CECONFIG
bit Name Default Description
23 Reserved 0
When this bit i s set, c ontrol of temper ature com pensation is
enabled for the 71M6x01 I sol ated Sensor Int erface.
22 EXT_TEMP 0
When 1, t he M P U contr ols tem per ature com pensation via the
GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, t he CE i s in
control.
21 EDGE_INT 1
When 1, XPULSE produces a pul se for eac h z er o-crossing of
the mains phase sel ec ted by FREQSEL[1:0] , whi c h c an be used
to interrupt the MP U.
20 SAG_INT 1
W hen 1, activ ates YPULSE output when a sag condition i s
detected.
19:8 SAG_CNT 252
(0xFC)
The number of consecutive volt age samples below SAG_THR
(CE RAM 0x24) before a s ag alar m is declared. The default value
is equival ent t o 100 ms.
7:6
FREQSEL[1:0]
0
FREQSEL[1:0] selec ts the phase to be used f or the frequency
m onitor, sag detect ion, and for the z er o crossing count er
(MAINEDGE_X, CE R AM 0x83 ).
FREQ SEL[1:0]
Phase S elected
0
0
A
0
1
B*
1
X
Not allowed
*71M6542F/G only
71M6541D/F/G and 71M6542F/G Dat a S heet
5 EXT_PULSE 1
When zero, causes the pul se generator s to r espond to int er nal
data (WPULSE = WSUM_X (CE RAM 0x84) , VPULSE = VARSUM_X
(CE RAM 0x88)). Otherwise,
the generators re spon d to values the
MPU places in APULSEW and APULSER ( CE RAM 0x45 and 0x49).
4:2 Reserved 0
Reserved.
1 PULSE_FAST 0
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse g enerator in put is
reduced by a factor of 64. These two param eters control the
pulse gai n fact or X (see table below). Allowed values are eit her
1 or 0. Default is 0 for both ( X = 6).
PULSE_FAST
PULSE_SLOW
X
0
0
1.5 * 22 = 6
1
0
1.5 * 26 = 96
0
1
1.5 * 2-4 = 0. 09375
1
1
Do not use
0 PULSE_SLOW 0
The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag
interrupt. Thus, a SAG_INT event occur s when the selected phase ha s sati sfi ed the sag ev ent cri teria as
set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]).
When the SAG_INT bit ( CE RAM 0x20[20]) is se t to 1, a sag event generat es a transi ti on on the YPULSE
output. In a two-phase system ( 71M6542F/G), and after a sag int er r upt, the MPU should change the
FREQSEL[1:0] setting t o sel ec t t he other phase, if it is powered. Even t hough a sag i nterrupt is only
generated on the selected phase, both phase s are simultaneously checked for sag. The presence of
power on a given phase can be sensed by dir ec tly checking t he SAG_A and SAG_B bits in CESTATUS (CE
RAM 0x80[0:1]).
The EXT_TEMP bit enables temperature com pensation by the MPU, when set to 1. When 0, inter nal ( CE )
temper ature com pensation is enabled.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external
pulse generat ion) by placing v alues i nto APULSEW and APULSER ( C E RAM 0x4 5 and 0x49). By sett ing
EXT_PULSE = 0, the CE controls the pulse rat e based on WSUM_X ( CE RAM 0x84) and VARSUM_X (CE
RAM 0x88).
The 71M6541D/F/G and 71M6542F/G Demo Code creep function hal ts both inter nal and exter nal
pulse generat ion.
Table 84: S ag Thresho ld and Gain Adjust Control
CE
Address
Name Default Description
0x24 SAG_THR 2.39*107
The v oltage thr eshol d for sag warnings. The de fault value is
equivalent to 113V pk or 80 Vrm s if V M A X = 600 Vrms.
_=2
7.8798 10
0x40 GAIN_ADJ0 16384
This register scales the voltage measurement channels VA and
VB*. The default value of 16384 is equivalent to unity gain (1.000).
*71M6542F/G only
0x41 GAIN_ADJ1 16384
This register scales the IA cur r ent channel for Phase A. The
default value of 1 6384 is equivalent to unity gain (1.000).
0x42 GAIN_ADJ2 16384
This register scales the IB current channel for Phase B. The
default value of 16384 i s equivalent t o unity gain (1.000).
5.3.8 CE Transfer Variables
71M6541D/F/G and 71M6542F/G Dat a S heet
When the MPU receives the XFER_B US Y interrupt, it knows that f r esh data is avail able in the transf er
variables. CE transfer v ari ables are modified duri ng the CE code pass that ends with an XFE R_B US Y
interrupt. They remain constant throughout eac h ac c um ulation interval. In this data sheet, t he nam es of
CE tr ansfer variables always end with “_X”. The transfer variables can be cat egor ized as:
• Fundamental energy measurement variables
• Instantaneous (RMS) values
• Other measurement parameters
5.3.8.1 Fund amental Energy Measuremen t V ariables
Table 85 and Table 86 describe each transfer variable for fundamenta l energy measurement. All
v ari ables are signed 32-bit integers. Accumulated variables such as WSUM ar e internally scaled so they
have at least 2x mar gin before ove r flow whe n the integration tim e is one second. Additionally, the hardw are
does no t permit output values to fold back upon overfl ow.
Table 85: CE Transfer Variables (with Local Sensors)
CE
Address
Name Description Configuration
0x84† WSUM_X
The signed sum: W0SUM_X+W1SUM_X. Not used
for EQU[2:0] = 0 (I/O RA M 0x210 6[7 :5]) and
EQU[2:0] = 1 .
Figure 35 (page 93)
Figure 37 (page 95)
0x85
W0SUM_X
The sum of Wh sam ples fr om eac h wattmet er
element.
LSBW = 9.4045*10
-13
* VMAX * IMAX Wh.
0x86
W1SUM_X
0x88† VARSUM_X
Th e signe d s um: V AR0SUM_X+VAR1SUM_X. Not
used for EQU[2:0] = 0 and EQU[2:0] = 1.
0x89
VAR0SUM_X
The sum of VA Rh samples from each wattmeter
element.
LSBW = 9.4045*10
-13
* VMAX * IMAX VARh.
0x8A
VAR1SUM_X
Note:
†
71M6542 onl y .
Table 86: CE Tran sf er V ariables (with Remot e S ensor)
CE
Address
Name Description Configuration
0x84† WSUM_X
The signed sum: W0SUM_X+W1SUM_X. Not used
for EQU[2:0] = 0 (I/O RA M 0x210 6[7 :5]) and
EQU[2:0]
= 1.
Figure 36 (page 94)
Figure 38 (page 96)
0x85
W0SUM_X
The sum of Wh sam ples fr om eac h wattmet er
element.
LSB = 1.55124*10
-12
* VMAX* IMAX Wh.
0x86
W1SUM_X
0x88† VARSUM_X
Th e signe d s um: V AR0SUM_X+VAR1SUM_X. Not
used for EQU[2:0] = 0 and EQU[2:0] = 1.
0x89
VAR0SUM_X
The sum of VA Rh samples from each wattmeter
element.
LSB = 1.55124*10
-12
*VMAX* IMAX VARh.
0x8A
VAR1SUM_X
Note:
†
71M6542 onl y .
WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x 88) ar e the signed sum of Phase-A and Phase-B Wh
or VARh v alues accor ding t o the metering equati on specif ied in the I/O RAM control field EQU[ 2:0] (I/O
RAM 0x 2106[7: 5]). WxSUM_X (x = 0 or 1, CE RAM 0x85 and 0x86) is the Wh value accumu lated for phas e x
in the last accumulation interval and can be computed based on the specif ied LSB value.
71M6541D/F/G and 71M6542F/G Dat a S heet
5.3.8.2 Inst antaneous Energy Measurement Variables
IxSQSUM_X and VxSQSUM (see Table 87) are the sum of the squared cur r ent and voltage samples
acqui r ed dur ing the l ast accumulati on interval.
Table 87: CE Energy Measurement Variables (with Local Sensors)
CE
Address
Name Description Configuration
0x8C I0SQSUM_X
The sum of squared curr ent samples fr om eac h
element.
LSBI = 9.4045*10-13 IMAX2 A2h
When EQU = 1, I0SQSUM_X i s based on IA and
IB.
Figure 35 (page 93)
Figure 37 (page 95)
0x8D I1SQSUM_X
0x90 V0SQSUM_X
The sum of squared voltage samples from eac h
element.
LSBV= 9.4045*10-13 VMAX2 V2h
0x91† V1SQSUM_X
† 71M6542 only.
Table 88: CE Energy Measurement Variables (with Remote Sen sor)
CE
Address Name Description Configuration
0x8C
I0SQSUM_X
The sum of squared curr ent samples fr om eac h
element.
LSBI = 2.55872*10-12 * IMAX2 A2h
When EQU = 1, I0SQSUM_X i s based on IA and
IB.
Figure 36 (page 94)
Figure 38 (page 96)
0x8D
I1SQSUM_X
0x90
V0SQSUM_X
The sum of squared voltage samples from eac h
element.
LSBV= 9.40448*10-13 * VMAX2 V2h
0x91
†
V1SQSUM_X
† 71M6542 only.
The RMS v alues can be com puted by the MPU f r om the squared curr ent and voltage samples as follows:
Note: NACC = SUM_SAMPS[12:0] (CE RAM 0x23).
Other Transfer vari ables include those av ailable for frequency and phase measurement, and those
refl ecting the count of the zer o-cross ings of the ma ins voltage and the battery voltage. These transf er
variables are listed in Table 89.
MAINEDGE_X (CE RAM 0x83) reflects the num ber of half-cycles accounted for in the last accumu lated
interval fo r the AC signal of the phase specified in the FREQSEL[1:0] field in CECONFIG (CE RAM 0x2 0[7: 6] ).
MAINEDGE_X is useful for implementing a real-time clock based on the i nput AC signal.
ACC
SI
RMS NFLSBIxSQSUM
Ix ⋅⋅⋅
=3600
ACC
SV
RMS NFLSBVxSQSUM
Vx
⋅⋅⋅
=3600
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 89: Other Transfer V ariables
CE
Address
Name Description
0x82 FREQ_X Fundamental frequency: LSB
6
32 10509.0
2
6.2520 −
⋅≈≡ Hz
Hz(for Local)
LSB
6
32 10587.0
2
6.2520 −
⋅≈≡ Hz
Hz(f or Rem ote)
0x83 MAINEDGE_X
The number of edge crossings of the select ed v oltage in t he pr evious
accumul atio n i nt erval . E d ge c r os si ng s ar e ei t h er di r ec ti o n a nd ar e
de-bounced.
5.3.9 Pulse Generation
Table 90 describes the CE pulse generation parameters.
The com binati on of the CECONFIG PULSE_SLOW and PULSE_FAST bits (CE RAM 0x20[0:1]) controls the
speed of the pulse rate. The def ault values of 0 and 0 maintain the original pul se rat e giv en by the Kh
equation.
WRATE (CE RAM 0x21) controls the number of pulses that are generat ed per m easured W h and V A Rh
quant ities . The lower WRATE is, the slo wer t he pulse ra te for the measur ed energ y quant ity . The metering
constant K h is derived from WRATE as the amount of energy measured for eac h pulse. That is, if Kh =
1Wh/pulse, a power ap plied to the meter of 120 V a nd 30 A results in on e puls e per secon d. If the l oad
is 2 40 V at 150 A, te n pulses per second are generated.
Control is transferr ed to the MPU for pulse generat ion if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case,
the pulse rate is det ermined by APULSEW and APULSER (CE R AM 0x45 an d 0x49). The MPU has to
l oad the source f or pul se generation in APULSEW and APULSER to generate pulses. Irrespect ive of t he
EXT_PULSE status, t he output pulse rat e c ontrolled by APULSEW and APULSER is implem ented by the CE
only. By set ting EXT_PULSE = 1, the MP U is providing the source for pulse generat ion. If EXT_PULSE is
0, W0SUM_X ( CE RAM 0x85) and VAR0SUM_X (CE R AM 0x89) are the def ault pulse generation sources. In
this case, creep cannot be cont r olled si nc e it is an MPU function.
The maximu m pulse rate is 3*FS = 7.56 kHz.
See 2.3.6.2 VPULSE and WPULSE for details on how to adjust t he timing of the output pulses.
The maximu m time jitter is 1/6 of the multiplexer cycle period (nominally 67 µs) and is independent of t he
num ber of pulses measured. Thus, if the pulse generator is monitor ed for one second, t he peak jitter is
67 ppm . Aft er 10 seconds, the peak jit ter is 6.7 ppm . The average jitter is al ways zero. If it is att em pted
to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum ra te w ithout
ex hibiti ng any rollover characteristics. The actual pulse rat e, using WSUM as an exam ple, is:
Hz
XFWSUMWRATE
RATE
S
46
2
⋅⋅⋅
=
,
where FS = sampling fr equenc y ( 2520.6 Hz), X = P ulse speed factor derived from the CE variables
PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1]).
71M6541D/F/G and 71M6542F/G Dat a S heet
Table 90: CE Pulse G eneration Parameters
CE
Address Name Default Description
0x21 WRATE 547
pulseWh
XNWRATE KIMAXVMAX
Kh
ACC
/⋅
⋅⋅
⋅⋅
=
where:
K = 66.1782 (Local Sensors)
K = 109.1587 ( Rem ote Sensor)
NACC = SUM_SAMPS[12:0] (CE RAM 0x23)
See Table 83 f or the defi nition of X.
The def ault value yields 1.0 Wh/pulse for VMAX = 600 V and
IMA X = 208 A. The maximu m va lue for WRATE is 32,768 (2
15
).
0x22
KVAR
6444
Scale factor for VAR measurement.
0x23
SUM_SAMPS
2520
SUM_SAMPS (NACC).
0x45 APULSEW 0
Wh pulse (WPULSE) generator input to be updated by the MPU
when using exter nal pulse generation. T he output pulse rat e is:
APULSEW * FS * 2 -32 * WRATE * X * 2-14.
This input is buffered and can be updated by the MP U during a
conversion interval. The change takes effect at the be ginning of
the next interval.
0x46
WPULSE_CTR
0
WPULSE counter.
0x47 WPULSE_FRAC 0
Unsigned numerator, containing a f raction of a pulse. The val ue
in this r egis ter always c ounts up towards the next pulse.
0x48
WSUM_ACCUM
0
Roll-over accu mulator for WPULSE.
0x49
APULSER
0
VARh (VPULSE) pulse generator input.
0x4A
VPULSE_CTR
0
VPULSE counter.
0x4B VPULSE_FRAC 0
Unsigned numerator, containing a f raction of a pulse. The val ue
in this r egis ter always c ounts up towards the next pulse.
0x4C
VSUM_ACCUM
0
Roll-over accumulator for VPULSE.
71M6541D/F/G and 71M6542F/G Dat a S heet
5.3.10 Other CE Parameters
Table 91 shows the CE parameters used for suppressi on of noi se due to scaling and tr unc ation ef fect s.
Table 91: CE Parameters for Noise Suppressi on and Code Versio n
CE
Address Name Default Description
0x25
QUANT_VA
0
Compensation factors for truncation and noise in voltage, current,
real ener gy and r eac tive energy for phase A.
0x26
QUANT_IA
0
0x27
QUANT_A
0
0x28
QUANT_VARA
0
0x29 †
QUANT_VB
0
Compensation factors for truncation and noise in voltage, current,
real ener gy and r eac tive energy for phase B.
† 71M6542 onl y .
0x2A
QUANT_IB
0
0x2B
QUANT_B
0
0x2C
QUANT_VARB
0
0x38
0x43453431
CE file name identifier in ASCII format (CE41a01f). These values
are overwritt en as soon as the CE star ts
0x39
0x6130316B
0x3A
0x00000000
LSB weight s for use wit h Loc al Sensors:
)(1008656.5__ 2213 AmpsIMAXLSBIxQUANT ⋅⋅= −
)(1004173.1__ 9WattsIMAXVMAXLSBWxQUANT ⋅⋅⋅= −
)(1004173.1__
9
VarsIMAXVMAXLSBVARxQUANT ⋅⋅⋅=
−
LSB weight s for use wit h the 71M6x01 isol ated sensors:
)(1038392.1__ 2212 AmpsIMAXLSBIxQUANT ⋅⋅= −
)(1071829.1__ 9WattsIMAXVMAXLSBWxQUANT ⋅⋅⋅= −
)(1071829.1__ 9VarsIMAXVMAXLSBVARxQUANT ⋅⋅⋅= −
71M6541D/F/G and 71M6542F/G Dat a S heet
5.3.11 CE Calibration Parameters
Table 92 lists the par ameters that ar e typic ally entered to effect calibration of meter accurac y .
Table 92: CE Calibrat ion Parameters
CE
Address Name Default Description
0x10
CAL_IA
16384
These constants contr ol the gai n of t heir r espect ive channels. The
nominal value for each para meter is 214 = 16384. The gain of eac h
channel is directl y pr opor tional to its CAL parameter. Thus, if the
gain of a channel is 1% slow, CAL should be increased by 1%.
Refer to the 71M6541 Demo Boar d Us er ’s Manual for the equat ions
to calc ulat e these cali br ation parameters.
†
71M6542 onl y .
0x11
CAL_VA
16384
0x13
CAL_IB
16384
0x14†
CAL_VB
16384
0x12 PHADJ_A 0 These constants control the CT phase compensation. Compensation
does not occur when PHADJ_X = 0. As PHADJ_X is increased,
m or e compensation (lag) is introduc ed. The range is ± 215 – 1. If
it is desired t o delay the cur r ent by the angle Φ, the equations are:
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 0131.01487.0 02229.0
2_ 20
at 60Hz
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 009695.01241.0 0155.0
2_ 20
at 50Hz
0x15 PHADJ_B 0
0x12 DLYADJ_A 0
The shunt delay c om pensation is obtained using the equation
provided bel ow:
( )
+
+
∆+∆=
s
ss
reesrees
ff
c
b
ff
ab
ff
a
XDLYADJ
π
ππ
π
2
sin
2
cos2
2
cos
360
2
21.01_
22
14
degdeg
where:
Aa 2=
1
2
+= Ab
= 2+ 42
+ 2
Where, f is the ma ins frequency and fs is the sampling frequency.
The t able below provides the value of A for each current channel:
Channel
Val ue of A
(decimal)
Eq. 0 or 2
Eq. 1
DLYADJ_A
15811 / 214
6811 / 214
DLYADJ_B
-1384 / 214
-1384 / 214
0x15 DLYADJ_B 0
71M6541D/F/G and 71M6542F/G Dat a S heet
5.3.12 CE Flow Diagrams
Figure 44 through Figure 46 show the data flow through the CE in sim plified form. F unc tions not shown
inc lude delay c om pensation, sag detect ion, scaling and the processing of m eter equati ons.
Figure 44: CE Data Flo w: Mu ltiplexer an d ADC
Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables
71M6541D/F/G and 71M6542F/G Dat a S heet
Figure 46: CE Data Flo w: Squaring and Summatio n Stages
I0
W0
SQUARE
W1
VAR0
VAR1
V0
I1
I0SQ
V0SQ
I1SQ
SUM
I0SQSUM_X
V0SQSUM_X
I1SQSUM_X
SUM W0SUM_X
W1SUM_X
VAR0SUM_X
VAR1SUM_X
Σ
Σ
Σ
Σ
Σ
Σ
Σ
SUM_SAMPS=2520
MPU
F0
I
2
I
2
V
2
71M6541D/F/G and 71M6542F/G Dat a S heet
6 Electrical Specifications
This secti on pr ov ides the electrical specif ications for the 71M654x. Please refer to the 71M6xxx Data
Sheet for the 71M6x01 electric al specif icati ons, pin-out, and package mechanical dat a.
The devices are 100% produc tion tested at room t em peratur e, and performance o ver the full te mperature
range i s guarant eed by desi gn.
6.1 Absolute Maximum Ratings
Table 93 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings
m ay cause permanent dam age to t he dev ic e. These are stress ratings only and functional oper ation at
these or any ot her c onditi ons beyond t hose i ndicated under r ec om mended oper ating conditions (see 6.3
Recommended Operating Cond itions ) is not implied. E xposure to ab s olute-maximum-rate d condi tions
for ext ende d perio ds may affec t devic e reli ability. All volt ages are wit h r espect to GNDA.
Table 93: Abso lu t e M aximu m Rating s
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A
−
0.5 V to 4.6 V
VBAT, VB AT_R TC
-0.5 V to 4.6 V
GNDD
-0.1 V to +0.1 V
A na log Output P ins
VREF
-10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
VDD
-10 mA to 10 mA,
-0.5 t o 3.0 V
V3P3D
-10 mA to 10 mA,
-0.5 V to 4.6 V
VLCD
-10 mA to 10 mA,
-0.5 V to 6 V
A na log Input Pins
IAP-IAN, VA, IBP-IBN, VB
†
(
†
71M6542F/G
only)
-10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
XIN, XOUT
-10 mA to +10 mA
-0.5 V to 3.0 V
SEG and SEGDIO Pins
Configured as SEG or COM drivers
-1 mA to 1 mA,
-0.5 V to V LCD+0.5 V
Configured as Di gital Inputs
-10 mA to 10 mA,
-0.5 V to 6 V
Configured as Di gital Outputs
-10 mA to 10 mA,
-0.5 V to V 3P 3D+0.5 V
Digital Pins
Inputs (PB, RESET, RX, ICE_E, TEST)
-10 mA to 10 mA,
-0.5 t o 6 V
Outputs (TX)
-10 mA to 10 mA,
-0.5 V to V 3P 3D+0.5 V
Temperature and ESD Stress
Operating junction temperature (peak, 100ms)
140 °C
Operating junction temperature (continuous)
125 °C
Stor age temperature
−45 °C t o +165 °C
71M6541D/F/G and 71M6542F/G Dat a S heet
Sol der temperature – 10 second duration
+250 °C
ESD stress on all pi ns
±
4 kV
6.2 Recommended External Components
Table 94: Recommended Extern al Co mponents
Name
From
To
Function
Value
Unit
C1
V3P3A
GNDA
Bypass capacit or for 3.3 V suppl y
≥
0.1
±
20%
µ
F
C2
V3P3D
GNDD
Bypass capacit or for 3.3 V output
0.1
±
20%
µ
F
CSYS
V3P3SYS
GNDD
Bypass capacitor for V3P3SYS
≥
1.0
±
30%
µ
F
CVDD
VDD
GNDD
Bypass capacitor for VDD
0.1
±
20%
µ
F
CVLCD VLCD GNDD
Bypass capacitor for VLCD pin (when
charge pump is used)
≥0.1 ±20% µF
XTAL XIN XOUT
32.768 kHz crystal – electrically similar to
ECS .327-12.5-17X, Vishay XT26T or
Suntsu SCP6–32.768kHz TR (load
capacitanc e 12.5 pF).
32.768 kHz
CXS XIN GNDA Load capacitor values for crystal depend on
crystal specifications and board parasitics.
Nomi nal v alues are based on 4 pF board
capacitanc e and inc lude an allowance for
chi p c apaci tance.
15 ±10% pF
CXL XOUT GNDA 10 ±10% pF
6.3 Recommended Operating Conditions
Unless otherwise speci fi ed, all parameters listed in 6.4 Performanc e S pecificati ons and 6.5 Timing
Specifications are vali d ov er the Rec ommended Operating Conditions provided in Table 95 below.
Table 95: Recommended Operati ng Conditions
Parameter
Condition
Min
Typ
Max
Unit
V3P3SYS and V3P3A Supply Voltage for
prec is ion me tering oper at ion (M SN mode ) .
Vol tages at VBAT and VBAT_RT C need
not be present.
VBAT=0 V to 3.8 V
VBAT_RTC =0 V to
3.8 V 3.0 3.6 V
VBAT Voltage (BRN m ode). V3P3SYS is
below the 2. 8 V comparator threshold.
Ei ther V3P3SYS or VBAT _RTC must be
high enough to power the RTC m odule.
V3P3SYS < 2.8 V
and
Max (VBAT_RTC,
V3P3SYS) > 2.0 V
2.5 3.8 V
VBAT_RTC Voltage. VB AT_RTC is not
needed to support the RTC and non-
volatile memory unless V3P3SYS < 2.0 V
V3P3SYS<2.0 V 2.0 3.8 V
Operating Temperature
-40
+85
ºC
Notes:
1. GNDA and GNDD must be connected together.
2. V3P 3S Y S and V 3P 3A must be connected together.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4 Performance Specifications
6.4.1 Input Logic Levels
Table 96: Input L ogic Lev e ls
Parameter Condition Min Typ Max Unit
Digital hi gh-level input voltage1, VIH
2
V
Digital l ow-leve l input voltage1, VIL
0.8
V
Input pullup current, I
IL
E_RXTX, E_RST, E_TCLK
OPT_R X, OPT_ TX
SPI _CS Z (S EGDIO 36)
Other d igital inputs
VIN=0 V,
ICE_E=3.3 V
10
10
10
-1
0
100
100
10
1
µA
µA
µΩ
µA
Input pull down current , IIH
ICE_E, RESE T, TEST
Other d igital inputs
VIN=V3P3D
10
-1
0
100
1
µA
µA
Note:
1. In battery powered modes, digital inp uts s houl d be below 0.1 V or above VBAT – 0.1 V to
minimize battery current.
6.4.2 Output Logic Levels
Table 97: Output Logic Levels
Parameter
Condition
Min
Typ
Max
Unit
Digital hi gh-level output voltage
VOH
ILOAD = 1 mA
V3P3D–0.4
V
I
LOAD
= 15 mA
(see note s 1, 2)
V3P3D-0.6
V
Digital l ow-leve l output voltage
VOL
ILOAD = 1 mA
0
0.4
V
I
LOAD
= 15 mA
(see note 1)
0
0.8
V
Note:
1. G uar anteed by design, not pr oduc tion t ested.
2. Caution: The sum of all pull up c ur r ents must be compati ble with the on-resistance of the
internal V3P 3D switc h. See 6.4.6 V3P3D Switch on page 143.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.3 Battery Monitor
Table 98: Bat t ery Monitor Performance Speci ficat ions (TEMP_BAT= 1)
Parameter Condition Min Typ Max Unit
BV: Battery Volt age
(definition)
MSN mode, TEMP_PWR = 1
BRN mode,
TEMP_PWR=TEMP_BSEL
= 3.3+( 142)0.0246+297
= 3.291+( 142)0.0255+ 328
V
Measurem ent Err or
−⋅ 1100 VBAT
BV
VBAT =
2.0 V
2.5 V
3.0 V
4.0 V
-7.5
-5
-3
-3
7.5
5
3
5
%
Input impedance in
continuous m easurement,
MSN mode.
V(VBAT_RTC)/I(VBAT_RTC)
V3P3 = 3.3 V,
TEMP_BSEL = 0,
TEMP_PER = 111,
VBAT_RTC = 3.6 V, 1 MΩ
Load applied wit h BCURR
IBAT(BCURR=1) - IBAT(BCURR=0)
V3P3 = 3.3 V 50 100 140 µA
6.4.4 Tempera ture Monitor
Table 99. Temperature Monitor
Parameter
Condition
Min
Typ
Max
Unit
Temper ature Measurement
Equation
In MSN , TEMP_PWR=1:
= 0.325 +22
In BRN, TEMP_PWR = TEMP_BSEL:
= 0.325 + 0.00218 0.609  +64.4
°C
Temper ature Er r or TA=+22°C -2 +2 °C
VBAT_RTC charge per
measurement
TEMP_BSEL = 0,
TEMP_PWR=0,
SLP Mode,
VBAT_RTC = 3.6 V
16 µC
Duration of tem per ature
m easurement after set ting
TEMP_START
(see note 1)
TEMP_PWR
= 0,
TEMP_PER = 7,
SLP Mode,
VBAT_RTC = 3.6 V
Force V3P3D = 1.0 V
15 60 ms
Notes:
1. G uar anteed by design; not pr oduc tion t ested.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.5 Supply Current
The supply c ur r ents provided in Table 100 bel ow inc lude only the cur r ent consumed by the 71M654x.
Refer to the 71M6xxx Data Sheet for additional c urrent requi r ed when using a 71M6x01 rem ote sensor.
Table 100: Supply Current Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
I1:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Single-phase: 2 Current s, 1 Vol t age
V3P3A = V3P3SYS = 3.3 V,
MPU_DIV [2:0]= 3 (614 kHz MPU clock),
No Flash memor y write ,
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=1, MUX_DIV[3:0]=3,
FIR_LEN[1:0]=1, PLL_FAST=1
5.5 6.7 mA
I1a:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Same as I1, except PLL_FAST=0
2.6 3.5 mA
I1b:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Same as I1, except PRE_E = 1 5.7 6.9 mA
I1c:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Same as I1, except PLL_FAST = 0 and
PRE_E = 1 2.6 3.6 mA
I2:
V3P3A + V3P3 SYS dynamic
current
S ame a s I1, except with variation of
MPU_DIV[2:0].
4.3
I-I 3MPU_DIV0MPU_DIV ==
0.4 0.6 mA/
MHz
VBAT current
I3: MSN Mod e
I4: BRN Mode
I5: LCD Mode (ext. VLCD)
I6: LCD Mode (boost, DAC)Note 1
I7: LCD Mode (DAC)Note 1
I8: LCD Mode (VBAT)Note 1
I9: SLP Mode
CE_E=0
LCD_VMODE[1:0]=3, also see not e 2
LCD_VMODE[1:0]=2, al so see note 3
LCD_VMODE[1:0]= 1, also see n ote 3
LCD_VMODE[1:0]= 0, also see n ote 3
SLP Mode
-300
-300
0
2.4
0.4
24
3.0
1.1
0
300
3.2
108
36
11
3.4
+300
nA
mA
nA
µA
µA
µA
nA
VBAT_RTC current
I10: MSN
I11: BRN
I12: LCD Mode
I13: SLP Mode
I14: SLP Mode (see n ote 1)
LCD_VMODE[1:0]=2, also see n ote 2
TA ≤ 25 °C
TA = 85 °C
-300
0
240
1.8
0.7
1.5
300
320
4.1
1.7
3.2
nA
nA
µA
µA
µA
I15:
V3P3A + V3P3SYS current,
Write Fl as h with ICE
S am e as I1, except writ e Flash at maximum rate,
CE_E=0, ADC_E=0. 7.1 8.7 mA
Notes:
1. Guaranteed by design; not producti on tested.
2. LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 1, LCD_BLANK=0,
LCD_ON=1.
3. LCD_DAC[4:0]=5 (2.9V ), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.6 V3P3D Switch
Table 101: V3P3D Switch Performance Specification s
Parameter
Condition
Min
Typ
Max
Unit
On resi stanc e – V3P3SYS to V3P3D
| IV3P3D | ≤ 1 mA
10
Ω
On resistance – VBAT to V3P3 D
| I
V3P3D
| ≤ 1 mA,
VBAT>2.5V
10 Ω
V3P3D I
OH
, MSN
V3P3SYS = 3V
V3P3D = 2. 9V
10 mA
V3P3D I OH, B RN VBAT = 2.6V
V3P3D = 2. 5V
10 mA
6.4.7 Internal Power Fault Compa rators
Table 102. Internal Power Fault Co mparator Specifications
Parameter
Condition
Min
Typ
Max
Unit
Overall response time
100mV o verdr ive, falling
100m V ov er drive, rising
20
200
200
µs
µs
Falling Thr eshol d
3.0 V Comparator
2.8 V Comparator
Diff er enc e 3.0V and 2.8V Comparator s
V3P3 falling
2.83
2.75
50
2.93
2.81
136
3.03
2.87
220
V
V
mV
Falling Thr eshol d
2.25 V Comparator
2.0 V Comparator
VDD (@VBAT=3.0V) – 2.25V Comparat or
Diff er enc e 2.25V and 2.0V Comparator s
VDD falling
2.2
1.90
0.25
0.15
2.25
2.00
0.35
0.25
2.5
2.20
0.45
0.35
V
V
V
V
Hysteresis,
(Rising Threshold - Falling Threshold)
3.0 V Comparator
2.8 V Comparator
2.25 V Comparat or
2.0 V Comparator
T
A
= 22 °C
22
25
10
10
45
42
33
28
65
60
60
60
mV
mV
mV
mV
6.4.8 2.5 V Voltage Regulator – System Power
Table 103: 2.5 V Voltage Regul ator Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
V2P5
V3P3 = 3. 0 V - 3.8 V
ILOAD = 0 mA
2.55 2.65 2.75 V
V2P5 load regulati on
VBAT = 3.3 V , V3P3 = 0 V
ILOAD = 0 mA to 1 mA
40 mV
Vol tage overhead V 3P 3SYS-V2P5
I
LOAD
=
5 mA,
Reduce V3P3D until V2P5
drops 200 mV
440 mV
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.9 2 .5 V Voltage Regulator – Battery Power
Unless otherwise speci fi ed, V3P3SYS = V3P3A = 0, PB=GND (BRN).
Table 104: Low -Power Vol t age Regulator Performance Specifi cat io ns
Parameter Condition Min Typ Max Unit
V2P5
VBAT = 3.0 V - 3.8 V,
V3P3 = 0 V, ILOAD = 0 mA
2.55 2.65 2.75 V
V2P5 load regulati on
VBAT = 3. 3 V, V3P3 = 0 V,
ILOAD = 0 mA to 1 mA
40 mV
Voltage Overhead 2V − VBAT-VDD
I
LOAD
=
0ma, VBAT = 2.0 V,
V3P3 = 0 V.
200 mV
6.4.10 Crystal Oscillator
Measurem ent condit ions: Cry stal disconnected, test load of 200 pF/100 kΩ bet ween XOUT and G NDD.
Table 105: Cryst al Oscillator Performance Specifications
Parameter Condition Min Typ Max Unit
Maximum Output Power to Crystal
Crystal connected, see note 1
1
μW
XIN to XOUT Capaci tance
(see note 1)
3 pF
Capaci tance change on XOUT
RTC_ADJ = 7F to 0,
Bi as voltage = unbiased
Vpp = 0.1 V
15 pF
Notes:
1. G uaranteed by design; not product i on t ested.
6.4.11 Phase-Locked Loop (PLL)
Table 106: P LL Perfo rmance Specifications
Parameter
Condition
Min
Typ
Max
Unit
PLL Power up Settli ng Time
(see note 1)
PLL_FAST = 0, V3P3 = 0 V to 3.3 V
step, measured fr om first edge of
MCK
5 ms
PLL_FAST settling time
PLL_FA S T rise (see note 1)
PLL_FAST fall ( see note 1)
V3P3 = 0 V, VBAT = 3.8 V to 2.0 V
5
5
ms
ms
PLL SLP to MSN Settling Time
(see note 2)
PLL_FAST = 0 5 ms
PLL power up overshoot
(see note 1)
PLL_FAST = 0 2.5 MHz
Notes:
1. G uaranteed by design; not product i on t ested.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.12 LCD Drivers
Table 107: LCD Driver Perf ormance Specificati on s
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
VLCD Current
(see Notes 1 to 4)
VLCD=3.3 , all LCD map bits=0
VLCD=5.0 , all LCD map bits=0
2
3
uA
uA
Notes:
1. These spec i f icati ons appl y to all CO M and SEG pins.
2. VL CD = 2.5 V t o 5 V.
3. LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2.
4. Output load is 74 pF per SEG and CO M pin.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.13 VLCD Generator
Table 108: LCD Dri ver P erf ormance Specification s1
Parameter Condition Min Typ Max Unit
VSYS to VLCD switch impedance
V3P3 = 3.3 V,
RVLCD=removed, LCD_BAT=0,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
750 Ω
VBAT to VLCD switch impedance
V3P3 = 0 V, VBAT = 2.5 V,
RVLCD =removed, LCD_BAT =1,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
700 Ω
LCD Boost Frequency
LCD_VMODE[1:0] = 2,
RVLCD = removed,
CVLCD = removed
PLL_FAST=1
PLL_FAST=0
820
786
kHz
kHz
VLCD IOH current
(VLCD(0)-VLCD(IOH)<0.25)
LCD_VMODE[1:0] = 2,
LCD_CLK[1:0] = 2 ,
RVLCD = removed,
V3P3 = 3.3V,
LCD_DAC[4:0] = 1F
10 µA
From LCDADJ0 and LCDADJ12 fu ses:
(_)= 50 + 12 0
12
_
(_)= 2.65 + 2.65 _
31 +(_)
The above equati ons descri be the nominal value of VLCD for a specific LCD_DAC value. The
specif ications below list t he m aximum deviation between act ual V LCD and VLCDno m. Note that when
VCC and boost are insufficient, the LCD DAC will not reach it s tar get value and a large negative error
will oc c ur .
LCD_DAC Error. VLCD-VLCDnom
( see no te 2)
Full Scale, with Boost
V3P 3 =3.6 V
V3P 3 =3.0 V
VBAT=4.0 V, V3P3=0, BRN Mode
VBAT=2.5 V, V3P3=0, BRN Mode
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.4
-0.15
-1.3
0.15
0.15
0.15
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
DAC=12, with Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 2 .5 V, V3P3 = 0 V, BRN Mode
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Zero S cale, w ith Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4 .0 V, V3P3 = 0 V, BRN Mode
(see no te 2)
VBAT = 2 .5 V, V3P3 = 0 V, BRN Mode
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] =0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.15
-0.15
-0.15
0.15
0.15
0.15
0.15
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Full Scale, no Boost
V3P3 = 3.6 V (see no te 2)
V3P3 = 3.0 V (see no te 2)
VBAT = 4 .0 V, V3P3 = 0 V, BRN Mode
VBAT = 2 .5 V, V3P3 = 0 V, BRN Mode
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-2.1
-2.8
-1.8
-3.2
V
V
V
V
71M6541D/F/G and 71M6542F/G Dat a S heet
Parameter Condition Min Typ Max Unit
LCD_DAC Error. VLCD-VLCDnom
DAC=12, no Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4 .0 V, V3P3 = 0 V, BRN Mode
VBAT = 2 .5 V, V3P3 = 0 V, BRN Mode
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.5
-1.1
-0.152
-1.52
0.152
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Zero S cale, no Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4 .0 V, V3P3 = 0 V, BRN Mode
VBAT = 2 .5 V, V3P3 = 0 V, BRN Mode
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.15
-0.15
-0.45
0.15
0.15
0.15
0.15
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Full Scale, with Boost, LCD mode
VBAT = 4 .0 V, V3P3 = 0 V
VBAT = 2 .5 V, V3P3 = 0 V
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-1.3
0.15
V
V
Notes:
1.
The following test conditions also apply to all parameters provided in this table: bypass capacitor CVLCD ≥
0.1 µF, test load RVLCD = 500 kΩ, no display, all SEGDIO pins configured as DIO.
2. Guaranteed by design; not producti on tested.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.14 VREF
Table 109 shows the performanc e specif ic ations f or the ADC reference voltage (VREF).
Table 109: VREF Performance Specifications
Parameter Condition Min Typ Max Unit
VREF output voltage,
VREF(22)
T
A
= 22 ºC
1.193 1.195 1.197 V
VREF output voltage,
VREF(22)
PLL_FAST=0
1.195 V
VREF output impedance
VREF_CAL = 1,
ILOAD = 10 µ A, -10 µ A
3.2 kΩ
VREF power supply sensitivity
ΔVREF / ΔV3P3A
V3P3A = 3.0 to 3. 6 V -1.5 1.5 mV/V
VREF input impedance
VREF_DIS = 1,
VREF = 1.3 V to 1.7 V
100 kΩ
VREF chop step, trimmed
VREF(CHOP=01) −
VREF(CHOP=10)
-10 0 10 mV
VNOM definition (see note 2)
2)22(1)22()22()( 2TCTTCTVREFTVNOM −+−+=
V
VNOM temperature
coefficients:
TC1 =
TC2 =
TRIMT⋅− 95.4275
TRIMT⋅+− 00028.0557.0
µV/°C
µV/°C2
VREF(T) de viation from
VNOM(T) (see note 1):
62
10
)( )()(
6
TVNOM TVNOMTVREF −
-40 +40 ppm/°C
VREF aging
±25
ppm/
year
Notes:
1. G uara nteed b y des ign; not produc tion teste d.
2. This relationship describes the nominal behavior of VREF at different temperatures, as governed by a
second order poly nomial of 1st and 2nd order coef fi cients TC1 and TC2.
3. For the parameters in this table, unless otherwise specified, VR EF_DIS = 0, PLL_FAST=1.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.4.15 ADC Converter
Table 110. ADC Con vert er P erf ormance Speci ficat ions
Parameter Condition Min Typ Max Unit
Recommended I nput Range
(Vin - V3P3A)
-250
250
mV
peak
Vol tage to Current Cr osstal k
)cos(
*106VcrosstalkVin
Vin
Vcrosstalk ∠−∠
( see no te 1)
Vin = 200 mV peak,
65 Hz, on VADC10 (V A )
or VADC9 (VB)†
†71M6542F/G only.
Vcrosstalk = largest
measurement on IAP-IAN
or IBP-IBN
-10 10 μV/V
Input Impedance, no pre-amp
Vin=65 Hz
40
90
kΩ
ADC Gai n Error vs %Power S upply
Variation
3.3/33100 /35710
6
APV VnVNout
INPK
∆
∆
Vi n=200 mV pk, 65 Hz
V3P3A=3.0 V, 3.6 V
50 ppm / %
Input Of fset
IADC0=IADC1=V3P3A
IADC0=V3P3A
DIFF0_E=1, PRE_E=0
DIFF0_E=0, PRE_E=0
-10
-10
10
10
mV
mV
THD @ 250mVpk
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B
1
0
0
2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F
0
1
0
2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
V
IN
= 65Hz, 2 5 0 mV p k,
64kpts FFT, Blackman Harris
Window.
A
B
-82
C
D
-84
E
F
-83
G
H
-86
J
A
-75
B
-75
C
-75
D
-75
E
-75
F
-75
G
-75
H
-75
J
-75
dB
THD @ 20mVpk
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B
1
0
0
2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F
0
1
0
2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
V
IN
= 65Hz, 2 0 mVp k,
64kpts FFT, Blackman Harris
Window.
A
-85
B
-91
C
-85
D
-91
E
-93
F
-85
G
-85
H
-91
J
-93
dB
LSB Si ze:
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B
1
0
0
2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F
0
1
0
2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
Vi n=65Hz, 20mVpk,
64kpts FFT, Blac kman-
Harris wi ndow
A
3470
B
406
C
3040
D
357
E
151
F
3470
G
3040
H
357
J
151
nV
Dig ital Full -Scale:
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B
1
0
0
2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F
0
1
0
2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
A: ±91125
B: ±778688
C: ±103823
D: ±884736
E: ±2097152
F: ±91125
G: ±103823
H: ±884736
J: ±2097152
LSB
71M6541D/F/G and 71M6542F/G Dat a S heet
Notes:
1. G uar anteed by design; not pr oduc tion t ested.
2. Unless stated ot her wise, the following test c onditi ons appl y to all the parameter s provided in
this tabl e: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values
do not include t he 9-bit left shift at CE input.
6.4.16 Pre-Amplifier for IAP-IAN
Table 111: Pre-Amplifier Performance Specifications
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Differen tia l Gain
Vi n=30mV diff er ential
Vi n=15mV diff er ential (see note 1)
T
A
= +25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
7.8
7.8
7.92
7.92
8.0
8.0
V/V
V/V
Gain Varia tion vs V3P3
Vi n=30mV diff er ential (see note 1)
V3P3 =
2.97 V, 3.63 V
-100 100 ppm/%
Gain Variation vs Temp
Vi n=30mV diff er ential (see note 1)
TA = -40⁰C, 85⁰C 10 -25 -80 ppm/C
Phase Shift,
Vi n=30mV diff er ential (see note 1)
T
A
=25⁰C,
V3P3=3.3 V
-6 6 mº
Preamp input curr ent
IADC0
IADC1
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1
2520Hz sample rate,
IADC0=IADC1=V3P3
4
4
9
9
16
16
uA
uA
Preamp+ADC THD
Vi n=30mV diff er ential
Vi n=15mV diff er ential
T
A
=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate.
-82
-86
dB
dB
Preamp Offset
IADC0=IADC1=V3P3+30mV
IADC0=IADC1= V3P3+15 mV
IADC0=IADC1= V3P3
IADC0=IADC1= V3P3-15mV
IADC0=IADC1= V3P3-30mV
T
A
=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
-0.63
-0.57
-0.56
-0.56
-0.55
mV
mV
mV
mV
mV
Notes:
1. G uar anteed by design; not pr oduc tion t ested.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.5 Timing Specifications
6.5.1 Flash Memory
Table 112: Flash Memory Timing Specifications
Parameter
Condition
Min
Typ
Max
Unit
Flash write c ycles
-40 °C t o +85 °C
20,000
Cycles
Flash data ret ention
25 °C
85 °C
100
10
Years
Flash byte writes between page or
m ass erase operati ons
2 Cycles
Write Time per Byte
21
µs
Page Erase (1024 bytes)
21
ms
Mass Erase
21
Ms
6.5.2 SPI Slave
Table 113. SPI Slave Timing Specifications
Parameter
Condition
Min
Typ
Max
Unit
SPI S etup Time
SPI _DI to SPI_CK rise
10
ns
SPI Hold Time
SPI _CK ri se to SPI _DI
10
ns
SPI Output Delay
SPI_CK fall to SPI_D0
40
ns
SPI Rec ov er y Tim e
SPI _CS Z f all to SPI_CK
10
ns
SPI Removal Time
SPI _CK to SPI_CS Z ri se
15
ns
SPI Cloc k Hi gh
40
ns
SPI Cloc k Low
40
ns
SPI Clock Freq
SPI Freq/MPU Freq
2.0
MHz/MHz
SPI Transaction Space
SPI _CS Z rise to S PI_CS Z f all
4.5
MPU Cycl es
6.5.3 EEPROM Interface
Table 114: EEPROM Interface Timing
Parameter Condition Min Typ Max Unit
Write Clock frequenc y (I2C)
CKMPU = 4.9 MHz,
Using i nterrupts
310 kHz
CKMPU = 4.9 MHz,
bit-bangi ng DIO 2/3
PLL_FAST = 0
100 kHz
Write Clock frequenc y ( 3-wire)
CKMPU = 4.9 MHz
PLL_FAST = 0
PLL_FAST = 1
160
500
kHz
71M6541D/F/G and 71M6542F/G Dat a S heet
6.5.4 RESET Pin
Table 115: RESET Pin Timing
Parameter Condition Min Typ Max Unit
Reset pulse width
5
µs
Reset pulse fall time (see note 1)
1
µs
Notes:
1. G uar anteed by design; not pr oduc tion t ested.
6.5.5 RTC
Table 116: RTC Ran ge for Date
Parameter Condition Min Typ Max Unit
Range for date
2000
-
2255
Year
71M6541D/F/G and 71M6542F/G Dat a S heet
6.6 Package Outline Drawings
6.6.1 64-Pin LQFP Outline Package Drawing
11.7
12.3
0.60 Typ.
1.40
1.60
11.7
12.3
0.00
0.20
9.8
10.2
0.50 Typ. 0.14
0.28
PIN No. 1 Indicator
+
Figure 47: 64-pin LQ FP Pa c k a ge Out l ine
71M6541D/F/G and 71M6542F/G Dat a S heet
6.6.2 100-Pin LQFP Package Outline Drawing
Controlling dimensions are in mm .
Figure 48: 100-pin LQFP Package Outline
1
15.7(0.618)
16.3(0.641)
15.7(0.618)
16.3(0.641)
Top View
MAX. 1.600
0.50 TYP.
14.000 +/- 0.200
0.225 +/- 0.045
0.60 TYP>
1.50 +/- 0.10
0.10 +/- 0.10
Sid e Vi ew
71M6541D/F/G and 71M6542F/G Dat a S heet
6.7 Package Markings
1
71M6541D-
IGT.428AB
104224TH
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
32
26
27
28
29
30
17
18
19
20
21
22
23
24
25
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64
63
62
61
51
52
53
54
55
56
57
58
59
60
49
50
1
71M6542G-IGT
110124TK
445AP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
92
93
94
95
96
97
98
99
100
26
27
28
29
30
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 49. Package Markings (Exampl es)
Figure 49 pr ov ides an example of the package mar ki ngs for the 64-pi n and 100-pin pac k ages. P ac k age
m ar ki ngs compr ise three lines of text and are as described in Table 117 and Table 118 below.
Table 117. 71M 6541 P ackage Markings
Line N o.
Markings
Description
1 71M6541D-
Part num ber ( ‘IGT’ wraps to the nex t li ne)
Refer to Table 122.
2 IGT.428AB
The five character s to the right of the dot
(i .e., 428AB ) are the l ot code.
3 104224TH
The fi r st four digit s to the lef t are the year
and week of m anufact ur e as YYW W. In
this example, the date code is 1042 whi c h
represents year 2010, week 42.
The last four charac ters (i.e., 24TH) are
reserved for M axim int er nal use onl y .
Table 118. 71M 6542 P ackage Marking s
Line N o.
Markings
Description
1
71M6542G-IGT
Part num ber . Ref er to Table 122.
2 110124TK
The fi r st four digit s to the lef t are the year
and week of m anufact ur e as YYW W. In
th is example, t he date code is 1101 which
represents year 2011, week 1.
The last four charac ters (i.e., 24TK) ar e
reserved for M axim int er nal use onl y .
3
445AP
A five charac ter lot code.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.8 Pinout Diagrams
6.8.1 71M6541D/F/G LQFP-64 Package Pinout
1
Teridian
71M6541D
71M6541F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
32
26
27
28
29
30
17
18
19
20
21
22
23
24
25
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64
63
62
61
51
52
53
54
55
56
57
58
59
60
49
50
SPI_DI/SEGDIO38
SPI_CSZ/SEGDIO36
COM1
COM2
COM3
COM0
SEGDIO27/COM4
SPI_DO/SEGDIO37
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
SEGDIO1/VPULSE
SEGDIO3/SDATA
OPT_RX/SEGDIO55
SEGDIO14
SEGDIO13
SEGDIO10
SEGDIO11
SEGDIO12
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
SEGDIO4
SEGDIO2/SDCK
SEGDIO0/WPULSE
TX
V3P3D
V3P3SYS
XIN
GNDD
VBAT
ICE_E
OPT_TX/SEGDIO51
VBAT_RTC
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
VDD
TMUXOUT/SEG47
SEGDIO45
V3P3A
GNDA
VA
PB
VLCD
TEST
XOUT
IAP
IAN
RESET
TMUX2OUT/SEG46
SEGDIO44
SPI_CKI/SEGDIO39
VREF
IBP
IBN
Figure 50: Pi nout for the 71M6541D/F/G (LQFP-64 Package)
71M6541D/F/G and 71M6542F/G Dat a S heet
6.8.2 71M6542F/G LQFP-10 0 Pa ckage Pinout
1
Teridian
71M6542F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
92
93
94
95
96
97
98
99
10026
27
28
29
30
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SEGDIO17
TMUXOUT/SEG47
SPI_DI/SEGDIO38
TX
V3P3D
SEGDIO1/VPULSE
SEGDIO3/SDATA
SPI_CSZ/SEGDIO36
V3P3SYS
COM1
COM2
COM3
COM0
SEGDIO45
NC
XIN
GNDD
VBAT
ICE_E
SEGDIO52
OPT_TX/SEGDIO51
VA
V3P3A
GNDA
NC
PB
VLCD
TEST
OPT_RX/SEGDIO55
XOUT
IAP
IBN
IAN
IBP
SEGDIO27/COM4
SPI_DO/SEGDIO37
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
SEGDIO35
SEGDIO33
SEGDIO32
SEGDIO30
SEGDIO29
SEGDIO31
SEGDIO28
SEGDIO34
SEGDIO18
GNDA
VBAT_RTC
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
SEGDIO53
RESET
TMUX2OUT/SEG46
SEGDIO44
SEGDIO43
SEGDIO42
SEGDIO41
SEGDIO40
SPI_CKI/SEGDIO39
SEGDIO16
SEGDIO15
SEGDIO14
SEGDIO13
SEGDIO10
SEGDIO11
SEGDIO12
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
SEGDIO4
SEGDIO2/SDCK
SEGDIO0/WPULSE
SEGDIO54
VREF
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
VB
NC
NC
NC
NC
Figure 51: Pinout for the 71M6542F/G (LQFP-100 Package)
71M6541D/F/G and 71M6542F/G Dat a S heet
6.9 Pin Descriptions
6.9.1 Power a nd Ground Pins
Pi n types: P = P ower, O = Output , I = Input, I/ O = Input/Output.
The cir c uit number denotes the equivalent circuit, as spec ifi ed under 6.9.4 I/O Equiv alent Circuits.
.
Table 119: Power an d Gr oun d Pins
Pin
(64 pin)
Pin
(100-pin)
Name Type Circuit Description
50 72, 80 GNDA P –
Analog ground: This pin should be connected directly to
the ground plane.
42 62 GNDD P –
Digital ground: This pin should be connected directly to
the ground plane.
53 85 V3P3A P –
Anal og power supply: A 3.3 V power supply should be
connect ed to this pi n. V3P 3A must be the same
v oltage as V3P3SYS.
45 69 V3P3SYS P –
System 3.3 V supply. This pin should be connected to a
3.3 V power supply.
41 61 V3P3D O 13
Auxiliary voltage output of the chip. In miss ion mode,
this pin is connected to V 3P 3S Y S by the i nternal
selection sw itch. In BRN mode, it is interna lly
connect ed to VBAT. V3P3D i s floating in LCD and
sleep mode. A 0.1 µF bypass capac itor to ground
m ust be c onnec ted to t his pin.
40 60 VDD O –
The out put of the 2.5V regulat or . Thi s pi n is powered
in MSN and BRN m odes. A 0.1 µF bypass capac itor to
ground should be connected to this pin.
57 89 VLCD O –
The out put of the LCD DAC. A 0. 1 µF bypass
capacitor to ground shoul d be c onnec ted to this pin.
46 70 VBAT P 12
Battery backup pin to support the battery modes (BRN,
LCD). A battery or super-capac itor is to be connected
between VB A T and G NDD. If no batt er y is used,
connect VBAT to V3P3SYS.
47 71 VBAT_RTC P 12
RTC and osci llat or power suppl y . A batt er y or super-
capacitor is to be connect ed between VBAT and
GNDD. If no battery is used, c onnect VBAT_RTC to
V3P3SYS.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.9.2 Analog Pins
Table 120: Analog Pins
Pin
(64 pin)
Pin
(100-pin)
Name Type Circuit Description
55
54
44
43
87
86
68
67
IAP-
IAN
IBP-
IBN
I 6
Differ ential or si ngle-ended Line Current Sense Inputs:
These pins are volt age inputs to the internal A/D
converter. Typically, they are connected to the outputs
of cur r ent sensors. Unused pins must be tied to
V3P3A.
Pins IBP-IBN may be configured for communic ati on with
the remote sensor interface (71M6 x01). When RMT_E =
1 (I/O RAM 0x2709[3]) , the IBP-IBN pins become
balanc ed differ ential pai r . If unuse d, RMT_E must be
zero and IBP-IBN must tied to V3P3A.
52
-- 82
83 VA
VB† I 6
Line V oltage Sense Input s: These pins are voltage
inputs to the internal A/ D converter . Typic all y , th ey are
c onnec ted to the outputs of resistor div ider s. Unused
pins must be tied to V3P3A.
56 88 VREF O 9
Vol tage Refer enc e for the ADC. Thi s pi n should be l eft
unconnect ed ( fl oating).
48
49 75
76 XIN
XOUT I
O 8
Crystal Inputs: A 32 kHz crystal should be connec ted
across these pi ns. Typically, a 15 pF capacitor is also
connected from XIN to GNDA and a
10 pF capacitor i s connected from XOUT t o GNDA. It
is impo r tant to minimize the capacitance between these
pins. See the crystal manufacturer data sheet for det ails.
If an exter nal c lock is used, a 150 m V ( p-p) clock signal
sho uld be appl ied to XIN, and XOUT should be left
unconnected.
† Pi n VB only av ailable on 71M6542F/G.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.9.3 Digita l Pins
Table 121 lists the digital pins. Pin types: P = Power, O = Output, I = Input, I/ O = Input/ Output, N/C = no
connect . The circuit number denotes the equivalent circuit, as specif ied in 6.9.4 I/O Equiv alent Circuits.
Table 121: D igi tal P ins
Pin
(64-pin)
Pin
(100-pin)
Name Type Circuit Function
4-7 12–15 COM0–COM3 O 5
LCD Common Output s. These four pins provide the select
signal s for the LCD display .
31 45 SEGDIO0/WPULSE
I/O 3, 4, 5
Multiple-Use Pi ns. Confi gur able as ei ther LCD segment
driver or DIO. Alt er native f unctions wi th proper sel ec tion of
associated I/O RAM register s are:
SEGDIO0 = WPULSE
SEGDIO1 = VPULSE
SEGDIO2 = SDCK
SEGDIO3 = SDATA
SEGDIO6 = XPULSE
SEGDIO7 = YPULSE
SEGDIO8 = DI
Unused pins must be configured as outputs or
terminated to V3P3/GNDD.
30 44 SEGDIO1/VPULSE
29 43 SEGDIO2/SDCK
28 42 SEGDIO3/SDATA
27 41 SEGDIO4
26 39 SEGDIO5
25 38
SEGDIO6/XPULSE
24 37 SEGDIO7/YPULSE
23 36 SEGDIO8/DI
22-17 35–30 SEGDIO[9:14]
-- 29-27 SEGDIO[15:17]
-- 25 SEGDIO[18]
16-10 24–18 SEGDIO[19:25]
-- 11–4 SEGDIO[28:35]
63-62 95-94 SEGDIO[44:45]
-- 99–96 SEGDIO[40:43]
-- 52 SEGDIO52
-- 51 SEGDIO53
-- 47 SEGDIO54
9 17 SEGDIO26/COM5 I/O 3, 4, 5
Multiple-Use Pi ns. Confi gur able as ei ther LCD segment
driver or DIO with alternative f unc tion (LCD common
drivers).
8 16 SEGDIO27/COM4
3
3
SPI_CSZ/SEGDIO36
I/O 3, 4, 5 Multiple-Use Pins. Configurable as either LCD segment
driver or DIO with alternative f unc tion (SPI interface).
2
2
SPI_DO/SEGDIO37
1
1
SPI_DI/SEGDIO38
64
100
SPI_CKI/SEGDIO39
33
53
OPT_TX/SEGDIO51
I/O 3, 4, 5 Multiple-Use Pins, confi gur able as either LCD segm ent
driver or DIO with alternative f unc tion (optic al por t/ UA RT1)
32
46
OPT_RX/SEGDIO55
38
58
E_RXTX/SEG48
I/O 1, 4, 5 Multiuse Pins. Conf igurable as either emulator port pins
(when ICE_E pull ed high) or LCD segment drivers (when
ICE_E tied to GND).
36
56
E_RST/SEG50
37
57
E_TCLK/SEG49
O
4, 5
71M6541D/F/G and 71M6542F/G Dat a S heet
Pin
(64-pin)
Pin
(100-pin)
Name Type Circuit Function
39 59 ICE_E I 2
ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX
become SEG50, SEG49, and SEG48 respectively. For
production units, this pin should be pulled to GND to disable
the emulator por t.
60
92
TMUXOUT/SEG47
O 4, 5 Multiple-Use Pins. Conf igurable as either multiplexer/clock
output or LCD segment driver usi ng the I/O RAM registers.
61
93
TMUX2OUT/SEG46
59 91 RESET I 2
Chip Reset. This input pi n is used to reset t he c hip into a
known state. For nor ma l oper ation, th is p in is pu lled low. To
reset the chip, t his pi n shoul d be pulled high. This pin has
an internal 30 μA (nominal) current source pulldown. No
ex ternal reset ci r c uitry is necessary.
35 55 RX I 3
UART0 Input. If t his pi n is unused it m us t be ter m i nated
to V 3P 3D or GNDD.
34
54
TX
O
4
UART0 Output
51 81 TEST I 7
Enables Production Test. This pin must be grounded in
no rmal operat ion.
58 90 PB I 3
Pushbutton Input. This pin must be at GNDD when not active
or unused. A ri si ng edge sets the WF_PB flag. It also
causes the part to wake up if it is in S LP or LCD mode. PB
does not have an inter nal pullup or pulldow n resistor.
--
26, 40,
48, 49,
50, 63,
64, 65,
66, 73,
74, 77,
78, 79,
84
NC N/C — No Connection. Do not connect this pin.
71M6541D/F/G and 71M6542F/G Dat a S heet
6.9.4 I/ O Equivale nt Circuits
Figure 52: I/O Equivalent Circuits
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
GNDD
110K
V3P3D
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
GNDD
110K
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
CMOS
Output
GNDD
V3P3D
GNDD
V3P3D
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
Digital
Output
Pin
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
LCD
Driver
GNDD
LCD SEG
Output
Pin
To
MUX
GNDA
V3P3A
Analog Input Equivalent Circuit
Typ e 6:
ADC Input
Analog
Input
Pin
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
GNDA
V3P3A
To
Comparator
Comparator
Input
Pin
To
Oscillator
GNDD
Oscillator
Pin
VREF Equivalent Circuit
Type 9:
VREF
from
internal
reference
GNDA
V3P3A
VREF
Pin
V2P5 Equi valent Circuit
Type 10:
V2P5
from
internal
reference
GNDD
V3P3D
V2P5
Pin
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
LCD
Drivers
VLCD
Pin
VBAT Equivalent Circuit
Type 12:
VBAT Power
GNDD
Power
Down
Circuits
VBAT
Pin
V3P3D E quival ent Cir cuit
Type 13:
V3P3D
from
V3P3SYS
V3P3D
Pin
from
VBAT
10
40
71M6541D/F/G and 71M6542F/G Dat a S heet
7 Ordering Information
7.1 71M6541D/F/G and 71M6542F/G
Table 122. Order ing Infor m a tion
Part Part Descript io n
(Package, Accuracy) Flash
Size Packaging O rder Number Package
Marking
71M6541D 64-pin LQFP Lead-Free, 0.5% 32 KB
bulk
71M6541D-IGT/F 71M6541D-IGT
71M6541D 64-pin LQFP Lead-Free, 0.5% 32 KB
tape and
reel
71M6541D-IGTR/F 71M6541D-IGT
71M6541F
64-pin LQFP Lead-Free, 0.5%
64 KB
bulk
71M6541F-IGT/F
71M6541F-IGT
71M6541F 64-pin LQFP Lead-Free, 0.5% 64 K B tape and
reel
71M6541F-IGTR/F 71M6541F-IGT
71M6541G* 64-pin LQFP Lead-Free, 0.5% 128 K B
bulk
71M6541G-IGT/F 71M6541G-IGT
71M6541G* 64-pin LQFP Lead-Free, 0.5% 128 K B
tape and
reel
71M6541G-IGTR/F 71M6541G-IGT
71M6542F
100-pin LQFP Lead-Free, 0.5%
64 KB
bulk
71M6542F-IGT/F
71M6542F-IGT
71M6542F 100-pin LQFP Lead-Free, 0.5% 64 KB tape and
reel
71M6542F-IGTR/F 71M6542F-IGT
71M6542G
100-pin LQFP Lead-Free, 0.5%
128 KB
bulk
71M6542G-IGT/F
71M6542G-IGT
71M6542G 100-pin LQFP Lead-Free, 0.5% 128 KB
tape and
reel
71M6542G-IGTR/F 71M6542G-IGT
*Futur e pr oduc t—cont act factory for availability.
8 Related Information
Users need these addit ional documents related to the 71M6541D/F/G and 71M6542F/G:
• 71M6541D/F/G and 71M6542F/G Data Sheet (t his document)
• 71M6xxx Data S heet
• 71M6541 Demo Board Us er ’s M anual
• 71M654x Software User’s Guide
9 Con ta ct In for m a tio n
For more information about Maxim products or to check the availability of t he 71M6541D/F/G and
71M6542F/G, contact tec hnic al support at www.maxim-ic.com/support.
71M6541D/F/G and 71M6542F/G Dat a S heet
App en dix A: Acronyms
AFE Anal og Front End
AMR Autom atic Meter Reading
ANSI American National Standards Institut e
CE Compute Engine
DIO Digital I /O
DSP Digital Si gnal Processor
FIR Finite Impulse Response
I2C Inter-IC Bu s
ICE In-Circuit Em ulator
IEC Int er nati onal El ectr otechnical Commission
MPU Mi c r opr oc essor Unit (CPU)
PLL Phase-loc k ed loop
RMS Root M ean S quar e
SFR Speci al Function Register
SOC System on Chip
SPI Serial Peripheral Interfa ce
TOU Ti me of Use
UART Universal Asynchr onous Receiver/Transmitter
71M6541D/F/G and 71M6542F/G Dat a S heet
Appendix B: Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
1.0
3/11
Initial release
—
1.1 4/11
Remo ved the inf ormati on about 18mW typ consum ption at 3.3V
in sleep mode from the Features section
1
Updated t he Temperature Measurement Equation and
Temper ature Er r or parameters in Table 99
141
2 11/11
Promoted 71M6542G to produc tion l ev el (Table 122)
Added refer enc es to 71M 6541G/2G throughout the docum ent,
as appropriate.
Added missing data sheet title header to odd and even pages.
Corrected errata detected si nc e the previous v1.1 (see
indic ated pages changed).
Added section 6.7 on page 155.
1, 9, 10, 27,
49, 54, 56,
62, 97, 120
71M6541D/F/G and 71M6542F/G Dat a S heet
166 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2011 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.