AM79C972BVI\W - AMD - Product.Network

Publication# 21485 Rev: EAmendment/0

Issue Date: March 2009

Refer to AMD’s Website (www.amd.com) for the latest inform ation.

Am79C972

PCnet™-FAST+

Enhanced 10/100 Mbps PCI Ethernet Controller with OnNo w Support

DISTINCTIVE CHARACTERISTICS

nIntegrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus

—32-bit gluele ss PCI hos t interf ace

—Supports PCI c lock frequenc y from DC to

33 MHz independent of network clock

—Supports network operation with PCI clock

from 15 MHz to 33 MHz

—High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

—PCI specification revision 2.1 compliant

—Supports PCI Subsystem/Subvendor ID/

V endor ID pro gramming through the

EEPROM interface

—Supports both PCI 3.3-V and 5.0-V signaling

environments

—Plug and Play compatible

—Supports an unlimited PCI burst length

—Big endian and little endian byte alignments

supported

—Implements optional PCI power management

event (PME) pin

nMedia Independent Interface (MII) for

connecting e xternal 10/100 megabit per second

(Mbps) transceivers

—IEEE 802.3-compliant MII

—Intelligent Auto-Poll™ external PHY status

monitor and interrupt

—Supports both auto-negotiab le and non

auto-negotiable external PHYs

—Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3-

compliant MII PHYs at full- or half-duplex

nSupports General Purpose Serial Interface

(GPSI) with receive frame tagging support for

internetworking applications

nFull-duplex operation supported in MII and GPSI

ports with independent Transmit (TX) and

Receive (RX) channels

nSupports PC97, PC98, and Net PC requirements

—Implements full OnNow features including

pattern matching and link status wake-up

—Implements Magic Packet mode

—Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock

—Supports PCI Bus Power Management

Interface Specification Version 1.0

—Supports Advanced Configuration and

Power Interface (ACPI) Specification

Version 1.0

—Supports Network Device Class Power

Management Specification Version 1.0

nLarge independent internal TX and RX FIFOs

—Programmable FIFO watermarks for both

transmit and receive operations

—Receive frame queuing for high latency PCI

bus host operation

—Programmable allocation of buffer space

between transmit and receive queues

nDual-speed CSMA/CD (10 Mbps a nd 100 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 and Blue Book Ethernet

standards

nEEPROM interface supports jumperless design

and provides through-chip programming

—Supports full programmability of half-/full-

duplex operation for external 10/100 Mbps

PHYs through EEPROM mapping

—Pr ogrammable PHY reset output pin c apable

of resetting external PHY without ne eding

buffering

nIntegrated oscillator circuit eliminates need for

external crystal

nExtensive programmable LED status support

nSupport for operation in industrial temperature

range (- 40 °C to +85°C)

2 Am79C972

nSupports up to 1 megaby te (Mbyte) optional

Boot PROM or Flash for diskless node

application

nLook-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead

by allowing protocol analysis to begin before

the end of a receive frame

nProgrammable Inter Packet Gap (IPG) to

address less network aggressive MAC

controllers

nOffers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

nIEEE 1149.1-c ompliant JTAG Boundary Scan

test access port interface and NAND tree test

mode f or board-level production connectivity

test

nSoftware compatible with AMD PCnet Family

and LANCE/C-LANCE register and descriptor

architecture

nCompatible with the existing PCnet Family

driver and diagnostic software

nAvailab le in 160-pin PQFP and 176-pin TQFP

packages

n+3.3 V power supply with 5 V tolerant I/Os

enables broad system compatibility

nExtensive programmable internal/external

loopback capabilities

nSupports patented External Address Detection

Interface (EADI)

GENERAL DESCRIPTION

The Am79C972 PCnet-FAST+ controller is a highly-

integrated 32-bit full-duplex, 10/100-Megabit per sec-

ond (Mbps) Ethernet controller solution, designed to

address high-perfor mance sys tem applicat ion requir e-

ments. It is a flexible bus ma stering device that can be

used in any application, including network-ready PCs

and bridge/router designs. The bus master architecture

provides high data throughput and low CPU and sys-

tem bus utilization. The Am79C972 controller is fabri-

cated with advanced low-power 3.3-V CMOS process

to provide low operating current for power sensitive ap-

plications.

The Am79C9 72 PCne t-FAST+ controller also has sev-

eral enhancements over its predecessor, the

Am79C971 PCnet-FAST de vice. In addition to integrat-

ing the SRAM on chip, it further reduces system imple-

mentation cost by the addition of a new EEPROM

programmable pin (PHY_RST), an internal oscillator

circuit e li mi nating the need for an extern al c ry s tal, an d

the integration of the PAL function needed for Magic

Packet applicati on. T he P HY_RST pin i s im plemente d

to reset the external PHY without increasing the load to

the PCI bus and to block RST to the PHY when PG

input is LO W.

The 32-bit multiplexed bus interface unit provides a di-

rect interface to the PCI local bus, simplifying the

design of an Ethernet node in a PC system. The

Am79C972 PCnet-FAST+ controller provides the com-

plete interface to an Expansion ROM or Flash device

allowing add-on card designs with only a single load

per PCI bus interface pin. With its built-in support for

both little and big endian byte alignment, this controller

also addresses non-PC applications. The Am79C972

controller’s advanc ed CMOS design al lows the bus in-

terface to be connected to either a +5-V or a +3.3-V sig-

naling environment. A compliant IEEE 1149.1 JTAG

test interf ace f or board-lev el testing is also provided, as

well as a NAND tree test structure for those systems

that cannot support the JTAG interface.

The Am79C972 PCnet-FAST+ controller is also com-

pliant with the PC97, PC98, and Net PC specifications.

It includes the full implementation of the Microsoft

OnNow and ACPI specifications, which are backward

compatible with the Magic Packet technology, and is

complia nt with the PCI Bus Power Management Inter -

face Specification by supporting the four power man-

agement states (D0, D1, D2, and D3), the optional

PME pin, and the necessary configuration and data

registers.

The Am79C972 PCnet-FAST+ controller is ideally

suited for Network PC (Net PC), motherboard, network

interface card (NIC), and embedded designs. It is av ail-

able in a 160-pin Plastic Quad Flat P ac k (PQFP) pack-

age and also in a 176-pin Thin Quad Flat Pac k (TQFP)

package for form factor sensitive designs.

The Am79C972 PCnet-FAST+ controller is a complete

Ether net node integrated into a single VLSI device. It

contains a bus interface unit, a Di rect M emor y Acce ss

(DMA) Buffer Management Unit, an ISO/IEC 8802-3

(IEEE 802.3)-compliant Media Access Controller

(MAC), a large Transmit FIFO and a large Receive

FIFO, and an IEEE 802.3-compliant MII. Both IEEE

802.3 comp liant full- duplex and half- dupl ex operations

are supp or ted on the MII a nd GPSI inter fac es. 1 0/100

Mbps operation is supported through the MII.

The Am79C972 PCnet-FAST+ controller is register

compatible with the LANCE™ (Am7990) and C-

LANCE™ (Am79C90) Ethernet controllers, and all

Ethernet controllers in the PCnet Family except

ILACC™ (Am79C900), including the PCnet-ISA™ con-

troller (Am79C960), PCnet-ISA+™ (Am79C961),

Am79C972 3

PCnet-ISA II™ (Am79C961A), PCnet-32™

(Am79C965), PCnet-PCI™ (Am79C970),

PCnet-PCI II™ (Am79C970A), and the PCnet-FAST™

(Am79C971). The Buffer Management Unit supports

the LANCE and PCnet descriptor software models.

The Am79C972 PCnet-FAST+ controller supports

auto-configuration in the PCI configuration space.

Additional Am79C972 controller configuration parame-

ters, including the unique IEEE physical address, can

be read from an external nonvolatile memory

(EEPROM) immediately following system reset.

In addition, the device provides programmable on-chi p

LED drivers for transmit, receive, collision, link integrity,

Magic Packet status, activity, address match, full-du-

plex, or 100 Mbps status. The Am79C972 controller

also provides an EADI to allow exter nal hardware a d-

dress fi lte r ing in intern e twor k ing applica tio ns and a r e-

ceive frame tagging feature.

The Am79C972 PCnet-FAST+ controller contains

12-kilobyte (Kbyte) buffers, the largest of its class of 10/

100 Mbps Ethernet controllers. The large internal

buffer is p rogrammable be tween th e tra nsm it (TX ) an d

receive (RX) queues for optimal performance.

With the rise of embedded networking applications op-

erating in harsh environments where temperatures

may exceed the normal commercial temperature win-

dow (0°C to 70°C), an industrial temperature (-40°C to

+85°C) version is available in both the 160-pin PQFP

and the 176-pin TQFP package. The Am79C972

PCnet-FAST+ 10/100 Mbps Ethernet controller can be

designed with the industrial temperature capable

Am79C874 NetPHY-1LP 10/100 Mbps Ethernet PHY

for a complete and robust Fast Ethernet solution that

can withstand extreme temperature environments.

4 Am79C972

BLOCK DIAGRAM

CLK

RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT

PERR

SERR

INTA

PCI Bus

Interface

Unit

Buffer

Management

Unit

Expansion Bus

Interface

Bus

Rcv

FIFO

Bus

Xmt

FIFO

Control Network

Port

Manager

MAC

Rcv

FIFO

12K

SRAM

MAC

Xmt

FIFO

JTAG

Port

Control

OnNow

Power

Management

Unit

802.3

MAC

Core

GPSI

Port

MII

Port

EADI

Port

93C46

EEPROM

Interface

LED

Control

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EROMCS

AS_EBOE

EBWE

EBCLK

TXEN

TXCLK

TXDAT

RXEN

RXCLK

RXDAT

CLSN

TBC_IN

TBC_EN

EECS

EESK

EEDI

EEDO

LED0

LED1

LED2

LED3

PME

RWU

WUMI PG

TCK

TMS

TDI

TDO

PHY_RST

TX_ER

TXD[3:0]

TX_EN

TX_CLK

COL

RXD[3:0]

RX_ER

RX_CLK

RX_DV

CRS

MDC

MDIO

SRDCLK

SRD

SFBD

EAR

MIIRXFRTGD/RXFRTG

MIIRXFRTGE/RXFRTGE

21485C-1

Am79C972 5
TABLE OF CONTENTS
AM79C972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DISTINCTIVE CHARACTERISTICS1
GENERAL DESCRIPTION2 BLOCK DIAGRAM4
TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
RELATED AMD PRODUCTS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CONNECTION DIAGRAM (PQR160)8 CONNECTION DIAGRAM (PQL176)9
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PIN DESIGNATIONS (PQL176)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Board Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
EEPROM Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
General Purpose Serial Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3
External Address Detection Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BASIC FUNCTIONS26
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DETAILED FUNCTIONS27
Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Master Bus Interface Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
General Purpose Serial Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5
Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
External Address Detection Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
EEPROM Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Magic P acket Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
NAND Tree Testing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

6 Am79C972

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

RAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Am79C972 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

DC CHARACTERISTICS OVER

COMMERCIAL AND INDUSTRIAL OPERATING RANGES 190

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . .194

SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . .195

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . .196

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .204

SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .206

SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. . . . . . . . . . . . . .207

SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PQR160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Plastic Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Thin Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

LAPP Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Control Register (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Auto-Negotiation Link Partner Ability Register (Register 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Am79C972 7

RELATED AMD PRODUCTS

Part No. Description

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver

Am79C98 Twisted Pair Ethernet Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Am79865 100 Mbps Physical Data Transmitter (PDT)

Am79866A 100 Mbps Physical Data Receiver (PDR)

Am79C871 Quad 100BASE-X Transceiver for Repeater

Am79C940 Media Access Controller for Ethernet (MACE™)

Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support)

Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses)

Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus

Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Ethernet Controller for PCI Local Bus

8 Am79C972

CONNECTION DIAGRAM (PQR160)

Pin 1 is marked for orientation.

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

131

130

129

128

127

126

125

124

123

122

121

132

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

VSSB

EBD6

VSSB

EBD7

EBDA15

EBD5

EEDO/LED3/SRD/MIIRXFRTGD

MDC

RXD0/RXFRTGD

VSS

MDIO

PHY_RST

RX_DV/RXFRTGE

RXD1

RXD2

RX_CLK/RXCLK

RX_ER/RXDAT

TX_ER

TX_CLK/TXCLK

TX_EN/TXEN

TXD0/TXDAT

VDD

TXD1

TXD2

COL/CLSN

VSSB

CRS/RXEN

EBD1

EBD2

VSS

EBD3

VDDB

EBD4

EBD0

TXD3

VDDB

RXD3

VDDB

EBDA14

VSSB

PAR

VDD_PCI

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

VDD_PCI

AD10

AD9

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

C/BE1

FRAME

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AS_EBOE

EBUA_EBA6

AD0

VSS

EROMCS

EBWE

EBCLK

VSSB

EBUA_EBA1

VDD

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5

EBUA_EBA7

VSS

VSSB

EBDA8

EBDA12

VDDB

EBDA10

AD3

AD4

AD2

VDD_PCI

EBUA_EBA0

EBDA9

EBDA13

VSSB

VDDB

AD1

EBDA11

AD30

VSSB

TDI

AD31

VSSB

VDD_PCI

GNT

RST

TDO

INTA

VDDB

TCK

WUMI

PME

VSS

EAR

VSSB

EESK/LED1/SFBD

VDDB

TBC_IN

EEDI/LED0

REQ

AD29

AD28

VSS

AD27

VDD_PCI

AD26

VSSB

C/BE3

AD24

AD25

VDD

RWU

EECS

LED2/SRDCLK/MIIRXFRTGE

TBC_EN

CLK

TMS

PCnet“-FAST+

Am79C972

21485C-2

Am79C972BKC

Am79C972 9

CONNECTION DIAGRAM (PQL176)

Pin 1 is marked for orientation.

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

EROMCS

EBWE

AS_EBOE

EBCLK

EBUA_EBA0

VSSB

EBUA_EBA1

VDD

VDDB

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5

EBUA_EBA6

EBUA_EBA7

VSS

EBDA8

VSSB

EBDA9

EBDA10

VDDB

EBDA11

EBDA12

EBDA13

EEDO/LED3/SRD/MIIRXFRTGD

PHY_RST

MDIO

VSSB

MDC

RXD3

RXD2

VDDB

RXD1

RXD0/RXFRTGD

VSS

RX_DV/RXFRTGE

RX_CLK/RXCLK

RX_ER/RXDAT

VSSB

TX_ER

TX_CLK/TXCLK

TX_EN/TXEN

TXD0/TXDAT

VDDB

VDD

TXD1

TXD2

TXD3

COL/CLSN

VSSB

CRS/RXEN

EBD0

EBD1

EBD2

VSS

EBD3

VDDB

EBD4

EBD5

EBD6

VSSB

EBD7

EBDA15

EBDA14

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

VSS

EAR

EECS

VSSB

EESK/LED1/SFBD

LED2/SRDCLK/MIIRXFRTGE

VDDB

TBC_EN

TBC_IN

EEDI/LED0

PCnet“-FAST+

Am79C972

21485C-3

Am79C972BVC

10 Am79C972

PIN DESIGNATIONS (PQR160)

Listed By Pin Number

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin No. Pin

Name

1IDSEL 41 AD8 81 EBDA14 121 EEDI/LED0

2AD23 42 C/BE0 82 EBDA15 122 TBC_IN

3VSSB 43 VSSB 83 EBD7 123 TBC_EN

4AD22 44 AD7 84 VSSB 124 VDDB

5VDD_PCI 45 VDD_PCI 85 EBD6 125 LED2/SRDCLK/

MIIRXFRTGE

6AD21 46 AD6 86 EBD5 126 EESK/LED1/SFBD

7AD20 47 AD5 87 EBD4 127 VSSB

8VDD 48 VDD 88 VDDB 128 EECS

9AD19 49 AD4 89 EBD3 129 EAR

10 AD18 50 AD3 90 VSS 130 VSS

11 VSSB 51 VSSB 91 EBD2 131 PME

12 AD17 52 AD2 92 EBD1 132 WUMI

13 VDD_PCI 53 VDD_PCI 93 EBD0 133 RWU

14 AD16 54 AD1 94 CRS/RXEN 134 TCK

15 C/BE2 55 AD0 95 VSSB 135 TMS

16 VSS 56 VSS 96 COL/CLSN 136 VDDB

17 FRAME 57 EROMCS 97 TXD3 137 TDO

18 IRDY 58 EBWE 98 TXD2 138 VSSB

19 VSSB 59 AS_EBOE 99 TXD1 139 TDI

20 TRDY 60 EBCLK 100 VDD 140 VDD

21 VDD_PCI 61 EBUA_EBA0 101 VDDB 141 PG

22 DEVSEL 62 VSSB 102 TXD0/TXDAT 142 INTA

23 STOP 63 EBUA_EBA1 103 TX_EN/TXEN 143 RST

24 VDD 64 VDD 104 TX_CLK/TXCLK 144 CLK

25 PERR 65 VDDB 105 TX_ER 145 GNT

26 SERR 66 EBUA_EBA2 106 VSSB 146 REQ

27 VSSB 67 EBUA_EBA3 107 RX_ER/RXDAT 147 VDD_PCI

28 PAR 68 EBUA_EBA4 108 RX_CLK/RXCLK 148 AD31

29 VDD_PCI 69 EBUA_EBA5 109 RX_DV/RXFRTGE 149 VSSB

30 C/BE1 70 EBUA_EBA6 110 VSS 150 VSS

31 AD15 71 EBUA_EBA7 111 RXD0/RXFRTGD 151 AD30

32 VSS 72 VSS 112 RXD1 152 AD29

33 AD14 73 EBDA8 113 VDDB 153 AD28

34 AD13 74 VSSB 114 RXD2 154 AD27

35 VSSB 75 EBDA9 115 RXD3 155 VDD_PCI

36 AD12 76 EBDA10 116 MDC 156 AD26

37 AD11 77 VDDB 117 VSSB 157 VSSB

38 VDD_PCI 78 EBDA11 118 MDIO 158 AD25

39 AD10 79 EBDA12 119 PHY_RST 159 AD24

40 AD9 80 EBDA13 120 EEDO/LED3/SRD/

MIIRXFRTGD 160 C/BE3

Am79C972 11

PIN DESIGNATIONS (PQL176)

Listed By Pin Number

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin No. Pin

Name

1NC 45 NC 89 NC 133 NC

2NC 46 NC 90 NC 134 NC

3IDSEL 47 AD8 91 EBDA14 135 EEDI/LED0

4AD23 48 C/BE0 92 EBDA15 136 TBC_IN

5VSSB 49 VSSB 93 EBD7 137 TBC_EN

6AD22 50 AD7 94 VSSB 138 VDDB

7VDD_PCI 51 VDD_PCI 95 EBD6 139 LED2/SRDCLK/

MIIRXFRTGE

8AD21 52 AD6 96 EBD5 140 EESK/LED1/SFBD

9AD20 53 AD5 97 EBD4 141 VSSB

10 VDD 54 VDD 98 VDDB 142 EECS

11 AD19 55 AD4 99 EBD3 143 EAR

12 AD18 56 AD3 100 VSS 144 VSS

13 VSSB 57 VSSB 101 EBD2 145 PME

14 AD17 58 AD2 102 EBD1 146 WUMI

15 VDD_PCI 59 VDD_PCI 103 EBD0 147 RWU

16 AD16 60 AD1 104 CRS/RXEN 148 TCK

17 C/BE2 61 AD0 105 VSSB 149 TMS

18 VSS 62 VSS 106 COL/CLSN 150 VDDB

19 FRAME 63 EROMCS 107 TXD3 151 TDO

20 IRDY 64 EBWE 108 TXD2 152 VSSB

21 VSSB 65 AS_EBOE 109 TXD1 153 TDI

22 TRDY 66 EBCLK 110 VDD 154 VDD

23 VDD_PCI 67 EBUA_EBA0 111 VDDB 155 PG

24 DEVSEL 68 VSSB 112 TXD0/TXDAT 156 INTA

25 STOP 69 EBUA_EBA1 113 TX_EN/TXEN 157 RST

26 VDD 70 VDD 114 TX_CLK/TXCLK 158 CLK

27 PERR 71 VDDB 115 TX_ER 159 GNT

28 SERR 72 EBUA_EBA2 116 VSSB 160 REQ

29 VSSB 73 EBUA_EBA3 117 RX_ER/RXDAT 161 VDD_PCI

30 PAR 74 EBUA_EBA4 118 RX_CLK/RXCLK 162 AD31

31 VDD_PCI 75 EBUA_EBA5 119 RX_DV/RXFRTGE 163 VSSB

32 C/BE1 76 EBUA_EBA6 120 VSS 164 VSS

33 AD15 77 EBUA_EBA7 121 RXD0/RXFRTGD 165 AD30

34 VSS 78 VSS 122 RXD1 166 AD29

35 AD14 79 EBDA8 123 VDDB 167 AD28

36 AD13 80 VSSB 124 RXD2 168 AD27

37 VSSB 81 EBDA9 125 RXD3 169 VDD_PCI

38 AD12 82 EBDA10 126 MDC 170 AD26

39 AD11 83 VDDB 127 VSSB 171 VSSB

40 VDD_PCI 84 EBDA11 128 MDIO 172 AD25

41 AD10 85 EBDA12 129 PHY_RST 173 AD24

42 AD9 86 EBDA13 130 EEDO/LED3/SRD/

MIIRXFRTGD 174 C/BE3

43 NC 87 NC 131 NC 175 NC

44 NC 88 NC 132 NC 176 NC

12 Am79C972

PIN DESIGNATIONS (PQR160, PQL176)

Listed By Group

Note: 1. Not including test features.

Pin Name Pin Function Type1No. of Pins

PCI Bus Interface

AD[31:0] Ad dress/Data Bus IO 32

C/BE[3:0] Bus Command/Byte Enable IO 4

CLK Bus Clock I 1

DEVSEL Device Sele ct IO 1

FRAME Cycle Frame IO 1

GNT Bus Grant I 1

IDSEL Initialization Device Select I 1

INTA Interrupt O 1

IRDY Initiator Ready IO 1

PAR Parity IO 1

PERR Parity Error IO 1

REQ Bus Request O 1

RST Reset I 1

SERR System Error IO 1

STOP Stop IO 1

TRDY Target Ready IO 1

Board Interface

LED0 LED0 O 1

LED1 LED1 O 1

LED2 LED2 O 1

LED3 LED3 O 1

TBC_IN Test Pin I 1

TBC_EN Test Pin I 1

PHY_RST Reset to PHY O 1

EEPRO M Interface

EECS Serial EEPROM Chip Select O 1

EEDI Serial EEPROM Data In O 1

EEDO Serial EEPROM Data Out I 1

EESK Serial EEPROM Clock IO 1

Expansion ROM Interface

AS_EBOE Addres s Strob e/Ex pan si on Bus Outpu t Enable O 1

EBCLK Expansi on Bus Cloc k I 1

EBD[7:0] Expansion Bus Data [7:0] IO 8

EBDA[15:8] Expansion Bus Data/Address [15:8] IO 8

EBUA_EBA[7:0] Expansion Bus Upper Address /Expansion Bus Address [7:0] O 8

EBWE Expansion Bus Write Enable O 1

EROMCS Expansion Bus ROM C hip Selec t O 1

Am79C972 13

PIN DESIGNATIONS

Listed By Group

Note: 1. Not including test features.

Pin Name Pin Function Type1No. of Pins

Media Independent Interface (MII)

COL Collision I 1

CRS Carrier Sense I 1

MDC Management Data Clock O 1

MDIO Management Data I/O IO 1

RX_CLK Recei ve Clock I 1

RXD[3:0] Receive Data I 4

RX_DV Receive Data V alid I 1

RX_ER Receiv e Error I 1

TX_CLK Tran sm it C lock I 1

TXD[3:0] Transmit Data O 4

TX_EN Tran sm it Data Enable O 1

TX_ER Transm it Error O 1

General Purpose Serial Interface (GPSI)

CLSN Collision I 1

RXCLK Receive Clock I 1

RXDAT Receive Data I 1

RXEN Receive Enabl e I 1

TXCLK Tran sm it Clock I 1

TXDAT Transmit Data O 1

TXEN Transm it Enable O 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I 1

SFBD Start Frame Byte D elim iter O 1

SRD Serial Receive Data O 1

SRDCLK Serial Receive Data Clock O 1

RXFRTGD Receiv e Frame Tag Data I 1

RXFRTGE Receiv e Frame Tag Enabl e I 1

MIIRXFRTGD MII Receiv e Frame Tag Data I 1

MIIRXFRTGE MII Receiv e Frame Tag Enabl e I 1

Power Ma na gemen t Interface

RWU Remote Wake Up O 1

PME Power Manag em ent Event O 1

WUMI Wak e-U p Mo de Indi ca tion O 1

PG Power Good I 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I 1

TDI Test Data In I 1

TDO Test Data Out O 1

TMS Test Mode Select I 1

Power Supplies

VDD Digital Power P 6

VSS Digital Ground P 8

VDDB I/O Buffer Power P 7

VSSB I/O Buffer Ground P17

VDD_PCI PCI I/O Buffer Power P 9

14 Am79C972

Listed By D river Type

The following table des cri bes th e various ty pes of out-

put drivers used in the Am79C972 controller . All IOL and

IOH values shown in the table apply to 3.3 V signaling.

A sustained tri-state signal is a low active signal that is

driv en high for one clock period before it is left floating.

Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50

OMII1 Totem Pole 4-4 50

OMII2 Totem Pole 4-4 390

O6 Totem Pole 6-0.4 50

OD6 Open Drain 6NA 50

STS6 Sustained Tr i-State 6-2 50

TS3 Tri-State 3-2 50

TS6 Tri-State 6-2 50

TSMII Tri-State 4-4 470

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the elements below.

K/V C/D/I

Am79C972B

DEVICE NUMBER/DESCRIPTION

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

D = Commercial Lead Free (0°C to +70°C)

I = Industrial (-40°C to +85°C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQR160)

V = Thin Quad Flat Pack (PQL176)

SPEED OPTION

Not Applicable

Am79C972B

PCnet-FAST+ Enhanced 10/100 Mbps

PCI Ethernet Controller with OnNow Support

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

Valid Combinations

Am79C972B KC/W

VC/W

VD/W

Am79C972B KI/W

VI/W

16 Am79C972

PIN DESCRIPTIONS

PCI I nterface

AD[31:0]

Address and Data Input/Output

Addres s and dat a ar e multi pl exed on t he s am e bus in-

terface pins. During the first clock of a transaction,

AD[31:0] contain a physical address (32 bits). During

the subsequent clocks, AD[31:0] contain data. Byte or-

dering is little endian by def ault. AD[7:0] are defined as

the least significa nt by te (LSB) and AD [31:24] are de-

fined as the most significant byte (MSB). For FIFO data

transfers, the Am79C972 controller can be pro-

grammed f or big endian byte ordering. See CSR3, bit 2

(BSWP) for more de tails.

During the address phase of the transaction, when the

Am79C972 controller is a bus master , AD[31:2] will ad-

dress the active Double Word (DWord). The

Am79C972 controller always drives AD[1:0] to ’00’ dur-

ing the address phase indicating linear burst order.

When the Am79C972 controller is not a bus master, the

AD[31:0] lines are continuously monitored to determine

if an address match exists for slave transfers.

Duri ng the data phase of the tran sac tion, AD[31:0] are

driven by the Am79C972 controller when performing

bus master write and slave read operations. Data on

AD[31:0 ] is la tched by the Am79C972 contr oller when

performing bus master read and slav e write operations.

When RST is active, AD[31:0] are inputs f or NAND tree

testing.

C/BE[3:0]

Bus Command and Byte Enab les Input/Output

Bus command and byte enables are multiplex ed on the

same bus inter face pin s. Du ring the addr ess phase of

the transaction, C/BE[3:0] define the bus command.

During the data phase, C/BE[3: 0] ar e used as b y te en -

ables. The byte enables define which physical byte

lanes carry meaningful data. C/BE0 applies to byte 0

(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The

function o f the byte enables i s ind epe nden t of th e byte

ordering mode (BSWP, CSR3, bit 2).

When RST is active, C/BE[3:0] are inputs for NAND

tree testing.

CLK

Clock Input

This clock is used to drive the system bus interface and

the internal buff er management unit. All bus signals are

sampled on the rising edge of CLK and all parameters

are defi ned with respec t to this edge. The Am79 C972

controller normally operates over a frequency range of

10 to 33 MHz on the PCI bus due to networking de-

mands. See th e Fre quency Deman ds for Network Op-

eration section for details. The Am79C972 controller

will support a clock frequency of 0 MHz after certain

precautions are taken to ensure data integrity. This

clock or a derivation is not used to drive any network

functions.

When RST is active, CLK is an input for NAND tree

testing.

DEVSEL

Device Select Input/Output

The Am79C9 72 controller dr ives DEVS EL when it de-

tects a transaction tha t selects the dev ice as a tar get.

The device samples DEVSEL to detect if a target

claims a transaction that the Am79C972 controller has

initiated.

When RST is activ e, DEVSEL is an input f or NAND tree

testing.

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79C972 controller when it

is the bus master to indicate the beginning and duration

of a transacti on. FRAME is asse r ted to indica te a bus

transaction is beginning. FRAME is asserted while

data transfers continue. FRAME is deasser ted before

the final data phase of a transaction. When the

Am79C972 controller is in slave mode, it samples

FRAME to d eter mine the address phase of a transac-

tion.

When RST is active, FRAME is an input for NAND tree

testing.

GNT

Bus Grant Input

This signal indicates that the access to the bus has

been granted to the Am79C972 controller.

The Am79C972 controller supports bus parking. When

the PCI bus is idle and the system arbiter asserts GNT

without an active REQ from the Am79C972 controller,

the device will drive the AD[31:0], C/BE[3:0] and PAR

lines.

When RST is active, GNT is an input for NAND tree

testing.

IDSEL

Initialization Device Select Input

This sig nal is used as a chi p sele ct for the Am7 9C97 2

control ler duri ng configuration read and w rite tran sac-

tions.

When RST is active, IDSEL i s an input for NAND tree

testing.

Am79C972 17

INTA

Interrupt Request Output

An attention signal which indicates that one or more of

the follo wing status flags is set: EXDINT, IDON, MERR,

MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,

TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE-

INT, and S TINT. Each status flag ha s eith er a ma sk or

an enable bit wh ic h a llows for suppressi on of IN TA as -

sertion. Table 1 shows the flag descriptions. By default

INTA is an open-drain output. For applications that

need a high-active edge-sensitive interr upt signal, the

INTA pin can be configured f or this mode by setting IN-

TLEVEL (BCR2, bit 7) to 1.

When RST is active, I NTA is the output fo r NAND tree

testing.

IRDY

Initiator Ready Input/Output

IRDY indicates the abili ty of the initi ato r of the transac -

tion to compl ete the current data phase. IRDY is used

in conj un ction wi t h TRDY. Wait states are inserted until

both IRDY and TRDY are asser ted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When the A m79C97 2 controll er is a bu s master, i t as-

serts IRDY during all write data phases to indicate that

va lid data is presen t on AD[31:0]. D uring all read data

phases, the device asser ts IRDY to indicate that it is

ready to accept the data.

When the Am79C972 controller is the target of a trans-

action, it checks IRDY during all write data phases to

determine if valid data is present on AD[31:0]. During

all read data phases, the device checks IRDY to deter-

mine if the initiator is ready to accept the data.

When RST is active, IRDY is an input for NAND tree

testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C972 controller is a bus master , it gen-

erates parity during the address and write data phases.

It checks parity during read data phases. When the

Am79C972 controller operates in slave mode, it checks

parity during every address phase. When it is the target

of a cycle, it checks parity during write data phases and

it generates parity during read data phases.

When RST is active, PAR is an input for NAND tree

testing.

PERR

P arity Error Input/Output

During any slave write transaction and any master read

transaction, the Am79C972 controller asserts PERR

when it d etec ts a dat a p arity erro r and repo rting of the

error is enabled by setting PERREN (PCI Command

the Am79 C972 cont roller mo nitors PE RR to see if the

target reports a data parity error.

When RST is active, PERR is an in put for NAND tree

testing.

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT Excessive

Deferral CSR5, bit 6 CSR5, bit 7

IDON Initialization

Done CSR3, bit 8 CSR0, bit 8

MERR Memory Error CSR3, bit 11 CSR0, bit 11

MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO Missed Frame

Count Over-

flow CSR4, bit 8 CSR4, bit 9

MPINT Magic Packet

Interrupt CSR5, bit 3 CSR5, bit 4

RCVCCO Receive

Collision Count

Overflow CSR4, bit 4 CSR4, bit 5

RINT Receive

Interrupt CSR3, bit 10 CSR0, bit 10

SINT System Error CSR5, bit 10 CSR5, bit 11

TINT Transmit

Interrupt CSR3, bit 9 CSR0, bit 9

TXSTRT Transm it Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MII

Management

Command

Complete

Interrupt

CSR7, bit 4 CSR7, bit 5

MPDTINT MII PHY Detect

Transition

Interrupt CSR7, bit 0 CSR7, bit 1

MAPINT MII Auto-Poll

Interrupt CSR7, bit 6 CSR7, bit 7

MREINT

MII

Management

Frame Read

Error Interrupt

CSR7, bit 8 CSR7, bit 9

STINT Software Timer

Interrupt CSR7, bit 10 CSR7, bit 11

18 Am79C972

REQ

Bus Request Input/Output

The Am79C972 controller asserts REQ pin as a signal

that it wish es to become a bus master. REQ is dri ve n

high when the Am79C972 controller doe s not request

the bus. In Power Management mode, the REQ pin will

not be driven.

When RST is active, REQ is an input for NAND tree

testing.

RST

Reset Input

When RST is as ser ted LOW and the PG pin is HIG H,

then the Am79C972 controller performs an internal

system reset of the type H_RESET

(HARDWARE_RESET, see section on RESET). RST

must be held for a minimum of 30 clock periods. While

in the H_RESET state, the Am79C972 controller will

disable or deassert all outputs. RST may be as ynch ro -

nous to clock when asserted or deasserted.

When the PG pi n is LOW, RST dis able s all of the PCI

pins except the PME pin.

When RST is LOW and PG is HIGH, NAND tree testing

is enabled.

SERR

System Error Output

During any slav e transaction, the Am79C972 controller

asserts SERR wh en it detects a n add re ss p arity er ror,

and repor ting of the error is enabled by setting PER-

REN (PCI Command register , bit 6) and SERREN (PCI

Command register, bit 8) to 1.

By default SERR is an open-d rain output. For compo-

nent test, it can be programmed to be an active-high

totem-pole output.

When RST is a cti ve, SERR is an input for NAND tree

testing.

STOP

Stop Input/Output

In slave mode, the Am79C972 controller drives the

STOP signal to infor m the bus master to sto p the cur-

rent transaction. In bus master mode, the Am79C972

controller checks ST OP to determine if the target wants

to disconnect the current transaction.

When RST is active, STOP is an input for NAND tree

testing.

TRDY

Target Ready Input/Output

TRDY indicates the abi lity of the target of the transac-

tion to complete the current data phase. Wait states are

inserted until both IRDY and TRDY are asserted simul-

taneously. A data phase is completed on any clock

when both IRDY and TRDY are asserted.

When the Am79C972 controller is a bus master, it

checks TRDY during all read data phases to determine

if valid data is present on AD[31:0]. During all write data

phases, the device checks TRDY to determine if the

target is ready to accept the data.

When the Am79C972 controller is the target of a trans-

action, it as se r ts TRDY dur ing a ll read da ta phases to

indicat e that valid data is present on AD[31 :0]. Durin g

all wr it e data phas es, the device asserts TR DY to indi-

cate that it is ready to accept the data.

When RST is active, TRDY is an input for NAND tree

testing.

PME

Power Management Event Output, Open Drain

PME is an output that can be used to indicate that a

power management ev ent (a Magic Pac ket, an OnNow

patter n match , or a change in li nk state) has bee n de-

tected. The PME pin is asserted when either

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1.

The PME signal is asynchronous with respect to the

PCI clock.

Board Interface

Note: Before programming the LED pins, see the

description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By de-

fault, LED0 indicates an active link connection. This pin

can also be programmed to indicate other network sta-

tus (see BCR 4). The LED0 pin polar ity is programma-

ble, but by default it is active LOW. When the LED0 pin

polarity is programmed to active LOW, the output is an

open drain driver. When the LED0 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED. By de-

fault, LED1 indicates receive activity on the network.

This pin can also be programmed to indicate other net-

work statu s (see BC R5). The LE D1 p in pola r ity is pro-

grammable, but by default, it is a ctive LOW. W hen the

LED1 pin polarity is programmed to active LOW, the

output is an ope n drain dri ver. When the LED1 pi n po-

Am79C972 19

larity is programmed to active HIGH, the output is a

totem pole driver.

Note: The LED1 pin is multiplex ed with the EESK and

SFBD pins.

The LED1 pin is also used during EEPROM Auto-

Detection to deter mine whe ther or not a n EEPROM is

present at the Am79C972 controller interface. At the

last rising edge of CLK while RST is active LOW, LED1

is sam pled to determi ne the value of the EEDE T bit i n

BCR19. It is i mportant to mai ntain adequ ate hol d tim e

around the rising edge of the CLK at this time to ensure

a correctly sampled value. A sampled HIGH value

means that an EEPROM is present, and EEDET will be

set to 1. A sampled LOW value means that an EE-

PROM is not present, and EEDET will be set to 0. See

the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead in

order to resolve the EEDET setting.

WARNING: The input signal level of LED 1 mus t b e

insured for correct EEPROM detection before the

deassertion of RST.

LED2

LED2 Output

This output is designed to directly drive an LED. This

pin can be programmed to indicate various network

status ( see BCR6) . The L ED2 pin pol arity is program-

mable, but by default it is ac tive LOW. When the LED 2

pin polarity is programmed to active LOW, the output is

an open drain driver. When the LED2 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED2 pin is multiplexed with the SRDCLK

pin and the MIIRXFRTGE pins.

LED3

LED3 Output

This output is designed to directly drive an LED. By de-

fault, LED3 indicates transmit activity on the network.

This pin can also be programmed to indicate other net-

work status (see BC R7). The LE D3 p in pola r ity is pro-

grammable, but by default it is act ive LOW. When the

LED3 pin polarity is programmed to active LOW, the

output is a n o pen drain dr i ver. Wh en the LE D3 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Special attention must be given to the external circuitry

attached to this pin. When this pin is used to dr ive an

LED while an EEPROM is used in the system, then

buffering maybe required between the LED3 pin and

the LED circuit. If an LED circuit were directly attached

to this pin , it may create an IOL re qui r eme nt tha t co ul d

not be met by the serial EEPROM attached to this pin.

If no EEP ROM is i nclud ed i n t he s y st em d es ign or low

current LEDs are used, then the LED3 signal may be

directly connected to an LED without buffering. For

more details regarding LED connection, see the sec-

tion on LED Support.

Note: The LED3 pin is multiplexed with the EEDO,

SRD, MIIRXFRTGD pins.

Power Good Input

The PG pin has two functions: (1) it puts the device into

Magic Packet™ mode, and (2) it blocks any resets

when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is

set to 1, the device enters the Magic Packet mode.

When PG is LOW, a LO W assertion of the PCI RST pin

will only caus e the PCI inte r face pins (exc ept for PME)

to be put in the high impedance state. The internal logic

will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin

causes the controller logic to be reset and the configu-

ration information to be loaded from the EEPROM.

PG input should be kept high during the NAND tree

testing.

RWU

Remote Wake Up Output

R WU is an output that is asserted either when the con-

troller is in the Magic Pac k et mode and a Magic Pac k et

frame has been detected, or the controller is in the Link

Change Detect mode and a Link Change has been de-

tected.

This pin can drive the external system management

logic that causes the CPU to get out of a low power

mode of operation. This pin is implemented for designs

that do not support the PME function.

Three bits that are loaded from the EEPROM into

CSR116 can program the characteristics of this pin:

1. RWU_POL determines the polarity of the R WU sig-

nal.

2. If RWU_GATE bit is set , RWU i s forc ed to the high

impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is

open drain or to tem pole.

The internal power-on-reset signal forces this output

into the high impedance state until after the polarity and

drive type have been determined.

WUMI

Wake-Up Mode Indicator Output

This outpu t, which is capable of dr iving an LE D, is as-

serted when the device is in Magic Pac ket mode. It can

20 Am79C972

be used to drive external logic that switches the device

power source fro m the main p ower supply to an aux il-

iary power suppl y.

TBC_EN

Time Base Clock Enable Input

TBC_EN is an input that controls the selection of the

source of the Time Base Clock. The Time Base Clock

is used in loading the EEPROM, generation of the

PHY_RST, and the timing of the MDC and MDIO sig-

nals. When the input to this pin is LOW, an internal free

running oscillator with a maximum frequency of 20

MHz is used. When the input to this pin is HIGH, the

TBC_IN pin input is used to inject externally generated

clock into the device. For typical applications which will

use the internal oscillation, this pin should be tied to

ground.

When RST is active, TBC_EN is an input f or NAND tree

testing.

TBC_IN

Time Base Clock Input Input

TBC_IN may be used to connect to an external clock

source to drive the internal circuitry that loads the

EEPROM and controls the MDC and MDIO signals.

This inpu t is select ed when the TBC_E N pin is HIG H.

This pin should be tied to ground when the TBC_EN pin

is LOW.

PHY_RST

PHY Reset Output

PHY_RST is an output pin that is used to reset the ex-

ternal PHY. This output eliminates the need for a fan

out buffer for the PCI RST signa l, provides polar ity for

the specific PHY used, and prevents the resetting of

the PHY when the PG input is LOW. The output polarity

is determined by the RST_POL bit(CSR116, bit0).

EEPROM Interface

EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EE-

PROM that uses the 93C46 EEPROM interface proto-

col. EECS is connected to the EEPROM’s chip select

pin. It is controlled by either th e Am79C972 con troller

during command por tions of a read of the entire EE-

PROM, or indirectly by the host system by writing to

BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. E EDI is connecte d to the EEPROM’s da ta input

pin. It is controlled by either th e Am79C972 con troller

during command portions of a read of the entire

EEPROM, or indirectly by the host system by writing to

BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

EEDO

EEPROM Data Out Input

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EEDO is connected to the EEPROM’s dat a o ut-

put pin. It is controlled by either the Am79C972

controller during command portions of a read of the en-

tire EEPROM, or indirectly by the host system by read-

ing from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3,

MIIRXFRTGD, and SRD pins.

EESK

EEPROM Serial Clock Input/Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EESK is connected to the EEPROM’s cl ock pin.

It is controlled by either the Am79C972 controller di-

rectl y during a re ad of the en tire EEPR OM, or ind irectly

by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplex ed with the LED1 and

SFBD pins.

The EESK pin is also used during EEPROM Auto-

Detect ion to deter min e whether or not an EEPROM is

present at the Am79C972 controller interface. At the

rising edge of the last CLK edge while RST is asserted,

EESK is sampled to determine the value of the EEDET

bit in BCR19. A sampled HIGH value means that an

EEPROM is present, and EEDET will be set to 1. A

sampled LOW value means that an EEPROM is not

present, and EEDET will be set to 0. See the EEPROM

Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead to re-

solve the EEDET setting.

WARNING: The input signal level of EESK must be

valid for correct EEPROM detection before the

deassertion of RST.

Expansion Bus Interface

EBUA_EBA[7:0]

Expansion Bus Upper Address/

Expansion Bus Address [7:0] Output

The EBUA_EBA[7:0] pins provide the least and most

significant bytes of address on the Expansion Bus. The

most significant address byte (address bits [19:16] dur-

ing boo t device access es) is valid on these pins at the

beginning of a boot device access, at the rising edge of

AS_EBOE. This upper address byte must be stored ex-

Am79C972 21

ter nally in a D fli p-flop. Dur ing subseq uent cycles of a

boot device access, address bits [7:0] are present on

these pins.

All EBUA_EBA[7:0] outputs are forced to a constant

lev el to conserve power while no access on the Expan-

sion Bus is being performed.

EBDA[15:8]

Expansion Bus Data/Addres s [15:8] Input/Output

When EROMCS is asserted low, EBDA[15:8] contain

address bits [15:8] for boot device accesses.

The EBDA[15:8] signals are driven to a constant level

to conserve power while no access on the Expansion

Bus is being performed.

EBD[7:0]

Expansion Bus Data [7:0] Input/Output

The EBD[7:0] pins provide data bits [7:0] for EPROM/

FLASH accesses. The EBD[7:0] signals are inte rnally

forced to a constant level to conserve power while no

access on the Expansion Bus is being performed.

EROMCS

Expansion ROM Chip Select Output

EROMCS serves as the chip select for the boot device.

It is asserted low during the data phases of boot device

accesses.

AS_EBOE

Address Strobe/Expansion Bus

Output Enable Output

AS_EBOE functions as the address strobe for the

upper address bits on the EBU A_EBA[7:0] pins and as

the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE is

supplied at the beginning of boot device accesses. This

rising edge provides a clock edge for a ‘374 D-type

edge-triggered flip-flop which must store the upper ad-

dress byte during Expansion Bus accesses for

EPROM/Flash.

AS_EBOE is asser ted active LOW during boot device

read operations on the expansion bus and is deas-

serted during boot device write operations.

EBWE

Expansion Bus Write Enable Output

EBWE p rovides the wr ite e nable for wr ite acc esses to

the Flash device.

EBCLK

Expansion Bus Clock Input

EBCLK may be used as the fundamental clock to drive

the Expan sion Bus and inte rn al SRAM a ccess cycles.

The actual internal clock used to drive the Expansion

Bus cycles depends on the values of the EBCS and

CLK_FAC settings in BCR27. Refer to the SRAM Inter-

face Bandwidth Requirements section for details on de-

termining the required EBCLK frequency. If a clock

source other than the EBCLK pin is programmed

(BC R27 , bi ts 5:3) to be us ed t o run t h e Ex pa n sion Bus

interface, this input should be tied to VDD through a 4.7

kΩ resistor.

EBCLK is not used to drive the bus interface, internal

buffer management unit, or the network functions.

Media Independent Interface

TX_CLK

Transmit Clock Input

TX_CLK is a continuous clock input that provides the

timing reference for the transfer of the TX_EN,

TXD[3:0], and TX_ER signals out of the Am79C972

device. TX_CLK must provide a nibble rate clock (25%

of the network data rate). Hence, an MII transceiver op-

erating at 10 Mbps mus t provide a T X_CL K frequen cy

of 2.5 MHz and an MII transceiver operating at 100

Mbps must provide a TX_CLK frequency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the TXCLK

pin.

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII transmit data bus. Valid

data is generated on TXD[3:0] on every TX_CLK rising

edge while TX_EN is asserted. While TX_EN is de-

asser ted, TXD[3:0] values are dr iven to a 0. TXD[3:0]

transitions synchronous to TX_CLK rising edges.

Note: The TXD[0] pin is multiplexed with the TXD pin.

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C972 device is pre-

senting v alid transmit nibbles on the MII. While TX_EN

is asserted, the Am79C972 device generates TXD[3:0]

and TX_ER on TX_CLK rising edges. TX_EN is as-

serted with the first nibble of preamble and remains as-

serted throughout the duration of a packet until it is

deasserted prior to the fi rst T X_CL K following the fi nal

nibble of the fram e. TX_EN tran si tio ns syn ch ronous t o

TX_CLK rising edges.

Note: The TX_EN pin is multiplexed with the TXEN

pin.

TX_ER

Transmit Error Output

TX_E R is an outpu t tha t, if asserted while TX_EN i s as-

ser ted, ins tructs the MII PHY device connecte d to the

Am79C972 device to transmit a code group error.

TX_ER is unused and is reserved for future use and will

always be driven to a logical zero.

22 Am79C972

COL

Collision Input

COL is an input that indicates that a collision has been

detected on the network medium.

Note: The COL pin is multiplexed with the CLSN pin.

CRS

Carrier Sense Input

CRS is an input tha t indicates that a non -idle med ium,

due eithe r to transmit or recei ve ac tivity, has been d e-

tected.

Note: The CRS pin is multiplexed with the RXEN pin.

RX_CLK

Receive Clock Input

RX_CLK is a c lock input that provides the tim ing refer-

ence for the transfer of the RX_DV, RXD[3:0], and

RX_ER signals into the Am79C972 device. RX_CLK

must provide a nibble rate clock (25% of the network

data rate). Hence, an MII transceiver operating at 10

Mbps must provid e an RX_C LK freq uency of 2 .5 MHz

and an MII transceiver operating at 100 Mbps must pro-

vide an RX_CLK frequency of 25 MHz. When the exter-

nal PHY switches the RX_CLK and TX_CLK, it must

provide glitch-free clock pulses.

Note: The RX_CLK pin is multiplex ed with the RXCLK

pin.

RXD[3:0]

Receive Data Input

RXD[3:0 ] is the nibble-wide MII recei ve data bus. Data

on RXD[3:0] is sampled on every rising edge of

RX_CLK while RX_D V is asserted. RXD[3:0] is ignored

while RX_DV is de-asserted.

Note: The RXD[0] pin is multiplexed with the

RXFRTGD pin.

If the MII port is not select ed, th e RXD[3:0] pin can be

left floating.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate that valid received

data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. In order

for a frame to be fully received by the Am79C9 72 de-

vice on th e MII, RX_DV must be asser ted prior to the

RX_CLK rising edge, when the first nibble of the Start

of Frame Delimiter is driven on RXD[3:0], and must re-

main asserted until after the rising edge of RX_CLK,

when the last nibble of the CRC is driven on RXD[3:0].

RX_DV must th en be dea sserted pri or to the RX _CLK

rising edge which follows this final nibble. RX_DV tran-

sitions are synchronous to RX_CLK rising edges.

Note: The RX_DV pin is multiplexed with the

RXFRTGE pin.

If the MII port is not selected, the RX_D V pin can be left

floating.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII trans-

ceiver device has detected a coding error in the receive

frame currently being transferred on the RXD[3:0] pins.

When RX_E R is asser t ed while RX_DV i s asser ted , a

CRC error will be indicated in the receive descriptor for

the incoming receive frame. RX_ER is ignored while

RX_DV i s d eas serted. S peci al co de group s gen erate d

on RXD while RX_DV is dea sser te d are ignored (e.g .,

Bad SSD in TX and IDLE in T4). RX_ER transitions are

synchronous to RX_CLK rising edges.

Note: The RX_ER pin is multiplexed with the RXDAT

pin.

MDC

Management Data Clock Out put

MDC is a non -continuous c lock ou tput that provides a

timing reference for bits on the MDIO pin. During MII

managemen t port operations, MDC r uns at a nominal

frequency of 2.5 MHz. When no management opera-

tions are in progress, MDC is driven LO W. The MDC is

derived from the Time Base Clock.

If the MII port is not sel ected, the MDC pin can be left

floating.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional MII management port data

pin. MDIO is an output during the header portion of the

managemen t frame transfers and dur ing the dat a por-

tions of write transfers. MDIO is an input during the

data portions of read data transfers. When an operation

is not in progress on the management port, MDIO is not

driv en. M DIO tr ansiti ons fro m the Am79C972 contro ller

are synchronous to MDC falling edges.

If the PHY is attached through an MII physical connec-

tor , then the MDIO pin should be externally pulled down

to VSS with a 10-kΩ ±5% resistor. If the PHY is on

board, then the MDIO pin should be externally pulled

up to VCC with a 10-kΩ ±5% resistor.

Am79C972 23

General Purpose Seri al Inte rface

CLSN

Collision Input

CLSN is an input that indicates a collision has occurred

on the network.

Note: The CLSN pin is multiplexed with the COL pin.

RXCLK

Receive Clock Input

RXCLK is an input. The rising edges of the RXCLK sig-

nal are used to sample the data on the RXDAT input

whenever the RXEN input is HIGH.

Note: The RXCLK pin is multiplex ed with the RX_CLK

pin.

RXDAT

Receive Data Input

RXD AT is an input. The rising edges of the RXCLK sig-

nal are used to sample the data on the RXDAT input

whenever the RXEN input is HIGH.

Note: The RXDAT pin is multiplexed with the RX_ER

pin.

RXEN

Receive Enable Input

RXEN is an input. When this signal is HIGH, it indicates

to the core logi c that the data on the RXDAT input pin

is valid.

Note: The RXEN pin is multiplexed with the CRS pin.

TXCLK

Transmit Clock Input

TXCLK is an input that provides a clock signal for MAC

activi ty, both tra nsmit and r ecei ve. The risi ng ed ges o f

the TXCLK can be used to validate TXDAT output data.

Note: The TXCLK pin is multiplexed with the TX_CLK

pin.

TXDAT

Transmit Data Output

TXDAT i s an output that prov ides the ser ial bit stream

for transmission, including preamble, SFD, data, and

FCS field, if appl ic able.

Note: The TXDAT pin is multiplexed with the TXD[0]

pin.

TXEN

Transmit Enable Output

TXEN is an output that provides an enable signal for

transmission. Data on the TXDAT pin is not valid unless

the TXEN signal is HIGH.

Note: The TXEN pin is multiplexed with the TX_EN

pin.

External Address Detection Interface

EAR

External Address Reject Low Input

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the re-

sult of this check will be OR’d with the value on the EAR

pin. The EAR pin is defined as REJECT. The pin value

is OR’d with the internal address detection result to de-

ter mine i f the curr ent frame sho uld be a ccepted or re-

jected.

The EAR pin must not be left unconnect ed, it should

be tied to VDD through a 10-kΩ ±5% resistor.

When RST is active, EAR is an input for NAND tree

testing.

SFBD

Start Frame-Byte Delimiter Output

For the GPSI port during External Address Detec-

tion:

An initial rising edge on the SFBD signal indicates that

a start of frame delimiter has been detected. The serial

bit stream will follow on the SRD signal, commencing

with the destination address field. SFBD will go high f or

4 bit times (400 ns when operating at 10 Mbps) after

detecting the second “1” in the SFD (Start of F rame De-

limiter) of a received frame. SFBD will subsequently

toggle every 4 bit times (1.25 MHz frequency when op-

erating at 10 Mbps) with each rising edge indicating the

first bit of ea ch subsequen t byte of the r eceive d serial

bit stream.

For the External PHY attached to the Media Inde-

pendent Interface during External Address Detec-

tion:

An initial rising edge on the SFBD signal indicates that

a start of valid data is present on the RXD[3:0] pins.

SFBD will go high f or one nibble time (400 ns when op-

erating at 10 Mbps and 40 ns when operating at 100

Mbps) one RX_ CLK perio d after RX_DV has been as-

ser ted and RX_ER is deasserted a nd the detect ion of

the SFD (Start of F r ame Delimiter) of a received frame.

Data on the RXD[3:0] will be the start of the destination

address field. SFBD will subsequently toggle ev ery nib-

ble time (1.25 MHz frequency when operating at 10

Mbps and 12.5 MHz freq uency when o perating a t 10 0

Mbps) indicating the first nibble of each subsequent

byte of the received nibble stream. The RX_CLK

should be used in conjunction with the SFBD to latch

the correct data for exter nal address matching. SFBD

will be active only during frame reception.

Note: The SFBD pin is multiplex ed with the EESK and

LED1 pins.

24 Am79C972

SRD

Serial Receive Data Input/Output

SRD is the de cod ed NRZ d ata from the network whe n

in GPSI mode. This signal can be used for e xternal ad-

dress dete ction .

Note: When the MII port is selected, SRD will not gen-

erate transitions and receive data must be derived from

the Media Independent Interface RXD[3:0] pins.

Note also that the SRD pin is multiplexed with the

MIIRXFRTGD, EEDO, and LED3 pins.

SRDCLK

Serial Receive Data Clock Output

Serial Receive Data is synchronous with reference to

SRDCLK.

Note: When the MII port is selected, SRDCLK will not

generate transiti ons and the rec eive clock must be de-

rived from the MII RX_CLK pin.

Note also that the SRD CLK pi n is mult iplexed wit h th e

MIIRXFRTGE and LED2 pin s.

RXFRTGD

Receive Frame Tag Data Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), a nd the MII is not selected , the RXFRTGD pin

becomes a data input pin for the Receive Frame Tag.

See the Receive Frame Tagging section for details.

Note: The RXFRTGD pin is multiplexed with the

RXD[0] pin.

RXFRTGE

Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is not selected, the RX FRTGE pin

becomes a data input enable pin for the Receive F rame

Tag. See the Receive Frame Tagging section for de-

tails.

Note: The RXFRTGE pin is multiplexed with the

RX_DV pin.

MIIRXFRTGD

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is selected, the MIIRXFRTGD pin

becomes a data input pin for the Re ceive Frame Tag.

See the Receive Frame Tagging section for details.

Note: The MIIRXFRTGD pin is multiplexed with the

SRD, EEDO, and LED3 pins.

MIIRXFRTGE

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is selected, the MIIRXFRTGE pin

becomes a data input enable pin f or the Receive F rame

Tag. See the Receive Frame Tagging section for de-

tails.

Note: The MIIRXFRTGE pin is multiplexed with the

SRDCLK and LED2 pins.

IEEE 1149. 1 (1990) Test Access Port

Interface

TCK

T est Clock Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull up resistor.

TDI

T est Data In Input

TDI is the test data input path to the Am79C972 con-

troller. The pin has an internal pull up resistor.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C972

controller . The pin is tri-stated when the JTAG port is in-

active.

TMS

Test Mode Select Input

A ser ial inpu t bit stream on the TMS pin is used to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull up resistor.

Am79C972 25

Power Supply Pins

VDDB

I/O Buffer P o wer (7 Pins) Po wer

There are sev en power supply pins that are used by the

input/output buff er drivers. All VDDB pins must be con-

nected to a +3.3 V supply.

VDD_PCI

PCI I/O Buffer Power (9 Pins) Power

There ar e n ine power suppl y pi ns tha t are used by the

PCI input/out put buffer drivers (exce pt PM E dr iver). All

VDD_PCI pins must be connected to a +3.3 V supply.

VSSB

I/O Buffer Ground (17 Pins) P ower

There are 17 ground pins that are used by the input/

output buffe r dr ivers.

VDD

Digital P ower (6 Pins) Power

There are six power supply pins that are used by the in-

ter na l di git al c ircu itry. Al l VDD pins must be co nne cted

to a +3.3 V supply.

VSS

Digital Ground (8 Pins) P o wer

There are ei gh t ground pin s tha t are use d by the inter-

nal digital circuitry.

26 Am79C972

BASIC FUNCTIONS

System Bus Interface

The Am79C9 72 controller is des igned to operate as a

bus master during nor mal operations. Some slave I/O

accesses to the Am79C972 controller are required in

normal operations as well. Initialization of the

Am79C972 controller is achieved through a combina-

tion of PCI Configuration Space accesses, bus slave

access es, bus master acc esses, and an o ptiona l read

of a serial EEPROM that is performed by the

Am79C9 72 con t roll er. The EEPROM read operat ion is

performed through the 93C46 EEPROM interface. The

ISO 880 2- 3 (IE EE /A NSI 80 2.3) Eth ernet Addr ess may

reside within the serial EEPROM. Some Am79C972

controller configuration registers may also be pro-

grammed by the EEPROM read operation.

The Address PROM, on-chip board-configuration reg-

isters, and the Ether net control ler registers occupy 32

bytes of address space. I/O and m emory mapped I/O

accesses are supported. Base Address registers in the

PCI configuration space allow locating the address

space on a wide variety of starting addresses.

For diskless stations, the Am79C972 controller sup-

ports a ROM or Flash-based (both referred to as the

Expansion ROM throughout this specification) boot de-

vice of up to 1 Mbyte in size. The host can map the boot

device to any memory address that aligns to a 1-Mbyte

boundar y by modifyi ng the Expansio n ROM B ase Ad-

dress register in the PCI configuration space.

Softw are Interface

The software interface to the Am79C972 controller is

divided into three parts. One part is the PCI configura-

tion registers used to identify the Am79C972 controller

and to setup the configuration of the device. The setup

information includes the I/O or memory mapped I/O

base address, mapping of the Expansion ROM, and

the routi ng o f the Am7 9C9 72 c ont ro ll er in ter rupt chan-

nel. This allows for a jumperless implementation.

The secon d por tion of the software interface is the d i-

rect access to the I/O resources of the Am79C972 con-

troller. T he Am79C972 controller occupies 32 by tes of

address space that must begin on a 32-byte block

boundary. The addr ess spa ce can be ma pped int o I/O

or memory space (memory mapped I/O). The I/O Base

Addres s Regi ster i n th e P CI Conf iguration S pa ce con-

trols the start address of the address space if it is

mapped to I/ O space. The Memor y Mapped I/O Base

Addres s Registe r controls the start addres s of the ad-

dress spac e if it is map ped to memory space. The 32-

byte address space is used by the software to program

the Am79C972 controller operating mode, to enable

and disa ble various features, to mon itor o peratin g sta-

tus, and to reques t par ticular fun ctions to be executed

by the Am79C972 controller.

The third portion of the software interface is the de-

scriptor and buffer areas that are shared between th e

software and the Am79C972 controller during normal

network operations. The descriptor area boundaries

are set by the soft ware and do n ot change du r ing nor-

mal network operations. There is one descriptor area

for receive activity and there is a separate area for

transmit activity. The descriptor space contains relocat-

able pointers to the network frame data, and it is used

to transfer frame status from the Am79 C972 con troller

to the software. The buff er areas are locations that hold

frame data for transmission or that accept frame data

that has been received.

Network Interfaces

The Am79C972 controller can be connected to an

IEEE 80 2.3 or propr ietar y network v ia one of two net-

work interfaces. The Media Independent Interf ace (MII)

provides an IEEE 802.3-compliant nibble-wide inter-

face to an external 100- and/or 10-Mbps transceiver

device. The General Purpose Serial Interface (GPSI) is

functionally equivalent to the GPSI found on the

LANCE.

While in auto-selection mode, the interface in use is de-

termined by the Network P ort Manager . If the quiescent

state of the MII MDIO pin is HIGH, the MII is activated.

The GPSI por t can only be enabled by disabling the

auto-selection and manually selecting the GPSI as the

network port.

The Am79C972 controller supports both half-duplex

and full-duplex operation on network interfaces (i.e.,

GPSI and MII).

Am79C972 27

DETAILED FUNCTIONS

Slave Bus I nterf ace Unit

The slave b us interface unit (BIU) controls all accesses

to the PCI configura tion space, the Cont rol and Status

Registers (CSR), the Bus Configuration Registers

(BCR), the Address PROM (APROM) locations, and

the Expansion ROM. Table 2 shows the response of

the Am79C972 controller to each of the PCI commands

in slave mode.

Table 2. Slave Commands

Slave Confi guration Transfers

The host can access the Am79C972 PCI configuration

space with a configuration read or write command. The

Am79C972 controller will asser t DEVSEL during the

address phase when IDSEL is asser ted, AD[1:0] are

both 0, and the access is a configuration cycle. AD[7:2]

select the DWord location in the configuration space.

The Am79C972 controller ignores AD[10:8], because it

is a single function device. AD[31:11] are don’t care.

The active bytes within a DW ord are determined by the

byte enable sig nals. Eight-bit, 16-bit, a nd 32-bit tran s-

fers are suppor ted . DEVSEL is asser ted two clock cy-

cles after the host has asserted FRAME. All

configuration cycles are of fixed length. The

Am79C972 controller will assert TRDY on the third

clock of the data phase.

The Am79C972 controller does not support burst trans-

fers for access to config uration space. When the host

keeps FRAME asser ted for a second data phase, the

Am79C972 controller will disconnect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET (see section on RESET) is on-going, the

Am79C 972 controller will ter minate the access o n the

PCI bus with a disconnect/retry response.

The Am79C972 controller supports fast back-to-back

transactions to different targets. This is indicated by the

F ast Back-To-Back Capable bit (PCI Status register , bit

7), whi ch is hardw ired to 1. T he Am79C97 2 controller

is capable of detecting a configuration cycle ev en when

its address phase immediately follows t he data phase

of a transaction to a different target without any idle

state in-between. There will be no contention on the

DEVSEL, TRDY, and STOP signals, since the

Am79C 972 controller asser ts DEVSE L on the secon d

clock after FRAME is asserted (medium timing).

Slave I/O Transfers

After the A m79C972 co ntroller is c onfigured as an I/O

device by setting IOEN (for regular I/O mode) or

MEMEN (for memory mapped I/O mode) in the PCI

Command re giste r, it s tarts monito ring the PCI bus for

access to its CSR, BCR, or APROM locations. If con-

figured for regular I/O mod e, the Am79C972 contr oller

will look f or an address that f alls within its 32 bytes of I/

O address spa ce (starting from the I/O bas e add re ss) .

The Am79C972 controller asserts DEVSEL if it det ects

an address match and the access is an I/O cycle. If

configured for memory mapped I/O mode, the

Am79C 972 controlle r will look fo r an address that falls

within its 32 bytes of me mory ad dress spa ce (star ting

from the memory mapped I/O base address). The

Am79C972 controller asser ts DEVSEL if it detects an

address match and the access is a memory cycle.

DEVSEL is asserted two clock cycles after the host has

asserted FRAME. See Figure 1 and Figure 2.

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Read of CSR, BCR, APROM,

and Reset registers

0011 I/O Write Write to CSR, BCR, and

APROM

0100 Reserved

0101 Reserved

0110 Memory Read

Memory mapped I/O read of

CSR, BCR, APROM, and

Reset registers

Read of the Expansion Bus

0111 Memory Write Memo ry mapped I/O write of

CSR, BCR, and APROM

1000 Reserved

1001 Reserved

1010 Configuration

Read Read of the Configuration

Space

1011 Configuration

Write Wr ite to the Configuration

Space

1100 Memory Read

Multiple Aliased to Memory Read

1101 Dual Address

Cycle Not used

1110 Memory Read

Line Aliased to Memory Read

1111 Memory Wri te

Invalidate Aliased to Memory Write

AD31

AD11 AD10

AD8 AD7

AD2 AD1 AD0

Don’t care Don’t care DWord

index 00

28 Am79C972

Figure 1. Slave Configuration Read

The Am79C972 controller will not asser t DEVSEL if it

detects an address match, but the PCI command is not

of the c orrect type. In m emor y mapped I/O mode, the

Am79C972 controller aliases all accesses to the I/O re-

source s o f the co m man d ty pes Mem ory Rea d Mu lti pl e

and Memory Read Line to the basic Memory Read com-

mand. All accesses of the type Memor y Write an d In-

validate are aliased to the basic Memory Write

command. Eight-bit, 16-bit, and 32-bit non-burst trans-

actions are supported. The Am79C972 controller de-

codes all 32 address lines to determine which I/O

resource is accessed.

The typica l numb er of wait st ates added to a slave I/O

or memory mapped I/O read or write access on the part

of the Am79C972 controller is six to seven clock cycles,

depending upon the relative phases of the internal Buff-

er Management Unit clock and the CLK signal, since

the inter nal Buffer Managemen t Unit clock is a divide-

by-two version of the CLK signal.

The Am79C972 controller does not support burst trans-

fers for access to its I/O resources. When the host keeps

FRAME asserted for a second data phase, the

Am79C972 controller will disconnect the transfer.

Figure 2. Slave Configuration Write

The Am79C972 controller supports fast back-to-back

transactions to different targets. This is indicated by the

F ast Back-To-Back Capable bit (PCI Status register , bit

7), whi ch is hardw ired to 1. T he Am79C97 2 controller

is capable of detecting an I/O or a memory-mapped

I/O cycle e ven when its address phase immediately fol-

lows the data phase of a transaction to a different target,

without any idle state in-between. There will be no con-

tention on the DEVSEL, TRD Y , and STOP signals, since

the Am79C972 controller asserts DEVSEL on the sec-

ond clock after FRAME is asserted (medium timing) See

Figure 3 and Figure 4.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1010

PAR PAR PAR

DEVSEL is sampled

DATA

ADDR

21485C-4

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1011

PAR PAR PAR

DATA

ADDR

21485C-5

Am79C972 29

Figure 3. Slave Read Using I/O Command

Figure 4. Slave Write Using Memory Command

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0010

PAR

1 2345678 109 11

DATA

PAR

21485C-6

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0111

PAR

1 2345678 10911

DATA

PAR

21485C-7

30 Am79C972

Expansion ROM Transfers

The host mus t initiali ze the Expansi on ROM Base Ad-

dress register at offset 30H in the PCI configuration

space wi th a valid add ress b efore enabling the ac ce ss

to the device. The Am79C972 controller will not react to

any access to the E xpansion ROM until bo th MEMEN

(PCI Command register, bit 1) and ROMEN (PCI Ex-

pansion ROM Base Address register, bit 0) are set to 1.

After the Expansion ROM is enabled, the Am79C972

controller will asser t DEVSEL on all memor y read ac -

cesses with an address between ROMBASE and

ROMBASE + 1M - 4. The Am79C972 controller aliases

all accesses to the Expansion ROM of the command

types Memory Read Multiple and Memory Read Line to

the basic Memory Read command. Eight-bit, 16-bit,

and 32-bit read transfers are supported.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given

the PCI Memory Mapped I/O Base Address register

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress re gister to a value th at prevents the Am7 9C972

controller from claiming any memory cycles not in-

tended for it.

The Am79C972 controller will always read four bytes

for every host Expansion ROM read access. TRDY will

not be asserted until all four bytes are loaded into an in-

ternal scr at ch re gis ter. The cycl e TRDY is asserted de-

pends on the programming of the Expansion ROM

interface timing. The following figure (Figure 5) as-

sumes tha t ROMTMG ( BCR1 8, bits 15- 12) is at its de-

fault value.

Note: The Expansion ROM should be read only during

PCI configuration time for the PCI system.

When the host tries to write to the Expansion ROM, the

Am79C972 controller will claim the cycle by asse rtin g

DEVSEL. TRDY will be a sserted one cl ock cycle la ter.

The write operation will have no effect. Writes to the Ex-

pansion ROM are done through the BCR30 Expansion

Bus D ata Por t. See the se ction on the Expansion Bus

Interface for more details. See Figure 5.

Figure 5. Expansion ROM Read

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

CMD

PAR

1 2345 484950

DATA

PAR

DEVSEL is sampled

21485C-8

Am79C972 31

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1).

Slave Cycle Termination

There are three scen arios besides nor mal completion

of a transact ion wher e the Am7 9C972 c ontrolle r is the

target of a slave cycle and it will terminate the access.

Disconnect When Busy

The Am79C972 controller cannot service any slav e ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not allowed in order to avoid

conflicts, since the EEPROM is used to initialize some

of the PCI configuration space locations and most of

the BCRs an d CSR 116. T he E EPROM r ea d o peration

will always happen automa tical ly af ter the deas sertion

of the RST pin. In addition, the host can star t the read

operation by setting the PREAD bit (BCR19, bit 14).

While the EEPROM read is on-going, the Am79C972

controller will disconnect any slave access where it is

the target by asser ting STOP together with DEVSEL,

while driving TRDY high. STOP will stay asserted until

the end of the cycle.

Note t hat I/O and m emo r y s lave acce sses w ill only b e

disconnected if they are enabled by setting the IOEN or

MEMEN bi t in the P CI Comma nd re gister. Wi thout th e

enable bit set, the cycles will not be claimed at all.

Since H_R ES ET c lears the IOEN an d ME ME N bit s for

the automati c EEPROM read after H_RESET, the dis-

conne ct onl y applies to configu rati on cycl es.

A seco nd s itu ati on wh er e the Am79 C972 con tro ller wil l

generate a PCI disconnect/retry cycle is when the host

tries to access any of the I/O resources right after hav-

ing read the Reset register. Since the access gener-

ates an i nter n al reset puls e of abo ut 1 µs i n leng th, all

further slave accesses will be deferred until the internal

reset operation is completed. See Figure 6.

Disconnect Of Burst Transfer

The Am79C972 controller does not support burst ac-

cess to the configuration space, the I/O resources, or to

the Expansion Bus. The host indicates a burst transac-

tion by keeping FRAME asserted during the data

phase. When the Am79C972 controller sees FRAME

and IRDY as se rted in the cl ock cycl e b efore it wan t s to

assert TRDY, it also asserts STOP at the same time.

The transfer of the first data phase is still successful,

since IRDY and TRD Y are both asserted. See Figure 7.

Figure 6. Disconnect Of Slave Cycle When Busy

Figure 7. Disconnect Of Slave Burst T ransfer - No

Host Wait States

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

CMD

PAR PAR PAR

DATA

ADDR

21485C-9

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

PAR PAR PAR

DATA

1st DATA

21485C-10

32 Am79C972

If the host is not yet ready when the Am79C972 control-

ler asserts TRDY, the device will wait for the host to as-

sert IRDY. When the host asserts IRDY and FRAME is

still asserted, the Am79C972 controller will finish the

first data phase by deasser ting TRDY one clock later.

At the same time, it will assert ST OP to signal a discon-

nect to the hos t. STOP will stay asserted until the host

removes FRAME. See Figure 8.

Figure 8. Disconnect Of Sla ve Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am 79C972 controller is not the current bus

master, it samples the AD[31:0], C/BE[3:0], and the

PAR lines during the address phase of any PCI com-

mand f or a parity error . When it detects an address par-

ity error, the controller sets PERR (PCI Status register ,

bit 15) to 1. Whe n reporting of that erro r is ena bled by

setting SERREN (PCI Command register, bit 8) and

PERREN (PCI Command register, bit 6) to 1, the

Am79C9 72 co ntroller a lso d r ives the SERR signal low

for one clock cycle and sets SERR (PCI Status register,

bit 14) to 1. The assertion of SERR f ollows the address

phase by two clock cycles. The Am79C972 controller

will not asser t DEVSEL for a PCI transaction th at has

an address parity error when PERREN and SERREN

are set to 1. See Figure 9.

Figure 9. Addre ss Parity Error Response

During the data phase of an I/O write, memory-mapped

I/O write, or configuration write command that selects

the Am79C972 controller as target, the device samples

the AD[31:0] and C/BE[3:0] lines for parity on the clock

edge, and data is transferred as indicated by the asser-

tion of IRDY and TRDY. PAR is sampled in the f ollowing

clock cycle. If a parity error is detected and reporting of

that error is enabled by setting PERREN (PCI Com-

mand reg ister, bit 6) to 1, P ERR is as serted one c lock

later . The parity error will always set PERR (PCI Status

regist er, bit 15 ) to 1 eve n wh en PERREN is c leared t o

0. The Am79C972 controller will finish a transaction

that has a data parity error in the normal way by assert-

ing TR DY. The corrup ted da ta wi ll be writt en to th e ad-

dressed location.

Figure 10 shows a transaction that suffered a parity

error at the time data was transferred (clock 7, IRDY

and TRDY are both asse r ted). PERR is driven high at

the beginning of the data phase and then drops low due

to the parity error on clock 9, two clock cycles after the

data was transferred. After PERR is driven low, the

Am79C972 controller drives PERR high for one clock

cycle, since PERR is a sustained tri-state signal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 23456

PAR

PAR PAR

DATA

1st DATA

21485C-11

FRAME

CLK

SERR

C/BE

DEVSEL

1 2345

PAR PAR

ADDR 1st DATA

CMD

PAR

21485C-12

Am79C972 33

Figure 10. Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acqui-

sition of th e PCI bu s and all acce sses to the initi aliza-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 3 shows the usage of

PCI comm ands by the Am 79C972 c ontr o lle r i n m as ter

mode.

Bus Acquisition

The Am79C972 microcode will determine when a DMA

transfer should be initiated. The first step in any

Am79C972 bus master transfer is to acquire ownership

of the bus. This task is handled by synchronous logic

within the BIU. Bus ownership is requested with the

REQ signal and ownership is granted by the arbiter

through the GNT signal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

1 2345678 109

DATA

PAR

PERR

21485C-13

Table 3. Master Commands

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Not used

0011 I/O Write Not used

0100 Reserved

0101 Reserved

0110 Memory Read

Read of the initialization

block and desc riptor

rings

Read of the transmit

buffer in non-burst mode

0111 Memory Write Write to the descriptor

rings and to the re-

ceive buffer

1000 Reserved

C[3:0] Command Use

1001 Reserved

1010 Config uration Read Not used

1011 Configuration Write Not used

1100 Memory Read

Multiple Read of the transmit

buffer in burst mode

1101 Dual Address C ycle Not used

1110 Memory Read Line Read of the transmit

buffer in burst mode

1111 Memory Write

Invalidate Not used

Table 3. M ast er Command s (Continued)

34 Am79C972

Figure 11 shows the Am79C972 controller bus acquisi-

tion. REQ is asserted and the arbiter returns GNT while

another bus master is transferring data. The

Am79C972 controller waits until the bus is idle (FRAME

and IR DY deasserted) before it star t s dr iving AD[ 31:0]

and C/B E[3:0 ] o n clo ck 5. FRAM E is asserted at clock

5 indicating a valid address and command on AD[31:0]

and C/BE[3:0]. The Am79C972 controller does not use

address stepping which is reflected by ADSTEP (bit 7)

in the PCI Command register being hardwired to 0.

Figure 11. Bus Acquisition

In burst mode, the deassertion of REQ depends on the

setting of EXTREQ (BCR18, bit 8). If EXTREQ is

cleared to 0, REQ is deasser ted at the same time as

FRAME is asser ted. (The Am79C972 controller never

performs mor e than one burst transactio n within a si n-

gle bus master ship per iod.) If EXTRE Q is set to 1, the

Am79C972 controller does not deasser t REQ until it

starts the last data phase of the transaction.

Once asse rted, REQ remains active until GNT has be-

come acti ve and indepen dent of subs equ ent s etti ng of

ST OP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-

tion of H_RESET or S_RESET, however, will cause

REQ to go inactive immediately.

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

Am79C972 controller uses non-burst as well as burst

cycles for read and write access to the main memory.

Basic Non-Burst Read Transfer

By default, the Am79C972 controller uses non-burst

cycles in all b us master read operations. All Am79C972

controller non-burst read accesses are of the PCI

command type Memory Read (type 6). Note that during

a non-burst read operation, all b yte lanes will alwa ys be

active. The Am79C972 controller will internally discard

unneeded bytes.

The Am79C972 controller typically performs more than

one non-burst read transaction within a single bus mas-

tership per iod. FRAME is dropped between consecu-

tive non-burst read cycles. REQ however stays

asserted until FRAME is asser te d fo r the last tran sac-

tion. The Am79C972 controller supports zero wait state

read cycles. It asser ts IRDY immediately after the ad-

dress phase and at the same time starts sampling

DEVSEL. Figure 12 shows two non-burst read transac-

tions. The firs t transaction has zero wait state s. I n the

second transaction, the target extends the cycle by as-

serting TRDY one clock later.

Basic Burst Read Transfer

The Am79C972 controller supports burst mode for all

bus master read operations. The burst mode must be

enabled by setting BREADE (BCR18, bit 6). To allow

burst transfers in descriptor read operations, the

Am79C972 controller must also be programmed to use

SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses

to the i nitiali zation block a nd descr iptor ring are of the

PCI com ma nd type Memory Read (type 6). Bur st rea d

accesses to the transmit buffer typically are longer than

two data phases. When MEMCMD (BCR18, bit 9) is

cleared to 0, all burst read accesses to the transmit

buffer are of the PCI command type Memory Read Line

(type 14). When MEMCMD (BCR18, bit 9) is set to1, all

burst read accesses to the transmit buffer are of the

PCI command type Memory Read Multiple (type 12).

AD[1:0] will both be 0 during the address phase indicat-

ing a linear burst order. Note that during a burst read

operation, all byte lanes will always be active. The

Am79C972 controller will internally discard unneeded

bytes.

The Am79C972 controller will always perform only a

single burst read transaction per bus mastership pe-

riod, where transaction is defined as one address

phase and one or multiple data phases. The

Am79C972 controller supports zero wait state read cy-

cles. It asserts IRDY immediately after the address

phase an d at the s ame tim e s tarts samplin g DE VS EL .

FRAME is deasserted when the next to last data phase

is completed.

Figure 13 shows a typical burst read access. The

Am79C 972 controller a rb itrates for the bus, is granted

access, reads three 32-bit words (D Word) from the sys-

tem memor y, and then releas es the bus. In the exam-

ple, the memory system extends the data phase of

each ac ce ss by on e wait s ta t e. The example as su mes

that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,

REQ is deasserted in the same cycle as FRAME is as-

serted.

FRAME

CLK

IRDY

C/BE

REQ

GNT

1 2345

CMD

ADDR

21485C-14

Am79C972 35

Figure 12. Non-Burst Read Transfer

Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

1 2345678 109 11

DATA

ADDR

DATA

PAR PAR PAR

0000 0110 0000

21485C-15

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

00001110

PAR

1 2345678 10911

DATA

PAR PAR PAR

21485C-16

36 Am79C972

Basic Non-Burst Write Transfer

By default, the Am79C972 controller uses non-burst

cycles in all bus master write operations. All

Am79C972 controller non-burst write accesses are of

the PCI command type Memory Write (type 7). The

byte enable signals indicate the byte lanes that have

valid data.T he Am79C972 controller typically performs

more than one non-burst write transaction within a sin-

gle bus mastership period. FRAME is dropped be-

tween consecutive non-burst write cycles. REQ,

however, stays asserted until FRAME is asser ted for

the last transaction. The Am79C972 supports zero wait

state write cycles except with descriptor write transfers.

(See the section Descriptor D M A Transfers f or the only

exception.) It asserts IRDY immediately after the ad-

dress phase.

Figure 14 sh ows two non-burst wr i te transac ti ons. The

first transacti on has two wait stat es. The target i nserts

one w ait stat e by as serting DEV SEL one clock late and

another wait state by also asser ting TRDY one clock

late. The second transaction shows a zero wait state

write cycle. The target asser ts DEVSEL and TRDY in

the same cycle as the Am79C972 controller asserts

IRDY.

Basic Burst Write Transfer

The Am79C972 controller supports burst mode for all

bus master wr ite operations. The burst mode must be

enabled by setting BWRITE (BCR18, bit 5). To allow

burst transfers in descriptor write operations, the

Am79C972 controller must also be programmed to use

SWSTYLE 3 (BCR20, bits 7-0). All Am79C972 control-

ler burst write transfers are of the PCI command type

Memory Write (type 7). AD[1:0] will both be 0 during the

address phase indicating a linear burst order. The byte

enable signals indicate the byte lanes that have valid

data.

The Am 79C972 contr olle r will always perform a si ngle

burst write transaction per bus mastership period,

where transaction is defined as one address phase and

one or mult iple da ta phase s. T he Am79C 972 co ntrol ler

supports zero wait state write cycles except with the

cas e of de sc ript o r w rite transfers. (S ee t he sectio n De-

scriptor DMA Transfers f or the only exception.) The de-

vice a sserts IRDY immediately after the address phase

and at the same time starts sampling DEVSEL.

FRAME is deasserted when the next to last data phase

is completed.

Figure 14. Non-Burst Wr ite Transfer

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 2345678 109

DATA

ADDR

DATA

PAR PAR PAR

BE 0111 BE

21485C-17

Am79C972 37

Figure 15 shows a typical burst write access. The

Am79C972 c ontroller arb itrat es for the bus, is gra nted

access, and writes four 32-bit words (DWords) to the

system memor y and then r eleases the bus. In this ex-

ample, the memor y sys tem extends the data phase of

the first access by one wait state. The following three

data phases take one clock cycle each, which is deter-

mined by the timing of TRDY. The example assumes

that EXTREQ (BCR18, bit 8) is set to 1, therefore , REQ

is not deasserted until the next to last data phase is fin-

ished.

Tar get Initiated Termination

When the Am79C972 controller is a b us master , the cy-

cles it pr oduces on the PCI bus may be termin ated by

the target in one of three different ways: disconnect

with data transfer , disconnect without data transfer , and

target abort.

Disconnect With Data Transfer

Figure 16 shows a disconnection in which one last data

transfer occurs after the target asser ted STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C972

controller terminates the current transfer with the deas-

sertion of FRAME on clock 5 and of IRDY one clock

later. It finally releases the bus on clock 7. The

Am79C972 controller will again request the bus after

two clock cycles, if it wants to transfer more da ta. The

starting address of the new transf er will be the address

of the next non-transferred data.

Figure 15. Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

12345678

ADDR DATA DATA DATA

0111

PAR PAR PAR PAR PAR

DATA

PAR

DEVSEL is sampled

21485C-18

38 Am79C972

Figure 16. Disconnect With Data Transfer

Disconnect Without Data Transfer

Figure 17 shows a ta rget disc onnect se quence du rin g

which no data is transferred. STOP is asserted on clock

4 without TRDY being ass er t ed at the s ame t ime. The

Am79C972 controller terminates the access with the

deassertion of FRAME on clock 5 and of IRDY one

clock cycle la ter. It fin ally releas es the bus on clock 7.

The Am79C972 controller will again request the bus

after two clock cycles to retry the last transfer. The

starting address of the new transfer will be the address

of the last non-transferred data.

Target Abort

Figure 18 shows a target abor t sequ ence. The target

asserts DEVSEL for one clock. It then deasserts

DEVSEL and asser ts STOP on clock 4. A tar get can

use the target abo r t sequence to indicate that it can-

not service the data transfer and that it does not want

the transaction to be retried. Additionally, the

Am79C972 controller cannot make any assumption

about the success of the previous data transf ers in the

current transaction. The Am79C972 controller termi-

nates the current transfer with the deassertion of

FRAME on clock 5 and of IRDY one clock cycle later.

It finally releases the bus on clo ck 6.

Since data integrity is not guaranteed, the Am79C972

controller cannot recover from a target abort ev ent. The

Am79C972 controller will reset all CSR locations to

their STOP_RESET values. Th e BCR and PCI c onfig-

uration regi sters wil l not be clea red. Any on-goin g net-

work transmission is terminated in an orderly

sequenc e. If les s than 512 bits have been transm itted

onto the network, the transmission will be terminated

immediately, generating a runt packet. If 512 bits or

more have been transmitted, the message will hav e the

current FCS inverted and appended at the next byte

boundary to guarantee an FCS error is detected at the

receiving station.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDRi

00000111

PAR

0111

23456789 11

PAR

DATA

STOP

ADDRi+8

DATA

21485C-19

Am79C972 39

Figure 17. Disconnect Without Data Transfer

RTABORT (PCI Status register, bit 12) will be set to

indicate that the Am79C972 controller has received a

target abort. In addition, SINT (CSR5, bit 11) will be set

to 1. When SINT is set, INTA i s asser ted if the e nable

bit SINTE (CSR5, bit 10) is set to 1. This mechanism

can be used to inform the driver of the system error. The

host can read the PCI Status regis ter to de termine the

exact cause of the interrupt.

Master Initiated Termination

There are three scen arios besides nor mal completion

of a transaction where the Am79C972 controller will

terminate the cycles it produces on the PCI bus.

Preemption During Non-Burst Transaction

When the Am79C972 controller performs multiple non-

burst transactions, it keeps REQ as se rted until the as -

ser tion of FRAME for the last transaction. When GNT

is removed, the Am79C972 controller will finish the cur-

rent transaction and then release the bus. If it is not the

last transaction, REQ will remain asserted to regain

bus ownership as soon as possible. See Figure 19.

Preemption During Burst Transaction

When the Am79C972 controller operates in burst

mode, it only performs a single transaction per bus

mast ersh ip period , wher e transaction is defined as one

address phase and one or multiple data phases. The

central arbiter can re move GNT at any time du ring th e

transaction. The Am79C972 controller will ignore the

deasser tion of GNT and continue with data transfers,

as long as the PCI Latency Timer is not expired. When

the Latency Timer is 0 and GNT is deasserted, the

Am79C972 controller will finish the current data phase,

deassert FRAME, finish the last data phase, and re-

lease the bus. If EXTREQ (BCR 18, bit 8) is clea red to

0, it will imme diately as ser t REQ to regai n bus owner-

ship as soon as possible. If EXTREQ is set to 1 , REQ

will stay asser t ed .

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

STOP

ADDRi

00000111

PAR

0111

23456789 11

ADDRi

DATA

PAR

21485C-20

40 Am79C972

Figure 18. Target Abort

When the preemption occurs after the counter has

counted down to 0, the Am79C972 controller will finish

the current data phase, deassert FRAME, finish the

last data phase, and release the bus. Note that it is im-

por tant for the host to program the PCI Lat ency Timer

according to the bus bandwidth requirement of the

Am79C972 controller. The host can determine this bus

bandwidth requirement by reading the PCI MAX_LAT

and MIN_GNT registers.

Figure 20 assumes that the PCI Latency Timer has

counted down to 0 on clock 7.

Master Abort

The Am79C972 controller will terminate its cycle with a

Master Abort sequence if DEVSEL is not asserted

within 4 clocks after FRAME is asserted. Master Abort

is treat ed as a fatal error by the Am79C9 72 contr oller.

The Am79C972 controller will reset all CSR locations

to their STOP_RESET values. The BCR and PCI c on-

figuration registers will not be cleared. Any on-going

network transmission is terminated in an orderly se-

quence. If less than 512 bits have been transmitted

onto the network, the transmission will be terminated

immediately, generating a runt packet. If 512 bits or

more have been transmitted, the message will hav e the

current FCS inverted and appended at the next byte

boundary to guarantee an FCS error is detected at the

receiving station.

RMABORT (in the PCI Status register, bit 13) will be set

to indicate that the Am79C972 controller has termi-

nated its transaction with a master abort. In addition,

SINT (CSR5, bit 11) will be set to 1. When SINT is set,

INTA is asserted if the enable bit SINTE (CSR5, bit 10)

is set to 1. This mechanism can be used to inform the

driver of the system error. The host can read the PCI

Status re gister to deter mine the exac t cause of the in-

terrupt. See Figure 21.

Parity Error Response

During every data phase of a DMA read operation,

when the target indicates that the data is valid by as-

serting TRDY, the Am79C972 controller samples the

AD[31:0], C/BE[3:0] and the PAR lines for a data parity

error. When it detects a data parity error, the controller

sets PERR (PCI S tatus r egister, bit 15) to 1. Wh en re-

porting of that error is enabled by setting PERREN

(PCI Command register, bit 6) to 1, the Am79C972

controller also drives the PERR signal low and sets

D ATAPERR (PCI Status register , bit 8) to 1. The asser-

tion of PERR follows the corrupted data/byte enables

by two clock cycles and PAR by one clock cycle.

Figure 22 shows a transaction that has a parity error in

the data phase. The Am79C972 controller asserts

PERR on clock 8, two clock cycles after data is valid.

The data on cl ock 5 is not checked for pa rity, since on

a read access PAR is only required to be valid one

clock after the target has asserted TRDY. The

Am79C972 controller then drives PERR high for one

clock cycle, since PERR is a sustained tri-state signal.

During every data phase of a DMA write operation, the

Am79C 972 contr oller checks the PERR input t o see if

the target reports a parity error . When it sees the PERR

input asserted, the controller sets PERR (PCI Status

sets DATAPERR (PCI Status register, bit 8) to 1.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

234567

ADDR

0000

0111

PAR PAR

DATA

STOP

21485C-21

Am79C972 41

Figure 19. Preemption Duri ng No n-Burst Transaction

Figure 20. Preemption During Burst Transaction

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

BE0111

PAR PAR

DEVSEL is sampled

PAR

DATA

ADDR

21485C-22

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

BE0111

PAR

1 23456789

DATA

PAR

REQ

DATA

PAR PAR PAR PAR

GNT

21485C-23

42 Am79C972

Figure 21. Master Abort

Figure 22. Master Cycle Data Parity Error Response

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

REQ

GNT

0000

21485C-24

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

PERR

21485C-25

Am79C972 43

Whenever the Am79C972 controller is the current bus

mast er an d a da ta pa rity error o ccu rs, SIN T (C S R 5, bi t

11) will be set to 1. When SINT is set, INTA is asserted

if the enable bit SI NTE (CSR 5, bit 10) is s et to 1. This

mechanism can be used to inform the driver of the sys-

tem error. The host can read the PCI Status register to

determi ne the exact cause of the interrupt. Th e set tin g

of SINT due to a data par ity e rror is not d ependen t on

the setting of PERREN (PCI Command register, bit 6).

By default, a data par ity er ror does not affect the stat e

of the MAC engine. The Am79C972 controller treats the

data in all bus mas ter trans fers that have a par it y err or

as if nothing has happened. All network activity contin-

ues.

Advanced Parity Error Handling

For al l DMA cy cl es, the Am 79C972 cont ro ll er provides

a second, more advanced level of parity error handling.

This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits

(RMD1 and TMD1, bit 23) are used to indicate parity

error in da ta transfers to the rece ive and transmit buff-

ers. Note that since the advanced parity error handling

uses an additional bit in the descriptor, SWSTYLE

(BCR20, bits 7-0) must b e s et to 2 or 3 to pr ogram the

Am79C972 controller to use 32-bit software structures.

The Am79C972 controller will react in the f ollowing way

when a data parity error occurs:

nInitialization block read: STOP (CSR0, bit 2) is set to

1 and causes a STOP_RESET of the device.

nDescriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bi t 2) is set to 1 to cause a STO P_RESET

of the device.

nDescriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bi t 2) is set to 1 to cause a STO P_RESET

of the device.

nTransmit buffer read: BPE (TMD1, bit 23) is set in

the current transmit descriptor. Any on-going net-

work transmission is terminated in an orderly se-

quence.

nReceive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Terminating on-going network transmission in an or-

derly sequence means that if less than 512 bits have

been transmitted onto the network, the transmission

will be terminated immediately, generating a runt

packet.

If 512 bits or more have been transmitted, the message

will have the current FCS inverted and appended at the

next byte boundary to guarantee an FCS error is de-

tected at the receiving station.

APERREN does not affect the reporting of address

parity errors or data parity errors that occur when the

Am79C 972 co ntrol ler is the target of the trans fer.

Initialization Block DMA Transfers

During ex ecution of the Am79C972 controller bus mas-

ter initialization procedure, the Am79C972 microcode

will repeatedly request DMA transfers from the BIU.

During each of these initialization block DMA transfers,

the BIU will perform two data transfer cycles reading

one DWord per transfer and then it will relinquish the

bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the

initialization block is organized as 32-bit software struc-

tures), there are seven DWords to transfer during the

bus master initialization procedure, so four b us master-

ship periods are needed in order to complete the initial-

ization s equence. Note that the last DWord transfer of

the last bus mastership period of the initialization se-

quence accesses an unneeded location. Data from this

transfer is discarded internally. When SSIZE32 is

cleared to 0 (i.e., the initialization block is organized as

16-bit software structures), then three bus mastership

periods are needed to complete the initialization se-

quence.

The Am7 9C97 2 supp orts two transfer modes for read-

ing the initialization block: non-burst and burst mode,

with burst mode being the preferred mode when the

Am79C 972 contr olle r is used in a PCI bus applica tion.

See Figure 23 and Figure 24.

When BREADE is cleared to 0 (BCR18, bit 6), all initial-

ization block read transfers will be executed in non-

burst mode. There is a new address phase for every

data phase. FRAME will be drop ped between the two

transfers. The two phases within a bus mastership pe-

riod will have addresses of ascending contiguous or-

der.

When BR EADE is se t to 1 (BCR18, bit 6) , al l initi al iz a-

tion block read transfers will be executed in burst mode.

AD[1:0] will be 0 during the address phase indicating a

linear burst order.

44 Am79C972

Figure 23. Initialization Block Read In Non-Burst Mode

Figure 24. Initialization Block Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

IADDi

00000110

PAR PAR

DATA DATA

IADDi+4

0000

0110

PAR PAR

1 2345678 109

21485C-26

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000110

PAR PAR PAR PAR

DEVSEL is sampled

DATA DATA

IADDi

21485C-27

Am79C972 45

Descriptor DMA Transf ers

Am79C972 m icrocode will deter mine when a descr ip-

tor access is required. A descriptor DMA read will con-

sist of two data transfers. A descriptor DMA write will

consist of one or two data transfers. The descriptor

DMA transfers within a single bus mastership period

will always be of the same type (either all read or all

write).

During descr iptor read accesses, the byte enable sig-

nals will indicate that all byte lanes are active. Should

some of the bytes not be needed, then the Am79C972

controller will internally discard the extraneous informa-

tion that was gathered during such a read.

The settings of SWSTYLE (BCR20, bits 7-0) and

BREADE (BCR18, bit 6) affect the way the Am79C972

controller performs descriptor read operations.

When SWSTYLE is set to 0 or 2, all descriptor read op-

erations are per forme d i n no n- burst mode. T he se t tin g

of BREADE has no effect in this configuration. See Fig-

ure 25.

When SW STY LE is s et to 3 , the desc rip tor entr ie s a r e

ordered to allow burst transfers. The Am79C972 con-

troller will perform all descriptor read operations in

burst mode, if BREADE is set to 1. See Figure 26.

Table 4 shows the descriptor read sequence.

During descriptor write accesses, only the byte lanes

which need to be written are enabled.

If buffer chaining is u sed, accesses to the descriptors

of all intermediate buffers consist of only one data

transfer to return ownership of the buff er to the system.

When SWST YLE (BCR2 0, bits 7- 0) is cle ared to 0 (i .e.,

the desc r iptor en tries a re orga nized as 16- bit s oft ware

structures), the descriptor access will write a single

byte. W hen SWST YLE (BCR 20, bits 7-0 ) is set to 2 or

3 (i.e., the descriptor entries are organized as 32-bit

software str uctures), th e descripto r access will wri te a

single word. On all single buffer transmit or receive de-

scriptors, as well as on the last buff er in chain, writes to

the descriptor consist of two data transfers.

The first data transfer writes a DW ord containing status

information. The second data transfer writes a byte

(SWSTYLE cleared to 0), or otherwise a word contain-

ing additional status and the ownership bit (i.e.,

MD1[31]).

The settings of SWSTYLE (BCR20, bits 7-0) and

BWRITE (B CR18, bit 5) affect the way the Am79 C972

controller performs descriptor write operations.

When SWSTYLE is set to 0 or 2, all descriptor write op-

erations are per forme d i n no n- burst mode. T he se t tin g

of BWRITE has no effect in this configuration.

When SWST Y LE is s et to 3 , the descript or en trie s ar e

ordered to allow burst transfers. The Am79C972 con-

troller will perform all descriptor write operations in

burst mode, if BWRITE is set to 1. See Table 5 for th e

descriptor write sequence.

A wri te trans action to the descr iptor ring entr ies is the

only case where the Am79C972 controller inserts a

wait state when being the bus master. Every data

phase in non-burst and burst mode is extended by one

clock cycle, during which IRDY is deasserted.

Note that Figure 26 assumes that the Am79C972 con-

troller is programm ed to use 32- bit so ftware s tructur es

(SWSTYLE = 2 or 3). The byte enable signals for the

second data transfer would be 0111b , if the de vice was

programmed to use 16-bit software structures (SW-

STYLE = 0).

Table 4. Descriptor Read Sequence

SWSTYLE

BCR20[7:0] BREADE

BCR18[6] AD Bus Sequence

Address = XXXX XX00h

Turn around cycle

Data = MD1[31:24],

MD0[23:0]

Idle

Address = XXXX XX04h

Turn around cycle

Data = MD2[15:0], MD1[15:0]

Address = XXXX XX04h

Turn around cycle

Data = MD1[31:0]

Idle

Address = XXXX XX00h

Turn around cycle

Data = MD0[31:0]

Address = XXXX XX04h

Turn around cycle

Data = MD1[31:0]

Idle

Address = XXXX XX08h

Turn around cycle

Data = MD0[31:0]

Address = XXXX XX04h

Turn around cycle

Data = MD1[31:0]

Data = MD0[31:0]

46 Am79C972

Figure 25. Descriptor Ring Read In Non-Burst Mode

Figure 26. Descriptor Ring Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD1

00000110

PAR PAR

DATA DATA

MD0

00000110

PAR PAR

1 2345678 109

21485C-28

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

MD1

00000110

PAR PAR PAR

DATA DATA

PAR

DEVSEL is sampled 21485C-29

Am79C972 47

Table 5. Descriptor Write Sequence

FIFO DMA Transfers

Am79C972 microcode will determine when a FIFO

DMA transfer is required. This transfer mode will be

used for transfers of data to and from the Am79C972

FIFOs. Once the Am79C972 BIU has been granted bus

mastership, it will perform a series of consecutive

transfer cycles before relinquishing the bus. All trans-

fers within the master cycle will be either read or write

cycle s, and al l transfe rs will be to contig uous, ascend-

ing addresses. Both non-burst and burst cycles are

used, with burst mode b ei ng th e pr eferred mode whe n

the device is used in a PCI bus application.

Non-Burst FIFO DM A Transfers

In the default mode, the Am79C972 controller uses

non-burst transfers to read and write data when ac-

cessing the FIFOs. Each non-burst transf er will be per-

formed sequentially with the issue of an address and

the transfer of the corresponding data with appropriate

output signals to indicate selection of the active data

bytes during the transfer.

FRAME wil l b e d eas s erted after eve ry add re ss ph as e.

Several factors will a ffect the length of the bus mas ter -

ship period. The possibilities are as follows:

Bus cycles will continue until the transmit FIFO is filled

to its high threshold (read transfers) or the receive FIFO

is emptied to its low threshold (write transfers). The

ex act number of total transfer cycles in the bus master-

ship period is dependent on all of the following vari-

ables: the settings of the FIFO watermarks, the

conditi ons of the FI FOs, the laten cy of the sy stem bus

to the Am79C972 controller’s b us request, the speed of

bus operation and bus preemption events. The TRDY

response time of the memory device will also affect the

number of transfers, since the speed of the accesses

will affect the state of the FIFO. During accesses, the

FIFO may be filling or emptying on the network end. For

example, on a receive operation, a slower TRDY re-

sponse will allow additional data to accumulate inside

of the F IFO. If t he access es are sl ow e nough, a c om-

plete DWord may become available before the end of

the bus mastership period and, thereby, increase the

number of transfers in that period. The general rule is

that the longer the Bus Grant latency, the slower the

bus transf er operations; the slower the clock speed, the

higher the transmit watermark; or the higher the re-

ceive watermark, the longer the bus mastership period

will be.

Note: The PCI La tency Time r is not s ignific ant dur ing

non-burst transfers.

SWSTYLE

BCR20[7:0] BWRITE

BCR18[5] AD Bus Sequence

Address = XXXX XX04h

Data = MD2[15:0],

MD1[15:0]

Idle

Address = XXXX XX00h

Data = MD1[31:24]

Address = XXXX XX08h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Data = MD1[31:16]

48 Am79C972

Figure 27. Descriptor Ring Write In Non-Burst Mode

Figure 28. Descriptor Ring Write In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD2

00000111

PAR

MD1

00110111

PAR

1 2345678 109

DATA

PAR

DATA

21485C-30

GNT

REQ

DEVSEL

TRDY

PAR

C/BE

FRAME

CLK 35

PAR

IRDY

DEVSEL is sampled

DATA

1 2 4 6 7 8

0110 0000 0011

MD2

PAR

DATA

PAR

21485C-31

Am79C972 49

Burst FIFO DMA Tr ansfers

Bursting is only performed by the Am79C972 controller

if the BR EA DE and/or BW RITE bi ts o f BCR 18 are se t.

These b its indivi dually en able/disable the abi lity of the

Am79C972 controller to perf orm burst accesses during

master read operations and master write operations,

respectively.

A burst transaction will start with an address phase, f ol-

lowed by one or more data phases. AD[1:0] will always

be 0 during the address phase indicating a linear burst

order.

During FIFO DMA read operations, all byte lanes will

always be active. The Am79C972 controller will inter-

nally discard unused bytes. During the first and the last

data phases of a FIFO DMA burst write operation, one

or mor e o f th e byte e nable s ign al s may be in ac tive. All

other data phases will alwa ys write a complete D Word.

Figure 29 shows the beginning of a FIFO DMA write

with the beginning of the buffer not aligned to a DWord

boundar y. The A m79C972 c ontroller star ts off by wri t-

ing only three bytes during the first data phase. This op-

eration aligns the address for all other data transfers to

a 32-bit boundary so that the Am79C972 controller can

continue bursting full DWords.

If a receive buffer doe s n ot end on a DWord boun dary,

the Am79C972 controller will perform a non-DWord

write on the last transfer to the buffer. Figure 30 shows

the fin al three FIF O DMA transfers to a receive buffer.

Since there were only nine bytes of space left in the re-

ceive buff er, the Am79C972 controller bursts three data

phases. The first two data phases write a full DWord,

the last one only writes a single byte.

Not e t hat t h e Am 7 9C9 7 2 c on t ro ll er wi ll al wa y s pe r form

a DWord transfer as long as it owns the buffer space,

even when there ar e less than four bytes to wr ite. For

ex ample, if there is only one byte left for the current re-

ceive frame, the Am79C972 controller will write a full

DWord, containing th e las t byte of the receive frame in

the le ast signifi ca nt byte position (BSWP is c leared to

0, CSR3, bit 2). The content of the other thr ee bytes is

undefined . The m essage byte count in th e recei ve d e-

scriptor always reflects the ex act length of the received

frame.

Figure 29. FIFO Burst Write At Start Of Unaligned

Buffer

The Am79C972 controller will continue transferring

FIFO data until the transmit FIFO is filled to its high

thresho ld (read transfers) or the receive FIFO is emp-

tied to its low threshold (write transfers), or the

Am79C972 controller is preempted, and the PCI La-

tency Timer is expired. The host should use the values

in the PCI MIN_GNT and MAX_LAT registers to deter-

mine the value for the PCI Latency Timer.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 23456

00000111

PAR PAR PAR

DEVSEL is sampled

0001

PAR

DATA DATA

DATA

ADD

21485C-32

50 Am79C972

Figure 30. FIFO Burst Write At End O f Unaligned

Buffer

The exact number of total transfer cycles in the bus

mastership per iod is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditio ns of the FIFOs, the l atency of th e sys tem bus

to the Am79C972 controller’s bus request, and the

speed of bus operation. The TRDY response time of

the memory device will also affect the number of trans-

fers, since the speed of the accesses will affect the

state of the FIFO. During accesses, the FIFO may b e

filling or emptying on the network end. For e xample, on

a receive operation, a slower TRDY response will allow

additional data to accumulate inside of the FIFO. If the

accesses are slow enough, a complete D Word may be-

come available before the end of the bus mastership

period and, thereby, increase the number of transfers in

that per i od. The genera l r ul e is that th e lon ger the Bus

Grant latency, the slower the bus transfer operations;

the slower the clock speed, the higher the transmit wa-

termark; or the lower the receive watermark, the longer

the total burst length will be.

When a FIFO DMA burst operation is preempted, the

Am79C9 72 co ntro lle r wil l not reli nqu is h bus ownershi p

until the PCI Latency Timer expires.

Buffer Management Unit

The Buffer Management Unit (BMU) is a microcoded

state machine which implements the init ialization pro-

cedure and manage s the descr iptors and buffers. The

buffer management unit operates at half the speed of

the CLK input.

Initialization

Am79C972 initialization includes the reading of the ini-

tializa tion block in mem ory to obta in the operating pa-

rameters. The initialization block can be organized in

two ways. When SSIZE32 (BCR20, bit 8) is at its de-

fault value of 0, all initialization block entries are logi-

cally 16-bits wide to be backw ards compatible with the

Am79C90 C-LANCE and Am79C96x PCnet-ISA family.

When SSI ZE32 (BCR20, bit 8) is set to 1, all i nitializ a-

tion block entries are logically 32-bits wide. Note that

the Am79C972 controller always performs 32-bit bus

transfers to read the initialization block entries. The ini-

tialization block is read when the INIT bit in CSR0 is set.

The INIT bit should be set before or concurrent with the

STRT bit to insure correct operation. Once the initial-

ization block has been co mplete ly rea d in a nd in ter nal

registers have been updated, IDON will be set in

CSR0, generating an interrupt (if IENA is set).

The A m79C972 cont roller obtain s the sta r t a ddres s of

the initialization block from the contents of CSR1 (least

signifi cant 16 b its o f addr ess) a nd CSR2 (most s igni fi-

cant 16 bits of address). The host must write CSR1 and

CSR2 before setting the INIT bit. The initialization block

contains the user defined conditions for Am79C972 op-

eration, together with the base addresses and length

information of the transmit and receive descriptor rings.

There is an alternate method to initialize the

Am79C972 controller. Instead of initialization via the

initialization block in memory, data can be written di-

rectly into the appropriate registers. Either method or a

combination of the two ma y be used at the discretion of

the programmer. Please refer to Appendix A, Alterna-

tive Method for Initialization for details on this alternate

method.

Re-Initialization

The transmitter and receiver sections of the Am79C972

controller can be turned on via the initialization block

(DTX, D RX, CSR1 5, bits 1- 0). Th e states o f the tran s-

mitter and receiver are monitored by the host through

CSR0 (RXON, TXON bits). The Am79C972 controller

should be re- initialized if the transmi tter and/or the re-

ceiver were not tur n ed on dur ing the or iginal initializ a-

tion, and it was subsequently required to activate them

or if either se ction was shut off due to the detec tion of

an error condition (MERR, UFLO, TX BUFF error).

Re-initialization may be done via the initialization block

or by setting the STOP bit in CSR0, followed by writing

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000111

PAR PAR PAR PAR

DEVSEL is sampled

1110

PAR

DATA DATA

DATA

ADD

21485C-33

Am79C972 51

to CSR15, and then setting the START bit in CSR0.

Note that thi s form of r e sta rt will not perfor m th e s am e

in the Am79C972 controller as in the C-LANCE device.

In particular , upon restart, the Am79C972 controller re-

loads the transmi t and rece ive descr iptor point ers wit h

their respective base addresses. This means that the

software must clear the des cript or OWN bits and reset

its descriptor ring pointers before restarting the

Am79C972 controller. The reload of descriptor base

addresses is performed in the C-LANCE device only

after initialization, so that a restart of the C-LANCE

without initialization leaves the C-LANCE pointing at

the same descriptor locations as before the restart.

Suspend

The Am79C972 controller offers two suspend modes

that allow easy updating of the CSR registers without

going through a full re-initialization of the device. The

suspend modes also allow stopping the device with or-

derly termination of all network activity.

The host requests the Am79C972 controller to enter

the suspend mode by setting SPND (CSR5, bit 0) to 1.

The host must poll SPND until it reads back 1 to deter-

mine that the Am79C972 controller has entered the

suspend mode. When the host sets SPND to 1, the pro-

cedure taken by the Am79C972 controll er to enter the

suspend mo de depe nds o n the setti ng of t he fast sus-

pend enable bit (FASTSPND, CSR7, bit 15).

When a fast suspend is requested ( FA STSPND is set

to 1), the Am79C 972 control ler p erforms a quick e ntr y

into the suspend mode. At the time the SPND bit is set,

the Am79C972 controller will continue the DMA pro-

cess o f any transmit and/or receive packets that have

already begun DMA activity until the network activity

has been completed. In addition, any transmit packet

that had started transmission will be fully transmitted

and any receive packet that had begun reception will be

fully received. However, no additional packets will be

transmitted or received and no additional transmit or re-

ceive DMA acti vity w ill begin after n etwor k acti vity has

ceased. Hence, the Am79C972 controller may enter

the suspend mode with transmit and/or receive packets

still in the FIFOs or the SRAM. This offers a worst case

suspend time of a maximum length packet over the

possibility of completely emptying the SRAM. Care

must be exercised in this mode, because the entire

memo ry subsyste m of the Am 79C972 co ntrolle r is sus-

pended. Any changes to e ither the descriptor rings or

the SRAM can cause the Am79C972 controller to start

up in an unknown c on dit ion and could c aus e d ata c or-

ruption.

When FASTSPNDE is 0 and the SPND bit is set, the

Am79C9 72 controller may take longe r before ente ring

the suspend mode. At the time the SPND bit is set, the

Am79C972 controller will complete the DMA process of

a transmit packet if it had already begun and the

Am79C 972 control ler wil l comple tely receive a receive

pack et if it had already begun. The Am79C972 control-

ler will not receive any new packets after the comple-

tion of the current reception. Additionally, all transmit

packets stored in the transmit FIFOs and the transmit

buff er area in the SRAM (if one is present) will be trans-

mitted, and all receive packets stored in the receive

FIFOs and the r eceive buffer area in the SR AM (if se-

lected) will be transferred into system memory. Since

the FIFO and the SRAM contents are flushed, it may

take much longer before the Am79C97 2 controller en-

ters the suspend mode. The amount of time that it

takes depends on many factors including the size of the

SRAM, bus latency, and network traffic level.

Upon completion of the described operations, the

Am79C972 controller sets the read-version of SPND to

1 and enters the suspe nd mode. In suspen d mode, all

of the CSR an d BCR r eg is ters ar e ac ce ssible. As lon g

as the Am79C972 controller is not reset while in sus-

pend mode (by H_RESET, S_RESET, or by setting the

STOP bit), no re-initialization of the device is required

after the device comes out of suspend mode. When

SPND is set to 0, the Am79C972 controller will leave

the suspend mode and will continue at the transmit and

receive descriptor ring locations where it was when it

entered the suspend mode.

See th e section on Magic Packet™ technol ogy fo r de-

tails on how t hat affects suspe nsion of t he Am7 9C972

controller.

Buffer Management

Buffer management is accomplished through message

descriptor entries organized as ring structures in mem-

ory . There are two descriptor rings, one for transmit and

one for receive. Each descriptor describes a single

buff er . A frame may occupy one or more buffers. If mul-

tiple buff ers are used, this is referred to as buff er chain-

ing.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of

memory. During initialization, the user-defined base

address for the transmit and receive descriptor rings,

as well as the number of entries contained in the de-

scri ptor rings a re set u p. The programmin g o f the s oft-

ware style (SWSTYLE, BCR20, bits 7-0) affects the

wa y the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the de-

scriptor rings are backwards compatible with the

Am79C90 C-LANCE and the Am79C96x PCnet-ISA

family. The descriptor ring base addresses must be

aligned t o an 8-byte boundar y and a maximum of 128

ring entries is allowed when the ring length is set

through th e TLEN and RLE N fields of the i nitializa tion

block. Each ring entry contains a subset of the three

32-bit transmit or receive message descriptors (TMD,

RMD) that are organized as four 16-bit structures

52 Am79C972

(SSIZE32 (BCR20, bit 8) is set to 0). Note that even

though the Am79C972 controller treats the descriptor

entries as 16-bit structures, it will always perf orm 32-bit

bus transfers to access the descriptor entries. The

v alue of CSR2, bits 15-8, is used as the upper 8-bits for

all memory addresses during bus master transf ers.

When SWSTYLE is set to 2 or 3, the descriptor ring

base addresses must be aligned to a 16-byte bound-

ary , and a maximum of 512 ring entries is allowed when

the ring length is set through the TLEN and RLEN fields

of the initializatio n block. Each r ing entr y is organi zed

as three 32-bit message descriptors (SSIZE32

(BCR20, bit 8) is set to 1). The fourth DWord is re-

served. When SWSTYLE is set to 3, the order of the

message descriptors is optimized to allow read and

write access in burst mode.

For any software style, the r i ng len gths can be set b e-

yond this range (up to 65535) by writing the transmit

and receive ring length registers (CSR76, CSR78) d i-

rectly.

Each ring entry contains the following information:

nThe address of the actual message data buffer in

user or host memory

nThe length of the message buffer

nStatus information indicating the condition of the

buffer

To permit the queuing and de-queuing of message

buffers, ownership of each buffer is allocated to either

the Am79C972 controller or the host. The OWN bit

within the descr iptor st atus infor mation, ei ther TMD or

RMD, is used for this purpose.

When OWN is set to 1, it sig nifies that the Am79C972

control ler currently ha s own ership of this ring descr ip-

tor and its a ssoc ia ted buffe r. O nly the owner i s permit-

ted to relinquish ownership or to write to any field in the

descr iptor en try. A device that is n ot the cu rrent owner

of a descriptor entry cannot assume ownership or

change any field in the entr y. A device may, however,

read from a descriptor that it does not currently own.

Software should always read descriptor entries in se-

quential order . When software finds that the current de-

scriptor is owned by the Am79C972 controller , then the

software must not read ahead to the next descriptor.

The software should wait at a descriptor it does not own

until the Am79C972 controller sets OWN to 0 to release

ownership to the so ftware. (When LAPPE N (CS R3, bit

5) is set to 1, this rule is modified. See the LAPPEN de-

scription. At initialization, the Am79C972 controller

reads the base address of both the transmit and re-

ceive descriptor rings into CSRs for use by the

Am79C972 controller during subsequent operations.

Figure 31 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

Am79C972 53

Figure 31. 16-Bit Software Model

Note that the value of C SR2, bits 1 5-8, is used as the

upper 8-bits f or all memory addresses during bus mas-

ter transfers.

Figure 32 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is set to 1.

Polling

If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity

being performed by the Am79C972 controller, then the

Am79C972 controller will periodically poll the current

receive and transmit descriptor entries in order to as-

certain their ownership. If the TXDPOLL bit in CSR4 is

set, then the transmit polling function is disabled.

A typica l polli ng operation c onsists of the following se-

quence. The Am79C9 72 cont roller will use the cu rrent

receive descriptor address stored internally to vector to

the appropriate Receive Descriptor Table Entry

(RDTE). It wil l then use the current tran smit de scr iptor

address (stored internally) to vector t o the a pprop r iate

Transmit Descriptor Table Entry (TDTE). The accesses

will be made in the f o llowing order: RMD1, then RMD0

of the current RDTE during one bus arbitration, and

after that, TMD1, then TMD0 of the current TDTE dur-

ing a second bus arbitration. All information collected

during polling activity will be stored internally in the ap-

propriate CSRs, if the OWN bit is set (i.e., CSR18,

CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,

CSR52).

A typical receiv e poll is the product of the f ollowing con-

ditions:

1. Am79C972 controller does not own the current

RDTE and the poll time has elapsed and

RXON = 1 (CSR0, bit 5), or

2. Am79C 972 con troller does no t own the next RDTE

and there is more than one receive descriptor in the

ring and the poll time has elapsed and RXON = 1.

Initialization

Block

IADR[15:0]IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLE RES RDRA[23:16]

TLE RES TDRA[23:16]

Rcv

Buffers

RMD RMD RMD RMD

Rcv Descriptor

Ring

NNNN

1st

desc. 2nd

desc.

RMD0

Xmt

Buffers

TMD TMD TMD TMD

Xmt Descriptor

Ring

MMMM

1st

desc. 2nd

desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

21485C-34

54 Am79C972

Figure 32. 32-Bit Software Model

If RXON is cleared to 0, the Am79C972 controller will

never poll RDTE locations.

In order to avoid missing frames, the system should

have at least one RDTE available. To minimize poll ac-

tivity, two RDTEs should be available. In this cas e, the

poll operation will only consist of the check of the status

of the current TDTE.

A typical transmit poll is the product of the following

conditions:

1. Am79C972 controller does not own the current

TDTE and TXDPOLL = 0 (CSR4, bit 12) and

TXON = 1 (CSR0, bit 4) and

the poll time has elapsed, or

2. Am79C972 controller does not own the current

TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been received, or

3. Am79C972 controller does not own the current

TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll. If the mi-

crocode is not executing the poll counting code when

the TDMD bit is set, then the demanded poll of the

TDTE will be delay ed until the microcode returns to the

poll counti ng co de.

The us er may change th e poll time val ue from the de-

fault of 65,536 clock per iods by modifyi ng the value i n

the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) ac-

cess, the A m79C972 c ontroller finds that the OWN bit

of that TDTE is not set, the Am79C972 controller re-

sumes the poll time count and re-examines the same

TDTE at the next expiration of the poll time count.

If the OWN bit of the TDTE is set, but the Start of

Packet (STP) bit is not set, the Am79C972 controller

will immediately request the bus in order to clear the

OWN bit of this descriptor. (This condition would nor-

mally be found following a late collision (LCOL) or retry

(RT RY) er ror that occur red in the m iddle of a transmit

frame chain of buffers.) Aft er resetting th e OWN bi t of

this desc ri ptor, the Am79 C972 con troll er will ag ain im-

Initialization

Block

CSR1CSR2

RMD RMD RMD RMD

Rcv Descriptor

Ring

NNNN

1st

desc.

start

2nd

desc.

start

RMD

TMD0 TMD1 TMD2 TMD3

Xmt Descriptor

Ring

MMMM

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16] IADR[15:0]

TLE

RES

RLE

RES

MODE

PADR[47:32]

RES LADRF[31:0

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

21485C-35

Am79C972 55

mediately request the bus in order to access the next

TDTE location in the r i ng .

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. In the C-LANCE device, the buffer

length of 0 is int er pret ed as a 409 6-byte buffer. A zero

length buffer is acceptable as l ong as i t is not the last

buffer in a chain (STP = 0 and ENP = 1).

If the O WN bit and STP are set, then microcode control

proceeds to a routine that will enable transmit data

transfers to the FIFO. The Am79C972 controller will

look ahead to the next transmit descriptor after it has

performe d at least one transm it data transfe r from the

first buffer.

If the Am79C972 controller does not own the next

TDTE (i.e., the second TDTE for this frame), it will com-

plete transm is sion of the cur rent buffer a nd upd ate the

status of the current (first) TDTE with the BUFF and

UFLO bits being set. If DXSUFLO (CSR3, bit 6) is

cleared to 0, the underflow error will cause the transmit-

ter to be disabled (CSR0, TXON = 0). The Am79C972

controller will have to be re-initialized to restore the

transmit function. Setting DXSUFLO to 1 enables the

Am79C972 controller to gracefully recover from an un-

derflow error . The de vice will scan the transmit descrip-

tor ring until it finds either the start of a new frame or a

TDTE it does not own. To avoid an un derfl ow situatio n

in a chained buffer transmission, the system should al-

ways set the transmit chain descriptor own bits in re-

verse order.

If the Am79C972 controller does own the second TDTE

in a chain, it will gradually empty the contents of the first

buffer (a s the bytes are needed by the transmit op era-

tion), perform a single-cycle DMA transfer to update the

status of the first descriptor (clear the OWN bit in

TMD1), and then it may perform one data DMA access

on the se co nd buffe r in the ch ain before executi ng an-

other lookahead operation. (i.e., a lookahead to the

third descriptor.)

It is imperative that the host system never reads the

TDTE OWN bits out of order . The Am79C972 controller

normally clears OWN bits in strict FIFO order. However ,

the Am79 C972 con troller can queue u p to two frames

in the transmit FIFO. When the second frame uses

buffer c haining, t he Am79C9 72 controll er might r etur n

ownership out of nor mal FIFO order. The OWN bit for

last (and maybe only) buffer of the first frame is not

cleared until transmission is completed. During the

transmission the Am79C972 controller will read in buff-

ers for the next frame and clear their OWN bits for all

but the last one. The first and all intermediate buffers of

the se co n d fr a m e ca n have th ei r OWN bits cle a r ed be -

f ore the Am79C972 controller returns ownership f or the

last buff er of the first frame.

If an error occurs in the transmission before all of the

bytes of the current buff er have been transf erred, trans-

mit sta tus of th e current buffer wil l be im mediately up-

dated. If the buffer doe s not c on tain the end of packet,

the Am79C972 controller will skip over the rest of the

frame whic h experien ce d t he error. T his i s do ne by re-

tur ning to the polling mi crocod e where the Am79C97 2

controlle r will clea r the OW N bit for all descrip tors wit h

O WN = 1 and STP = 0 and continue in like manner until

a descriptor with OWN = 0 (no more transmit frames in

the ri ng) or OWN = 1 and STP = 1 (t he first buffer o f a

new frame) is reached.

At the end of any transmit operation, whether success-

ful or with err ors, imme dia tel y following the com ple tio n

of the descriptor updates, the Am79C972 controller will

always perform another polling operation. As described

earl ier, th is pollin g operation will be gin with a check of

the current RDTE, unless the Am79C972 controller al-

ready owns tha t descripto r. Then the Am79C972 con-

troller will poll the next TDTE. If the transmit descriptor

OWN bit has a 0 value, the Am79C972 controller will

resume incrementing the poll time counter . If the trans-

mit descriptor OWN bit has a value of 1, the Am79C972

controller will begin filling the FIFO with transmit data

and initiate a transmission. This end-of-operation poll

coupled with the TDTE lookahead operation allows the

Am79C972 controller to avoid inserting poll time counts

between successive transmit frames.

By default, whenever the Am79C972 controller com-

pletes a transmit frame (either with or without error) and

writes the status information to the current de scriptor,

then the TINT bit of CSR0 is set to indicate the comple-

tion of a transmission. This causes an interrupt signal if

the IENA bit of CSR0 has been set a nd the TINTM bit

of CSR3 is cleared. The Am79C972 controller provides

two modes to reduce the number of transmit interrupts.

The interrupt of a successfully transmitted frame can

be suppressed by setting TINTOKD (CSR5, bit 15) to

1. Another mode, which is enabled by setting LTINTEN

(CSR5, bit 14) to 1, allows suppression of interrupts for

succes sful transmiss ions for al l but the l ast frame in a

sequence.

Receive Descriptor Table Entry

If the Am79C972 controller does not own both the cur-

rent and the next Receive Descriptor Table Entry

(RDTE), then the Am79C972 controller will continue to

poll according to the polling sequence described

above. If the receive descriptor ring length is one, then

there is no next descriptor to be polled.

If a poll operation has re vealed that the current and the

next RDTE belong to the Am79C972 controller, then

additional poll accesses are not necessary. Future poll

operations wil l not inc lude RDTE acce sses as lon g as

the Am79C97 2 control ler r eta ins owne rshi p of the cur-

rent and the next RDTE.

When receive activity is present on the channel, the

Am79C972 controller waits for the complete address of

56 Am79C972

the message to arrive. It then decides whether to ac-

cept or reject the frame based on all active addressing

schemes. If the frame is accepted, the Am79C972 con-

troller c hecks the current receive buffer s tatus regis ter

CRST (CSR41) to determine the ownership of the cur-

rent buffer.

If ownership is lacking, the Am79C972 controller will

immediately perf orm a final poll of the current RDTE. If

ownership is still denied, the Am79C972 controller has

no buffer in which to store the incoming message. The

MISS bit will be set in CSR0 and the Missed Frame

Counter (CSR112) will be incremented. Another poll of

the current RDTE will not occur until the frame has fin-

ished.

If the Am79C972 controller sees that the last poll (ei-

ther a normal poll, or the final effor t described in the

above paragraph) of the current RDTE shows valid

ownership, it proceeds to a pol l o f the n ext RDTE. Fol-

lowing this poll, and regardless of the outcome of this

poll, transfers of receive data from the FIFO may begin.

Regardless of ownership of the second receive de-

scr iptor, the A m79C972 co ntroller will continue to per -

f orm receive data DMA transfers to the first buffer . If the

frame length exceeds the l ength of the first buffer, and

the Am79C972 controller does not own the second

buffer, ownership of the current descriptor will be

passed b ack to the system by wr iting a 0 to the OWN

bit of RMD1. Status will be written indicating buffer

(BUFF = 1) and possibly overflow (OFLO = 1) errors.

If the frame length exce eds the lengt h of the first (cur-

rent) buffer, and the Am79C972 controller does own

the second (next) buffer, ownership will be passed back

to the system by writing a 0 to the OWN bit of RMD1

when the fir st buffer is full. The OWN bit is th e only bit

modi fied in the desc riptor . Receiv e dat a tran sf ers to t he

second buffer may occur before the Am79C972 con-

troller pr oceeds to loo k ahead to the owne rship of the

third buffer. Such action will depend up on the state of

the FIFO when the OWN bit has been updated in the

first descriptor. In any case, lookahead will be per-

formed to the third buffer and the inf ormation gathered

will be s tored in the chi p, regardless o f the state of the

ownership bit.

This activity continues until the Am79C972 controller

recognizes the completion of the frame (the last byte of

this receive message has been removed from the

FIFO). The Am79C972 controller will subsequently up-

date the current RDTE status with the end of frame

(ENP) indication set, write the message byte count

(MCNT) for the enti re frame into RM D2, and over writ e

the “current” entries in the CSRs with the “next” entries.

Receive Frame Queuing

The A m79 C972 c on troll er s up ports the lack o f R DT Es

when SRAM (SRAM SIZE in BCR 25, bits 7-0) is en-

abled through the Receive Frame Queuing mecha-

nism. When the SRAM SIZE = 0, then the Am79C972

controller reverts back to the PCnet PCI II mode of op-

eration. This operation is automatic and does not re-

quire any programming by the host. When SRAM is

enabled, the Receive Frame Queuing mechanism

allows a slow protocol to manage more frames without

the high frame loss rate normally attributed to FIFO

based network controllers.

The Am79C972 controller will store the incoming

frames in the extended FIFOs until polling takes place;

if enabled, it discovers it owns an RDTE. The stored

frames are n ot altered i n any way un til wri tten out int o

system buffers. When the r eceive FIFO overflows, fur-

ther incoming receiv e frames will be missed during that

time. As soon as the network receive FIFO is empty, in-

coming frames are processed as nor mal. Status on a

per frame basi s is not kept during t he ov erfl ow pr ocess .

Statistic counters are maintained and accurate during

that time.

During the time that the Receive F rame Queuing mech-

anism is in operation, the Am79C972 controller relies

on the Recei ve Poll Time Counter (CSR 48) to control

the worst cas e access to the RDTE. The Re ceive Poll

Time Counter is programmed through the Receive P oll-

ing Interval (CSR49) register. The Received Polling In-

ter val defaults to approximately 2 ms. The Am7 9C972

controlle r will also tr y to access the RDT E during nor-

mal descriptor accesses whether they are transmit or

receive accesses. The host can force the Am79C972

controller to immediately access the RDTE by setting

the RDMD (CSR 7, bit 13) to 1. Its operation is similar

to the transmit one. The polling process can be dis-

abled by setting the RXDPOLL (CSR7, bit 12) bit. This

will stop the automatic polling process and the host

must set the RDMD bit to initiate the receive process

into host memory. Receive frames are still stored even

when the rece ive polling process is disabled.

Software Interrupt Timer

The Am79C9 72 controller is equi pped with a software

programmable free-running interrupt timer . The timer is

constantly running and will generate an interrupt STINT

(CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to

1. After generating the interrupt, the software timer will

load t he value s tored in STVAL a nd restar t. The timer

value STVAL (BCR31, bits 15-0) is interpreted as an

unsigned number with a resolution of 256 Time Base

Clock periods. For instance, a value of 122 ms would

be programmed with a value of 9531 (253Bh), if the

Time Base Clock is running at 20 MHz. The default

v alue of STVAL is FFFFh which yields th e appro x imate

maximum 8 38 ms tim er du ration. A write to STVA L re -

starts the timer with the new contents of STVAL.

Am79C972 57

Media Access Control

The Medi a Ac ce ss Con tr ol ( MAC) engin e in corpo rates

the essen tial pro toc ol requi re men ts for operation of a n

Etherne t/IE EE 80 2.3-c om pli ant no de and pr ovid es the

interface between the FIFO subsystem and the MII.

This section describes operation of the MAC engine

when operating in half-duplex mode. When operating in

half-duplex mode, the MAC engine is fully compliant to

Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard

1990 Second Edition) and ANSI/IEEE 802.3 (1985).

When operating in full-duplex mode, the MAC engine

behavior changes as described in the section Full-

Duplex Op eration .

The MAC engine provides programmable enhanced

features designed to minimize host supervision, bus

utilization, and pre- or post-message processing.

These features include the ability to disable retries after

a collision, dynamic FCS generation on a frame-by-

frame basis, autom ati c p ad fi el d ins ertion and de le tio n

to enforce minimum frame size attributes, automatic re-

transmission without reloading the FIFO, and auto-

matic deletion of collision fragments.

The two primary attributes of the MAC engine are:

nTransmit and receiv e message data encapsulation

—Framing (frame boundary delimitation, frame

synchronization)

—Addressing (source and destination address

handling)

—Error detection (physical medium transmission

errors)

nMedia access management

—Medium allocation (collision avoidance, except

in full-duplex operation)

—Contention resolution (collision handling, except

in full-duplex operation)

T ransmit and Receive Message Data Encapsulation

The MAC engine provides minimum frame size en-

forcement for transmit and receive frames. When

APAD_XMT (CSR, bit 11) is set to 1, transmit mes-

sages will be padded with sufficient bytes (containing

00h) to ensure that the receiving station will observe an

informati on fie ld ( des tin ati on add ress, sou rc e add re ss,

length/type, data, and FCS) of 64 bytes. When

ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will

automatically strip pad bytes from the received mes-

sage by obser ving th e value in the length field and by

stripping excess bytes if this value is below the mini-

mum data size (46 bytes). Both features can be inde-

pendently over-ridden to allow illegally short (less than

64 bytes of frame data) messages to be transmitted

and/or received. The use of this feature reduces bus

utilization because the pad bytes are not transferred

into or out of main memory.

Framing

The MAC engine will autonomously handle the con-

struction of the transmit frame. Once the transmit FIFO

has been fi lled to the predet ermi ned threshold (se t by

XMTSP in CSR80) and access to the channel is cur-

rently permitted, the MAC engine will commence the 7-

byte preamble sequence (10101010b, where first bit

transmitte d is a 1). The MAC engine will subs equen tly

append the Start Frame Delimiter (SFD) byte

(10101011b) followed by the serialized data from the

transmit FIFO . Once the data has been completed, the

MAC engine will append the FCS (most significant bit

first) which was computed on the entire data portion of

the frame. The data portion of the frame consists of

destination address, source address, length/ type, and

frame data. Th e user is respo nsible fo r the correct or-

dering and content in each of these fields in the frame.

The MAC does not use the content in the length/type

field unless APAD_XMT (CSR4, bit 11) is set and the

data portion of the frame is shorter than 60 bytes.

During GPSI operation, the MAC will discard the first 8

bits of information before searching for the SFD se-

quence. Once the SFD is detected, all subsequent bits

are treated a s par t of the frame. Durin g MII operation,

the MAC engine wi ll d etect the i nc omi ng prea mble s e-

quence whe n the RX _DV signal i s acti vated by the ex-

ternal PHY. The MAC will discard the preamble and

begin searching for the SFD except in the case of

100BASE-T4. In that case, the SFD will be the first nib-

ble across the MII interface. Once the SFD is detected,

all subsequent nibbles are treated as part of the frame.

The MAC engine will ins pect the le ngth field to ens ure

minimum frame size , strip unnecessary pad characters

(if enabled), and pas s th e rema ini ng bytes throu gh th e

receive FIFO to the host. If pad strippi ng is perfor med ,

the MAC engine will also strip the received FCS bytes,

although normal FCS computation and checking will

occur . Note that apart from pad stripping, the frame will

be passed unmodified to the host. If the length field has

a value of 46 or great er, all frame bytes includi ng FCS

will be passed unmodified to the receive buff er, regard-

less of the actual frame length.

If the frame ter mina tes or suffers a colli sion before 64

bytes of infor mation (after SFD) have been received,

the MAC engine will automatically delete the frame

from the receive FIFO, without host intervention. The

Am79C972 controller has the ability to accept runt

packets for diagnostic purposes and proprietary net-

works.

Destination Address Handling

The firs t 6 bytes of info rmati on after SFD will be inter-

preted as the destination address field. The MAC en-

58 Am79C972

gine provides facilities for physical (unicast), logical

(multicast), and broadcast address reception.

Error Detection

The MAC engine provides several facilities which re-

port and recover from errors on the medium. In addi-

tion, it protects the network from gross errors due to

inabili ty of t he hos t to keep pac e with the MAC engin e

activity.

On completion of transmission, the following transmit

status is av ailable in the appropriate Transmit Message

Descriptor (TMD) and Control and Status Register

(CSR) areas:

nThe number of transmission retry attempts (ONE,

MORE, RT RY, and TRC).

nWhether the MA C engine had to Defer (DEF) due to

chann el activ it y.

nExcessive deferral (EXDEF), indicating that the

transmitter experienced Excessive Deferral on this

transmit frame, where Excessive Deferral is defined

in the ISO 8802-3 (IEEE/ANSI 802.3) standard.

nLoss of Carrier (LCAR), indicating that there was an

interruption in the ability of the MA C engine to mon-

itor its ow n tran smissi on. Rep eated LC AR erro rs in-

dicate a potentially faulty transceiver or network

connection.

nLate Collision (LCOL) indicates that the transmis-

sion suffered a collision after the slot time. This is in-

dicative of a badly configured network. Late

collisions should not occur in a normal operating

network.

nCollision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the first 4 µs after a transmission was com-

pleted. T his may be due to a failed transce iver, dis-

connected or faulty transceiver drop cable, or

because the transceiver does not suppor t this fea-

ture (or it is disabled). SQE Test is only valid for 10-

Mbps network s.

In addition to the reporting of network errors, the MAC

engine will also atte mpt to prevent the creation of any

network error due to the inabi lity o f the hos t to se r vic e

the MAC engine. During transmission, if the host fails

to keep the transmi t F IFO f illed s uffi ci en tly, causin g a n

underflow , the MAC engine will guarantee the message

is either sent as a runt packet (which will be deleted by

the receiving station) or as an invalid FCS (which will

also cause the receiver to reject the message).

The statu s of eac h re ce ive message is available in the

appropriate Receive Message Descriptor (RMD) and

CSR areas. All received frames are passed to the host

regardless of any error . The FRAM error will only be re-

por ted if an FCS error i s detected and there is a no n-

integral number of bytes in the message.

During the reception, the FCS is generated on every

nibble (including the dribbling bits) coming from the ca-

ble, although the internally saved FCS value is only up-

dated on the eighth bit (on each byte boundary). The

MAC engine will ignore up to 7 additional bits at the end

of a message (dribbling bits), which can occur under

normal network operating conditions. The framing error

is reported to the user as follows:

nIf the number of dribbling bits are 1 to 7 and there is

no FCS error , then there is no F raming error (FRAM

= 0).

nIf the number of dribbling bits are 1 to 7 and there is

a FCS error, then there is also a Framing error

(FRAM = 1).

nIf the number of dr ibblin g bits is 0 , then th ere is no

Framing er ror. T here may or may not be a FCS er-

ror.

nIf the number of dribbling bits is EIG HT, then there

is no Fram ing er ror. F CS err or wil l be rep orted and

the receive message count will indicate one extra

byte.

Media Access Management

The basic requirement f or all stations on the network is

to provide fairness of channel allocation. The IEEE

802.3/Ethernet protocols define a media access mech-

anism which permits all stations to access the channel

with equ ality. Any node can atte mpt to conten d for the

channel by waiting for a predetermined time (Inter

Packet Gap) after the last activity, before transmitting

on the media. T he channel is a multidrop com munica-

tions media (with various topological configurations

permitted), which allows a single station to transmit and

all other stations to receive. If two nodes simulta-

neously contend for the channel, their signals will inter-

act causing loss of data, defined as a collision. It is the

responsibility of the MAC to attempt to avoid and

recover from a coll isio n, to guaran tee data i ntegr ity for

the end-to-end transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)

requires th at the CSMA/CD MAC mo nitor the medium

for traffic b y watching for carrier activity. When carrier is

detected, the media i s considere d bus y, and th e MAC

should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also al-

lows optiona lly a two -p art defer ral after a recei ve mes-

sage.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: It is possible f or the PLS carrier sense indication

to fail to be asserted durin g a co lli s ion on the me di a. If

the deference process simply times the inter-Frame

gap based on this indication, it is possible f or a short in-

terFrame gap to be generated, leading to a potential

Am79C972 59

reception failure of a subsequent frame. To enhance

system robustness, the following optional measures,

as specified in 4.2.8, are recommended when Inter-

Frame-SpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap, as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset the inter-frame gap timing if carrier sense be-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer shal l not be re set to ens ure fa ir acces s to

the medium. An initial period shorter than 2/3 of the

interval is permissible including 0.

The MAC engine impleme nts the optional receive two

part deferral algorithm, with an InterFrameSpacing-

Par t 1 time of 6.0 µs. The In terFrameSp acingPart 2 in-

terval is, therefore, 3.4 µs.

The Am79C972 controller will perform the two-part

deferral algorithm as specified in Section 4.2.8 (Pro-

cess Deference). The Inter Packet Gap (IPG) timer will

star t timi ng the 9.6 µs InterFrameS pacing a fter th e re-

ceive carrier is deasserted. During the first part def erral

(InterFrameS pac i ngPar t1 - IFS1) , the Am7 9C97 2 co n-

troller will defer any pending transmit frame and re-

spond to the receive message. The IPG counter will be

cleared to 0 continuously until the carrier deasserts, at

which point the IPG counter will resume the 9.6 µs

count once again. Once the IFS1 period of 6.0 µs has

elapsed, the Am79C972 controller will begin timing the

second par t deferral (InterFrameSpacingPart2 - IFS2)

of 3.4 µs. Once IFS1 has completed and IFS2 has com-

menced, the Am79C972 controller will not defer to a re-

ceive frame if a transmit frame is pending. This means

that the Am79C972 controller will not attempt to receive

the receive frame, since it will start to transmit and gen-

erate a collision at 9.6 µs. The Am79C972 controller

will complete the preamble (64-bit) and jam (32-bit) se-

quence before ceasing transmission and invoking the

random backoff algorithm.

The Am79C972 controller allows the user to program

the IPG and the first part deferral (InterFrame-

SpacingPart1 - IFS1) through CSR125. By changing

the IPG default v alue of 96 bit times (60h), the user can

adjust the fairness or aggressiveness of the

Am79C972 MAC on the network. By programming a

lower number of bit times than the ISO/IEC 8802-3

standard requires, the Am79C972 MAC engine will be-

come more aggressive on the network. This aggressive

nature wi ll gi ve ris e t o th e A m79 C972 c ontrol le r pos s i-

bly capturin g t he net work at times by forcing other less

aggressive comp liant nodes to d efer. B y programm ing

a larg er number of b it times, the Am79C972 MAC will

become less aggressive on the network and may def er

more often than normal. The performance of the

Am79C972 controller may d ecrease as the IPG value

is increased from the default value, but the resulting be-

havior may improve ne twor k performance by re ducing

collisions. The Am79C972 controller uses the same

IPG for back- to-back transmits and receive-to-transmit

accesses. Changing IFS1 will alter the period for which

the Am79C972 MAC engine will defer to incoming re-

ceive frames.

CAUTION: Care must be exercised when altering

these parameters. Adverse network activity could

result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disabled using the

DXMT2PD bit in CSR3. The IFS1 programming will

have no effect when DXMT2PD is set to 1, but the IPG

programming value is stil l valid. Two p art d eferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver should

generate the SQE Test message within 0.6 to 1.6 µs

after the transmission ceases. During the time period in

which the SQE Test message is expected, the

Am79C972 controller will not respond to receive carrier

sense.

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the co nclusion o f the output fu nction, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when

the CARRIER_STATUS becomes

CARRIER_OFF. If execution of the output function

does not cause CARRIER_ON to occur, no SQE

test occurs in the DTE. The duration of the window

shall be at least 4.0 µs but no more than 8.0 µs.

During the time window the Carrier Sense Function

is inhibited.”

The Am79C972 controller implements a carrie r sense

“blinding” period of 4.0 µs length starting from the

deassertion of carrier sense after transmission. This ef-

fectively means tha t w hen tran smit two part deferral is

enabled (DXM T2PD is cle ared), the IFS 1 time is fro m

4 µs to 6 µs after a transmission. However, since IPG

shrinkage below 4 µs will rarely be encountered on a

correctly configured network, and since the fragment

size will be larger than the 4 µs blinding window, the

IPG counter will be reset by a worst case IPG shrink-

age/fragment scenario and the Am79C972 controller

will defer its transmission. If carrier is detected within

the 4.0 to 6.0 µs IFS1 perio d, t he Am79C 972 co ntro lle r

will not restart the “blinding” period, but only restart

IFS1.

60 Am79C972

Collision Handling

Collision detection is performed and reported to the

MAC engine via the COL/CLSN input pin.

If a collision is detected before the complete preamble/

SFD seq uen ce has bee n transmitted, the MAC engine

will comple te the pream bl e/SFD before appending th e

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits

being transmitted, the MA C engine will abort the trans-

mission and append the jam sequence immediately.

The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retr ies) due to nor-

mal coll isions (those wit hin the s lot time) . Detecti on of

collis io n wil l c aus e the trans mi ssio n to be r es ch edu le d

to a time determ ine d by the rando m ba ckoff algorithm .

If a single retry w as required, the 1 bit will be set in the

transmit frame status. If more than one retry was re-

quired, the M ORE bit will be set. If all 16 atte mpts ex-

perienced collisions, the RTRY bit will be set (1 and

MORE will be cl ear) , and the transmi t mes sage wi ll be

flushed from the FIFO. If retries have been disabled by

setting the DRTY bit in CSR15, the MAC engine will

abandon tra ns mis sion of the fram e on de tec tio n o f th e

first collision. In this case, only the RTRY bit will be set

and the transmit message will be flushed from the

FIFO.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MAC engine will abor t the transmission, append the

jam se quence, and se t the LCOL bit. No r etr y attemp t

will be scheduled on detection of a late collision, and

the transmit message will be flushed from the FIFO.

The ISO 8802- 3 ( IEE E/ ANS I 802 .3) Stan dar d r equ ires

use of a “truncated binary exponential backoff” algo-

rithm, which provides a controlled pseudo random

mechanism to enforce the collision backoff interval,

before retransmission is attempte d.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the

CSMA /CD su blayer delays before attemp ting t o re-

transmit the frame. The delay is an integer multiple

of slot time. The number of slo t times to delay be-

fore the nth retransmission attempt is chosen as a

uniformly distributed random integer r in the range:

0 ≤ r < 2k where k = min (n,10).”

The Am79C972 controller provides an alternativ e algo-

rithm, which suspends the counting of the slot time/IPG

during the time that receive carrier se nse is detected.

This aids in networks where large numbers of nodes

are present, and numerous nodes can be in collision. It

effectively accelerate s the in crea se in the backoff time

in busy networ ks and allow s nodes not involved in the

collision to access the channel, while the colliding

nodes await a reduction in channel activity. Once chan-

nel activity is reduced, the nodes resolving the collision

time-out their slot time counters as normal.

This modified backoff algorithm is enabled when EMBA

(CSR3, bit 3) is set to 1.

Transmit Operation

The transm it operat ion and features of the Am79C97 2

cont roll er are c ontro lled b y prog ramm ab le opti ons . The

Am79C972 controller offers a large transmit FIFO to

provide frame buffering for increased system latency,

automatic retransmission with no FIFO reload, and au-

tomatic transmit padding.

Transmit Function Programming

Auto matic transmit features such as retr y on collision,

FCS generation/transmission, and pad field insertion

can all be programme d to pr ovide flexibility in the (r e-)

transmis si on of mes sa ges.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

Automatic pad field insertion is controlled by the

APAD_XMT bit in CSR4.

The disable FCS generation/transmission feature can

be programmed as a static feature or dynamically on a

frame-by-frame basis.

Transmit FIFO W atermark (XMTFW) in CSR80 sets the

point at which the BMU requests more data from the

transmit buffers for the FIFO. A minimum of XMTFW

empty spaces must be available in the transmit FIFO

before the BMU will request the system bus in order to

transfer transmit frame data into the transmit FIFO.

Transmit S tart Poin t (XM T SP ) in CS R80 s ets th e p oin t

when the transmitter actually attempts to transmit a

frame onto the media. A minimum of XMTSP bytes

must be written to the transmit FIFO for the current

frame before transmis si on of th e c urr ent frame wil l be-

gin. (When automatically padded packets are being

sent, it is conceivable that the XMTSP is not reached

when all of th e data has been tra nsferred to the F IFO.

In this case, the transmission will begin when all of the

frame data has been placed into the transmit FIFO.)

The default v alue of XMTSP is 01b, meaning there has

to be 64 bytes in the transmit FIFO to start a transmis-

sion.

Automatic Pad Generation

Transmit frames can be automatically padded to extend

them to 64 data bytes (excluding preamble). This al-

lows the min imum frame s ize o f 64 bytes (5 12 bit s) for

IEEE 802.3/Ethernet to be guaranteed with no software

inter vention from the host/controlling process. Setting

the APAD_XMT bit in CSR4 enables the automatic

Am79C972 61

padding feature. The pad is placed between the LLC

data field and FCS field in th e IEEE 802.3 frame. FCS

is always added if the frame is padded, regardless of

the state of DXMTFCS (CSR15, bit 3) or ADD_FCS

(TMD1, bit 29). The transmit frame will be padded by

bytes with the value of 00H. The default value of

APAD_XMT is 0, which will disable automatic pad gen-

eration after H_RESET.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC

Data bytes encapsulated in the frame (length field as

defined in the ISO 8802-3 (IEEE/ANSI 802.3) stan-

dard). The length value contained in the message is not

used by the Am79C972 controller to compute the ac-

tual number of pad bytes to be inserted. The

Am79C972 controller will append pad bytes dependent

on the actual number of bits transmitted onto the net-

work. Once the last data byte of the frame has com-

pleted, prior to appending the FCS, the Am79C972

controlle r will check to ensure that 544 bi ts have been

transmitted. If not, pad bytes are added to extend the

frame size to this value, and the FCS is then added.

See Figure 33.

Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble/SFD,

including FCS) 64 bytes 512 bits

Preamb le/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble/SFD + (Min Frame Size - FCS)

64 + (512-32) = 544 bits

A minimum len gth transmit fram e from the Am79C97 2

controller, therefore, will be 576 bits, after the FCS is

appended.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(CSR15, bit 3). If DXMTFCS is cleared to 0, the trans-

mitter will generate and appe nd the FCS to the trans-

mitted frame. If the automatic padding feature is

invoked (APAD_XMT is set in CSR4), the FCS will be

appended to frames shorter than 64 bytes by the

Am79C972 controller regardless of the state of DXMT-

FCS or ADD_FCS (TMD1, bit 29). Note that the calcu-

lated FCS is transmitted most significant bit first. The

default value of DXMTFCS is 0 after H_RESET.

ADD_FCS (TMD1, b it 29) allows the au tomatic gener-

ation and transmission of FCS on a frame-by-frame

basis. DXMTFCS should be set to 1 in this mode. To

generate FCS for a frame, ADD_FCS must be set in all

descriptors of a frame (STP is set to 1). Note that bit 29

of TMD1 has the function of ADD_FCS if SWSTYLE

(BCR20, bits 7-0) is programmed to 0, 2, or 3.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distinct categories: those conditions which are the

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal ev ents which may occur and which are handled

autonomously by the Am79C972 controller include col-

lisions within the slot time with automatic retry. The

Am79C972 controller will ensure that collisions which

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with

no host intervention. The transmit FIFO ensures this by

guaranteeing that data contained within the FIFO will

not be overwritten until at least 64 bytes (512 bits) of

preamble plus address, length, and data fields have

been transmitted ont o the network without encounter-

ing a co llisio n. Note that i f DRTY (CSR15, bi t 5) is se t

to 1 or if the network interface is operating in full-duplex

mode, no collision handling is required, and any byte of

Preamble

1010....1010 SFD

10101011 Destination

Address Source

Address Length LLC

Data Pad FCS

Bytes

46 — 1500

Bytes

Bits

21485C-36

62 Am79C972

frame data in the FIFO can be overwritten as soon as it

is transmitted.

If 16 total attempts (initial attempt plus 15 retries) fail,

the Am79C97 2 contr oller s ets the RTRY bit in the cur-

rent transmit TDTE in host memory (TMD2), gives up

ownership (resets the OWN bit to 0) f or this frame, and

processe s the next frame in the transmit r ing for trans-

mission.

Abnormal network conditions include:

nLoss of carrier

nLate collision

nSQE Test Error (Does not apply to 100-Mbps net-

works.)

These conditio ns should not occ ur on a correctl y con-

figured IEEE 802.3 network operating in half-duplex

mode. If they do, they will be repor ted. None of these

conditions will occur on a network operating in full-

duplex mode. (See the section Full-Duplex Operation

for more deta il .)

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the

current descriptor. The OWN bit(s) in the subsequent

descriptor(s) will be cleared until the STP (the next

frame) is found.

Loss of Carrier

When operating in half-duplex mode, a loss of carrier

condition will be reported if the Am79C972 controller

cannot observe receive activity while it is transmitting

on the GPSI port.

When the MII por t is selected, LCAR will be repor ted

for every frame transmitted if the controller detects a

loss of carrier.

Late Collision

A late collision will be repor ted if a collision condition

occurs after one slot time (512 bit times) after the trans-

mit process was initiated (first bit of preamble com-

menced). The Am79C972 controller will abandon the

transmit process for that frame, set Late Collision

(LCOL) i n t he as soci ated T MD 2, a nd pr oc ess the next

transmit frame in the ring . Frames exper iencing a lat e

collision will not be retried. Recover y from this condi-

tion must be performed by upper layer software.

SQE Test Error

In GPSI mode, CLSN must be asserted after the trans-

mission or otherwise CERR will be set. CERR will be

asser ted i n t he 10BASE-T mode thr ough the MII after

transmit, if the network port is in Link Fail sta te. CERR

will never cause INTA to b e activated. It wil l, however,

set the ERR bit CSR0.

Receive Opera tio n

The receive operation and features of the Am79C972

cont roll er are c ontro lled b y prog ramm ab le opti ons . The

Am79C972 controller offers a large receive FIFO to

provide frame buffering for increased system latency,

automatic flushing of collision fragments (runt packets),

automatic receive pad stripping, and a variety of ad-

dress match options.

Receive Function Programming

Auto matic pad field str ipping is enabled by setting the

ASTRP_RCV bit in CSR4. This can provide fle xibility in

the reception of messages using the IEEE 802.3 frame

format.

All receive frames can be accepted by setting the

PROM bit in CSR15. Acceptance of unicast and broad-

cast frames can be individually turned off by setting the

DRCVPA or DRCVBC bits in CSR15. The Ph ysical Ad-

dress register (CSR12 to CSR14) stores the address

that the Am79C972 controller compares to the destina-

tion address of the incoming frame for a unicast ad-

dress match. The Logical Address Filter register

(CSR8 to CS R11) ser ves as a hash filter for multicast

address match.

The point at which the BMU will star t to transfer data

from the receive FIFO to buffer memory is controlled by

the RCVFW bits in CSR80. The default established

during H_RESET is 01b , which sets the watermark flag

at 64 bytes filled.

For test purposes, the Am79C972 controller can be

programmed to a ccept runt packets by setting RPA in

CSR124.

Address Matching

The Am79C972 controller suppor ts three types of ad-

dress matching: unicast, multicast, and broadcast. The

normal address matching procedure can be modified

by programming three bits in CSR15, the mode register

(PRO M, DRCVPA, and DRCVBC).

If the first bit received after the SFD (the least signifi-

cant bit of the first byte of the destination address field)

is 0, the frame is unicast, which indicates that the frame

is meant to b e r ec ei ved by a single nod e. If the firs t bi t

received is 1, the frame is multicast, which indicates

that the frame is meant to be received by a group of

nodes. If the destination address field contains all 1s,

the frame is broadcast, which is a special type of multi-

cast. Frames with the broadcast address in the destina-

tion address field are meant to be received by all nodes

on the local area networ k .

When a unicast frame arr ives at the Am79C972 con-

troller , the controller will accept the frame if the destina-

tion address field of the incoming frame exactly

matches the 6-byte station address stored in the Phys-

ical Ad dress reg isters (PADR, CS R12 to CS R14). Th e

Am79C972 63

byte ordering is such that the first byte received from

the network (after the SFD) must match the least signif-

icant byte of CSR12 (PADR[7:0]), and the sixth byte re-

ceived must matc h th e mo st si gni fica n t byte of C SR1 4

(PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1, the

Am79C972 controller will not accept unicast frames.

If the incoming frame is multicast, the Am79C972 con-

troller performs a calculation on the contents of the

destination address field to determine whether or not to

accept the frame. This calculation is explained in the

section that describes the Logical Address Filter

(LADRF).

When all bits of the LADRF registers are 0, no multicast

frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special

multicast frames, they are treated differently by the

Am79C972 contr ol le r har dware. B roadc as t f rames a r e

always accepted, except when DRCVBC (CSR15, bit

14) is set and there is no Logical Address match.

None of the address filtering described above applies

when the Am 79C 972 c ontro ll er is operati ng in the pro-

miscuous mode. In the promiscuous mode, all properly

formed packets are received, regardless of the con-

tents of their destination address fields. The promiscu-

ous mode overrides the Disable Receive Broadcast bit

(DRCVBC bit l4 in the MODE register) and the Disable

Receive Physical Address bit (DRCVPA, CSR15, bit

13).

The Am79C972 controller operates in promiscuous

mode when PROM (CSR15, bit 15) is set.

In addition, the A m79C972 controlle r pr ovide s the Ex-

ter nal Address Detec tion Interface (EADI) to allow ex -

ternal address filtering. See the section External

Address Detection Interface for further detail.

The recei ve descr ipt or entry RMD1 contain s t hree bits

that indicate which method of address matching

caused t he Am79C972 c ontroller to a ccept the frame.

Note that these indicator bits are only available when

the Am79C97 2 control ler is programmed to use 32-bit

structures for the descriptor entries (BCR20, bit 7-0,

SWSTYLE is set to 2 or 3).

PAM (RMD1, bit 22) is set by the Am79C972 controller

when it accepted the received frame due to a match of

the frame’s de sti na tion add re ss with the conten t of th e

physical address register.

LAFM (RM D1, bi t 21) is se t by the Am79C972 cont ro l-

ler when it accepted the received frame based on the

value in the logical address filter register.

BAM (RMD1, bit 20) is set by the Am79C972 controller

when it accepted the received frame because the

frame’s destination address is of the type ’Broadcast’.

If DRCVBC (CSR15 , b it 14) i s c lea red t o 0 , on ly B AM,

but not LAFM will be set when a Broadcast frame is re-

ceived, even if the Logical Address Filter is pro-

grammed in s uch a way that a Broa dcast fram e would

pass the hash filter . If DRCVBC is set to 1 and the Log-

ical Address Filter is programmed in such a way that a

Broadc ast frame would pas s the hash fi lter, LAFM will

be set on the reception of a Broadcast frame.

When the Am79C972 contr oller operates in pro miscu-

ous mode and n one of the thr ee ma tch bi ts is s et, it is

an indication that the Am79C972 controller only ac-

cepted the frame because it was in promiscuous mode.

When the A m79C972 cont roller is no t programmed to

be in pro mi scuo us mod e, but the EADI inte rface is en-

abled, then when none of the thr ee matc h bit s is set , it

is an i ndication that the Am79C972 controll er only a c-

cepted the frame because it was not rejected by driving

the EAR pin LOW within 64 bytes after SFD.

See Table 6 for receive address matches.

Table 6. Receive Address Match

Automatic Pad Stripping

During reception of an IEEE 802.3 frame, the pad field

can be stripped automatically. Setting ASTRP_RCV

(CSR4, bi t 0) to 1 enables the automa tic pa d str ippin g

feature. The pad fiel d wi ll be stripp ed before the frame

is pas se d to th e FIF O, thus pres erv ing FI FO sp ac e for

addition al frames. The FCS field will also be stripped,

since it is computed at the transmitting station based on

the data and pad field characters, and will be inv alid for

a receive frame that has had the pad characters

stripped.

The number of bytes to be s tripped is calculated f rom

the embedded length field (as defined in the ISO 8802-

3 (IEEE/ANSI 802.3) definition) contained in the frame.

The length indicates the actual number of LLC data

bytes contained in the message. Any received frame

which contains a length field less than 46 bytes will have

the pad fi eld s tri pped ( if AST RP_RCV i s se t). Re ceive

PAM LAF

MBAM

DRC

VBC Comment

000X

Frame accepted due to

PROM = 1 or no EADI

reject

1 0 0 X Physical address match

0100

Logical address filter

match;

frame is not of type

broadcast

0101

Logical address filter

match;

frame can be of type

broadcast

0010Broadcast frame

64 Am79C972

frames which have a length field of 46 bytes or greater

will be passed to the host unmod ified. Figure 34 shows the byte/bit ordering of the received

length field for an IEEE 802.3-compatible frame format.

Figure 34. IEEE 802.3 Frame And Length Field Transmission Order

Since any valid Ethernet Type field value will alwa ys be

greater than a normal IEEE 802.3 Length field (≥46),

the Am 79C972 controll er will not attem pt to str ip vali d

Et hernet fr ames . Note that for some network protocols,

the value passed in the Ethernet Type and/or IEEE

802.3 Length field is not compliant with either standard

and may cause problems if pad stripping is enabled.

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the Am79C972 controller.

Note that if the Au tomatic Pad Strippi ng featu re is en-

abled, the FCS for padded frames will be verified

against the value computed for the incoming bit stream

includi ng pad c hara cters, but the F CS value for a pa d-

ded frame will not be passed to the host. If an FCS

error is detected in any frame, the error will be reported

in the CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinc t categor i es, i.e., those co ndi tio ns whi c h a re th e

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal ev ents which may occur and which are handled

autonomously by the Am79C972 controller are basi-

cally collisions within the slot time and automatic runt

packe t rej ec tio n. T he A m79 C972 co ntr ol le r wil l e ns ure

that collisions that occur with in 512 bit t imes from the

start of reception (excluding preamble) will be automat-

ically del ete d fro m the recei ve FIFO with no ho st i nter -

ve ntion. The recei ve FIFO wil l dele te any frame that is

composed of fewer than 64 bytes provided that the

Runt Packet Accept (RPA bit in CSR124) feature has

not bee n enabled a nd the network interface is operat-

ing in half- duplex mode, or the full-dupl ex Runt Packet

Accept D isable b it (FDRPAD, BC R9, bit 2) is set. Th is

crit erion wil l be met regardl ess of whether the receive

frame was the fir s t (or onl y) frame i n th e FIFO or i f th e

receive frame was queued behind a previously re-

ceived message.

Abnormal network conditions include:

nFCS er rors

nLate collision

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

section, Buffer Management Unit.

Loopback Operation

Loopback is a mode of operation intended for system

diagnos tics. I n this mode, the transmi tter and receiver

Preamble

1010....1010 SFD

10101011 Destination

Address Source

Address Length LLC

Data Pad FCS

Bytes

46 — 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing T ime

Bit

0Bit

7Bit

0Bit

Most

Significant

Byte

Least

Significant

Byte

1 — 1500

Bytes 45 — 0

Bytes

21485C-37

Am79C972 65

are both operating at the same time so that the control-

ler receives its own transmissions. The controller pro-

vides two basic types of loopback. In internal loopback

mode, the transmitted data is looped back to the re-

ceiver inside the controller without actually transmitting

any data to the external network. The receiver will

move the received data to the next receive buffer,

where it can be examined by software. Alter n ati vely, i n

external loopback mode, data can be transmitted to

and received from the external network.

Refer to Table 21 for various bit settings required for

Loopback modes.

GPSI Loopback Modes

When GPSI is the active network por t, there are only

two modes of loopback operation: internal and external

loopback. Loopback operation is enabled by setting

LOOP (CSR15, bit 2) to 1.

When INTL is set to 1, internal loopback is selected.

Data comi ng out of the transmit FIFO is fed directly t o

the receive FIFO. All GPS I outputs are inactive; inputs

are ignored.

External loopback operation is selected by setting INTL

to 0. Data is transmitted to the network and is expected

to be looped back to the GPSI receive pins outside the

chip. Collision detection is active in this mode.

Media Independent Interface Loopback Features

Loopback through the MII can be handled in two wa ys.

The Am79C972 controller supports an internal MII

loopback and an external MII loopback. The MII

loopback requires that the MII port be manually config-

ured through software using ASEL (BCR 2, bit 1) and

PORTSEL (CSR 15, bits 8-7).

The extern al loopba ck through the MII requires a two-

step o peration. The exter nal PH Y must be pl aced int o

a loopback mode by writing to the MII Control Register

(BCR33, BCR34). Then the Am79C972 controller must

be placed into an external loopback mode by setting

the Loop bits.

The inter nal loopback through the MII is controlled by

MIIILP (BCR32, bit 1). When set to 1, this bit will cause

the inter na l portion of the MII data port to loopback on

itself. The MII management port (MDC, MDIO) is unaf-

fected by the MIILP bit. The internal MII interface is

mapped in the following way:

nThe TXD[3:0 ] nibble d ata path is looped back onto

the RXD[3:0] nibble data path;

nTX_CLK is looped back as RX_CLK;

nTX_EN is looped back as RX_DV.

nCRS is correctly OR’d with TX_EN and RX_DV and

always encompasses the transmit frame.

nTX_ER is not driven by the Am79C972 and there-

fore not looped back.

During the internal loopback, the TXD, TX_CLK, and

TX_EN pins will toggle appropriately with the correct

data.

Miscellaneous Loopback Features

All transmit and receive function programming, such as

automa tic transmit p adding and rece ive pad stripp ing,

operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the C-

LANCE (Am79C90) software.

Since the Am79C972 controller has two FCS genera-

tors, there are no mo re res tr i cti ons on FC S genera tio n

or checking, or on testing multicast address detection

as they exist in the half-duplex PCnet family devices

and in the C-LA NCE. On rece ive, the Am79C972 con-

troller now provides true FCS status. The descriptor for

a frame with an FCS error will hav e the FCS bit (RMD1,

bit 27) set to 1. The FCS generator on the transmit side

can sti ll be disabled by sett ing DXMT FCS (CSR15, bi t

3) to 1.

In interna l lo opb ack operation , the Am 79C 972 con tro l-

ler provides a special mode to test the collision logic.

When FCOLL (CSR15, bit 4) is set to 1, a collision is

forced durin g every transmission attempt. Thi s will re-

sult in a Retry error.

General Purpose Serial Interface

The Gen eral Purp os e Se rial Inte rface (GPSI) provides

a direct interface to the MAC section of the Am79C972

controller. All signals are digital and data is non-en-

coded. The GPSI allows use of an external Manchester

encoder/decoder such as the Am7992B Serial Inter-

f ace Ad apter ( SIA). I n addit ion, it allo ws the Am 79C972

controlle r to be used as a MAC s ublayer engine in re-

peater designs based on the IMR+ device

(Am79C981).

GPSI mode is invoked by selecting the interface

through the PORTSEL bits of the Mode register

(CSR15, bits 8-7).

The GPSI interface uses some of the same pins as the

interface to the MII. Simultaneous use of both functions

is not possible.

After an H_RESET, all MII pins are internally config-

ured to function as the MII interface. When the GPSI in-

terface is selected by setting PORTSEL (CSR15, bits

8-7) to 10 b, the Am7 9C97 2 control ler will ter minate all

further accesses to the MII.

GPSI signal functions are described in the pin descrip-

tion section under the GPSI subheading.

Full-Duplex Operation

The Am79C972 controller supports full-duplex opera-

tion on both network interfaces. Full-duplex operation

66 Am79C972

allows simultaneous transmit and receive activity on the

TXDAT and RXDAT pins of the GPSI port, and the

TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex

operation i s enabled by the FDEN bit loc ated in BCR9

for all ports. Full-duplex operation is also enabled

through Auto-Negotiation when DANAS (BCR 32, bit 7)

is not enabled on the MII port and the ASE L bit is set,

and both the extern al PHY and its link partner are ca-

pable of Auto-Negotiation and full-duplex operation.

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

nThe first 64 bytes of every transmit frame are not

preserved in the Transmit FIFO during transmission

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

plex mode is active and a frame is being transmitted,

the XMTFW bits (CSR80, bits 9-8) always govern

when transmit DMA is requested.

nSuccessful reception of the first 64 bytes of every

receive frame is not a requirement f or Receive DMA

to begin as described in the Receive Exception Con-

ditions section. Instead, receive DMA will be re-

quested as soon as either the RCVFW threshold

(CSR80, bi ts 12-13 ) is re ached o r a compl ete valid

receive frame is detected, regardless of length. This

Receive FIFO operation is identical to when the RP A

bit (CSR124, bit 3) is set during half-duplex mode

operation.

The MAC engine chan ges for full-du plex operation a re

as follows:

nChanges to the Transmit Deferral mechanism:

—Transmission is not deferred while receive is

active.

—The IPG counter which governs transmit def erral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, instead of when transmit and car-

rie r act ivity ends.

nThe 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

nThe collision indication input to the MAC engine is

ignored.

The MII changes for full-duplex operation are as fol-

lows:

nThe collision detect (COL) pin is disabled.

nThe SQE test function is disabled.

nLoss of Carrier (LCAR) reporting is disabled.

Full-Duplex Link Status LED Support

The Am79C972 controller provides bits in each of th e

LED Status registers (BCR4, BCR5, BCR6, BCR7) to

display the Full-Duplex Link Status. If the FDLSE bit (bit

8) is set, a value of 1 will be sent to the associated LED-

OUT bit when in Full-Duplex.

Am79C972 67

Media Independent Interface

The Am79C972 controller fully supports the MII ac-

cording to the IEEE 802.3 standard. This Reconcilia-

tion Sublayer interface allows a variety of PHYs

(100BASE-TX, 100BASE-FX, 100BASE-T4,

100BASE-T2, 10BASE-T, etc.) to be attached to the

Am79C972 MAC engine without future upgrade prob-

lems. The MII interface is a 4-bit (nibble) wide data path

interface that runs at 25 MHz for 100-Mbps networks or

2.5 MHz for 10-Mbps networ ks. The in terface consists

of two independent data paths, receive (RXD(3:0)) and

transmit (TXD(3:0)), control signals for each data path

(RX_ER, RX_DV, TX_ER, TX_EN), network status sig-

nals (COL, CRS), c locks (RX_CLK, TX _CLK) for each

data path, and a two-wire management interface (MDC

and MDIO). See Figure 35.

MII Transmit Interface

The MII transmit clock is generated by the external

PHY and is sent to the Am79C972 controller on the

TX_CLK input pin. The clock can run at 25 MHz or 2.5

MHz, depe ndi ng on the s pee d of t he network to whi ch

the external PHY is attached. The data is a nibb le-wide

(4 bits) data path, TXD( 3:0), from the Am79C9 72 con-

troller to the external PHY and is synchronous to the

rising edge of TX_CLK. The transmit process starts

when the Am79C972 controller asserts the TX_EN,

which indicates to the external PHY that the data on

TXD(3:0) is valid.

Normally, unrecoverable errors are signaled through

the MII to the external PHY with the TX_ER output pin.

The external PHY will respond to this error by generat-

ing a TX coding error on the current transmitted frame.

The Am79C972 controller does not use this method of

signaling errors on the transmit side. The Am79C972

controller will invert the FCS on the last byte generating

an invalid FCS. The TX_ER pin is reserved for future

use and is actively driven to 0.

MII Receive Interface

The MII receive clock is also generated by the external

PHY and is sent to the Am79C972 controller on the

RX_CLK input pin. The clock will be the same fre-

quency as the TX_CLK but will be out of phase and can

run at 25 MHz o r 2. 5 M Hz, dep end ing on the s pe ed o f

the network to which the ex tern al PHY is attached .

Figure 35. Media Independent Interfa ce

The RX_CLK is a continuous clock during the reception

of the frame, but can be stopped for up to two RX_CLK

periods at the beginning and the end of frames, so that

the external PHY can sync up to the network data traffic

necessary to recover the receive clock. During this

time, the external PHY may switch to the TX_CLK to

maintain a stable clock on the receive interface. The

Am79C972 controller will handle this situation with no

loss of data. The data is a nibble-wide (4 bits) data

path, RXD(3:0), from the external PHY to the

Am79C9 72 controll er and is synchro nous to the risin g

edge of RX_CLK.

The receive process starts when RX_DV is asserted.

RX_D V will remain asserted until the end of the receive

frame. The Am79C972 controller requires CRS (Car-

rie r Sens e) to toggle in be tween f rames in order t o re-

ceive them properly. Errors in the currently received

frame are signaled across the MII by the RX_ER pin.

RX_ER can be used to signal special conditions out of

band when RX_DV is not asserted. Two defined out-of-

band conditions for this are the 100BASE-TX signaling

of bad Star t of Frame Delimiter and the 100BASE-T4

indicat ion of i ll eg al co de gr oup before the rec ei ver has

synched to the incoming data. The Am79C972 control-

ler wil l no t res pond to th es e c ond iti ons. Al l out of band

4RXD(3:0)

RX_DV

RX_ER

RX_CLK

4TXD(3:0)

TX_EN

Am79C972

MII Interface

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

21485C-38

68 Am79C972

conditions are currently treated as NULL events. Cer-

tain in band non-IEEE 802.3u-compliant flow control

sequences may cause erratic behavior for the

Am79C972 controller. Consult the switch/bridge/router/

hub manual to disable the in-band flow control se-

quences if they are being used.

MII Network Status Interface

The MII also provides signals that are consistent and

necessary for IE EE 802.3 an d IE EE 8 02.3 u operation .

These signals are CRS (Carrier Sense) and COL (Col-

lision S ens e). Car rier Se ns e i s us ed to detect non -i dle

activity on the network. Collision Sense is used to indi-

cate th at simultan eou s transmi ssio n has o ccurr ed in a

half-duplex network.

MII Management Interface

The MII provides a two -wire manage ment interface so

that the Am79 C972 controller can control and receive

status from external PHY devices.

The Am79 C972 controller c an suppor t up to 31 exter-

nal PHYs attached to the MII Management Interface

with software support and only one such device without

software support.

The Network P ort Manager copies the PHYAD after the

Am79C972 controller reads the EEPROM and uses it

to communicate with the external PHY. The PHY ad-

dress must be programmed into the E EPROM prior to

starting the Am79C972 controller. This is necessary so

that the inter nal management controller can work au-

tonomously from the software driver and can always

know where to access the external PHY. The

Am79C9 72 controll er is unique by offering di re ct h ar d-

ware suppor t of the external PHY device without soft-

ware support. The PHY address of 1Fh is reserved and

should not be used. To access the 31 exter nal PHYs,

the software driver must have knowledge of the exter-

nal PHY’s address when multiple PHYs are present be-

fore attempting to address it.

The MII Management Interface uses the MII Control,

Address, and Data registers (BCR32, 33, 34) to control

and communicate to the external PHYs. The

Am79C972 controller generates MII management

frames to the external PHY through the MDIO pin syn-

chronous to the rising edge of the Management Data

Clock (MDC) based on a combination of writes and

reads to these registers.

MII Management Frames

MII management frames are automatically generated

by the Am79C972 controller and conform to the MII

clause in the IEEE 802.3u standard.

The start of the frame is a preamble of 32 ones and

guarantees that all of the external PHYs are synchro-

nized on the same interface. (See Figure 36. ) Loss of

synchronization is possible due to the hot-plugging ca-

pability of the exposed MII.

The IEEE 802.3 specification allows you to drop the

preamble, if after re ading the MII Statu s Regis ter f rom

the external PHY you can determine that the external

PHY will support Preamble Suppression (BCR34, bit

6). After having a valid MII Status Register read, the

Am79C 972 cont roller will then dro p the creati on of the

preamble stream until a reset occurs, receives a read

error, or the external PHY is disconnected.

Figure 36. Frame Format at the MII Interface Connection

This is followed by a star t field (ST) and an operation

field (OP). The operation field (OP) indicates whether

the Am79C972 controller is initiating a read or write op-

eration. This is followed by the external PHY address

(PHYAD) and the register address (REGAD) pro-

grammed in BCR33. The PHY address of 1Fh is re-

served and should not be used. The external PHY may

hav e a larger address space starting at 10h - 1Fh. This

is the ad dress range se t aside by the IEE E as vend or

usable address space and will v ary from vendor to v en-

dor . This field is followed by a bus turnaround field. Dur-

ing a read operation, the bus turnaround field is used to

determine if the external PHY is responding correctly to

the read requ est or not. The Am79C972 contr oller will

tri-state the MDIO for both MDC cycles.

During the second cycle, if the external PHY is syn-

chronized to the Am79C972 controller, the external

PHY will drive a 0. If the external PHY does not drive a

0, the Am79C972 controller will signal a MREINT

(CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set

Preamble

1111....1111 OP

10 Rd

01 Wr

PHY

Address Register

Address TA

Z0 Rd

10 Wr Data

Bits

Bits 16

Bits 1

Bit

Idle

21485C-39

Am79C972 69

to a 1, indicati ng the Am79C972 contr oller had an MII

management frame read error and that the data in

BCR34 is no t valid . The data field to/from the exter nal

PHY is read or written into the BCR34 register . The last

field is an IDLE field that is necessary to give ample

time for drivers to tur n of f before t he nex t access. The

Am79C972 controller will drive the MDC to 0 and tri-

state the MDIO anytime the MII Management Port is

not active.

To help to speed up the r eading an d wri ting of th e MII

management frames to the external PHY, the MDC can

be sped up to 10 MHz by setting the FMDC bits in

BCR32. The IEEE 802.3 specification requires use of

the 2.5-MHz clock rate, but 5 MHz and 10 MHz are

available for the user. The intended applications are

that the 10-MHz clock rate can be used for a single e x-

ternal PHY on an adapter card or motherboard. The 5-

MHz clock rate can be used for an exposed MII with

one extern al PHY att ach ed. The 2. 5-MHz clock rate is

intended to be used when multiple external PHYs are

connected to the MII Management Port or if compli-

ance to the IEEE 802.3u standard is required.

Auto-Poll External PHY Status Polling

As defined in the IEEE 802.3 standard, the external

PHY attached to the Am79C972 controller’s MII has no

way of communicating important timely status inf orma-

tion back to Am79C972 controller. The Am79C972

control le r has no way of knowing that an exter na l PHY

has undergone a change in status without polling the

MII status register . To pre v ent problems from occurring

with inadequate host or software polling, the

Am79C972 controller will Auto-Poll when APEP

(BCR32, bit 11) is set to 1 t o ins ure that the m ost cur -

rent information is available. See Appendix C, MII

Management Registers, for the bit descriptions of the

MII Status Register. The contents of the latest read

from the external PHY will be stored in a shadow regis-

ter in the Auto-P oll block. The first read of the MII Status

be compared to the contents already stored in the

shadow register . If there has been a change in the con-

tents of the MII Status Register, a MAPINT (CSR7, bit

7) interr upt wil l be generated o n INTA if the MAPINTE

(CSR7, bit 6) is set to 1. The Auto-Poll features can be

disabled if software driver polling is required.

The Auto-Poll’s frequency of generating MII manage-

ment frames can be adjusted by setting of the APDW

bits (BCR32, bits 10-8). The delay can be adjusted

from 0 MDC periods to 2048 MDC periods. Auto-P oll by

default will only read the MII Sta tus register in the ex-

ternal PHY.

Network Port Manager

The Am7 9C972 controlle r is unique in that it does no t

require software intervention to control and configure

an external PHY attached to the MII. This was done to

ensure backwards compatibility with existing software

driv ers. To the current software drivers, the Am79C972

controller will look and act like the PCnet-PCI II and will

interoperate with existing PCnet drivers from revision

2.5 upward. The heart of this system is the Network

Port Manager.

If the external PHY is present and is active, the Net-

work P ort Manager will request status from the e xternal

PHY by generating MII management frames. These

frames will be sent roughly every 900 ms. These

frames are necessary so that the Network Port Man-

ager can m onitor the c urre nt acti ve link and can sel ect

a different network port if the current link goes down.

Auto-Negotiation

Through the external PHY, the following capabilities are

possible: 100BASE-T4, 100BASE-TX Full-/Half-Du-

ple x, and 10BASE-T Full-/Half-Duplex. The capabilities

are then sent to a link partner that will also send its ca-

pabilities. Both sides look to see what is possible and

then they will connect at the greatest possible speed

and capa bilit y as defi ned in the IE EE 80 2.3u st and ard

and according to Table 7.

By default, the link partner must be at least 10BASE-T

half-duplex capable. The Am79C972 controller can au-

tomatically negotiate with the network and yield the

highest performance possible without software sup-

port. See the section on Network Port Manager for

more details.

A uto-Negotiation goes further by providing a message-

based communication scheme called, Next Pages, be-

fore connecting to the Link Par tner. This feat ure is not

supported in Am79C972 unless the DANAS (BCR32,

bit 10) is selected and the software driver is capable of

controlling the external PHY. A complete bit description

of the MII and Auto-Negotiation registers can be found

in Appendix C.

Automatic Network Port Selection

If ASEL (BCR2, bit 0) is set to 1 and DANAS (BCR 32,

bit 7) is set to 0, then the Network Por t Manager will

star t to confi gure the exter nal PHY if it detects the ex-

ternal PHY on the MII Interface.

Table 7. Auto-Negotiation Capabilities

Network Speed Physical Network Type

200 Mbps 100BASE-X, Full Duplex

100 Mbps 100BASE-T4, Half Duplex

100 Mbps 100BASE-X, Half Duplex

20 Mbps 10BASE-T, Full Duplex

10 Mbps 10BASE-T, Half Duplex

70 Am79C972

Automatic Network Selection: Exceptions

If ASEL (BCR2, bit 0) is set to 0 or DANAS (BCR 32, bit

7) is set to 1, then the Network Por t Ma nager will dis -

continue ac tively tr y ing to esta blish the co nne ction s. It

is assumed that the software driver is attempting to

configure the network port and the Am79C972 control-

ler will always defer to the software dr iver. When The

ASEL is set to 0, the software d river should the n con-

figure the ports with PORTSEL (CSR15, bit s 7-8) . The

GPSI does not participate in the automatic selection

process and should be manually configured with the

PORTSEL bits.

Note: It is highly recommended that ASEL and

PORTSEL be used wh en tr ying to manuall y configure

a specific network port.

In order to manually configure the External PHY, the

recommended procedure is to fo rce the PHY config-

urations when Auto-Negotiation is not enabled. Set the

DANAS bi t (BC R32, bit 7) to turn off the Networ k Por t

Manager. Then writ e a gai n to BCR32 with th e DANAS

and XPHANE (BCR32, bit 5) bits cleared, together with

the XPHYFD (BCR32, bit 4) and XPHYSP (BCR32,

bit 3) bits set to the desired configuration. The Network

Port Manager will send a few frames to validate the

configuration.

CAUTION: The Network Port Manager utilizes the

PHYADD (BCR33, bits 9-5) to communicate with the

exter nal PHY dur in g the automatic por t sele ction pro-

cess. The PHYADD is copied into a shadow register

after the Am 79C972 co ntr ol le r has r ea d th e c on fig ura-

tion information from the EEPROM. Extreme care must

be ex ercised by the host software not to access BCR33

during this time. A read of PVALID (BCR19, bit 15) be-

f ore accessing BCR33 will guarantee that the PHYADD

has been shadowed.

Am79C972’s Automatic Network Port selection mecha-

nism falls within the following general categories:

nExtern al PHY Not Auto-Negotiable

nExtern al PHY Auto-Negotia ble

Automatic Network Selection: External PHY Not

Auto-Negotiable

This case occurs when the MIIPD (BCR32, bit 14) bit is

1. This indicates that there is an external PHY attached

to Am79C972 controller’s MII. If more than one external

PHY is attached to the MII Management Interface, then

the D ANAS (BCR32, bit 7) bit must be set to 1 and then

all con figuration c ontrol should reve r t to so ftware. The

Am79 C97 2 co ntr olle r wi ll r ead the r eg ist er of th e exter-

nal PHY to deter mine its status and networ k capabili-

ties. See Appendix C, MII Management Registers, fo r

the bit des cr i pti ons of t he M II St atus regi st er. If the ex-

ter nal PHY is no t Auto-Ne gotiation cap able and/or the

XPHYA NE (BCR32, bit 5) bit is set to 0, then the Net-

work Port Manager will match up the external PHY ca-

pabilities with the XPHYFD (BCR 32, bit 4) and the

XPHYSP (BCR32, bit 3) bits programmed from the EE-

PROM. The Am79C972 controller will then program the

exte r nal PHY with those values. A new read of the ex-

ternal PHYs MII Status register will b e made to see if

the link is up. If the link does not come up as pro-

grammed after a spec ifi c tim e, the Am 79C9 72 c on tro l-

ler will fail the external PHY link. The Network Port

Manager will periodically query the external PHY for

active links.

Automatic Network Selection: External PHY

Auto-Negotiable

This case occurs when the MIIPD (BCR32, bit 14) bit is

1. This indicates that there is an e xternal PHY attached

to Am79C972 controller’s MII. If more than one external

PHY is attached to the MII Management Interface, then

the DANAS (BCR32, bit 7) bit must be set to 1 and then

all con figuration control sh ould reve r t to so ftware. The

Am79C972 controller will read the MII Status register of

the external PHY to determine its status and network

capabil iti es. S ee Ap pend ix C for the bit d es cripti ons of

the MII Status re giste r. If the exter n al PHY is Auto-Ne-

gotiat ion c apa ble and /or th e X PH YANE (BCR32, b it 5)

bit is set to 1, then the Am79C972 controller will star t

the external PHY’s Auto-Negotiation process. The

Am79C972 controller will write to the external PHY’s

Adver tisement register with the following conditions

set: turn off the Next P ages support, set the Technology

Ability Field ( See Appe ndix C for the Auto-Nego tiation

tus register read, and set the Type Selector field to the

IEEE 802.3 standard. The Am79C972 controller will

then write to the e xternal PHY’s MII Control register in-

structing the external PHY to negotiate the link. The

Am79C972 controller will poll the external PHY’s MII

Status re gister until the Auto-N egotiation Com plete bit

is set to 1and the Link Status bit is set to 1. The

Am79C 972 co ntr ol le r wil l t hen wait a s pe cific time an d

then again read the external PHY’s MII Status register .

If the Am79C972 controller sees that the external

PHY’s link is down, it will try to bring up the external

PHY’s link manually as described abov e. A new read of

the external PHY’s MII Status regi ster will be ma de to

see if the link is up. If the link does not come up as pro-

grammed after a spec ifi c tim e, the Am 79C9 72 c on tro l-

ler will fail the external PHY link and star t the process

again.

Automatic Network Selection: Force External Reset

If the XPHYRS T bit (B CR32 , bit 6) is s et to 1, then th e

flow changes slightly. The Am79C972 controller will

write to the external PHY’s MII Control register with the

RESET bit set to 1 (See Appendix C, MII Management

Registers, for the MII register bit descriptions). This will

force a complete reset of the external PHY. The

Am79C972 controller after a specific time will poll the

ex ternal PHY’s MII Control register to see if the RESET

Am79C972 71

bit is 0. After the RESET bit is cleared, then the normal

flow continues.

External Address Detection Interface

The EADI is provided to allow e xternal address filtering

and to provide a Receive Frame Tag word for propri-

etary routing information. It is selected by setting the

EADISEL b it in B CR2 to 1. T hi s feature is ty pi call y ut i-

lized by terminal servers, bridges and/or router prod-

ucts. The EADI interface can be used in conjunction

with external logic to capture the pack et destination ad-

dress from the serial bit stream as it arrives at the

Am79C972 controller, to compare the captured ad-

dress with a table of stored addresses or identifiers,

and then to determine whether or not the Am79C972

controller should accept the packet.

External Address Detection Interface: GPSI Port

The EA DI interface outputs are deli ve red direct ly from

the NRZ decoded data and clock recovered by the ex-

ter nal PHY. This allows the extern al addr ess det ectio n

to be performed in parallel with frame reception and ad-

dress com paris on in the MAC Station A ddress Detec-

tion (SAD) block of the Am79C972 controller.

SRDCLK is provided to allow clocking of the receive bit

stream int o th e exter na l a ddr es s detectio n l ogi c. O nc e

a received frame commences and data and clock are

available, the EADI logic will monitor the alternating

(“1,0”) preamble pattern until the two 1s of the Start

Frame Delimiter (SFD, 10101011 bit pattern) are de-

tected, at which point the SFBD output will be driven

HIGH.

The SFBD signal will initially be LO W. The assertion of

SFBD is a signal to the external address detection logic

that the SFD has been detected and that subsequent

SRDCLK cycles will deliver packet data to the external

logic. Therefore, when SFB D is asse r ted, the ext er nal

address matching logic should begin de-serialization of

the SRD data and send the resulting destination ad-

dress to a Content Addressable Memory (CAM) or

other add ress d etection device. In order to red uce the

amount of logic external to the Am79C972 controller for

multiple address decoding systems, the SFBD signal

will toggle at each new byte boundary within the

packet, subsequent to the SFD. This eliminates the

need for externally supplying byte framing logic.

SRD is the deco ded NRZ data from the networ k. This

signal can be used for external address detection.

The EAR pin should be driven LOW b y the external ad-

dress comparison logic to reject a frame.

If an address match is detected by comparison with ei-

ther the Physical Address or Logical Address Filter reg-

isters contained within the Am79C972 controller or the

frame is of the ty pe 'B roadcast', then th e frame will b e

accepted regardless of the condition of EAR. When the

EADISEL bit of BCR2 is set to 1 and the Am79C972

controller is programmed to promiscuous mode

(PROM bit of the Mode Register is set to 1), then all in-

coming fra mes will be acc epted, rega rdle ss of a ny ac-

tivity on the EAR pin.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR 15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filt er registers (C SR8 to CSR11) are

programmed to all zeros.

When the EADISEL bit of BCR2 is set to 1 and internal

address match is disabled, then all incoming frames

will be accepted by the Am79C972 controller, unless

the EAR pin becomes active during the first 64 bytes of

the frame (excluding preamble and SFD). This allows

external address lookup logic approximately 58 byte

times aft er the last d estination ad dress bit is available

to generate the EAR signal, assuming that the

Am79C972 controller is not configured to accept runt

packe ts. The EADI l ogic only samples EAR from 2 bit

times after SFD until 512 bit times (64 bytes) after SFD .

The frame will be accepted if EAR has not been as-

ser ted during this window. In order for the EAR pin to

be functi onal in f ull-duplex mode, FDRPAD bit (BCR9,

bit 2) needs to be set. If Runt Pac k et Accept (CSR124,

bit 3) is enabled, then the EAR signal must be gener-

ated prior to the 8 bytes received, if frame rejection is

to be guaran tee d. Ru nt p acket sizes could b e a s sho rt

as 12 byte times (assuming 6 bytes for source address,

2 bytes for length, no data, 4 bytes for FCS) after the

last bit of the destination address is available. EAR

must have a pulse width of at least 110 ns.

The EADI outp uts continue to pr ovide data throu ghout

the rec ept ion of a frame. Thi s al lows th e exter na l log ic

to captur e fram e head er infor mation to de ter mi ne pro-

tocol type, intern etwor king infor matio n, and ot her us e-

ful data.

The EADI interf ace will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

are set ). This conf iguration is useful a s a semi-power-

down mode in that the Am79C972 controller will not

perform a ny power-cons uming DMA ope rations. How-

ever, external circuitry can still respond to control

frames on the network to facilitate remote node control.

Table 8 summarizes the operation of the EADI inter-

face.

72 Am79C972

External Address Detection Interface: External

PHY

When usi ng the MII, the EA DI int er face changes to re-

flect the changes on that interface. Except for the nota-

tions below the interface conforms to the previous

functiona lity. The data arr ives in nibbles and can b e at

a rate of 25 MHz or 2.5 MHz.

The MII provides al l necessar y data and clock signa ls

needed for the EADI interface. Consequently, SRDCLK

and SRD are not used and are driven to 0. Data for the

EADI is the RXD(3:0) receive data provided to the MII.

Instead of des erial izing the networ k data, the user will

receive the data as 4 bit n ibbles. RX_CLK is provided

to allow clocking of the RXD(3:0) receive nibble stream

into the ex ternal address detection logic. The RXD(3:0)

data is synchronous to the rising edge of the RX_CLK.

The assertion of SFBD is a signal to the external ad-

dress detection logic that the SFD has be en detected

and that the first valid data nibble is on the RXD(3:0)

data bus. The SFBD signal is delayed one RX_CLK

cycle from the above definition and actually signals the

start of valid data. In order to reduce the amount of

logic external to the Am79C972 controller for multiple

address decoding systems, the SFBD signal will go

HIGH at each new byte boundary within the packet,

subsequent to the SFD . This eliminates the need for e x-

ternally supplying byte framing logic.

The EAR pin function is the same and should be driven

LOW by the external address comparison logic to reject

a frame. See the External A ddr es s Det ect ion Inte rface:

GPSI Port section for more details.

External Address Detection Interface: Receive

Frame Tagging

The Am7 9C972 c ontro ller su pports rece ive frame tag-

ging in both GPSI or MII mode. The method remains

constant, but the chip interface pins will change be-

tween the MII and the GPSI modes. The receive frame

tagging implementation will be a two- and three-wire

chip interface, respectively, added to the existing EADI.

The Am7 9C97 2 c ont ro ll er su ppo rts up to 15 bits of re-

ceive frame tagging per frame in the receive frame sta-

tus (RFRTAG). The RFRTAG bits are in the receive

frame status field in RMD2 (bits 30-16) in 32-bit soft-

ware mode. The receive frame tagging is not supported

in the 16-bi t softwa re mo de. The RF RTAG field are all

zeros when either the EADISEL (BCR2, bit3) or the

RXFRTA G (CSR7, bit 14) are set to 0. When EADISEL

(BCR2, bit 3) and RXFRTAG (CSR7, bi t 14) are set to

1, then the RFRTA G reflects the tag word shifted in dur-

ing that receive frame.

In the MII mode, the two-wire interface will use the

MIIRXFRTGD and MIIRXFRTGE pins from the EADI

interface. These pins will provide the data input and

data input enable for the receive frame tagging, respec-

tively. The se pins are no rm ally not us ed dur in g the M II

operation.

In the GPS I mo de, the three- wir e in ter face will use the

RXFR TGD , SRDCLK, and the RXFRTGE pins from the

EADI and MII. These pins will provide the data input,

data input clock, and the data input for the receive

frame tagging enable, respectively.

The receive frame tag register is a shift register that

shifts data in MSB first, so that less than the 15 bits al-

loca ted m ay be utilized by the use r. Th e upp er bit s no t

utilized will return zeros. The receive fr ame tag register

is set to 0 in between reception of frames. After receiv-

ing SFBD indication on the EADI, the user can star t

shifting data i nto the rece ive tag regis ter u ntil o ne net-

work clock period before the Am79C972 controller re-

ceives the end of the current receive frame.

In the MII mode, the user must see the RX_CLK to

driv e the synchronous receive frame tag data interface.

After receiving the SFBD indication, sampled by the ris-

ing edge of the RX_CLK, the user will drive the data

input and the data input enable synchronous with the

rising edge of the RX_CLK. The user has until one net-

work clock period before the deassertion of the RX_D V

to input the data in to the r eceive frame tag re gister. At

the deassertion of the RX_DV, the receive frame tag

terface. If the us er is sti ll dr iving th e data i nput enable

pin, erroneous or corrupted data may reside in the re-

ceive frame tag register. See Figure 37.

In the GPSI mode, the user must use the recovered re-

ceive data clock driven on the SRDCLK pin to driv e the

synchronous receive frame tag data interf ace. After re-

ceiving the SFBD indication, sampled by the rising

edge of the rec overed receive data clock, the user wi ll

driv e the data input and the data input enable synchro-

nous with the rising edge of the recov ered receive data

clock. The user has until one networ k cl ock perio d be-

fore the deasser tion of the data from the network to

input the data into the receive frame tag register . At the

completion of received network data, the receive frame

tag register will no longer accept data from the two-wire

interface. If the user is still driving the data input enable

pin, erroneous or corrupted data may reside in the re-

ceive frame tag register. See Figure 38.

Table 8 . EADI Operations

PROM EAR Required

Timing Received

Frames

1 X No timing

requirements All received fr am es

0 1 No timing

requirements All received frames

0 0 Low for two bit

times plus 10 ns

Fr ame rejected if in

address match

mode

Am79C972 73

Figure 37. MII Receive Frame Tagging

Figure 38. GPSI Mode Frame Tagging

Expansion Bus Interface

The Am79 C972 controller contains an Expa nsion Bus

Interface that suppor ts Flash and EPROM devices as

boot devices, as well as p rovides read/w rite acc ess to

Flash or EPROM.

The signal AS_EBOE is provided to strobe the upper 8

bits of the address into an external ‘374 (D f lip- flop) ad-

dress latch. AS_EBOE is asserted LOW during

EPROM/Flash read o peratio ns to c ontro l the OE inpu t

of the EPROM/Flash.

The Expansion Bus Address is split into two different

buses, EBUA_EBA[7:0] and EBDA[15:8]. The

EBU A_EBA[7:0] provides the least and the most signif-

icant address byte. When accessing EPROM/Flash,

the EBUA_EBA[7:0] is strobed into an ex ternal ‘374 (D

flip-flop) address latch. This constitutes the most signif-

icant portion of the Expansion Bus Address. For

EPROM/Flash accesses, EBUA_EBA[7:0] constitutes

the remaining least significant address byte. For byte

oriented EPROM/Flash accesses, EBDA[15:8] consti-

tutes the upper or middle address byte. EBADDRU

(BCR29, bits 3-0) should be set to 0 when not used,

since EBADDRU constitutes the EBUA por tion of the

EBU A_EBA address byte and is strobed into the exter-

nal ’374 addre ss latch.

The signal EROMCS is connec ted to the CS /CE input

of the EPROM/Flash. The signal EBWE is connected

to the WE of the Flash device.

The Expansion Data Bus is configured f or 8-bit byte ac-

cess during EPROM/Flash accesses. During EPROM/

Flash accesses, EBD[7:0] provides the data byte. See

Figure 39, Figure 40, and Figure 41.

Expansion ROM - Boot Device Access

The Am79C972 controller supports EPROM or Flash

as an Expansion ROM boot device. Both are config-

ured using the same methods and operate the same.

See the previous section on Expansion ROM transfers

to get the PCI timing and functional descr iption of the

transfer method. The Am79C972 controller is function-

ally equivalent to the PCnet-PCI II controller with Ex-

pansion ROM. See Figure 40 and Figure 41.

The Am79C972 controller will always read four bytes for

every host Expansion ROM read access. The interface

to the Expansion Bus runs synchronous to the PCI bus

interface clo ck. The Am 79C9 72 control ler will start the

read operation to the Expansion ROM by driving the

upper 8 bits of the Expansion ROM address on

EBUA_ EB A[ 7:0] . On e- hal f cl ock later, AS_EBOE goes

high to allow registering of the upper address bits ex-

ter nally. Th e upper por tion of the Expansi on ROM ad-

dress will be the same for all four byte read cycles.

RX_CLK

RX_DV

MIIRXFRTGE

MIIRXFRTGD

SF/BD

21485C-40

SRDCLK

MIIRXFRTGE

MIIRXFRTGD

SFD Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

SFBD

Bit8 Bitx Bity Bitz

Note:

Bitz is last data bit.

SRD

21485C-41

74 Am79C972

AS_EBOE is driven high for one-half clock,

EBUA_ EBA[7:0] ar e driven with the upp er 8 bi ts of th e

Expansion ROM address for one more clock cycle after

AS_EBOE goes low. Next, the Am79C972 controller

starts driving the lower 8 bits of the Expansion ROM

address on EBUA_EBA[7:0].

The time that the Am79C972 controller waits for data to

be valid is programmable. ROMTMG (BCR18, bi ts 15-

12) defines the time from when the Am79C972 control-

ler drives EBUA_EBA[7:0] with the lower 8 bits of the

Expansion ROM address to when the Am79C972 con-

troller latches in the data on the EBD[7:0 ] inputs. The

cles. When ROMTMG is set to nine (the default value),

EBD[7:0] is sampled wit h the next r ising edge of CLK

ten clock cy cles a fter EBUA _EBA [7:0] was driven wit h

a new address value. The clock edge that is used to

sample th e data is also th e clock edge that generates

the next Expansion ROM address. All four bytes of Ex-

pansion ROM data are stored in holding registers. One

clock cycle after the last data byte is available, the

Am79C972 controller asserts TRDY.

Figure 39. Flash Configuration for the Expansion Bus

The access time for the Expansion ROM or the EB-

DATA (BCR30) device (tACC) during read operations

can be calculated by subtracting the clock to output

delay for the EBUA_EBA[7:0] output s (t v_A_D) and by

subtracting the input to clock setup time for the

EBD[7:0] inputs (ts_D) from the time defined by

ROMTMG:

tACC = ROMTMG * CLK period *CLK_FAC - (tv_A_D) -

(ts_D)

The access time for the Expansion ROM or for the EB-

DATA (BCR30) device (tACC) during write operations

can be calculated by subtracting the clock to output

delay for the EBUA EBA[7:0] outputs (tv_A_D) and by

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

AS_/EBOE A[15:8]

A[7:0]

DQ[7:0]

Am79C972

’374

D-FF

FLASH

EROMCS

A[23:16]

21485C-42

Am79C972 75

adding the input to clock setup time f or Flash/EPRO in-

puts (ts_D) from the time defined by ROMTMG:

tACC = ROMTMG * CLK period * CLK_FAC - (tv_A_D) -

(ts_D)

The timing diagram in Figure 42 assumes the default

programming of ROMTMG (1001b = 9 CLK). After

reading the first byte, the Am79C972 controller reads in

three mo re by tes by increment ing the l ower po rti on of

the ROM address. After the last byte is strobed in,

TRDY will be asserted on clock 50. When the host tries

to perform a burst read of the Expansion ROM, the

Am79C972 c ontr ol ler wi ll dis co nne ct the acces s at the

second data phase.

The hos t must pr ogram th e Expa ns ion ROM Bas e A d-

dress register in the PCI configuration space before the

first access to the Expansion ROM. The Am79C972

controller will not react to any access to the Expansion

ROM until both MEMEN (PCI Command register , bit 1)

and ROMEN (PCI Expansion ROM Base Address reg-

ister, bit 0) are set to 1. After the Expansion ROM is

enabled, the Am79C972 controller will claim all memory

read accesses with an address between ROMBASE

and ROMB ASE + 1M - 4 (ROMBASE , PCI E xpansio n

ROM Base Addr ess regist er, bits 31-20). Th e address

output to the Expansion ROM is the offset from the ad-

dress on the PCI bus to ROMBASE. The Am79C972

controller aliases all accesses to the Expansion ROM

of the command types Memory Read Multiple and Mem-

ory Read Line to the basic Memory Read command.

Figure 40. EPROM Only Configuration for the Expansion Bus (64K EPROM)

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

EROMCS

A[15:8]

A[7:0]

DQ[7:0]

Am79C972

EPROM

AS_EBOE

21485C-43

76 Am79C972

Figure 41. EPROM Only Configuration for the Expansion Bus (>64K EPROM)

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given to

the PCI Memory Mapped I/O Base Address register,

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress re gister to a va lue that prevents the Am79C97 2

controller from claiming any memory cycles not in-

tended for i t.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55h (byte 0) and AAh (byte 1).

Direct Flash Access

Am79C9 72 controll er su pports Flas h as an E xpa nsio n

ROM device, as well as providing a read/write data

path to the Flash. The Am79C972 controller will sup-

port up to 1 Mbyte of Flash on the Expansion Bus. The

Flash is acc essed by a read or wri te to the Expa nsion

Bus Data port (BCR30). T he use r must load the up per

address EPADDR U (BCR 29, bits 3-0) and then set the

FLASH (BCR29, bit 15) bit to a 1. The Flash read/write

utilizes the PCI clock instead of the EBCLK during all

access es. EPADDRU is not need ed i f t he Fla sh size is

64K or less, but still must be programmed. The user will

then load the low er 16 bits of address, EPADDRL (BCR

28, bits 15-0).

Flash/EPROM Read

A read to the Expansion Bus Data Port (BCR30) will

start a read cycle on the Expansion Bus Interface . The

Am79C972 controller will drive EBUA_EBA[7:0] with

the most s i gnific an t ad dr es s byte at the sa me tim e th e

Am79C972 controller will drive AS_EBOE high to

strobe the address in the external ‘374 (D flip-flop). On

the next clock, the Am79C972 controller will drive

EBDA[15:8] and EBUA_EBA[7:0] with the middle and

least significant address bytes.

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

EROMCS

A[15:8]

A[7:0]

DQ[7:0]

Am79C972

EPROM

AS_EBOE

’374

D-FF A[23:16]

21485C-44

Am79C972 77

Figure 42. Expansion ROM Bus Read Sequence

Figure 43. Flash Read from Expansion Bus Data Port

The EROMCS is driven low for t he val ue ROMTMG +

1. Figure 43 assumes that ROMTMG is set to nine.

EBD[7:0] is sampled with the next rising edge of CLK

ten clock cy cles af ter EBUA _EBA [7:0] was d riven wit h

a new address value. This PCI slave access to the

Flash/EP ROM will res ult in a retry fo r the ver y fi rst ac-

cess. Subsequent accesses may give a retry or not, de-

pending on whether or not the data is present and valid.

The access time is dependent on the ROMTMG bits

(BCR18, bits 15-12) and the Flash/EPROM. This ac-

cess mechanism differs from t he Expansion ROM ac-

cess mechanism since only one byte is read in this

manner, instead of the 4 bytes in an Expansion ROM

access. T he PCI bus will not be held d uring acce sses

through the Expansion Bus Data Port. If the LAAINC

(BCR29, bit 15) is set, the EBADDRL address will be

incremented and a continuous series of reads from the

Expansion Data Port (EBDATA, BCR30) is possible.

The add ress i ncremen tor wi ll rol l over without war nin g

and without incrementing the upper address EBAD-

DRU.

The Flash write is almost the same procedure as the

read ac cess, except that th e Am7 9C972 c ontroll er will

not drive AS_EBOE low. The EROMCS and EBWE are

dri ve n low for the value ROMTM G again. The wr ite to

the FLASH port is a posted write and will not result in a

retry to the PCI unless the host tries to write a new

value before the previous write is complete, then the

host will experience a retry. See Figure 44.

CLK

EBUA_EBA [7:0]

Latched Address

EBDA [15:8]

EBD

AS_EBO

EROMCS

FRAME

IRDY

TRDY

DEVSEL

510 15 20 25 30 35 40 45 50 55 60 66

A[7:2], 0, 1A[7:2], 0, 0

A[19:16]

A[7:2], 1, 0 A[7:2], 1, 1

21485C-45

21485C-46

EBUA_EBA[7:0]

EBD[7:0]

AS_EBOE

EROMCS

EBUA[19:16]

EBDA[15:8]

EBA[7:0]

CLK 12345678910 11 12 13

78 Am79C972

Figure 44. Flash Write from Expansion Bus Data Port

AMD Flash Progr amming

AMD’s Flash products are programmed on a byte-by-

byte basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed

by the program set-up command and data write cycles.

Addresses are latched on the falling edge of EBWE

and the data is latched on the rising edge of EBWE.

The rising edge of EBWE begins programming.

Upon executing the AMD Flash Embedded Program

Algorithm command sequence, the Am79C972 con-

troller is not requi red to provide further controls or tim-

ing. The AMD Flash product will compliment EBD[7]

during a read of the programmed location until the pro-

gramming is complete. The host software should poll

the programmed address until EBD[7] matches the

programmed value.

AMD Flash byte programming is allowed in any se-

quence and across sector boundaries. Note that a data

0 cannot be programmed back to a 1. Only erase oper-

ations can convert zeros to ones. AMD Flash chip

erase is a six-bus cycle operation. There are two unlock

write cycles, followed by writing the set-up command.

Two more unlock cycles are then followed by the chip

erase command. Chip erase does not require the user

to program the device prior to erasure. Upon e xecuting

the AMD Flash Embedde d Erase Algor ithm com mand

sequence, the Flash de vice will program and verify the

entire memory for an all zero data pattern prior to elec-

trical erase. The Am79C972 controller is not required

to provide any c ontrols or timings during th ese opera-

tions. The automatic erase begins on the rising edge of

the last EBWE pulse in the command sequence and

terminates when the data on EBD[7] is 1, at which time

the Flash device returns to the read mode. Polling by

the Am79C972 controller is not required during the

erase sequence. The following FLASH programming-

table exce r pt (Table 9) sh ows the comm and seque nce

for byte programming and sector/chip erasure on an

AMD Flash device. In the following table, PA and PD

stand for programmed address and programmed data,

and SA stands for sector address.

The Am79C972 controller will support only a single

sector erase per command and not concurrent sector

erasures. The Am79C972 controller will support most

FLASH devices as long as there is no timing require-

ment between the completion of commands. The

FLASH access time cannot be guaranteed with the

Am79C972 controller access mechanism. The

Am79C972 controller will also support only Flash de-

vices that do not require data hold times after write op-

erations.

EBUA_EBA[7:0]

EBD[7:0]

AS_EBOE

EROMCS

EBUA[19:16]

EBDA[15:8]

EBA[7:0]

CLK 12345678910 11 12 13

EBWE

21485C-47

Table 9. Am29Fxxx Flash Command

Command

Sequence

Bus

Write

Cycles

Req’dFirst Bus

Write Cycl e Second Bus

Write Cycle Third Bus

Write C ycle Fourth Bus

Write C ycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Byte Progr am 45555h AAh 2AAAh 55H 5555h A0h PA PD

Chip Erase 65555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h

Sector Erase 65555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h SA 3h

Am79C972 79

SRAM Configuration

The Am79C972 controller supports SRAM as a FIFO

ex tension as well as providing a read/write data path to

the SRAM. The Am79C972 controller contains

12 Kbytes of SRAM.

Internal SRAM Configuration

The SRAM _SIZE (B CR25, bi ts 7-0) programs the size

of the SRAM. SRAM_SIZE can be programmed to a

smaller value than 12 Kbytes.

The SRAM should be programmed on a 512-byte

boundary. However, there should be no accesses to the

RAM space while the Am79C972 controller is running.

The Am79C972 controller assumes that it completely

owns the SRAM while it is in operation. To specify how

much of the SRAM is allocated to transmit and how

much is alloc ated to receive, the user shoul d p rogram

SRAM_BND (BCR26, bits 7-0) with the page boundary

where the receive b uffer begins. The SRAM_BND also

should be programmed on a 512-byte boundary. The

transmit buffer space starts at 0000h. It is up to the user

or the s oftware dr iver to spli t up the memory for trans-

mit or receive; there is no defaulted value. The mini-

mum SRAM size required is four 512-byte pages for

each transmit and receive queue, which limits the

SRAM size to be at least 4 Kbytes.

The SRAM_BND upon H_RESET will be reset to

0000h. The Am79C972 controller will not have any

transmit buffer space unless SRAM_BND is pro-

grammed. The last configuration parameter necessary

is the c lock source used to contr ol the E xpansio n Bus

interface. This is programmed through the SRAM Inter-

face Control register. The externally driven Expansion

Bus Clo ck (EBCLK ) can be used by specif ying a value

of 010h in EBCS (BCR27, bits 5-3). This allows the

user to utilize any clock that may be available.

There are two standard clocks that can be chosen as

well, the PCI clock or the externally provided time base

clock. Use of the internal clock is not recommended.

When the PCI or time base clock is used, the EBCLK

does not have to be driven, but it must be tied to V DD

through a resistor. The user must specify an SRAM

clock (BCR27, bits 5-3) that will not stop unless the

Am79C972 controller is stopped. Otherwise, the

Am79C972 controller will repor t buffer overflows, un-

derflows, corrupt data, and will hang eventually.

The user can decide to use a f ast clock and then divide

down the frequency to get a better duty-cycle if re-

quired. The choices are a divide by 2 or 4 and is pro-

grammed by the CLK_F A C bits (BCR27, bits 2-0). Note

that the Am79C972 controller does not support an

SRAM frequency above 33 MHz regardless of the clock

and clock factor used.

No SRAM Configuration

If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the

SRAM size register, the Am79C972 controller will as-

sume that t her e i s no S RAM present and will rec onfi g-

ure the four internal FIFOs into two FIFOs, one for

transmit and one for receive. The FIFOs will operate

the same as in the PCnet-PCI II controller. When the

SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM

BND (BCR2 6, bits 7-0) ar e ignored by the Am7 9C972

controller. See Figure 45.

Low Latency Receive Configuration

If the LOLATRX ( BCR27, bit 4) bit is set to 1, then the

Am79C972 controller will configure itself for a low la-

tency rec eive confi guration. In this mode, SRAM is r e-

quired at all times. If th e SRAM_S IZE (BCR25 , bits 7-

0) value is 0, the Am7 9C972 controller will not config-

ure for low latency receive mode. The Am79C972 con-

troller will provide a fast path on the receive side

bypassing the SRAM. All transmit traffic will go to the

SRAM, so SRAM_BND (BCR26, bits 7-0) has no

meaning in low latency receive mode. When the

Am79C972 controller has received 16 bytes from the

network , it will start a DMA req uest to the P CI Bus In-

terface Unit. The Am79C97 2 contr oller will not wait for

the first 6 4 bytes to pa ss to check for collisions in L ow

Latency Receive mode. The Am79C972 controller

must be in STOP before switching to this mode. See

Figure 46.

CA UTION: T o provide data integrity when switching

into and out of the low latency mode, DO NOT SET

the FASTSP NDE bit whe n sett ing the SP ND bit. Re -

ceive frames WILL be overwritten and the

Am79C972 controller may give erratic behavior

when it is enabled again.

Direct SRAM Access

The SRAM can be accessed through the Expansion

Bus Data por t (BCR30). To access this data por t, the

user must load the upper address EPADDRU (BCR29,

bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the

user will load the lower 16 bits of address EPADDRL

(BCR28, bits 15-0). To initiate a read, the user reads

the Exp ansion Bus Data Por t (BCR30) . This slave ac-

cess fro m the P CI wil l result i n a r etr y fo r the ver y fir st

access. Su bs equ ent acces ses may give a retry or no t,

depending on whether or not the data is present and

v alid. The direct SRAM access uses the same FLASH/

EPROM access except for accessing the SRAM in

word format instead of byte format. This access is

meant to be a diagno stic access onl y. The SRAM ca n

only be accesse d while t he Am79C9 72 contr oller is in

STOP or SPND (FASTSPNDE is set to 0) mode.

80 Am79C972

Figure 45. Block Diagram No SRAM Configuration

Figure 46. Block Diagram Low Latency Receive Configuration

PCI Bus

Interface

Unit

802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

21485C-48

PCI Bus

Interface

Unit 802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

SRAM

21485C-49

Am79C972 81

EEPROM Interface

The A m79 C972 c on tro ll er c on tai ns a built- in capabil ity

for reading and writing to an external serial 93C46

EEPROM. This built-in capability consists of an inter-

face for direct connection to a 93C46 compatible

EEPROM, an automa tic EE PROM read feature, and a

user-programmable register that allows direct access

to the interface pins.

Automatic EEPROM Read Operation

Shortly after the deassertion of the RST pin, the

Am79C972 controller will read the contents of the

EEPROM that is at tached to the in terface. Beca use o f

this automatic-read capability of the Am79C972 con-

troller, an EEPROM can be used to program many of

the features of the Am79C972 controller at power-up,

allowing system-dependent configuration information

to be stored in the hardware, instead of inside the

device driver.

If an EEP ROM exists on the inter face, the A m79C972

controller will read the EEPROM contents at the end of

the H_RESET operation. The EEPROM contents will

be serially shifted into a temporary register and then

sent to various register locations on board the

Am79C972 controller. Access to the Am79C972 con-

figuration space, the Expansion ROM or any I/O

resource is not possible during the EEPROM read op-

eration. The Am79C972 controller will terminate any

access attempt with the assertion of DEVSEL and

STOP while TRDY is not asser t ed, signal ing to the in i-

tiator to disconnect and retry the access at a later time.

A checksum verification is performed on the data that

is read from the EEPROM. If the checksum verification

passes, PVALID (BC R19, bit 1 5) will b e set to 1 . If the

checksum verification of the EEPROM data fails,

PVALID will be cleared to 0, and the Am79C972 con-

troller wi ll forc e all EEPROM-pr ogrammable BCR reg-

isters back to their H_RESET default values. However,

the content of the Address PROM locations (offsets

0h - Fh from the I/O or memor y mappe d I/O base ad-

dress) will not be cleared. The 8-bit checksum for the

entire 68 bytes of the EEPROM should be FFh.

If no EEP ROM is present a t the time of the automatic

read operation, the Am79C972 controller will recognize

this conditi on and will abor t the automatic read op era-

tion and clear both the PREAD and PVALID bits in

BCR19. All EEPROM-programmable BCR registers

will be assigned their default values after H_RESET.

The content of the Address PROM locations (offsets

0h - Fh from the I/O or memor y mappe d I/O base ad-

dress) will be undefined.

EEPROM Auto-Detection

The Am79C972 controller uses the EESK/LED1/SFBD

pin to dete rmine if an EEPROM is present in the sys-

tem. At the rising edge of CLK during the last clock dur-

ing which RST is asserted, the Am79C972 controller

will sample the value of the EESK/LED1/SFBD pin. If

the sampled value is a 1, then the Am79C972 controller

assumes that an EEPROM is present, and the EE-

PROM read operation begins shortly after the RST pin

is deasserted. If the sampled value of EESK/LED1/

SFBD is a 0, the Am79C972 controller assumes that an

exter nal pulldown device is holding the EESK/LED1/

SFBD pin low, indicating that there is no EEPROM in

the system. Note tha t if the desi gner crea tes a syste m

that contains an LED circuit on the EESK/LED1/SFBD

pin, but has no EEPROM present, then the EEPROM

auto-detection function will incorrectly conclude that an

EEPROM is present in the system. However, this will

not pose a problem for the Am79C972 controller , since

the checksum verification will fail.

Direct Access to the Interface

The user may directly access the port through the

EEPROM register, BCR19. This register contains bits

that can be used to control the interface pins. By per-

forming an appropriate sequence of accesses to

BCR19, the user can effectively write to and read from

the EEPROM. This feature may be used by a system

configurat ion utility to program hardware c onfiguration

information into the EEPROM.

EEPROM-Programmable Registers

The following registers contain configuration informa-

tion that will be programmed automatically during the

EEPROM read operation:

nI/O offsets 0h-Fh Address PROM locations

nBCR2 Miscellaneous Configuration

nBCR4 LED0 Status

nBCR5 LED1 Status

nBCR6 LED2 Status

nBCR7 LED3 Status

nBCR9 Full-Duplex Control

nBCR18 Burst and Bus Control

nBCR22 PCI Latency

nBCR23 PCI Subsystem Vendor ID

nBCR24 PCI Subsystem ID

nBCR25 SRAM Size

nBCR26 SRAM Boundary

nBCR27 SRAM Interface Control

nBCR32 MII Control and Status

nBCR33 MII Address

nBCR35 PCI Vendor ID

nBCR36 PCI Power Management

Capabilities (PMC) Alias Regis-

ter

82 Am79C972

nBCR37 PCI D ATA Register Zero (D ATA0)

Alias Register

nBCR38 PCI DATA Register One (DATA1)

Alias Register

nBCR39 PCI DATA Register Two (DATA2)

Alias Register

nBCR40 PCI DATA Register Three

(DATA3) Alias Register

nBC R41 PCI DATA R egi st er Four (DATA4 )

Alias Register

nBCR42 PCI DATA Regi ster Five (DATA 5)

Alias Register

nBCR43 PCI DATA Register Six (DATA6)

Alias Register

nBCR44 PCI DATA Register Seven

(DATA7) Alias Register

nBCR45 OnNow Pattern Matching

nBCR46 OnNow Pattern Matching

nBCR47 OnNow Pattern Matching

nCSR116 OnNow Miscellaneous

If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)

are cleared to 0, then the EEPROM read has experi-

enced a failure and the content s of the EEPROM pro-

grammable BCR register will be set to default

H_RESET values. The conten t of the Address PROM

locations, however, will not be cleared.

Accesses to the Address PROM I/O locations do not di-

rectly access the Address EEPROM itself. Instead,

these accesses are routed to a set of shadow registers

on board the Am79C972 controller that are loaded with

a copy of the EEPROM c ontents dur ing the automatic

read ope ration th at immedi ately fo llows the H_RE SET

operation.

EEPROM MAP

The automatic EEPROM read operation will access 34

words (i.e., 68 bytes) of the EEPROM. The format of

the EEPROM contents is shown in Table 10 (next

page), begi nning with the byte that resides at the low-

est EEPROM address.

Note: The first bit out of any word locati on in the EE-

PROM is treated as the MSB of the register being pro-

grammed. For example, the first bit out of EEPROM

word location 0 9h wi ll be written into BCR4 , bi t 15; th e

second bit out of EEPROM word location 09h will be

written into BCR4, bit 14, etc.

There are two checksum locations within the EE-

PROM. The first checksum will be used by AMD driver

software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The

va lue of bytes 0 Ch and 0Dh s hould matc h the sum o f

bytes 00h thr ough 0B h and 0Eh and 0Fh. The sec ond

checksum locati on (byte 43 h) is not a checksum total,

but is, instead, a checksum adjustment. The value of

this byte should be such that the total checksum for the

entire 68 bytes of EEPROM data equals the value FFh.

The checksum adjust byte is needed by the Am79C972

controller in order to verify that the EEPROM content

has not been corrupted.

LED Support

The Am79C972 contro ller can support up to fo ur LEDs .

LED outputs LED0, LED1, and LED2 allow for direct

connection of an LED and its supporting pullup device.

In applications that want to use the pin to drive an LED

and also have an EEPROM, it might be necessar y to

buffer t he LED3 c ircuit from the EE PROM connection .

When an LED circuit is directly connected to the

EEDO/LED3/SRD pin, then it is not possible for most

EEPROM devices to sink enough IOL to maintain a valid

low level on the EEDO input to the Am79C972 control-

ler . Use of buffering can be av oided if a low power LED

is used.

Each LED can be programmed through a BCR register

to indicate one or more of the following networ k status

or activities: Collision Status, Full-Duplex Link Status,

Half-Dupl ex Link Status, Receive Match , Receive Sta-

tus, Magic Packet, Disable Transceiver, and Transmit

Status.

Am79C972 83

Table 10. EEPROM Map

The LED pins can be configured to operate in either

open-drain mode (active low) or in totem-pole mode

(active high) . The ou tput c an be stret ched t o allow the

human eye to recognize even short events that last only

several microseconds. After H_RESET, the four LED

outputs are configured as shown in Table 11.

Word

Address Byte

Address Most Significant Byte Byte

Address Least Significant Byte

00h* 01h 2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3)

station physical address for this node. 00h

First byte of the IS O 8802-3 (IEEE/ANSI

802.3) station physical address for this

node, where “first byte” refers to the first

byte to appear on the 802.3 medium.

01h 03h 4th byte of the node address 02h 3rd byte of the node address

02h 05h 6th byte of the node address 04h 5th byte of the node address

03h 07h CSR116[15:8] (OnNow Misc. Config.) 06h CSR116[7:0] (OnNow Misc. Config.)

04h 09h Hardware ID; must be 11h if compatibility to

AMD drive r s is des ire d 08h Reserved location: must be 00h

05h 0Bh User progr ammable spac e 0Ah User programmable sp ace

06h 0Dh MSB of tw o-byte chec ksum , whi ch is the s um

of bytes 00h-0Bh and bytes 0Eh and 0Fh 0Ch LSB of two-byte checksum, which is the

sum of bytes 00h-0Bh and bytes 0Eh and

0Fh

07h 0Fh Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired 0Eh Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired

08h 11h BCR2 [15 :8] (Mi sc ell an eou s Configuration ) 10h BCR2[7:0] (Miscell an eou s Co nfi gur at ion)

09h 13h BCR4[15: 8] (Link Status LED) 12h BCR4[7:0] (Link Status LED)

0Ah 15h BCR5[15 :8] (LED1 Statu s) 14h BCR5[7:0] (LED1 Status)

0Bh 17h BCR6[15 :8] (LED2 Statu s) 16h BCR6[7:0] (LED2 Status)

0Ch 19h BCR7[15 :8] (LED3 S tatu s) 18h BCR7[7:0] (LED3 Status)

0Dh 1Bh BCR9[15:8] (Full-Duplex Control) 1Ah BCR9[7:0] (Full-Duplex Control)

0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)

0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[ 7:0] (PC I Latency)

10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (P CI Subsystem Vendor ID)

11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID)

12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size)

13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary)

14h 29h BCR27[15:8] (SRAM Interface Control) 28h BC R27[ 7:0] (SR AM Interface Control)

15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status)

16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address)

17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID)

18h 31h BCR36[15:8] (Conf. Space byte 43h alias) 30h BCR36[7:0] (Conf. Space byte 42h alias)

19h 33h BCR37[15:8] (DATA_SCALE alias 0) 32h BCR37[7:0] (Conf. Space byte 47h 0 alias)

1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Space. byte 47h 1 alias)

1Bh 75h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Space. byte 47h 2 alias)

1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Space. byte 47h 3 alias)

1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Space. byte 47h 4 alias)

1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 0) 3Ch BCR42[7:0] (Conf. Space. byte 47h 5 alias)

1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 0) 3Eh BCR43[7:0] (Conf. Space. byte 47h 6 alias)

20h 41h BCR44[15:8] (DATA_SCALE alias 0) 40h BCR44[7:0] (Conf. Space. byte 47h 7 alias)

21h 43h Checksum adjust byte for the 68 bytes of the

EEPROM contents. Checksum of the 68 bytes

of the EEPROM should total FFh. 42h Reser ved location: must be 00h

Unused locations - Ignored by device

3Fh 7Fh Reserved 7Eh Reserved

84 Am79C972

Table 11. LED Default Configuration

For each LED register, each of the status signals is

AND’d w ith its en able signal, and these signals ar e all

OR’d tog ether to fo rm a combi ned status signal. Each

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shi ft register is norm ally at logic 0. The OR gate

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asser ted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 47.

Power Savings Mode

Power Management Support

PCnet-F AST+ supports power management as defined

in the PCI Bus Po wer Management Interface Specifica-

tion V1.0 and Network Device Class Power Manage-

ment Reference Specification V1.0.These

specifi cations define the network devic e power states,

PCI power managemen t interfa ce including the Cap a-

bilities Data Structure and power management regis-

ters block defini tions, power manageme nt events, and

OnNow network Wake-up events. In addition,

PCnet-FAST+ supports legacy power management

schemes, such as Remote Wake-Up (RWU) mode.

When the system is in RWU mode, PCI bus power is

on, the PCI clock may be slowed down or stopped, and

the wake-up output pin may drive the CPU's System

Management Interrupt (SMI) line.

Figure 47. LED Control Logic

The general scheme for the PCnet-FAST+ power man-

agement is that when a PCI Wak e-up ev ent is detected,

a signal is generated to cause hardware e xternal to the

PCnet-FAST+ device to put the computer into the work-

ing (S0) mode.

The PCnet-FAST+ device supports three types of

wake-up events:

1. Magic Pac ket Detect

2. OnNow Pattern Match Detect

3. Link State Change

Figure 48 shows the relationship between these Wake-

up events and the various outputs used to signal to the

external hardware.

Note: The OnNOW Pattern Match and Link State

Change only work on the MII interface.

OnNow Wake-Up Sequence

The system software enables the PME pin by setting

the PME_EN bit in the PMCSR register (PCI configura-

tion re gisters, offse t 44h, bit 8) to 1 . When a Wake-up

event is detected, the PCnet-FAST+ device sets the

PME_STATUS bit in the PMCSR register (PCI configu-

ration registers, offset 44h, bit 15). Setting this bit

causes the PME signal to be asserted. Assertion of the

PME signal causes external hardware to wake up the

CPU . The system software then reads the PMCSR reg-

ister of every PCI device in the system to determine

which device asserted the PME signal.

LED

Output Indication Driver Mode Pulse Stretch

LED0 Link Status Open Drain -

Active Low Enabled

LED1 Receive

Status Open Drain -

Active Low Enabled

LED2 -- Open Drain -

Active Low Enabled

LED3 Transmit

Status Open Drain -

Active Low Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse

Stretcher

SPEED_SEL

100E

MPS

MPSE 21485C-50

Am79C972 85

Figure 48. OnNow Functional Diagram

When the software determines that the signal came

from the P Cnet- FAST+ device, it writes to the device’s

PMCSR to put the device into power state D0. The soft-

ware then writes a 0 to the PME_STATUS bit to clear

the bit and turn off the PM E sig nal, and it ca lls the de-

vice’s soft ware driver to tell it that the device is now in

state D0. The system software can clear the

PME_STATUS bit either before, after, or at the same

time that it puts the device back into the D0 state.

Link Change Detect

Link change detect is one of Wake-up events defined

by the OnNow specification and is supported by the

R WU mode. Link Change Detect mode is set when the

LCMODE bit (CSR116, bit 8) is set either by software

or loaded through the EEPROM.

When thi s bit is set, any chan ge in th e Link status will

cause the LCDET bit (CSR116, bit 9) to be set. Whe n

the LCDET bit is set, the RWU pin will be asserted and

the PME_ STATUS bit ( PMCSR regist er, bit 15 ) will be

set. If either the PME_EN bit (PMCSR, bit 8) or the

PME_EN_OVR bit (CSR116, bit 10) are set, then the

PME will also be asserted.

OnNow Pattern Match Mode

In the OnNow Pattern Ma tch Mode, the PC net-FAST+

compares the incoming packets with up to eight pat-

terns stored in the Pattern Match RAM (PMR). The

stored patter ns can b e comp ared with pa r t or all of i n-

coming packets, depending on the pattern length and

the way the PMR is programmed. When a pattern

match has been detected, then PMAT bit (CSR116, bit

7) is set. The setting of the PMAT bit causes the

MPDETECT

MPPEN

MPMODE

MPEN

MPINT

LED

WUMI

Magic Packet

Link Change

LCMODE

Link Change

MPMAT

LCDET

DET

CLR

BCR47 BCR46 BCR45

SET

CLR

SET

CLR

SET

CLR

PMAT

Pattern Match

Input

Pattern

PME_STATUS

Pattern Match RAM (PMR)

PME Status

PME_EN

MPMAT

PME_EN_OVR

LCEVENT

PME

RWU

SET

CLR

POR

H_RESET

POR

21485C-51

86 Am79C972

PME_ STATUS bit (PMCSR , bit 15) to be set, whic h in

turn will assert the PME pin if the PME_EN bit

(PMCSR, bit 8) is set.

Pattern Match RAM (PMR)

PMR is organized as an array of 64 words by 40 bits as

shown in Figure 49. The PMR is programmed indirectly

through the BC Rs 45, 46 , and 47 . Wh en the BC R45 is

writ ten and the PMAT_M ODE bit (BCR45, bi t 7) i s set

to 1, Patter n Matc h logic is e nabled. No bu s accesses

into the P MR are possi ble when the PMAT_MO DE bit

is set, and BCR46, BCR47, and all other bits in BCR45

are ignored. When PMAT_MODE is set, a read of

BCR45 returns all bits undefined except for

PMAT_MODE. In order to access the contents of the

PMR, PMAT_MODE bit should be programmed to 0.

When BCR45 is wri tten to set th e PMAT_MO DE bit to

0, the Patter n Mat ch logi c is d is abled and a cc ess es t o

the PMR are possible. Bits 6:0 of BCR45 specify the

address of the PMR word to be accessed. Writing to

BCR45 does not immediately affect the contents of the

PMR. Following the write to BCR45, the PMR word ad-

dressed by the bits 6:0 of the BCR45 may be read by

reading BCR45, BCR46, and BCR47 in any order. To

write to the PMR word, the write to BCR45 must be

foll owed by a wr ite to BCR46 and a wr ite to BCR47 i n

that order to complete the operation. The PMR will not

actually be written until the write to BCR47 is complete.

The first two 40-bit words in this RAM serve as pointers

and contain enable bits for the eight possible match

patterns. The remainder of the RAM contains the

match patterns and associated match pattern control

bits. The byte 0 of the first word contains the Patter n

Enable bits. Any bit position set in this byte enables the

corresponding match pattern in the PMR, as an e xam-

ple if the bit 3 is set, then the Patter n 3 is enabled for

matching . Bytes 1 t o 4 in the fi rst word are poin ters to

the beginning of the patterns 0 to 3, and bytes 1 to 4 in

the second word are pointers to the beginning of the

patterns 4 to 7, respectively. Byte 0 of the second word

has no function associated with it.The byte 0 of the

words 2 to 63 is th e Control Fi eld of the PM R. Bit 7 of

this field is the End of Pac ket (EOP) bit. When this bit is

set, it indicates the end of a pattern in the PMR. Bits 6-

4 of the Control Field byte are the SKIP bits. The value

of the SKIP field indicates the number of the Dwords to

be skipped bef ore the pattern in this PMR word is com-

pared wi th data from t he incoming frame. A maximum

of seven Dwords may be skipped. Bits 3-0 of the Con-

trol Field byte are the MASK bits. These bits corre-

spond to the pattern match bytes 3-0 of the same PMR

word (PMR bytes 4-1). If bit n of this field is 0, then byte

n of the corresponding pattern word is ignored. If this

field is programmed to 3, then bytes 0 and 1 of the pat-

tern match field (bytes 2 and 1 of the word) are used

and bytes 3 an d 2 ar e ign ored in t he patte r n ma tchin g

operation.

The contents of the PMR are not affected by

H_RESET, S_RESET, or STOP. The contents are un-

defined after a power up reset (POR).

Magic Packet Mode

In Magic P ac ket mode, the PCnet-FAST+ controller re-

mains f ully powered up (all VDD an d VDDB pins mus t

remain a t their supp ly levels). T he devic e will not g en-

erate any bus master transfers. No transmit operations

will be initiated on the network. The device will continue

to recei ve frames from the networ k, bu t all frames will

be autom atically flus hed from the rece ive FIFO. Slave

accesses to the PCnet-FAST+ cont roll er ar e st ill p ossi -

ble. A Magic Packet is a frame that is addressed to the

PCnet-FAST+ controller and contains a data sequence

anywhere in its data field made up of 16 consecutive

copies of the device’s physical address (PADR[47:0]).

The PCnet-FAST+ controller will search incoming

frames until it finds a Magic Packet frame. It starts

scanni ng for the s equence a fter processi ng the lengt h

field of the frame. The data sequence can begin any-

where in the data field of the frame, but must be de-

tected b efore the PCn et-FAST+ controller reaches the

frame’s FCS field. Any deviation of the incoming

frame’s data sequence from the required physical ad-

dress sequence, even by a single bit, will prevent the

detection of that frame as a Magic Packet frame.

The PCnet-FAST+ controller supports two different

modes of ad dress d etecti on for a Magic Packet frame.

If MPPLBA (CSR5, bit 5) or EMPPLBA (CSR116, bit 6)

are at their default value of 0, the PCnet-FAST+ con-

troller wil l only detect a Ma gic Packet frame if the de s-

tination address of the packet matches the content of

the physical address register (PADR). If MPPLBA or

EMPPLB A are se t to 1, the des tination addr ess of the

Magic Packet frame can be unicast, multicast, or

broadcast.

Note: The setting of MPPLBA or EMPPLBA only ef-

fects the address detection of the Magic Packet frame.

The Magic Packet’s data sequence must be made up

of 16 consecutive copies of the device’s physical ad-

dress (PADR[47:0]), regardless of what kind of destina-

tion address it has.

Am79C972 87

Figure 49. Pattern Ma tch RAM

There are two general methods to place the PCnet-

FAST+ into the Magic Packet mode. The first is the soft-

ware method. In t his method, eithe r th e BIOS or other

software, sets the MPMODE bit (CSR5, bit 1). Then

PCnet-FAST+ controller must be put into suspend

mode (see description of CSR5, bit 0), allowing any

current network activity to finish. Finally , either PG must

be deasserted (hardware control) or MPEN (CSR5, bit

2) must be set to 1 (software control).

Note: FASTSPNDE (CSR7, bit 15) has no meaning in

Magic Packet mode.

The second method is the hardware method. In this

method, the MPPEN bit (CSR116, bit 4) is set at power

up by the loading of the EEPROM. This bit can also be

set by software. The PCnet-FAST+ will be place d in the

Magic Packet Mode when either the PG input is

deasserted or the MPEN bit is set. WUMI out put wi ll be

asserted when the PCnet-FAST+ is in the Magic

Packet mode. Magic Packet mode can be disabled at

any time by asserting PG or clearing MPEN bit.

When the PCnet-FAST+ controller detects a Magic

Packet frame, it sets the MPMAT bit (CSR116, bit 5),

the MPINT bit (CSR5, bit 4), and the PME_STATUS bit

(PMCSR, bit 15). The setting of the MPMAT bit will also

cause the RWU pin to be asserted and if the PME_EN

or the PME_EN_OVR bits are set, then the PME will be

asserted as well. If IENA (CSR0, bit 6) and MPINTE

(CSR5, bit 3) are set to 1, INTA will be asser ted. Any

one of the four LED pins can be programmed to indi-

cate that a Magic Packet frame has been received.

BCR 47 BCR 46 BCR 45

BCR Bit Number 15 8 7 0 15 8 7 0 15 8

PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0

Pattern Match

RAM Address Pattern Match RAM Bit Number

39 32 31 24 23 16 15 8 7 0 Comments

0P3 pointer P2 pointer P1 pointer P0 pointer Pattern Enable

bits First Address

1P7 pointer P6 pointer P5 pointer P4 pointer X Second

Address

2Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Control Start Patte rn

2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End Pattern P1

JData Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start P attern Pk

J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m +1 Data Byte 4m+0 Pattern Control End Pattern Pk

63 Last Address

7 6 5 4 3 2 1 0

EOP SKIP MASK

21485C-52

88 Am79C972

MPSE (BCR4 -7, bit 9) must be s et to 1 to enable that

function.

Note: The polarity of the LED pin can be programmed

to be active HIGH by setting LEDPOL (BCR4-7, bit 14)

to 1.

Once a Magic Packet frame is detected, the PCnet-

FAST+ controller will discard the frame internally, but

will not resume normal transmit and receive operations

until PG is as s erted or MP E N is cl ea re d. O nc e b oth o f

these events has occurred, indicating that the system

has detec ted the Ma gic Packet and is awake, the co n-

troller will continue polling receive and transmit de-

scr iptor r ings where it le ft off. It is not necess ar y to r e-

initial ize the d evice. If the pa r t is reinitial ized, th en the

descriptor locations will be reset and the PCnet-FAST+

controller will not start where it left off.

If magic packet mode is disabled by the assertion of

PG, then in order to immediately re-enable Magic

Packet mode, the PG pin must remain asser ted for at

least 200 ns before it is deasserted. If Magic Packet

mode is di sa bled by clearing M PE N bit, then it may be

immediately re-enabled by setting MPEN back to 1.

The PCI bus interface clock (CLK) is not required to be

running while the device is operating in Magic Packet

mode. Either of the INTA, the LED pins, RWU or the

PME signal may be used to indicate the receipt of a

Magic Packet frame when the CLK is stopped. If the

system wishes to stop the CLK, it will do so after en-

abling the Magic P acket mode.

CAUTION: To prevent unwanted inte rrupts from other

active par ts of th e PCnet-FAST+ controller, ca re must

be taken to mask all likely interruptible events during

Magic Packet mode. An example would be the inter-

rupts from the Media Independent Interface, which

could occur while the device is in Magic Packet mode.

IEEE 1149.1 (1990) Test Ac ces s Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-lev el continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. The following paragraphs summarize

the IEEE 1149.1-compatible test functions imple-

mented in the Am79C9 72 con troll er.

Boundary Scan Circuit

The boundary scan test circuit requires f our pins (TCK,

TMS, TDI, and TDO), defined as the Tes t Acces s Port

(TAP). It includes a finite state machine (FSM), an in-

struct io n reg is ter, a d at a reg is ter arr a y, a nd a p o w er- on

reset circuit. Inter nal pull-up resistors are provid ed for

the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK), and the Test

Mode Select (TMS) pins. An independent power-on

reset circuit is provided to ensure that the FSM is in the

TEST_LOGIC_RESET state at power-up. Therefore,

the TRST is not provided. The FSM is also reset when

TMS and TDI are high for five TCK periods.

Supported Instructions

In addition to the min imum IEEE 1149.1 requir ements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP, and SET-

BYP) are provided to fur ther ease board-level testing.

All unused instruction codes are reserved. See Table

12 for a summary of supported instructions.

Instruction Register and Decoding Logic

After th e TAP FSM i s res et, the IDCODE i nstr uction is

always invoked. The decoding logic gives signals to con-

trol the data flow in the Data registers according to the

current instructi on.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the P arallel Output Stage, respectively.

There are four possible operation modes in the BSR

cell shown in Table 13.

Table 12. IEEE 1149.1 Supported Instruction

Summary

Instructio

Name

Instructi

Code Description Mode

Selected

Data

EXTEST 0000 External Test Test BSR

IDCODE 0001 ID Code

Inspection Normal ID REG

SAMPLE 0010 Sample

Boundary Normal BSR

TRIBYP 0011 Force Float Normal Bypass

SETBYP 0100 Control

Boundary To

1/0 Test Bypass

BYPASS 1111 Bypass Scan Normal Bypass

Table 13. BSR Mode Of Operation

1Capture

2Shift

3Update

4System Function

Am79C972 89

Other Data Registers

Other data registers are the following:

1. Bypass Register (1 bit)

2. Device ID register (32 bits) (Table 14).

Note: The content of the Device ID register is the

same as the conten t of CSR88.

NAND Tree Testing

The Am79C972 controller provides a NAND tree test

mode to allow checking connectivity to the device on a

pri nted ci rcui t bo ard. T he NAND tre e is built on al l P CI

bus, TBC_EN, and EAR pins.

NAND tree testing is enabled by asserting RST. PG

input should be driven HIGH during NAND tree testing.

All PCI bus signals will become inputs on the assertion

of RST. The result of the NAND tree test can be ob-

served on the INTA pin. See Figure 50.

Pin 143 (RST) is the first input to the NAND tree. Pin

144 (CLK) is the second input to the NAND tree, fol-

lowed by pi n 1 45 (GNT). All other PCI bus signals fol-

low, counterclockwise, with pin 129 (EAR) being the

last. Table 15 shows the complete list of pins connected

to the NAND tree.

RST must be asserted low to start a NAND tree test se-

quence. Initially, all NAND tree inputs except RST

should be driven high. This will result in a high output

at the INTA pin. If the NAND tree inputs are driven from

high to low in the same order as they are connected to

build the NAND tree, INTA will toggle ev ery time an ad-

ditional input is driven low. INTA will change to low,

when CLK is driven low and all other NAND tree inputs

stay high. INTA will toggle back to high, when GNT is

addition ally driven low. The square wave will continue

until all NAND tree inputs are driven low. INTA will be

high, when all NAND tree inputs are driven low. See

Figure 51.

Some of the pins connected to the NAND tree are out-

puts in normal mode of operation. They must not be

driven from an external source until the Am79C972

controller is configured for NAND tree testing.

Figure 50. NAND Tree Circuitry

Table 14. Device ID Register

Bits 31-28 Version

Bits 27-12 Part Number (0010 0110 0010 0100)

Bits 11-1 Ma nuf act urer ID. The 11 bi t manuf ac turer ID

cod f or AMD is 000000 00001 in acc ordance

with JEDEC publication 106-A.

Bit 0 Always a logic 1

Am79C972

Core

RST (pin143)

CLK (pin 144)

VDD

GNT (pin 145)

EAR (pin 129)

INTA (pin 142)

MUX

....

INTA

21485C-53

90 Am79C972

Figure 51. NAND Tree Waveform

Table 15. NAND Tree Pin Sequence

NAND Tree

Input No. Pin No. Name NAND Tree

Input No. Pin No. Name

1143 RST 18 7AD20 35 34 AD13

2144 CLK 19 9AD19 36 36 AD12

3145 GNT 20 10 AD18 37 37 AD11

4146 REQ 21 12 AD17 38 39 AD10

5148 AD31 22 14 AD16 39 40 AD9

6151 AD30 23 15 C/BE2 40 41 AD8

7152 AD29 24 17 FRAME 41 42 C/BE0

8153 AD28 25 18 IRDY 42 44 AD7

9154 AD27 26 20 TRDY 43 46 AD6

10 156 AD26 27 22 DEVSEL 44 47 AD5

11 158 AD25 28 23 STOP 45 49 AD4

12 159 AD24 29 25 PERR 46 50 AD3

13 160 C/BE3 30 26 SERR 47 52 AD2

14 1IDSEL 31 28 PAR 48 54 AD1

15 2AD23 32 30 C/BE1 49 55 AD0

16 4AD22 33 31 AD15 50 123 TBC_EN

17 6AD21 34 33 AD14 51 129 EAR

RST

CLK

GNT

REQ

AD[31:0]

C/BE[3:0]

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

INTA

FFFFFFFF

0000FFFF

... ... ...

21485C-54

Am79C972 91

Reset

There are four different types of RESET operations that

may be performed on the Am79C972 device,

H_RESET, S_RESET, STOP, and POR. The following

is a description of each type of RESET operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C972 reset

operation that has been created by the proper asser-

tion of the RST pi n of the Am79C972 device whi le the

PG pin is HIGH. When the minimum pulse width timing

as specified in the RST pin description has been satis-

fied, then an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR reg-

isters to thei r default val ue. Note that ther e are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for deta ils.

H_RESET will clear most of the registers in the PCI

configuration space. H_RESET will cause the micro-

code program to jump to its reset state. Following the

end of the H_RESET operation, the Am79C972 con-

troller will attempt to read the EEPROM device through

the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the

Am79C972 controller will be in 16-bit I/O mode after

the reset operation. A DWord write operation to the

RDP (I/ O offs et 10h ) mu st be per f ormed to set the de -

vice into 32-bit I/O mode.

S_RESET

Software Reset (S_RESET) is an Am79C972 reset op-

eration tha t has be en created by a read access to the

Reset register, which is located at offset 14h in Word

I/O mode or offset 18h in DWord I/O mode from the

Am79C972 I/O or memory mapped I/O base address.

S_RESET will reset all of or some portions of CSR0, 3,

4, 15, 80, 100, and 124 to default values. For the iden-

tity of individual CSRs and bit locations that are af-

fected by S_RESET, see the individual CSR register

descriptions. S_RESET will not affect any PCI configu-

ration space location. S_RESET will not affect any of

the BCR register values. S_RESET will cause the mi-

crocode program to jump to its reset state. Following

the end of the S_RESET operation, the Am79C972

controller will not attempt to read the EEPROM device.

After S_ RESET, the host must perfor m a full re-ini tial-

ization of the Am79C972 controller before starting net-

work activity. S_RESET will cause REQ to deassert

immed iat ely. STOP (CSR0, bit 2 ) or SPND (CSR5, bi t

0) can be used to terminate any pending bus master-

ship request in an orderly sequence.

S_RESET term ina tes all networ k acti vity abruptly. The

host can use the suspend mode (SPND, CSR5, bit 0)

to terminate all network activity in an orderly sequence

before issuing an S_RESET.

STOP

A STOP reset is generated by the assertion of the

STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,

when the stop bit currently has a value of 0, will initiate

a STOP reset. If the STOP bit is already a 1, then writ-

ing a 1 to the STOP bit will not generate a ST OP reset.

ST OP will reset all or some portions of CSR0, 3, and 4

to default values. For the identity of individual CSRs

and bit locations that are aff ected by STOP, see the in-

dividual CSR register descriptions. STOP will not affect

any of the BCR and PCI configuration space locations.

STOP w ill c ause the m icroco de p rogram to jum p to its

reset state. Following the end of the STOP operation,

the Am79C972 controller will not attempt to read the

EEPROM device.

Note: STOP w ill not cause a deasser tion of the REQ

signal, if it happens to be active at the time of the write

to CSR0. The Am79C972 controller will wait until it

gains bus ownership and it will first finish all scheduled

bus master accesses before the STOP reset is exe-

cuted.

ST OP terminates all network activity abruptly. The host

can use the suspend mode (SPND, CSR5, bit 0) to ter-

minate all network activity in an orderly sequence be-

fore setting the STOP bit.

Power on Reset

Power on Reset (POR) is generated when the

Am79C972 controller is powered up. POR generates a

har dw ar e reset (H_RE SE T). In ad dit ion , it clea rs some

bits that H_RESET does not affect.

Software Access

PCI Configuration Registers

The Am79C972 controller implements the 256-byte

configuration space as defined by the PCI specification

rev ision 2.1. The 64 -byte he ader includes a ll registers

required to identify the Am79C972 controller and its

function. Additionally, PCI Power Management Inter-

face registers are implemented at location 40h - 47h.

The layout of the Am79C972 PCI configuration space

is shown in Table 16.

The PCI c onfiguratio n regi sters ar e acces sible only by

configuration cycles. All multi-byte numeric fields follow

little endian byte ordering. All write accesses to Re-

served locations have no effect; reads from these loca-

tions will return a data value of 0.

I/O Resources

The Am79C972 controller requires 32 bytes of address

space for access to all the various internal registers as

we ll a s t o some set u p informati o n st or ed in a n external

serial EEPROM. A software reset port is av ailab le, too .

92 Am79C972

Table 16. PCI Configuration Space Layout

The Am79C972 controller supports mapping the ad-

dress space to both I/O and memory space. The value

in the PCI I/O Base Address register determines the

start address of the I/O addres s space. The regi ster is

typically programmed by the PCI configuration utility

after system power-up. The PCI configuration utility

must also set the IOEN bit in the PCI Command register

to enable I/O accesses to the Am79C972 controller. For

memory mapped I/O access, the PCI Memory Mapped

I/O Base Address register controls the start address of

the memory space. The MEMEN bit in the PCI Com-

mand register must also be set to enable the mode. Both

base address registers can be active at the same time.

The Am7 9C972 con troller supp or ts two modes for ac -

cessing the I/O resources. For backwards compatibility

with AMD’s 16- bit E thernet controlle rs, Word I/O is th e

default mode after power up. The de vice can be config-

ured to DWord I/O mode by software.

I/O Registers

The Am79C972 controller registers are divided into two

groups. The Control and Status Registers (CSR) are

used to confi gure the Ethernet MAC eng ine and to ob-

tain status information. The Bus Control Registers

(BCR) are u sed to c onf igu re the bus in terface unit an d

the LEDs. Both sets of registers are accessed using in-

direct addre ss in g.

The CSR and BCR share a common Register Address

Por t (RAP). There are, however, separate data por ts.

The Register Data Port (RDP) is used to access a

CSR. The BCR Data Port (BDP) is used to access a

BCR.

In order to acc ess a par ticular CSR locati on, the RAP

should first be written with the appropriate CSR ad-

dress. The RDP will then po int to the selected CS R. A

read of the RDP will yield the selected CSR data. A

write to the RDP will write to the selected CSR. In order

to access a particular BCR location, the RAP should

first be wr it ten with the app ropr iate B CR addres s. The

BDP will th en poi nt t o the sel ect ed BCR. A re ad o f th e

BDP will yield the selected BCR data. A write to the

BDP will write to the selected BCR.

Once t he RA P has been written with a value, the RAP

value remains unchan ged until another RAP write oc-

curs, or until an H_ RESET or S_RESET occurs. RAP

is cleared to all 0s when an H_RESET or S_RESET oc-

curs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C972 controller allows for connection of a

serial EEPROM. The first 16 bytes of the EEPROM will

be automatically loaded into the Address PROM

(APROM) space a fter H_RESET. A dditionally, the first

six bytes of the EEPROM will be loaded into CSR12 to

CSR14. The Address PROM space is a convenient

place to store the value of the 48-bit IEEE station ad-

dress. It can be overwritten by the host computer and

its content has no effect on the operation of the control-

ler. The software must copy the station address from

the Address PROM space to the initialization block in

31 24 23 16 15 8 7 0 Offset

Device ID Vendor ID 00h

Status Command 04h

Base-Class Sub-Class Programming IF Revision ID 08h

Reserved Header Type Latency Timer Reserved 0Ch

I/O Base Address 10h

Memory Mapped I/O Base Address 14h

Reserved 18h

Reserved 1Ch

Reserved 20h

Reserved 24h

Reserved 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CAP-PTR 34h

Reserved 38h

MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch

PMC NXT_ITM_PTR CAP_ID 40h

DATA_REG PMCSR_BSE PMCSR 44H

Reserved .

Reserved FCh

Am79C972 93

order for the receiver to accept unicast frames directed

to this station.

The six bytes of the IEEE station address occupy the

first six locations of the Address PROM space. The

next six bytes are reserved. Bytes 12 and 13 should

match the value of the checksum of bytes 1 through 11

and 14 and 15. Bytes 14 and 15 should each be ASCII

“W” (57h). The above requirements must be met in

order to be compatible with AMD driver software.

APROMWE bit (BCR2, bit 8) must be set to 1 to enable

write access to the Address PROM space.

Reset Register

A read of the Reset register creates an internal soft-

ware reset (S_RESET) pulse in the Am79C972 control-

ler. The internal S_RESET pulse that is generated by

this access is different from both the assertion of the

hardware RST pin ( H_RESET ) a nd fr om th e asse rtion

of the software STOP bit. Specifically, S_RESET is the

equivalent of the a ssertion of the RST p in (H _R ES ET )

ex cept that S_RESET has no effect on the BCR or PCI

Configuration space locations.

The NE2100 LANCE-based family of Ethernet cards

requires that a write access to the Reset register fol-

lows each read access to the Reset register. The

Am79C972 controller does not have a similar require-

ment. The write access is not required and does not

have any effect.

Note: The Am79C972 controller cannot service any

slave accesses for a v ery short time after a read access

of the Reset register, because the internal S_RESET

operation takes about 1 µs to finish. The Am79C972

control le r will terminate all sl ave accesses wit h the as -

sertion of DEVSEL and STOP while TRDY is not as-

serted, signaling to the initiator to disconnect and retry

the access at a later time.

Word I/O Mode

After H_RESET, the Am79C972 controller is pro-

grammed to operate in Word I/O mode. D WIO (BCR18,

bit 7) will be cleared to 0. Table 17 shows how the 32

bytes of address space are used in Word I/O mode.

All I/O resou rces must be acce ssed in word quan tities

and on word addresses. The Address PROM locations

can also be read in byte quantities. The only allowed

DWord operation is a write access to the RDP, which

s witches the device to DW ord I/O mode. A read access

other than l isted in th e table below will yield un define d

data, a write operation may cause unexpected repro-

gramming of the Am79C972 control registers. Table 18

shows legal I/O accesses in Word I/O mode.

Double Word I/O Mode

The Am79C972 controller can be configured to operate

in DWord (32-bit) I/O mode. The software can invoke

the DWIO mode by performing a DWord write access

to the I/O location at offset 10h (RDP ). The dat a of the

write access must be such that it does not affect the in-

tended operation of the Am79C972 controller. Setting

the device into 32-bit I/O mode is usually the first oper-

ation after H_RESET or S_RESET. The RAP register

will point to CSR0 at that time. Writing a value of 0 to

CSR0 is a safe operation. DWIO (BCR18, bit 7) will be

set to 1 as an indic ation th at the Am 79C972 c ontr oller

operates in 32-bit I/O mode.

Note: Even though the I/O resource mapping changes

when th e I/O mo de settin g cha nges, the RDP loca tio n

offset is the same for both modes. O nce the DW IO bit

has been set to 1, only H_RESET can clear it to 0. The

DWIO mod e settin g is unaffected by S_RESET or set-

ting of the S TOP bit. Table 19 shows how the 32 bytes

of address space are used in DWord I/O mode.

All I/O resources must be accessed in DWord quanti-

ties and on DWord addresses. A read access other

than listed in Table 20 will yield undefined data, a write

operation may cause unexpected reprogramming of

the Am79C972 control registers.

Table 17. I/O Map In Word I/O Mode (DWIO = 0)

Offset No. of

Bytes Register

00h - 0Fh 16 APROM

10h 2RDP

12h 2RAP (shared by RDP and BDP)

14h 2Reset Register

16h 2BDP

18h - 1Fh 8Reserved

94 Am79C972

Table 20. Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

Table 18. Legal I/O Accesses in Word I/O Mode (DWIO = 0)

AD[4:0] BE[3:0] Type Comment

0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch

0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh

0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh

0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh

0XX00 1100 RD Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or

Ch and Dh

0XX10 0011 RD Word read of APR O M lo cat ion s 3 h (MSB) a nd 2 h (L SB), 7h an d 6 h, Bh and Ah o r

Fh and Eh

10000 1100 RD Word read of RDP

10010 0011 RD Word read of RAP

10100 1100 RD Word read of Reset Register

10110 0011 RD Word read of BDP

0XX00 1100 WR Word write to APROM lo cations 1h (MSB) and 0h (LS B ), 5h an d 4h, 8h and 9h or

Ch and Dh

0XX10 0011 WR W ord write to APR OM locat ions 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or

Fh and Eh

10000 1100 WR Word write to RDP

10010 0011 WR Word write to RAP

10100 1100 WR Word write to Reset Register

10110 0011 WR Word write to BDP

10000 0000 WR DWord write t o RDP,

switches device to DWord I/O mode

Table 19. I/O Map In DWord I/O Mode (DWIO = 1)

Offset No. of Bytes Register

00h - 0Fh 16 APROM

10h 4RDP

14h 4RAP (shared by RDP and

BDP)

18h 4Reset Register

1Ch 4BDP

AD[4:0] BE[3:0] Type Comment

0XX00 0000 RD

DWord read of APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h or Fh to

10000 0000 RD DWord read of RDP

10100 0000 RD DWord read of RAP

11000 0000 RD DWord read of Reset

0XX00 0000 WR

DWord write to APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h or Fh to

10000 0000 WR DWord write to RDP

10100 0000 WR DWord write to RAP

11000 0000 WR DWord write to Reset

Am79C972 95

USER ACCESSIBLE REGISTERS

The Am7 9C97 2 controll er has thre e ty pes of us er re g-

isters: the PCI configu ration regist ers, the Contro l and

Status registers (CSR), and the Bus Control registers

(BCR).

The Am79C972 controller implements all PCnet-ISA

(Am79C960) registers, all C-LANCE (Am79C90) regis-

ters, plus a number of additional registers. The

Am79C972 CSRs are compatible upon power up with

both the PCnet-ISA CSRs and all of the C-LANCE

CSRs.

The PCI configuration registers can be accessed in any

data width. All other registers must be accessed ac-

cording to the I/O mode that is currently selected.

When WIO mode is selected, all other register loca-

tions are defined to be 16 bits in width. When DWIO

mode is selected, all these register locations are de-

fined to be 32 bits in width, with the upper 16 bits of

most register locations marked as reserved locations

with u ndefin ed values. When per fo r min g regis ter writ e

operations in D WIO mode, the upper 16 bits should al-

ways be written as zeros. When performing register

read operations in DWIO mode, the upper 16 bits of

I/O resources should alw ays be regarded as ha ving un-

defined values, except for CSR88.

The Am79C972 registers can be divided into four

groups: PCI Configuration, Setup, Running, and Test.

Registers not included in any of these categories can

be assumed to be inten ded for diagnostic purposes.

nPCI Configuration Registers

These registers are intended to be initialized by the

system initialization procedure (e.g., BIOS device ini-

tialization routine) to program the operation of the

Am79C972 controller PCI bus interface.

The following is a list of the registers that would typi-

cally need to be programmed once during the initializa-

tion of the Am79C972 controller within a system:

—PCI I/O Base Address or Memory Mapped I/O

Base Address register

—PCI Expansion ROM Base Address register

—PCI Interrupt Line register

—PCI Latency T ime r regis te r

—PCI Status register

—PCI Command register

—OnNow register

nSetup Registers

These registers are intended to be initialized by the de-

vice driver to program the operation of various

Am79C972 control ler features.

The following is a list of the registers that would typi-

cally ne ed to be pr ogrammed onc e during the setu p of

the Am79C 972 co ntroller w ithin a sys tem. The c ontrol

bits in each of these registers ty pically do not need to

be modified once they have been written. However,

there are no restrictions as to how many times these

registers may actually be accessed. Note that if the de-

fault power up values of any of these registers is ac-

ceptable to the application, then such registers need

never be accessed at all.

Note: Registers marked with “^” may be programma-

ble through the EEPROM read operation and, there-

fore, do not necessarily need to be written to by the

system initialization procedure or by the driver soft-

wa re. Regist ers mark ed wi th “*” will be initialized by the

initialization block read operation.

CSR1 Initialization Bloc k Address[15:0]

CSR2* Initialization Bloc k Address[31:16]

CSR3 Interrupt Masks and Deferral Control

CSR4 Test and Features Control

CSR5 Exte nded Contr ol and Inte rr u pt

CSR7 Exte nded Contr ol and Inte rr u pt2

CSR8* Logical Address Filter[15:0]

CSR9* Logical Address Filter[31:16]

CSR10* Logical Address Filter[47:32]

CSR11* Logical Address Filter[63:48]

CSR12*^ Physic al Add r ess[1 5:0]

CSR13*^ Physical Address[31:16]

CSR14*^ Physical Address[47:32]

CSR15* Mode

CSR24* Base Address of Receive Ring Lower

CSR25* Base Address of Receive Ring Upper

CSR30* Base Address of Transmit Ring Lower

CSR31* Base Address of Transmit Ring Upper

CSR47* Transmit Polling Interval

CSR49* Receive Polling Interval

CSR76* Receive Ring Length

CSR78* Transmit Ring Length

CSR80 DMA Transfer Counter and FIFO Thresh-

old Control

CSR82 Bus Activity Timer

CSR100 Memory Error Timeout

CSR116^ OnNow Miscellaneous

CSR122 Recei ver Packet Al ign men t Control

96 Am79C972

CSR125^ MAC Enhanced Configuration Control

BCR2^ Miscella neou s Configuratio n

BCR4^ LED0 Status

BCR5^ LED1 Status

BCR6^ LED2 Status

BCR7^ LED3 Status

BCR9^ Full-Duplex Control

BCR18^ Bus and Burst Control

BCR19 EEPROM Control and Status

BCR20 Software Style

BCR22^ PCI Latency

BCR23^ PCI Subsystem Vendor ID

BCR24^ PCI Subsystem ID

BCR25^ SRAM Size

BCR26^ SRAM Boundary

BCR27^ SRAM Interface Control

BCR32^ MII Control and Status

BCR33^ MII Address

BCR35^ PCI Vendor ID

BCR36 PCI Power Management Capabilities

(PMC) Alias Register

BCR37 PCI DATA Register Zero (DATA0) Alias

BCR38 PCI DATA Register One (DATA1) Alias

BCR39 PCI DATA Register Two (DATA2) Alias

BCR40 PCI DATA Register Three (DATA3) Alias

BCR41 PCI DATA Register Four (DATA4) Alias

BCR42 PCI DATA Register Five (DATA5) Alias

BCR43 PCI D ATA Register Six (D ATA6) Alias Reg-

ister

BCR44 PCI DATA Register Seven (DATA7) Alias

BCR45 OnNow Pa ttern Matc hi ng Regis ter 1

BCR46 OnNow Pa ttern Matc hi ng Regis ter 2

BCR47 OnNow Pa ttern Matc hi ng Regis ter 3

nRunning Registers

These reg isters are in tended to be use d by the device

driver software after the Am79C972 controller is run-

ning to access status information and to pass control

information.

The following is a list of the registers that would typi-

cally ne ed to be peri odically read and perhaps wr itten

duri ng the norm al run nin g ope ratio n of the Am7 9C97 2

controller within a system. Each of these registers con-

tains control bits, or status bits, or both.

RAP Register Address Port

CSR0 Am79C972 Controller Status

CSR3 Interrupt Masks and Deferral Control

CSR4 Test and Features Control

CSR5 Extended Control and Interrupt

CSR7 Extended Control and Interrupt2

CSR112 Missed Frame Count

CSR114 Receive Collision Count

BCR32 MII Control and Status

BCR33 MII Address

BCR34 MII Management Data

nTest Registers

These registers are intended to be used only for testing

and diagnos ti c purposes. Those r egi ste rs not include d

in any of the above lists can be assumed to be intended

for diagnostic purposes.

PCI Configuration Registers

PCI Vendor ID Register

Offset 00h

The PCI V endor ID register is a 16-bit register that iden-

tifies the manufacturer of the Am79C972 controller.

AMD’s Vendo r ID is 1022h. Note tha t this vendor ID is

not the same as the Manufacturer ID in CSR88 and

CSR89. The vendor ID is assigned by the PCI Special

Interest Group.

The PCI Vendor ID register is located at offset 00h in

the PCI Configuration Space. It is read onl y.

This register is the same as BCR35 and can be written

by the EEPROM.

PCI Device ID Register

Offset 02h

The PCI Device ID register is a 16-bit register that

uniquely identifies the Am79C972 controller within

AMD's product line. The Am79C972 Device ID is

2000h. Note that thi s Device ID is not the sam e as th e

Par t number in CSR88 and CSR89. The Device ID is

assigned by AMD. The Device ID is the same as the

Am79C972 97

PCnet-PCI II (Am79C970A) and PCnet-FAST

(Am79C971) devices.

The PCI Device ID register is located at offset 02h in

the PCI Configuration Space. It is read only.

PCI Command Register

Offset 04h

The PCI Command register is a 16-bit register used to

control the gross functionality of the Am79C972 con-

troller. It controls the Am79C972 controller’s ability to

generate and respond to PCI bus cycles. To logically

disconn ect the Am 79C972 device from all PCI bus cy-

cles except configuration cycles, a v alue of 0 should be

written to this register.

The PCI Command register is located at offset 04h in

the PC I Configuration Sp ace. It is read a nd writt en by

the host.

Bit Name Description

15-10 RES Re served locati ons. Read as ze-

ros; write operations have no ef-

fect.

9 FBTBEN Fast Back-to-Back Enable. Read

as zero; write operations have no

effect. The Am79C972 controller

will not generate Fast Back-to-

Back cycles.

8 SERREN SERR Enable. Controls the as-

ser tio n of t he S ERR pin. SERR is

disabled when SERREN is

cleared. SERR will be asserted

on detecti on of an addre ss p arity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN is cleared by

H_RESET and is not effecte d by

S_RESET or by setting the STOP

bit.

7 RES Reserved location. Read as ze-

ros; write operations have no ef-

fect.

6 PERREN Parity Error Response Enable.

Enables the parity error response

functions. When PERREN is 0

and the Am79C972 controller de-

tects a parity error, it only sets the

Detected Parity Error bit in the

PCI Status register. When PER-

REN is 1, the Am79C972 control-

ler asserts PERR on the

detection of a data parit y err or. It

also sets the DATAPERR bit (PCI

Status register, bit 8), when the

data parity error occurred during

a master cycle. PERREN also

enables reporting address parity

errors thr oug h th e S ERR pin and

the SERR bit in the PCI Status

PERREN is cleared by

H_RESET and is not affecte d by

S_RESET or by setting the STOP

bit.

5 VGASNOOP VGA Palette Snoop. Read as ze-

ro; write operations have no ef-

fect.

4 MWI EN Memo ry Wr it e and Inv ali da te Cy-

cle Enable. Read as zero; write

operations have no effect. The

Am79C972 controller only gener-

ates Memory Write cycles.

3 SCYCEN Special Cycle Enable. Read as

zero; write operations have no ef-

fect. The Am79C972 controller

ignores all Special Cycle opera-

tions.

2 BMEN Bus Master Enable. Setting

BMEN enables the Am79C972

controller to become a bus mas-

ter on the PCI bus. The host must

set BMEN before setting the INIT

or STRT bit in CSR0 of the

Am79C972 controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

1 MEMEN Memory Space Access Enable.

The Am79 C972 controller will ig-

nore all memory accesses when

MEMEN is cleared. The host

must set MEMEN before the first

memory ac ce ss to the device.

For memory mapped I/O, the

host must program the PCI Mem-

ory Mapped I/O Base Address

dress before setting MEMEN.

For accesses to the Expansion

ROM, the host must pr ogram the

PCI Expansion ROM Base Ad-

dress register at offset 30h with a

98 Am79C972

valid memory address before set-

ting MEMEN. The Am79C972

control ler will onl y respond to ac-

cesses to the Expansion ROM

when both ROMEN (PCI Expan-

sion ROM Base Address register,

bit 0) and MEMEN are set to 1.

Since MEMEN also enables the

memory mapped access to the

Am79C972 I/O resources, the

PCI Memory Mapped I/O Base

Address register must be pro-

grammed with an address so that

the device does no t claim cycles

not intended for it.

MEMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

0 IOEN I/O Space Access Enable. The

Am79C972 controller will ignore

all I/O accesses when IOEN is

cleared . The hos t mus t set IOE N

before the first I/O access to the

device. The PCI I/O Base Ad-

dress register must be pro-

grammed with a valid I/O address

before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

PCI Status Register

Offset 06h

The PCI Status register is a 16-bit register that contains

status infor mation for the PCI bus related events. It is

located at offset 06h in the PCI Configuration Space.

Bit Name Description

15 PERR Parity Error. PERR is set when

the Am79C972 controller detects

a parity error.

The Am79C972 controller sam-

ples the AD[31:0], C/BE[3:0 ], a nd

the PAR li nes fo r a par it y e rro r a t

the following times :

• In slave mode, during the ad-

dress phase of any PCI bus com-

mand.

• In slave mode , for al l I/O, me m-

ory and configuration write com-

mands that select the Am79C972

controller when data is trans-

ferred (TRDY and IRDY are as-

serted).

• In master mode, during the data

phase of all memory read com-

mands.

In master mode, during the data

phase of the memory write com-

mand, the Am79C972 controller

sets the PERR bit if the target re-

ports a data parity error by as-

serting t he PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the Am79C972

controller and cleared by writing a

1. Writing a 0 has no effect.

PERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

14 SERR Signaled SERR. SERR is set

when the Am79C972 controller

detects an address parity error

and both SERREN and PERREN

(PCI Command register, bits 8

and 6) are set.

SERR is set by the Am79C972

controller and cleared by writing a

1. Writing a 0 has no effect.

SERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

13 RMABORT Received Master Abort. RM-

ABORT is set when the

Am79C972 controller terminates

a master cycle with a master

abort sequence.

RMABORT is set by the

Am79C972 controller and

cleared by writing a 1. Writing a 0

has no effect. RMABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

12 RTABORT Received Target Abort. RT-

ABORT is set when a target ter-

minates an Am79C972 master

cycle with a target abort se-

quence.

Am79C972 99

RTABORT is set by the

Am79C972 controller and

cleared by writing a 1. Writing a 0

has no effect. RTABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

11 STABORT Send Target Abort. Read as ze-

ro; write operations have no ef-

fect. The Am79C972 controller

will never terminate a slave ac-

cess with a target abort se-

quence.

STABORT is read only.

10-9 DEVSEL Device Select Timing. DEVSEL

is set to 01b (medium), which

means that the Am79C972 con-

troller will assert DEVSEL two

clock per io ds aft er F RA ME is as-

serted.

DEVSEL is read only.

8 DATAPERR Data Parity Error Detected.

DATAPERR is set when the

Am79C972 controller is the cur-

rent bus master and it detects a

data parity error and the Parity

Error Response enable bit (PCI

Command register, bit 6) is set.

During the data phase of all

memory read commands, the

Am79C972 controller checks for

parity error by sampling the

AD[31:0] and C/BE[3:0] and the

PAR lines. During the data phase

of all memory write commands,

the Am79C972 controller checks

the PERR input to detect whether

the target has reported a parity

error.

DATAPERR is set by the

Am79C972 controller and

cleared by writing a 1. Writing a 0

has no effect. DATAPERR is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

7 FBTBC Fast Back-To-Back Capable.

Read as one; write operations

have no effect. The Am79C972

control ler is c apa bl e of a ccep t in g

fast back-to-back transactions

with the first transaction address-

ing a different target.

6-5 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

4 NEW_CAP New Capabilities. This bit indi-

cates whether this function imple-

ments a list of extended

capabilities such as PCI power

management. When set, this bit

indicates the presence of New

Capabilities. A value of 0 means

that this fu nction does n ot imple-

ment New Capabilities.

Read as one; write operations

have no effect. The Am79C972

controller supports the Linked

Addit ion al Capa bilit ies List .

3-0 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

PCI Revision ID Register

Offset 08h

The PCI Revision ID register is an 8-bit register that

specifies the Am79C972 controller revision number.

The value of this register is 3Xh with the lower four bits

being silicon-re vision dependent.

The PCI Revision ID register is located at offset 08h in

the PCI Configuration Space. It is read onl y.

PCI Programming Interface Register

Offset 09h

The PCI Programming Interface register is an 8-bit reg-

ister that identifies the programming interface of

Am79C972 controller. PCI does not define any specific

es. The value of this register is 00h.

The PCI Programming Interface register is located at

offset 09h in the PCI Configuration Space. It is read only.

PCI Sub-Class Register

Offset 0Ah

The PCI Sub-Class register is an 8-bit register that iden-

tifies specifically the function of the Am79C972 control-

ler . The value of this register is 00h which identifies the

Am79C972 device as an Ethernet controller.

The PC I Sub-Cl ass regi ster is located at offse t 0Ah in

the PCI Configuration Space. It is read onl y.

100 Am79C972

PCI Base-Class Register

Offset 0Bh

The PCI Base-Class register is an 8-bit register that

broadly classifies the function of the Am79C972 con-

troller . The value of this register is 02h which classifies

the Am79C972 device as a network controller.

The PCI Base-Class register is located at offset 0Bh in

the PCI Configuration Space. It is read only.

PCI Latency Timer Register

Offset 0Dh

The PCI Latency Timer register is an 8-bit register that

specifies the minimum guaranteed time the Am79C972

controller will control the bus once it starts its bus mas-

tership period. The time is measured in clock cycles.

Every time the Am79C972 controller asserts FRAME at

the beginning of a bus mastership period, it will copy the

va lue of the PCI La tency Timer register into a c ounter

and star t counting down. The counter will freeze at 0.

When the system arbiter removes GNT while the

counter is non-zero, the Am79C972 controller will con-

tinue with its dat a transfe rs. It will only release the bus

when the counter has reached 0.

The PCI Latency Timer is only significant in burst trans-

actions, where FRAME stays asserted until the last data

phase. In a non-burst transaction, FRAME is only as-

ser ted dur ing the addres s phase. The inter nal laten cy

counter will be cleared and suspended while FRAME is

deasserted.

All eight bits of the PCI Latency Timer register are pro-

grammable. The host should rea d the Am79C 972 PCI

MIN_GNT and PCI MAX_LA T registers to determine the

latency requirements for the device and then initialize

the Latency Timer register with an appropriate value.

The PCI Latency Timer register is located at offset 0Dh

in the PCI Configuration Space. It is read and written by

the host. T h e PC I L aten cy T imer r egis ter is c le ared by

H_RESET and is not effected by S_RESET or by setting

the STOP bit.

PCI Header Type Register

Offset 0Eh

The PCI Header Type register is an 8-bit register that

describes the format of the PCI Configuration Space

loca tions 10h to 3C h and that identi fies a device to be

single or multi-function. The PCI Heade r Type regis ter

is located at address 0Eh in the PCI Configuration

Space. It is read only.

Bit Name Description

7 FUNCT Single-function/multi-function de-

vice. Read as zero; write opera-

tions have no effect. The

Am79C972 controller is a single

function device.

6-0 LAYOUT PCI configuration space layout.

Read as zeros; write operations

have no effect. The layout of the

PCI configuration space loca-

tions 10h to 3Ch is as shown in

the table at the beginning of this

section.

PCI I/O Base Address Register

Offset 10h

The PCI I/O Base Address register is a 32-bit register

that determines the location of the Am79C972 I/O re-

sources in all of I/O spa ce. It is locate d at offs et 10h in

the PCI Configuration Space.

Bit Name Description

31-5 IOBASE I/O base address most significant

27 bits. These bit s are written by

the host to s pe cify the l ocati on o f

the Am79C972 I/O resources in

al l of I/ O sp ace. IOB AS E mus t be

written with a valid address be-

fore the Am79C972 controller

slave I/O mode is turned on by

setting the IOEN bit (PCI Com-

mand register, bit 0).

When the Am79C972 controller

is enable d for I/O mode (IOEN is

set), it monitors the PCI bus for a

valid I/O command. If the value

on AD[31:5] during the address

phase of the cycles matches the

value of IOBASE, the Am79C972

control ler wil l dri ve DEV SEL ind i-

cating it will respond to the ac-

cess.

IOBASE is read and written by

the host. IOBASE is cleared by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

4-2 IOSIZE I/O size requirements. Read as

zeros; write operations have no

effect.

IOSIZE indicates the size of the

I/O space the Am79C972 control-

ler requires. When the host writes

a value of FFF F FFFFh to the I/O

Bas e Addr ess reg ister , it w ill r ead

back a value of 0 in bits 4-2. That

indicates an Am79C972 I/O

space requirement of 32 bytes.

Am79C972 101

1 RES Reserved location. Read as zero;

write operatio ns hav e no effec t.

0 IOSPACE I/O space indicator. Read as one;

write operations have no effect.

Indicating that this base address

address.

PCI Memory Mapped I/O Base Address Register

Offset 14h

The PCI Memory Mapped I/O Base Address register is

a 32-bit register that determines the location of the

Am79C9 72 I/O resou rces in all of memor y space. It is

located at offset 14h in the PCI Configuration Space.

Bit Name Description

31-5 MEMBASE Memory mapped I/O base ad-

dress most significant 27 bits.

These bits are written by the host

to specify the location of the

Am79C972 I/O resources in all of

memory s pace . MEMB ASE m ust

be written with a valid address

before the Am79C972 controller

slave mem ory mapped I/O mode

is turned on by setting the ME-

MEN bit (PCI Command register,

bit 1).

When the Am79C972 controller

is enabled for memory mapped

I/O mode (MEMEN is set), it mon-

itors the PCI bus for a valid mem-

ory command. If the value on

AD[31:5] during the address

phase of the cycles matches the

value of MEMBASE, the

Am79C972 controller will drive

DEVSEL indicating it will respond

to the access.

MEMBASE is read and written by

the host. MEMBASE is cleared

by H_RESE T and is not affec ted

by S_RESET or by setting the

STOP bit.

4 MEMSIZE Memory mapped I/O size re-

quiremen ts . Read as ze r os; writ e

operations have no effect.

MEMSIZE indicates the size of

the memory space the

Am79C972 controller requires.

When the host writes a value of

FFFF FFFFh to the Memory

Mapped I /O B ase Addres s regis-

ter, it will read back a value of 0 in

bi t 4. That indica tes a Am79 C972

memory space requirement of 32

bytes.

3 PREFETCH Prefetchable. Read as zero; write

operations have no effect. Indi-

cates that memory space con-

trolled by this base address

registe r is not prefetch able. Data

in the memory mapped I/O space

cannot be prefetched. Because

one of the I/O resources in this

address space is a Reset regis-

ter, the order of the read access-

es is important.

2-1 TYPE Memory type indicator. Read as

zeros; write operations have no

effect. Indicates that this base ad-

dress reg is ter is 3 2 bi ts wid e an d

mapping can be done anywhere

in the 32-bit memory space.

0 MEMSPACE Memory space indicator. Read

as zero; write operations have no

effect. Indicates that this base ad-

dress register describes a memo-

ry base address.

PCI Subsystem Vendor ID Register

Offset 2Ch

The PCI Su bsy st em Vend or ID r e gis ter i s a 1 6- bit reg-

ister that together with the PCI Subsystem ID uniquely

identifies the add-in card or subsystem the Am79C972

controller is used in. Subsystem V endor IDs can be ob-

tained from the PCI SIG. A value of 0 (the default) indi-

cates that the Am79C972 controller does not support

subsystem identification. The PCI Subsystem Vendor

ID is an alias of BCR23, bits 15-0. It is programmable

through the EEPROM.

The PCI Subsystem V endor ID register is located at off-

set 2Ch in the PCI Configuration Space. It is read only.

PCI Subsystem ID Register

Offset 2Eh

The PCI Subsystem ID register is a 16-bit register that

together with the PCI Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the Am79C972

controlle r is used in . The value of the Subsys tem ID is

up to the system vendor. A value of 0 (the default) indi-

cates that the Am79C972 controller does not support

subsyste m identifica tion. The P CI Subsyst em ID is a n

alias of BCR24, bits 15-0. It is programmable through

the EEPROM.

The PCI Subsystem ID register is located at offset 2Eh

in the PCI Configuration Space. It is read only.

102 Am79C972

PCI Expansion ROM Base Address Register

Offset 30h

The PCI Expansion ROM Base Address register is a

32-bit regis ter that defi nes the base addre ss, size and

address alig nment of an Expa nsion ROM. It is locate d

at offset 30h in the PCI Configuration Space.

Bit Name Description

31-20 ROMBASE Expansion ROM base address

most significant 12 bits. These

bits are written by the host to

specify the location of the Expan-

sion ROM in all of memory space.

ROMBASE must be written with a

valid address before the

Am79C972 Expansion ROM ac-

cess is enabled by setting

ROMEN (PCI Expansion ROM

Base Ad dr es s reg is ter , b it 0) an d

MEMEN (PCI Command register,

bit 1).

Since the 12 mos t signific ant bits

of the base address are program-

mable, th e host c an map the Ex-

pansion ROM on any 1M

boundary.

When the Am79C972 controller

is enabled for Expansion ROM

access (ROMEN and MEMEN

are set to 1), it monitors the PCI

bus for a valid memory com-

mand. If the value on AD[31:2]

during the address phase of the

cycle falls between ROMBASE

and ROMBASE + 1M - 4, the

Am79C972 controller will drive

DEVSEL indicating it will respond

to the access.

ROMBASE is read and written by

the host. ROMBASE is cleared

by H_RESE T and is not affec ted

by S_RESET or by setting the

STOP bit.

19-1 ROMSIZE ROM size. Read as zeros; write

operation have no effect. ROM-

SIZE indicates the maximum size

of the Expansion ROM the

Am79C972 controller can sup-

port. The ho st can dete rmine th e

Expansion ROM size by writing

FFFF FFFFh to the Expansion

ROM Base Address register. It

will read back a value of 0 in bit

19-1, indicating an Expansion

ROM size of 1M.

Note that ROMSIZE only speci-

fies the maximum size of E xpan-

sion ROM the Am79C972

controller supports. A smaller

ROM can be used, too. The actu-

al size of the code in the Expan-

sion ROM is always determined

by reading the Expansion ROM

header.

0 ROMEN Expansion ROM Enable. Written

by the host to enable access to

the Expansion ROM. The

Am79C972 controller will only re-

spond to a cces ses to th e Exp an-

sion ROM when both ROMEN

and MEMEN (PCI Command reg-

ister, bit 1) are set to 1.

ROMEN is read and written by

the host. ROMEN is cleared by

H_RESET an d is not effected by

S_RESET or by setting the STOP

bit.

PCI Capabilities Pointer Register

Offset 34h

Bit Name Description

7-0 CAP_PTR The PCI Capabilities pointer

points to a linked list of capabili-

ties implemented on this device.

This register has a default value

of 40h.

The PCI Capabilities register is

located at offset 34h in the PCI

Configuration Space. It is read

only.

PCI Interrupt Line Register

Offset 3Ch

The PCI Inter rupt Line registe r is an 8-bit regist er that

is used to communicate the routing of the interrupt.

This register is written by the POST software as it ini-

tializes the Am79C972 controller in the system. The

regist er is read by the network driver to deter min e the

interrupt channel which the POST software has as-

signed to the Am79C97 2 controller. The PCI Interrupt

Line register is not modified by the Am79C972 control-

ler. It has no eff ect on the operation of the device.

The PCI Int er r upt Li ne reg ist er is lo ca ted a t offs et 3C h

in the PCI Configuration Space. It is read and written by

Am79C972 103

the host. It i s clea re d by H_RESE T a nd i s no t affected

by S_RESET or by setting the STOP bit.

PCI Interrupt Pin Register

Offset 3Dh

This PCI Interrupt Pin register is an 8-bit register that

indicates the interrupt pin that the Am79C972 controller

is u sing. T he v alue fo r the Am 79C972 Inter rupt P in reg -

ister is 01h, which corresponds to INTA.

The PCI Interrupt Pin register is located at offset 3Dh

in the PCI Configuration Space. It is read only.

PCI MIN_GNT Register

Offset 3Eh

The PCI MIN_GNT register is an 8-bit register that

specifies the minimum length of a burst period that the

Am79C972 device needs to keep up with the network

activity. The length of the burst period is calculated as-

suming a clock rate of 33 MHz. The register value spec-

ifies the time in units of 1/4 µs. The PCI MIN_GNT

mended th at t he BCR2 2 be programmed t o a value o f

1818h.

The host sh ould use the value in this r egist er to deter-

mine the setting of the PCI Latency Timer register.

The PCI MIN_GNT register is located at offset 3Eh in

the PCI Configuration Space. It is read only.

PCI MAX_LAT Register

Offset 3Fh

The PCI MAX_LA T register is an 8-bit register that spec-

ifies the maximum arbitration latency the Am79C972

control ler can sustai n without cau sing problems to the

netw ork activi ty. The regist er val ue specif ies the ti me in

units of 1/4 µs. The MAX_LAT register is an alias of

BCR22, bits 15-8. It is recommended that BCR22 be

programmed to a value of 1818h.

The host sh ould use the value in this r egist er to deter-

mine the setting of the PCI Latency Timer register.

The PCI MAX_LAT register is located at offset 3Fh in

the PCI Configuration Space. It is read only

PCI Capability Ide ntifier Register

Offset 40h

Bit Name Description

7-0 CAP_ID This register, when set to 1, iden-

tifies the linked list item as bein g

the PCI Power Management reg-

isters. T his regis ter has a default

value of 1h.

The PCI Capabilities Identifier

the PCI Configuration Space. It is

read only.

PCI Next Item Pointer Register

Offset 41h

Bit Name Description

7-0 NXT_ITM_PTR

The Next Item Pointer Register

points to the starting address of

the next capability. The pointer at

this offset is a null pointer, indi-

cating that this is the last capabil-

ity in the linked list of the

capabilities. This register has a

default value of 0h.

The P CI Next P ointe r Regist er is

located at offset 41h in the PCI

Configuration Space. It is read

only.

PCI Power Management Capabilities Register

(PMC)

Offset 42h

Note: All bits of this register are loaded from

EEPROM. Th e regi st er is al iased to BCR36 for testin g

purposes.

Bit Name Description

15-11 PME_SPT PME Support. This 5-bit field indi-

cates the power states in which

the function may assert PME. A

value of 0b for any bit indicates

that the function is not capable of

ass er t ing t h e PM E si gn al w h il e in

that power state.

Bit(11) XXXX1b - PME can be

asserted from D0.

Bit(12) XXX1Xb - PME can be

asserted from D1.

Bit(13) XX1XXb - PME can be

asserted from D2.

Bit(14) X1XXXb - PME can be

asserted from D3hot.

Bit(15) 1XXXXb - PME can be

asserted from D3cold.

Read onl y.

104 Am79C972

10 D2_SPT D2 Support. If this bit is a 1, this

function supports the D2 Power

Management State.

Read only.

9 D1_SPT D1 Support. If this bit is a 1, this

function supports the D1 Power

Management State.

Read only.

8-6 RES Reserved locations. Written as

zeros and read as undefined.

5 DSI Device Specific Initialization.

When this bit is 1, it indicates that

special initialization of the func-

tion is require d (beyo nd the sta n-

dard PCI configuration header)

before the generic class device

driver is able to use it.

Read only.

4 AUXPS Auxiliary Power Source. This bit

is only meaningful if bit 15

(D3cold supporting PME) is a 1.

When this bit is also a 1, it indi-

cates that support for PME in

D3cold requires auxiliary power

supp li e d by th e sy st e m by way of

a proprietary delivery vehicle.

A 0 in this bit indicates that the

function supplies its own auxiliary

power sour ce .

If the function does not support

PME while in D3cold, (bit15=0)

then this fie ld must alwa ys retu r n

Read only.

3 PME_CLK PME Clock. When t his bit is a 1 ,

it indicates that the function relies

on the pr esen ce o f the PCI c lock

for PME o peration. Wh en this bit

is a 0 it indicates that no PCI

clock is required for the function

to generate PME.

Functions that do not support

PME generation in any state

must return 0 for this field.

Read only.

2-0 PMIS_VER Power Management Interface

Specification Version. A value of

001b indicates that this function

complies with the revision 1.0 of

the PCI Power Management In-

terface Specification.

PCI Power Management Control/St atus Register

(PMCSR)

Offset 44h

Bit Name Description

15 PME_STATUS PME Status. This bit is set when

the function would normally as-

sert the PME s ignal independen t

of the state of the PME_EN bit.

Writing a 1 to this bit will clear it

and cause the function to stop as-

serting a PME (if enabled). Writ-

in g a 0 has no effect.

If the function supports PME from

D3cold then this bit is sticky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

Read/write accessible always.

Sticky bit. This bit is reset by

POR. H_RESET, S_RESET, or

setting the STOP bit has no ef-

fect.

14-13 DATA_SCALE

Data Scale. This two bit read-

only field indicates the scaling

factor to b e used when inter pret-

ing the value of the Data register.

The value and meaning of this

field will vary depending on the

DATA_SCALE field.

Read onl y.

12-9 DATA_SEL Data Select. This optional four-bit

field is used to selec t which data

is repo rted thro ugh the Data reg-

ister and DATA_SCALE field.

Read/write accessible always.

Sticky bit. This bit is reset by

POR. H_RESET, S_RESET, or

setting the STOP bit has no ef-

fect.

Am79C972 105

8 PME_EN PME Enable. When a 1,

PME_EN en ables the functi on to

assert PM E. When a 0, PME as-

sertion is disabled.

This bit defaults to “0” if the func-

tion does not support PME gener-

ation from D3cold.

If the function supports PME from

D3cold, the n this bi t is stic ky and

must be explicitly cleared by the

operating system each time the

operating system is initially loa d-

ed.

Read/write accessible always.

Sticky bit. This bit is reset by

POR. H_RESET, S_RESET, or

setting the STOP bit has no ef-

fect.

7-2 RES Reserved locations. Read only.

1-0 PWR_STATE Power State. This 2-bit field is

used both to determine the cur-

rent power state of a function and

to set the function into a new

power sta te. The de fin ition of th e

field values is given below.

00b - D0.

01b - D1.

10b - D2.

11b - D3.

These bits can be written and

read, but their contents have no

effect on th e operat ion of the d e-

vice.

Read/write accessible always.

PCI PMCSR Bridge Support Extensions Register

Offset 46h

Bit Name Description

7-0 PM CSR _BSE The PCI PM CSR Bridge Suppor t

Extensions Register is an 8-bit

Extensions are not supported.

This register has a default value

of 00h.

The PCI PM CSR Bridge Suppor t

Extensions register is located at

offset 46h in the PCI Configura-

tion Space. It is read only.

PCI Data Register

Offset 47h

Note: All bits of this register are loaded from EE-

PROM. The register is aliased to lower bytes of the

BCR37-44 for testing purposes.

Bit Name Description

7-0 DATA_REG The PCI Data Register is an 8-bit

Power Management Interface

Specification” version 1.0 for a

more detailed description of this

The PCI DATA register is located

at offset 47h in the PCI Configu-

ration Space. It is read only.

RAP Register

The RAP (Register Address P ointer) register is used to

gain access to CSR and BCR registers on board the

Am79C972 controller. The RAP contains the address

of a CSR or BCR.

As an example of R AP use, con si der a r ead ac ces s t o

CSR4. In order to access this register, it is necessar y

to first load the value 0004h into the RAP by performing

a wri te ac cess t o the RAP o ffset of 12h ( 12h wh en WI O

mode has been selected, 14h when DWIO mode has

been selected). Then a second access is performed,

this time to the RDP offset of 10h (for either WIO or

DWIO m ode). The RDP ac cess is a read access, and

since RAP has just been loaded with the value of 0004h,

the RDP read will yield the contents of CSR4. A read of

the BDP at this time (offset of 16h when WIO mode has

been selected, 1Ch when DWIO mode has been select-

ed) will yield the contents of BCR4, since the RAP is

used as the pointer into both BDP and RDP space.

RAP: Register Address Por t

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 RES Reserved locations. Read and

written as zeros.

7-0 RAP Reg ister Addr ess Por t. The value

of these 8 bits determines which

CSR or BCR will be accessed

when an I/O access to the RDP

or BDP po rt, respectiv ely, is per-

formed.

A write acces s to undefi ned CSR

or BCR lo cations may cause un-

expected reprogramming of the

106 Am79C972

Am79C972 control registers. A

read access will yield undefined

values.

Read/Write accessible always.

RAP is cleared by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

Control and Status Registers

The CSR spac e is accessible by performing ac cesses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will depend

upon the current setting of th e RAP. RAP ser ves as a

pointer into the CSR space.

CSR0: Am79C972 Controller Status and Control

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 ERR Error is set by the OR of CERR,

MISS, and MERR. ERR remains

set as long as any of the error

flags are true.

Read accessible always. ERR is

read only. Write operations are

ignored.

14 RES Reserved locations. Read/Write

accessible always. Read returns

zero.

13 CERR Collision Error is set by the

Am79C972 controller when the

device operates in half-duplex

mode and the collision inputs to

the GPSI port failed to activate

within 20 network bit times after

the chip terminated transmission

(SQE Test). This feature is a

transceiver test feature. CERR

reporting is disabled when the

GPSI port is active and the

Am79C9 72 co ntrol ler oper a tes in

full-duplex mode.

When the MII port is selected,

CERR is only reported when the

external PHY is operating as a

half-duplex 10BASE-T PHY.

CERR assertion will not result in

an interrupt being generated.

CERR as ser tion w ill s et the E RR

bit.

Read/Write accessible always.

CERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. CERR is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

12 MISS Missed Frame is set by the

Am79C972 controller when it has

lost an incoming receive frame

resulting from a Receive Descrip-

tor not bei ng ava il able. T h is bi t is

the only immediate indication that

receive data has been lost since

there is no current receive de-

scriptor. The Missed Frame

Counter (CSR112) also incre-

ments each time a rece ive fr ame

is missed.

When MISS is set, INTA is as-

serted if IENA is 1 and the mask

bit MISSM (CSR3, bit 12) is 0.

MISS assertion will set the ERR

bit, regardless of the settings of

IENA and MISSM.

Read/Write accessible always.

MISS is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MISS is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

11 MERR Memory Error is set by the

Am79C972 controller when it re-

quests the use of the system in-

terface bus by asserting REQ

and has not received GNT asser-

tion after a p rogrammable lengt h

of time. T he length of time in mi-

croseconds before MERR is as-

serted will depend upon the

setting of the Bus Timeout Regis-

ter (CSR100). The default setting

of CSR100 will give a MERR after

153.6 µs of bus latency.

Am79C972 107

When MERR is set, INTA is as-

serted i f IENA is 1 and the ma sk

bit MERRM (CSR3, bit 11) is 0.

MERR assertion wil l set the E RR

bit, regardless of the settings of

IENA and MERRM.

Read/Write accessible always.

MERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MERR is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

10 RINT Receive Interrupt is set by the

Am79C972 controller after the

last des criptor o f a rec eive fr ame

has been updated by writing a 0

to the OWNership bit. RINT may

also be set when the first descrip-

tor of a receive frame has been

updated by writing a 0 to the

OWNershi p bit if th e LAPP EN bit

of CSR3 has been set to a 1.

When RINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

RINTM (CSR3, bit 10) is 0.

Read/Write accessible always.

RINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. RINT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

9 TINT Transmit Interrupt is set by the

Am79C972 controller after the

OWN bit in the last descriptor of a

transmit frame has been cleared

to indicate the frame has been

sent or an error occurred in the

transmission.

When TINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

TINTM (CSR3, bit 9) is 0.

TINT will not be set if TINTOKD

(CSR5, bit 15) is set to 1 and the

transmission was succes sful.

Read/Write accessible always.

TINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. TINT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

8 IDON Initialization Done is set by the

Am79C972 controller after the

initialization sequence has com-

pleted. When IDON is set, the

Am79C972 controller has read

the initial ization bl ock from mem-

ory.

When IDON is set, INTA is as-

serted if IENA is 1 and the mask

bit IDONM (CSR3, bit 8) is 0.

Read/Write accessible always.

IDON is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. IDON is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

7 INTR Interrupt Flag indicates that one

or more following interrupt caus-

ing conditions has occurred:

EXDINT, IDON, MERR, MISS,

MFCO, RCVCCO, RINT, SINT,

TINT, TXSTRT, UINT, STINT,

MREINT, MCCINT, MIIPDTINT,

MAPINT and the associated

mask or enable bit is pro-

grammed to allow the event to

cause an interrupt. If IE NA is set

to 1 and INTR is set, INTA will be

active. When INTR is set by SINT

or SLPINT, INTA will be active in-

dependent of the state of IENA.

Read acces sib le always . INTR is

read only. INTR is cleared by

clearing all of the active individual

interrupt bits that have not been

masked out.

6 IENA Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will be

disabled regardless of the state

of INTR.

Read/Write accessible always.

IENA is set by writing a 1 and

cleared by writing a 0. IENA is

cleared by H_RESET or

S_RESET and setting the STOP

bit.

5 RXON Receive On indicates that the re-

ceive function is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the START bit is set. If

INIT and START are set together,

108 Am79C972

RXON will not be set until after

the initialization block has been

read in.

Read accessible always. RXON

is read on ly. RXON is c leared by

H_RESET or S_RESET and s et-

ting the STOP bit.

4 TXON Transmit On indicates that the

transmit function is enabled.

TXON is set if DTX (CSR15, bit 1)

is set to 0 after the START bit is

set. If INIT and START are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

This bit will reset if the DXSUFLO

bit (CSR3, bit 6) is reset and there

is an underflow condition encoun-

tered.

Read accessible always. TXON

is read only. TXO N is cleared by

H_RESET or S_RESET and s et-

ting the STOP bit.

3 TDMD Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit De-

scriptor Ring without waiting for

the poll- time cou nter to elapse. If

TXON is not enabled, TDMD bit

will be reset and no Transmit De-

scriptor Ring access will occur.

TDMD is required to be set if the

TXDPOLL bit in CSR4 is set. Set-

ting TDMD while TXDPOLL = 0

merely hastens the Am79C972

controller’s response to a Trans-

mit Descriptor Ring Entry.

Read/Write accessible always.

TDMD is se t by writing a 1. W ri t-

ing a 0 has no effect. TDMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a

Transmit Descriptor. TDMD is

cleared by H_RESET or

S_RESET and set ting the STOP

bit.

2 STOP STOP assertion disables the chip

from all DMA activity. The chip re-

mains inactive until either STRT

or INIT are set. If STOP, STRT

and INIT are all set together,

STOP will override STRT and

INIT.

Read/Write accessible always.

STOP is set by writing a 1, by

H_RESET or S_RESET. Writing

a 0 has no effect. STOP is

cleared by setting either STRT or

INIT.

1 STRT STRT assertion enables

Am79C972 controller to send and

receive frames, and perform buff-

er management operations. Set-

ting STR T clear s the STOP b it. If

STRT and INIT are set together,

the Am79C972 controller initial-

ization will be performed first.

Read/Write accessible always.

STRT is set by writing a 1. Writing

a 0 has no effect. STRT is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

0 INIT INIT assertion enables the

Am79C972 controller to begin the

initialization procedure which

reads in the initialization block

from memory. Setting INIT clears

the STOP bit. If STRT and INIT

are set together, the Am79C972

controller initialization will be per-

formed first. INIT is not cleared

when the initialization sequence

has completed.

Read/Write accessible always.

INIT is set by wri ting a 1. Writing

a 0 has no e ffect. INIT is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

CSR1: Initialization Block Address 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADR[15:0] Lower 16 bits of the address of

the Initialization Block. Bit loca-

tions 1 and 0 must both be 0 to

align the initialization block to a

DWord boundary.

This register is aliased with

CSR16.

Am79C972 109

Read/Write accessible only when

either the ST OP or the SPND bit

is set. Unaffected by H_RESET

or S_RESET, or by setting the

STOP bit.

CSR2: Initialization Block Address 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 IAD R[31:24] If S SIZE32 is s et (BCR20, b it 8),

then the IADR[31:24] bits will be

used strictly as the upper 8 bits of

the initialization block address.

However, if SSIZE32 is reset

(BCR20, bit 8), then the

IADR[31:24] bits will be used to

generate the upper 8 bits of all

bus mastering addresses, as re-

quired for a 32-bit address bus.

Note that the 16-bit software

structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for the

Am79C972 bus master access-

es, while the 32-bit hardware for

which the Am79C972 controller is

intended will require 32 bits of ad-

dress. Therefore, whenever

SSIZE32 = 0, the IADR[31:24]

bits will be appended to the 24-bit

initiali zatio n addre ss, to each 24-

bit descriptor base address and

to each beginning 24-bit buffer

address in order to form complete

32-bit addresses. The upper 8

bits that exist in the descriptor ad-

dress registers and the buffer ad-

dress registers which are stored

on board the Am79C972 c ontrol-

ler will be overwritten with the

IADR[31:24] value, so that CSR

accesses to these registers will

show the 32-bit address that in-

cludes the appended field.

If SSIZE32 = 1, then software will

provide 32-bit pointer values for

all of the shared software struc-

tures - i.e., descriptor bases and

buffer addresses, and therefore,

IADR[31: 24] will not be written to

the upper 8 bits of any of these

resources, but it will be used as

the upper 8 bits of the initializa-

tion address.

This register is aliased with

CSR17.

Read/Write accessible only when

either the STO P or the SPND bit

is set. Unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

7-0 IADR[23:16] Bits 23 through 16 of the address

of the Initialization Block. When-

ever this register is written,

CSR17 is updated with CSR2’s

contents.

Read/Write accessible only when

either the STO P or the SPND bit

is set. Unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR3: Interrupt Masks and Deferral Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-13 RES Reserved locations. Read and

written as zero.

12 MISSM Missed Frame Mask. If MISSM is

set, the MISS bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

MISSM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

11 MERRM Memory Error Mask. If MERRM

is set, the MERR bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

MERRM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

10 RINTM Receive Interrupt Mask. If RINTM

is set, the RINT bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RINTM is cleared by H_RESET

110 Am79C972

or S_RESET and is not affected

by STOP.

9 TINTM Transmit Interrupt Mask. If

TINTM is set , th e TINT b it wi ll b e

masked and unable to set the

INTR bit.

Read/Write accessible always.

TINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

8 IDONM Initialization Done Mask. If

IDONM is set, the IDON bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

IDONM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

7 RES Reserved location. Read and

written as zeros.

6 DXSUFLO Disable Transmit Stop on Under-

flow error.

When DXSUFLO (CSR3, bit 6) is

set to 0, the transmitter is turned

off when an UFLO error occurs

(CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C972 controller gracefully

recovers from an UFLO error. It

scans the transmit descriptor ring

until it finds the start of a new

frame an d s tarts a n ew t ra nsmis -

sion.

Read/Write accessible always.

DXSUFLO is cleared by

H_RESET or S_RESET and is

not affected by STOP.

5 LAPPEN Look Ahead Packet Processing

Enable. When set to a 1, the

LAPPEN bit will cause the

Am79C972 controller to generate

an interrupt following the descrip-

tor write operation to the first buff-

er of a receive frame. This

interrupt will be generated in ad-

dition to t he interrupt tha t is gen-

erated following the descriptor

write operation to the last buffer

of a receive packet. The interrupt

will be signaled through the RINT

bit of CSR0.

Setting LAPPEN to a 1 also en-

ables the Am79C972 controller to

read the STP bit of receive de-

scriptors. The Am79C972 con-

troller will use the STP

information to determine where it

should begin writing a receive

packet’s data. Note that while in

this mode, the Am79C972 con-

troller can write intermediate

packet data to buff ers whose de-

scrip tors do not con tain STP b its

set to 1. Following the write to the

last descriptor used by a p acket,

the Am79C972 controller will

scan through the next descriptor

entries t o locate the ne xt STP bit

that is set to a 1. The Am79C972

controller will begin writing the

next packets data to the buffer

pointed to by that descriptor.

Note that because several de-

scrip tors may be alloc at ed by the

host for each packet, and not all

messages may need all of the de-

scriptors that are allocated be-

tween descriptors that contain

STP = 1, then some descriptors/

buffers may be skipped in the

ring. While performing the search

for the n ext STP bi t that is set t o

1, the Am79C972 controller will

advance through the receive de-

scriptor ring regardless of the

state of ownership bits. If any of

the entries that are examined

during this search indicate

Am79C972 controller ownership

of the descriptor but also indicate

STP = 0, then the Am79C972

controller will reset the OWN bit

to 0 in these entries. If a scanned

entry indicates host ownership

with STP = 0, then the

Am79C972 controller will not al-

ter the entry, but will advance to

the next entry.

When the STP bit is found to be

true, but the descriptor that con-

tains th is setting is not owned by

the Am79C972 controller, then

the Am79C972 controller will stop

advancing through the ring en-

Am79C972 111

tries and begin periodic polling of

this entry. When the STP bit is

found to be true, and the descrip-

tor that contains this setting is

owned by the Am79C972 control-

ler, then the Am79C972 control-

ler will stop advancing through

the ring entries, store the descrip-

tor information that it has just

read, and wait for the next re-

ceive to arrive.

This behavior allows the host

software to pre-assign buffer

space in such a manner that the

header portion of a receive pack-

et will a lways b e w ritten to a par-

ticular memory area, and the data

portion of a receive packet will al-

ways be written to a separate

memory area. The interrupt is

generated when the header bytes

have been written to the header

memory area.

Read/Write accessible always.

The LAPPEN bit will be reset to 0

by H_RESET or S_RESET and

will be unaffected by STOP.

See Appendix B for more infor-

mation on the Lo ok Ah ead P ack-

et Processing concept.

4 DXMT2PD Disable Transmit Two Part Defer-

ral (see Medium Allocation sec-

tion in the Media Access

Management section for more

details). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

Read/Write accessible always.

DXMT2PD is cleared by

H_RESET or S_RESET and is

not affected by STOP.

3 EMBA Enable Modified Back-off Algo-

rithm (see Contenti on Re solu tion

section in Media Access Man-

agement section for more de-

tails). If EMBA is set, a modified

back-off algorithm is implement-

ed.

Read/Write accessible always.

EMBA is cleared by H_RESET or

S_RESET a nd is not affected by

STOP.

2 BSWP Byte Swap. This bit is used to

choose between big and little En-

dian modes of operation. When

BSWP is set to a 1, big Endian

mode is sele cted. Wh en BSWP i s

set to 0, lit tle En dian m ode is se-

lected.

When big End ian mode is se lec t-

ed, the Am79C972 controller will

swap the order of bytes on the AD

bus during a data phase on ac-

cesses to the FIFOs only. Specif-

ically, AD[31:24] becomes Byte

0, AD[23:16] becomes Byte 1,

AD[15:8] becomes Byte 2, and

AD[7:0] becomes Byte 3 when

big Endian mode is selected.

When little Endian mode is se-

lected, the order of bytes on the

AD bus during a data phase is:

AD[31:2 4] is B yte 3, A D[23: 16] is

Byte 2, AD[15:8] is Byte 1, and

AD[7:0] is Byte 0.

Byte swap only affects data

transfers that involve the FIFOs.

Initialization block transfers are

not affected by the setting of the

BSWP bit. Descriptor transfers

are not affected by the setting of

the BSWP bit. RDP, RAP, BDP

and PCI configuration space ac-

cesses are not affected by the

setting o f the B SWP bi t. Add ress

PROM transfers are not affe cted

by the setting of the BSWP bit.

Expansion ROM accesses are

not affected by the setting of the

BSWP bit.

Note that the byte ordering of the

PCI bus is de fined to be little En-

dian. BSW P should not be set to

1 when the Am79 C972 con troller

is used in a PCI bus application.

Read/Write accessible always.

BSWP is cleared by H_RESET or

S_RESET a nd is not affected by

STOP.

1-0 RES Reserved location. The default

value of this bit is a 0. Writing a 1

to this bit ha s no effect on d evi c e

function. If a 1 is written to this bit,

then a 1 will be read back . Exist-

ing drivers may write a 1 to this bit

for compatibility, but new drivers

112 Am79C972

should write a 0 to this bit and

should treat the read value as un-

defined.

CSR4: Test and Features Control

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 RES Reserved location. It is OK for

legacy software to write a 1 to this

location. This bit must be set

back to 0 before setting INIT or

STRT bits.

Read/Write accessible always.

This bit is cleared by H_RESET

or S_RESET and is unaffected by

the STOP bit.

14 DMAPLUS Writing and reading from this bit

has no effect. DMAPLUS is al-

ways set to 1.

13 RES Reserved Location. Written as

zero and read as undefined.

12 TXDPO LL Disabl e Transm it Poll ing. If TXD-

POLL is set, the Buffer Manage-

ment Unit will disable transmit

polling. Likewise, if TXDPOLL is

cleared, automatic transmit poll-

ing is enabled. If TXDPOLL is set,

TDMD bit in CSR0 must be set in

order to initiate a manual poll of a

transmit descriptor. Transmit de-

scriptor polling will not take place

if TXON is reset. Transmit polling

will take place following Receive

activities.

Read/Write accessible always.

TXDPOLL is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

11 APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame, including pad, and ap-

pended after the pad field.

APAD_XMT will override the pro-

gramming of the DXMTFCS bit

(CSR15, bit 3) and of the

ADD_FCS bit (TMD1, bit 29) for

frames shorter than 64 bytes.

Read/Write accessible always.

APAD_XMT is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

10 ASTRP_RCV Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

Read/Write accessible always.

ASTRP_RCV is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

9 MFCO Missed Fram e Counter Overflow

is set by the Am79C972 control-

ler when the Missed Frame

Counter (CSR112 and CSR114)

has wrapped around.

When MFCO is set, INTA is as-

serted if IENA is 1 and the mask

bit MFCOM is 0.

Read/Write accessible always.

MFCO is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MFCO is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

8 MFCOM Missed Fram e Counter Overflow

Mask. If MFCOM is set, the

MFCO bit will be masked and un-

able to set the INTR bit.

Read/Write accessible always.

MFCOM is set to 1 by H_RE SE T

or S_RESET and is not affected

by the STOP bit.

7 UINTCMD User Interrupt Command.

UINTCMD can be used by the

host to generate an interrupt un-

related to any network activity.

When UINTCMD is set, INTA is

asserted if IENA is set to 1.

Am79C972 113

Writing a 1 to UNIT will clear

UNITCMD and stop interrupts.

Read/Write accessible always.

UINTCMD is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

6 UINT User Interrupt. UINT is set by the

Am79C972 controller after the

host has issued a user interrupt

command by setting UINTCMD

(CSR4, bit 7) to 1.

Read/Write accessible always.

UINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. UINT is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

5 RCVCCO Receive Collision Counter Over-

flow is set by the Am79C972 con-

troller when the Receive Collision

Counter (CSR114 and CSR115)

has wrapped around.

When RCVCCO is set, INTA is

asserted if IENA is 1 and the

mask bit RCVCCOM is 0.

Read/Write accessible always.

RCVCCO is cleared by the host

by writ ing a 1. W riti ng a 0 has n o

effect. RCVCCO is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

4 RCVCCOM Receive Collision Counter Over-

flow Mask. If RCVCCOM is set,

the RCVCCO bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RCVCCOM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

3 TXST RT T ransmi t St art status is set by the

Am79C972 controller whenever it

begins transmission of a frame.

When TXSTRT is set, INTA is as-

serted i f IENA is 1 and the ma sk

bit TXSTRTM is 0.

Read/Write accessible always.

TXSTRT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. TXSTRT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

2 TXSTRTM Transmit Start Mask. If TX-

STRTM is set, the TXSTRT bit

will be mas ked an d unable to set

the INTR bit.

Read/Write accessible always.

TXSTRTM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

1-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 TOKINTD Transmit OK Inte rrupt Disable. If

TOKINTD is set to 1, the TINT bit

in CSR0 will not be set when a

transmission was successful.

Only a transmit error will set the

TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5 , bit 14) is set to

1. A transmit descriptor with

LTINT set to 1 will always cause

TINT to be set to 1, independen t

of the success of the transmis-

sion.

Read/Write accessible always.

TOKINTD is cleared by

H_RESET or S_RESET and is

unaffected by STOP.

14 LTINTEN Last Transmit Interrupt Enable.

When set to 1, the LTINTEN bit

will cause the Am79C972 control-

ler to read bit 28 of TMD1 as

LTINT. The setting LTINT will de-

termine if TINT will be set at the

end of the transmission.

114 Am79C972

Read/Write accessible always.

LTINTEN is cleared by

H_RESET or S_RESET and is

unaffected by STOP.

13-12 RES Reserved locations. Written as

zeros and read as undefined.

11 SINT System Interrupt is set by the

Am79C9 72 control ler when it de-

tects a sys tem err or dur i ng a bus

master transfer on the PCI bus.

System e rrors are d ata parity er-

ror, master abort, or a target

abort. Th e settin g of SINT due to

data parity error is not dependent

on the setting of PERREN (PCI

Command register, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to SINT is not depen-

dent on the state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system er ro r.

Read/Write accessible always.

SINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. The state of SINT is not af-

fected b y clea ring a ny o f the PCI

Status register bits that get set

when a data parity error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTA BORT, bit 12 ) occurs.

SINT is cleared by H_RESET or

S_RESET a nd is not affected by

setting the STOP bit.

10 SINTE System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

Read/Write accessible always.

SINTE is set to 0 by H_RESET or

S_RESET a nd is not affected by

setting the STOP bit.

9-8 RES Reserved locations. Written as

zeros and read as undefined.

7 EXDINT Excessive Deferral Interrupt is

set by the Am79C972 controller

when the transmitter has experi-

enced Excessive Deferral on a

transmit frame, where Excessive

Deferral is defined in the ISO

8802-3 (IEEE/ANSI 802.3) stan-

dard.

When EXDINT is set, INTA is as-

serted i f the enab le bit E XDINTE

is 1.

Read/Write accessible always.

EXDINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. EXDINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 EXDINTE Excessive Deferral Interrupt En-

able. If EXDINTE is set, the

EXDINT bit will be able to set the

INTR bit.

Read/Write accessible always.

EXDINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

5 MPPLBA Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C972 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If

MPPLBA is set to 1, the des tina-

tion ad dress of the Ma gic P acket

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of MPPLBA only affects the

address detection of the Magic

Packet fr ame. The Magi c Packet

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless of what kind of

destination address it has. This

bit is OR’ed with EMPPLBA bit

(CSR116, bit 6).

Read/Write accessible always.

MPPLBA is set to 0 by H_RESET

or S_RESET and is not affected

by setting the STOP bit.

4 MPINT Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C972 controller when the

device is in the Magic Packet

Am79C972 115

mode and the Am79C972 con-

troller receives a Magic Packet

frame. When MPINT is set to 1,

INTA is asserted if IENA (CSR0,

bit 6) and the enable bit MPINTE

are set to 1.

Read/Write accessible always.

MPINT is cleared by the host by

writing a 1. Writing a 0 has no af-

fect. MPINT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

3 MPINTE M agic Pa cket Interru pt Enabl e. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MPINT is cleared to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

2 MPEN Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C972 controller will enter

the Magic Packet mode when

both MPEN and MPMODE are

set to 1.

Read/Write accessible always.

MPEN is cleared to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

1 MPMODE The Am79C972 controller will en-

ter the Ma gi c P ack et m ode whe n

MPMODE is set to 1 and either

PG is asserted or MPEN is set to

Read/Write accessible always.

MPMODE is cleared to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit

0 SPND Suspend. Setting SPND to 1 will

cause the Am79C972 controller

to start requesting entrance into

suspend mode. The host must

poll SPND until it reads back 1 to

determine that the Am79C972

controller has entered the sus-

pend mode. Setting SPND to 0

will get the Am79C972 controller

out of sus pe nd m ode . S PND ca n

only be set to 1 if STOP (CSR0,

bit 2) is set to 0. H_RESET,

S_RESET or setting the STOP bit

will get the Am79C972 controller

out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit des cription of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

In susp end mode, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C972

controller is not reset while in

suspend mode (by H_RESET,

S_RESET or by setting the STOP

bit), no re-initialization of the de-

vice is required after the device

comes out of suspend mode. The

Am79C972 controller will contin-

ue at the transmit and receive de-

scriptor ring locations, from

where it had left, when it entered

the susp end mod e.

Read/Write accessible always.

SPND is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 TLEN Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during the Am79C972 controller

initialization. This field is written

during the Am79C972 controller

initialization routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

TLEN is only defin ed after ini tial-

ization. These bits are unaffected

116 Am79C972

by H_RESET, S_RESET, or

STOP.

11-8 RLEN Contains a copy of the receive

encoded ring length (RLEN) read

from the initialization block during

Am79C972 controller initializa-

tion. This field is written during

the Am79C972 controller initial-

ization routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

RLEN is only define d a fter ini tial-

ization. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

7-0 RES Rese rved locations. Re ad as 0s.

Write operations are ignored.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 FASTSPNDE Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C972 controller performs a

fast suspend whenever the

SPND bit is set.

When a fa st suspend is req uest-

ed, the Am79C972 controller per-

forms a quick entry into the

suspend mode. At the time the

SPND bit is set, the Am79C972

controller will complete the DMA

process of any transmit and/or re-

ceive packet that had already be-

gun DMA activity. In addition, any

transmit packet that had started

transmission will be fully transmit-

ted and any receive packet that

had begun reception will be fully

receiv ed. Howev er, no a dditional

packets wil l be transmitted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence, the Am79C97 2 controll er

may enter the suspend mode

with transmit and/or receive

packets still in the FIFOs or the

SRAM.

When FASTSPNDE is 0 and the

SPND bit is set, the Am79C972

control ler may tak e lo nger bef ore

entering the suspend mode. At

the time the SPND bit is set, the

Am79C972 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun

and t he Am79 C 9 72 cont ro l l er will

completely receive a receive

packet if it had already begun.

Additionally, all transmit packets

stored in the tran smit FIFOs and

the transmit buffer area in the

SRAM (if one is enabled) will be

transmitted and all receive pack-

ets stored in the receive FIFOs,

and the receive buffer area in the

SRAM (if one is enabled) will be

transferred into system memory.

Since the FIFO and SRAM con-

tents are flushed, it may take

much longer before the

Am79C972 controller enters the

suspend mode. The amount of

time that it takes depends on

many factors including the size of

the SRAM, bus latency, a nd net-

work traffic level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach is

used to enter suspend mode.

Read/Write accessible always.

FASTSPNDE is cleared by

H_RESET, S_RESET or by set-

ting the STOP bit.

14 RXFRTG Receive Frame Tag. When Re-

ceive Frame Tag is set to 1, a tag

word is put into the receive de-

scriptor supplied by the EADI.

See the section Receive Frame

Tagging for details. This bit is

valid only when the EADISEL

(BCR2, bit 3) is set to 1.

Read/Write accessible always.

RXFRTG is cleared by

H_RESET. RXFRTG is unaffect-

Am79C972 117

ed by S_RESET or by setting the

STOP bit.

13 RDMD Receive Demand, when set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is requir ed to be set if th e

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C972

controller’s response to a receive

Descriptor Ring Entry.

Read/Write accessible always.

RDMD is set by w riting a 1 . Writ-

ing a 0 has no effect. R DMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a re-

ceive Descriptor. RDMD is

cleared by H_RESET. RDMD is

unaffected by S_RESET or by

setting the STOP bit.

12 RXDPOLL Receive Disable Polling. If RXD-

POLL is set, the Buffer Manage-

ment Unit will disable receive

polling. Likewise, if RXDPOLL is

cleared, automatic receive poll-

ing is enabled. If RXDPOLL is

set, RDMD bit in CSR7 must be

set in order to initiate a manual

poll of a receive descriptor. Re-

ceive Descriptor Polling will not

take place if RXON is reset.

Read/Write accessible always.

RXDPOLL is cleared by

H_RESET. RXDPOLL is unaf-

fected by S_RESET or by setting

the STOP bit.

11 STINT Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C972 controller when

the Software Timer counts down

to 0. The Software Timer will im-

mediately load the STVAL (BCR

31, bits 5-0) into the Software

Timer and begin cou nti ng down .

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

Read/Write accessible always.

STINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. STINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

10 STINTE Softwar e Timer Interrupt Enable .

If STINTE is set, the STINT bit

will be able to set the INTR bit.

Read/Write accessible always.

STINTE is se t to 0 by H_RESE T

and is not affected by S_RESET

or setting the STOP bit

9 MREINT MII Management Read Error In-

terrupt. T he MII Read Er ror inter -

rupt is set by the Am79C972

control ler to indi ca te t hat the cur-

rently read register from the ex-

ternal PHY is invalid. The

contents of BCR34 are incorrect

and that the operation should be

performed again. The indication

of an incorrect read comes from

the PHY. During the read turn-

around time of the MII manage-

ment frame the external PHY

should drive the MDIO pin to a

LOW state. If this does not hap-

pen, it indicates that the PHY and

the Am79C972 controller have

lost synchronization.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

Read/Write accessible always.

MREINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MREINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 MREINTE MII Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

Read/Write accessible always.

MREINTE is set to 0 by

118 Am79C972

H_RESET an d is not affected by

S_RESET or setting the STOP bit

7 MAPIN T MII Mana gement A uto-Poll I nter-

rupt. The MII Auto-Poll interrupt is

set by the Am79C972 controller

to indicate that the cu rrently read

status do es not match t he store d

previous status indicating a

change in state for the external

PHY. A change in the Auto-Poll

Access Method (BCR32, Bit 11)

will reset the shadow register and

will not cause a n interrup t on the

first access from the Auto-Poll

section. Subsequent accesses

will generate an interrupt if the

shadow register and the read

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

Read/Write accessible always.

MAPINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MAPINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 MAPINTE MII Auto-Poll Interrupt Enable. If

MAPINTE is set, the MAPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MAPINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP bit

5 MCCINT MII Management Command

Complete Interrupt. The MII Man-

agement Command Complete In-

terrupt is set by the Am79C972

controller when a read or write

operation to the MII Data Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MCCINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

4 MCCINTE MII Management Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the MC-

CINT bit will be able to set the

INTR bit when the host reads or

writes to the MII Data Port

(BCR34) only. Internal MII Man-

agement Commands will not gen-

erate an interrupt. For instance

Auto-Po ll sta te mach ine gen erat-

ed MII management frames will

not generate an interrupt upon

completion unless there is a com-

pare error which get reported

through the MAPINT (CSR7, bit

6) interrupt or the MCCIINTE is

set to 1.

Read/Write accessible always.

MCCINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 MCCIINT MII Management Command

Complete Internal Interrupt. The

MII Management Command

Complete Interrupt is set by the

Am79C972 controller when a

read or write operation on the MII

management port is complete

from an internal operation. Exam-

ples of internal operations are

Auto-Poll or MII Management

Port generated MII management

frames. These are normally hid-

den to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCIINT is cleared by the host

by writing a 1. W r iti ng a 0 has no

effect. MCCIINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

2 MCCIINTE MII Management Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state machines generate MII

Am79C972 119

management frames. For in-

stance, when MCCIINTE is set to

1 and the Auto-Poll state ma-

chine generates a MII manage-

ment frame, the MCCIINT will set

the INTR bit upon completion of

the MII management frame re-

gardless of the comparison out-

come.

Read/Write accessible always.

MCCIINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 MIIPDTINT MII PHY Detect Transition Inter-

rupt. The MII PHY Detect Transi-

tion Interrupt is set by the

Am79C972 controller whenever

the MIIPD bit (BCR32, bit 14)

transitions from 0 to 1 or vice ver-

sa.

Read/Write accessible always.

MIIPDTINT is cleared by the host

by writ ing a 1. W riti ng a 0 has n o

effect. MIIPDTINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

0 MIIPDTINTE MII PHY Detect Transition Inter-

rupt Enable. If MIIPDTINTE is set

to 1, the MIIPDTINT bit will be

able to set the INTR bit.

Read/Write accessible always.

MIIPDTINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

CSR8: Logical Address Filter 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[15:0] Logical Address Filter, LADRF-

[15:0]. The content of this register

is undefined until loaded from the

initialization block after the INIT

bit in CSR0 h as bee n set or a d i-

rect register write has been per-

formed on this register.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR9: Logical Address Filter 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[31:16] Logical Address Filter, LADRF-

[31:16]. The content of this regis-

ter is unde fin ed until l oaded f rom

the initialization block after the

INIT bit in CSR0 has been s et or

a direct register write has been

performed on this register.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR10: Logical Address Filter 2

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[47:32] Logical Address Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has b een perfo rm ed o n th is

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR11: Logical Address Filter 3

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[63:48] Logical Address Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

120 Am79C972

write has be en per for m ed o n th is

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR12: Physical Address Register 0

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[15:0] Physical Address Register,

PADR[15:0]. The c onte nts o f th is

PROM after H_RESET or by an

EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR13: Physical Address Register 1

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[31:16]Physical Address Register,

PADR[31:16]. The contents of

this regis ter are loaded f ro m EE-

PROM after H_RESET or by an

EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR14: Physical Address Register 2

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[47:32]Physical Address Register,

PADR[47:32].The contents of

this regis ter are loaded f ro m EE-

PROM after H_RESET or by an

EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR15: Mode

This register’s fields are loaded duri ng the A m79C97 2

controller initialization routine with the corresponding

Initialization Block values, or when a direct register write

has been performed on this register.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PROM Promiscuous Mode. When

PROM = 1, all incoming receive

frames are accepted.

Am79C972 121

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

14 DRCVBC Disable Receive Broadcast.

When set, disables the

Am79C972 controller from re-

ceiving broadcast messages.

Used for protocols that do not

support broadcast addressing,

except as a func tion of mu ltic ast.

DRCVBC is cleared by activatio n

of H_RESET or S_RESET

(broadcast messages will be re-

ceived) and is unaffected by

STOP.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

13 DRCVPA Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C972 controller

will be disabled. Frames ad-

dressed to the nodes individual

physical address will not be rec-

ognized.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

12-9 RES Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0] Port Select bits allow for software

controlled selection of the net-

wor k medium. The only legal val-

ues for this field are 11 and 10.

A value of 11 selects the MII port

and a value of 10 selects the

GPSI port.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. Cleared by H_RESET or

S_RESET and is unaffected by

STOP.

6 INTL Internal Loopback. See the de-

scription of LOOP (CSR15, bit 2).

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

5 DRTY Disable Retry. When DRTY is set

to 1, the Am79C972 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwr itten, because au to-

matic retransmission will not be

necessar y. When DRTY is set to

0, the Am79C972 controller will

attempt 16 transmissions before

signaling a retry error.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

4 FCOLL Force Collision. This bit allows

the collision logic to be tested.

The Am79C972 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a co lli-

sion will be forced during loop-

back transmission attempts,

which will result in a Retry Error.

If FCOLL = 0, the Force Co ll is io n

logic will be disabled. FCOLL is

defined after the initialization

block is read.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

3 DXMTFCS Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. W hen DX MTF CS is s et t o

1, no FCS is generated or sent

with the transmitted frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in TMD1.

When APAD_XMT bit (CSR4,

bit11) is set to 1, the setting of

DXMTFCS has no effect on

frames shorter than 64 bytes.

If DXMTFCS is set and

ADD_ FCS is clear for a parti cula r

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_F CS bit in TMD1.

122 Am79C972

This bit was called DTCR in the

LANCE (Am7990) device.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

2 LOOP Loopback Enable allows the

Am79C972 controller to operate

in full-duplex mode for test pur-

poses. The setting of the full-

duplex c ontrol b its i n BCR9 h ave

no effect when the device oper-

ates in loopback mode. When

LOOP = 1, loopback is enabled.

In combination with INTL and

MIIILP, various loopback modes

are defined as follows in Table

21.

Refer to Loop Back Operation

section for more details.

Read/Write accessible only

when either the STOP or the

SPND bit is set. LOOP is cleared

by H_RESET or S_RESET and

is unaffected by STOP.

1 DTX Disable Transmit results in

Am79C972 controller not access-

ing the Transmit Descriptor Ring

and, therefore, no transmissions

are attempted. DTX = 0, will set

TXON bit (CSR0 bit 4) if STRT

(CSR0 bit 1) is asserted.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

0 DRX Disable Receiver results in the

Am79C972 controller not access-

ing the Receive Descriptor Ring

and, therefore, all receive frame

data are ignored. DRX = 0, will

set RXON bit (CSR0 bit 5) if

STRT (CSR0 bit 1) is asserted.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

CSR16: Initialization Block Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADRL This register is an alias of CSR1.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

CSR17: Initialization Block Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADRH This register is an alias of CSR2.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

CSR18: Current Receive Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRB AL Contains th e lower 16 bits of the

current receive buffer address at

which the Am79C972 controller

will store incoming frame data.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR19: Current Receive Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRB AU Contains the upper 16 bits of th e

current receive buffer address at

which the Am79C972 controller

will store incoming frame data.

Table 21. Loopback Configuration

LOOP INTL MIIILP Function

GPSI 0 0 0 Normal Operation

1 1 0 Internal Loop

1 0 0 External Loop

MII 0 0 0 Normal Operation

0 0 1 Internal Loop

1 0 0 External Loop

Am79C972 123

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR20: Current Transmit Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXB AL Conta ins the lower 16 bits of the

current transmit buffer address

from which the Am79C972 con-

troller is transmitting.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR21: Current Transmit Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXB AU Contains the uppe r 16 bits of th e

current transmit buffer address

from which the Am79C972 con-

troller is transmitting.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR22: Next Receive Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRBA L Contains the l ower 16 bits of th e

next receive buffer address to

which the Am79C972 controller

will store incoming frame data.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR23: Next Receive Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRB AU Contains the upper 16 bits of th e

next receive buffer address to

which the Am79C972 controller

will store incoming frame data.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR24: Base Address of Receive Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BA DRL Contains th e lower 16 bits of the

base address of the Receive

Ring.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR25: Base Address of Receive Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BA DRU Contains the upper 16 bits of the

base address of the Receive

Ring.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR26: Next Receive Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRDAL Contains the lower 16 bits of th e

next receive descriptor address

pointer.

124 Am79C972

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR27: Next Receive Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRDAU Contains the uppe r 16 bits of th e

next receive descriptor address

pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR28: Current Receive Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRDAL Co ntains the lower 16 bits o f the

current receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR29: Current Receive Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRDAU Contains the uppe r 16 bits of th e

current receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR30: Base Address of Transmit Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BA DXL Conta ins the lower 16 bits of the

base address of the Transmit

Ring.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR31: Base Address of Transmit Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BA DXU Contains the upper 16 bits of th e

base address of the Transmit

Ring.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR32: Next Transmit Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NX DAL Conta ins the lower 16 bi ts of the

next transmit descriptor address

pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR33: Next Transmit Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NX DAU Conta ins the uppe r 16 bits of th e

next transmit descriptor address

pointer.

Am79C972 125

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR34: Current Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXD AL Co ntains the lo wer 16 bits of th e

current transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR35: Current Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXD AU Contains the upper 16 bits of the

current transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR36: Next Next Receive Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNRDAL Contains the lo wer 16 bits of the

next next receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR37: Next Next Receive Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNRDAU Contains the uppe r 16 bits of the

next next receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR38: Next Next Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNX DAL Contains th e lower 16 bits of the

next next transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR39: Next Next Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNX DAU C onta ins the uppe r 16 bits of th e

next next transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

126 Am79C972

CSR40: Current Receive Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 CRBC Current Receive Byte Count.

This field is a copy of the BCNT

field of RMD1 of the current re-

ceive descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR41: Current Receive Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRST Current Receive Status. This

field is a copy of bits 31-16 of

RMD1 of the current receive de-

scriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR42: Current Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 CXBC Current Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the current trans-

mit descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR43: Current Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXST Current Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of th e current transm it de-

scriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR44: Next Receive Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 NRBC Next Receive Byte Count. This

field is a copy of the BCNT field of

RMD1 of the next receive de-

scriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR45: Next Receive Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRST Nex t R ec eiv e Sta tus . Thi s fie ld is

a copy of bits 31-16 of RMD1 of

the next receive descriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

Am79C972 127

CSR46: Transmit Poll Time Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXPOLL Transmi t P ol l T ime C oun ter . This

counter is incremented by the

Am79C972 controller microcode

and is used to trigger the transmit

descriptor ring polling operation

of the Am79C972 controller.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR47: Transmit Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXPOLLINT Transmit Polling Interval. This

Am79C972 controller will wait be-

tween successive polling opera-

tions. The TXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of TXPOLLINT

represents 1 clock period of time.

TXPOLLINT[3:0] are ignored.

(TXPOLLINT[16] is implied to be

a one, so TXPOLLINT[15] is sig-

nificant and does not represent

the sign of the tw o’s complement

TXPO LLIN T va lue .)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz). The TXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR47 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for POLLINT other than the

default, then the correct proce-

dure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR47 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the stan-

dard initialization procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead, chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is im perativ e that the user

also writes all zeros to CSR47 as

part of the alternative initialization

sequence.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR48: Receive Poll Time Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RXPOLL Receive Poll Time Counter. This

counter is incremented by the

Am79C972 controller microcode

and is used to t rigger the re ceiv e

descriptor ring polling operation

of the Am79C972 controller.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR49: Receive Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RXPOLLINT Receive Polling Interval. This reg-

ister contains the time that the

Am79C972 controller will wait be-

tween successive polling opera-

tions. The RXPOLLINT value is

expressed as the two’s comple-

128 Am79C972

ment of the desired interval,

where each bit of RXPOLLINT

approximately represents one

clock time period. RXPOL-

LINT[3:0] are ignored. (RXPOL-

LINT[16] is implied to be a 1, so

RXPOLLINT[15] is significant

and does not represent the sign

of the two’s complement RXPOL-

LINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz). The RXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR49 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for RX POLLINT other tha n

the default, then the correct pro-

cedure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR49 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the stan-

dard initialization procedure

(standard implies use of an initial-

ization block in me mory and set-

ting the INIT bit of CSR0), but

instead, c hooses to wri te directly

to each of the registers that are

involved in the INIT operation,

then it is im perative that the user

also writes all zeros to CSR49 as

part of the alternative initialization

sequence.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR58: Software Style

This register is an alias of the location BCR20. Accesses

to and from th is register are equivalent to ac cesses to

BCR20.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-11 RES Reserved locations. Written as

zeros and read as undefined.

10 APERREN Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer th at was a ccess ed when a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descriptor, SWSTYLE (bits

7-0 of this register) must be set to

2 or 3 to program the Am79C972

controller to use 32-bit software

structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C972 controller is the

target of the transfer.

Read anytime, write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

9 RES Reserved locations. Written as

zeros and read as undefined.

8 SSIZE32 Software Si ze 32 bits. When se t,

this bit indicates that the

Am79C972 controller utilizes 32-

bit softwa re struct ures for the ini-

tialization block and the transmit

and receive descriptor entries.

When cleared, this bit indicates

that the Am79C972 controller uti-

lizes 16-bit software structures for

the initialization block and the

transmit and receive descriptor

entries. In this mode, the

Am79C972 controller is back-

wards compatible with the

Am79C972 129

Am799 0 LANCE and Am79C96 0

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined by the Am 79C972 cont ro l-

ler accor ding to the setting of the

Software Style (SWSTYLE, bits

7-0 of this register).

Read accessible always.

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-b it add re ss

bus durin g maste r acc esses i niti-

ated by the Am79C972 controller.

This action is required, since th e

16-bit software structures speci-

fied by the SSIZE32 = 0 setting

will yield only 24 bits of address

for the Am79C972 controller bus

master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C972 controller and

the host system will supply a full

32 bits for each address pointer

that is n eed ed by th e A m79 C97 2

controller for performing master

accesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress p ins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE3 2 b it has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in thi s register de termines th e

style of register and memory re-

sources that sha ll be used by the

Am79C972 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width of

the descriptors and initialization

block entries.

All Am79C972 controller CSR

bits and BCR bits and all descrip-

tor, buffer , and ini tiali zation blo ck

entries not cited in Table 22 are

unaffected by the Software Style

selection and are, therefore, al-

ways full y functional a s specified

in the CSR and BCR sections .

Read/Write accessible only when

either the STO P or the SPND bit

is set. The SWSTYLE register will

contain the value 00h following

H_RESET and wi ll be un affecte d

by S_RESET or STOP.

CSR60: Previous Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PXDAL Contains the lower 16 bits of the

previous transmit descriptor ad-

dress pointer. The Am79C972

controller has the capability to

stack multiple transmit frames.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

130 Am79C972

CSR61: Previous Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 PXDAU Con tains the upper 16 b its of th e

previous transmit descriptor ad-

dress pointer. The Am79C972

controller has the capability to

stack multiple transmit frames.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR62: Previous Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-12 RES Reserved locations.

11-0 PXBC Previous Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the previous

transmit descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR63: Previous Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PXST Previous Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of the previous transmit

descriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR64: Next Transmit Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXBAL Contains the lower 16 bits of the

next trans mit buffer address fro m

which the Am79C972 controller

will transmit an outgoing frame.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

Table 22. Software Styles

SWSTYLE

[7:0] Style

Name SSIZE32 Initia liza t ion Block

Entries Descriptor Ring Entries

00h LANCE/

PCnet-ISA

controller 016-bit software structures,

non-burst or burst access 16-bit software structures,

non-burst access only

01h RES 1RES RES

02h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access 32-bit software structures,

non-burst access only

03h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access 32-bit software structures,

non-burst or burst access

All Other Reserved Undefined Undefined Undefined