1
®80C86
CMOS 16-Bit Microprocessor
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). Two modes of operation,
minimum for small systems and maximum for larger
applications such as multiprocessing, allow user
configuration to achieve the highest performance level. Full
TTL compatibility (with the exception of CLOCK) and
industry standard operation allow use of existing NMOS
8086 hardware and software designs.
Features
• Comp atible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operatio n
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memo ry Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/ U ns igned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Availabl e (RoHS Co mpl ia nt)
Ordering Information
PART NUMBER PART
MARKING
TEMP.
RANGE
(°C) PACKAGE PKG.
DWG. #
CP80C86-2 CP80C86-2 0 to +70 40 Ld PDIP E40.6
CP80C86-2Z
(Note) CP80C86-2Z 0 to +70 40 Ld PDIP*
(Pb-free) E40.6
MD80C86-2/883 MD80C86-2/883 -55 to +125 40 Ld CERDIP F40.6
MD80C86-2/B MD80C86-2/B -55 to +125 40 Ld CERDIP F40.6
8405202QA 8405202QA -55 to +125 40 Ld CERDIP
(SMD) F40.6
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solde r processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Datasheet FN2957.3January 9, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN2957.3
January 9, 2009
Pinout 80C86
(40 LD PDIP, CERDIP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
TEST
READY
RESET
(INTA)
(ALE)
(DEN)
(DT/R))
(M/IO)
(WR)
(HLDA)
(HOLD)
MAX (MIN)
80C86
3FN2957.3
January 9, 2009
Functional Diagram
REGISTER FILE
EXECUTION UNIT
CONTROL AND TIMING
INSTRUCTION
QUEUE
6-BYTE
FLAGS
16-BIT ALU
BUS INTERFACE UNIT 16
4
QS0, QS1
S2, S1, S0
2
4
3
GND
VCC
CLK RESET READY
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
3
A19/S6
A16/S3
INTA, RD, WR
DT/R, DEN, ALE, M/IO
BHE/S7
2
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
DATA POINTER
AND
INDEX REGS
(8 WORDS)
TEST
INTR
NMI
HLDA
HOLD
RQ/GT0, 1
LOCK
MN/MX
3
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
ARITHMETIC/
LOGIC UNIT
B-BUS
C-BUS
EXECUTION
UNIT
INTERFACE
UNIT
BUS
QUEUE
INSTRUCTION
STREAM BYTE
EXECUTION UNIT
CONTROL SYSTEM
FLAGS
MEMORY INTERFACE
A-BUS
AD15-AD0
80C86
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Pin Descriptions
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL PIN
NUMBER TYPE DESCRIPTION
AD15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (t1) and data
(t2, t3, tW, t4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW
during Ti when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.
Eight-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions
(See BHE). These lines are active HIGH and are held at high impedance to the last valid logic level
during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.
A19/S6
A18/S5
A17/S4
A16/S3
35-38 O ADDRESS/STA TUS: During t1, these are the 4 most significant address lines for memory operations.
During I/O operations these lines are LOW. During memory and I/O operations, status information is
available on these lines during t2, t3, tW, t4. S6 is always LOW. The status of the interrupt enable
FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge”
or “grant sequence”.
BHE/S7 34 O BUS HIGH ENABLE/STATUS: During t1 the bus high enable signal (BHE) should be used to enable
data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the
upper half of the bus would normally u se BHE to cond ition chip sele ct functions. BHE is LOW during
t1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion
of the bus. The S7 status information is available during t2, t3 and t4. The sig nal is active LOW, and
is held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold
acknowledge” or “grant sequence”, it is LOW during t1 for the first interrupt acknowledge cycle.
RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending
on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the 80C86 local
bus. RD is active LOW during t2, t3 and tW of any read cycle, and is guaranteed to remain HIGH in t2
until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand sequence”.
READY 22 I READY: The acknowledgment from the addressed memory or I/O device that will complete the data
transfer . The RDY signal from memory or I/O is synchronized by the 82C84A Clock Generator to form
READY. This signal is active H IGH. The 80C 86 READY inpu t is not synchr onized. Correct oper ation
is not guaranteed if the Setup and Hold Times are not met.
INTR 18 I INTERRUPT REQUEST: A level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be
internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
S4 S3 CHARACTERISTICS
00Alternate Data
01Stack
1 0 Code or None
11Data
BHE A0 CHARACTERISTICS
0 0 Whole Word
0 1 Upper Byte From/to Odd Address
1 0 Lower Byte From/to Even address
1 1 None
80C86
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TEST 23 I TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” st ate. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
NMI 17 I NON-MASKABLE INTERRUPT: An edge triggered input which causes a type 2 interrupt. A subroutine
is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable
internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current
instruction. This input is internally synchronized.
RESET 21 I RESET: Causes the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least 4 clock cycles. It restarts execution, as described
in the “Instruction Set Summary” on page 31 when RESET returns LOW. RESET is internally
synchronized.
CLK 19 I CLOCK: Provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
VCC 40 VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for
decoupling.
GND 1, 20 GND: Ground. Note: Both must be connected. A 0.1µF capacitor between pins 1 and 20 is
recommended for decoupling.
MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to minimum
mode are described; all other pin fu nctions are as described in the following.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
M/IO 28 O STATUS LINE: Logically equivalent to S2 in the maximum mode. It is used to distinguish a memory
access from an I/O access. M/lO becomes valid in the t4 preceding a bus cycle and remains valid until
the final t4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic one during local
bus “hold acknowledge”.
WR 29 O WRITE: Indicates that the processor is performing a wr ite memory or write I/O cycle, depending on
the state of the M/IO signal. WR is active for t2, t3 a nd tW of any write cycle. It is active LOW, and is
held to high impedance logic one during local bus “hold acknowledge”.
INTA 24 O INTERRUPT ACKNOWLEDGE: Used as a read strobe for interrupt acknowledge cycles. It is active
LOW during t2, t3 and tW of each interrupt acknowledge cycle. Note that INTA is never floated.
ALE 25 O ADDRESS LATCH ENABLE: Provided by the processor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock LOW of t1 of any bus cycle. Note that ALE is never
floated.
DT/R 27 O DA T A TRANSMIT/RECEIVE: Needed in a minimum system that desires to use a data bus transceiver .
It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN 26 O DATA ENABLE: Provided as an output enable for a bus transceiver in a minimum system which uses
the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a
read or INTA cycle it is active from the middle of t2 until the middle of t4, while for a write cycle it is
active from the beginning of t2 until the middle of t4. DEN is held to a high impedance logic one during
local bus “hold acknowledge”.
Pin Descriptions (Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL PIN
NUMBER TYPE DESCRIPTION
80C86
6FN2957.3
January 9, 2009
HOLD
HLDA 31, 30 I
OHOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged, HOLD
must be active HIGH. The processor receiving the “ hold” will issue a “hold acknowledge” (HLDA) in
the middle of a t4 or TI clock cycle. Simultaneously with the issuance of HLDA, the processor will float
the local bus and control lines. After HOLD is detected as being LOW , the processor will lower HLDA,
and when the processor needs to run another cycle, it will again drive the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the setup time.
Minimum Mode System (Continued)
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to minimum
mode are described; all other pin fu nctions are as described in the following.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique
to maximum mode are described in the following.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
S0
S1
S2
26
27
28
O
O
O
STATUS: is active during t4, t1 and t2 and is returned to the passive state (1, 1, 1) during t3 or during
tW when READY is HIGH. This status is used by the 82 C88 Bus Controller to generate all memory
and I/O access control signals. Any change by S2, S1 or S0 during t4 is used to indicate the beginning
of a bus cycle, and the return to the passive state in t3 or tW is used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2 S1 S0 CHARACTERISTICS
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
011Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
80C86
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RQ/GT0
RQ/GT1 31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the
local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GTO having
higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it may be left
unconnected. The request/grant sequence is as follows (see RQ/GT Sequence Timing)
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to the
80C86 (pulse 1).
2. During a t4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master
(pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the “grant
sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logically from the
local bus during “grant sequence”.
3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the “hold”
request is about to end and that the 80C86 can reclaim the local bus at the next CLK. The CPU
then enters t4 (or TI if no bus cycles pending). Each Master-Master exchange of the local bus is
a sequence of 3 pulses. There must be one idle CLK cycle after each bus exchange. Pulses are
active low.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during
t4 of the cycle when all the following conditions are met:
1. Request occurs on or before t2.
2. Current cycle is not the low byte of a word (o n an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the re quest is made the two possible events will follow:
1. Local bus will be released during the next cycle.
2. A memory cycle will start within three clocks. Now the four rules for a currently active memory
cycle apply with condition number 1 already satisfied.
LOCK 29 O LOCK: output indicates that other system bus masters are not to gain control of the system bus while
LOCK is active LOW . The LOCK signal is activated by the “LOCK” prefix instruction and remains active
until the completion of the next instruction. This signal is active LOW , and is held at a high impedance
logic one state during “grant sequence”. In MAX mode, LOCK is automatically generated during t2 of
the first INTA cycle and removed during t2 of the second INTA cycle.
QS1, QSO 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue operation is
performed.
QS1 and QS0 provide status to allow exter nal tracking of the intern al 80C86 inst ruction queue. N ote
that QS1, QS0 never become high impedance.
Maximum Mode System (Continued)
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique
to maximum mode are described in the following.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
QSI QSO
0 0 No Operation
0 1 First byte of op code from qu eue
1 0 Empty the queue
1 1 Subsequent byte from queue
80C86
8FN2957.3
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Functional Description
Static Operation
All 80C86 circuitry is of static design. Internal registers,
counters and latches are static and require no refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other
microprocessors. The CMOS 80C86 can operate from DC to
the specified upper frequency limit. The processor clock may
be stopped in either state (HIGH/LOW) and held there
indefinitely. This type of operation is especially useful for
system debug or power critical applications.
The 80C86 can be single stepped using only the CPU clock.
This state can be maintained as long as is necessary. Single
step clock operation allows simple interface circuitry to
provide critical information for bringing up your system.
S tatic design also allows very low frequency operation (down
to DC). In a power critical situation, this can provide
extremely low power operation since 80 C86 power
dissipation is directly related to operating frequency. As the
system frequency is reduced, so is the operating power until,
ultimately, at a DC input frequency, the 80C86 power
requirement is the standby current, (500µA maximu m).
Internal Archite ct u re
The internal functions of the 80C86 processor are partitioned
logically into two processing units. The first is the Bus
Interface Unit (BlU) and the seco nd is the Execution Unit
(EU) as shown in the “Functional Diagram” on page 3.
These units can interact directly, but for the most part perform
as separate asynchrono us operationa l pro cessors. The bu s
interface unit provides the functions rela ted to instruction
fetching and queuing, operand fetch and sto re, and address
relocation. This unit also provides the basic bus control. The
overlap of instruction pre-fetching provided by this unit serves
to increase processor performance through impro ved bus
bandwidth utili zati on. Up to 6 bytes of the instruction stream
can be queued while waiting for d eco ding and execu tion.
The instruction stream queuing mechanism allows the BIU to
keep the memory utilized very efficiently. Whenever there is
space for at least 2 bytes in the queue, the BlU will attempt a
word fetch memory cycle. This greatly reduces “dead-time”
on the memory bus. The queue acts as a First-In-First-Out
(FIFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue
immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from the
BlU queue and provides un-relocated operand addresses to
the BlU. Memory operands are passed through the BIU for
processing by the EU, which passes results to the BIU for
storage.
Memory Organization
The processor provides a 20-bit address to memory, which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divid ed into
code, data, extra and stack segments of up to 64k bytes
each, with each segment falling on 16-byte boundaries
(see Figure 1).
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of
programs. The segment register to be selected is
automatically chosen according to the specific rules of
Table 1. All information in one segment type share the same
logical attributes (e.g. code or data). By structuring memory
into re-locatable areas of similar characteristics an d by
automatically selecting segment registers, pro grams are
shorter, faster and more structured (see Table 1).
TABLE 1.
TYPE OF
MEMORY
REFERENCE
DEFAULT
SEGMENT
BASE
ALTERNATE
SEGMENT
BASE OFFSET
Instruction Fetch CS None IP
Stack Operation SS None SP
Variable (except
following) DS CS, ES, SS Effective
Address
String Source DS CS, ES, SS SI
String Destination ES None DI
BP Used As Base
Register SS CS, DS, ES Effective
Address
SEGMENT
REGISTER FILE
CS
SS
DS
ES
64k-BIT
+ OFFSET
FFFFFH
CODE SEGMENT
XXXXOH
STACK SEGMENT
DATA SEGMENT
EXTRA SEGMENT
00000H
FIGURE 1. 80C86 MEMORY ORGANIZATION
80C86
9FN2957.3
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Word (16-bit) operands can be located on even or odd
address boundaries and are thus , not constrained to even
boundaries as is the case in many 16-bit computers. Fo r
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location. The
BIU automatically performs the proper number of memory
accesses; one, if the word operand is on an even byte
boundary and two, if it is on an odd byte boundary. Except
for the performance penalty, this double access is
transparent to the software. The performance penalty does
not occur for instruction fetches; only word operands.
Physically, the me mory is organized as a high bank
(D15-D8) and a low bank (D7-D0) of 512k bytes addressed
in parallel by the processor’s address lines.
Byte data with even addresses is transferred on the D7-D0
bus lines, while odd addressed byte data (A0 HIGH) is
transferred on the D15-D8 bus lines. The processor provides
two enable signals, BHE and A0, to selectively allow reading
from or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the
processor at the byte level as necessary.
In referencing word data, the Bl U requires one or two memory
cycles depending on whether the starting byte of the word is
on an even or odd address, respectively. Consequently, in
referencing word operands performance can be optimized by
locating data o n eve n address boundarie s. This is an
especially useful tech nique for using the stack, since odd
address references to the st ack may ad versely af fect the
context switching time for interrupt processing or t ask
multiplexing.
Certain locations in memory are reserved for specific CPU
operations (see Figure 2). Locations from address FFFF0H
through FFFFFH are reserved for o perations including a jump
to the initial program loading routine. Follo wing RESET, the
CPU will always begin execution at location FFFF0H where
the jump must be located. Locations 00000H through 003FFH
are reserved for interrupt operations. Each of the 256 possible
interrupt service routines is accessed through its own p air of
16-bit pointers (segment address pointer and o ffset address
pointer). The first pointer, used as the offset address, is
loaded into the lP and the second pointer, which designates
the base address is loaded into the CS. At this p oint, program
control is transferred to the interrupt routine. The pointer
elements are assumed to have been stored at the respective
places in reserved memory pri or to occurrence of in terrupts.
Minimum and Maximum Operation Modes
The requirements for su pporting minimu m and ma xi mum
80C86 systems are suf ficiently different that they cannot be
met effi ciently usi ng 40 uniquel y de fined pi ns. Consequen tl y,
the 80C86 is equipped with a stra p pin (MN/MX ) which
defines the system config urati on. The defi nition of a certain
subset of the pins changes, depe ndent on the conditio n of the
strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum mode.
When the MN/MX pin is strapped to VCC, the 80C86
generates bus control signal s it self on pins 24 through 31
and 34.
The minimum mode 80C86 can be used with either a
multiplexed or demultiplexed bus. This architecture provides
the 80C86 processing power in a highly integrated form.
The demultiplexed mod e re quires two 82C 82 latches (for 64k
addressability) or three 82C82 latches (for a full megabyte of
addressing). An 82C86 or 82C87 transceiver can also be
used if data bus buf ferin g is requ ired (see Fig ure 6A.) The
80C86 provides DEN and DT/R to control the transceiver, and
ALE to latch the addresses. This configuration of the minimum
mode provides the standard de multiple xed bus structure with
heavy bus buf feri ng and relaxed bus timing re quirement s.
The maximum mode employs the 82C88 bus controller (see
Figure 6B). The 82C88 decodes status lines S0, S1 and S2,
and provides the system with all bus control signals.
Moving the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
lock, queue status, and two request/grant interfaces are
provided by the 80C86 in maximum mode. These features
allow coprocessors in local bus and remote bus
configurations.
Bus Operation
The 80C86 has a combined addre ss and data bus
commonly referred to as a time multiplexed bus. This
technique provides the most efficient use of pins on the
processor while permitting the use of a standard 40 lead
package. This “local bus” can be buffered directly and used
throughout the system with add ress latching provided on
memory and I/O modules. In addition, the bus can also be
demultiplexed at the processor with a single set of 82C82
address latches if a standard non-multiplexed bus is desired
for the system.
Each processor bus cycle consists of at least 4 CLK cycles.
These are referred to as t1, t2, t3 and t4 (see Figure 3). The
address is emitted from the processor during t1 and data
transfer occurs on th e bu s du ri n g t3 an d t4. t2 is used
primarily for changing the direction of the bus during read
operations. In the event that a “NOT READY” indication is
given by the addressed device, “Wait” states (tW) are
inserted be tw e e n t3 and t4. Each inserted wait state is the
same duration as a CLK cycle. Periods can occur between
80C86 driven bus cycles. These are referred to as idle”
states (TI) or inactive CLK cycles. The processor uses these
cycles for internal housekeeping and processing.
During t1 of any bus cycle, the ALE (Address Latch Enable)
signal is emitted (by either the processor or th e 82 C 88 bus
controller, depending on the MN/MX strap). At the trailing
80C86
10 FN2957.3
January 9, 2009
edge of this pulse, a valid address and certain status
information for the cycle may be latched.
Status bits S0, S1 and S2 are used by the bus con t roller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
Status bits S3 through S7 are time multiplexed with high
order address bits and the BHE signal, and are therefore
valid during t2 through t4. S3 and S4 indicate which segment
register (see “Instruction Set Summary” on page 31) was
used for this bus cycle in forming the address, according to
Table 3.
S5 is a reflection of the PSW interrupt enable bit. S3 is
always zero and S7 is a spare status bit.
I/O Addressing
In the 80C86, I/O operations can address up to a maximum
of 64k I/O byte registers or 32k I/O word registers. The I/O
address appears in the same format as the memory address
on bus lines A15-A0. The address lines A19-A16 are zero in
I/O operations. The variable I/O instructions which use
register DX as a pointer have full address capability while
the direct I/O instructions directly address one or two of the
256 I/O byte locations in page 0 of the I/O address space.
I/O ports are addressed in the same manner as memory
locations. Even addressed bytes are transferred on the D7-D0
bus lines an d odd add resse d byte s on D15-D8. Care must be
taken to ensure that each register within an 8-bit peripheral
located on the lower portion of the bus b e addre ssed as even .
TABLE 2.
S2 S1 S0 CHARACTERISTICS
0 0 0 Interrupt
001Read I/O
010Write I/O
011Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (No Bus Cycle)
TABLE 3.
S4 S3 CHARACTERISTICS
0 0 Alternate Data (Extra Segment)
01Stack
1 0 Code or None
11Data
80C86
11 FN2957.3
January 9, 2009
TYPE 225 POINTER
(AVAILABLE)
RESET BOOTSTRAP
PROGRAM JUMP
TYPE 33 POINTER
(AVAILABLE)
TYPE 32 POINTER
(AVAILABLE)
TYPE 31 POINTER
(AVAILABLE)
TYPE 5 POINTER
(RESERVED)
TYPE 4 POINTER
OVERFLOW
TYPE 3 POINTER
1 BYTE INT INSTRUCTION
TYPE 2 POINTER
NON MASKABLE
TYPE 1 POINTER
SINGLE STEP
TYPE 0 POINTER
DIVIDE ERROR
16 BITS
CS BASE ADDRESS
IP OFFSET
014H
010H
00CH
008H
004H
000H
07FH
080H
084H
FFFF0H
FFFFFH
3FFH
3FCH
AVAILABLE
INTERRUPT
POINTERS
(224)
DEDICATED
INTERRUPT
POINTERS
(5)
RESERVED
INTERRUPT
POINTERS
(27)
FIGURE 2. RESERVED MEMORY LOCATIONS
80C86
12 FN2957.3
January 9, 2009
External Interface
Processor RESET and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 80C8 6 RES ET is
required to be H IGH for greater than 4 CLK cyc les. Th e 8 0C86
will terminate o perations on the hi gh-going edge of RESE T and
will remain dormant as long as RESET is HIGH. The low-goin g
transition of RESET triggers an internal reset sequence for
approximately 7 CLK cycles. After this interval, the 80C86
operates normally be ginning with the instru cti on in ab so lute
location FFFF0H (see Figure 2). The R ESET inp ut is inte rnall y
synchronized to the processor clock. At initialization, the
HIGH-to-LOW transit ion of RESET must occur no sooner than
50µs (or 4 CLK cycles, whichever is greater) after power-up, to
allow complete initialization of the 80 C86.
NMl will not be recognized prior to the second CLK cycle
following the end of RESE T. If NMl is asserted sooner than nine
clock cycles after the end of RESET, the proces sor may
execute one instructio n be fore re spon ding to the interrup t.
(4 + NWAIT) = TCY
t1 t2 t3 t4tWAIT t1 t2 t3 t4tWAIT
(4 + NWAIT) = TCY
GOES INACTIVE IN THE STATE
JUST PRIOR TO t4
BHE,
A19-A16 S7-S3
A15-A0 D15-D0
VALID A15-A0 DATA OUT (D15-D0)
READYREADY
WAIT WAIT
MEMORY ACCESS TIME
ADDR/
STATUS
CLK
ALE
S2-S0
ADDR/DATA
RD, INTA
READY
DT/R
DEN
WR
BHE
A19-A16 S7-S3
BUS RESERVED
FOR DATA IN
FIGURE 3. BASIC SYSTEM TIMING
80C86
13 FN2957.3
January 9, 2009
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate need for pull-up/down resistors,
“bus-hold” ci rcui try has b een u sed on the 80C 86 pi ns 2-1 6,
26-32 and 34-39 (see Figures 4A and 4B). These circuits will
maintain the last valid logic st at e if no d rivi ng s our ce is p res ent
(i.e., an unconnected pin or a d rivi ng s ource whi ch goe s to a
high impedance state). To overdrive the “bus hold” circ uits, an
external driver mus t be capable of supplyi ng a pprox imate ly
400µA minimum sink or source current at valid input voltage
levels. Since this “b us hold ” circ ui try is ac tive an d no t a
“resistive” type element, the asso ciated power su pply current is
negligible and power dissipation is significantly reduced when
compared to the use of p ass ive pu ll-up res isto rs.
Interrupt Operations
Interrupt ope r a ti o ns fa l l into tw o cl asses: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in the
“Instruction Set Summary” on page 31. Hardware interrupts
can be classified as non-maskable or maskable.
Interrupts result in a transfer of control to a new program
location. A 256-element table cont aining address p ointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH, wh ich are reserved for thi s
purpose. Each element in the t able i s 4 bytes in size an d
corresponds to an interrupt “type”. An interrupting device
supplies an 8-bit type number during the interrupt
acknowledge sequence, which is used to “vector” through the
appropriate element to the new inte rrupt service program
location. All flags and both th e Code Se gment and Instructi on
Pointer register are saved as part of the lNTA sequence.
These are restored upon execution of an In te rrupt Retu rn
(IRET) instruction.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrup t pi n
(NMI) which has higher priority than the ma skable interrupt
request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a
LOW-to-HIGH transition. The activation of this pin causes a
type 2 interrupt.
NMl is required to have a duratio n in the HIGH state of
greater than two CLK cycles, but is not required to be
synchronized to the clock. Any positive transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves of a block-type
instruction. Worst case response to NMI would be for
multiply, divide, and varia ble shift instructions. There is no
specification on the occurrence of the low-going edge; it may
occur before, during or after the servicing of NMI. Another
positive edge triggers another respo nse if it occurs after the
start of the NMI procedure. The signal must be free of logical
spikes in general and be free of bounces on the low-going
edge to avoid triggering extraneous respon ses.
Maskable Interrupt (INTR)
The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the
resetting of the interrupt enable flag (IF) status bit. The
interrupt request signal is level trig gered. It is internally
synchronized during each clock cycle on the high-going
edge of CLK. To be responded to, lNTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a block
type instruction. lNTR may be removed anytime after the
falling edge of the first INTA signal. During the interrupt
response sequence further interrupts are disabled. The
enable bit is reset as part of the response to any interrupt
(lNTR, NMI, software interrupt or single-step), although the
FLAGS register which is automatically pushed onto the stack
reflects the state of the processor prior to the interrupt. Until
the old FLAGS register is restored, the enable bit will be zero
unless specifically set by an instruction.
During the response sequence (see Figure 5) the processor
executes two successive (back-to-back) interrupt acknowledge
cycles. The 80C86 emits the LOCK signal (Max mode only)
from t2 of the first bus cycle until t2 of the second. A local bus
“hold” request will not be honored until the end of the second
bus cycle. In the second bus cycle, a byte is supplied to the
80C86 by the 82C59A Interrupt Controller , which identifies the
source (type) of the interrupt. This byte is multiplied by 4 and
used as a pointer into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within the
limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable bit
when it restores the FLAGS.
FIGURE 4A. BUS HOLD CIRCUITRY PINS 2-16, 34-39
FIGURE 4B. BUS HOLD CIRCUITR Y PINS 26-32
FIGURE 4. INTERNAL BUS HOLD DEVICES
OUTPUT
DRIVER
INPUT
BUFFER INPUT
PROTECTION
CIRCUITRY
BOND
PAD EXTERNAL
PIN
OUTPUT
DRIVER
INPUT
BUFFER INPUT
PROTECTION
CIRCUITRY
EXTERNAL
PIN
PVCC
BOND
PAD
80C86
14 FN2957.3
January 9, 2009
.
Halt
When a software “HALT” instruction is executed, the
processor indicates that it is entering the “HALT” state in one
of two ways depending upon which mode is strap ped. In
minimum mode, the processor issues one ALE with no
qualifying bus control signals. In maximum mode the
processor issues appropriate HAL T st atus on S2, S1, S0 and
the 82C88 bus controller issues one ALE. The 80C86 will not
leave the “HALT” state when a local bus “hold” is entered
while in “HALT”. In this case, the processor reissues the
HALT indicator at the end of the local bus hold. An NMI or
interrupt request (when interrupts enabled) or RESET will
force the 80C86 out of the “HALT” state.
Read/Modify/Write (Semaphore)
Operations Via Lock
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the execution
of an instruction. This gives the pr ocessor the capability of
performing read/modify/write operations on memory (via the
Exchange Register With Memory instruction, for example)
without another system bus master receiving intervening
memory cycles. This is useful in multiprocessor system
configurations to accomplish “test and set lock” operations. The
LOCK signal is activated (forced LOW) in the clock cycle
following decoding of the software “LOCK” prefix instruction. It
is deactivated at the end of the last bus c ycle of the instruction
following the “LOCK” prefix instruction. While LOCK is active a
request on a RQ/GT pin will be recorded and then honored at
the end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C86 provides a single
software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
repeatedly executed until the TEST input goes active (LOW).
The execution of WAIT does not consume bus cycles once
the queue is full.
If a local bus request occurs during WAIT execution, the
80C86 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold
circuits. If interrupts are enabled, the 80C86 will recognize
interrupts and process them when it regains control of the
bus. The WAIT instruction is then refetched, and
re-executed.
TABLE 4. 80C86 REGISTER
Basic System Timing
Typical system configurations for the processor operating in
minimum mode and in maximum mode are shown in
Figures 6A and 6B, respectively. In minimum mode, the
MN/MX pin is strapped to VCC and the processor emits bus
control signals (e.g. RD, WR, etc.) directly. In maximum
mode, the MN/MX pin is strapped to GND and the processor
emits coded status information which the 82C88 bus
controller uses to generate MULT IBUS compatible bus
control signals. Figure 3 shows the signal timi ng
relationships.
System Timing - Minimum System
The read cycle begins in t1 with the assertion of the Address
Latch Enable (ALE) signal. The trailing (low-going) edge of
this signal is used to latch the address information, which is
valid on the address/da ta bus (AD0-AD15) at this time, into
the 82C82/82C83 latch. The BHE and A0 signals add ress
the low, high or both bytes. From t1 to t4 the M/lO signal
indicates a memory or I/O operation. At t2, the address is
removed from the address/data bus and the bus is held at
the last valid logic state by internal bus hold devices. The
read control signal is also asserted at t2. The read (RD)
signal causes the addressed device to enable its data bus
drivers to the local bus. Some time later, valid data will be
available on the bus and the addressed device will dr ive the
READY line HIGH. When the processor returns the read
signal to a HIGH level, the addresse d device will again
three-state its bus drivers. If a transceiver (82C86/82C87) is
ALE
LOCK
INTA
AD0- FLOAT TYPE
AD15
t1 t2 t3 t4 TI t1 t2 t3 t4
VECTOR
FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE
AH AL
BH
CH
DH
BL
CL
DL
SP
BP
SI
DI
IP
FLAGSHFLAGSL
CS
DS
SS
ES
AX
BX
CX
DX
ACCUMULATOR
BASE
COUNT
DATA
STACK POINTER
BASE POINTER
SOURCE INDEX
DESTINATION INDEX
INSTRUCTION POINTER
STATUS FLAG
CODE SEGMENT
DATA SE GMENT
STACK SEGMENT
EXTRA SEGMENT
80C86
15 FN2957.3
January 9, 2009
required to buffer the 80C86 local bus, signals DT/R and
DEN are provided by the 80C86.
A write cycle also begins with the assertion of ALE and the
emission of the address. The M/IO signal is again asserted
to indicate a memory or I/O write operation. In t2,
immediately following the addre ss emission, the processor
emits the data to be written into the addressed location. This
data remains valid until at least the middle of t4. During t2, t3
and tW, the processor asserts the write control signal. The
write (WR) signal becomes active at the beginning of t2 as
opposed to the read which is delayed some what into t2 to
provide time for output drivers to become inactive.
The BHE and A0 signals are used to select the proper
byte(s) of the memory/lO word to be read or written
according to Table 5.
I/O ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the
D7-D0 bus lines and odd address bytes on D15-D8.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge
signal (INTA) is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal
bus hold devices (see Figure 4). In the second of two
successive INTA cycles a byte of information is read from
the data bus (D7-D0) as supplied by the interrupt system
logic (i.e., 82C59A Priority Interrupt Controller). This byte
identifies the source (type) of the interrupt. It is multiplied by
4 and used as a pointer into an interrupt vector lookup table,
as described earlier.
Bus Timing - Medium Size Systems
For medium complexity systems the MN/MX pin is
connected to GND and the 82C88 Bus Controller is added to
the system as well as an 82C82/82C83 latch for latching the
system address, and an 82C86/82C87 transceiver to allow
for bus loadin g grea te r th an the 80C86 is capable of
handling. Signals ALE, DEN, and DT/R are generated by the
82C88 instead of the processor in this configuration,
although their timing remains relatively the same. The
80C86 status outputs (S2, S1 and S0) provide type-of-cycle
information and become 82C88 inputs. This bus cycle
information specifies read (code, data or I/O), write (data or
I/O), interrupt acknowledge, or software halt. The 82C88
issues control signals specifying memory read or write, I/O
read or write, or interrupt acknowledge. The 82C88 provides
two types of write strobes, normal and advanced, to be
applied as required. The normal write strobes have data
valid at the leading edge of write. The advanced write
strobes have the same timing as read strobes, and hence,
data is not valid at the leading edge of write. The
82C86/82C87 transceiver receives the usual T an d OE
inputs from the 82C88 DT/R and DEN signals.
The pointer into the interrupt vector table, which is passed
during the second INTA cycle, can be derived from an
82C59A located on either the local bus or the system bus. If
the master 82C59A Priority Interrupt Controller is positioned
on the local bus, the 82C86/82C87 transceiver must be
disabled when reading from the master 82C59A during the
interrupt acknowledge sequence and software “poll”.
TABLE 5.
BHE A0 CHARACTERISTICS
0 0 Whole word
0 1 Upper Byte From/To Odd Address
1 0 Lower Byte From/To Even Address
11None
80C86
16 FN2957.3
January 9, 2009
FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION
FIGURE 6B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION
GND
82C8A/85
CLOCK
BHE
A16-A19
AD0-AD15
ALE
80C86
CPU
DT/R
WR
RD
MN/MX
RESET
READY
CLK
VCC C1
C2
GND
GND
1
20
40
C1 = C2 = 0.1µF
VCC
VCC
STB
OE
82C82
T
OE
82C86
TRANSCEIVER
(2) BHE
ADDR
DATA
A0
E G
HM-6616
CMOS PROM (2)
2k x 8 2k x 8
CS RDWR
CMOS
82CXX
PERIPHERALS
HM-6516
CMOS RAM
2k x 8
WG
GND
VCC
WAIT
STATE
GENERATOR
GENERATOR
RES RDY
M/IO
INTA
DEN
LATCH
2 OR 3
EHEL
2k x 8
ADDR/DATA
OPTIONAL
FOR INCREASED
DATA BUS DRIVE
GND
82C84A/85
CLOCK
GENERATOR/
BHE
A16-A19
AD0-AD15
LOCK
80C86
CPU
S2
S1
S0
MN/MX
RESET
READY
CLK
VCC C1
C2
GND
GND
1
20
40
C1 = C2 = 0.1µF
GND
VCC
CLK
S0
S1
S2
DEN
DT/R
ALE
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
82C88
BUS
CTRLR
STB
OE
82C82
(2 OR 3)
T
OE
82C86
TRANSCEIVER
(2) BHE
NC
NC
ADDR
DATA
A0
E G
HM-6616
CMOS PROM (2)
2k x 8 2k x 8
CS RDWR
CMOS
82CXX
PERIPHERALS
HM-65162
CMOS RAM
2k x 8
EH
GND
VCC
NC
ADDR/DATA
WAIT
STATE
GENERATOR
ELW G
2k x 8
RES RDY
80C86
17 FN2957.3
January 9, 2009
Absolute Maximum Ratings Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage. . . . . . . . . . . . GND -0.5V to VCC +0.5V
Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Operating Conditions
Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V
M80C86-2 ONLY . . . . . . . . . . . . . . . . . . . . . . . .+4.75V to +5.25V
Temperature Range
C80C86-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
M80C86-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
PDIP Package* (Note 1) . . . . . . . . . . . 50 N/A
CERDIP Package (Notes 1, 2) . . . . . . 30 6
Storage Temperature Range . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact prod uct reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
DC Electrical Specifications VCC = 5.0V, ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V, ±10%; TA = -55°C to +125°C (M80C86)
VCC = 5.0V, ±5%; TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
SYMBOL PARAMETER TEST CONDITION MIN MAX UNITS
VlH Logical One C80C86 (Note 6) 2.0 V
Input Voltage M80C86 (Note 6) 2.2 V
VIL Logical Zero Input Voltage 0.8 V
VIHC CLK Logical One Input Voltage VCC - 0.8 V
VILC CLK Logical Zero Input Voltage 0.8 V
VOH Output High Voltage lOH = -2.5mA 3.0 V
lOH = -100µA VCC - 0.4 V
VOL Output Low Voltage lOL = +2.5mA 0.4 V
IIInput Leakage Current VIN = GND or VCC DIP
Pins 17-19, 21-23, 33 -1.0 1.0 µA
lBHH Input Current-Bus Hold High VIN = - 3.0V (Note 3) -40 -400 µA
lBHL Input Current-Bus Hold Low VIN = - 0.8V (Note 4) 40 400 µA
IOOutput Leakage Current VOUT = GND (Note 6) - -10.0 µA
ICCSB Standby Power Supply Current VCC = - 5.5V (Note 5) - 500 µA
ICCOP Operating Power Supply Current FREQ = Max, VIN = VCC or GND,
Outputs Open (Note 7) -10mA/MHz
80C86
18 FN2957.3
January 9, 2009
Capacitance TA = +25°C
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
COUT Output Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
CI/O I/O Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
NOTES:
3. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34- 39.
4. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 34-39.
5. lCCSB tested during clock high time after halt instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
6. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
7. MN/MX is a strap option and should be held to VCC or GND.
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%; TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
SYMBOL PARAMETER TEST
CONDITIONS
80C86 80C86-2
UNITSMIN MAX MIN MAX
MINIMUM COMPLEXITY SYSTEM
Timing Requirements
(1) TCLCL Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V 10 10 ns
(5) TCL2C1 CLK FaIl Time From 3.5V to 1.0V 10 10 ns
(6) TDVCL Data In Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A
(Notes 8, 9) 35 35 ns
(9) TCLR1X RDY Hold Time into 82C84A (Notes 8, 9) 0 0 ns
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 10) -8 -8 ns
(13) THVCH HOLD Setup Time 35 20 ns
(14) TINVCH lNTR, NMI, TEST Setup Time (Note 9) 30 15 ns
(15) TILIH Input Rise Time (Except CLK) From 0.8V to 2.0V 15 15 ns
(16) TIHIL Input FaIl Time (Except CLK) From 2.0V to 0.8V 15 15 ns
Timing Responses
(17) TCLAV Address Valid Delay CL = 100pF 10 110 10 60 ns
(18) TCLAX Address Hold Time CL = 100pF 10 10 ns
(19) TCLAZ Address Float Delay CL = 100pF TCLAX 80 TCLAX 50 ns
(20) TCHSZ Status Float Delay CL = 100pF 80 50 ns
(21) TCHSV Status Active Delay CL = 100pF 10 110 10 60 ns
(22) TLHLL ALE Width CL = 100pF TCLCH - 20 TCLCH - 10 ns
80C86
19 FN2957.3
January 9, 2009
(23) TCLLH ALE Active Delay C L = 100pF 80 50 ns
(24) TCHLL ALE Inactive Delay CL = 100pF 85 55 ns
(25) TLLAX Address Hold Time to ALE Inactive CL = 100pF TCHCL - 10 TCHCL - 10 ns
(26) TCLDV Data Valid Delay CL = 100pF 10 110 10 60 ns
(27) TCLDX2 Data Hold Time CL = 100pF 10 10 ns
(28) TWHDX Data Hold Time After WR CL = 100pF TCLCL - 30 TCLCL - 30 ns
(29) TCVCTV Control Active Delay 1 CL = 100pF 10 110 10 70 ns
(30) TCHCTV Control Active Delay 2 CL = 100pF 10 110 10 60 ns
(31) TCVCTX Control Inactive Delay CL = 100pF 10 110 10 70 ns
(32) TAZRL Address Float to READ Active CL = 100pF 0 0 ns
(33) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns
(34) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns
(35) TRHAV RD Inactive to Next Address Active CL = 100pF TCLCL - 45 TCLCL - 40 ns
(36) TCLHAV HLDA Valid Delay CL = 100pF 10 160 10 100 ns
(37) TRLRH RD Width CL = 100pF 2TCLCL - 75 2TCLCL - 50 ns
(38) TWLWH WR Width CL = 100pF 2TCLCL - 60 2TCLCL - 40 ns
(39) TAVAL Address Valid to ALE Low CL = 100pF TCLCH - 60 TCLCH - 40 ns
(40) TOLOH Output Rise Time From 0.8V to 2.0V 20 15 ns
(41) TOHOL Output Fall Time From 2.0V to 0.8V 20 15 ns
NOTES:
8. Signal at 82C84A shown for reference only.
9. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
10. Applies only to t2 state (8ns into t3).
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%; TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Contin ued)
SYMBOL PARAMETER TEST
CONDITIONS
80C86 80C86-2
UNITSMIN MAX MIN MAX
80C86
20 FN2957.3
January 9, 2009
Waveforms
FIGURE 7A. BUS TIMING - MINIMUM MODE SYSTEM
NOTE: Signals at 82C84A are shown for reference only. RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to be
inserted.
TCVCTX
(31)
(29) TCVCTV
DEN
DT/R
(30)
TCHCTV TCLRL
(33)
(30)
TCHCTV
READ CYCLE
(35)
(34) TCLRH
RD
DATA IN
(7)
TCLDX1
(10)
TRYHCH
AD15-AD0
(24)
(17)
TCLAV
READY (80C86 INPUT)
RDY (82C84A INPUT)
SEE NOTE
ALE
BHE/S7, A19/S6-A16/S3
(17)
TCLAV
M/IO
(30) TCHCTV
CLK (82C84A OUTPUT)
(3) TCHCL
TCH1CH2
(4)
(2)
TCLCH TCHCTV
(30)
(5)
TCL2CL1
t1 t2 t3
tW
t4
(WR, INTA = VOH)
(1)
TCLCL
(26) TCLDV
(18) TCLAX
BHE, A19-A16
(23) TCLLH TLHLL
(22) TLLAX
(25)
TCHLL
TAVAL
(39) VIL
VIH
(12)
TRYLCL
(11)
TCHRYX
(19)
TCLAZ (16)
TDVCL
AD15-AD0
TRHAV
(32) TAZRL
TRLRH
(37)
TCLR1X (9)
TR1VCL (8)
S7-S3
80C86
21 FN2957.3
January 9, 2009
FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM
NOTE: T wo INT A cycles run back-to-back. The 80C86 local ADDR/DA TA bus is floating during both INT A cycles. Control signals are shown for the
second INTA cycle.
Waveforms (Continued)
t4t3t2t1
TW
TDVCL TCLDX1 (7)
TWHDX
TCVCTX
TCHCTV (30)
TCLAV
TCLAZ
TCHCTV
(31) TCVCTX
TCVCTV
(17) (26) (27)
(29) TCVCTV
DATA OUT
AD15-AD0
INVALID ADDRESS
CLK (82C84A OUTPUT)
WRITE CYCLE
(RD, INTA,
DT/R = VOH)
AD15-AD0
DEN
WR
INTA CYCLE
(SEE NOTE)
(RD, WR = VOH
BHE = VOL)
AD15-AD0
DT/R
INTA
DEN
AD15-AD0
SOFTWARE
HALT -
DEN, RD,
WR, INTA = VOH
DT/R = INDETERMINATE
SOFTWARE HALT
(29) TCVCTV
POINTER
TCL2CL1
(5)
tW
TCLAV TCLDV
TCLAX (18) TCLDX2
(29) (28)
TWLWH
(38)
(29) TCVCTV
(19) TCVCTX (31)
(6)
(30)
(31)
(17)
TCH1CH2
(4)
80C86
22 FN2957.3
January 9, 2009
AC Electrical Specifications VCC = 5.0V ±10%TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±10%;TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%;TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
TIMING REQUIREMENTS
TEST CONDITIONS
80C86 80C86-2
UNITSSYMBOL PARAMETER MIN MAX MIN MAX
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
Timing Requirements
(1) TCLCL CLK Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V 10 10 ns
(5) TCL2CL1 CLK Fall Time From 3.5V to 1.0V 10 10 ns
(6) TDVCL Data in Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A
(Notes 11, 12) 35 35 ns
(9) TCLR1X RDY Hold Time into 82C84A
(Notes 11, 12) 00ns
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 13) -8 -8 ns
(13) TlNVCH Setup Time for Recognition (lNTR, NMl,
TEST) (Note 12) 30 15 ns
(14) TGVCH RQ/GT Setup Time 30 15 ns
(15) TCHGX RQ Hold Time into 80C86 (Note 14) 40 TCHCL +
10 30 TCHCL +
10 ns
(16) TILlH Input Rise Time (Except CLK) From 0.8V to 2.0V 15 15 ns
(17) TIHIL Input Fall Time (Except CLK) From 2.0V to 0.8V 15 15 ns
Timing Responses
(18) TCLML Command Active Delay (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
535535ns
(19) TCLMH Command Inactive (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
535535ns
(20) TRYHSH READY Active to Status Passive
(Notes 13, 15) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
110 65 ns
(21) TCHSV Status Active Delay CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
10 110 10 60 ns
80C86
23 FN2957.3
January 9, 2009
(22) TCLSH Status Inactive Delay (Note 15) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
10 130 10 70 ns
(23) TCLAV Address Valid Delay CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
10 110 10 60 ns
(24) TCLAX Address Hold Time CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
10 10 ns
(25) TCLAZ Address Float Delay CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
TCLAX 80 TCLAX 50 ns
(26) TCHSZ Status Float Delay CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
80 50 ns
(27) TSVLH Status Valid to ALE High (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
20 20 ns
(28) TSVMCH Status Valid to MCE High (Note 11) CL= 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
30 30 ns
(29) TCLLH CLK low to ALE Valid (Note 11) CL= 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
20 20 ns
(30) TCLMCH CLK low to MCE High (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
25 25 ns
(31) TCHLL ALE Inactive Delay (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
418418ns
(32) TCLMCL MCE Inactive Delay (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
15 15 ns
(33) TCLDV Data Valid Delay CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
10 110 10 60 ns
AC Electrical Specifications VCC = 5.0V ±10%TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±10%;TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%;TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Contin ued)
TIMING REQUIREMENTS
TEST CONDITIONS
80C86 80C86-2
UNITSSYMBOL PARAMETER MIN MAX MIN MAX
80C86
24 FN2957.3
January 9, 2009
(34) TCLDX2 Data Hold Time CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
10 10 ns
(35) TCVNV Control Active Delay (Note 11) CL = 100pF for All
80C86 Outputs (In
Addition to 80C86 Self
Load)
545545ns
(36) TCVNX Control Inactive Delay (Note 11) CL = 100pF 10 45 10 45 ns
(37) TAZRL Address Float to Read Active CL = 100pF 0 0 ns
(38) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns
(39) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns
(40) TRHAV RD Inactive to Next Address Active CL = 100pF TCLCL
- 45 TCLCL
- 40 ns
(41) TCHDTL Direction Control Active Delay
(Note 11) CL = 100pF 50 50 ns
(42) TCHDTH Direction Control Inactive Delay
(Note 11) CL = 100pF 30 30 ns
(43) TCLGL GT Active Delay CL = 100pF 10 85 0 50 ns
(44) TCLGH GT Inactive Delay CL = 100pF 10 85 0 50 ns
(45) TRLRH RD Width CL = 100pF 2TCLCL
- 75 2TCLCL
- 50 ns
(46) TOLOH Output Rise Time From 0.8V to 2.0V 20 15 ns
(47) TOHOL Output Fall Time From 2.0V to 0.8V 20 15 ns
NOTES:
11. Signal at 82C8 4 A or 82C88 shown for reference only.
12. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
13. Applies only to t2 state (8ns into t3).
14. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.
15. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
AC Electrical Specifications VCC = 5.0V ±10%TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±10%;TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%;TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Contin ued)
TIMING REQUIREMENTS
TEST CONDITIONS
80C86 80C86-2
UNITSSYMBOL PARAMETER MIN MAX MIN MAX
80C86
25 FN2957.3
January 9, 2009
Waveforms
FIGURE 8A. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
16. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to
be inserted.
17. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high
82C88 CEN.
18. Status inactive in state just prior to t4.
t1 t2 t3 t4
TCLCL
TCH1CH2
TCL2CL1 tW
TCHCL (3)
(21) TCHSV
(SEE NOTE 17)
TCLDV
TCLAX
(23) TCLAV TCLAV
BHE, A19-A16
TSVLH
TCLLH
TR1VCL
TCHLL
TCLR1X
TCLAV TDVCL TCLDX1
TCLAX
AD15-AD0DATA IN
TRYHSH
(39) TCLRH TRHAV
(41) TCHDTL
TCLRL TRLRH TCHDTH
(37) TAZRL
TCLML TCLMH
(35) TCVNV
TCVNX
CLK
QS0, QS1
S2, S1, S0 (EXCEPT HALT)
BHE/S7, A19/S6-A16/S3
ALE (82C88 OUTPUT)
RDY (82C84 INPUT)
NOTE
READY 80C86 INPUT)
READ CYCLE
82C88
OUTPUTS
SEE NOTES
15, 16
MRDC OR IORC
DEN
S7-S3
AD15-AD0
RD
DT/R
TCLAV
(1)
(4)
(23) TCLCH
(2)
TCLSH (22)
(24) (23)
(27)
(29)
(31)
(8)
(9)
TCHRYX
(11)
(20)
(12) TRYLCL
(24)
TRYHCH (10)
(6) (7)
(23)
(40)
(42)
(45)
(38)
(18) (19)
(36)
(33)
TCLAZ
(25)
(5)
80C86
26 FN2957.3
January 9, 2009
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
19. Signals at 82C84A or 82C86 are shown for reference only.
20. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
21. Status inactive in state just prior to t4.
22. Cascade address is valid between first and second INTA cycles.
23. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown
for second INTA cycle.
Waveforms (Continued)
t1 t2 t3 t4
tW
TCLSH
(SEE NOTE 20))
TCLDX2
TCLDV
TCLAX
TCLMH
(18) TCLML
TCHDTH
(19) TCLMH
TCVNX
TCLAV
TCHSV TCLSH
CLK
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
AD15-AD0
DEN
AMWC OR AIOWC
MWTC OR IOWC
82C88
OUTPUTS
SEE NOTES
18, 19
INTA CYCLE
AD15-AD0
(SEE NOTES 21, 22)
AD15-AD0
MCE/PDEN
DT/R
INTA
DEN
82C88 OUTPUTS
SEE NOTES 18, 19
RESERVED FOR
CASCADE ADDR
(25) TCLAZ
(30) TCLMCH
TCVNV
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
(18) TCLML
TCLMH (19)
TCLDX1 (7)
(18)TCLML
POINTER
INVALID ADDRESS
AD15-AD0
S2
TCHDTL
TCHSV (21)
(34)
(22)
(33)
(24)
DATA
TCVNX (36)
(19)
(6) TDVCL
TCLMCL (32)
(41)
(42)
(35)
(36)
(23)
(21) (22)
TCLAV
(23)
TCVNV
(35)
(28) TSVMCH
80C86
27 FN2957.3
January 9, 2009
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
FIGURE 10. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
NOTE: Setup requirements for asynchronous signals only to
guarantee recognition at next CLK.
FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
Waveforms (Continued)
CLK
TCLGH
RQ/GT
PREVIOUS GRANT
AD15-AD0
RD, LOCK
BHE/S7, A19/S0-A16/S3
S2, S1, S0
TCLCL
ANY
CLK
CYCLE
>0-CLK
CYCLES
PULSE 2
80C86
TGVCH (14)
TCHGX (15) TCLGH (44)
PULSE 1
COPROCESSOR
RQ TCLAZ (25)
80C86 GT
PULSE 3
COPROCESSOR
RELEASE
(SEE NOTE)TCHSZ (26)
(1) TCLGL
(43)
COPROCESSOR
TCHSV (21)
(44)
CLK
HOLD
HLDA
AD15-AD0
BHE/S7, A19/S6-A16/S3
RD, WR, M/IO, DT/R, DEN
80C86
THVCH (13)
TCLHAV (36)
≥ 1CLK 1 OR 2
CYCLES
TCLAZ (19)
COPROCESSOR 80C86
TCLHAV (36)
CYCLE
TCHSZ (20)
THVCH ( 13)
TCHSV (21)
NMI
INTR
TEST
CLK
SIGNAL
TINVCH (SEE NOTE)
(13)
ANY CLK CYCLE
CLK
LOCK
TCLAV
ANY CLK CYCLE
(23) TCLAV
(23)
80C86
28 FN2957.3
January 9, 2009
FIGURE 13. RESET TIMING
Waveforms (Continued)
VCC
CLK
RESET
≥ 50µs
≥ 4 CLK CYCLES
(7) TCLDX1
(6) TDVCL
AC Test Circuit
NOTE: Includes stay and jig capacitance.
AC Testing Input, Output Waveform
NOTE: AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between 0.4V
and VCC. - 0.4 Input rise and fall times are driven at 1ns/V.
OUTPUT FROM
DEVICE UNDER TEST TEST POINT
CL (SEE NOTE)
INPUT
VIH + 20% VIH
VIL - 50% VIL
OUTPUT
VOH
VOL
1.5V 1.5V
80C86
29 FN2957.3
January 9, 2009
Burn-In Circuits MD80C86 CERDIP
NOTES:
24. VCC = 5.5V ±0.5V, GND = 0V.
25. Input voltage limits (except clock):
VIL (maximum) = 0.4V
VIH (minimum) = 2.6V, VIH (clock) = (VCC - 0.4V) minimum.
26. VCC/2 is external supply set to 2.7V ±10%.
27. VCL is generated on program card (VCC - 0.65V).
28. Pins 13 - 16 input sequenced instruction from internal hold devices.
29. F0 = 100kHz ±10%.
30. Node = a 40µs pulse every 2.56ms.
COMPONENTS:
1. RI = 10kΩ ±5%, 1/4W
2. RO = 1.2kΩ ±5%, 1/4W
3. RIO = 2.7kΩ ±5%, 1/4W
4. RC = 1kΩ ± ±5%, 1/4W
5. C = 0.01µF (Minimum)
33
34
35
36
37
38
40
32
31
30
29
24
25
26
27
28
21
22
23
13
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
39
GND
GND
NMI
INTR
CLK
GND
1
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RC
RI
RI
VCC/2
VCL
VCL
VCC/2
GND
VCC/2
VCC/2
RI
VCC/2
VCC/2
VCC/2
VCL
VCC
GND
RIO
RO
RO
RO
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
GND
VCL
NODE
FROM
PROGRAM
CARD
GND
GND
VCL
GND
GND
VCL
GND
GND
GND
VCL
VCL
VCL
OPEN
OPEN
OPEN
OPEN
GND
GND
F0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
A
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCC
QS2
TEST
READY
RESET
AD15
AD16
AD17
AD18
AD19
BHE
MX
RD
RQ0
RQ1
LOCK
S2
S1
S0
QS0
C
A
80C86
30 FN2957.3
January 9, 2009
Metallization Topology
DIE DIMENSIONS:
249.2 x 290.9 x 19
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout 80C86
AD11 AD12 AD13 AD14 A17/S4A18/S5GND A16/S3VCC AD15
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI INTR CLK GND RESET READY TEST QS1 QS0
80C86
31 FN2957.3
January 9, 2009
Instruction Set Summary
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
DATA TRANSFER
MOV = Move:
Register/Memory to/from Register 1 0 0 0 1 0 d w mod reg r/m
Immediate to Register/Memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w 1
Immediate to Register 1 0 1 1 w reg data data if w 1
Memory to Accumulator 1 0 1 0 0 0 0 w addr-low addr-high
Accumulator to Memory 1 0 1 0 0 0 1 w addr-low addr-high
Register/Memory to Segment Register †† 1 0 0 0 1 1 1 0 mod 0 reg r/m
Segment Register to Register/Memory 1 0 0 0 1 1 0 0 mod 0 reg r/m
PUSH = Push:
Register/Memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP = Pop:
Register/Memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m
Register 0 1 0 1 1 reg
Segment Register 0 0 0 reg 1 1 1
XCHG = Exchange:
Register/Memory with Register 1 0 0 0 0 1 1 w mod reg r/m
Register with Accumulator 1 0 0 1 0 reg
IN = Input from:
Fixed Port 1 1 1 0 0 1 0 w port
Variable Port 1 1 1 0 1 1 0 w
OUT = Output to:
Fixed Port 1 1 1 0 0 1 1 w port
Variable Port 1 1 1 0 1 1 1 w
XLAT = Translate Byte to AL 1 1 0 1 0 1 1 1
LEA = Load EA to Register2 1 0 0 0 1 1 0 1 mod reg r/m
LDS = Load Pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m
LES = Load Pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m
LAHF = Load AH with Flags 1 0 0 1 1 1 1 1
SAHF = Store AH into Flags 1 0 0 1 1 1 1 0
PUSHF = Push Flags 1 0 0 1 1 1 0 0
POPF = Pop Flags 1 0 0 1 1 1 0 1
ARITHMETIC
ADD = Add:
Register/Memory with Register to Either 0 0 0 0 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s:w = 01
Immediate to Accumulator 0 0 0 0 0 1 0 w data data if w = 1
80C86
32 FN2957.3
January 9, 2009
ADC = Add with Carry:
Register/Memory with Register to Either 0 0 0 1 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s:w = 01
Immediate to Accumulator 0 0 0 1 0 1 0 w data data if w = 1
INC = Increment:
Register/Memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m
Register 0 1 0 0 0 reg
AAA = ASCll Adjust for Add 0 0 1 1 0 1 1 1
DAA = Decimal Adjust for Add 0 0 1 0 0 1 1 1
SUB = Subtract:
Register/Memory and Register to Either 0 0 1 0 1 0 d w mod reg r/m
Immediate from Register/Memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s:w = 01
Immediate from Accumulator 0 0 1 0 1 1 0 w data data if w = 1
SBB = Subtract with Borrow
Register/Memory and Register to Either 0 0 0 1 1 0 d w mod reg r/m
Immediate from Register/Memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s:w = 01
Immediate from Accumulator 0 0 0 1 1 1 0 w data data if w = 1
DEC = Decrement:
Register/Memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m
Register 0 1 0 0 1 reg
NEG = Change Sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m
CMP = Compare:
Register/Memory and Register 0 0 1 1 1 0 d w mod reg r/m
Immediate with Register/Memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s:w = 01
Immediate with Accumulator 0 0 1 1 1 1 0 w data data if w = 1
AAS = ASCll Adjust for Subtract 0 0 1 1 1 1 1 1
DAS = Decimal Adjust for Subtract 0 0 1 0 1 1 1 1
MUL = Multiply (Unsigned) 1 1 1 1 0 1 1 w mod 1 0 0 r/m
IMUL = Integer Multiply (Signed) 1 1 1 1 0 1 1 w mod 1 0 1 r/m
AAM = ASCll Adjust for Multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0
DlV = Divide (Unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m
IDlV = Integer Divide (Signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m
AAD = ASClI Adjust for Divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0
CBW = Convert Byte to Word 1 0 0 1 1 0 0 0
CWD = Convert Word to Double Word 1 0 0 1 1 0 0 1
LOGIC
NOT = Invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m
SHL/SAL = Shift Logical/Arithmetic Left 1 1 0 1 0 0 v w mod 1 0 0 r/m
SHR = Shift Logical Right 1 1 0 1 0 0 v w mod 1 0 1 r/m
Instruction Set Summary (Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
33 FN2957.3
January 9, 2009
SAR = Shift Arithmetic Right 1 1 0 1 0 0 v w mod 1 1 1 r/m
ROL = Rotate Left 1 1 0 1 0 0 v w mod 0 0 0 r/m
ROR = Rotate Right 1 1 0 1 0 0 v w mod 0 0 1 r/m
RCL = Rotate Through Carry Flag Left 1 1 0 1 0 0 v w mod 0 1 0 r/m
RCR = Rotate Through Carry Right 1 1 0 1 0 0 v w mod 0 1 1 r/m
AND = And:
Reg./Memory and Register to Either 0 0 1 0 0 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w = 1
Immediate to Accumulator 0 0 1 0 0 1 0 w data data if w = 1
TEST = And Function to Flags, No Result:
Register/Memory and Register 1 0 0 0 0 1 0 w mod reg r/m
Immediate Data and Register/Memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w = 1
Immediate Data and Accumulator 1 0 1 0 1 0 0 w data data if w = 1
OR = Or:
Register/Memory and Register to Either 0 0 0 0 1 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 0 1 r/m data data if w = 1
Immediate to Accumulator 0 0 0 0 1 1 0 w data data if w = 1
XOR = Exclusive Or:
Register/Memory and Register to Either 0 0 1 1 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w = 1
Immediate to Accumulator 0 0 1 1 0 1 0 w data data if w = 1
STRING MANIPULATION
REP = Repeat 1 1 1 1 0 0 1 z
MOVS = Move Byte/Word 1 0 1 0 0 1 0 w
CMPS = Compare Byte/Word 1 0 1 0 0 1 1 w
SCAS = Scan Byte/Word 1 0 1 0 1 1 1 w
LODS = Load Byte/Word to AL/AX 1 0 1 0 1 1 0 w
STOS = Stor Byte/Word from AL/A 1 0 1 0 1 0 1 w
CONTROL TRANSFER
CALL = Call:
Direct Within Segment 1 1 1 0 1 0 0 0 disp-low disp-high
Indirect Within Segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m
Direct Intersegment 1 0 0 1 1 0 1 0 offset-low offset-high
seg-low seg-high
Indirect Intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m
JMP = Unconditional Jump:
Direct Within Segment 1 1 1 0 1 0 0 1 disp-low disp-high
Direct Within Segment-Short 1 1 1 0 1 0 1 1 disp
Indirect Within Segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m
Instruction Set Summary (Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
34 FN2957.3
January 9, 2009
Direct Intersegment 1 1 1 0 1 0 1 0 offset-low offset-high
seg-low seg-high
Indirect Intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m
RET = Return from CALL:
Within Segment 1 1 0 0 0 0 1 1
Within Seg Adding lmmed to SP 1 1 0 0 0 0 1 0 data-low data-high
Intersegment 1 1 0 0 1 0 1 1
Intersegment Adding Immediate to SP 1 1 0 0 1 0 1 0 data-low data-high
JE/JZ = Jump on Equal/Zero 0 1 1 1 0 1 0 0 disp
JL/JNGE = Jump on Less/Not Greater or Equal 0 1 1 1 1 1 0 0 disp
JLE/JNG = Jump on Less or Equal/ Not Greater 0 1 1 1 1 1 1 0 disp
JB/JNAE = Jump on Below/Not Above or Equal 0 1 1 1 0 0 1 0 disp
JBE/JNA = Jump on Below or Equal/Not Above 0 1 1 1 0 1 1 0 disp
JP/JPE = Jump on Parity/Parity Even 0 1 1 1 1 0 1 0 disp
JO = Jump on Overflow 0 1 1 1 0 0 0 0 disp
JS = Jump on Sign 0 1 1 1 1 0 0 0 disp
JNE/JNZ = Jump on Not Equal/Not Zero 0 1 1 1 0 1 0 1 disp
JNL/JGE = Jump on Not Less/Greater or Equal 0 1 1 1 1 1 0 1 disp
JNLE/JG = Jump on Not Less or Equal/Greater 0 1 1 1 1 1 1 1 disp
JNB/JAE = Jump on Not Below/Above or Equal 0 1 1 1 0 0 1 1 disp
JNBE/JA = Jump on Not Below or Equal/Above 0 1 1 1 0 1 1 1 disp
JNP/JPO = Jump on Not Par/Par Odd 0 1 1 1 1 0 1 1 disp
JNO = Jump on Not Overflow 0 1 1 1 0 0 0 1 disp
JNS = Jump on Not Sign 0 1 1 1 1 0 0 1 disp
LOOP = Loop CX Times 1 1 1 0 0 0 1 0 disp
LOOPZ/LOOPE = Loop While Zero/Equal 1 1 1 0 0 0 0 1 disp
LOOPNZ/LOOPNE = Loop While Not Zero/Equal 1 1 1 0 0 0 0 0 disp
JCXZ = Jump on CX Zero 1 1 1 0 0 0 1 1 disp
INT = Interrupt
Type Specified 1 1 0 0 1 1 0 1 type
Type 3 1 1 0 0 1 1 0 0
INTO = Interrupt on Overflow 1 1 0 0 1 1 1 0
IRET = Interrupt Return 1 1 0 0 1 1 1 1
PROCESSOR CONTROL
CLC = Clear Carry 1 1 1 1 1 0 0 0
CMC = Complement Carry 1 1 1 1 0 1 0 1
STC = Set Carry 1 1 1 1 1 0 0 1
CLD = Clear Direction 1 1 1 1 1 1 0 0
Instruction Set Summary (Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
35 FN2957.3
January 9, 2009
STD = Set Direction 1 1 1 1 1 1 0 1
CLl = Clear Interrupt 1 1 1 1 1 0 1 0
ST = Set Interrupt 1 1 1 1 1 0 1 1
HLT = Halt 1 1 1 1 0 1 0 0
WAIT = Wait 1 0 0 1 1 0 1 1
ESC = Escape (to External Device) 1 1 0 1 1 x x x mod x x x r/m
LOCK = Bus Lock Prefix 1 1 1 1 0 0 0 0
NOTES:
AL = 8-bit accumulator
AX = 16-bit accumulator
CX = Count register
DS= Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater = more positive;
Less = less positive (more negative) signed values
if d = 1 then “to” reg; if d = 0 then “from” reg
if w = 1 then word instruction; if w = 0 then byte
instruction
if mod = 11 then r/m is treated as a REG field
if mod = 00 then DISP = O†, disp-low and disp-high
are absent
if mod = 01 then DISP = disp-low sign-extended
16-bits, disp-high is absent
if mod = 10 then DISP = disp-high:disp-low
if r/m = 000 then EA = (BX) + (SI) + DISP
if r/m = 001 then EA = (BX) + (DI) + DISP
if r/m = 010 then EA = (BP) + (SI) + DISP
if r/m = 011 then EA = (BP) + (DI) + DISP
if r/m = 100 then EA = (SI) + DISP
if r/m = 101 then EA = (DI) + DISP
if r/m = 110 then EA = (BP) + DISP †
if r/m = 111 then EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data
if required)
†except if mod = 00 and r/m = 110 then
EA = disp-high: disp-low.
†† MOV CS, REG/MEMORY not allowed.
if s:w = 01 then 16-bits of immediate data form the operand.
if s:w. = 11 then an immediate data byte is sign extended
to form the 16-bit operand.
if v = 0 then “count” = 1; if v = 1 then “count” in (CL)
x = don't care
z is used for string primitives for comparison with ZF FLAG.
SEGMENT OVERRIDE PREFIX
001 reg 11 0
REG is assigned according to the following table:
16-BIT (w = 1) 8-BIT (w = 0) SEGMENT
000 AX 000 AL 00 ES
001 CX 001 CL 01 CS
010 DX 010 DL 10 SS
011 BX 011 BL 11 DS
100 SP 100 AH 00 ES
101 BP 101 CH 00 ES
110 SI 110 DH 00 ES
111 DI 111 BH 00 ES
Instructions which reference the flag register file as a 16-bit object
use the symbol FLAGS to represent the file:
FLAGS =
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics © Intel, 1978
Instruction Set Summary (Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
36 FN2957.3
January 9, 2009
80C86
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.980 2.095 50.3 53.2 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N40 409
Rev. 0 12/93
80C86
37
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of I nter sil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2957.3
January 9, 2009
80C8680C86
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.225 - 5.72 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 2.096 - 53.24 5
E 0.510 0.620 12.95 15.75 5
e 0.100 BSC 2.54 BSC -
eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.070 0.38 1.78 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N40 408
Rev. 0 4/94
