NJW1111
– 1
–
Ver.4.0
9-IN 3-OUT STEREO AUDIO SELECTOR
!
!!
!
GENERAL DESCRIPTION !
!!
!
PACKAGE OUTLINE
The NJW1111 is a 9-input 3-output stereo audio selector.
It includes three independent 9input-1output stereo audio selectors
and adjustable gain buffers.
The NJW1111 performs superior audio characterist ics such as low
distorti on, lo w output no is e and lo w cross talk .
All of internal status and variables are controlled by three-wired
serial bus. Selectable two Chip address is available for using two
chips on same serial bus line. It is suitable for AV amplifier and
receiver system and others.
!
!!
!
FEATURES
• Operating Voltage ±4.5 to ±7.5V
• 9-Input, 3-Output Stereo Audio Selector
• Operating Current 8mA typ.
• Low Distortion 0.0007% typ.
• Low Output Noise -116dBV typ.
• Low Crosstalk 110dB typ.
• Channel Separation 110dB typ.
• Variable Gain Buffer 0, 3 to 8dB/0.5dB step
• 3-Wired Serial Control
• Bi-CMOS Technology
• Package Outline SSOP32
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!
BLOCK DIAGRAM
NJW1111V
26 25 2432 31 30 29 28 27 19 18 1723 22 21 20
7 8 9 1 2 3 4 5 6 14 15 1610 11 12 13
Control Logic
++++ +
++ + + +
+
10µF10
µF10
µF10
µF10µF
100µF
10µF10
µF10
µF10
µF10µF
OutA3
V-
8dB to 3dB
/ 0. 5dBstep
Gain
8dB to 3dB
/ 0. 5dBstep
Gain
GND
ADR
+
10µF
OutA2
+
10µF
OutA1
+
10µF
+
10µF
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB t o 3dB
/ 0.5dB st ep
Gain
8dB t o 3dB
/ 0.5dB st ep
Gain
+
10µF
+
10µF
+
10µF
+
10µF
+
10µF
++++
10µF10
µF10
µF10
µF
+
10µF
InA4
GND
50KΩX１８
LATCH DATA CLOCK
V+
+
100µF
InA1 InA3InA2 InA7 InA8 InA9InA6
InA5
InB4InB1 InB3InB2 InB7 InB8 InB9InB6
InB5 OutB3OutB2OutB1
NJW1111
– 2 –
Ver.4.0
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!PIN CONFIGURATION
No. Symbol Function No. Symbol Function
1 InA1 Ach Input 1 17 V- V- Power Supply Term i nal
2 InA2
Ach Input 2
18 V+ V+ Power Supply Terminal
3 InA3
Ach Input 3
19 ADR Chip address setting terminal
4 InA4
Ach Input 4
20 OutB3 Bch Output 3
5 InA5
Ach Input 5
21 OutB2 Bch Output 2
6 InA6
Ach Input 6
22 OutB1 Bch Output 1
7 InA7
Ach Input 7
23 GND Ground Terminal
8 InA8
Ach Input 8
24 InB9
Bch Input 9
9 InA9
Ach Input 9
25 InB8
Bch Input 8
10 GND Ground Terminal 26 InB7
Bch Input 7
11 OutA1 Ach Output 1 27 InB6
Bch Input 6
12 OutA2 Ach Output 2 28 InB5
Bch Input 5
13 OutA3 Ach Output 3 29 InB4
Bch Input 4
14 LATCH LATCH 30 InB3
Bch Input 3
15 DATA DATA 31 InB2
Bch Input 2
16 CLOCK CLOCK 32 InB1
Bch Input 1
16
32
31
30
29
28
27
26
25
24
23
20
21
22
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
InA1
InA2
InA3
InA4
InB1
InB2
InB3
InB4
OutA1 OutB1
DATA
CLOCK
LATCH
GND
V-
V+ 18
16 17
InA5
InA6
InA7
InA8
InB5
InB6
InB7
InB8
InA9 InB9
OutA2 OutB2
OutA3 OutB3
GND
A
DR
NJW1111
– 3 –
Ver.4.0
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!
ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER SYMBOL RATING UNIT
Power Supply Voltage V
+
+8/-8
V
Maximum Input Voltage V
IM
V
+
/V
-
V
Power Dissipation P
D
800
NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
mW
Operating Temperature Range Topr -40 to +85 °C
Storage Temperature Range Tstg -40 to +125 °C
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!
RECOMMENDED OPERATING CONDITIONS (Ta=25°C)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Operating Voltage V
+
/V
-
- ±4.5 ±7.0 ±7.5
V
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!!
!
ELECTRICAL CHARACTERISTICS
♦
♦♦
♦Power Supply (Ta=25°C, V
+
/V
-
=±7V)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Supply Current 1 I
CC
V
+
, No Signal 4.0 8.0 12.0 MA
Supply Current 2 I
EE
V
-
No Signal 4.0 8.0 12.0 MA
♦
♦♦
♦AC C HARACTE RIS TICS (Ta=25°C, V
+
/V
-
=±7V, V
IN
=1Vrms,f=1kHz,R
L
=47k
Ω
)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Maximum Output Voltage V
OM
THD=1% 10.6
(3.4)
12.9
(4.4)
- dBV
(Vr ms)
Voltage Gain 1 G
V1
- -0.5 0 0.5
Voltage Gain 2 G
V2
V
IN
=200mVrms, Gain=6dB 5.0 6.0 7.0 dB
Total Harmonic Distortion 1 THD1 BW=400Hz-30kHz - 0.0007 0.02
Total Harmonic Distortion 2 THD2 Vin=2Vrms,
BW=400Hz-30kHz - 0.001 -
Total Harmonic Distortion 3 THD3 f=10kHz, BW=400Hz-30kHz - 0.001 -
%
Mute Level A
TT
Selector=Mute, A-weighted - -110 - dB
Output Noise V
NO
Rg=0Ω, A- Wei ghted - -116
(1.6)
-106
(5.0)
dBV
(µVrms)
Cross Talk 1 CT1 Rg=0Ω, A-Weighted - -110 -
Cross Talk 2 CT2 Rg=0Ω, f=20kHz - -96 - dB
Channel Separation 1 CS1 Rg=0Ω, A- Weighted - -1 10 -90
Channel Separation 2 CS2 Rg=0Ω, f=20kHz - -96 - dB
BW: Band W i dth
♦
♦♦
♦Logic Control Characteristics (Ta=25°C, V
+
/V
-
=±7V)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
High Level Input Voltage V
ADRH
ADR Terminal 2.5 - V
+
Low Level Input Voltage V
ADRL
ADR Terminal 0 - 1.5 V
NJW1111
– 4 –
Ver.4.0
!
!!
! TERMINAL DESCRIPTION
PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL
DC
VOLTAGE
1 to 9
32 to 24 InA1 to 9
InB1 to 9 Ach Input 1 to 9
Bch Input 1 to 9
0V
11 to 13
22 to 20 OutA1 to 3
OutB1 to 3 Ach Output 1 to 3
Bch Output 1 to 3
0V
18 V
+
V+ Power Supply Terminal
V+
10
23 GND Ground Terminal
0V
14
15
16
19
LATCH
DATA
CLOCK
ADR
LATCH
DATA
CLOCK
Chip address setting terminal
0V
GND
V-(sub)
200Ω
V+
50kΩ
V-(sub)
200Ω
V+
V+
50Ω
50Ω
V-(sub)
V-(sub)
V+
V-(sub)
4kΩ
8kΩ
V+
NJW1111
– 5 –
Ver.4.0
!
!!
! CONTROL DATA FORMAT
(
✴
)
MSB First
SYMBOL PARAMETER MIN TYP MAX UNIT
t1
CLOCK Clock Width
4 - -
µsec
t2
CLOCK Puls e Width (High)
2 - -
µsec
t3
CLOCK Puls e Width (Low)
2 - -
µsec
t4
LATCH Rise Hold Time
4 - -
µsec
t5
DATA Setup Time
1.6 - - µsec
t6
DATA Hold Time
1.6 - - µsec
t7
CLOCK Set up T ime
1.6 - - µsec
t8
LATCH High Pulse Width
1.6 - - µsec
LATCH
DAT
A
CLOCK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
t7 t1
t2 t3
t4 t8
t5 t6
NJW1111
– 6 –
Ver.4.0
!
!!
! CONTROL DATA
NJW1111 control data is constructed with 16bits.
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Setting DATA Select Address Chip Address
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Gain1 Selector1 0 0 0 0 * * * *
Gain2 Selector2 0 0 0 1 * * * *
Gain3 Selector3 0 0 1 0 * * * *
* Chip address is set by chip address select terminal (ADR) status.
Chip Address
Chip address select
terminal
D3 D2 D1 D0
Low 1 0 1 0
High 1 0 1 1
!
!!
!INITIAL CONDITION
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0 * * * *
0 0 0 0 0 0 0 0 0 0 0 1 * * * *
0 0 0 0 0 0 0 0 0 0 1 0 * * * *
* Chip address is set by chip address select terminal (ADR) status.
NJW1111
– 7 –
Ver.4.0
!
!!
! CONTROL DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Gain1 Selector1 0 0 0 0 * * * *
Gain2 Selector2 0 0 0 1 * * * *
Gain3 Selector3 0 0 1 0 * * * *
a)Gain
DATA
D15 D14 D13 D2
Setting
0 0 0 0 0dB
0 0 0 1 +3.0 dB
0 0 1 0 +3.5 dB
0 0 1 1 +4.0 dB
0 1 0 0 +4.5 dB
0 1 0 1 +5.0 dB
0 1 1 0 +5.5 dB
0 1 1 1 +6.0 dB
1 0 0 0 +6.5 dB
1 0 0 1 +7.0 dB
1 0 1 0 +7.5 dB
1 0 1 1 +8.0 dB
b)Input Selector
DATA
D11 D10 D9 D8
Setting
0 0 0 0 Mute
(
✴
)
0 0 0 1 InA1/B1
0 0 1 0 InA2/B2
0 0 1 1 InA3/B3
0 1 0 0 InA4/B4
0 1 0 1 InA5/B5
0 1 1 0 InA6/B6
0 1 1 1 InA7/B7
1 0 0 0 InA8/B8
1 0 0 1 InA9/B9
NJW1111
– 8 –
Ver.4.0
!
!!
! APPLICATION CIRCUIT
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
26 25 2432 31 30 29 28 27 19 18 1723 22 21 20
7 8 9 1 2 3 4 5 6 14 15 1610 11 12 13
Control Logic
++++ +
++ + + +
+
10µF10
µF10
µF10
µF10µF
100µF
10µF10
µF10
µF10
µF10µF
OutA3
V-
8dB t o 3dB
/ 0.5dB st ep
Gain
8dB t o 3dB
/ 0.5dB st ep
Gain
GND
ADR
+
10µF
OutA2
+
10µF
OutA1
+
10µF
+
10µF
8dB to 3dB
/ 0. 5dBstep
Gain
8dB to 3dB
/ 0. 5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
+
10µF
+
10µF
+
10µF
+
10µF
+
10µF
++++
10µF10
µF10
µF10
µF
+
10µF
InA4
GND
50KΩX１８
LATCH DATA CLOCK
V+
+
100µF
InA1 InA3InA2 InA7 InA8 InA9InA6
InA5
InB4InB1 InB3InB2 InB7 InB8 InB9InB6
InB5 OutB3OutB2OutB1
