ANALOG DEVICES Monolithic 16-Bit Serial/Byte DACPORT AD660 FEATURES Complete 16-Bit D/A Function On-Chip Output Amplifier On-Chip Buried Zener Voltage Reference +1LSB Integral Linearity 15-Bit Monotonic over Temperature Microprocessor Compatible Serial or Byte Input Double Buffered Latches Fast (40 ns) Write Pulse Asynchronous Clear (to 0 V) Function Serial Output Pin Facilitates Daisy Chaining Unipolar or Bipolar Output Low Glitch: 15 nV-s Low THD+N: 0.009% PRODUCT DESCRIPTION The AD660 DACPORT is a complete 16-bit monolithic D/A converter with an on-board voltage reference, double buffered latches and output amplifier. It is manufactured on Analog Devices BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. The AD660s architecture ensures 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is main- tained at +0.003% max. The on-chip output amplifier provides a voltage output settling time of 10 ws to within 1/2 LSB for a full-scale step. The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This is made possible by two digital input pins which have dual functions. The serial mode input format is pin selectable to be MSB or LSB first. The serial output pin allows the user to daisy chain several AD660s by shifting the data through the input latch into the next DAC thus minimizing the number of control lines required to SIN, CS and LDAC. The byte mode input format is also flexible in that the high byte or low byte data can be loaded first. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. The AD660 is available in five grades. AN and BN versions are specified from 40C to +85C and are packaged in a 24-pin 300 mil plastic DIP. AR and BR versions are also specified from 40C to +85C and are packaged in a 24-pin SOIC. The SQ version is packaged in a 24-pin 300 mil cerdip package and is also available compliant to MIL-STD-883. Refer to the AD660/ 883B data sheet for specifications and test conditions. DACPORT is a registered trademark of Analog Devices, Inc. 3-42 DIGITAL-TO-ANALOG CONVERTERS FUNCTIONAL BLOCK DIAGRAM UNVBIP CLAY __siy meaviSBY (BE CS 080 DB1_ 087 45, 14 124114 5 __ ADE660 HBE U6 16-BIT LATCH 13) Sout SER G7) CONTROL LoGic 10k CLAS) 16-BIT LATCH e BP OFFSET LAC (19) 10.08k 10k REF IN(23) 16-BIT DAC ~ 21) v, + out +10V REF 20) AGND 24 i2 3G REFOUT -Vi, +Vac +,, DGND PRODUCT HIGHLIGHTS 1. The AD660 is a complete 16-bit DAC, with a voltage refer- ence, double buffered latches and output amplifier on a sin- gle chip. . The internal buried Zener reference is laser trimmed to 10.000 volts with a +0.1% maximum error and a tempera- ture drift performance of +15 ppm/C. The reference is available for external applications. . The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to +10 V or a bipolar output range of 10 V to +10 V. No external com- ponents are required. . The AD660 is both de and ac specified. DC specifications include +1 LSB INL and +1 LSB DNL errors. AC specifi- cations include 0.009% THD+N and 83 dB SNR. . The double buffered latches on the AD660 eliminate data skew errors and allow simultaneous updating of DACs in multi-DAC applications. - The CLEAR function can asynchronously set the output to 0 V regardless of whether the DAC is in unipolar or bipolar mode. . The output amplifier settles within 10 us to +1/2 LSB for a full-scale step and within 2.5 1s for a 1 LSB step over tem- perature. The output glitch is typically 15 nV-s when a full- scale step is loaded. REV. ASPECIF ICATIONS (Ty = +25C, Veg = +15 V, Veg = 15 V, Vy = +5 V unless otherwise noted) AD660 AD660AN/AR/SQ AD660BN/BR Parameter Min Typ Max Min Typ Max Units RESOLUTION 16 16 Bits DIGITAL INPUTS (Tyan Taax) Vis (Logic 1) 2.0 5.5 x * Volts Viz, (Logic 0) 0 0.8 * * Volts Tha Vin = 5.5 V) +10 * pA In Vn = 9 V) +10 * pA TRANSFER FUNCTION CHARACTERISTICS' Integral Nonlinearity +2 +1 LSB 3 Tau t0 Tyax +4 +2 LSB Differential Nonlinearity +2 +] LSB Tyan 10 Taax +4 +2 LSB Monotonicity Over Temperature 14 15 Bits Gain Error ? +0.10 * % of FSR Gain Drift? (Tyr to T, 25 15 ppm/C DAC Gain eet max) . +0.05 * % of FSR DAC Gain Drift* 10 * ppm/Cc Unipolar Offset #2.5 * mV Unipolar Offset Drift (Tain to Taax) 3 * ppm/??C Bipolar Zero Error +7.5 * mV Bipolar Zero Error Drift (Tain to Tmax) 5 * ppm/C REFERENCE INPUT Input Resistance 7 10 13 * * * kQ Bipolar Offset Input Resistance 7 10 13 * * * ka REFERENCE OUTPUT Voltage 9.99 10.00 10.01 * * * Volts Drift 25 15 ppm/C External Current? 2 4 * x mA Capacitive Load 1000 * pF Short Circuit Current 25 * mA OUTPUT CHARACTERISTICS Output Voltage Range / Unipolar Configuration _. 0 +10 * * Volts Bipolar Configuration ~10 +10 * * Volts Output Current : 5 * mA Capacitive Load 1000 * pF Short Circuit Current 25 * mA POWER SUPPLIES Voltage Vec +13.5 +16.5 * * Volts Ver ~13.5 16.5 * * , Volts Vit +4.5 +5.5 * * Volts Current (No Load) Tec +12 +18 * * mA Teg -12 18 * * mA Ii @ Vip Vin = 5,0V 0.3 2 x * mA @ Vins Vin = 2.4, 0.4 V 3 75 * * mA Power Supply Sensitivity 1 2 * * ppm/% Power Dissipation (Static, No Load) 365 625 * * mW TEMPERATURE RANGE Specified Performance (A, B) 40 +85 * * C Specified Performance (S) 55 +125 C NOTES 1For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, | LSB = 0.006% of FSR. FSR stands for Full-Scale Range and is 10 V in a Unipolar Mode and 20 V in Bipolar Mode. Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660 can be used with a precision external reference such as the AD587, AD586 or AD688. Gain Error is measured with fixed 50 1 resistors as shown in the Application section. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). *DAC Gain Error and Drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference. External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660. Operation on +12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section. *Indicates that che specification is the same as AD660AN/AR/SQ. Specifications subject to change without notice. REV. A DIGITAL-TO-ANALOG CONVERTERS 3-43AD660 AC PERFORMANCE CHARACTERIST Ics (With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. Twn << Ta = Taw Veo = +15 V, Vee = 15 V, Vi, = +5 V except where noted.) Parameter Limit Units Test Conditions/Comments Output Settling Time 13 ps max 20 V Step, Ty = +25C (Time to +0.0008% FS 8 ps typ 20 V Step, T, = +25C with 2 kQ, 1000 pF Load) 10 ps typ 20 V Step, Tyaw = Ta = Tmax 6 ps typ 10 V Step, T, = +25C 8 BS typ 10 V Step, Tym = Ta = Tomax 2.5 ps typ 1 LSB Step, Turn = Ta = Thax Total Harmonic Distortion + Noise A, B, S Grade 0.009 % max 0 dB, 990.5 Hz; Sample Rate = 96 kHz; T, = +25C A, B, Grade 0.056 % max ~20 dB, 990.5 Hz; Sample Rate = 96 kHz; T, = +25C A, B, Grade 5.6 % max ~60 dB, 990.5 Hz; Sample Rate = 96 kHz; T, = +25C Signal-to-Noise Ratio 83 dB min Ta = +25C Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000,, and 7FFF,, Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000,; and FFFF,,; CS High Output Noise Voltage 120 nV/Rt Hz typ Measured at Voy, 20 V Span; Excludes Reference Density (1 kKHz-1 MHz) Reference Noise 125 nV/Rt Hz typ Measured at REF OUT Specifications subject to change without notice. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high cnergy clectrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS* Veco toAGND ........0......00000. 0.3 V to +17.0 V Vex to AGND ........0.......04.. +0.3 V to -17.0 V Viz toDGND .............-..00.-- -0.3Vt0+7V AGND to DGND .................-..-020000- #1V Digital Inputs (Pins 5 through 23) to DGND ..... 1.0 V to +7.0V REF IN to AGND ..........-....2.002005 10.5 V Span/Bipolar Offset to AGND ..............-5. 10.5 V Ref Out, Vour --..--- Indefinite Short To AGND, DGND, Voc> Vex, and Viz Power Dissipation (Any Package) To +60 2. ee eee 1000 mW Derates above +60C .. 6.0... 2... ee eee 8.7 mW/C Storage Temperature ................ -65C to +150C Lead Temperature (Soldering, 10 sec) .............. 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3-44 DIGITAL-TO-ANALOG CONVERTERS Tee eel eth TAEDA ae Pika 01 PIN CONFIGURATION Vy ve [1 eo 24] REF OUT Vee [2] 23] REF IN Vv. SPAN, mee [3 [23] BIPOLAR OFFSET peno [6 | 21] Your ps7, 15 [6 | 20] AGND DB6, 14 [s| AD660 /19] LDAC TOP VIEW DBS, 13 7 {Not to Scate) DB4, 12 [e] DBS, 11 [s| 062, 10 [10 0B1, 9, MSB/LSB |11 Bo, 8, SIN [12| Fa] ata li7] SER Fa] ABE 5] LBE, UNVBIP CLEAR fra] oS 3] Sour REV. AAD660 ORDERING GUIDE Linearity Error Max | Linearity Error Max | Gain TC max | Package Package Model Temperature Range | +25C Tan Tomax ppm/C Description | Option* AD660AN -40C to + 85C +2 LSB +4 LSB 25 Plastic DIP | N-28 AD660AR ~40C to + 85C +2 LSB +4 LSB 25 SOIC R-28 AD660BN 40C to +85C +1 LSB +2 LSB 15 Plastic DIP | N-28 AD660BR 40C to +85C +1 LSB +2 LSB 15 SOIC R-28 AD660SQ ~55C to +125C +2 LSB +4 LSB 25 Cerdip Q-28 AD660SQ/883B** | 55C to +125C +2 LSB a xe ae ak *N = Plastic DIP; Q = Cerdip; R = SOIC. For outline information see Package Information section. **Refer to AD660/883B military data sheet. TIMING CHARACTERISTICS v,, = +15, vee = -15. Vy = +5, Vy, = 24V, Vy = 04V Parameter Limit +25C [ Limit 55C to +125C Units (Figure 1a) tes 40 50 ns min Ips 40 50 ns min py 0 10 ns min tgEs 40 50 ns min tpEH 0 10 ns min toy 80 100 ms min lw 40 50 ns min (Figure 1b) toLK 80 100 ns min tLo 30 50 ns min tar 30 50 ns min tgs 0 10 ns min tps 40 50 ns min tou 0 10 ns min tsi 0 10 ms min tly 80 100 ns min tlw 40 50 ns thin (Figure Ic) tcLR 80 110 ns min tser 80 110 ns min tyoLD 0 10 ns min (Figure Id) "prop 30 100 ns min tos 50 80 ns min Specifications subject to change without notice. BIT 0-7 HBE_OR LBE LOAC REV. A w<" Figure la. AD660 Byte Load Timing = DIGITAL-TO-ANALOG CONVERTERS 3-45AD660 >< xX BITO * VALID 1 x . VAUD 16 Pa | l= tos fon | ton SER tes tc ae i T as Bm "1" = MSB FIRST, "0" =LSBFIRST 27 <a t, 1 |} tok LDAC ee Figure 1b. AD660 Serial Load Timing ar / ar \ J ~~ oe x 1 = BIP 0, o" = UNIO beer > | toto xX Figure 1c. Asynchronous Clear to Bipolar or Unipolar Zero BITO x VALID 16 x aaa x x t-te | DS SER BIT} (MSB/LSB) SERIAL OUT x VALID Sgy71 xX Figure 1d. Serial Out Timing DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY: Analog Devices defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS-1 LSB) for any bit combination. This is also referred to as relative accuracy. DIFFERENTIAL NONLINEARITY: Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with a 1 LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be greater than or equal to ] LSB over the temperature range of interest. MONOTONICITY: A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. GAIN ERROR: Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. OFFSET ERROR: Offset error is a combination of the offset errors of the voltage-mode DAC and the output amplifier and is measured with all 0s loaded in the DAC. 3-46 DIGITAL-TO-ANALOG CONVERTERS BIPOLAR ZERO ERROR: When the AD660 is connected for bipolar output and 10. . . 000 is loaded in the DAC, the devia- tion of the analog output from the ideal midscale value of 0 V is called the bipolar zero error. DRIFT: Drift is the change in a parameter (such as gain, offset and bipolar zero) over a specified temperature range. The drift temperature coefficient, specified in ppm/C, is calculated by measuring the parameter at Tun, 25C and Ty,x and dividing the change in the parameter by the corresponding temperature change. TOTAL HARMONIC DISTORTION + NOISE: Total har- monic distortion + noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input fre- quency. It is usually expressed in percent (%). THD+N is a measure of the magnitude and distribution of lin- earity error, differential linearity error, quantization error and noise. The distribution of these errors may be different, depend- ing upon the amplitude of the output signal. Therefore, to be the most useful], THD+N should be specified for both large and small signal amplitudes. REV. ASIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full- scale signal is present to the output with no signal present. This is measured in dB. DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is measured at half scale when the DAC switches around the MSB and as many as possible switches change state, i.e., from 011... 111 to 100. . . 000. DIGITAL FEEDTHROUGH: When the DAC is not selected (i.e., CS is held high), high frequency logic activity on the digi- tal inputs is capacitively coupled through the device to show up as noise on the Voyry pin. This noise is digital feedthrough. THEORY OF OPERATION The AD660 uses an array of bipolar current sources with MOS current steering switches to develop a current proportional to the applied digital word, ranging from 0 to 2 mA. A segmented architecture is used, where the most significant four data bits are thermometer decoded to drive 15 equal current sources. The lesser bits are scaled using a R-2R ladder, then applied together with the segmented sources to the summing node of the output amplifier. The internal span/bipolar offset resistor can be con- nected to the DAC output to provide a 0 V to +10 V span, or it can be connected to the reference input to provide a 10 V to +10 V span. REFOUT -V.. +Voo +,, DGND Figure 2. AD660 Functional Block Diagram ANALOG CIRCUIT CONNECTIONS Internal scaling resistors provided in the AD660 may be con- nected to produce a unipolar output range of 0 V to +10 V ora bipolar output range of ~10 V to +10 V. Gain and offset drift are minimized in the AD660 because of the thermal tracking of the scaling resistors with other device components. UNIPOLAR CONFIGURATION The configuration shown in Figure 3a will provide a unipolar 0 V to +10 V ourput range. In this mode, 50 2 resistors are tied between the span/bipolar offset terminal (Pin 22) and Voyr REV. A ADG60 (Pin 21), and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible to use the AD660 without any external com- ponents by tying Pin 24 directly to Pin 23 and Pin 22 directly to Pin 21. Eliminating these resistors will increase the gain error by 0.25% of FSR. UNVBIP CLAY_ IP C SIN MSB/LSB/ iBE CS DB0 DBI 087 15)>(14)-42)(411 5 BE Ge 1 AD660 16-BIT LATCH 43) Sour SER (Gp)-| CONTROL 3 Loaic SPAN 10k BIP OFF CLAUS 16-BIT LATCH 22 q << R2 LDAC (19 | 10.05k S500 AA 6-BIT DAC y, (23 1 - REF IN 27), + OUTPUT +10V REF '20) AGND ) 1)(2 3)(4 Ri $00) REF OUT Vee Voc Vi, GND Figure 3a. 0 V to +10 V Unipolar Voltage Output If it is desired to adjust the gain and offset errors to zero, this can be accomplished using the circuit shown in Figure 3b. The adjustment procedure is as follows: STEP1 ... ZERO ADJUST Turn all bits OFF and adjust zero trimmer, R4, until the output reads 0.000000 volts (1 LSB = 153 pV). STEP 2... GAIN ADJUST Turn all bits ON and adjust gain trimmer, R1, until the output is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the nominal full scale of 10.000000 volts). UNI/BIP CLR/ IPCLA/_ SIN MSB/LSBY iBE CS DB0DB1 DB7 15)(14)(12)(11) (5 aw AD660 ce HBE U6 16-BIT LATCH 13) Sour sea CONTROL SER G7 Oars ara R3 16k Ra aA 10k 10k CLAS, 16-BIT LATCH aD q R2 LDac (1g 10.05k 502 -V,, A 10k EF IN 3) 16-BIT DAC = a1 + OUTPUT +10V REF 20) 24 1 (2)(3}(4 REF OUT Mee Meo My Ri 1000 DGND AGND Figure 3b. 0 V to +10 V Unipolar Voltage Output with Gain and Offset Adjustment DIGITAL-TO-ANALOG CONVERTERS 3-47ADGE0 BIPOLAR CONFIGURATION The circuit shown in Figure 4a will provide a bipolar output voltage from 10.000000 V to +9.999694 V with positive full scale occurring with all bits ON. As in the unipolar mode, resis- tors Rl and R2 may be eliminated altogether to provide AD660 bipolar operation without any external components. Eliminating these resistors will increase the gain error by 0.50% of FSR in the bipolar mode. R2 50Q AAA Wr SIN MSBYLSB/ DBO DB1 _DB7 UNVBIP CLAY ise cs AGND Figure 4a. +10 V Bipolar Voltage Output Gain offset and bipolar zero errors can be adjusted to zero using the circuit shown in Figure 4b as follows: STEP 1... OFFSET ADJUST Turn OFF all bits. Adjust trimmer R2 to give 10.000000 volts output. STEP II... GAIN ADJUST Turn all bits ON and adjust RJ to give a reading of +9.999694 volts. STEP IH... BIPOLAR ZERO ADJUST (Optional) In applications where an accurate zero output is required, set the MSB ON, all other bits OFF, and readjust R2 for zero volts output. UNVBIP CLAY ise ts SIN MSB/LSB/ DBO DBt DB MM MTN 16-BIT DAC SPAN BIP OFF Vee Vee *u = AGND DGND Figure 4b. +10 V Bipolar Voltage Output with Gain and Offset Adjustment 3-48 DIGITAL-TO-ANALOG CONVERTERS It should be noted that using external resistors will introduce a small temperature drift component beyond that inherent in the AD660. The internal resistors are trimmed to ratio-match and temperature-track other resistors on chip, even though their absolute tolerances are +20% and absolute temperature coeffi- cients are approximately 50 ppm/C. In the case that external resistors are used, the temperature coefficient mismatch between internal and external resistors, multiplied by the sensitivity of the circuit to variations in the external resistor value, will be the resultant additional temperature drift. INTERNAL/EXTERNAL REFERENCE USE The AD660 has an internal low noise buried Zener diode refer- ence which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give long-term stability equal or supe- rior to the best discrete Zener diode references. The perfor- mance of the AD660 is specified with the internal reference driving the DAC and with the DAC alone (for use with a preci- sion external reference ). The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 1 mA to REF IN and | mA to BIPOLAR OFFSET). A minimum of 2 mA is available for driving external loads. The AD660 reference output should be buffered with an external op amp if it is required to supply more than 4 mA total current. The reference is tested and guaranteed to +0.2% max error. It is also possible to use external references other than 10 volts with slightly degraded linearity specifications. The recom- mended range of reference voltages is +5 V to + 10.24 V, which allows 5 V, 8.192 V and 10.24 V ranges to be used. For exam- ple, by using the AD586 5 V reference, outputs of 0 V to +5 V unipolar or +5 V bipolar can be realized. Using the AD586 voltage reference makes it possible to operate the AD660 with +12 V supplies with 10% tolerances. REV. AFigure 5 shows the AD660 using the AD586 precision 5 V refer- ence in the bipolar configuration. The highest grade ADS86MN is specified with a drift of 2 ppm/C which is a 7.5x improve- ment over the AD660s internal reference. This circuit includes two optional potentiometers:and one optional resistor that can be used to adjust the gain, offset and bipolar zero errors in a manner similar to that described in the BIPOLAR CONFIGU- RATION section. Use 5.000000 V and +4.999847 as the out- put values. AD660 The AD660 can also be used with the AD587 10 V reference, using the same configuration shown in Figure 5 to produce a +10 V output. The highest grade ADS87LR, N is specified at 5 ppm/C, which is a 3X improvement over the AD660s internal reference. Figure 6 shows the AD660 using the AD680 precision +10 V reference, in the unipolar configuration. The highest grade AD688BQ is specified with a temperature coefficient of 1.5 ppm/C. The 10 V output is also ideal for providing pre- cise biasing for the offset trim resistor R4. LBE cs R2 50 AAA V ONVBIP CLAY SIN MSBVLSBY DBO DBI OB7 REFOUT -Vee +Vo Figure 5. Using the AD660 with the AD586 5 V Reference ONVBIP CLAY ssINy MSB/LSBY iBE CS DBO DBI oB7 15, (14, 42411 5 _ = AD660 HBE (16 16-BIT LATCH 13 Sour SER(17)| CONTROL SPAN Ra _ Locic 10k BIP OFF. Wk. ony cLACS 16-BIT LATCH 22 WW" 1082 L < LDACc(is) om 10.08k 2 Tho 23) 16-BIT DAC - Vour Rt REF IN 21 OUTPUT 7 64-3 toon +10V REF - emorin . 26) AGND At 28 1 2 3 4 S , REFOUT -V__ +V = + + Rts 4 to AD688 EE cc ub = at; DGND aN r R2> s = > RS < Ad>O5 s > as /M) zn yt (16) -VEE 5 g 10, & H12)4(11)(13 Figure 6. Using the AD660 with the AD688 High Precision +10 V Reference REV. A DIGITAL-TO-ANALOG CONVERTERS 3-49AD660 OUTPUT SETTLING AND GLITCH The AD660s output buffer amplifier typically settles to within 0.0008% FS (1/2 LSB) of its final value in 8 ps for a full-scale step. Figures 7a and 7b show settling for a full-scale and an LSB step, respectively, with a 2 kO, 1000 pF load applied. The guaranteed maximum settling time at +25C for a full-scale step is 13 ys with this load. The typical settling time for a 1 LSB step is 2.5 ps. The digital-to-analog glitch impulse is specified as 15 nV-s typi- cal. Figure 7c shows the typical glitch impulse characteristic at the code 011... 111 to 100. . . 000 transition when loading the second rank register from the first rank register. uv 233 88 & 0 10 20 ys a. ~10 Vto +10 V Full-Scale Step Settling b. LSB Step Settling c. D-to-A Glitch Impulse Figure 7. Output Characteristics 3-50 DIGITAL-TO-ANALOG CONVERTERS DIGITAL CIRCUIT DETAILS The AD660 has several dual-use pins which allow flexible operation while maintaining the lowest possible pin count and consequently the smallest package size. The user should, there- fore, pay careful attention to the following information when applying the AD660. Data can be loaded into the AD660 in serial or byte mode as described below. Serial Mode Operation is enabled by bringing SER (Pin 17) low. This changes the function of DBO (Pin 12) to that of the serial input pin, SIN. It also changes the function of DB} (Pin 11) to a control input that tells the AD660 whether the serial data is going to be loaded MSB or LSB first. In serial mode HBE and LBE are effectively disabled except for LBEs dual function which is to control whether the user wishes to have the asynchronous clear function go to unipolar or bipo- lar zero. (A low on LBE, when CLR is strobed, sends the DAC output to unipolar zero, a high to bipolar zero.) The AD660 does not care about the status of HBE when in serial mode. Data is clocked into the input register on the rising edge of CS as shown in Figure 1b. The data is then resident in the first rank latch and can be loaded into the DAC latch by taking LDAC high. This will cause the DAC to change to the appro- priate output value. It should be noted that the clear function clears the DAC latch but does not clear the first rank latch. Therefore, the data that was previously resident in the first rank latch can be reloaded simply by bringing LDAC high after the event that necessitated CLR to be strobed has ended. Alternatively, new data can be loaded into the first rank latch if desired. The serial out pin (SOUT) can be used to daisy chain several DACs together in multi-DAC applications to minimize the num- ber of isolators being used to cross an intrinsic safety barrier. The first rank latch simply acts like a 16-bit shift register, and repeated strobing of CS will shift the data out through SOUT and into the next DAC. Each DAC in the chain will require its own LDAC signal unless all of the DACs are to be updated simultaneously. Byte Mode Operation is enabled simply by keeping SER high, which configures DBODB7 as data inputs. In this mode HBE and LBE are used to identify the data as either the high byte or low byte of the 16-bit input word. (The user can load the data, in any order, into the first rank latch.) As in the serial mode case, the status of LBE, when CLR is strobed determines whether the AD660 clears to unipolar or bipolar zero. There- fore, when in byte mode, the user must take care to set LBE to the desired status before strobing CLR. (In serial mode the user can simply hardware CBE to the desired state.) NOTE: CS is edge triggered. HBE, LBE and LDAC are level triggered. REV. AAD660 TO MC68HC11 (SPI BUS) INTERFACE The AD660 interface to the Motorola SPI (serial peripheral interface) is shown in Figure 8. The MOSI, SCK, and SS pins of the HC11 are respectively connected to the BITO, CS and LDAC pins of the AD660. The SER pin of the AD660 is tied low causing the first rank latch to be transparent. The majority of the interfacing issues are taken care of in the software initial- ization. A typical routine such as the one shown below begins by initializing the state of the various SPI data and control registers. The most significant data byte (MSBY) is then retrieved from memory and processed by the SENDAT subroutine. The SS pin is driven low by indexing into the PORTD data register and clear Bit 5. This causes the 2nd rank latch of the AD660 to become transparent. The MSBY is then set to the SPI data reg- ister where it is automatically transferred to the AD660. The HC11 generates the requisite 8 clock pulses with data valid on the rising edges. After the most significant byte is transmit- ted, the least significant byte (LSBY) is loaded from memory and transmitted in a similar fashion. To complete the transfer, the LDAC pin is driven high latching the complete 16-bit word into the AD660. INIT LDAA #2F 38S = 1; SCK = 0; MOSI = 1 STAA PORTD ;SEND TO SPI OUTPUTS LDAA #$38 388, SCK,MOSI = OUTPUTS STAA DDRD ;SEND DATA DIRECTION INFO LDAA #$50 ;DABL INTRPTS,SPI IS MASTER & ON STAA SPCR ;CPOL=0, CPHA = 0,1MHZ BAUD RATE NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE JMP NEXTPT ;INFINITE LOOP SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS BCLR $08,Y,$20 ;DRIVE SS (LDAC) LOW STAA SPDR 3SEND MS-BYTE TO SPI DATA REG WAITL LDAA SPSR ;CHECK STATUS OF SPIE BPL WAITI ;POLL FOR END OF X-MISSION LDAA LSBY ;GET LOW 8 BITS FROM MEMORY STAA SPDR ;SEND LS-BYTE TO SPI DATA REG WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE BPL WAIT2 ;POLL FOR END OF X-MISSION BSET $08,Y,$20 ;DRIV SS HIGH TO LATCH DATA RTS Figure 8. AD660 to 68HC11 (SPI) Interface AD660 TO MICROWIRE INTERFACE The flexible serial interface of the AD660 is also compatible with the National Semiconductor MICROWIRE interface. The MICROWIRE interface is used on microcontrollers such as the COP400 and COP800 series of processors. A generic inter- face to the MICROWIRE interface is shown in Figure 9. The G1, SK, And SO pins of the MICROWIRE interface are respec- tively connected to the LDAC, CS and BITO pins of the AD660. MICROWIRE is a registered trademark of National Semiconductor. REV. A Microprocessor Interface Section AD660 MICROWIRE~ Figure 9. AD660 to MICROWIRE Interface AD660 TO ADSP-210x FAMILY INTERFACE The serial mode of the AD660 minimizes the number of control and data lines required to interface to digital signal processors (DSPs) such as the ADSP-210x family. The application in Fig- ure 10 shows the interface between an ADSP-2101 and the AD660. Both the TFS pin and the DT pins of the ADSP-2101 should be connected to the SER and BITO pins of the AD660, respectively. An inverter is required between the SCLK output and the CS input of the AD660 in order to assure that data transmitted to the BITO pin is valid on the rising edge of CS. The serial port (SPORT) of the DSP should be configured for alternate framing mode so that TFS complies with the word- length framing requirement of SER. Note that the INVTFS bit in the SPORT control register should be set to invert the TFS signal so that SER is the correct polarity. The LDAC signal, which must meet the minimum hold specification of t,;, is eas- ily generated by delaying the rising edge of SER with a 74HC74 flip-flop. The CS signal clocks the flip-flop resulting in a delay of approximately one C clock cycle. In applications such as waveform generation, accurate timing of the output samples is important to avoid noise that would be induced by jitter on the LDAC signal. In this example, the ADSP-2101 is set up to use the internal timer to interrupt the processor at the precise and desired sample rate. When the timer interrupt occurs, the processorss 16-bit data word is writ- ten to the transmit register (TXn). This causes the DSP to auto- matically generate the TFS signal and begin transmission of the data. ADSP-210x 7aHC7T4 Figure 10. AD660 to ADSP-210x Interface AD660 TO Z80 INTERFACE Figure 11 shows a Zilog Z-80 8-bit microprocessor connected to the AD660 using the byte mode interface. The double-buffered capability of the AD660 allows the microprocessor to indepen- dently write to the low and high byte registers, and update the DAC output. Processor speeds up to 6 MHz on Z-80B require no extra wait states to interface with the AD660 using a 74ALS138 as the address decoder. DIGITAL-TO-ANALOG CONVERTERS 3-51AD660 Applications Information The address decoder analyzes the input-output address produced by the processor to select the function to be performed by the AD660, qualified by the coincidence of the Input-Output Request (IORQ*) and Write (WR*) pins. The least significant address bit (AO) determines if the low or high byte register of the AD660 is active. More significant address bits select between input register loading, DAC output update, and unipo- lar or bipolar clear. A typical Z-80 software routine begins by writing the low byte of the desired 16-bit DAC data to address 0, followed by the high byte to address 1. The DAC output is then updated by activating LDAC with a write to address 2 (or 3). A clear to unipolar zero occurs on a write to address 4, and a clear to bipo- lar zero is performed by a write to address 5. The actual data written to addresses 2 through 5 is irrelevant. The decoder can easily be expanded to control as many AD660s as required. aL _# ADDAESS = CODE OBO-DB7 SER Vi. - 2 cia iona } 2 _. _ vi > LDAC AD660 wR [}-j Et Yo cs AI-A15 HBE LBE DGN 780 BE LBE DGND > a Figure 11. Connections for 8-Bit Bus Interface NOISE In high resolution systems, noise is often the limiting factor. A 16-bit DAC with a 10 volt span has an LSB size of 153 wV (96 dB). Therefore, the noise floor must remain below this level in the frequency range of interest. The AD660s noise spectral density is shown in Figures 12 and 13. Figure 12 shows the DAC output noise voltage spectral density for a 20 V span excluding the reference. This figure shows the 1/f corner frequency at 100 Hz and the wideband noise to be below 120 nV/\/Hz. Figure 13 shows the reference noise voltage spec- tral density. This figure shows the reference wideband noise to be below 125 nV/\/Hz. 1000 NOISE VOLTAGE - nv/7 Hz 1 10 100 1k 10k 100k = 1M 10M FREQUENCY ~ Hz Figure 12. DAC Output Noise Voltage Spectral Density 3-52 DIGITAL-TO-ANALOG CONVERTERS NOISE VOLTAGE - nv/ Hz 1 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 13. Reference Noise Voltage Spectral Density BOARD LAYOUT Designing with high resolution data converters requires careful attention to board layout. Trace impedance is the first issue. A 306 A current through a 0.5 2 trace will develop a voltage drop of 153 wV, which is 1 LSB at the 16-bit level for a 10 V full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital sig- nals. Finally, power supplies need to be decoupled in order to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recom- mended to provide low impedance signal paths. Separate analog and digital ground planes should also be used, with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. One feature that the AD660 incorporates to help the user layout is that the analog pins (Vcc, Veg, REF OUT, REF IN, SPAN/ BIP OFFSET, Voy and AGND) are adjacent to help isolate analog signals from digital signals. SUPPLY DECOUPLING The AD660 power supplies should be well filtered, well regu- lated, and free from high frequency noise. Switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout prox- imity between ail power supply pins and ground. A 10 wF tan- talum capacitor in parallel with a 0.1 ,.F ceramic capacitor provides adequate decoupling. V., and Vgz should be bypassed to analog ground, while V,, should be decoupled to digital ground. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD660, associated analog circuitry and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD660 will isolate large switching ground cur- rents. For these reasons, the use of wire wrap circuit construc- tion is not recommended; careful printed circuit construction is preferred. REV. AGROUNDING The AD660 has two pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the high quality ground reference point for the device. Any exter- nal loads on the output of the AD660 should be returned to ana- log ground. If an external reference is used, this should also be returned to the analog ground. ' If a single AD660 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and REV. A AD660 the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD660. If multiple AD660s are used or the AD660 shares ana- log supplies with other components, connect the analog and dig- ital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground. DIGITAL-TO-ANALOG CONVERTERS 3-53