NCP1589MNTZG - ON Semiconductor

© Semiconductor Components Industries, LLC, 2008

January, 2008 - Rev. 4

1Publication Order Number:

NCP1588/D

NCP1588, NCP1589

Low Voltage Synchronous

Buck Controller

The NCP158x is a low cost PWM controller designed to operate

from a 5 V or 12 V supply. This device is capable of producing an

output voltage as low as 0.8 V. This device is capable of converting

voltage from as low as 2.5 V. This 10-pin device provides an optimal

level of integration to reduce size and cost of the power supply.

Features include a 1.5 A gate driver design and an internally set

300kHz oscillator. In addition to the 1.5 A gate drive capability, other

efficiency enhancing features of the gate driver include adaptive

non-overlap circuitry. The NCP158x also incorporates an externally

compensated error amplifier. Protection features include

programmable short circuit protection and undervoltage lockout

(UVLO).

Features

•VCC Range from 4.5 to 13.2 V

•300 kHz Internal Oscillator

•Boost Pin Operates to 26.4 V

•Voltage Mode PWM Control

•Precision 0.8 V Internal Reference

•Adjustable Output Voltage

•Internal 1.5 A Gate Drivers

•80% Max Duty Cycle

•Input Under Voltage Lockout

•Programmable Current Limit

•This is a Pb-Free Device

Applications

•Graphics Cards

•Desktop Computers

•Servers / Networking

•DSP & FPGA Power Supply

•DC-DC Regulator Modules

DFN10

CASE 485C

MARKING DIAGRAMS

PIN CONNECTIONS

158x = Specific Device Code

x = 8 or 9

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb-Free Device

BOOT 10 PGOOD

9 VOS

8FB

7 COMP/EN

(Top View)

Device Package Shipping†

ORDERING INFORMATION

NCP1588MTR2G DFN10

(Pb-Free)

3000/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

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GND 6VCC

(Note: Microdot may be in either location)

158x

ALYWG

NCP1589MNTZG DFN10

(Pb-Free)

3000/Tape & Reel

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Figure 1. Typical Application Diagram

BOOT

VCC

GND

VOS

PGOOD

VIN = 2.5 V - 13.2 VVCC = 4.5 V - 13.2 V

0.1mF

4.7nF

2x1800mF

2.2

1mH

1500mF

1.02k

3.878kW

0.014mF

1.02k

74.2W

4.12kW

0.007mF

17.08kW

0.0015mF

1mF

COMP/EN

ROCSET

NTD4806 NTD4809

3x22mF

1500mF

2x0.22mF

VBST = 4.5 V - 15 V

GND

VOUT

1.65 V

R9 R10

Figure 2. Detailed Block Diagram

POR

UVLO

PWM

OUT

LATCH

BOOT

GND

CLOCK

RAMP

OSC

VOCP

FAULT

SOFT

START

VOS PGOOD

MONITOR

OV and UV

PGOOD

0.8 V

(Vref)

0.8 V

(Vref)

COMP/EN

-Q

-VCC

2 V

VCC

±10% of Vref

±25% of Vref

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PIN FUNCTION DESCRIPTION

Pin No. Symbol Description

1 BOOT Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired

input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (CBOOT) between this pin and

the LX pin. Typical values for CBOOT range from 0.1 mF to 1 mF. Ensure that CBOOT is placed near the IC.

2 LX Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top

MOSFET.

3 UG Top gate MOSFET driver pin. Connect this pin to the gate of the top N-channel MOSFET.

4 LG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-channel MOSFET.

5 GND IC ground reference. All control circuits are referenced to this pin.

6 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor

to GND. Ensure that this decoupling capacitor is placed near the IC.

7 COMP/EN Compensation Pin. This is the output of the error amplifier (EA) and the non-inverting input of the PWM com‐

parator. Use this pin in conjunction with the FB pin to compensate the voltage-control feedback loop. Pull this

pin low for disable.

8 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com‐

pensate the voltage-control feedback loop. Connect this pin to the output resistor divider (if used) or directly

to Vout.

9 VOS Offset voltage pin from Vout.

10 PGOOD Power Good output. Open drain type output that is flagged low if ±10% of Vout.

ABSOLUTE MAXIMUM RATINGS

Pin Name Symbol VMAX VMIN

Main Supply Voltage Input VCC 15 V -0.3 V

Bootstrap Supply Voltage Input BOOT 30 V wrt/GND

38-40 V < 100 ns

15 V wrt/LX

-0.3 V

Switching Node (Bootstrap Supply Return) LX 25 V

30 V for < 100 ns -5 V

High-Side Driver Output (Top Gate) UG 30 V wrt/GND

15 V wrt/LX

40 V for < 100 ns

-0.3 V wrt/LX

Low-Side Driver Output (Bottom Gate) LG VCC + 0.3 V -0.3 V

-2 V < 100 ns

Feedback, VOS FB, VOS 3.6 V -0.3 V

COMP/EN COMP/EN 3.6 V -0.3 V

PGOOD PGOOD 7 V -0.3 V

MAXIMUM RATINGS

Rating Symbol Value Unit

Thermal Resistance, Junction-to-Ambient RqJA 165 °C/W

Thermal Resistance, Junction-to-Case RqJC 45 °C/W

NCP1588 Operating Junction Temperature Range TJ0 to 150 °C

NCP1588 Operating Ambient Temperature Range TA-40 to 85 °C

Storage Temperature Range Tstg -55 to +150 °C

Moisture Sensitivity Level MSL 3 -

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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ELECTRICAL CHARACTERISTICS (-40°C < TA < 85°C, 0°C < TJ < 125°C; 4.5 V < VCC < 13.2 V, 4.5 V < BOOT < 26.4 V,

CUG = CLG = 1.0 nF (REF:NTD30N02), for min/max values unless otherwise noted.)

Characteristic Conditions Min Typ Max Unit

Input Voltage Range 4.5 13.2 V

Boost Voltage Range 13.2 V wrt LX 4.5 26.4 V

Supply Current

Quiescent Supply Current VFB = 1.0 V, No Switching, VCC = 13.2 V 1.0 4.0 mA

Boost Quiescent Current VFB = 1.0 V, No Switching 140 mA

Undervoltage Lockout

UVLO Threshold NCP1588

NCP1589

VCC Rising Edge 3.8

3.9

4.0

4.1

UVLO Hysteresis NCP1588

NCP1589

0.37

0.2

Switching Regulator

VFB Feedback Voltage NCP1588

NCP1589 (FB Tied to Comp. Measure FB Pin.)

0.792

0.7936

0.8

0.808

0.8064

Oscillator Frequency 270 300 330 kHz

Ramp-Amplitude Voltage 1.1 V

Minimum Duty Cycle 0 %

Maximum Duty Cycle 70 75 80 %

LG Minimum on Time 500 ns

Error Amplifier

Open Loop DC Gain (Note 1) 70 80 dB

Output Source Current

Output Sink Current

Vfb < 0.8 V

Vfb > 0.8 V

2.0

Input Offset Voltage (Note 1) -2.0 0 2.0 mV

Input Bias Current 0.1 1.0 mA

Unity Gain Bandwidth (Note 1) 15 Mhz

Disable Threshold NCP1588

NCP1589

0.3

0.6 0.8

0.5 V

Output Source Current During Disable 100 mA

Gate Drivers

Upper Gate Source VCC = 5 V, VUG - VLX = 2.5 V 1.5 A

Upper Gate Sink 1.4 W

Lower Gate Source 1.5 A

Lower Gate Sink VCC = 12 V 1.0 W

UG Falling to LG Rising Delay VCC = 12 V, UG-LX < 2.0 V, LG > 2.0 V 30 90 ns

LG Falling to UG Rising Delay VCC = 12 V, LG < 2.0 V, UG > 2.0 V 30 60 ns

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ELECTRICAL CHARACTERISTICS (-40°C < TA < 85°C, 0°C < TJ < 125°C; 4.5 V < VCC < 13.2 V, 4.5 V < BOOT < 26.4 V,

CUG = CLG = 1.0 nF (REF:NTD30N02), for min/max values unless otherwise noted.)

Characteristic UnitMaxTypMinConditions

Soft-Start

Soft-Start time 3.0 7.0 ms

Power Good

Output Saturation Voltage IPG = 4 mA, VCC = 12 Vdc 0.4 V

OVP Threshold to Part Disable 1.0 V

UVP Threshold to Part Disable 0.6 V

OVP Threshold to PGOOD Output Low 0.88 V

UVP Threshold to PGOOD Output Low 0.72 V

Overcurrent Protection

OC Current Source Sourced from LG pin, before SS 10 mA

1. Guaranteed by design but not tested in production.

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TYPICAL CHARACTERISTICS

305

303

301

299

297

020406080

TJ, JUNCTION TEMPERATURE (°C)

fSW, FREQUENCY (kHz)

808

-40 25 85

TJ, JUNCTION TEMPERATURE (°C)

Vref REFERENCE (mV)

806

804

802

800

798

796

794

792

Figure 3. Oscillator Frequency (fSW) vs. Temperature Figure 4. Reference Voltage (Vref) vs.

Temperature

295

VCC = 5.0 V

VCC = 12 V

-556

-558

-560

-562

-564

-566

-568

-570020406080

TJ, JUNCTION TEMPERATURE (°C)

OCP THRESHOLD (mV)

0 20 406080

TJ, JUNCTION TEMPERATURE (°C)

ICC (mA)

4.0

3.5

3.0

2.5

1.0

Figure 5. ICC vs. Temperature Figure 6. OCP Threshold with 55k Rset vs.

Temperature

1.5

2.0

Series 1

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APPLICATIONS INFORMATION

Overcurrent Protection (OCP)

The low-side RDSon sense is implemented by comparing

the voltage at the LX, at the end of LG on time to an

internally generated fixed voltage. If the phase voltage is

lower than OCP trip voltage, an overcurrent condition

occurs and a counter is initiated.

When the counter completes after two clock cycles, the

PWM logic and both HS-FET and LS-FET are turned off.

Power has to be recycled to exit out of the overcurrent fault.

The minimum turn-on time of the LS-FET is set to be

500 ns.

NCP158x allows to easily program an Overcurrent

Threshold ranging from 50 mV to 550 mV, simply by

adding a resistor (ROCSET) between LG and GND. During

a short period of time following VCC rising over UVLO

threshold, an internal 10 mA current (IOCSET, trimmed to

$5%) is sourced from LG pin, determining a voltage drop

across ROCSET. This voltage drop will be sampled and

internally held by the device as OverCurrent Threshold. The

OC setting procedure overall time length is about 4.2 ms.

Connecting a ROCSET resistor between LG and GND, the

programmed threshold will be:

IOCth +

IOCSET @ROCSET

RDS(on)

RSET values range from 5 kW to 55 kW. In case ROCSET

is not connected, the device switches the OCP threshold to

a fixed 640 mV value: an internal safety clamp on BG is

triggered as soon as LG voltage reaches 700 mV, enabling

the 640 mV fixed threshold and ending OC setting phase.

The current trip threshold tolerance is ±25 mV. The accuracy

of the set point is best at the highest set point. The accuracy

will decrease as the set point decreases.

Internal Soft –Start

The NCP158x features an internal soft-start function,

which reduces the inrush current and overshoot of the output

voltage. Figure 7. shows a typical soft-start sequence.

Soft-Start is achieved by ramping the internal reference

using the oscillator clock (64 steps from 0 V to 0.8 V of

Vref). The order of startup sequence is as follows: UVLO →

OCP programming → Comp voltage reach the lower end of

the Ramp voltage (1.45 V). The typical soft-start time is

4.2 ms. The internal soft-start is held low when the part is

in UVLO or Disable mode.

Power Good

Power Good is an open drain and active high output. This

output can be pulled up high to the appropriate level with an

external resistor. It monitors the output voltage through the

VOS pin. The PGOOD is flagged low for ±10% of Vout for

OV/UV trip points respectively. The separate VOS input is

not slowed down by the compensation on the VFB pin. The

PGOOD output can deliver a max of 4 mA sink current at

0.4 V when de-asserted. The PGOOD pin is held low during

soft-start. Once soft-start is complete PGOOD goes high if

there are no faults without any delays associated to it.

Undervoltage Protection

If the voltage at VOS pin drops below UV threshold, the

device turns off both HS and LS MOSFETs, latching the

condition. This requires a POR to recover.

Overvoltage Protection

If the voltage at VOS pin rises over OV threshold (1V typ),

overvoltage protection turns off UG MOSFET and turns on

LG MOSFET. The LG MOSFET will be turned off as soon

as VOS goes below Vref/2 (0.4 V). The condition is latched,

and requires POR to recover. The device still controls the LG

MOSFET and can switch it on whenever VOS rises above

1.0 V.

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Figure 7. Typical Startup Sequence

VCC

COMP

VOUT

Vfb

Monitor

UVLO

Fault

-0.7 V

1.45 V

700 mV

50 mV

OCP

Program‐

mable

0.8 V

NORMALSSUVLOPOR

4.3 V

3.7 V

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Figure 8. Typical Power Good Function

0.88V

0.4V

1.0V

0.88V

0.8V

0.72V

0.8V

0.6V

VOS

Overvoltage Undervoltage

Feedback and Compensation

The NCP158x allows the output voltage to be adjusted

from 0.8 V to 5.0 V via an external resistor divider network.

The controller will try to maintain 0.8 V at feedback pin.

Thus, if a resistor divider circuit was placed across the

feedback pin to VOUT, the controller will regulate the output

voltage proportional to the resistor divider network in order

to maintain 0.8 V at the FB pin. The same formula applies

to the VOS pin and the controller will maintain 0.8 V at the

VOS pin.

VOUT

Figure 9.

The relationship between the resistor divider network

above and the output voltage is shown in the following

equation:

R4+R1 ǒVREF

VOUT *VREFǓ

The same formula can be applied to the feedback resistors

at VOS.

R9+R10 ǒVREF

VOUT *VREFǓ

Design Example

Voltage Mode Control Loop with TYPE III

Compensation

Converter Parameters:

Input Voltage: VIN = 5 V

Output Voltage: VOUT = 1.65 V

Switching Frequency: 300 kHz

Total Output Capacitance: COUT = 3600 mF

Total ESR: ESR = 6 mW

Output Inductance: LOUT: 1 mH

Ramp Amplitude: VRAMP = 1.1 V

Figure 10.

C3R3

C2R2

VOUT VCOMP

Vref

E/A

a.. Set a target for the close loop bandwidth at 1/6th of

the switching frequency.

Fcross_over :+50kHz

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b.. Output Filter Double Pole Frequency

Flc +2.653kHz

Flc :+1

2@p@LOUT @COUT

c.. ESR Zero Frequency:

FESR +7.368kHz

FESR :+1

2@p@COUT @CESR

Step 1: Set a value for R1 between 2 kW and 5 kW

R1 :+4.12kW

Step 2: Pick compensation DC gain (R2/R1) for desired

close loop bandwidth.

VRAMP :+1.1V

R2 :+R1 @ǒVRAMP

VIN Ǔ@ǒFcross_over

Flc Ǔ

R2 +17.085kW

Step 3: Place 1st zero at half the output filter double pole

frequency.

C2 :+

2@LOUT @COUT

C2 +7.024 10-3mF

Step 4: Place 1st pole at ESR zero frequency.

C1 :+C2

C2 @R2 @2@p@FESR *1

C1 +1.542 10-3mF

Step 5: Place 2nd zero at the output filter double pole

frequency.

R3 :+R1

FSW

2@Flc *1

R3 +74.169W

Step 6: Place 2nd pole at half the switching frequency.

C3 :+1

ǒp@R3 @FSWǓ

C3 +0.014mF

Step 7: R4 is sized to maintain the feedback voltage to

Vref = 0.8 V.

R4 :+

VREF @R1

VOUT *VREF

R4 +3.878kW

The Component values for Type III Compensation are:

R1 = 4.12 kW

R2 = 17.085 kW

R3 = 74.169 W

R4 = 3.878 kW

C1 = 0.0015 mF

C2 = 0.007 mF

C3 = 0.014 mF

NOTE: Recommend to change values to industry

standard component values.

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PACKAGE DIMENSIONS

DFN10, 3x3, 0.5P

CASE 485C-01

ISSUE A

10X

SEATING

PLANE

0.15 C

10 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. TERMINAL b MAY HAVE MOLD COMPOUND

MATERIAL ALONG SIDE EDGE. MOLD

FLASHING MAY NOT EXCEED 30 MICRONS

ONTO BOTTOM SURFACE OF TERMINAL b.

6. DETAILS A AND B SHOW OPTIONAL VIEWS

FOR END OF TERMINAL LEAD AT EDGE OF

PACKAGE.

ÇÇÇ

0.15 C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN 1

REFERENCE

0.10 C

0.08 C

(A3)

10X

0.10 C

0.05 C

A B

NOTE 3

10X

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D3.00 BSC

D2 2.45 2.55

E3.00 BSC

E2 1.75 1.85

e0.50 BSC

L0.35 0.45

L1 0.00 0.03

DETAIL A

K0.19 TYP

DETAIL A

Bottom View

(Optional)

ÉÉ

DETAIL B

Side View

(Optional)

EDGE OF PACKAGE

MOLD CMPD

EXPOSED Cu

DETAIL B

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.1746

2.6016

1.8508

0.5000 PITCH

0.5651

10X

3.3048

0.3008

10X

DIMENSIONS: MILLIMETERS

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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PUBLICATION ORDERING INFORMATION

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Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81-3-5773-3850

NCP1588/D

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