LTC3703-5
1
37035fa
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
■
High Voltage Operation: Up to 60V
■
Large 1
Ω
Gate Drivers (with 5V Supply)
■
No Current Sense Resistor Required
■
Step-Up or Step-Down DC/DC Converter
■
Dual N-Channel MOSFET Synchronous Drive
■
Excellent Line and Load Transient Response
■
Programmable Constant Frequency: 100kHz to
600kHz
■
±1% Reference Accuracy
■
Synchronizable up to 600kHz
■
Selectable Pulse Skip Mode Operation
■
Low Shutdown Current: 25µA Typ
■
Programmable Current Limit
■
Undervoltage Lockout
■
Programmable Soft-Start
■
16-Pin Narrow SSOP and 28-Pin SSOP Packages
The LTC
®
3703-5 is a synchronous step-down switching
regulator controller that can directly step-down voltages
from up to 60V input, making it ideal for telecom and au-
tomotive applications. The LTC3703-5 drives external logic
level N-channel MOSFETs using a constant frequency (up
to 600kHz), voltage mode architecture.
A precise internal reference provides 1% DC accuracy. A
high bandwidth error amplifier and patented* line feed
forward compensation provide very fast line and load
transient response. Strong 1Ω gate drivers allow the
LTC3703-5 to drive multiple MOSFETs for higher current
applications. The operating frequency is user program-
mable from 100kHz to 600kHz and can also be synchro-
nized to an external clock for noise-sensitive applications.
Current limit is programmable with an external resistor
and utilizes the voltage drop across the synchronous
MOSFET to eliminate the need for a current sense resistor.
For applications requiring up to 100V operation, refer to
the LTC3703 data sheet.
60V Synchronous
Switching Regulator Controller
Efficiency vs Load Current
High Efficiency High Voltage Step-Down Converter
LTC3703-5
MODE/SYNC
FSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
22µF
×2
1000pF
2200pF
10k
100Ω113k
1%
21.5k
1% 10Ω
12k
30k
0.1µF
VIN
6V TO 60V
8µH
D1
MBR1100
VOUT
5V
5A
270µF
16V
MMDL770T1
VCC
5V
0.1µF
37035 TA04
10µF
1µF
+
+
+
Si7850DP
Si7850DP
22µF
470pF
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
95
90
85
80 4
37053 TA04b
1235
VIN = 12V
VIN = 42V
VIN = 24V
■
48V Telecom and Base Station Power Supplies
■
Networking Equipment, Servers
■
Automotive and Industrial Control
PARAMETER LTC3703-5 LTC3703
Maximum V
IN
60V 100V
MOSFET Gate Drive 4.5V to 15V 9.3V to 15V
V
CC
UV
+
3.7V 8.7V
V
CC
UV
–
3.1V 6.2V
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*U.S. Patent Numbers: 5408150, 5055767, 6677210, 5847554, 5481178, 6304066, 6580258;
Others Pending.
LTC3703-5
2
37035fa
Supply Voltages
V
CC
, DRV
CC
.......................................... –0.3V to 15V
(DRV
CC
– BGRTN), (BOOST – SW) ...... –0.3V to 15V
BOOST (Continuous) ............................ –0.3V to 85V
BOOST (400ms) ................................... –0.3V to 95V
BGRTN ...................................................... –5V to 0V
V
IN
Voltage (Continuous).......................... –0.3V to 70V
V
IN
Voltage (400ms) ................................. –0.3V to 80V
SW Voltage (Continuous) ............................ –1V to 70V
SW Voltage (400ms) ................................... –1V to 80V
Run/SS Voltage .......................................... –0.3V to 5V
ABSOLUTE AXI U RATI GS
W
WW
U
(Note 1)
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 5V, VMODE/SYNC = VINV = VSW =
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
, DRV
CC
V
CC
, DRV
CC
Supply Voltage ●4.1 15 V
V
IN
V
IN
Pin Voltage ●60 V
I
CC
V
CC
Supply Current V
FB
= 0V ●1.7 2.5 mA
RUN/SS = 0V 25 40 µA
I
DRVCC
DRV
CC
Supply Current (Note 5) 0 5 µA
RUN/SS = 0V 0 5 µA
I
BOOST
BOOST Supply Current (Note 5) ●360 500 µA
RUN/SS = 0V 0 5 µA
MODE/SYNC, INV Voltages....................... –0.3V to 15V
f
SET
, FB, I
MAX
, COMP Voltages ................... –0.3V to 3V
Driver Outputs
TG ................................ SW – 0.3V to BOOST + 0.3V
BG ........................... BGRTN – 0.3V to DRV
CC
+ 0.3V
Peak Output Current <10µs BG,TG ............................ 5A
Operating Temperature Range (Note 2)
LTC3703E-5 ........................................ –40°C to 85°C
LTC3703I-5 ....................................... –40°C to 125°C
Junction Temperature (Notes 3, 7) ....................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
ORDER PART
NUMBER
GN PART
MARKING
T
JMAX
= 125°C, θ
JA
= 110°C/W
37035
3703I5
LTC3703EGN-5
LTC3703IGN-5
PACKAGE/ORDER I FOR ATIO
UUW
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ORDER PART
NUMBER
LTC3703EG-5
LTC3703IG-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BOOST
TG
SW
NC
NC
NC
NC
VCC
DRVCC
BG
NC
NC
NC
BGRTN
VIN
NC
NC
NC
NC
MODE/SYNC
fSET
COMP
FB
IMAX
INV
NC
RUN/SS
GND
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
B00ST
TG
SW
VCC
DRVCC
BG
BGRTN
T
JMAX
= 125°C, θ
JA
= 100°C/W
LTC3703-5
3
37035fa
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3703-5 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3703I-5 is guaranteed over the full
–40°C to 125°C operating junction temperature range.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC3703-5: T
J
= T
A
+ (P
D
• 100 °C/W) G Package
Note 4: The LTC3703-5 is tested in a feedback loop that servos V
FB
to the
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 5V, VMODE/SYNC = VINV = VSW =
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
reference voltage with the COMP pin forced to a voltage between 1V and 2V.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(Q
G
• f
OSC
).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: R
DS(ON)
guaranteed by correlation to wafer level measurement.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
V
FB
Feedback Voltage (Note 4) 0.792 0.800 0.808 V
●0.788 0.812 V
∆V
FB, LINE
Feedback Voltage Line Regulation 5V < V
CC
< 15V (Note 4) ●0.007 0.05 %/V
∆V
FB, LOAD
Feedback Voltage Load Regulation 1V < V
COMP
< 2V (Note 4) ●0.01 0.1 %
V
MODE/SYNC
MODE/SYNC Threshold MODE/SYNC Rising 0.75 0.8 0.87 V
∆V
MODE/SYNC
MODE/SYNC Hysteresis 20 mV
I
MODE/SYNC
MODE/SYNC Current 0 ≤ V
MODE/SYNC
≤ 15V 0 1 µA
V
INV
Invert Threshold 1 1.5 2 V
I
INV
Invert Current 0 ≤ V
INV
≤ 15V 0 1 µA
I
VIN
V
IN
Sense Input Current V
IN
= 60V 80 130 µA
RUN/SS = 0V, V
IN
= 10V 0 1 µA
I
MAX
I
MAX
Source Current V
IMAX
= 0V 10.5 12 13.5 µA
V
OS,
IMAX
V
IMAX
Offset Voltage |V
SW
| – V
IMAX
at I
RUN/SS
= 0µA – 25 10 55 mV
V
RUN/SS
Shutdown Threshold 0.7 0.9 1.2 V
I
RUN/SS
RUN/SS Source Current RUN/SS = 0V 2.3 3.8 5.3 µA
Maximum RUN/SS Sink Current |V
SW
| – V
IMAX
> 100mV 9 17 25 µA
V
UV
Undervoltage Lockout V
CC
Rising ●3.4 3.7 4.1 V
V
CC
Falling ●2.8 3.1 3.4 V
Hysteresis ●0.45 0.65 0.85 V
Oscillator
f
OSC
Oscillator Frequency R
SET
= 25kΩ270 300 330 kHz
f
SYNC
External Sync Frequency Range 100 600 kHz
t
ON, MIN
Minimum On-Time 200 ns
DC
MAX
Maximum Duty Cycle f < 200kHz 89 93 96 %
Driver
I
BG, PEAK
BG Driver Peak Source Current 0.75 1 A
R
BG, SINK
BG Driver Pull-Down R
DS, ON
(Note 8) 1.2 1.8 Ω
I
TG, PEAK
TG Driver Peak Source Current 0.75 1 A
R
TG, SINK
TG Driver Pull-Down R
DS, ON
(Note 8) 1.2 1.8 Ω
Feedback Amplifier
A
VOL
Op Amp DC Open Loop Gain (Note 4) 74 85 dB
f
U
Op Amp Unity Gain Crossover Frequency (Note 6) 25 MHz
I
FB
FB Input Current 0 ≤ V
FB
≤ 3V 0 1 µA
I
COMP
COMP Sink/Source Current ±5±10 mA
LTC3703-5
4
37035fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs Input Voltage Efficiency vs Load Current Load Transient Response
VCC Current vs VCC Voltage VCC Current vs Temperature
VCC Shutdown Current vs VCC
Voltage
VCC Shutdown Current
vs Temperature
Reference Voltage
vs Temperature
Normalized Frequency
vs Temperature
TEMPERATURE (°C)
–60 –40 –20 0 60 100 120 140
20 40 80
TEMPERATURE (°C)
–60 –40 –20 0 60 100 120 140
20 40 80 –60 –40 –20 0 20 40 60 80 140100 120
TEMPERATURE (°C)
NORMALIZED FREQUENCY
37035 G09
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
95
90
85
80 1234
37035 G02
5
V
CC
VOLTAGE (V)
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7.5
37035 G04
2.5 5 10 12.5 15
V
CC
CURRENT (mA)
37035 G05
37035 G03
V
CC
CURRENT (µA)
37035 G07
35
30
25
20
15
10
5
0
REFERENCE VOLTAGE (V)
0.803
0.802
0.801
0.800
0.799
0.798
37035 G08
V
OUT
= 12V
f = 250kHz
PULSE SKIP ENABLED
V
IN
= 42V
V
IN
= 24V
V
OUT
50mV/DIV
AC COUPLED
I
OUT
2A/DIV
V
IN
= 50V
V
OUT
= 12V
1A TO 5A LOAD STEP
50µs/DIV
V
FB
= 0V
V
CC
RISING
COMP = 1.5V
TEMPERATURE (°C)
–60 –40 –20 0
V
CC
CURRENT (mA)
60 120 140100
20 40 80
4
3
2
1
0
V
FB
= 0V
COMP = 1.5V
INPUT VOLTAGE (V)
0
80
EFFICIENCY (%)
85
90
95
100
10 20 30 40
37035 G01
50 60
I
OUT
= 1A
V
OUT
= 5V
f = 250kHz
FORCED CONTINUOUS
I
OUT
= 5A
V
CC
VOLTAGE (V)
0
0
V
CC
CURRENT (µA)
20
40
60
80
4812 16
37035 G06
100
120
2610 14
V
CC
= 5V
TA = 25°C (unless otherwise noted).
LTC3703-5
5
37035fa
PEAK SOURCE CURRENT (A)
1.2
1.1
1.0
0.9
0.8
37035 G10
TEMPERATURE (°C)
R
DS(ON)
(Ω)
37035 G11
DRV
CC
/BOOST VOLTAGE (V)
0 2.5 7.5 10 12.5
PEAK SOURCE CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
05
37035 G12
15
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
V
CC
= 5V
|SW| VOLTAGE (V)
0
25
20
15
10
5
0
–5
–10
0.3 0.5
37035 G17
0.1 0.2 0.4 0.6 0.7
RUN/SS SINK CURRENT (µA)
RUN VOLTAGE (V)
0.5
MAX DUTY CYCLE (%)
100
90
80
70
60
50
40
30
20
10
0
–10 2.5
37035 G18
1.0 1.5 2.0 3.0
I
MAX
= 0.3V
TEMPERATURE (°C)
RUN/SS CURRENT (µA)
15735 G15
6
5
4
3
2
1
0
–60 –20 20 40
–40 0 60 80 100 120 140
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
DRV
CC
/BOOST VOLTAGE (V)
2.5
1.1
1.2
1.3
12.5
37035 G13
1.0
0.9
5 7.5 10 15
0.8
0.7
0.6
R
DS(ON)
(Ω)
GATE CAPACITANCE (nF)
0
RISE/FALL TIME (ns)
100
150
20
37035 G14
50
0510 15
200
RISE TIME
FALL TIME
V
CC
= 5V
V
CC
VOLTAGE (V)
0
0
RUN/SS PULL-UP CURRENT (µA)
1
2
3
4
5
2.5 57.510
37035 G16
12.5 15
V
CC
= 5V V
CC
= 5V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Driver Peak Source Current
vs Temperature
Driver Pull-Down RDS(ON)
vs Temperature
Driver Peak Source Current
vs Supply Voltage
Rise/Fall Time
vs Gate Capacitance
RUN/SS Pull-Up Current
vs Temperature
RUN/SS Pull-Up Current
vs VCC Voltage
RUN/SS Sink Current
vs SW Voltage Max % DC vs RUN/SS Voltage
Driver Pull-Down RDS(ON)
vs Supply Voltage
LTC3703-5
6
37035fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
I
MAX
Current vs Temperature % Duty Cycle vs COMP Voltage
Max % DC vs Frequency and
Temperature
Shutdown Threshold vs
Temperature tON(MIN) vs Temperature
I
MAX
SOURCE CURRENT (µA)
13
12
11
37035 G19
FREQUENCY (kHz)
MAX DUTY CYCLE (%)
37035 G21
100
95
90
85
80
75
70 0 200 400 500100 300 600 700
TEMPERATURE (°C)
SHUTDOWN THRESHOLD (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
37035 G22 37035 G23
t
ON(MIN)
(ns)
200
180
160
140
120
100
80
60
40
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
25°C
–45°C
90°C
125°C
COMP (V)
0.5
DUTY CYCLE (%)
100
80
60
40
20
00.75 1.00 1.25 1.50
37035 G20
1.75 2.00
V
IN
= 10V
V
IN
= 50V
V
IN
= 25V
LTC3703-5
7
37035fa
MODE/SYNC
(Pin 1/Pin 6): Pulse Skip Mode Enable/Sync
Pin. This multifunction pin provides Pulse Skip Mode en-
able/disable control and an external clock input for synchro-
nization of the internal oscillator. Pulling this pin below 0.8V
or to an external logic-level synchronization signal disables
Pulse Skip Mode operation and forces continuous opera-
tion. Pulling the pin above 0.8V enables Pulse Skip Mode
operation. This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor
to regulate a second output voltage.
f
SET
(Pin 2/Pin 7): Frequency Set. A resistor connected to
this pin sets the free running frequency of the internal os-
cillator. See applications section for resistor value selec-
tion details.
COMP (Pin 3/Pin 8): Loop Compensation. This pin is con-
nected directly to the output of the internal error amplifier.
An RC network is used at the COMP pin to compensate the
feedback loop for optimal transient response.
FB (Pin 4/Pin 9): Feedback Input. Connect FB through a
resistor divider network to V
OUT
to set the output voltage.
Also connect the loop compensation network from COMP
to FB.
I
MAX
(Pin 5/Pin 10): Current Limit Set. The I
MAX
pin sets
the current limit comparator threshold. If the voltage drop
across the bottom MOSFET exceeds the magnitude of the
voltage at I
MAX
, the controller goes into current limit. The
I
MAX
pin has an internal 12µA current source, allowing the
current threshold to be set with a single external resistor
to ground. See the Current Limit Programming section for
more information on choosing R
IMAX
.
INV (Pin 6/Pin 11): Top/Bottom Gate Invert. Pulling this pin
above 2V sets the controller to operate in step-up (boost)
mode with the TG output driving the synchronous MOSFET
and the BG output driving the main switch. Below 1V, the
controller will operate in step-down (buck) mode.
RUN/SS (Pin 7/Pin 13): Run/Soft-Start. Pulling RUN/SS be-
low 0.9V will shut down the LTC3703-5, turn off both of the
external MOSFET switches and reduce the quiescent sup-
ply current to 25µA. A capacitor from RUN/SS to ground
will control the turn-on time and rate of rise of the output
voltage at power-up. An internal 4µA current source pull-
up at the RUN/SS pin sets the turn-on time at approximately
750ms/µF.
GND (Pin 8/Pin 14): Ground Pin.
BGRTN (Pin 9/Pin 15): Bottom Gate Return. This pin con-
nects to the source of the pull-down MOSFET in the BG
driver and is normally connected to ground. Connecting a
negative supply to this pin allows the synchronous
MOSFET’s gate to be pulled below ground to help prevent
false turn-on during high dV/dt transitions on the SW node.
See the Applications Information section for more details.
BG (Pin 10/Pin 19): Bottom Gate Drive. The BG pin drives
the gate of the bottom N-channel synchronous switch
MOSFET. This pin swings from BGRTN to DRV
CC
.
DRV
CC
(Pin 11/Pin 20): Driver Power Supply Pin. DRV
CC
provides power to the BG output driver. This pin should be
connected to a voltage high enough to fully turn on the
external MOSFETs, normally 4.5V to 15V for logic level
threshold MOSFETs. DRV
CC
should be bypassed to BGRTN
with a 10µF, low ESR (X5R or better) ceramic capacitor.
V
CC
(Pin 12/Pin 21) :
Main Supply Pin. All internal circuits
except the output drivers are powered from this pin. V
CC
should be connected to a low noise power supply voltage
between 4.5V and 15V and should be bypassed to GND
(Pin 8) with at least a 0.1µF capacitor in close proximity to
the LTC3703-5.
SW (Pin 13/Pin 26): Switch Node Connection to Inductor
and Bootstrap Capacitor. Voltage swing at this pin is from
a Schottky diode (external) voltage drop below ground to
V
IN
.
TG (Pin 14/Pin 27): Top Gate Drive. The TG pin drives the
gate of the top N-channel synchronous switch MOSFET. The
TG driver draws power from the BOOST pin and returns to
the SW pin, providing true floating drive to the top MOSFET.
BOOST (Pin 15/Pin 28): Top Gate Driver Supply. The BOOST
pin supplies power to the floating TG driver. The BOOST pin
should be bypassed to SW with a low ESR (X5R or better)
0.1µF ceramic capacitor. An additional fast recovery Schot-
tky diode from DRV
CC
to BOOST will create a complete float-
ing charge-pumped supply at BOOST.
V
IN
(Pin 16/Pin 1):
Input Voltage Sense Pin. This pin is con-
nected to the high voltage input of the regulator and is used
by the internal feedforward compensation circuitry to im-
prove line regulation. This is not a supply pin.
UU
U
PI FU CTIO S
(GN16/G28)
LTC3703-5
8
37035fa
FU CTIO AL DIAGRA
UU
W
5
1
UVSD OTSD
CHIP
SD
1V
3.2V
4µA
RUN/SS
BANDGAP
SYNC
DETECT
OVER
TEMP V
CC
UVLO
OSC
% DC
LIMIT
DRIVE
LOGIC
+
–
+
–
+
–
+
–
EXT SYNC
FORCED CONTINUOUS
÷
+
+
–
+–+–
+
–
0.8V
MODE/SYNC
3
COMP
4
FB
16
15
14
13
11
10
9
6
12
V
IN
V
CC
(<15V)
INV
PWM
MIN MAX
0.76V 0.84V
±
OVERCURRENT
12µA
50mV
I
MAX
R
MAX
BOOST
TG
SW
DRV
CC
BG
BGRTN
INV
8GND
GN16
OT SD 0.8V
REFERENCE
INTERNAL
3.2V V
CC
UV SD
2
FSET
37035 FD
REVERSE
CURRENT
FB
RSET
5
C
SS
R2 R1
V
CC
C
VCC
D
B
C
B
V
CC
V
IN
M1
M2
C
OUT
V
OUT
L1
INV
±
OPERATIO
U
(Refer to Functional Diagram)
The LTC3703-5 is a constant frequency, voltage mode
controller for DC/DC step-down converters. It is designed
to be used in a synchronous switching architecture with
two external N-channel MOSFETs. Its high operating volt-
age capability allows it to directly step down input voltages
up to 60V without the need for a step-down transformer.
For circuit operation, please refer to the Functional
Diagram of the IC and the circuit on the first page of this
data sheet. The LTC3703-5 uses voltage mode control in
which the duty ratio is controlled directly by the error
amplifier output and thus requires no current sense resis-
tor. The V
FB
pin receives the output voltage feedback and
is compared to the internal 0.8V reference by the error
amplifier, which outputs an error signal at the COMP pin.
LTC3703-5
9
37035fa
OPERATIO
U
(Refer to Functional Diagram)
When the load current increases, it causes a drop in the
feedback voltage relative to the reference. The COMP volt-
age then rises, increasing the duty ratio until the output
feedback voltage again matches the reference voltage. In
normal operation, the top MOSFET is turned on when the
RS latch is set by the on-chip oscillator and is turned off
when the PWM comparator trips and resets the latch. The
PWM comparator trips at the proper duty ratio by compar-
ing the error amplifier output (after being “compensated”
by the line feedforward multiplier) to a sawtooth waveform
generated by the oscillator. When the top MOSFET is turned
off, the bottom MOSFET is turned on until the next cycle
begins or, if Pulse Skip Mode operation is enabled, until
the inductor current reverses as determined by the reverse
current comparator. MAX and MIN comparators ensure
that the output never exceed ±5% of nominal value by
monitoring V
FB
and forcing the output back into regulation
quickly by either keeping the top MOSFET off or forcing
maximum duty cycle. The operation of its other features—
fast transient response, outstanding line regulation, strong
gate drivers, short-circuit protection, and shutdown/
soft-start—are described below.
Fast Transient Response
The LTC3703-5 uses a fast 25MHz op amp as an error am-
plifier. This allows the compensation network to be opti-
mized for better load transient response. The high
bandwidth of the amplifier, along with high switching fre-
quencies and low value inductors, allow very high loop
crossover frequencies. The 800mV internal reference allows
regulated output voltages as low as 800mV without exter-
nal level shifting amplifiers.
Line Feedforward Compensation
The LTC3703-5 achieves outstanding line transient re-
sponse using a patented feedforward correction scheme.
With this circuit the duty cycle is adjusted instantaneously
to changes in input voltage, thereby avoiding unaccept-
able overshoot or undershoot. It has the added advantage
of making the DC loop gain independent of input voltage.
Figure 1 shows how large transient steps at the input have
little effect on the output voltage.
20µs/DIV
VOUT
50mV/DIV
AC COUPLED
VOUT = 12V
ILOAD = 1A
25V TO 60V VIN STEP
VIN
20V/DIV
IL
2A/DIV
37035 F01
Figure 1. Line Transient Performance
Strong Gate Drivers
The LTC3703-5 contains very low impedance drivers
capable of supplying amps of current to slew large MOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
60V floating high side driver drives the top side MOSFET
and a low side driver drives the bottom side MOSFET (see
Figure 2). They can be powered from either a separate DC
supply or a voltage derived from the input or output
voltage (see MOSFET Driver Supplies section). The bot-
tom side driver is supplied directly from the DRV
CC
pin.
The top MOSFET drivers are biased from floating boot-
strap capacitor C
B
, which normally is recharged during
each off cycle through an external diode from DRV
CC
when
the top MOSFET turns off. In Pulse Skip Mode operation,
where it is possible that the bottom MOSFET will be off for
an extended period of time, an internal counter guarantees
that the bottom MOSFET is turned on at least once every
10 cycles for 10% of the period to refresh the bootstrap
capacitor. An undervoltage lockout keeps the LTC3703-5
shut down unless this voltage is above 4.1V.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-thru.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is holding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-thru between the top side and bottom side
LTC3703-5
10
37035fa
OPERATIO
U
MOSFETs can occur. To prevent this from occuring, the
bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V supply
is used on BGRTN, the switch node dV/dt could pull the
gate up 2V before the V
GS
of the bottom MOSFET has more
than 0V across it.
cycle control set to 0%. As C
SS
continues to charge, the
duty cycle is gradually increased, allowing the output
voltage to rise. This soft-start scheme smoothly ramps the
output voltage to its regulated value, with no overshoot.
The RUN/SS voltage will continue ramping until it reaches
an internal 4V clamp. Then the MIN feedback comparator
is enabled and the LTC3703-5 is in full operation. When the
RUN/SS is low, the supply current is reduced to 25µA.
CURRENT
LIMIT
NORMAL OPERATION
START-UP
0V
4V
3V
1.4V
1V
0V
POWER
DOWN MODE
MINIMUM
DUTY CYCLE
OUTPUT VOLTAGE
IN REGULATION
LTC3703-5
ENABLE
MIN COMPARATOR ENABLED
37035 F03
RUN/SS SOFT-STARTS
OUTPUT VOLTAGE AND
INDUCTOR CURRENT
SHUTDOWN
V
OUT
V
RUN/SS
(Refer to Functional Diagram)
BOOST
TG
SW
BG
BGRTN
DRV
CC
DRV
CC
LTC3703-5
M1
M2
+
+
V
IN
C
IN
V
OUT
C
OUT
D
B
C
B
L
37035 F02
0V TO –5V
Figure 3. Soft-Start Operation in Start Up and Current Limit
Figure 2. Floating TG Driver Supply and Negative BG Return
Constant Frequency
The internal oscillator can be programmed with an exter-
nal resistor connected from f
SET
to ground to run between
100kHz and 600kHz, thereby optimizing component size,
efficiency, and noise for the specific application. The
internal oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin and can lock to a
frequency in the 100kHz to 600kHz range. When locked to
an external clock, Pulse Skip Mode operation is automati-
cally disabled. Constant frequency operation brings with it
a number of benefits: Inductor and capacitor values can be
chosen for a precise operating frequency and the feedback
loop can be similarly tightly specified. Noise generated by
the circuit will always be at known frequencies.
Subharmonic oscillation and slope compensation, com-
mon headaches with constant frequency current mode
switchers, are absent in voltage mode designs like the
LTC3703-5.
Shutdown/Soft-Start
The main control loop is shut down by pulling RUN/SS pin
low. Releasing RUN/SS allows an internal 4µA current
source to charge the soft-start capacitor C
SS
. When C
SS
reaches 1V, the main control loop is enabled with the duty
Current Limit
The LTC3703-5 includes an onboard current limit circuit
that limits the maximum output current to a user-pro-
grammed level. It works by sensing the voltage drop across
the bottom MOSFET and comparing that voltage to a user-
programmed voltage at the I
MAX
pin. Since the bottom
MOSFET looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowing in it. In a buck converter, the average current in the
inductor is equal to the output current. This current also
flows through the bottom MOSFET during its on-time.
Thus by watching the drain-to-source voltage when the
bottom MOSFET is on, the LTC3703-5 can monitor the
output current. The LTC3703-5 senses this voltage and
inverts it to allow it to compare the sensed voltage (which
becomes more negative as peak current increases) with a
positive voltage at the I
MAX
pin. The I
MAX
pin includes a
12µA pull-up, enabling the user to set the voltage at I
MAX
with a single resistor (R
IMAX
) to ground. See the Current
Limit Programming section for R
IMAX
selection.
LTC3703-5
11
37035fa
For maximum protection, the LTC3703-5 current limit
consists of a steady-state limit circuit and an instanta-
neous limit circuit. The steady-state limit circuit is a g
m
amplifier that pulls a current from the RUN/SS pin propor-
tional to the difference between the SW and I
MAX
voltages.
This current begins to discharge the capacitor at RUN/SS,
reducing the duty cycle and controlling the output voltage
until the current regulates at the limit. Depending on the
size of the capacitor, it may take many cycles to discharge
the RUN/SS voltage enough to properly regulate the
output current. This is where the instantaneous limit
circuit comes into play. The instantaneous limit circuit is
a cycle-by-cycle comparator which monitors the bottom
MOSFET’s drain voltage and keeps the top MOSFET from
turning on whenever the drain voltage is 50mV above the
programmed max drain voltage. Thus the cycle-by-cycle
comparator will keep the inductor current under control
until the g
m
amplifier gains control.
Pulse Skip Mode
The LTC3703-5 can operate in one of two modes select-
able with the MODE/SYNC pin—Pulse Skip Mode or
forced continuous mode. Pulse Skip Mode is selected
when increased efficiency at light loads is desired. In this
mode, the bottom MOSFET is turned off when inductor
current reverses to minimize the efficiency loss due to
reverse current flow. As the load is decreased (see Fig-
ure 5), the duty cycle is reduced to maintain regulation
until its minimum on-time (~200ns) is reached. When the
load decreases below this point, the LTC3703-5 begins to Figure 4. Efficiency in Pulse Skip/Forced Continuous Modes
LOAD (mA)
10
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0100 1000 10000
37035 F04
FORCED CONTINUOUS
PULSE SKIP MODE
V
IN
= 42V
V
IN
= 12V
V
OUT
= 5V
V
IN
= 12V
V
IN
= 42V
skip cycles to maintain regulation. The frequency drops
but this further improves efficiency by minimizing gate
charge losses. In forced continuous mode, the bottom
MOSFET is always on when the top MOSFET is off,
allowing the inductor current to reverse at low currents.
This mode is less efficient due to resistive losses, but has
the advantage of better transient response at low currents,
constant frequency operation, and the ability to maintain
regulation when sinking current. See Figure 4 for a com-
parison of the effect on efficiency at light loads for each
mode. The MODE/SYNC threshold is 0.8V ±7.5%, allow-
ing the MODE/SYNC to act as a feedback pin for regulating
a second winding. If the feedback voltage drops below
0.8V, the LTC3703-5 reverts to continuous operation to
maintain regulation in the secondary supply.
Figure 5. Comparison of Inductor Current Waveforms for Pulse Skip Mode and Forced Continuous Operation
PULSE SKIP MODE FORCED CONTINUOUS
DECREASING
LOAD
CURRENT
37035 F05
OPERATIO
U
(Refer to Functional Diagram)
LTC3703-5
12
37035fa
The basic LTC3703-5 application circuit is shown on the first
page of this data sheet. External component selection is de-
termined by the input voltage and load requirements as
explained in the following sections. After the operating
frequency is selected, R
SET
and L can be chosen. The
operating frequency and the inductor are chosen for a
desired amount of ripple current and also to optimize ef-
ficiency and component size. Next, the power MOSFETs and
D1 are selected based on voltage, load and efficiency re-
quirements. C
IN
is selected for its ability to handle the large
RMS currents in the converter and C
OUT
is chosen with low
enough ESR to meet the output voltage ripple and transient
specifications. Finally, the loop compensation components
are chosen to meet the desired transient specifications.
Operating Frequency
The choice of operating frequency and inductor value is a
trade off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses and gate charge losses. How-
ever, lower frequency operation requires more induc-
tance for a given amount of ripple current, resulting in a
larger inductor size and higher cost. If the ripple current
is allowed to increase, larger output capacitors may be
required to maintain the same output ripple. For convert-
ers with high step-down VIN to VOUT ratios, another
consideration is the minimum on-time of the LTC3703-5
(see the Minimum On-time Considerations section). A
final consideration for operating frequency is that in
APPLICATIO S I FOR ATIO
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noise-
sensitive communications systems, it is often de-
sirable to keep the switching noise out of a sensitive
frequency band.
The LTC3703-5 uses a constant frequency architecture
that can be programmed over a 100kHz to 600kHz range
with a single resistor from the f
SET
pin to ground, as shown
in the circuit on the first page of this data sheet. The
nominal voltage on the f
SET
pin is 1.2V, and the current that
flows from this pin is used to charge and discharge an
internal oscillator capacitor. The value of R
SET
for a given
operating frequency can be chosen from Figure 6 or from
the following equation:
Rk f kHz
SET () ()–
Ω=7100
25
Buck or Boost Mode Operation
The LTC3703-5 has the capability of operating both as a
step-down (buck) and step-up (boost) controller. In boost
mode, output voltages as high as 60V can be tightly
regulated. With the INV pin grounded, the LTC3703-5
operates in buck mode with TG driving the main (top side)
switch and BG driving the synchronous (bottom side)
switch. If the INV pin is pulled above 2V, the LTC3703-5
operates in boost mode with BG driving the main (bottom
side) switch and TG driving the synchronous (top side)
switch. Internal circuit operation is very similar regardless
of the operating mode with the following exceptions: In
boost mode, Pulse Skip Mode operation is always dis-
abled regardless of the level of the MODE/SYNC pin and
the line feedforward compensation is also disabled. The
overcurrent circuitry continues to monitor the load current
by looking at the drain voltage of the main (bottom side)
MOSFET. In boost mode, however, the peak MOSFET
current does not equal the load current but instead
I
D
= I
LOAD
/(1 – D). This factor needs to be taken into
account when programming the I
MAX
voltage.
FREQUENCY (kHz)
R
SET
(kΩ)
1000
37035 F06
10
1
100
200 1000800600400
0
Figure 6. Timing Resistor (RSET) Value
OPERATIO
U
(Refer to Functional Diagram)
LTC3703-5
13
37035fa
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
Pulse Skip Mode operation is disabled. The clock high
level must exceed 2V for at least 25ns. As shown in
Figure 7, the top MOSFET turn-on will follow the rising
edge of the external clock by a constant delay equal to one-
tenth of the cycle period.
ripple current occurs at the highest V
IN
. To guarantee that
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
LV
fI
V
V
OUT
LMAX
OUT
IN MAX
≥∆
⎛
⎝
⎜⎞
⎠
⎟
() ()
–1
The inductor also has an affect on low current operation
when Pulse Skip Mode operation is enabled. The fre-
quency begins to decrease when the output current drops
below the average inductor current at which the LTC3703-5
is operating at its t
ON(MIN)
in discontinuous mode (see
Figure 5). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
Power MOSFET Selection
The LTC3703-5 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type and “on” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
be used. A much smaller and much lower input capaci-
tance MOSFET should be used for the top MOSFET in
applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V
IN
>> V
OUT
,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch-
ing regulators.
Selection criteria for the power MOSFETs include the “on”
resistance R
DS(ON)
, input capacitance, breakdown voltage
and maximum output current.
The most important parameter in high voltage applica-
tions is breakdown voltage BV
DSS
. Both the top and
bottom MOSFETs will see full input voltage plus any
additional ringing on the switch node across its drain-to-
source during its off-time and must be chosen with the
37035 F07
2V TO 10V
MODE/
SYNC
TG
I
L
t
MIN
= 25ns
0.8T
0.1T
D = 40%
T T = 1/f
O
APPLICATIO S I FOR ATIO
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Figure 7. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
The inductor in a typical LTC3703-5 circuit is chosen for
a specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the
ripple current. The inductor ripple current in the buck
mode is:
∆=⎛
⎝
⎜⎞
⎠
⎟
IV
fL
V
V
LOUT OUT
IN
()() –1
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this, how-
ever, requires a large inductor.
A reasonable starting point is to choose a ripple current
between 20% and 40% of I
O(MAX)
. Note that the largest
LTC3703-5
14
37035fa
appropriate breakdown specification. Since most MOSFETs
in the 30V to 60V range have logic level thresholds
(V
GS(MIN)
≥ 4.5V), the LTC3703-5 is designed to be used
with a 4.5V to 15V gate drive supply (DRV
CC
pin).
For maximum efficiency, on-resistance R
DS(ON)
and input
capacitance should be minimized. Low R
DS(ON)
minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 8).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
DS
drain voltage, but can be
adjusted for different V
DS
voltages by multiplying by the
ratio of the application V
DS
to the curve specified V
DS
values. A way to estimate the C
MILLER
term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V
DS
voltage
specified. C
MILLER
is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
RSS
and C
OS
are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
APPLICATIO S I FOR ATIO
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MainSwitchDutyCycle V
V
SynchronousSwitchDutyCycle VV
V
OUT
IN
IN OUT
IN
=
=–
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
PV
VIR
VIRC
VV V f
PVV
VIR
MAIN OUT
IN MAX DR ON
IN MAX DR MILLER
CC TH IL TH IL
SYNC IN OUT
IN MAX DS N
=
()
++
+
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
=+
2
2
20
1
2
11
1
()
()( )•
–()
–()()
()
() ()
()
δ
δ
where δ is the temperature dependency of R
DS(ON)
, R
DR
is
the effective top driver resistance (approximately 2Ω at
V
GS
= V
MILLER
), V
IN
is the drain potential
and
the change
in drain potential in the particular application. V
TH(IL)
is the
data sheet specified typical gate threshold voltage speci-
fied in the power MOSFET data sheet at the specified drain
current. C
MILLER
is the calculated capacitance using the
gate charge curve from the MOSFET data sheet and the
technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 25V, the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 25V, the transition losses
rapidly increase to the point that the use of a higher
RDS(ON) device with lower CMILLER actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, and
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
Figure 8. Gate Charge Characteristic
+
–
V
DS
V
IN
V
GS
MILLER EFFECT
Q
IN
ab
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
37035 F08
LTC3703-5
15
37035fa
Multiple MOSFETs can be used in parallel to lower R
DS(ON)
and meet the current and thermal requirements if desired.
The LTC3703-5 contains large low impedance drivers
capable of driving large gate capacitances without signifi-
cantly slowing transition times. In fact, when driving
MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (10Ω or less) to reduce noise and EMI caused by
the fast transitions.
Schottky Diode Selection
The Schottky diode D1 shown in the circuit on the first
page of this data sheet conducts during the dead time
between the conduction of the power MOSFETs. This
prevents the body diode of the bottom MOSFET from
turning on and storing charge during the dead time and
requiring a reverse recovery period that could cost as
much as 1% to 2% in efficiency. A 1A Schottky diode is
generally a good size for 3A to 5A regulators. Larger
diodes result in additional losses due to their larger
junction capacitance. The diode can be omitted if the
efficiency loss can be tolerated.
Input Capacitor Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle V
OUT
/V
IN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
II
V
V
V
V
CIN RMS O MAX OUT
IN
IN
OUT
() ()
/
–≅⎛
⎝
⎜⎞
⎠
⎟
1
12
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
O(MAX)
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be placed in
parallel to meet size or height requirements in the design.
Because tantalum and OS-CON capacitors are not avail-
able in voltages above 30V, ceramics or aluminum
electrolytics must be used for regulators with input sup-
plies above 30V. Ceramic capacitors have the advantage of
very low ESR and can handle high RMS current, but
ceramics with high voltage ratings (>50V) are not available
with more than a few microfarads of capacitance. Further-
more, ceramics have high voltage coefficients which means
that the capacitance values decrease even more when used
at the rated voltage. X5R and X7R type ceramics are rec-
ommended for their lower voltage and temperature coef-
ficients. Another consideration when using ceramics is
their high Q which, if not properly damped, may result in
excessive voltage stress on the power MOSFETs. Alumi-
num electrolytics have much higher bulk capacitance, but
they have higher ESR and lower RMS current ratings.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low
ESR and RMS current. If the RMS current cannot be
handled by the aluminum capacitors alone, when used
together, the percentage of RMS current that will be
supplied by the aluminum capacitor is reduced to
approximately:
%
()
•%
,
I
fCR
RMS ALUM
ESR
≈
+
1
18
100
2
where R
ESR
is the ESR of the aluminum capacitor and C is
the overall capacitance of the ceramic capacitors. Using an
aluminum electrolytic with a ceramic also helps damp the
high Q of the ceramic, minimizing ringing.
Output Capacitor Selection
The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(∆V
OUT
) is approximately equal to:
∆≤∆ +
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT L OUT
1
8
Since ∆I
L
increases with input voltage, the output ripple is
highest at maximum input voltage. ESR also has a signifi-
cant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of C
OUT
until the feedback loop in the LTC3703-5 can
change the inductor current to match the new load current
APPLICATIO S I FOR ATIO
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LTC3703-5
16
37035fa
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
Manufacturers such as Nichicon, Nippon Chemi-Con and
Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semicon-
ductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electro-
lytic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recom-
mended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, spe-
cial polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminum electrolytic capacitors have significantly higher
ESR, but can be used in cost-driven applications providing
that consideration is given to ripple current ratings and
long term reliability. Other capacitor types include
Panasonic SP and Sanyo POSCAPs.
Output Voltage
The LTC3703-5 output voltage is set by a resistor divider
according to the following formula:
VV
R
R
OUT =+
⎛
⎝
⎜⎞
⎠
⎟
08 1 1
2
.
The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of ±1%. Tolerance of the feedback resistors will
add additional error to the output voltage. 0.1% to 1%
resistors are recommended.
MOSFET Driver Supplies (DRV
CC
and BOOST)
The LTC3703-5 drivers are supplied from the DRV
CC
and
BOOST pins (see Figure 2), which have an absolute
maximum voltage of 15V. If the main supply voltage, V
IN
,
is higher than 15V a separate supply with a voltage
between 5V and 15V must be used to power the drivers. If
a separate supply is not available, one can easily be
generated from the main supply using one of the circuits
shown in Figure 9. If the output voltage is between 5V and
15V, the output can be used to directly power the drivers
as shown in Figure 9a. If the output is below 5V, Figure 9b
shows an easy way to boost the supply voltage to a
sufficient level. This boost circuit uses the LT1613 in a
ThinSOT
TM
package and a chip inductor for minimal extra
area (<0.2 in
2
). Two other possible schemes are an extra
winding on the inductor (Figure 9c) or a capacitive charge
pump (Figure 9d). All the circuits shown in Figure 9
require a start-up circuit (Q1, D1 and R1) to provide driver
power at initial start-up or following a short-circuit. The
resistor R1 must be sized so that it supplies sufficient base
current and zener bias current at the lowest expected value
of V
IN
. When using an existing supply, the supply must be
capable of supplying the required gate driver current
which can be estimated from:
I
DRVCC
= (f)(Q
G(TOP)
+ Q
G(BOTTOM)
)
This equation for I
DRVCC
is also useful for properly sizing
the circuit components shown in Figure 9.
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFETs. Capacitor CB is charged through external
diode, DB, from the DRVCC supply when SW is low. When
the top side MOSFET is turned on, the driver places the CB
voltage across the gate-source of the top MOSFET. The
switch node voltage, SW, rises to VIN and the BOOST pin
follows. With the topside MOSFET on, the boost voltage
is above the input supply: VBOOST = VIN + VDRVCC. The
value of the boost capacitor CB needs to be 100 times that
of the total input capacitance of the top side MOSFET(s).
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
APPLICATIO S I FOR ATIO
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ThinSOT is a tradmark of Linear Technology Corporation.
LTC3703-5
17
37035fa
Figure 9a. VCC Generated from 5V < VOUT < 15V
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V
CC
DRV
CC
V
IN
TG
SW
BG
BGRTN
LTC3703-5
V
OUT
5V TO
15V
+C
OUT
37035 F09a
+CIN
+1µF
VIN
L1
D1
5.1V
R1
Q1
V
CC
DRV
CC
V
IN
TG
SW
BG
BGRTN
LTC3703-5
V
OUT
<5V
+C
OUT
3703 F09b
+
C
IN
C9
4.7µF
6.3V
V
IN
L1
D1
5.1V
Q1 R1
C10
1µF
10V V
IN
SW
GND
SHDN
FB
R17
37.4k
1%
R17
12.1k
1%
LT1613
D2
ZHCS400 L2
4.7µH
Figure 9b. VCC Generated from VOUT < 5V
current to flow at full reverse voltage. If the reverse
current times reverse voltage exceeds the maximum
allowable power dissipation, the diode may be damaged.
For best results, use an ultrafast recovery diode such as
the MMDL770T1.
An internal undervoltage lockout (UVLO) monitors the
voltage on DRV
CC
to ensure that the LTC3703-5 has
sufficient gate drive voltage. If the DRV
CC
voltage falls
V
CC
DRV
CC
FCB
GND
V
IN
TG1
SW
BG1
BGRTN
LTC3703-5
V
OUT
V
SEC
+C
OUT
+1µF
3703 F09c
R1
V
IN
T1
OPTIONAL V
CC
CONNECTION
5V < V
SEC
< 15V
R2
+C
IN
R1
Q1
N
1
D1
5.1V
VCC
DRVCC
VIN
TG
SW
BG
BGRTN
LTC3703-5
VOUT
+COUT
3703 F09d
+
+
CIN
VIN (<40V)
L1
1µF
Q1
R1
BAT85
BAT85 BAT85
VN2222LL
0.22µF
D1
5.1V
Figure 9c. Secondary Output Loop and VCC Connection Figure 9d. Capacitive Charge Pump for VCC (VIN < 40V)
below the UVLO threshold, the LTC3703-5 shuts down
and the gate drive outputs remain low.
Bottom MOSFET Source Supply (BGRTN)
The bottom gate driver, BG, switches from DRV
CC
to BGRTN
where BGRTN can be a voltage between ground and –5V.
Why not just keep it simple and always connect BGRTN to
ground? In high voltage switching converters, the switch
LTC3703-5
18
37035fa
node dV/dt can be many volts/ns, which will pull up on the
gate of the bottom MOSFET through its Miller capacitance.
If this Miller current, times the internal gate resistance of
the MOSFET plus the driver resistance, exceeds the thresh-
old of the FET, shoot-through will occur. By using a nega-
tive supply on BGRTN, the BG can be pulled below ground
when turning the bottom MOSFET off. This provides a few
extra volts of margin before the gate reaches the turn-on
threshold of the MOSFET. Be aware that the maximum
voltage difference between DRV
CC
and BGRTN is 15V. If,
for example, V
BGRTN
= –2V, the maximum voltage on
DRV
CC
pin is now 13V instead of 15V.
Current Limit Programming
Programming current limit on the LTC3703-5 is straight
forward. The I
MAX
pin sets the current limit by setting the
maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its on-
resistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703-5 current
limit circuit inverts the negative voltage across the MOSFET
before comparing it to the voltage at I
MAX
, allowing the
current limit to be set with a positive voltage.
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
V
PROG
= (I
LIMIT
)(R
DS(ON)
)(
1 + δ
)
where
δ
is explained in the MOSFET Selection section.
V
PROG
is then programmed at the I
MAX
pin using the
internal 12µA pull-up and an external resistor:
R
IMAX
= V
PROG
/12µA
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
OUT(MAX)
. The minimum value of current limit
generally occurs with the largest V
IN
at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I
LIMIT
which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the R
DS(ON)
of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for R
DS(ON)
, but not a minimum. A
reasonable assumption is that the minimum R
DS(ON)
lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
For best results, use a V
PROG
voltage between 100mV and
500mV. Values outside of this range may give less accu-
rate current limit. The current limit can also be disabled by
floating the I
MAX
pin.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
In a typical LTC3703-5 circuit, the feedback loop consists
of the modulator, the external inductor, the output capaci-
tor and the feedback amplifier with its compensation
network. All of these components affect loop behavior and
must be accounted for in the loop compensation. The
modulator consists of the internal PWM generator, the
output MOSFET drivers and the external MOSFETs them-
selves. From a feedback loop point of view, it looks like a
linear voltage transfer function from COMP to SW and has
a gain roughly equal to the input voltage. It has fairly
benign AC behavior at typical loop compensation frequen-
cies with significant phase shift appearing at half the
switching frequency.
The external inductor/output capacitor combination makes
a more significant contribution to loop behavior. These
components cause a second order LC roll off at the output,
with the attendant 180° phase shift. This rolloff is what filters
the PWM waveform, resulting in the desired DC output
voltage, but the phase shift complicates the loop compen-
sation if the gain is still higher than unity at the pole fre-
quency. Eventually (usually well above the LC pole
frequency), the reactance of the output capacitor will ap-
proach its ESR and the rolloff due to the capacitor will stop,
leaving 6dB/octave and 90° of phase shift (Figure 10).
So far, the AC response of the loop is pretty well out of the
user’s control. The modulator is a fundamental piece of the
LTC3703-5 design and the external L and C are usually
chosen based on the regulation and load current require-
ments without considering the AC loop response. The
APPLICATIO S I FOR ATIO
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LTC3703-5
19
37035fa
for an extended frequency range. LTC3703-5 circuits
using conventional switching grade electrolytic output
capacitors can often get acceptable phase margin with
Type 2 compensation.
“Type 3” loops (Figure 13) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703-5
circuits using low ESR tantalum or OS-CON output capaci-
tors need Type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and some-
thing less than 360° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 11). This “Type
1” configuration is stable but transient response is less
than exceptional if the LC pole is at a low frequency.
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GAIN (dB)
37035 F10
A
V
0
PHASE
–6dB/OCT
–12dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
Figure 10. Transfer Function of Buck Modulator
GAIN (dB)
37035 F11
0
PHASE
–6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
RB
R1
FB
C1
IN
OUT
+
–
VREF
Figure 11. Type 1 Schematic and Transfer Function
GAIN (dB)
37035 F12
0
PHASE
–6dB/OCT
–6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
R
B
V
REF
R1
R2
FB
C2
IN
OUT
+
–
C1
Figure 12. Type 2 Schematic and Transfer Function
GAIN (dB)
37035 F13
0
PHASE
–6dB/OCT
+6dB/OCT –6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
R
B
V
REF
R1
R2
FB
C2
IN
OUT
+
–
C1
C3
R3
Figure 13. Type 3 Schematic and Transfer Function
Figure 12 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable perfor-
mance with similar power components, but can be way off
LTC3703-5
20
37035fa
if even one major power component is changed signifi-
cantly. Applications that require optimized transient re-
sponse will require recalculation of the compensation
values specifically for the circuit in question. The underly-
ing mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.
Modulator gain and phase can be measured directly from
a breadboard or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurate results, but simulation can often get close enough
to give a working system. To measure the modulator gain
and phase directly, wire up a breadboard with an LTC3703-5
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC3703-5, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
V
OUT
to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (R
B
) as required to set the
desired output voltage. Disconnect R
B
from ground and
connect it to a signal generator or to the source output of
a network analyzer (Figure 14) to inject a test signal into
the loop. Measure the gain and phase from the COMP pin
to the output node at the positive terminal of the output
capacitor. Make sure the analyzer’s input is AC coupled so
that the DC voltages present at both the COMP and V
OUT
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nodes don’t corrupt the measurements or damage the
analyzer.
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
ate an AC plot of V(V
OUT
)/V(COMP) in dB and phase of
V
OUT
in degrees. Refer to your SPICE manual for details of
how to generate this plot.
*3703-5 modulator gain/phase
*2003 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
*MOSFETs
rfet mod sw 0.02 ;MOSFET rdson
*inductor
lext sw out1 10u ;inductor value
rl out1 out 0.015 ;inductor series R
*output cap
cout out out2 540u ;capacitor value
resr out2 0 0.01 ;capacitor ESR
*3703-5 internals
emod mod 0 value = {43*v(comp)}
;3703-5multiplier
vstim comp 0 0 ac 1 ;ac stimulus
.ac dec 100 1k 1meg
.probe
.end
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 10. Choose the crossover frequency in the
rising or flat parts of the phase curve, beyond the external
LC poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be –GAIN to make the loop gain at 0dB at this
frequency. Now calculate the needed phase boost, assum-
ing 60° as a target phase margin:
BOOST = –(PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
V
IN
TG
SW
BG
INV
MODE/SYNC
COMP
FB
RUN/SS
LTC3703-5
V
CC
C
IN
5V V
IN
M1
V
OUT
TO
ANALYZER
V
COMP
TO
ANALYZER
AC
SOURCE
FROM
ANALYZER
L
EXT
M2
10µF
DRV
CC
f
SET
0.1µF
R
B
BOOST
GND BGRTN
++
10k
NC C
OUT
37035 F14
+
Figure 14. Modulator Gain/Phase Measurement Set-Up
LTC3703-5
21
37035fa
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
Finally, choose a convenient resistor value for R1 (10k is
usually a good value). Now calculate the remaining values:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10
(GAIN/20)
(this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
TYPE 3 Loop:
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Boost Converter Design
The following sections discuss the use of the LTC3703-5
as a step-up (boost) converter. In boost mode, the
LTC3703-5 can step-up output voltages as high as 60V.
These sections discuss only the design steps specific to a
boost converter. For the design steps common to both a
buck and a boost, see the applicable section in the buck
mode section. An example of a boost converter circuit is
shown in the Typical Applications section. To operate the
LTC3703-5 in boost mode, the INV pin should be tied to
the V
CC
voltage (or a voltage above 2V). Note that in boost
mode, pulse-skip operation and the line feedforward com-
pensation are disabled.
For a boost converter, the duty cycle of the main switch is:
DVV
V
OUT IN
OUT
=–
For high V
OUT
to V
IN
ratios, the maximum V
OUT
is limited
by the LTC3703-5’s maximum duty cycle which is typically
93%. The maximum output voltage is therefore:
VV
DV
OUT MAX IN MIN
MAX IN MIN() () ()
–
=≅
114
Boost Converter: Inductor Selection
In a boost converter, the average inductor current equals
the average input current. Thus, the maximum average
inductor current can be calculated from:
II
DIV
V
LMAX OMAX
MAX OMAX O
IN MIN
() () () ()
•=−=
1
As with a buck converter, choose the ripple current to be
20% to 40% of I
L(MAX)
. The ripple current amplitude then
determines the inductor value as follows:
LV
IfD
IN MIN
L
MAX
=∆
()
••
The minimum required saturation current for the inductor
is:
I
L(SAT)
> I
L(MAX)
+ ∆I
L
/2
KBOOST
CfGKR
CCK
RK
fC
RVR
VV
BREF
OUT REF
=+°
⎛
⎝
⎜⎞
⎠
⎟
=
=−
()
=
=−
tan
•• • •
••
()
245
21
21
12 1
221
1
2
π
π
KBOOST
CfGR
CCK
RK
fC
RR
K
C
fKR
RVR
VV
BREF
OUT REF
=+°
⎛
⎝
⎜⎞
⎠
⎟
=
=−
()
=
=−
=
=−
tan
•• •
••
•
()
2
445
21
21
12 1
221
31
1
31
23
1
π
π
π
LTC3703-5
22
37035fa
Boost Converter: Power MOSFET Selection
For information about choosing power MOSFETs for a
boost converter, see the Power MOSFET Selection sec-
tion for the buck converter, since MOSFET selection is
similar. However, note that the power dissipation equa-
tions for the MOSFETs at maximum output current in a
boost converter are:
PD I
DR
VI
DRC
VV V f
PDIR
MAIN MAX MAX
MAX DS ON
OUT MAX
MAX DR MILLER
CC TH IL TH IL
SYNC MAX MAX DS ON
=⎛
⎝
⎜⎞
⎠
⎟+
()
+
⎛
⎝
⎜⎞
⎠
⎟
()( )
+
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
()
=⎛
⎝
⎜⎞
⎠
⎟
()
+
()
11
1
21
11
1
11
2
2
2
–
–•
–
––
()
() ()
()
δ
δ
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
more demanding due to the fact that the current waveform
is pulsed instead of continuous as in a buck converter. The
choice of component(s) is driven by the acceptable ripple
voltage which is affected by the ESR, ESL and bulk
capacitance as shown in Figure 15. The total output ripple
voltage is:
∆=+
⎛
⎝
⎜⎞
⎠
⎟
VI fC
ESR
D
OUT O MAX
OUT MAX
()
•–
1
1
where the first term is due to the bulk capacitance and
second term due to the ESR.
The choice of output capacitor is driven also by the RMS
ripple current requirement. The RMS ripple current is:
II
VV
V
RMS COUT O MAX O IN MIN
IN MIN
()() ()
()
•–
≈
At lower output voltages (less than 30V), it may be
possible to satisfy both the output ripple voltage and RMS
ripple current requirements with one or more capacitors of
APPLICATIO S I FOR ATIO
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Figure 15. Output Voltage Ripple
Waveform for a Boost Converter
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆VESR
∆VCOUT
VOUT
(AC)
a single capacitor type. However, at output voltages above
30V where capacitors with both low ESR and high bulk
capacitance are hard to find, the best approach is to use a
combination of aluminum and ceramic capacitors (see
discussion in Input Capacitor section for the buck con-
verter). With this combination, the ripple voltage can be
improved significantly. The low ESR ceremic capacitor
will minimize the ESR step, while the electrolytic will
supply the required bulk capacitance.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical than
the output capacitor, due to the fact that the inductor is in
series with the input and the input current waveform is
continuous. The input voltage source impedance deter-
mines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is
recommended though not as critical as for the output
capacitor.
The RMS input capacitor ripple current for a boost con-
verter is:
IV
Lf D
RMS CIN IN MIN MAX() ()
.• ••=03
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
Boost Converter: Current Limit Programming
The LTC3703-5 provides current limiting in boost mode by
monitoring the V
DS
of the main switch during its on-time
and comparing it to the voltage at I
MAX
. To set the current
limit, calculate the expected voltage drop across the
MOSFET at the maximum desired inductor current and
LTC3703-5
23
37035fa
maximum junction temperature. The maximum inductor
current is a function of both duty cycle and maximum load
current, so the limit must be set for the maximum expected
duty cycle (minimum V
IN
) in order to ensure that the
current limit does not kick in at loads < I
O(MAX)
:
VI
DR
V
VIR
PROG OMAX
MAX DS ON
OUT
IN MIN O MAX DS ON
=+
=⎛
⎝
⎜⎞
⎠
⎟+
() ()
()() ()
–()
•()
11
1
δ
δ
Once V
PROG
is determined, R
IMAX
is chosen as follows:
R
IMAX
= V
PROG
/12µA
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where V
OUT
> V
IN
.
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Program-
ming for buck mode for further considerations for current
limit programming.
Boost Converter: Feedback Loop/Compensation
Compensating a voltage mode boost converter is unfortu-
nately more difficult than for a buck converter. This is due
to an additional right-half plane (RHP) zero that is present
in the boost converter but not in a buck. The additional phase
lag resulting from the RHP zero is difficult if not impossible
to compensate even with a Type 3 loop, so the best approach
is usually to roll off the loop gain at a lower frequency than
what could be achievable in buck converter.
A typical gain/phase plot of a voltage-mode boost con-
verter is shown in Figure 16. The modulator gain and
phase can be measured as described for a buck converter
or can be estimated as follows:
GAIN (COMP-to-V
OUT
DC gain) = 20Log(V
OUT2
/V
IN
)
Dominant Pole: f
P
=
V
VLC
IN
OUT
•1
2π
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of the
compensation network should equal –GAIN at this fre-
quency so that the overall loop gain is 0dB here. The
compensation component to achieve this, using a Type 1
amplifier (see Figure 11), is:
G = 10
–GAIN/20
C1 = 1/(2π • f • G • R1)
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provide a soft-
start function and a means to shut down the LTC3703-5.
Soft-start reduces the input supply’s surge current by
gradually increasing the duty cycle and can also be used
for power supply sequencing.
Pulling RUN/SS below 1V puts the LTC3703-5 into a low
quiescent current shutdown (I
Q
≅ 25µA). This pin can be
driven directly from logic as shown in Figure 17. Releasing
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Figure 16. Transfer Function of Boost Modulator
GAIN
(dB)
PHASE
(DEG)
37035 F16
A
V
00
–90
–180
PHASE
GAIN
–12dB/OCT
Figure 17. LTC3703-5 Startup Operation
2ms/DIV
V
OUT
5V/DIV
V
IN
= 50V
I
LOAD
= 2A
C
SS
= 0.01µF
RUN/SS
2V/DIV
I
L
2A/DIV
37035 F17
LTC3703-5
24
37035fa
the main output voltage and the turns ratio of the extra
winding to the primary winding as follows:
V
SEC
≈ (N + 1)V
OUT
Since the secondary winding only draws current when the
synchronous switch is on, load regulation at the auxiliary
output will be relatively good as long as the main output is
running in continuous mode. As the load on the primary
output drops and the LTC3703-5 switches to Pulse Skip
Mode operation, the auxiliary output may not be able to
maintain regulation, especially if the load on the auxiliary
output remains heavy. To avoid this, the auxiliary output
voltage can be divided down with a conventional feedback
resistor string with the divided auxiliary output voltage fed
back to the MODE/SYNC pin. The MODE/SYNC threshold
is trimmed to 800mV with 20mV of hysteresis, allowing
precise control of the auxiliary voltage and is set as
follows:
VV
R
R
SEC MIN()
.≈+
⎛
⎝
⎜⎞
⎠
⎟
08 1 1
2
where R1 and R2 are shown in Figure 9c.
If the LTC3703-5 is operating in Pulse Skip Mode and the
auxiliary output voltage drops below V
SEC(MIN)
, the MODE/
SYNC pin will trip and the LTC3703-5 will resume continu-
ous operation regardless of the load on the main output.
Thus, the MODE/SYNC pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary winding. With the loop
in continuous mode (MODE/SYNC < 0.8V), the auxiliary
outputs may nominally be loaded without regard to the
primary output load.
The following table summarizes the possible states avail-
able on the MODE/SYNC pin:
Table 1.
MODE/SYNC Pin Condition
DC Voltage: 0V to 0.75V Forced Continuous
Current Reversal Enabled
DC Voltage: ≥ 0.87V Pulse Skip Mode Operation
No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext. Clock: 0V to ≥ 2V Forced Continuous
No Current Reversal
the RUN/SS pin allows an internal 4µA current source to
charge up the soft-start capacitor C
SS
. When the voltage
on RUN/SS reaches 1V, the LTC3703-5 begins operating
at its minimum on-time. As the RUN/SS voltage increases
from 1V to 3V, the duty cycle is allowed to increase from
0% to 100%. The duty cycle control minimizes input
supply inrush current and elimates output voltage over-
shoot at start-up and ensures current limit protection even
with a hard short. The RUN/SS voltage is internally clamped
at 4V.
If RUN/SS starts at 0V, the delay before starting is
approximately:
tV
ACsFC
DELAY START SS SS,
(. / )=µ=µ
1
4025
plus an additional delay, before the output will reach its
regulated value, of:
tVV
ACsFC
DELAY REG SS SS,
–(. / )≥µ=µ
31
405
The start delay can be reduced by using diode D1 in
Figure 18.
Figure 18. RUN/SS Pin Interfacing
APPLICATIO S I FOR ATIO
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3.3V
OR 5V RUN/SS
D1
CSS
37035 F18
RUN/SS
CSS
MODE/SYNC Pin (Operating Mode and Secondary
Winding Control)
The MODE/SYNC pin is a dual function pin that can be used
for enabling or disabling Pulse Skip Mode operation and
also as an external clock input for synchronizing the inter-
nal oscillator (see next section). Pulse Skip Mode is enabled
when the MODE/SYNC pin is above 0.8V and is disabled,
i.e. forced continuous, when the pin is below 0.8V.
In addition to providing a logic input to force continuous
operation and external synchronization, the MODE/SYNC
pin provides a means to regulate a flyback winding output
as shown in Figure 9c. The auxiliary output is taken from
a second winding on the core of the inductor, converting
it to a transformer. The auxiliary output voltage is set by
LTC3703-5
25
37035fa
MODE/SYNC Pin (External Synchronization)
The internal LTC3703-5 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2VP-P. The internal oscillator
locks to the external clock after the second clock transi-
tion is received. When external synchronization is de-
tected, LTC3703-5 will operate in forced continuous
mode. If an external clock transition is not detected for
three successive periods, the internal oscillator will revert
to the frequency programmed by the RSET resistor. The
internal oscillator can synchronize to frequencies be-
tween 100kHz and 600kHz, independent of the frequency
programmed by the RSET resistor. However, it is recom-
mended that an RSET resistor be chosen such that the
frequency programmed by the RSET resistor is close to the
expected frequency of the external clock. In this way, the
best converter operation (ripple, component stress, etc)
is achieved if the external clock signal is lost.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC3703-5 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
tV
Vf
t
ON OUT
IN
ON MIN
=>
•()
where t
ON(MIN)
is typically 200ns.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3703-5 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t
ON(MIN)
for the same step-down ratio.
Pin Clearance/Creepage Considerations
The LTC3703-5 is available in two packages (GN16 and
G28) both with identical functionality. The GN16 package
gives the smallest size solution, however the 0.013”
(minimum) space between pins may not provide sufficient
APPLICATIO S I FOR ATIO
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PC board trace clearance between high and low voltage
pins in higher voltage applications. Where clearance is an
issue, the G28 package should be used. The G28 package
has 4 unconnected pins between the all adjacent high
voltage and low voltage pins, providing 5(0.0106”) =
0.053” clearance which will be sufficient for most applica-
tions up to 60V. For more information, refer to the printed
circuit board design standards described in IPC-2221
(www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703-5 circuits: 1) LTC3703-5 V
CC
current,
2) MOSFET gate current, 3) I
2
R losses and 4) Topside
MOSFET transition losses.
1. V
CC
Supply current. The V
CC
current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703-5.
Total supply current is typically about 2.5mA and usually
results in a small (<1%) loss which is proportional to V
CC
.
2. DRV
CC
current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge Q
G
moves from DRV
CC
to
ground. The resulting dQ/dt is a current out of the DRV
CC
supply. In continuous mode, I
DRVCC
= f(Q
G(TOP)
+ Q
G(BOT)
),
where Q
G(TOP)
and Q
G(BOT)
are the gate charges of the top
and bottom MOSFETs.
3. I
2
R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
LTC3703-5
26
37035fa
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with the
DCR resistance of L to obtain I
2
R losses. For example, if
each R
DS(ON)
= 25mΩ and R
L
= 25mΩ, then total resis-
tance is 50mΩ. This results in losses ranging from 1% to
5% as the output current increases from 1A to 5A for a 5V
output.
4. Transition losses apply only to the topside MOSFET in
buck mode and they become significant when operating at
higher input voltages (typically 20V or greater). Transition
losses can be estimated from the second term of the P
MAIN
equation found in the Power MOSFET Selection section.
The transition losses can become very significant at the
high end of the LTC3703-5 operating voltage range. To
improve efficiency, one may consider lowering the fre-
quency and/or using MOSFETs with lower C
RSS
at the
expense of higher R
DS(ON)
.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, Schottky conduction losses during dead-time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703-5, the output accuracy due
to DC variations in input voltage and output load current
will be almost negligible. For the few cycles following a
load transient, however, the output deviation may be
larger while the feedback loop is responding. Consider a
typical 48V input to 5V output application circuit,
subjected to a 1A to 5A load transient. Initially, the loop is
in regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A (= 5A-1A) flows out of the
output capacitor while the inductor is still supplying only
1A. This sudden change will generate a (4A) • (RESR)
voltage step at the output; with a typical 0.015Ω output
capacitor ESR, this is a 60mV step at the output.
The feedback loop will respond and will move at the band-
width allowed by the external compensation network
towards a new duty cycle. If the unity gain crossover fre-
quency is set to 50kHz, the COMP pin will get to 60% of the
way to 90% duty cycle in 3µs. Now the inductor is seeing
43V across itself for a large portion of the cycle and its
current will increase from 1A at a rate set by di/dt = V/L. If
the inductor value is 10µH, the peak di/dt will be 43V/10µH
or 4.3A/µs. Sometime in the next few micro-seconds after
the switch cycle begins, the inductor current will have
risen to the 5A level of the load current and the output
voltage will stop dropping. At this point, the inductor cur-
rent will rise somewhat above the level of the output cur-
rent to replenish the charge lost from the output capacitor
during the load transient. With a properly compensated
loop, the entire recovery time will be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple ca-
pacitors at the output. The capacitance value accounts for
the rest of the voltage drop until the inductor current rises.
With most output capacitors, several devices paralleled to
get the ESR down will have so much capacitance that this
drop term is negligible. Ceramic capacitors are an excep-
tion; a small ceramic capacitor can have suitably low ESR
with relatively small values of capacitance, making this
second drop term more significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC3703-5 to
recover after the output voltage has dropped due to a load
step. Optimizing loop compensation entails maintaining
the highest possible loop bandwidth while ensuring loop
stability. The feedback component selection section de-
scribes in detail the techniques used to design an opti-
mized Type 3 feedback loop, appropriate for most
LTC3703-5 systems.
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LTC3703-5
27
37035fa
Measurement Techniques
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gener-
ating a suitable transient to test the circuit. Output mea-
surements should be taken with a scope probe directly
across the output capacitor. Proper high frequency prob-
ing techniques should be used. In particular, don’t use the
6" ground lead that comes with the probe! Use an adapter
that fits on the tip of the probe and has a short ground clip
to ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703-5 and the transient generator
must be minimized.
Figure 19 shows an example of a simple transient genera-
tor. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC3703-5
circuits. Solder the MOSFET and the resistor(s) as close to
the output of the LTC3703-5 circuit as possible and set up
the signal generator to pulse at a 100Hz rate with a 5% duty
cycle. This pulses the LTC3703-5 with 500µs
transients10ms apart, adequate for viewing the entire
transient recovery time for both positive and negative
transitions while keeping the load resistor cool.
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 20V to 60V (48V nominal), V
OUT
=
12V ±5%, I
OUT(MAX)
= 10A, f=250kHz. First, calculate R
SET
to give the 250kHz operating frequency:
R
SET
= 7100/(250-25) = 31.6k
Next, choose the inductor value for about 40% ripple
current at maximum V
IN
:
LV
kHz A H=⎛
⎝
⎜⎞
⎠
⎟=µ
12
250 0 4 10 112
60 10
( )( . )( ) –
With 10µH inductor, ripple current will vary from 1.9A to
3.8A (19% to 38%) over the input supply range.
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum V
IN
:
tV
V f kHz ns
ON MIN OUT
IN MIN
() ()
() ( )
== =
12
60 250 800
which is above the LTC3703-5’s 200ns minimum on-time.
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
60V(max) plus any ringing, choose a 60V MOSFET.
Si7850DP has a 60V BV
DSS
, R
DS(ON)
= 22mΩ(max), δ =
0.007/°C, C
MILLER
= (9nC – 3nC)/30V = 200pF, V
GS(MILLER)
= 3.8V, θ
JA
= 20°C/W. The power dissipation can be
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Figure 19. Transient Load Generator
LTC3703-5 V
OUT
IRFZ44 OR
EQUIVALENT
R
LOAD
50Ω
0V TO 10V
100Hz, 5%
DUTY CYCLE
LOCATE CLOSE TO THE OUTPUT
37035 F19
PULSE
GENERATOR
LTC3703-5
28
37035fa
estimated at maximum input voltage, assuming a junction
temperature of 100°C (30°C above an ambient of 70°C):
P
pF k
WWW
MAIN =+
[]
+⎛
⎝
⎜⎞
⎠
⎟+
⎛
⎝
⎜⎞
⎠
⎟
=+=
12
60 10 1 0 007 100 25 0 022
60 10
22 200 1
10 3 8
1
38 250
067 076 143
2
2
() . ( – )(. )
() ()( )• –. . ()
...
And double check the assumed T
J
in the MOSFET:
T
J
= 70°C + (1.43W)(20°C/W) = 99°C
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7850DP
MOSFETs on the bottom:
P
W
SYNC
=−
⎛
⎝
⎜⎞
⎠
⎟+
[]
⎛
⎝
⎜⎞
⎠
⎟=
60 12
60 10 1 0 007 100 25
0 022
2134
2
() . ( – )•
..
T
J
= 70°C + (1.34W)(20°C/W) = 97°C
Next, set the current limit resistor. Since I
MAX
= 10A, the
limit should be set such that the minimum current limit is
>10A. Minimum current limit occurs at maximum R
DS(ON)
.
Using the above calculation for bottom MOSFET T
J
, the
max R
DS(ON)
= (22mΩ/2) [1 + 0.007 (97-25)] = 16.5mΩ
Therefore, I
MAX
pin voltage should be set to (10A)(0.0165)
= 0.165V. The R
SET
resistor can now be chosen to be
0.165V/12µA = 14kΩ.
C
IN
is chosen for an RMS current rating of about 5A
(I
MAX
/2) at 85°C. For the output capacitor, two low ESR
OS-CON capacitors (18mΩ each) are used to minimize
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
(ESR) = (4A)(0.018Ω/2)
= 36mV
However, a 0A to 10A load step will cause an output
voltage change of up to:
∆V
OUT(STEP)
= ∆I
LOAD(ESR)
= (10A)(0.009Ω)
= 90mV
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703-5. These items are also illustrated graphically in
the layout diagram of Figure 20. For layout of a boost mode
converter, layout is similar with V
IN
and V
OUT
swapped.
Check the following in your layout:
1. Keep the signal and power grounds separate. The signal
ground consists of the LTC3703-5 GND pin, the ground
return of C
VCC
, and the (–) terminal of V
OUT
. The power
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRV
CC
capacitor. Connect the signal
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRV
CC
capacitor and away from
the Schottky loop described in (2).
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the C
IN
capacitor
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of C
IN
, and connect the source of the bottom side
MOSFET directly to the (–) terminal of C
IN
. This capacitor
provides the AC current to the MOSFETs.
4. Place the ceramic C
DRVCC
decoupling capacitor imme-
diately next to the IC, between DRV
CC
and BGRTN. This
capacitor carries the MOSFET drivers’ current peaks.
Likewise the C
B
capacitor should also be next to the IC
between BOOST and SW.
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LTC3703-5
29
37035fa
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Figure 20. LTC3703-5 Buck Converter Suggested Layout
LTC3703-5
MODE/SYNC
FSET
COMP
FB
I
MAX
INV
RUN/SS
GND
V
IN
BOOST
TG
SW
VCC
DRV
CC
BG
BGRTN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
C1
C
IN
C
C2
C
C3
R
C1
R
C2
R1
R2
R
F
R
MAX
R
SET
C
B
V
IN
M1
M2
L1
D1
V
OUT
C
OUT
D
B
V
CC
C
SS
37035 F18
C
DRVCC
X5R
C
VCC
X5R
+
+
+
–
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG). In
the layout shown in Figure 20, all the small signal compo-
nents have been placed on one side of the IC and all of the
power components have been placed on the other. This
also helps keep the signal ground and power ground
isolated.
6. A separate decoupling capacitor for the supply, V
CC
, is
useful with an RC filter between the DRV
CC
supply and V
CC
pin to filter any noise injected by the drivers. Connect this
capacitor close to the IC, between the V
CC
and GND pins
and keep the ground side of the V
CC
capacitor (signal
ground) isolated from the ground side of the DRV
CC
capacitor (power ground).
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3703-5 in order to
keep the high impedance FB node short.
8. For applications with multiple switching power convert-
ers connected to the same input supply, make sure that the
input filter capacitor for the LTC3703-5 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple, and this could
interfere with the operation of the LTC3703-5. A few
inches of PC trace or wire (L ≅ 100nH) between C
IN
of the
LTC3703-5 and the actual source V
IN
should be sufficient
to prevent input noise interference problems.
LTC3703-5
30
37035fa
Single Input Supply 5V/5A Output Step-Down Converter
TYPICAL APPLICATIO S
U
15V-60V Input Voltage to 12V/10A Step-Down Converter with Pulse Skip Mode Enabled
LTC3703-5
MODE/SYNC
FSET
COMP
FB
I
MAX
INV
RUN/SS
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
BOOST
TG
SW
V
CC
DRV
CC
BG
BGRTN
C
IN
22µF
100V
×2
C
C2
1000pF
C
C3
2200pF
R
C1
10k
R
MAX
15k
C
C1
470pF
R
C2
100ΩR1
113k
1%
R2
8.06k
1%
R
F
10Ω
R
SET
25k
C
B
0.1µF
V
IN
15V TO 60V
M2
Si7460DP
L1
8µH
D1
MBR1100
V
OUT
12V
10A
C
OUT
220µF
25V
×2
D
B
MMDL770T1
V
CC
5V TO 15V
C
SS
0.1µF
37035 TA01
C
DRVCC
10µF
C
VCC
1µF
+
+
+
M1
Si7850DP
22µF
25V
LTC3703-5
MODE/SYNC
FSET
COMP
FB
I
MAX
INV
RUN/SS
GND
V
IN
BOOST
TG
SW
V
CC
DRV
CC
BG
BGRTN
C
IN
22µF
100V
V
IN
6V TO 60V
C
C2
1000pF
C
C3
2200pF
R
C1
10k
R
MAX
15k
R
C2
100Ω
*OPTIONAL ZENER PROVIDES UNDERVOLTAGE LOCKOUT ON INPUT SUPPLY, V
UVLO
≅ 5 + V
Z
R1
113k
1%
R2
21.5k
1%
R
F
10Ω
R
SET
25k
C
B
0.1µF
M2
Si7850DP
L1 4.7µH
D1
MBR1100
V
OUT
5V
5A
C
OUT
220µF
25V
D
B1
MMDL770T1
C
SS
0.1µF
3703 TA02
C
DRVCC
10µF
C
VCC
1µF
+
+
+
M1
Si7850DP
22µF
25V
FZT600
100Ω
10k *
5.1V
CMDSH-3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
C1
470pF
4.7Ω
D
B2
MMDL770T1
LTC3703-5
31
37035fa
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
G28 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
LTC3703-5
32
37035fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT/LT 0505 REV A • PRINTED IN USA
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TYPICAL APPLICATIO
U
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LTC3703-5
MODE/SYNC
FSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
COUT
220µF
30V
×3
RMAX 15k
0.1µFCC1
100pF
10k
R2
3.92k
1%
RF
10Ω
R1
113k
1%
RSET 25k
CB
0.1µF
M2
Si7892DP
L1
3.3µH
MBRS140T3
VIN
4.5V TO 15V
VOUT
24V
5A
CIN
100µF
20V
DB
CMDSH-3
CSS
0.1µF
37035 TA03
CDRVCC
10µF
CVCC
1µF
+
+
+
M1
Si7390DP
22µF
25V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
