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PRELIMINARY DATA
July 2004
This is preliminary information on a new product now in devel opment or unde rgoing ev aluation. Details are subject to change witho ut no tic e.
M50FW016
16 Mbit (2Mb x8, Uniform Block)
3V Supply Firmware Hub Flash Memory
FEATURES SUMMARY
■SUPPLY VOLTAGE
–V
CC = 3 V to 3.6 V for Program, Erase and
Read Operations
–V
PP = 12 V for Fast Program and Fast
Erase
■TWO INTERFACES
– Firmware Hub (FWH) Interface for
embedded operation with PC Chipsets
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility
■FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
supporting Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write
Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Multi-byte Read Operation (4/16 /128-
byte)
– Synchronized with 33 MHz PCI clock
■BYTE PROGRAMMING TIME
– Single Byte Mode: 10µs (typical)
– Quadruple Byte Mode: 2.5µs (typical)
■32 UNIFORM 64 Kbyte MEMORY BLOCKS
■PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase
Suspend
■FOR USE in PC BIOS AP PLICATION S
■ELECTRONIC SIGNATURE
– Manufa cture r Code: 20h
– Device Code: 2Eh
Figure 1. Package
TSOP40 (N)
10 x 20mm
M50FW016
2/45
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Communications (FWH0-FWH3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FWH Bus Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. FWH Bus Read Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. FWH Bus Read Waveforms (Single Byte Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. FWH Bus Write Field Definitions (Single Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. FWH Bus Write Waveforms (Single Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. FWH Bus Write Field Definitions (Quadruple Byte Program) . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. FWH Bus Write Waveforms (Quadruple Byte Program) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Manufacturer and Device Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Quadruple Byte Program Command (A/A Mux Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Quadruple Byte Program Command (FWH Mode).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 22
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M50FW016
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Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Multi-Byte Read/Write Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 15. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. A/A Mux Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. A/A Mux Interface AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 26. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 35
Table 27. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 35
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 38
Figure 18.Quadruple Byte Program Flowchart and Pseudo Code (FWH Interface Only) . . . . . . . . 39
Figure 19.Program Suspend and Resume Flowchart, and Pseudo Code. . . . . . . . . . . . . . . . . . . . 40
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Figure 20.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 41
Figure 21.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22.Erase Suspend and Resume Flowchart, and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . 43
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
M50FW016
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SUMMARY D ESCRIPTION
The M50FW016 is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing, an
optional 1 2V power supp ly ca n be us ed to re duce
the programming and the erasing times.
The memory is divided into blocks that can be
erased independen tly s o it is po ss i ble to p re se rve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memor y.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two differen t bus inte rfaces are suppor ted by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW016 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplex ed (o r A/A M ux) Inter face, is de signe d to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
package a nd it is s upplied with al l the bits erased
(set to ’1’).
Figure 2. Logic Diagram (FWH Interface) Table 1. Signal Names (FWH Interface)
AI04462
4
FWH4
FWH0-
FWH3
VCC
M50FW016
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID3
FGPI0-
FGPI4
VPP
FWH0-FWH3 Input/O utp ut Co mm u nic atio ns
FWH4 Input Communication Frame
ID0-ID3 Identification Inputs
FGPI0-FGPI4 General Purpose Inputs
IC Interface Configuration
RP Interface Reset
INIT CPU Re se t
CLK Clock
TBL Top Block Lock
WP Write Protect
RFU Reserved for Future Use. Leave
disconnected.
VCC Supply Voltage
VPP Optional Supply Voltage for Fast
Program and Fast Erase Operations
VSS Ground
NC Not Connected Internally
RFU Reserved for Future Use
7/45
M50FW016
Figure 3. Logic Diagram (A/A Mux Interface) Table 2. Signal Names (A/A Mux Interface)
Figure 4. TSOP Connections
AI04463
11
RC
DQ0-DQ7
VCC
M50FW016
IC
VSS
8
G
W
RB
RP
A0-A10
VPP
IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
GOutput En ab le
WWrite Enable
RC Row/Co lum n Ad dre ss Sele ct
RB Ready/B us y Ou tpu t
RP Interface Reset
VCC Supply Voltage
VPP Optional Supply Voltage for Fast
Program and Fast Erase
Operations
VSS Ground
NC Not Connected Internally
RFU Reserved for Future Use
AI04464b
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
VSS
RFU
DQ7
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1
FWH2
FGPI3
TBL ID2
FGPI0
WP
NC
RFU
NC
IC (VIL)
RFU
FGPI4
NC
VSS
FWH4
RFU
FWH3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50FW016
10
1
11
20 21
30
31
40
ID3
NC INIT
NC RFU
FGPI2 FWH0
FGPI1 ID0
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC
M50FW016
8/45
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH ) Signal Descripti ons section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions se cti on bel ow.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
2., Logic Diagram (FWH Interface), and Table
1., Signal Names (FWH Interface).
Input/Output Communications (FWH0-FWH3). All
Input and Output Communication with the memory
take pla ce on th es e pin s. Addr es ses an d Data fo r
Bus Read a nd Bus Wri te operation s are encod ed
on these pins.
Input Communication Frame (FWH4). The In-
put Communication Frame (FWH4) signals the
start of a bus operatio n. When In put Communica -
tion Frame is Low, VIL, on the rising edge of the
Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the op erati on is ab orted . When In-
put Communication Frame is High, VIH, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The
Identification Inputs select the address that the
memory responds to. Up to 16 memories can be
addressed on a bus. For an address bit to be ‘0’
the pin can be left floating or driven Low, VIL; an
internal pull-down resistor is included with a value
of RIL. For an address bit to be ‘1’ the pin must be
driven High, VIH; there will be a leakage current of
ILI2 through each pin when pulled to VIH; see Table
21.
By convention the boot memory must have
address ‘0000’ and all additional memories take
sequential addresses starting from ‘0001’.
By convention the boot memory must have ID0-
ID3 pins left floating or driven Low, VIL and a ‘1’
value on A21, A23-A25 and all additional
memories take sequential ID0-ID3 configuration.
General Purpose Inputs (FGPI0-FGPI4). The Ge n-
eral Purpose Inputs can be used as digital inputs
for the CPU to read. The General Purpose Input
Register holds the values o n these pins . The pins
must hav e st a ble da ta from befo re th e s tart of the
cycle that reads the General Purpose Input Regis-
ter until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
VIL, or High, VIH.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Int er fac e is us ed . Th e chos e n in terf ace mus t
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplex ed (A /A Mux) In terface th e pin sh ould be
driven High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
cu rrent of ILI2 through each pin when pulled to VIH;
see Table 21.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the ou tput s are put to h igh imped ance a nd
the current consumption is minimized. When RP is
set Hi gh, VIH, t he memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the inter nal Reset line i s the logical OR (el ectric al
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock
input is used to prevent the Top Block (Block 31)
from being ch anged. When T op Block Lock , TBL,
is set Low, VIL, Program and Block Erase
operations in the Top Block have no effect,
regardless of the state of the Lock Register. When
Top Block Lock, TBL, is set High, VIH, the
protection of the Block is determined by the Lock
Register . The state o f Top Block L ock, TBL, does
not affect the protection of the Main Blocks (Blocks
0 to 30).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the M ain Blocks (Blocks 0 to 30 )
from being changed. When Write Protect, WP, is
set Low, VIL, Program and Block Erase operations
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
9/45
M50FW016
WP, is set High, VIH, the protection of the Block
determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 31).
Write Protect, WP, must be set prior to a Program
or Block Er ase operati on is initiate d and must not
be changed until the operation completes or un-
pred ictable re sults may occur. Care sh ould be tak-
en to avoid unpredictable behavior by changing
WP during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have as signed functi ons in th is rev ision of the
part. They must be left disconnected.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 3., Logic Diagram (A/A Mux
Interface), and Table 2., Signal Names (A/A Mux
Interface).
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A20). They are
latched du r ing any bu s operation by the Row / Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the command s sent to the Comma nd Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Writ e En a bl e, W , controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row
Address bits (A0-A10) or the Column Address bits
(A11-A20). The Row Address bits are latched on
the falling edge of RC whereas the Column
Address bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase
Suspend command. When Ready/Busy is High,
VOH, the mem or y is r ead y for an y Read , P ro gram
or Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the
memory contents being altered will be invalid.
After VCC becomes valid the Command Interface
is reset to Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply V oltage pin s and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents
required during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast
Program (see the Quadruple Byte Program
Command descr iption) and Fast Erase options of
the memory and to protect the memory. When VPP
< VPPLK Program and Erase operations cannot be
performed and an error is reported in the Status
Register if an attempt to change the memory
conten ts is made . Whe n VPP = VCC Progra m and
Erase operations take place as normal. When VPP
= VPPH Fast Program operations (using the
Quadruple Byte Program command, 30h, from
Table 10.) and Fast Erase operations are used.
Any other voltage input to VPP will result in
undefined behavior and should not be used.
VPP should not be set to VPPH for more than 80
hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt -
age measure men ts.
M50FW016
10/45
Table 3. Block Addresses
Size
(Kbytes) Address Range Block
Number Block Type
64 1F0000 h- 1F FFFFh 31 Top Blo ck
64 1E0000h-1EFFFFh 30 Main Block
64 1D0000h-1DFFFFh 29 Main Block
64 1C0000h-1CFFFFh 28 Main Block
64 1B0000h-1BFFFFh 27 Main Block
64 1A0000h-1AFFFFh 26 Main Block
64 190000h-19FFFFh 25 Main Block
64 180000h-18FFFFh 24 Main Block
64 170000h-17FFFFh 23 Main Block
64 160000h-16FFFFh 22 Main Block
64 150000h-15FFFFh 21 Main Block
64 140000h-14FFFFh 20 Main Block
64 130000h-13FFFFh 19 Main Block
64 120000h-12FFFFh 18 Main Block
64 110000h-11FFFFh 17 Main Block
64 100000h-10FFFFh 16 Main Block
64 0F0000h-0FFFFFh 15 Main Block
64 0E0000h-0EFFFFh 14 Main Block
64 0D0000h-0DFFFFh 13 Main Block
64 0C0000h-0CFFFFh 12 Main Block
64 0B0000h-0BFFFFh 11 Main Block
64 0A0000h-0AFFFFh 10 Main Block
64 090000h-09FFFFh 9 Main Block
64 080000h-08FFFFh 8 Main Block
64 070000h-07FFFFh 7 Main Block
64 060000h-06FFFFh 6 Main Block
64 050000h-05FFFFh 5 Main Block
64 040000h-04FFFFh 4 Main Block
64 030000h-03FFFFh 3 Main Block
64 020000h-02FFFFh 2 Main Block
64 010000h-01FFFFh 1 Main Block
64 000000h-00FFFFh 0 Main Block
11/45
M50FW016
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Firmware Hub (FWH) Interface is the usual
interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/
Address Multiplexed (A/A Mux) Interface.
Follow the section Firmware Hub (FWH) Bus
Operations below and the section Address/
Address Multiplexed (A/A Mux) Bus Operations
below for a description of the bus operations on
each interface.
Firmware Hub (FWH) Bus Operations
The Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FW H3), one control line
(FWH4) and a clock (CLK). In addition protection
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (R P and INIT)
are available to put the memory into a known
state.
The data signals, control signal and clock are
designed to be compatible with PCI electrical
specifications. The interface operates with clock
speeds up to 33MHz.
The following operations can be performed using
the appropr iate bus cycles : Bus Read, Bus Wri te,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Fi rmware Hub Regis ters. A valid Bu s
Read operati on star ts when Inp ut Communicati on
Frame, FWH4, is Low , VIL, as Clock rises and the
correct Start cycle is on FWH0-FWH3. On the
following clock cycles the Host will send the
Memory ID Selec t, Address and other contro l bits
on FWH0-FWH3. The memory responds by
outputting Sync data until the wait-states have
elapsed followed by Data0-Data3 and Data4-
Data7.
Refer to Table 4., FWH Bus Read Field Defini-
tions, and Figure 5., FWH Bus Read Waveforms
(Single Byte Read), for a description of the Field
definitions for each clock cycle of the transfer. See
Table 23., FWH Inte rf ace AC Signa l T iming Char -
acteristics and Figur e 11., FWH Inte rfac e AC Sig-
nal Timing Waveforms, for details on the timings of
the signals.
FWH Bus Write. Bus Write operations write to
the Command Interface or Firmware Hub
Registers. A valid Bus Write operation starts when
Input Communication Frame, FWH4, is Low, VIL,
as Clock rises and the correct Start cycle is on
FWH0-FWH3. On the following Clock cycles the
Host will send the Memory ID Select, Address,
other control bits, Data0-Data3 and Data4-Data7
on FWH0-F WH3. The memor y outputs Syn c data
until the wait-states have elapsed.
Refer to Table 5., FWH Bus Write Field Definitions
(Single Byte), and Figure 6., FWH Bus Write
Waveforms (Single Byte), for a description of the
Field definitions for each clock cycle of the
transfer. S ee Tabl e 2 3., FWH Inter fa ce AC Si gn al
Timing Characteristics, and Figure 11., FWH
Interface AC Signal Timing Waveforms, for details
on the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immedi ately abort t he current b us operation. A
Bus Abo rt occurs when F WH4 is dr iven Low , VIL,
during th e bu s oper at ion ; the memory wi ll tri- st ate
the Input/Output Communication pins, FWH0-
FWH3.
Note that, during a Bus Write operation, the
Command Interface starts executing the
comma nd as soon as the data is fully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.
Standby. When FWH4 is High, VIH, the memory
is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply
Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interfac e Res et, RP, or CP U
Reset, INIT, i s Low, VIL. RP or INIT m ust be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default state s regardless
of their sta te before Res et, see Table 13. If RP or
INIT goes Low, VIL, during a Program or Erase
operation, the operation is aborted and the
memory cells affected no longer contain valid
data; the m emory can take up to tPLRH to abort a
Program or Erase operation.
Block Protection. Block Protection can be
forc ed usin g the sig nals To p Block Lo ck, TBL, and
Write Protect, WP, regardless of the state of the
Lock Regis ter s.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux)
Interface has a more traditional style interface.
The signals consist of a multiplexed address
signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional
signal, RP, can be used to reset the memory.
The Address/Address Multiplexed (A/A Mux)
Interface is included for use by Flash
Programming equipment for faster factory
M50FW016
12/45
programming. Only a subset of the features
available to the Firmware Hub (FWH) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropr iate bus cycles : Bus Read, Bus Wri te,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read. Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then
Write Enable (W) and Interface Reset (RP) must
be High, VIH, and Output Enable, G, Low, VIL, in
order to per form a B us Rea d operati on. T he Data
Inputs/Outputs will output the value, see Figure
13., A/A Mux Interface Rea d AC Waveform s, and
Table 25., A/A Mux Interface Read AC
Characteristics, for details of when the output
becomes va li d.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC. The data should be set up on
the Data Inputs/Outputs; Output Enable, G, and
Interface Re set, R P, must be High, VIH and Write
Enable, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write
Enable, W. See Figure 14., A/A Mux Interface
Write AC Waveforms, and Table 26., A/A Mux
Interface Write AC Characteristics, for details of
the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode wh en RP is Low, VIL. RP mus t be
held Low, VIL for tPLPH. If RP is goes Low, VIL,
during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to tPLRH to abort a Program or Erase operation.
13/45
M50FW016
Table 4. FWH Bus Read Field Definitions
Note: 1. Clock Cycle Number = (2MSIZE –1)*2+18
2. Clock Cycle Number = (2MSIZE –1)*2+19
Figure 5. FWH Bus Read Waveforms (Single Byte Read)
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1101b I On the rising ed ge of CL K with FWH 4 Lo w, the contents of
FWH0-F WH 3 ind ica te the start of a FWH Re ad cycle .
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is bei ng addr ess ed .
3-9 7 ADDR XXXX I
A 28-bit address phase is transferred starting with the most
significant nibble first. For the multi-byte read operation, the
least signif ica nt bits (MSI ZE of them ) are tre ate d as Do n't
Care, and the read operation is started with each of these
bits reset to 0.
10 1 MSIZE 0XXXb I
This one clock cycle is driven by the host to determine how
many bytes will be transferred. M50FW016 will support:
sing le byt e tran sfer (0000b ), 4- byte t ransf er (00 10b), 16-byte
transfer (0100b) and 128-byte transfer (0111b).
11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
12 1 TAR 1111b
(float) OThe FWH Flash Me mo ry takes contr ol of FW H0 -F WH 3
during this cycle.
13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b
(sho rt wai t-syn c) for two clo ck cycl es, in dicat ing th at the d ata
is not yet available. Two wait-states are always included.
15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least
significant nibble. If multi-byte read operation is
enabled, repeat cycle 16-17 n times, where n = 2MSIZE –1
Note 1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to
indicate a turnaround cycle.
Note 2 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs, the host takes
control of FWH0-FWH3.
AI03437
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE TAR SYNC DATA TAR
11712322
M50FW016
14/45
Table 5. FWH Bus Write Field Definitions ( Single Byte)
Figure 6. FWH Bus Write Waveforms (S ingle Byt e)
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1110b I On the rising ed ge of CL K with FWH 4 Lo w, the contents of
FWH0-F WH 3 ind ica te the start of a FWH Writ e Cyc le.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is bei ng addr ess ed .
3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most
significa nt nib ble first.
10 1 MSIZE 0000b I Always 0000b (single byte transfer).
11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant
nibble.
13 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
14 1 TAR 1111b
(float) OThe FWH Flash Me mo ry takes contr ol of FW H0 -F WH 3
during this cycle.
15 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
16 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
17 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
AI03441
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
11712212
15/45
M50FW016
Table 6. FWH Bus Write Field Definitions (Quadruple Byte Program)
Figure 7. FWH Bus Write Waveforms (Quadruple Byte Program)
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1110b I On the rising ed ge of CL K with FWH 4 Lo w, the contents of
FWH0-F WH 3 ind ica te the start of a FWH Writ e Cyc le.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is bei ng addr ess ed .
3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most
significant nibble first. The A1-A0 lines are treated as Don't
Care.
10 1 MSIZE 0010b I Always 0010b (quadruple byte transfer).
11-18 8 DATA XXXX I
Data transfer is two cycles, starting with the least significant
nibble. (The first pair of nibbles is that at the address with A1-
A0 set to 00, the second pair with A1-A0 set to 01, the third
pair with A1-A0 set to 10, and the fourth pair with A1-A0 set
to 11.)
19 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
20 1 TAR 1111b
(float) OThe FWH Flash Me mo ry takes contr ol of FW H0 -F WH 3
during this cycle.
21 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
22 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
23 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
AI05784
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
11718212
M50FW016
16/45
Table 7. A/A Mux Bus Operations
Table 8. Manufacturer and Device Codes
Operation G WRP VPP DQ7-DQ0
Bus Read VIL VIH VIH Don't Care Data Output
Bus Write VIH VIL VIH VCC or VPPH Data Input
Output Dis ab le VIH VIH VIH Don't Care Hi-Z
Reset VIL or VIH VIL or VIH VIL Don't Care Hi-Z
Operation G WRP A20-A1 A0 DQ7-DQ0
Manufacturer Code VIL VIH VIH VIL VIL 20h
Device Code VIL VIH VIH VIL VIH 2Eh
17/45
M50FW016
COMMAND INTERFACE
All Bus Write operations to the memory are
interpreted by the Command Interface.
Commands consist of one or more sequential Bus
Write operations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table
10., Commands. Refer to Table 10. in conjunction
with the text descriptions below.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM . One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Re ad mode . Onc e the com mand i s is-
sued the memory re mains in Rea d mo de until an -
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read Sta-
tus Register co mmand is us ed to read the S tatus
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
comma nd is is sued s ubsequen t Bu s Read opera -
tions read the Status Register until another com-
mand is issued. See the section on the STATUS
REGISTER for details on the definitions of the Sta-
tus Register bits.
Read Ele ctronic Sig natur e Comma nd. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read
Electronic Signature command. Once the
command is issued subsequent Bus Read
operations read the Manufacturer Code or the
Device Code until another command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be rea d us in g B us Read ope ra tio ns usi ng the
addresses in Table 9.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the address and
data in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued s ub se que nt B us Re ad o perations re ad the
Status Register. See t he section on the STATUS
REGISTER for details on the definitions of the
Status Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the
memory arr ay will not be ch anged and the S tatus
Register will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other comm and s wil l be igno red. T yp ical P ro gram
times are given in Table 15.
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cau se any modi ficat ion on it s value. One of th e
Erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 16., Program Flowchart and Pseudo
Code, for a suggested flowchart on using the
Program command.
Quadruple Byte Program Command (A/A Mux
Mode). The Quadruple Byte Program Command
can be used to program four adjacent bytes in the
memory array at a time. The four bytes must differ
only for the addresses A0 and A1. Programming
should not be attempted when VPP is not at VPPH.
Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued sub seque nt Bus Read operat ion s read the
Status Register. See t he section on the STATUS
REGISTER for details on the definitions of the
Status Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Rea d Status regi ster
comma nd and the Prog ram/Erase S uspend com-
mand. All other commands will be ignored. Typical
Qua druple Byte Program times are give n in Table
15..
Note that the Quad ruple Byte Progra m command
cannot change a bit set to ‘0’ back to ‘1’ and
attempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figu re 17., for a suggested flowchart on using
the Quadruple Byte Program command.
Quadruple Byte Program Command (FWH
Mode). The Quadruple Byte Program Command
can be used to program four adjacent bytes in the
memory array at a time. The four bytes must differ
only for the addresses A0 and A1. Programming
should not be attempted when VPP is not at VPPH.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
M50FW016
18/45
start address and four data bytes in the internal
state machine and starts the Program/Erase
Controller. Once the command is issued
subseque nt Bus Read ope rations read t he Statu s
Register. See the section on the STATUS
REGISTER for details on the definitions of the
Status Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Rea d Status regi ster
comma nd and the Prog ram/Erase S uspend com-
mand. All other commands will be ignored. Typical
Qua druple Byte Program times are given in Table
15.
Note that the Quad ruple Byte Progra m command
cannot change a bit set to ‘0’ back to ‘1’ and
attempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figu re 18., for a suggested flowchart on using
the Quadruple Byte Program command.
Chip Erase Command. The Chip Erase Com-
mand can be only used in A/A Mux mode to erase
the entire chip at a time. Erasing should not be at-
tempted when VPP is not at VPPH. The operation
can also be executed if VPP is below VPPH, but re-
sult could be uncertain. Two Bus Write operations
are required to issue the command and start the
Program/Erase Controller. Once the command is
issued s ub se que nt B us Re ad o perations re ad the
Status Register. See t he section on the STATUS
REGISTER for details on the definitions of the Sta-
tus Register bits. During the Chip Erase operation
the memory will only accept the Read Status Reg-
ister command. All other commands will be ig-
nored. Typical Chip Erase times are given in Table
15. The Chip Erase command sets all of the bits in
the memory to ‘1’. See Figure 20., Chip Erase
Flowchart and Pseudo Code (A/A Mux Interface
Only), for a suggested flowchart on using the Chip
Erase command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Wr it e cy cle latches the block addr es s
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See t he section on the STATUS
REGISTER for details on the definitions of the Sta-
tus Register bits.
If the block is protected then the Block Erase
operation will abort, the data in the block will not be
changed and the Status Register will output the
error.
During the Bl ock Er ase o per at ion the memory wil l
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 15.
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
See Figure 21., Block Erase Flowchart and
Pseudo Cod e, for a su ggeste d flowc hart on usi ng
the Erase command.
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the mem-
ory ret urns to its previous mode, subseq uent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
Program/ Erase Suspend Command. The Pro-
gram/Erase Suspend command can be used to
pause a Program or Block Erase operation. One
Bus Write c ycle is requ ired to issue th e Program/
Erase Suspend command and pause the Pro-
gram/Erase Controller. Once the command is is-
sued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/
Erase Controller has paused; no other commands
will be accepte d until the Program/E rase Control-
ler has pau sed. After the Program /Erase Control -
ler has paused, the memory will continue to output
the Status Register until another command is is-
sued.
During the polling period between issuing the
Program/Erase Suspend command and the
Program/Erase Controller pausing it is possible for
the operation to complete. Once Program/Erase
Controller Status bit indicates that the Program/
Erase Contro ller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to determine if the operation has
completed or is suspended. For timing on the
delay between issuing the Program/Erase
Suspend command and the Program/Erase
Controller pausing see Table 15.
During Program/Erase Suspend the Read
Memory Array, Read Status Register, Read
Electroni c Sign ature and P rogram /Eras e Resu me
commands will be accepted by the Command
Interface . A ddi tiona lly , if the s us pen ded op er ati on
was Bloc k Erase th en the Progr am comm and will
also be accepted; only the blocks not being erased
may be read or programmed correctly.
19/45
M50FW016
See Figure 19., Program Suspend and Resume
Flowchart, and Pseudo Code, and Figure
22., Erase Suspend and Resume Flowchart, and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command ca n be us ed to re-
start the Program/Erase Controller after a
Program/Erase Su spend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume co mma nd. On ce the comma nd is issu ed
subseque nt Bus Read ope rations read t he Statu s
Register.
Table 9. Read Electronic Signature
Table 10. Commands
Note: X Don’t Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Address es, BA Any addres s in t he Block.
Read Memor y Arra y . After a Read Memory Array command , read the memory as normal until ano the r co mmand is issued.
Read St atu s Register. A fter a Read St atus Regist er command, read the St atus Registe r as normal until ano th er command is issued.
Read E l e c t r on ic Signatu re. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-
mand is issued .
Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-
sued.
Quadruple Byte Program (A/A Mux Mode). Addresses A 1, A2, A3 and A4 must be consecutive addresses differing only for address
bit A0 and A1. After this command, the user should repeatedly read the Status Register until the command has completed, at which
point another command can be issu ed.
Quadruple Byte Program (FWH Mo de). Aqbp is the start address, A1 and A0 are treated as Don’t Care. The first data byte is pro-
grammed at the address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that has A1-
A0 at 10, and t he fourt h at th e addr ess that has A1-A0 at 11. After this command, the user sho uld repeat edly read the St atus Register
until the command has completed, at which point another command can be issued.
Chip Erase . This command is o nly valid in A/A Mu x mode. A fter this command re ad the Stat us Reg ister unt il the c ommand c omplet es
and another command is issue d.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Prog ram/Erase Suspend command has been accept ed, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Eras e resume commands.
Prog ram/Era se Resu me. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Regis ter until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.
Code Address Data
Manufacturer Code 00000h 20h
Device Co de 00001h 2Eh
Command
Cycles
Bus Write Operations
1st 2nd 3rd 4th 5th
Addr Data Addr Data Addr Data Addr Data Addr Data
Read Memory Array 1 X FFh
Read Status Register 1 X 70h
Read Electronic Signature 1X 90h
1X 98h
Program 2X 40hPA PD
2X 10hPA PD
Quadruple Byte Program
(A/A Mux Mod e) 5X 30hA1PD A2PD A3PD A4PD
Quadruple Byte Program
(FWH Mode) 2X 30h
Aqbp PDqbp
Chip Erase 2 X 80h X 10h
Block Erase 2 X 20h BA D0h
Clear Status Register 1 X 50h
Program/Eras e Su spe nd 1 X B0 h
Program /E r as e Re sum e 1 X D0h
Invalid/Reserved
1X 00h
1X 01h
1X 60h
1X2Fh
1XC0h
M50FW016
20/45
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.
To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. T he Statu s Register can be read from
any address.
The Status Regis te r bits ar e su mma ri zed in Table
11., Status Register Bits. Refer to Table 11. in
conjunction with the text descriptions below.
Program/Er ase Controller Stat us (Bit 7). The Pro-
gr a m/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Pro gram/Eras e Controll er Status is ‘0’ imme -
diately afte r a Prog ram/Er ase Suspe nd comma nd
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the en d of the op erati on. T he othe r bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and B lock Pr otection Status b its sh ould be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Sta tus bi t in dic at es that a Bl oc k E ras e op er -
ation has been suspended and is waiting to be
resumed . The Erase Suspe nd Status shoul d only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Eras e Sus pe nd Sta tus bit is ‘0’ the Pro -
gram/Erase Controller is active o r has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctl y; when the Er ase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of p ulses to t he block(s) and still faile d to
verify that the block(s) has erased correctly.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, othe rwise the new command will appea r to
fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong
command sequence has been attempted).
Program Status (Bit 4). The Program Status bit
can b e used to iden tify if the memor y ha s app lied
the maximum number of program pulses to the
byte an d still failed to verify that th e byte has p ro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to v erify that the byte h as pr ogram med cor -
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong
command sequence has been attempted).
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage o n the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Inde terminate res ults can oc-
cur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was samp le d at a va li d vol tage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase opera-
tion cannot be performed. (The VPP status bit is ‘1’
if a Quadruple Byte Program command is issued
and the VPP signal has a voltage less than VPPH
applied to it.)
Once the VPP Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
21/45
M50FW016
hardware reset. If it is set to ‘1’ it s hould be reset
before a new Program or Erase command is is-
sued, othe rwise the new command will appea r to
fail.
Program Suspend Status (Bit 2). The Program
Susp en d S t at us bi t i ndicates that a Pr og r am o pe r-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
su me command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection St atus bit is to ‘0’ no P rogram or Block
Erase operations have been attempted to protect-
ed blocks since the last Clear Status Register
command or hardware reset; when the Block Pro-
tection S tatus bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1 ’ the Block Pr otect ion Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
Using the A/A Mux Interface the B lock Protecti on
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 11. Status Register Bits
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwis e Bit 6 is ‘0’.
Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Program active ‘0’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’
Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘0’ ‘1’ ‘0’ ‘0’
Program failure due to Block Protection (FWH Interface only) ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘1’
Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Block Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase failure due to VPP Error ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’
Block Erase failure due to Block Protection (FWH Interface
only) ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’
Erase failure due to failed cell(s) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’
M50FW016
22/45
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS
When the Firmware Hub Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the
Blocks, read the General Purpose Input pins and
identify the memory using the Electronic Signature
codes. See Table 12. for the memory map of the
Configuration Registers in the FWH Protocol.
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bi t is set, ‘1’, f urther m odific ation s
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 13. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
When VPP is less than VPPLK all blocks are pro-
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is L ow, V IL, then the To p Block (Block 3 1) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 30) are write protected and
cannot be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(f rom Rea d mode ). Wh en the R ead Lo ck Bit is set ,
‘1’, the bloc k is read pr otecte d; any opera tion that
attempts to read the contents of the block will read
00h instead. W hen the Re ad Loc k B it is r es et, ‘0 ’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanis m for pr otecti ng s oftwa re data fr om sim-
ple ha cking and ma licious a ttack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be perform ed. A rese t or pow er -up is requir ed be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Firmware Hub (FWH) General Purpose Input
Register
The Firm ware Hub ( FWH) Ge neral Purpos e Input
Register holds the state of the Firmware Hub Inter-
face General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface Gener-
al Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the manuf acturer co de for the memor y. The man -
ufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code Register
Reading the Device Code Register returns the de-
vice code for the memory, 2Eh. This register is
read-only and writing to it has no effect.
Multi-Byte Read/Write Configuration Registers
The Multi-Byte Read/Write Configuration Regis-
ters contain information as which multi-byte read
and write access sizes will be accepted. The
M50FW016 supports 4/16/128-byte reading and
4-byte writing.
23/45
M50FW016
Table 12. Firmware Hub Register Configuration Map
Mnemonic Register Name Memory
Address Default
Value Access
T_BLOCK_LK Top Block Lock Register (Block 31) FBF0002h 01h R/W
T_MINUS01_LK Top Block [-1] Lock Register (Block 30) FBE0002h 01h R/W
T_MINUS02_LK Top Block [-2] Lock Register (Block 29) FBD0002h 01h R/W
T_MINUS03_LK Top Block [-3] Lock Register (Block 28) FBC0002h 01h R/W
T_MINUS04_LK Top Block [-4] Lock Register (Block 27) FBB0002h 01h R/W
T_MINUS05_LK Top Block [-5] Lock Register (Block 26) FBA0002h 01h R/W
T_MINUS06_LK Top Block [-6] Lock Register (Block 25) FB90002h 01h R/W
T_MINUS07_LK Top Block [-7] Lock Register (Block 24) FB80002h 01h R/W
T_MINUS08_LK Top Block [-8] Lock Register (Block 23) FB70002h 01h R/W
T_MINUS09_LK Top Block [-9] Lock Register (Block 22) FB60002h 01h R/W
T_MINUS10_LK Top Block [-10] Lock Register (Block 21) FB50002h 01h R/W
T_MINUS11_LK Top Block [-11] Lock Register (Block 20) FB40002h 01h R/W
T_MINUS12_LK Top Block [-12] Lock Register (Block 19) FB30002h 01h R/W
T_MINUS13_LK Top Block [-13] Lock Register (Block 18) FB20002h 01h R/W
T_MINUS14_LK Top Block [-14] Lock Register (Block 17) FB10002h 01h R/W
T_MINUS15_LK Top Block [-15] Lock Register (Block 16) FB00002h 01h R/W
T_MINUS16_LK Top Block [-16] Lock Register (Block 15) FAF0002h 01h R/W
T_MINUS17_LK Top Block [-17] Lock Register (Block 14) FAE0002h 01h R/W
T_MINUS18_LK Top Block [-18] Lock Register (Block 13) FAD0002h 01h R/W
T_MINUS19_LK Top Block [-19] Lock Register (Block 12) FAC0002h 01h R/W
T_MINUS20_LK Top Block [-20] Lock Register (Block 11) FAB0002h 01h R/W
T_MINUS21_LK Top Block [-21] Lock Register (Block 10) FAA0002h 01h R/W
T_MINUS22_LK Top Block [-22] Lock Register (Block 9) FA90002h 01h R/W
T_MINUS23_LK Top Block [-23] Lock Register (Block 8) FA80002h 01h R/W
T_MINUS24_LK Top Block [-24] Lock Register (Block 7) FA70002h 01h R/W
T_MINUS25_LK Top Block [-25] Lock Register (Block 6) FA60002h 01h R/W
T_MINUS26_LK Top Block [-26] Lock Register (Block 5) FA50002h 01h R/W
T_MINUS27_LK Top Block [-27] Lock Register (Block 4) FA40002h 01h R/W
T_MINUS28_LK Top Block [-28] Lock Register (Block 3) FA30002h 01h R/W
T_MINUS29_LK Top Block [-29] Lock Register (Block 2) FA20002h 01h R/W
T_MINUS30_LK Top Block [-30] Lock Register (Block 1) FA10002h 01h R/W
T_MINUS31_LK Top Block [-31] Lock Register (Block 0) FA00002h 01h R/W
FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R
MANUF_REG Manufacturer Code Register FBC0000h 20h R
DEV_REG Device Code Register FBC0001h 2Eh R
MBR_REG_LB Multi-Byte Read Configuration Register (Low Byte) FBC0005h 4Ah R
MBR_REG_HB Multi-Byte Read Configuration Register (High Byte) FBC0006h 00h R
MBW_REG_LB Multi-Byte Write Configuration Register (Low Byte) FBC0007h 02h R
MBW_REG_HB Multi-Byte Write Configuration Register (High Byte) FBC0008h 00h R
M50FW016
24/45
Table 13. Lock Register Bit Definitions
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-31] Lock
Register (T_MI NUS31_LK).
Table 14. General Purpose Input Register Definition
Note: 1 . Applies to the General Purpose Input Register (FGPI_REG).
Bit Bit Name Value Function
7-3 Reserved
2 Read-Lock ‘1’ Bus Read operations in this Block always return 00h.
‘0’ Bus read operations in this Block return the Memory Array contents. (Default
value).
1 Lock-Down ‘1’ Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
0Write-Lock ‘1’ Program and Block Erase operations in this Block will set an error in the Status
Register. The memory contents will not be changed. (Default value).
‘0’ Program and Block Erase operations in this Block are executed and will modify the
Block contents.
Bit Bit Name Value Function
7-5 Reserved
4 FGPI4 ‘1’ Input Pin FGPI4 is at VIH
‘0’ Input Pin FGPI4 is at VIL
3 FGPI3 ‘1’ Input Pin FGPI3 is at VIH
‘0’ Input Pin FGPI3 is at VIL
2 FGPI2 ‘1’ Input Pin FGPI2 is at VIH
‘0’ Input Pin FGPI2 is at VIL
1 FGPI1 ‘1’ Input Pin FGPI1 is at VIH
‘0’ Input Pin FGPI1 is at VIL
0 FGPI0 ‘1’ Input Pin FGPI0 is at VIH
‘0’ Input Pin FGPI0 is at VIL
25/45
M50FW016
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table
15.
Table 15. Program and Erase Times
Note: 1. TA = 25°C, VCC = 3.3V
2. This time is obtained executing the Quadruple Byte Program Command.
3. Sampled only, not 100% tested.
4. Time to pr ogram four bytes.
Parameter Interface Test Condition Min Typ (1) Max Unit
Byte Progr am 10 200 µs
Quadruple Byte Program VPP = 12V ± 5% 10 (4) 200 µs
Chip Erase A/A Mux VPP = 12V ± 5% 18 s
Block Program A/A Mux VPP = 12V ± 5% 0.1 (2) 5s
VPP = VCC 0.4 5 s
Block Erase VPP = 12V ± 5% 0.75 8 s
VPP = VCC 110s
Program/Erase Suspend to Program pause (3) 5µs
Program/Erase Suspend to Block Erase pause (3) 30 µs
M50FW016
26/45
MAXIMUM RATING
Stressing the dev ice above the ratin g lis ted in the
Absolute Maximum Ratin gs table ma y cause pe r-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other cond itions above thos e indicated i n the
Operating sections of this specification is not im-
plie d. Exposu re to Abso lute Max imum Rat ing con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 16. Absolute Maximum Ratings
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Rest rictions on Hazardous Substances (RoHS) 2002/95/EU.
2. Minimum Voltage may undershoot to –2 V, for less than 20 ns, during transitions. Maximum Voltage may oversh oot to VCC+2V , for
less than 20 ns, during transitions.
Symbol Parameter Min Max Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1
VIO (2) Input or Output Voltage –0.6 VCC + 0.6 V
VCC Supply Voltage –0.6 4 V
VPP Program Voltage –0.6 13 V
27/45
M50FW016
DC AND AC PARA METERS
This section summarizes the operating measure-
ment condi tions, an d the DC and AC characteri s-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 17., Table 18.
and Table 19. Designers should check that the op-
erating conditions in their circuit match the operat-
ing conditions when relying on the quoted
parameters.
Table 17. Operating Conditions
Table 18. FWH Interface AC Measurement Conditions
Table 19. A/A Mux Interface AC Measurement Conditions
Figure 8. FWH Interface AC Testing Input Output Waveforms
Symbol Parameter Min Max Unit
TAAmbient Operating Temperature (Device Grade 1) 0 70 °C
Ambient Operating Temperature (Device Grade 5) –20 85 °C
VCC Supply Voltage 3 3.6 V
Parameter Value Unit
Load Capacitance (CL)10 pF
Input Rise and Fall Times ≤ 1.4 ns
Input Pulse Voltages 0.2 VCC and 0.6 VCC V
Input and Output Timing Ref. Voltages 0.4 VCC V
Parameter Value Unit
Load Capacitance (CL)30 pF
Input Rise and Fall Times ≤ 10 ns
Input Pulse Voltages 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 V
AI03404
0.6 VCC
0.2 VCC
0.4 VCC
IO > ILO
IO < ILO IO < ILO
Input and Output AC Testing Waveform
Output AC Tri-state Testing Waveform
M50FW016
28/45
Figure 9. A/A Mux Interface AC Testing Input Output Waveform
Table 20. Impedance
Note: 1 . Sampled only, not 100% tested.
2. S e e PCI Specific a ti o n.
Symb ol Parame te r Te st Co nd itio n Min Max Unit
CIN(1) Input Capacitance VIN = 0V 13 pF
CCLK(1) Clock Capacitanc e VIN = 0V 312pF
LPIN(2) Recommended Pin
Inductance 20 nH
AI01417
3V
0V
1.5V
29/45
M50FW016
Table 21. DC Characteristics
Note: 1 . Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
Symbol Parameter Interface Test Condition Min Max Unit
VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V
A/A Mux 0.7 VCC VCC + 0.3 V
VIL Input Low Voltage FWH –0.5 0.3 VCC V
A/A Mux -0.5 0.8 V
VIH(INIT)INIT Input High Voltage FWH 1.35 VCC + 0.5 V
VIL(INIT)INIT Input Low Voltage FWH –0.5 0.2 VCC V
ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA
ILI2 IC, IDx Input Leakage
Current IC, ID0, ID1, ID2, ID3 = VCC 200 µA
RIL IC, IDx Input Pull Low
Resistor 20 100 kΩ
VOH Output High Voltage FWH IOH = –500µA0.9 VCC V
A/A Mux IOH = –100µAVCC – 0.4 V
VOL Output Low Voltage FWH IOL = 1.5mA 0.1 VCC V
A/A Mux IOL = 1.8mA 0.45 V
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA
VPP1 VPP Voltage 33.6V
VPPH VPP Voltage (Fast
Program/Fast Erase) 11.4 12.6 V
VPPLK(1) VPP Lockout Voltage 1.5 V
VLKO(1) VCC Lockout Voltage 1.8 2.3 V
ICC1 Supply Current (Standby) FWH FWH4 = 0.9 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz 100 µA
ICC2 Supply Current (Standby) FWH FWH4 = 0.1 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz 10 mA
ICC3 Supply Current
(Any intern al ope ra tio n
active) FWH VCC = VCC max, VPP = VCC
f(CLK) = 33MHz
IOUT = 0mA 60 mA
ICC4 Supp ly Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA
ICC5(1) Supply Current
(Program/Erase) A/A Mux Program/Erase Controller Active 20 mA
IPP VPP Supply Current
(Read/Standby) VPP > VCC 400 µA
IPP1(1) VPP Supply Current
(Program /E ra se ac tive ) VPP = VCC 5µA
VPP = 12V ± 5% 15 mA
M50FW016
30/45
Figure 10. FWH Interface Clock Waveform
Table 22. FWH Interface Clock Characteristics
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.
Symbol Param et er Test Co nd itio n Value Unit
tCYC CLK Cycle Time(1) Min 30 ns
tHIGH CLK Hig h Time Min 11 ns
tLOW CLK Low Time Min 11 ns
CLK Slew Ra te peak to peak Min 1 V/ns
Max 4 V/ns
AI03403
tHIGH tLOW
0.6 VCC
tCYC
0.5 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.4 VCC, p-to-p
(minimum)
31/45
M50FW016
Figure 11. FWH Interface AC Signal Timing Waveforms
Table 23. FWH Interface AC Signal Timing Characteristics
Note: 1 . The timing measurement s for Active/F loat transit ions are defin ed when t he curr ent t hrough t he pi n equa ls the leakage current spec-
ification.
2. Applies to all inputs except CLK.
Symbol PCI
Symbol Parameter Test Condition Value Unit
tCHQV tVAL CLK to Data Out Min 2 ns
Max 11 ns
tCHQX(1) tON CLK to Active
(Float to Active Delay) Min 2 ns
tCHQZ tOFF CLK to Inactive
(Active to Float Delay) Max 28 ns
tAVCH
tDVCH tSU Input Set-up Time(2) Min 7 ns
tCHAX
tCHDX tHInput Hold Time(2) Min 0 ns
AI03405
tCHQV
tCHQX
tCHQZ
tCHDX
VALID
FWH0-FWH3
tDVCH
CLK
VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA
M50FW016
32/45
Figure 12. Reset AC Waveforms
Table 24. Reset AC Characteristics
Note: 1. See Chapter 4 of the PCI Specification.
Symbol Parameter Test Condition Value Unit
tPLPH RP or INIT Reset Pulse Width Min 100 ns
tPLRH RP or INIT Low to Reset Program/Erase Inactive Max 100 ns
Program/Erase Active Max 30 µs
RP or INIT Slew Rate(1) Rising edge only Min 50 mV/ns
tPHFL RP or INIT High to FWH4 Low FWH Interface only Min 30 µs
tPHWL
tPHGL RP High to Wr it e Enab le or Outp ut
Enable Lo w A/A Mux Interface only Min 50 µs
AI03420
RP, INIT
W, G, FWH4
tPLPH
RB
tPLRH
tPHWL, tPHGL, tPHFL
33/45
M50FW016
Figure 13. A/A Mux Interface Read AC Waveforms
Table 25. A/A Mux Interface Read AC Characteristics
Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.
Symbol Parameter Test Condition Value Unit
tAVAV Read Cycle Time Min 250 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC high Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tCHQV(1) RC High to Output Valid Max 150 ns
tGLQV(1) Output Enable Low to Output Valid Max 50 ns
tPHAV RP High to Row A ddress Valid Min 1 µs
tGLQX Output Enable Low to Output Transition Min 0 ns
tGHQZ Output Enable High to Output Hi-Z Max 50 ns
tGHQX Output Hold from Output Enable High Min 0 ns
AI03406
tAVAV
tCLAX tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID NEXT ADDR VALID
tAVCL tAVCH
M50FW016
34/45
Figure 14. A/A Mux Interface Write AC Waveforms
Table 26. A/A Mux Interface Write AC Characteristics
Note: 1 . Sampled only, not 100% tested.
2. A p pl i c a b l e i f VPP is seen as a logic input (VPP < 3.6V) .
Symbol Parameter Test Condition Value Unit
tWLWH Write Enable Low to Write Enable High Min 100 ns
tDVWH Data Valid to Write Enable High Min 50 ns
tWHDX Write Enable High to Data Transition Min 5 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC High Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tWHWL Write Enable High to Write Enable Low Min 100 ns
tCHWH RC High to Write Enable High Min 50 ns
tVPHWH(1) VPP High to Write Enable High Min 100 ns
tWHGL Write Enable High to Output Enable Low Min 30 ns
tWHRL Write Enable High to RB Lo w Min 0 ns
tQVVPL(1,2) Outp ut Valid, RB High to VPP Low Min 0 ns
AI04194
tCLAX
tCHAX
tWHDXtDVWH
VALID SRD
A0-A10
G
DQ0-DQ7
RC
tCHWH
tWHRL
C1
W
R1
tAVCL
tAVCH
R2 C2
tWLWH
tWHWL
RB
VPP
tVPHWH tWHGL
tQVVPL
DIN1 DIN2
Write erase or
program setup
Write erase confirm or
valid address and data
Automated erase
or program delay Read Status
Register Data Ready to write
another command
35/45
M50FW016
PACKAGE MECHANICAL
Figure 15. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline
Note: Drawing is not to scale.
Table 27. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283
e 0.500 – – 0.0197 – –
E 9.900 10.100 0.3898 0.3976
L 0.500 0.700 0.0197 0.0276
α0° 5° 0° 5°
N40 40
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
M50FW016
36/45
PART NUMBERING
Table 28. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Example: M50FW016 N1TG
Device Type
M50
Architecture
F = Firmware Hub Interface
Operatin g Voltage
W = 3.0 to 3.6V
Device Function
016 = 16 Mbit (2Mb x8), Uniform Block
Package
N = TSOP40: 10 x 20 mm
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow
Option
blank = Standard Pa ck ing
T = Tape & Reel Packing
Plating Technology
blank = Standard Sn Pb plati ng
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
37/45
M50FW016
APPENDIX A. FLOWCHARTS AND PSEUDO CODES
Figure 16. Program Flowchart and Pseudo Code
Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by
following the correct command sequence.
2. If an erro r is f ound, the Status Register must be cleared before further Program/Erase Controller operations.
Write 40h or 10h
AI03407
Start
Write Address
& Data
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Program command:
– write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)
do:
–read Status Register if Program/Erase
Suspend command given execute
suspend program loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4 = 1, Program error:
– error handler
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2) If b1 = 1, Program to protected block error:
– error handler
Suspend
Suspend
Loop
NO
YES
FWH
Interface
Only
M50FW016
38/45
Figure 17. Quadruple Byte Program Flowcha rt and Pseudo Code (A/A Mux Interface Only)
Note: 1 . A Status check of b3 (VPP invalid) and b4 (Pr ogram Error) can be made after each Pro gram operation by following th e correct com-
mand sequence.
2. If an erro r is f ound, the Status Register must be cleared before further Program/Erase Controller operations.
3. Addres s 1, Address 2, Add r ess 3 and Address 4 must be consecutive addresses dif fering only for add ress bits A0 and A1.
AI03982
Write Address 4
& Data 4
(3)
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1
(3)
– write Address 2 & Data 2
(3)
– write Address 3 & Data 3
(3)
– write Address 4 & Data 4
(3)
(memory enters read status state after
the Quadruple Byte Program command)
do:
– read Status Register if Program/Erase
Suspend command given execute
suspend program loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4 = 1, Program error:
– error handler
End
YES
Suspend
Suspend
Loop
NO
YES
Write 30h
Start
Write Address 1
& Data 1
(3)
Write Address 2
& Data 2
(3)
Write Address 3
& Data 3
(3)
39/45
M50FW016
Figure 18. Quadruple Byte Program Flowchart and Pseudo Code (FWH Interface Only)
Note: 1 . A Status check of b3 (VPP invalid) and b4 (Pr ogram Error) can be made after each Pro gram operation by following th e correct com-
mand sequence.
2. If an erro r is f ound, the Status Register must be cleared before further Program/Erase Controller operations.
3. A1 and A0 are treated as Don’t Care. Starting at the Start Address, the first data byte is programmed at the address that has A1-
A0 at 00, t he second at the address t hat has A1-A0 a t 01, the third at the ad dress that has A1-A0 at 1 0, and the fou rth at th e address
that has A1-A0 at 11.
AI05736B
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Quadruple Byte Program command:
– write 30h
– write Start Address and 4 Data Bytes
(3)
(memory enters read status state after
the Quadruple Byte Program command)
do:
– read Status Register if Program/Erase
Suspend command given execute
suspend program loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4 = 1, Program error:
– error handler
Suspend
Suspend
Loop
NO
YES
Write 30h
Start
Write Start Address
and 4 Data Bytes
(3)
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2) If b1 = 1, Program to protected block error:
– error handler
M50FW016
40/45
Figure 19. Program Suspend and Resume Flowc hart, and Pseudo Code
Write 70h
AI03408
Read Status
Register
YES
NO
b7 = 1
YES
NO
b2 = 1
Program Continues
Write a read
Command
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while b7 = 1
If b2 = 0 Program completed
Write D0h Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
Read Data
41/45
M50FW016
Figure 20. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controll er operations.
Write 80h
AI04195
Start
Write 10h
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4, b5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Chip Erase command:
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
do:
– read Status Register
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4, b5 = 1, Command sequence error:
– error handler
YES
NO
b5 = 0 Erase Error (1) If b5 = 1, Erase error:
– error handler
End
YES
M50FW016
42/45
Figure 21. Block Erase Flowchart and Pseudo Code
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controll er operations.
Write 20h
AI04196
Start
Write Block Address
& D0h
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4, b5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Block Erase command:
– write 20h
– write Block Address & D0h
(memory enters read Status Register after
the Block Erase command)
do:
– read Status Register
– if Program/Erase Suspend command
given execute suspend erase loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4, b5 = 1, Command sequence error:
– error handler
YES
NO
b5 = 0 Erase Error (1)
YES
NO
Suspend
Suspend
Loop
If b5 = 1, Erase error:
– error handler
End
YES
NO
b1 = 0 Erase to Protected
Block Error (1) If b1 = 1, Erase to protected block error:
– error handler
YES
FWH
Interface
Only
43/45
M50FW016
Figure 22. Erase Suspend and Resume Flowchart, and Pseudo Code
Write 70h
AI03410
Read Status
Register
YES
NO
b7 = 1
YES
NO
b6 = 1
Erase Continues
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while b7 = 1
If b6 = 0, Erase completed
Write D0h
Read data from
another block
or
Program
Start
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
M50FW016
44/45
REVISION HISTORY
Table 29. Document Revision History
Date Version Revision Details
May 2001 -01 F irs t Issu e
October 2001 -02 Added LPC Bus Read and Bus Write cycles
Added FWH 64 and 128 byte Bus Reading
21-Feb-2002 -03 Removed LPC Bus Read and Bus Write cycles
01-Mar-2002 -04 RFU pins must be left disconnected
30-Jul-2002 -05 Quadruple Byte Mode changed to 4/16/128 bytes
13-Feb-2003 5.1
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(rev ision version 05 eq ua ls 5.0 )
Datasheet promoted from Product Preview to Preliminary Data status.
12-Jul-2004 6.0
Document imported in new template and reformatted.
Temperature Range ordering information replaced by Device Grade, Standard
packing option added and Plating Technology added to Table 28., Ordering
Inform ati on Scheme . TLEAD parameter added to Table 16., Absolute Maximum
Ratings and TBIAS parameter removed. Pin 39 changed from VCC to RFU in Figure
4., TSOP Connections.
45/45
M50FW016
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