CS52843 CS52843 Current Mode PWM Control Circuit Description Features before the output stage is enabled. In the CS52843 turn on is at 8.4V and turn off at 7.6V. The CS52843 provides all the necessary features to implement offline fixed frequency current-mode control with a minimum number of external components. Other features include low start-up current, pulse-by-pulse current limiting, and a high-current totem pole output for driving capacitive loads, such as gate of a power MOSFET. The output is low in the off state, consistent with N-channel devices. The CS52843 incorporates a new precision temperature-controlled oscillator to minimize variations in frequency. An undervoltage lockout ensures that VREF is stabilized Absolute Maximum Ratings Supply Voltage (ICC<30mA) ..........................................................Self Limiting Supply Voltage (Low Impedance Source)...................................................30V Output Current ...............................................................................................1A Output Energy (Capacitive Load) .................................................................5J Analog Inputs (VFB, VSENSE)...........................................................-0.3V to 5.5V Optimized for Off-line Control Internally Temperature Compensated Oscillator VREF Stabilized before Output Stage is Enabled Very Low Start-up Current 300 A (typ) Pulse-by-pulse Current Limiting Improved Undervoltage Lockout Double Pulse Suppression 2% 5 Volt Reference High Current Totem Pole Output Error Amp Output Sink Current...............................................................10mA Lead Temperature Soldering Reflow (SMD styles only) ...........60 sec. max above 183C, 230C peak Package Options Block Diagram 8L SO Narrow VCC Undervoltage Lock-out VCC 34V VCC Pwr Set/ Reset Gnd 5.0 Volt Reference VREF 8.4V/7.6V VFB Internal Bias + OSC R 2.50V OUTPUT ENABLE R VOUT NOR Oscillator S 2R Pwr Gnd R R Sense 1 8 VREF VFB 2 7 VCC Sense 3 6 VOUT OSC 4 5 Gnd 14L SO Narrow Error Amplifier COMP COMP 1V PWM Current Sensing Latch Comparator COMP 1 14 VREF NC 2 13 NC VFB 3 12 VCC NC 4 11 VCC Pwr Sense 5 10 VOUT NC 6 9 Pwr Gnd OSC 7 8 Gnd Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 12/23/97 1 A (R) Company CS52843 Electrical Characteristics: -40 TA 85C; VCC = 15V (Note 1); RT = 680; CT = .022F for triangle mode, RT = 10k; CT = 3.3nF sawtooth mode unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference Section Output Voltage TJ = 25C, IREF = 1mA 5.00 5.10 V Line Regulation 12 VCC 25V 4.90 6 20 mV Load Regulation 1 IRE F 20mA 6 25 mV Temperature Stability (Note 1) 0.4 mV/C Total Output Variation Line, Load, Temp. (Note 1) Output Noise Voltage 10Hz f 10kHz, TJ = 25C (Note 1) 0.2 4.82 5.18 50 V V Long Term Stability TA = 125C, 1000 Hrs. (Note 1) 5 25 mV Output Short Circuit TA = 25C -30 -100 -180 mA Sawtooth Mode, TJ = 25C (Note 1) 47 52 57 kHz Triangle Mode, TJ = 25C 44 52 60 kHz 0.2 1.0 % Oscillator Section Initial Accuracy Voltage Stability 12 VCC 25V Temperature Stability Sawtooth Mode TMIN TA TMAX Amplitude Triangle Mode TMIN TA TMAX (Note 1) VOSC (peak to peak) Discharge Current TJ = 25C 7.3 TMIN TA TMAX 6.8 2.42 5 % 8 1.7 % V 8.3 9.3 mA 9.8 mA Error Amp Section Input Voltage VCOMP = 2.5V Input Bias Current VFB = 0V 2.50 2.58 V -0.3 -2.0 A AVOL 2 VOUT 4V 65 90 dB Unity Gain Bandwidth (Note 1) 0.7 1.0 MHz PSRR 12 VCC 25V 60 70 dB Output Sink Current VFB = 2.7V, VCOMP = 1.1V 2 6 mA Output Source Current VFB = 2.3V, VCOMP = 5V -0.5 -0.8 mA VOUT HIGH VFB = 2.3V, RL = 15k to Gnd 5 6 VOUT LOW VFB = 2.7V, RL = 15k to VREF V 0.7 1.1 V V/V Current Sense Section Gain (Notes 2 & 3) 2.85 3.00 3.15 Maximum Input Signal VCOMP = 5V (Note 2) 0.9 1.0 1.1 PSRR 12 VCC 25V (Note 2) 70 V dB Input Bias Current VSense=0V -2 -10 A Delay to Output TJ=25C (Note 1) 150 300 ns Output Low Level ISINK = 20mA ISINK = 200mA 0.1 1.5 0.4 2.2 V V Output High Level ISOURCE = 20mA ISOURCE = 200mA Output Section 13.0 12.0 2 13.5 13.5 V V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Rise Time TJ = 25C, CL = 1nF (Note 1) 50 150 ns Fall Time TJ=25C, CL=1nF (Note 1) 50 150 ns Output Leakage UVLO Active VOUT = 0 -.01 -10.0 A Total Standby Current Start-Up Current 300 500 A Operating Supply Current VFB=VSense=0V RT=10k, CT=3.3nF 11 17 mA VCC Zener Voltage ICC=25mA 34 V Undervoltage Lockout Section Start Threshold Min. Operating Voltage Notes: After Turn On 7.8 8.4 9.0 V 7.0 7.6 8.2 V 1.These parameters, although guaranteed, are not 100% tested in production. 2. Parameter measured at trip point of latch with VFB=0. 3. Gain defined as: A = VCOMP VSense ; 0 VSense 0.8V. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 8L SO Narrow 14L SO Narrow 1 1 2 3 VFB 3 5 Sense 4 7 OSC Oscillator timing network with Capacitor to Ground, resistor to VREF. 5 8 Gnd Ground. 5 9 Pwr Gnd 6 10 VOUT 7 11 VCCPwr 7 12 VCC Positive power supply. 8 14 VREF Output of 5V internal reference. 2,4,6,13 NC No Connection. COMP Error amp output, used to compensate error amplifier. Error amp inverting input. Noninverting input to Current Sense Comparator. Output driver Ground. Output drive pin. Output driver positive supply. 3 CS52843 Electrical Characteristics: -40 TA 85C; VCC = 15V (Note 1); RT = 680; CT = .022F for triangle mode, RT = 10k; CT = 3.3nF sawtooth mode unless otherwise stated. CS52843 Typical Performance Characteristics 100 900 90 800 RT =680 80 DUTY CYCLE (%) FREQ. (kHz) 700 600 500 RT =1.5k 400 70 60 50 40 300 30 200 RT =10k 20 100 10 .0005 .001 .002 .003 .005 .01 .02 .03 .04 .05 100 200 300 400 500 700 CT (F) 1k 2k 3k 4k 5k 7k 10k RT () Oscillator Frequency vs CT Oscillator Duty Cycle vs RT Test Circuit Open Loop Laboratory Test Fixture V REF RT 2N2222 V CC A 100k 4.7k 1k Error Amp Adjust 4.7k V REF COMP V FB 0.1F V CC 0.1F 5k V OUT Sense Sense Adjust OSC 1k 1W V OUT Gnd Gnd CT Circuit Description VCC Undervoltage Lockout During Undervoltage Lockout (Figure 1), the output driver is biased to sink minor amounts of current. The output should be shunted to ground with a resistor to prevent activating the power switch with extraneous leakage currents. ON/OFF Command to reset of IC VON =8.4V VOFF = 7.6V PWM Waveform To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure 2). An increase in VCC causes the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage. ICC <15mA <500A VCC VON VOFF Figure 1: Startup voltage for the CS52843. 4 CS52843 Circuit Description When the power supply sees a sudden large output current increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent transformer saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator timing components. Setting the Oscillator The times Tc and Td can be determined as follows: t c = RTCT ln t d = RTCT ln ( ( VREF - VLOWER VREF - VUPPER ) VREF - IdRT - VLOWER VREF - IdRT - VUPPER VOSC ) Substituting in typical values for the parameters in the above formulas: OSC RESET VREF = 5.0V, VUPPER = 2.7V, VLOWER = 1.0V, Id = 8.3mA, Toggle F/F Output then EA Output tc 0.5534RTCT Switch Current VCC IO td = RTCT ln VO ( 2.3 - 0.0083 RT 4.0 - 0.0083 RT ) For better accuracy RT should be 10k. Figure 2: Timing Diagram Grounding High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Gnd in a single point ground. V REF RT OSC The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense. CT Gnd Vupper Vlower tc td Sawtooth Mode LARGE RT (10k) VOSC Internal Clock Triangular Mode SMALL RT (700k) VREF Internal Clock Figure 3: Oscillator Timing Network and Parameters 5 CS52843 Package Specification PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) D Lead Count Metric Max Min 5.00 4.80 8.75 8.55 8L SO Narrow 14L SO Narrow Thermal Data English Max Min .197 .189 .344 .337 8L SO Narrow 14L SO Narrow RJC typ 45 30 C/W RJA typ 165 125 C/W Surface Mount Narrow Body (D); 150 mil wide 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D 0.25 (0.10) 0.10 (.004) REF: JEDEC MS-012 Ordering Information Part Number CS52843ED8 CS52843EDR8 CS52843ED14 CS52843EDR14 Rev. 12/23/97 Description 8L SO Narrow 8L SO Narrow (tape & reel) 14L SO Narrow 14L SO Narrow (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 6 (c) 1999 Cherry Semiconductor Corporation