LNK456DG - Power Integrations

LNK454/456-458/460

LinkSwitch-PL Family

www.powerint.com November 2010

LED Driver IC with TRIAC Dimming, Single-Stage PFC and

Constant Current Control for Non-Isolated Applications

™

Output Power Table

Product2

85-265 VAC

Minimum Output

Power

Maximum Output

Power1

LNK454D 1.5 W 3 W

LNK456D 3 W 6 W

LNK457D/K/V 4 W 8 W

LNK458K/V 6 W 11.5 W

LNK460K/V 8 W 16 W

Table 1. Output Power Table.

Notes:

1. Maximum practical continuous power in an open frame design with adequate

heat sinking, measured at +50 °C ambient (see Key Applications Considerations

for more information).

2. Packages: D: SO-8C, K: eSOP-12, V: eDIP-12.

Output Current

Number of

Serial LEDs 350 mA 500 mA 700 mA 1000 mA

1LNK454 LNK454 LNK454 LNK456

2LNK454 LNK456 LNK456 LNK457

3LNK456 LNK456 LNK457 LNK458

4LNK456 LNK457 LNK458 LNK460

5LNK457 LNK458 LNK460

6LNK457 LNK458 LNK460

7LNK458 LNK460

8LNK458 LNK460

9LNK458 LNK460

10 LNK460

11 LNK460

12 LNK460

Product Highlights

Dramatically Simpliﬁes Off-line LED Drivers

• Flicker-free phase-controlled TRIAC dimming

• Single stage power factor correction and accurate constant

current (CC) output

• Very low component count with small non-electrolytic bulk

capacitor for compact replacement lamp designs

• Compact SO8, eSOP, and eDIP packages

• Completely eliminates control loop compensation

Advanced Performance Features

• Optimized for non-isolated ﬂyback designs

• Frequency jitter greatly reduces EMI ﬁlter size and costs

• Low dissipation direct sensing of LED current

Advanced Protection and Safety Features

• Cycle skipping regulation for abnormally low output power to

clamp peak output current delivered

• 725 V integrated power MOSFET allows small bulk capacitance

and maximizes power capability

• Short-circuit, overload, open feedback and output overvoltage

protection

• Hysteretic thermal shutdown

• Meets high-voltage creepage between DRAIN and all other pins

both on PCB and at package

EcoSmart™ - Energy Efﬁcient

• High power factor optimizes system lumen per input VA

• Control algorithm balances switching and conduction losses

over line and load to maintain optimum efﬁciency

Description

The LinkSwitch-PL family enables a very small and low cost

single-stage power factor corrected constant current driver for

solid state lighting. Optimized for direct LED current sensing, the

LinkSwitch-PL operates over a wide input voltage range

delivering an output power of up to 16 W. The LinkSwitch-PL

control algorithm provides ﬂicker-free TRIAC dimming with minimal

external components.

Each device incorporates a 725 V rated power MOSFET, a novel

discontinuous mode variable frequency variable on-time controller,

frequency jitter, cycle by cycle current limit and hysteretic thermal

shutdown in a monolithic 4-pin IC, available in SO-8C, eSOP-12,

and eDIP-12 packages.

Figure 1. Basic Application Schematic.

Figure 2. Device Selection Based on Length of Output LED Series String and

Current. A Typical Voltage Drop of 3.5 V per LED is Assumed.

CONTROL

PI-5835-060710

LinkSwitch-PL

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Figure 3. Pin Conﬁguration (Top View).

Figure 2. Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:

High-voltage power MOSFET drain connection. The internal

start-up bias current is drawn from this pin through a switched

high-voltage current source. Drain current sensing and

associated controller functions are also performed using this pin.

SOURCE (S) Pin:

Power MOSFET source connection. Ground reference for

BYPASS and FEEDBACK pins.

BYPASS (BP) Pin:

Connection point for the external bypass capacitor for the

internally generated 5.85 V supply.

FEEDBACK (FB) Pin:

LED current sensing pin. During normal operation the 290 mV

threshold determines the average value of the current ﬂowing

through the load sense resistor.

A second threshold clamps excessive output current ripple.

A third higher threshold is used to protect against output

short-circuit and overvoltage conditions (see Figure 5).

PI-5893-091010

DRAIN (D)

SOURCE (S)

BYPASS (BP)

FEEDBACK (FB)

VFB(LO)

VFB(SK)

Zero Crossing

V_ILIM

IFB V_ZLIM

4.9 V

ILIM ILIM

SOA

Update

CLK

S Q

ON-TIME

EXTENSION

AUTO-RESTART

FREQUENCY/

DUTY CYCLE

CONTROLLER

DIGITAL

INTEGRATOR

INC/DEC

FILTER

PHASE

MEASUREMENT

REGULATOR

5.85 V

VREF DAC

SET

CLR

SET

CLR

CURRENT LIMIT

SOA

STATE MACHINE

1 µA

PI-5836a-092710

Exposed Pad Internally

Connected to SOURCE Pin

1 NC

2 FB

3 BP

4 NC

5 NC

6 D

S 12

S 11

S 10

S 9

S 8

S 7

V Package (eDIP-12)

D Package (SO-8C)

S12 S

11 S

10 S

9 S

8 S

7 S

NC 1

FB 2

BP 3

NC 4

NC 5

D 6

K Package

(eSOP-12)

Exposed Pad (On Bottom)

Internally Connected to

SOURCE Pin

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Functional Description

The LinkSwitch-PL combines a high-voltage power MOSFET

switch with a power supply controller in one device. The IC

provides a single stage power factor correction plus LED

current control. The LinkSwitch-PL controller consists of an

oscillator, feedback (sense and logic) circuit, 5.85 V regulator,

hysteretic over-temperature protection, frequency jittering,

cycle-by-cycle current limit, loop compensation circuitry, auto-

restart, switching on-time extension, power factor and constant

current control.

In a direct LED current sensing conﬁguration, the average

FEEDBACK pin voltage is a replica of the LED current, scaled

by the sense resistor (RSENSE in Figure 4). A small low-pass ﬁlter

(RF and CF in Figure 4) reduces high frequency noise at the

FEEDBACK pin.

Figure 5 illustrates the operating regions of the FEEDBACK pin

voltage. The LinkSwitch-PL sets its operating point such that

the average FEEDBACK pin voltage in steady-state operation is

290 mV. This threshold is set low to minimize the sensing

resistor dissipation. The internal MOSFET switching frequency

and on-time are updated once every input AC half-cycle to

regulate the output current and maintain high power factor.

If the FEEDBACK pin peak voltage exceeds 520 mV, cycle

skipping mode is triggered and the power processed by the

integrated power MOSFET is clamped on a cycle-by-cycle

basis. Switching frequency may vary during an input voltage

half-cycle to reduce thermal stress on the output LEDs.

Figure 4. Typical Application Schematic.

Figure 5. FEEDBACK Pin Operational Voltage Thresholds.

Auto-restart protection is triggered by a FEEDBACK pin voltage

in excess of 2 V. This feature can be used to provide output

overvoltage protection (via DZOV and ROV, in Figure 4), which

triggers the IC to enter auto-restart.

PI-5838-091010

Auto-Restart

2 V

520 mV

Cycle Skipping

Mode

Normal Operation

290 mV

CONTROL

PI-5837-060710

LinkSwitch-PL

CFRSENSE

ROV

DZOV

RES

DES

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

TRIAC (Phase-Controlled) Dimming

The LinkSwitch-PL integrates several features to improve

dimming range and reduce external circuit complexity when

using a phase-controlled TRIAC dimmer. The output LED

current is controlled by the FEEDBACK pin voltage which

changes proportionally to the TRIAC dimmer conduction angle.

When the conduction angle decreases, the voltage at the

FEEDBACK pin decreases causing the average LED current to

decrease.

The FEEDBACK pin reference voltage adjustment is initiated at

approxi-mately 25% of the AC line half-cycle duration. When this

(jOS) threshold is exceeded, VFB and the output LED current

are reduced until a second phase angle threshold is reached.

At this point, with the TRIAC conduction angle being very

limited, the IC runs open loop at constant frequency and duty

cycle (jOL region) and the integrated power MOSFET

processes as much power as the heavily chopped input voltage

will allow creating a light output that is deeply dimmed.

The 520 mV clamping feedback threshold is also linearly reduced

during dimming to control LED current ripple.

Figure 6. Feedback Voltage vs. Phase Angle Dimming Characteristics.

VFB(ϕ)VFB(ϕ)

VFB

ϕOL

ϕ ϕ

180°0°

VLINE

Phase

Angle

Phase

Angle

Conduction

Angle

Conduction

Angle

Leading Edge

TRIAC Dimmers

Trailing Edge

Dimmers

VTRIAC

180°0°

0° 0°

PI-5894a-091010

ϕOS ϕOL ϕOS

Phase

Angle

Phase

Angle

Phase

Angle

Phase

Angle

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

IC Supply and BYPASS Pin

The internal 5.85 V regulator charges the bypass capacitor

connected to the BYPASS pin to 5.85 V by drawing current

from the voltage on the DRAIN pin whenever the power MOSFET

is off. The BYPASS pin is the internal supply voltage node.

When the power MOSFET is on, the device operates from the

energy stored in the bypass capacitor. Extremely low power

consumption of the internal circuitry allows LinkSwitch-PL to

operate continuously from current it takes from the DRAIN pin.

A bypass capacitor value of 1 µF is sufﬁcient for both high

frequency decoupling and energy storage. Dimming

applications may require a higher bypass capacitor value.

During phase angle dimming when the conduction angle is

small the AC input voltage is present for only short periods of

time. In that case the IC should not rely on the integrated high

voltage current source, but instead external bias circuitry should

be used to supply the IC from the output (DES and RES in Figure

4). If the output voltage is less than 7 V, external bias circuitry

should be implemented. This is accomplished by adding an

auxiliary winding on the transformer, which is then rectiﬁed and

ﬁltered via a diode (ultrafast) and capacitor. The winding voltage

(turns) should be selected such that the maximum IC consumption

can be supported at the lowest operating output current.

Start-up, Switching Frequency and On-time Range

At start-up the controller uses an initial switching frequency fMIN

and minimum on-time tON(MIN). The charging of the output

capacitor together with the energy delivery to the output LEDs

determines a step-by-step increase of the power MOSFET

switching frequency and on-time updated every half-cycle of the

AC input voltage.

The steady state switching frequency and on-time are

determined by the line voltage, voltage drop across the LEDs

and converter efﬁciency.

At light load when the device reaches the minimum frequency

fMIN and on-time tON(MIN), the controller regulates by skipping

cycles. In this mode of operation the input current is not power

factor corrected and the average output current is not

guaranteed to fall within the normal range. The FEEDBACK pin

cycle skipping threshold is reduced from approximately twice

the normal regulation level down to just above the level required

to limit output power delivery under these conditions. A

properly designed supply will not operate in this mode under

normal load conditions. A power supply designed correctly will

operate within the switching frequency range [fMIN … fMAX], with

an on-time falling between tON(MIN) and tON(MAX) when connected

to a normal load.

Overload Protection

In case of overload, the system will increase the operating

frequency and on-time each AC half-cycle until the maximum

frequency and maximum on-time are reached. When this state

is reached, the controller enters auto-restart protection, thus

inhibiting the gate of the power MOSFET for approximately

1.28 s if the main line frequency is 50 Hz, 1.02 s if it is 60 Hz.

After this auto-restart off-time expires, the power MOSFET is

re-enabled and a normal start-up is initiated, i.e. at fMIN and

tON(MIN), stepping up until regulation is achieved again. In case of

a persistent overload condition, the auto-restart duty cycle DCAR

is ~33%.

Overload protection is inhibited during phase dimming when the

TRIAC conduction duty cycle is less than 60%.

Output Overvoltage Protection

If a no-load condition is present on the output of the supply, the

output overvoltage Zener (DZOV in Figure 4) will conduct once its

threshold is reached. A voltage VOV in excess of VFB(AR) = 2 V will

appear across the FEEDBACK pin and the IC will enter auto-

restart.

Output Short-Circuit

If the output of the supply (i.e. the LED load) is short-circuited,

then a large amount of energy will be delivered to the sense

resistor, generating a high voltage at the FEEDBACK pin. If this

condition develops more than 2 V on the FEEDBACK pin, then

the IC will interpret this event as an output short-circuit and will

enter auto-restart.

Safe Operating Area (SOA) Protection

If 3 consecutive cycles of the power MOSFET are prematurely

terminated due to the power MOSFET current exceeding the

current limit after the leading edge blanking time, SOA protection

mode is triggered and the IC will enter auto-restart.

Hysteretic Thermal Shutdown

The thermal shutdown circuitry senses the die junction

temperature. The thermal shutdown threshold is set to 142 °C

typical with a 75 °C hysteresis. When the die temperature rises

above this threshold (142 °C) the power MOSFET is disabled

and remains disabled until the die temperature falls by 75 °C, at

which point the power MOSFET is re-enabled.

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

LinkSwitch-PL Application Example

The circuit shown in Figure 7 provides a single constant current

output of 350 mA with an LED string voltage of 15 V. The

output current can be reduced using a standard AC mains

TRIAC dimmer down to 1% (3 mA) without instability and

ﬂickering of the LED load. The board is compatible with both

low cost leading edge and more sophisticated trailing edge

dimmers.

The board was optimized to operate over the universal AC input

voltage range (85 VAC to 265 VAC, 47 Hz to 63 Hz) but suffers

no damage over an input range of 0 VAC to 300 VAC. This

increases ﬁeld reliability and lifetime during line sags and swells.

LinkSwitch-PL based designs provide high power factor (>0.9

at 115 VAC / 230 VAC) and low THD (<15% at 230 VAC, <10%

at 115 VAC) enabling compliance to all current international

requirements and enabling a single design to be used

worldwide.

The form factor of the board was chosen to meet the requirements

for standard pear shaped (A19) LED replacement lamps. The

output is non-isolated and requires the mechanical design of

the enclosure to isolate both the supply and the LED load from

the user.

PI Part Selection

One device size larger than required was selected to increase

efﬁciency and reduce device thermal rise. This typically gives

the highest efﬁciency. Further increasing the device size often

results in the same or lower efﬁciency due to the larger

switching losses associated with a larger power MOSFET.

AC Line TRIAC Dimmer Interface Circuits

The requirement to provide output dimming with low cost,

TRIAC based, leading edge phase dimmers introduces a

number of trade-offs in the design.

Due to the much lower power consumed by LED lighting

compared to incandescent lighting, the current drawn by the

lamp is below the holding current of the TRIAC dimmer. This

causes undesirable behavior such as limited dimming range

and/or ﬂickering. Inrush current that ﬂows to charge the input

capacitance when the TRIAC turns on causes current ringing.

This too can cause similar undesirable behavior as the ringing

may cause the TRIAC current to fall to zero and turn off for the

remainder of the AC cycle or rapidly turn on and off.

To overcome these issues the design includes three circuit

blocks, a passive damper, an active damper and a bleeder. The

drawback of these blocks is increased power dissipation and

therefore reduced efﬁciency of the supply. In this design, the

values selected allow ﬂicker-free operation with a single lamp

connected to a single dimmer at high line. For ﬂicker-free

operation with multiple lamps in parallel or at low line voltages

only (100/115 VAC) then the values may be optimized to reduce

dissipation and increase efﬁciency.

As these blocks are only required for dimming applications, for

non-dimming designs these components can simply be omitted

with jumpers used to replace R7, R8 and R20.

Active and Passive Damper Circuits

Resistor R20 forms a passive damper that together with the

active damper limits the peak inrush current when the TRIAC

ﬁres on each half cycle. It should be a ﬂameproof type to safely

fail during a single point fault (e.g. failure of a bridge diode).

The active damper circuit connects a series resistance (R7 and

R8) with the input rectiﬁer for a period of each AC half-cycle, it is

then bypassed for the remainder of the AC cycle by a parallel

SCR (Q3). Resistor R3, R4 and C3 determines the delay before

the turn-on of Q3 which then shorts out the damper resistors

R7 and R8.

750 kΩ

4.7 kΩ

2.2 mH

PI-6171a-102910

CONTROL

EE16

R10

510 Ω

3.15 A

RV1

275 VAC

R20

47 Ω

4.7 kΩ

R11

510 Ω

R13

4.7 Ω

R12

100 kΩ

R16

10 kΩ

15 V, 350 mA

90 - 265

VAC

RTN

R18

0.82 Ω

R17

27 Ω

R15

3.3 kΩ

R14

1 kΩ

R21

1 kΩ

US1J

BAV19WS

Passive Damper

Active Damper Bleeder

VR2

MAZS2000ML

20 V

SS110-TP

DL4006

BR1

MB6S

600 V

C10

1 nF

100 V

C11

680 µF

25 V

10 nF

50 V

1 µF

25 V

LinkSwitch-PL

LNK457DG

68 nF

400 V

1000 pF

630 V

68 nF

400 V

22 nF

630 V

2.2 mH

240 Ω

22 nF

50 V

240 Ω

Figure 7. Schematic of a 5 W, 15 V LED Driver for A19 Incandescent Lamp Replacement.

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Bleeder Circuit

Resistor R10, R11 and C6 form a bleeder network which

ensures the initial input current is high enough meet the TRIAC

holding current requirement, especially during small conduction

angles. For non-dimming application R10, R11 and C6 may be

omitted.

Input Rectiﬁer and EMI Filter

EMI ﬁltering is provided by L1 and a pi (π) ﬁlter formed by C4, L2

and C5. Resistors R2 and R9 dampen the self resonances of

the ﬁlter stages and reduce the resultant peaks in the

conducted EMI spectrum. As shown the design meets

EN55015 conducted limits with >20 dB margin.

The incoming AC is rectiﬁed by BR1 and ﬁltered by C4 and C5.

The total effective input capacitance, the sum of C4 and C5,

was selected to ensure correct zero crossing detection of the

AC input by the LinkSwitch-PL device, necessary for correct

dimming operation.

Primary Components

The LNK457DG device (U1) incorporates the power switching

device, oscillator, CC control engine, startup, and protection

functions. The integrated 725 V power MOSFET provides

extended design margin, improving robustness during line

surge events even in high line applications. The device is

powered from the BYPASS pin via the decoupling capacitor C9.

At start-up, C9 is charged by U1 from an internal current source

via the DRAIN pin and then during normal operation it is

supplied by the output via R15 and D4. For non-dimming

designs D4 and R15 may be omitted.

The rectiﬁed and ﬁltered input voltage is applied to one end of

the primary winding of T1. The other side of the transformer’s

primary winding is driven by the integrated power MOSFET in

U1. The leakage inductance drain voltage spike is limited by an

RCD-R clamp consisting of D2, R13, R12, and C7.

Diode D6 is used to protect the IC from negative ringing (drain

voltage below source voltage) when the power MOSFET is off

and the input voltage is below the reﬂected output voltage (VOR).

Output Rectiﬁcation

The secondary of the transformer is rectiﬁed by D5, a Schottky

barrier type for higher efﬁciency, and ﬁltered by C11. Resistor

R17 and C10 damp high frequency ringing and improve

conducted and radiated EMI.

Output Feedback

The CC mode set-point is determined by the voltage drop that

appears across R18 which is then fed to the FEEDBACK pin of

U1. Output overvoltage protection is provided by VR2 and R21.

Application Considerations

Input Capacitor Selection

For correct operation during dimming, the LinkSwitch-PL device

must detect line voltage zero crossing. This is sensed internally

via the drain node at the point the DC bus falls to <19 V. The

requirement for the DC bus to reach this level on each half-cycle

limits the maximum capacitance on the DC side of the input

bridge rectiﬁer. Typically the maximum capacitance value

needed for high power factor also results in meeting the 19 V

limit however during development, this should be veriﬁed on an

oscilloscope.

If a reduction in capacitance is required and this results in

increased conducted EMI then capacitance may be added

before the input rectiﬁer which effectively isolates it from the bus

capacitance.

For applications intended for use with leading edge TRIAC

dimmers, ﬁlm capacitors are recommended as ceramic

capacitors typically create audible noise.

Output Capacitor Selection

Output capacitance has a direct effect on the output load (LED)

ripple current. The larger the capacitance, the lower the ripple

current. Excessive capacitance can prevent the output reaching

regulation within the auto-restart time and either cause failure to

start or require several start-up attempts (hiccups). Too little

capacitance can cause the voltage of the FEEDBACK pin to

exceed the cycle skipping mode threshold, degrading PF and

causing output ﬂicker while dimming.

Therefore the output capacitance value should be selected

such that the ripple voltage across the output current sense

resistor (R18 in Figure 7) and fed into the FEEDBACK pin is

within the range of 100 mVp-p ≤ VFEEDBACK ≤ 400 mVp-p with a

target value of 290 mVp-p.

The output capacitor type is not critical. Non-electrolytic

capacitors are attractive in terms of lifetime (ceramics and solid

dielectric types do not have an electrolyte that evaporates over

time) however electrolytic types offer the best volumetric

efﬁciency vs. cost. If multi-layer ceramics are selected, verify

the data sheet curves of capacitance vs. applied voltage and

temperature coefﬁcient. The typical capacitance value may be

50% lower across temperature and/or close to rated voltage.

For all capacitor types verify the capacitor(s) selected are rated

for the output ripple current. For electrolytic types, this requires

selecting a low ESR type. A temperature rating of 105 °C or

higher is recommended for long lifetime. For typical designs

there is minimal self heating of the output capacitor and

therefore lifetime is determined by the internal ambient

temperature and broadly follows the Arrhenius equation, i.e.

lifetime doubles for every 10 °C drop in operating temperature.

For example the selection of a capacitor with a rated life of

5,000 hours at 105 °C would have an expected lifetime of

40,000 hours at 75 °C. End of life is typically deﬁned for an

electrolytic capacitor as a doubling of the ESR and the

capacitance reducing by 20%. This often has little impact to

the performance seen by the end user and extends the ﬁt for

purpose lifetime.

Feedback Pin Signal

During normal non-dimming (full power) operation, the FEEDBACK

pin threshold voltage (the voltage developed across the current

sense resistor) is 290 mV. For best output current regulation,

between 100 mVp-p to 400 mVp-p of voltage ripple is recommended.

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

This can be achieved through selecting the appropriate value of

output capacitance and the value of the current sense resistor.

If the peak of the ripple voltage exceeds 520 mV, the device will

enter cycle skipping mode which will reduce PFC performance

(lower PF and increase THD).

Transformer Considerations for use with

Leading Edge TRIAC Dimmers

Audible noise can be created in the transformer due to the

abrupt change in ﬂux when the TRIAC turns on. This can be

minimized by selecting cores with higher mechanical resonant

frequencies. Cores with long narrow legs should be avoided

(e.g. EEL types). RM and other pot core types are good

choices and produce less audible noise than EE cores for the

same ﬂux density. Reducing the core ﬂux density (BM) also

reduces audible noise generation. A value below 1500 Gauss

usually eliminates any noise generation but reduces the power

capability of a given core size.

Working with TRIAC Dimmers

The requirement to provide output dimming with low cost,

TRIAC based, leading edge phase dimmers introduces a

number of trade-offs in the design.

For correct operation incandescent phase angle dimmers

typically have a speciﬁed minimum load, typically ~40 W for a

230 VAC rated unit. This is to ensure that the current through

the internal TRIAC stays above its speciﬁed holding current

threshold.

Due to the much lower power consumed by LED lighting the

input current drawn by the lamp is below the holding current of

the TRIAC within the dimmer. The input capacitance of the

driver allows large inrush currents to ﬂow when the TRIAC ﬁres.

This then generates input current ringing with the input stage

and line inductance which may cause the current to fall below

the TRIAC holding current. Both of these mechanisms cause

undesirable behavior such as limited dimming range and/or

ﬂickering.

To overcome these issues two circuit blocks, damper and

bleeder, are incorporated in dimming applications. The

drawback of these circuits is increased dissipation and

therefore reduced efﬁciency of the supply.

Figure 8 shows the line voltage and current at the input of a

leading edge TRIAC dimmer. In this example, the TRIAC

conducts at 90 degrees.

Figure 9 shows the desired rectiﬁed bus voltage and current.

Figure 10 shows undesired rectiﬁed bus voltage and current

with the TRIAC turning off prematurely and restarting. On the

ﬁrst half cycle this is due to the input current ringing below the

holding current of the TRIAC, excited by the initial inrush current.

The second half cycle also shows the TRIAC turning off due to

the current falling below the holding current towards the end of

the conduction angle. This difference in behavior on alternate

half cycles is often seen due to a difference in the holding

current of the TRIAC between the two operating quadrants.

If the TRIAC is turning off before the end of the half cycle or

rapidly turning on and off then a bleeder and damper circuit are

required.

In general as power dissipated in the bleeder and damper

circuits increases, so does dimmer compatibility.

Initially install a bleeder network across the rectiﬁed power bus

(R10, R11 and C6 in Figure 7) with initial values of 0.1 µF and a

total resistance of 1 kW and power rating of 2 W.

Figure 8. Ideal Input Voltage and Current Waveforms for a Leading Edge

TRIAC Dimmer at 90° Conduction Angle.

50 100 150 200 250 300 350 400

Conduction Angle (°)

Line Voltage (at Dimmer Input) (V)

Line Current (Through Dimmer) (A)

350

250

150

-50

-150

-250

-350

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

PI-5983-060810

Voltage

Current

0.5

050 100 150 200 250 400350300

Conduction Angle (°)

Rectified Input Voltage (V)

Rectified Input Current (A)

350

300

250

200

150

100

0.35

0.3

0.25

0.2

0.15

0.1

0.05

PI-5984-060810

Voltage

Current

Figure 9. Resultant Waveforms Following Rectiﬁcation of Ideal TRIAC

Dimmer Output.

050 100 150 200 250 400350300

Conduction Angle (°)

Rectified Input Voltage (V)

Rectified Input Current (A)

350

300

250

200

150

100

0.35

0.3

0.25

0.2

0.15

0.1

0.05

PI-5985-102810

Voltage

Current

Figure 10. Example of Phase Angle Dimmer Showing Erratic Firing.

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Reduce the capacitance value to ﬁnd the minimum acceptable

value. Reducing the capacitance value reduces power

dissipation and therefore increases efﬁciency.

If the bleeder circuit does not maintain conduction in the TRIAC,

then add a damper. The purpose of the damper is to limit the

inrush current (as the input capacitance charges) and

associated ringing that occurs when the TRIAC turns on.

Initially add a passive damper which is a simple resistor in series

with the AC input (R20 in Figure 7). Values in the range of 10 W

– 100 W are typical with the upper range being limited by the

allowed dissipation / temperature rise and reduction in

efﬁciency. Values below 10 W may also be used but are less

effective especially in high AC line input designs.

If a passive damper is insufﬁcient to prevent incorrect TRIAC

operation then an active damper can be added. This is typical

in high line applications due to the much larger inrush current

that ﬂows when the TRIAC turns on. A low cost active damper

circuit is formed by R3, R4, C3, Q3, R7 and R8 in Figure 7.

Resistor R7 and R8 limit the inrush current and can be a much

higher value than the passive case as they are in circuit for only

a fraction of the line cycle. Silicon controlled rectiﬁer (SCR) Q3

shorts R7 and R8 after a delay deﬁned by R3, R4 and C3. The

delay is adjusted to give the shortest time that provides

acceptable dimmer performance to minimize the dissipation in

the resistors. The SCR is a low current, low cost device

available in TO-92 packages with very low gate current

requirements. The gate drive requirement of the selected SCR

together with the minimum speciﬁed line voltage deﬁnes the

maximum value of R7 and R8.

It’s common for different dimmers to behave differently across

manufacturers and power ratings. For example a 300 W

dimmer requires less dampening and requires less power loss

in the bleeder than a 600 W or 1000 W dimmer due to the use

of a lower current rating TRIAC which typically have lower

holding currents. Line impedance differences can also cause

variation in behavior so during development the use of an AC

source is recommended for consistency however testing using

AC mains power should also be performed.

Electronic Trailing Edge Dimmers

Figure 11 shows the line voltage and current at the input of the

power supply with a trailing edge electronic dimmer. In this

example, the dimmer conducts at 90 degrees. This type of

dimmer typically uses a power MOSFET or IGBT to provide the

switching function and therefore no holding current is

necessary. Also since the conduction begins at the zero

crossing, high current surges and line ringing are not an issue.

Use of these types of dimmers typically does not require

damper and bleeder circuits.

Thermal Considerations

Lighting applications present unique thermal challenges for the

power supply designer. In many cases the LED load and

associated heatsink determine the power supply ambient

temperature. Therefore it is important to properly heatsink and

verify the operating temperatures of all devices. For the

LinkSwitch-PL device a SOURCE pin (D package) or exposed

pad (K or V package) temperature of <115 °C is recommended

to allow margin for unit to unit variation. Worst case conditions

are typically maximum output power, maximum external

ambient and either minimum or maximum input voltage.

Layout Considerations

Primary Side Connections

The BYPASS pin capacitor should be located as close to the

BYPASS pin and connected as close to the SOURCE pin as

possible. The SOURCE pin trace should not be shared with the

main power MOSFET switching currents. All FEEDBACK pin

components that connect to the SOURCE pin should follow the

same guideline as for the BYPASS pin capacitor.

It is critical that the main power MOSFET switching currents

return to the bulk capacitor with the shortest path possible. Long

high current paths create excessive conducted and radiated

noise.

50 100 150 200 250 300 350

Conduction Angle (°)

Dimmer Output Voltage (V)

Dimmer Output Current (A)

350

250

150

-50

-150

-250

-350

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

PI-5986-060810

Voltage

Current

Figure 11. Ideal Dimmer Output Voltage and Current Waveforms for a Trailing Edge

Dimmer at 90° Conduction Angle.

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Secondary Side Connections

The output rectiﬁer and output ﬁlter capacitor should be as

close as possible. The transformer output return pin should

have a short trace to the return side of the output ﬁlter

capacitor. These currents should not ﬂow through the primary

side source pin currents. The primary side source pin and

secondary side return should be connected with a short trace.

Quick Design Checklist

Maximum Drain Voltage

Verify that the peak VDS does not exceed 700 V under all

operating conditions including start-up and fault conditions.

Maximum Drain Current

Measure the peak drain current under all operation conditions

including start-up and fault conditions. Look for signs of

transformer saturation (usually occurs at high ambient

temperatures). Verify that the peak current is less than stated in

the Absolute Maximum Ratings section.

Thermal Check

At maximum output power, both minimum and maximum line

voltage and ambient temperature; verify that temperature

speciﬁcations are not exceeded for the LinkSwitch-PL,

transformer, output diodes, output capacitors and drain clamp

components.

Figure 12. RD-251 PCB Top View.

Figure 13. RD-251 PCB Bottom View.

Transformer

Bulk Capacitor Copper Heat Sink Area Output Filter

Capacitor

Switching

Current Loop

(Primary)

PI-6212-102810

Transformer

Bulk Capacitor

Connection Between

Primary and Secondary

Switching

Current Loop

(Secondary)

PI-6213-102810

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 to +125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Control Functions

Maximum Output

Frequency fMAX TJ = 25 °C

Average 110 122 134 kHz

Peak-Peak Jitter 6 %

Minimum Output

Frequency fMIN TJ = 25 °C

Average 25.8 28.7 31.6 kHz

Peak-Peak Jitter 6 %

Maximum Switch

ON-Time tON(MAX) TJ = 25 °C 5.74 µs

Minimum Switch

ON-Time tON(MIN) TJ = 25 °C 1.2 µs

Maximum Duty Cycle DCMAX 70 %

FEEDBACK Pin Voltage VFB

TJ = 25 °C

Non-dimming (full power) operation 280 290 300 mV

FEEDBACK Pin Voltage

Triggering Cycle

Skipping Mode

VFB(SK) Non-dimming (full power) operation 520 mV

FEEDBACK Pin Voltage

for IC Auto-Restart VFB(AR) 2 V

Feedback Pull-up

Current IFB -1.3 -1.0 -0.7 µA

Absolute Maximum Ratings(1,4)

DRAIN Pin Peak Current(5): LNK454 ............... 400 mA (750 mA)

LNK456 ..............850 mA (1450 mA)

LNK457 ........... 1350 mA (2000 mA)

LNK458 ............1750 mA (2650 mA)

LNK460 ............2700 mA (5100 mA)

DRAIN Pin Voltage ……………………… ............. -0.3 V to 725 V

FEEDBACK Pin Voltage ……………………… ............ -0.3 to 9 V

BYPASS Pin Voltage ……………………… ................. -0.3 to 9 V

Lead Temperature(3) ....................................................... .........260 °C

Storage Temperature …………………. .................. -65 to 150 °C

Operating Junction Temperature(2) .........................-40 to 150 °C

Notes:

1. All voltages referenced to SOURCE, TA = 25 °C.

2. Normally limited by internal circuitry.

3. 1/16 in. from case for 5 seconds.

4. The Absolute Maximum Ratings speciﬁed may be applied,

one at a time without causing permanent damage to the

product. Exposure to Absolute Maximum Ratings for

extended periods of time may affect product reliability.

5. The higher peak Drain current (in parentheses) is allowed

while the Drain voltage is simultaneously less than 400 V.

Thermal Resistance

Thermal Resistance: D (SO-8C) Package:

(qJA) .................................. 100 °C/W(1), 80 °C/W(2)

(qJC) ........................................................ 30 °C/W(3)

K (eSOP) Package:

(qJA) .................................... 69 °C/W(1), 49 °C/W(2)

(qJC) ...........................................................2 °C/W(4)

V (eDIP) Package:

(qJA) .................................... 76 °C/W(1), 64 °C/W(2)

(qJC) ...........................................................2 °C/W(4)

Notes:

1. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610g/m2) copper clad,

with no external heat sink attached.

2. Soldered to 1 sq. in. (645 mm2), 2 oz. (610g/m2) copper clad,

with no external heat sink attached.

3. Measured on the SOURCE pin close to plastic interface.

4. Measured at the surface of exposed pad.

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 to +125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Control Function (cont.)

DRAIN Supply Current

IS1

VFB > VFB(SK)

(MOSFET not switching) 450 µA

IS2

VFB = 0 V

(MOSFET switching

at fMAX)

LNK454 530

µA

LNK456 585

LNK457 650

LNK458 730

LNK460 1050

BYPASS Pin

Charge Current

ICH1

VBP = 0 V,

TJ = 25 °C

LNK454 -5.9 -4.2 -2.5

mALNK456/457/458 -8.3 -5.9 -3.5

LNK460 -11.9 -8.5 -5.1

ICH2

VBP = 4 V,

TJ = 25 °C

LNK454 -3.4 -2.4 -1.4

mALNK456/457/458 -5.2 -3.7 -2.2

LNK460 -8.0 -5.7 -3.4

BYPASS Pin Voltage VBP 5.60 5.85 6.15 V

BYPASS Pin

Shunt Voltage VSHUNT IBP = 2 mA 5.9 6.2 6.6 V

Circuit Protection

Current Limit ILIMIT

di/dt = 160 mA/µs

TJ = 25 °C LNK454 255 290 325

di/dt = 325 mA/µs

TJ = 25 °C LNK456 510 580 650

di/dt = 490 mA/µs

TJ = 25 °C LNK457 800 910 1020

di/dt = 650 mA/µs

TJ = 25 °C LNK458 1012 1150 1288

di/dt = 980 mA/µs

TJ = 25 °C LNK460 1637 1860 2083

Leading Edge

Blanking Time tLEB TJ = 25 °C 160 200 ns

Current Limit Delay tILD TJ = 25 °C 150 ns

Thermal Shutdown

Temperature TSD 135 142 150 °C

Thermal Shutdown

Hysteresis TSD(H) 75 °C

BYPASS Pin Power-up

Reset Threshold Voltage VBP(RESET) 4.9 V



Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 to +125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Output

ON-State Resistance RDS(ON)

LNK454

ID = 26 mA

TJ = 25 °C 23.1 26.6

TJ = 100 °C 34.4 39.8

LNK456

ID = 53 mA

TJ = 25 °C 11.7 13.5

TJ = 100 °C 17.5 20.2

LNK457

ID = 85 mA

TJ = 25 °C 6.9 7.9

TJ = 100 °C 10.4 11.9

LNK458

ID = 110 mA

TJ = 25 °C 4.4 5.1

TJ = 100 °C 6.7 7.6

LNK460

ID = 170 mA

TJ = 25 °C 2.2 2.6

TJ = 100 °C 3.3 3.9

OFF-State Leakage IDSS1

VBP = 6.2 V, VFB > VFB(SK) , VDS = 580 V,

TJ = 125 °C 50 µA

Breakdown Voltage BVDSS VBP = 6.2 V, VFB > VFB(SK), TJ = 25 °C 725 V

DRAIN Supply Voltage 50 V

Auto-Restart OFF-Time tAR(OFF)

fMAIN = 50 Hz 1.28

fMAIN = 60 Hz 1.02

Auto-Restart Duty Cycle DCAR 33 %

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Typical Performance Characteristics

0 100 200 300 400 500 600

100

1000

PI-6005-060210

DRAIN Voltage (V)

DRAIN Capacitance (pF)

LNK454 0.3

LNK456 0.6

LNK457 1.0

LNK458 1.55

LNK460 3.1

Scaling Factors:

1.2

02 4 6 8 10 12 14 16 18 20

DRAIN Voltage (V)

DRAIN Current (A)

PI-6006-060210

0.6

0.4

0.2

LNK457 TCASE = 25 °C

LNK457 TCASE = 100 °C

0.8

LNK454 0.3

LNK456 0.6

LNK457 1.0

LNK458 1.55

LNK460 3.1

Scaling Factors:

Figure 7. Drain Capacitance vs. Drain Voltage.

Figure 9. Breakdown vs. Temperatue. Figure 10. Standard Current Limit vs. Temperature.

Figure 8. Drain Current vs. Drain Voltage.

1.1

1.0

0.9

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Breakdown Voltage

(Normalized to 25 °C)

PI-2213-012301

0.8

0.6

0.4

0.2

-50 0 50 100 150

Temperature (°C)

PI-6209-102910

1.2

Current Limit

(Normalized to 25 °C)

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

PI-4526-040110

D07C

3.90 (0.154) BSC

Notes:

1. JEDEC reference: MS-012.

2. Package outline exclusive of mold flash and metal burr.

3. Package outline inclusive of plating thickness.

4. Datums A and B to be determined at datum plane H.

5. Controlling dimensions are in millimeters. Inch dimensions

are shown in parenthesis. Angles in degrees.

0.20 (0.008) C

26.00 (0.236) BSC

4.90 (0.193) BSC

0.10 (0.004) C

0.10 (0.004) C 2X

A-B

1.27 (0.050) BSC

7X 0.31 - 0.51 (0.012 - 0.020)

0.25 (0.010) M C A-B D

0.25 (0.010)

0.10 (0.004)

(0.049 - 0.065)

1.25 - 1.65

1.75 (0.069)

1.35 (0.053)

0.10 (0.004) C



1.27 (0.050)

0.40 (0.016)

GAUGE

PLANE

0 - 8

1.04 (0.041) REF 0.25 (0.010)

BSC

SEATING

PLANE

0.25 (0.010)

0.17 (0.007)

DETAIL A

SEATING PLANE

Pin 1 ID





4.90 (0.193)

1.27 (0.050) 0.60 (0.024)

2.00 (0.079)

Reference

Solder Pad

Dimensions



SO-8C (D Package)

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

SIDE VIEW END VIEW

12×

PI-5748-082510

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost

extremes of the plastic body exclusive of mold flash,

tie bar burrs, gate burrs, and interlead flash, but

including any mismatch between the top and bottom of

the plastic body. Maximum mold protrusion is 0.007

[0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include inter-lead flash or protrusions.

5. Controlling dimensions in inches [mm].

6. Datums A & B to be determined at Datum H.

eSOP-12 (K Package)

TOP VIEW BOTTOM VIEW

Pin #1 I.D.

(Laser Marked)

0.023 [0.58]

0.018 [0.46]

0.006 [0.15]

0.000 [0.00]

0.098 [2.49]

0.086 [2.18]

0.092 [2.34]

0.086 [2.18]

0.032 [0.80]

0.029 [0.72]

Seating

Plane

Detail A

Seating plane to

package bottom

standoff

0.034 [0.85]

0.026 [0.65]

0.049 [1.23]

0.046 [1.16]

3 4

0.460 [11.68]

0.400 [10.16]

0.070 [1.78]

0.306 [7.77]

Ref.

0.350 [8.89]

0.010 [0.25]

Ref.

Gauge Plane

Seating Plane

0.055 [1.40] Ref.

0.010 [0.25]

0.059 [1.50]

Ref, Typ 0.213 [5.41]

Ref.

0.019 [0.48]

Ref.

0.022 [0.56]

Ref.

0.020 [0.51]

Ref.

0.028 [0.71]

Ref.

0.316 [8.03]

Ref.

0.356 [9.04]

Ref.

0.059 [1.50]

Ref, Typ

0.010 (0.25) M C A B

12×

0.016 [0.41]

0.011 [0.28]

DETAIL A (Not drawn to scale)

0.008 [0.20] C

2X, 6 Lead Tips

0.004 [0.10] C

0.004 [0.10] C A 2X

0.004 [0.10] C B

0 -

° 8°

123 4 5 6 6 1

7 12

0.217 [5.51]

0.321 [8.15]

0.429 [10.90]

0.028 [0.71]

0.067 [1.70] Land Pattern

Dimensions

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

SIDE VIEW

END VIEW

12×

Detail A

0.059 [1.50]

Ref, typ.

Notes:

1. Dimensioning and tolerancing per

ASME Y14.5M-1994.

2. Dimensions noted are determined

at the outermost extremes of the plastic

body exclusive of mold flash, tie bar

burrs, gate burrs, and interlead flash,

but including any mismatch between the

top and bottom of the plastic body. Maximum

mold protrusion is 0.007 [0.18] per side.

3. Dimensions noted are inclusive of plating

thickness.

4. Does not include inter-lead flash or

protrusions.

5. Controlling dimensions in inches [mm].

6. Datums A & B to be determined at Datum H.

7. Measured with the leads constrained to be

perpendicular to Datum C.

8. Measured with the leads unconstrained.

9. Lead numbering per JEDEC SPP-012.

eDIP-12 (V Package)

TOP VIEW

0.316 [8.03]

Ref.

Pin #1 I.D.

(Laser Marked)

Pin #1 I.D.

(Laser Marked)

0.350 [8.89]

0.070 [1.78]

1 2 3 4 5 6

12 11 10 9 8 7 7 12

0.059 [1.50]

Ref, typ.

0.213 [5.41]

Ref.

0.192 [4.87]

Ref.

0.436 [11.08]

0.406 [10.32]

0.023 [0.58]

0.018 [0.46]

0.092 [2.34]

0.086 [2.18]

0.049 [1.23]

0.046 [1.16] 0.022 [0.56]

Ref.

0.031 [0.80]

0.028 [0.72]

0.016 [0.41]

0.011 [0.28]

0.400 [10.16]

3 4

0.400 [10.16]

0.010 [0.25] Ref.

Seating Plane

0.412 [10.46]

Ref.

0.306 [7.77]

Ref.

0.104 [2.65] Ref.

0.356 [9.04]

Ref.

0.019 [0.48]

Ref.

0.028 [0.71]

Ref.

0.020 [0.51]

Ref.

BOTTOM VIEW

0.010 [0.25] M C A B

0.004 [0.10] C B

DETAIL A (Not drawn to scale)

0.004 [0.10] C A

5 ±

° 4°

PI-5556-110210

0.07 [1.78] 0.03 [0.76]

0.400 [10.16]

Mounting

Hole Pattern

Dimensions

Drill Hole 0.03 [0.76]

Round Pad 0.05 [1.27]

Solder Mask 0.056 [1.42]

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

Part Ordering Information

• LinkSwitch Product Family

• PL Series Number

• Package Identiﬁer

D SO-8C

K eSOP-12

V eDIP-12

• Package Material

G GREEN: Halogen Free and RoHS Compliant

• Tape & Reel and Other Options

Blank Standard Conﬁgurations

TL Tape & Reel, 2.5 k pcs minimum for D package, 1 k pcs minimum for K package.

LNK 454 D G - TL

Rev. A 11/01/10

LNK454/456-458/460

www.powerint.com

For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power

Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES

NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by

one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A

complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under

certain patent rights as set forth at http://www.powerint.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)

whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signiﬁcant

injury or death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, EcoSmart, Clampless, E-Shield, Filterfuse,

StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.

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Revision Notes Date

A Initial Release 11/01/10