SA303 SA303 P r o d u c t IInnnnoovvaa t i o n FFr roomm 3 Phase Switching Amplifier FEATURES Low Cost 3 Phase Intelligent Switching Amplifier Directly Connects to Most Embedded Microcontrollers and Digital Signal Controllers Integrated Gate Driver Logic with Dead-Time Generation and Shoot-through Prevention Wide Power Supply Range (8.5V To 60V) Over 10A Peak Output Current per Phase 3A Continuous Output Current per Phase Independent Current Sensing for each Output User Programmable Cycle-by-cycle Current Limit Protection Over-Current and Over-Temperature Warning Signals APPLICATIONS 3 phase brushless DC motors Multiple DC brush motors 3 independent solenoid actuators DESCRIPTION The SA303 is a fully integrated switching amplifier designed primarily to drive three-phase Brushless DC (BLDC) motors. Three independent half bridges provide over 10 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for the microcontroller to take appropriate action. A block diagram is provided in Figure 1. Additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of the microcontroller. Output current is measured using an innovative low loss technique. The SA303 is built using a multi-technology process allowing CMOS logic control and complementary DMOS output power devices on the same IC. Use of P-channel high side FETs enables 60V operation without bootstrap or charge pump circuitry. The Power Quad surface mount package balances excellent thermal performance with the advantages of a low profile surface mount package. Figure 1. BLOCK Diagram VS + VDD SC TEMP ILIM/D IS 1 Ia Ib Ic PWm Signals Fault Logic V s (p ha se A ) Ia ' At Ab P ha se A Ct Cb VDD VDD Ia ' Ib ' Ic' Ic' gate Control Bt Bb VDD Ib ' D IS 2 Control Logic V s (p ha se B & C ) O ut A A O ut B B P ha se B C O ut C P ha se C SGND SA303 Switching Amplifier P G N D (A & B ) P G N D (C ) GND SA303U http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2009 (All Rights Reserved) MAY 2009 APEX - SA303UREVA SA303 P r o d u c t I n n o v a t i o nF r o m 1. Characteristics and Specifications Absolute Maximum Ratings Parameter Symbol Min Max Units SUPPLY VOLTAGE VS 60 V SUPPLY VOLTAGE VDD 5.5 V (VDD+0.5) V LOGIC INPUT VOLTAGE (-0.5) OUTPUT CURRENT, peak, 10ms (Note 2) IOUT 10 A POWER DISSIPATION, avg, 25C (Note 2) PD 100 W TEMPERATURE, solder, 10sec TS 260 C TEMPERATURE, junction (Note 2) TEMPERATURE RANGE, storage 150 C TSTG TJ -55 125 C TA -40 125 C OPERATING TEMPERATURE, case Specifications Parameter Test Conditions (Note 1) Min Typ Max Units 1 V LOGIC INPUT LOW INPUT HIGH 1.8 V OUTPUT LOW 0.3 OUTPUT HIGH 3.7 OUTPUT CURRENT (SC, Temp, ILIM/DIS1) V V 50 mA POWER SUPPLY VS UVLO VS UNDERVOLTAGE LOCKOUT, (UVLO) 50 60 8.3 VDD 4.5 V V 5.5 V SUPPLY CURRENT, VS 20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V 25 30 mA SUPPLY CURRENT, VDD 20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V 5 6 mA CURRENT LIMIT Current Limit Threshold (Vth) 3.75 V Vth Hysteresis 100 mV OUTPUT CURRENT, continuous 25C Case Temperature 3 A Rising delay, td(rise) See Figure 10 270 ns Falling delay, td(fall) See Figure 10 270 ns Disable delay, td(dis) See Figure 10 200 ns Enable delay, td(dis) See Figure 11 200 ns Rise Time, t(rise) See Figure 11 50 ns Fall Time, t(fall) 50 ns On resistance Sourcing (P-Channel) 3A Load 400 m On resistance Sinking (N-Channel) 400 m 3A Load SA303U SA303 P r o d u c t I n n o v a t i o nF r o m Specifications, continued Parameter Test Conditions (Note 1) Min Typ Max Units THERMAL Thermal Warning 135 40 Thermal Warning Hysteresis RESISTANCE, junction to case Full temperature range TEMPERATURE RANGE, case Meets Specifications NOTES: C 1.25 -40 C/W 1.5 C/W 85 C * The specification of SA303A is identical to the specification for SA303 in applicable column to the left. 1. (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25C). 2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power dissipation to achieve high MTBF. 3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. Figure 2. 64-Pin QFP, Package Style HQ SA303U SA303 10 5 8 7.5 7 ONE PHASE SWITCHING FREQUENCy = 20kHz 50% DUTy CyCLE 20 30 40 50 VS SUPPLy VOLTAGE (V) VDD SUPPLY CURRENT ONE PHASE SWITCHING FREQUENCy = 20kHz 50% DUTy CyCLE 6.5 6 125C 5.5 25C 5 4.5 4 10 20 30 40 50 VS SUPPLy VOLTAGE (V) RDS(on),() RDS(on),() 40 ONE PHASE SWITCHING @ 50% DUTy CyCLE; VS=50V 20 0 50 VDD SUPPLY CURRENT 120 4.8 4.7 4.6 ONE PHASE SWITCHING @ 50% DUTy CyCLE; VS=50V 50 1 0.1 0.01 100 150 200 250 300 FREQUENCy (kHz) 4.9 5 (N-Channel) 100 150 200 250 300 FREQUENCy (kHz) 0.1 1 SENSE CURRENT (mA) 10 POWER DERATINg 100 80 60 40 20 0 -40 0 40 80 120 CASE TEMPERATURE, TC DIODE FORWARD VOLTAgE - TOP FET (P-Channel) 4 CURRENT (A) CURRENT (A) 60 ON RESISTANCE - TOP FET 4 3 2 1 80 0.8 0.75 (P-Channel) 0.7 0.65 0.6 VS=11 0.55 VS=13 0.5 0.45 VS=15 0.4 0.35 0.3 VS>17 0.25 0.2 0.15 0 1 2 3 4 5 6 7 8 9 10 IOUT,(A) DIODE FORWARD VOLTAgE - BOTTOm FET 0 0.5 100 4.5 0 ON RESISTANCE - BOTTOm FET 5 120 5 60 0.8 0.75 (N-Channel) 0.7 0.65 0.6 0.55 VS=11 0.5 VS=13 0.45 VS=15 0.4 0.35 VS=17 0.3 0.25 0.2 VS>22 0.15 0 1 2 3 4 5 6 7 8 9 10 IOUT,(A) 140 0 60 CURRENT SENSE 160 LOAD CURRENT (A) 25C 10 POWER DISSIPATION, PD VS SUPPLy CURRENT (mA) 125C 15 VS SUPPLY CURRENT 180 20 0 10 VDD SUPPLy CURRENT (mA) VS SUPPLY CURRENT VDD SUPPLy CURRENT (mA) VS SUPPLy CURRENT (mA) 25 P r o d u c t I n n o v a t i o nF r o m 3 2 1 0.7 0.9 1.1 1.3 FORWARD VOLTAGE (V) 1.5 0 0.5 0.7 0.9 1.1 1.3 FORWARD VOLTAGE (V) 1.5 SA303U SA303 P r o d u c t I n n o v a t i o nF r o m OUT C OUT C NC VS B & C VS B & C VS B & C VS B & C NC OUT B OUT B OUT B NC PGND A & B PGND A & B PGND A & B PGND A & B NC OUT A OUT A OUT A 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 3. External Connections OUT C 53 32 NC NC 54 31 VS A PGND C 55 30 VS A PGND C 56 29 VS A PGND C 57 28 NC HS 58 27 HS Table 1. Pin Descriptions Pin # Pin Name 29,30,31 51,52,53 55,56,57 3 61 63 1 5 VS (phase A) OUT C PGND (phase C) SC Cb Ct Ic Ib 7 ILIM/DIS1 SA303U Signal Type Power Power Output Power Logic Output Logic Input Logic Input Analog Output Analog Output 10 11 12 13 14 15 16 17 18 19 20 NC Bt NC Bb NC Ab NC At NC VDD NC 9 SGND Ia 8 21 NC 64 7 NC NC ILIM/DIS1 22 6 63 NC DIS2 Ct 5 23 4 62 Ib NC NC NC 24 3 61 SC TEMP Cb 2 HS 25 1 26 60 Ic 59 NC HS NC Simplified Pin Description High Voltage Supply (8.5-60V) supplies phase A only Half Bridge C Power Output High Current GND Return Path for Power Output C Indication of a short of an output to supply, GND or another phase Logic high commands C phase lower FET to turn on Logic high commands C phase upper FET to turn on Phase C current sense output Phase B current sense output As an output, logic high indicates cycle-by-cycle current limit, and logic low indicates normal operation. As an input, logic high places Logic Input/Output all outputs in a high impedance state and logic low disables the cycle-by-cycle current limit function. SA303 P r o d u c t I n n o v a t i o nF r o m Table 1. Pin Descriptions - Cont. Pin # 9 11 13 15 17 19 21 23 25 42,43,44 46,47,48,49 33,34,35 37,38,39,40 26,27,58,59 2,4,6,8,10, 12,14,16,18, 20,22,24,28, 32,36,41,45, 50,54,60,62, 64 Pin Name Signal Type Simplified Pin Description SGND Bt Bb Ab At VDD Ia DIS2 TEMP OUT B VS (phase B&C) OUT A PGND (phase A&B) HS Power Logic Input Logic Input Logic Input Logic Input Power Analog Output Logic Input Logic Output Power Output Power Power Output Power Mechanical Analog and digital GND - internally connected to PGND Logic high commands B phase upper FET to turn on Logic high commands B phase lower FET to turn on Logic high commands A phase lower FET to turn on Logic high commands A phase upper FET to turn on Logic Supply (5V) Phase A current sense output Logic high places all outputs in a high impedance state Thermal indication of die temperature above 135C Half Bridge B Power Output High Voltage Supply phase B&C Half Bridge A Power Output High Current GND Return Path for Power Outputs A&B Pins connected to the package heat slug NC --- Do Not Connect 1.2 Pin Descriptions VS: Supply voltage for the output transistors. These pins require decoupling (1F capacitor with good high frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. Note that VS pins 29-31 carry only the phase A supply current. Pins 46-49 carry supply current for phases B & C. Phase A may be operated at a different supply voltage from phases B & C. Both VS voltages are monitored for undervoltage conditions. OUT A, OUT B, OUT C: These pins are the power output connections to the load. NOTE: When driving an inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6) PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of this datasheet for more details. SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input commands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately 200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12k series resistor. Ab, Bb, Cb: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side N-channel FET off. If Ab, Bb, or Cb is high at the same time that a corresponding At, Bt, or Ct input is high, protection circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the top and bottom input signals. SA303U P r o d u c t I n n o v a t i o nF r o m SA303 At, Bt, Ct: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel FET off. Ia, Ib, Ic: Current sense pins. The SA303 supplies a positive current to these pins which is proportional to the current flowing through the top side P-channel FET for that phase. Commutating currents flowing through the backbody diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can be monitored with ADC inputs of a processor or external circuitry. The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this functionality are described in the applications section of this datasheet. ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA303. Pulling this pin to logic high places OUT A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the output of the current limit latch through a 12k resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature. SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure do to this may result in oscillations on the output pins during rising or falling edges. VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the SA303. This pin requires decoupling (at least 0.1F capacitor with good high frequency characteristics is recommended) to the SGND pin. DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high impedance state when pulled high. DIS2 has an internal 12k pull-down resistor and may therefore be left unconnected. TEMP: This logic level output goes high when the die temperature of the SA303 reaches approximately 135C. This pin WILL NOT automatically disable the device. The TEMP pin includes a 12k series resistor. HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be connected to GND. Neither the heat slug nor these pins should be used to carry high current. NC: These "no-connect" pins should be left unconnected. 2. SA303 OPERATION The SA303 is designed primarily to drive three phase motors. However, it can be used for any application requiring three high current outputs. The signal set of the SA303 is designed specifically to interface with a DSP or microcontroller. A typical system block diagram is shown in the figure below. Over-temperature, Short-Circuit and Current Limit fault signals provide important feedback to the system controller which can safely disable the output drivers in the presence of a fault condition. High side current monitors for all three phases provide performance information which can be used to regulate or limit torque. SA303U SA303 P r o d u c t I n n o v a t i o nF r o m Figure 4. System Diagram VDD SC TEMP ILIM/D IS 1 Vs + Vs (phase A) Vs (phase B&C) Fault Logic Current Ia monitor Ib Signals Ic BRUSHLESS MOTOR GND D IS 2 At Ab PWm Signals Bt Bb Control Logic gate Control A B C OUT A OUT B OUT C Ct Cb SGND SA303 Switching Amplifier M icrocontroller or DSC SGND GND Sensing circuits PGND (C) PGND (A&B) Sensor - Hall Sensors or Sensorless - Input from Stator leads SA303U SA303 P r o d u c t I n n o v a t i o nF r o m The block diagram in Figure 5 illustrates the features of the input and output structures of the SA303. For simplicity, a single phase is shown. Figure 5. Input and output structures for a single phase 12k SC Current Sense SC Logic Vdd Ia' Ref 12k I LIM/DIS1 Vth + _ Temp Sense _ + 12k TEMP Lim a Lim b Lim c Ia UVLO DIS2 12k Vs At Gate Control OUT A Ab PGND SGND X X >Vth X X X X X X X X X X X X SA303U Dis2 OUT A, OUT B, OUT C Ia, Ib, Ic 0 X 1 <Vth 0 <Vth 1 X ILIM/Dis1 0 0 1 1 Ab, Bb, Cb At, Bt, Ct TABLE 2. Truth Table X 0 0 X X 0 0 X High-Z PGND VS High-Z Comments Top and Bottom output FETs for that phase are turned off. Bottom output FET for that phase is turned on. Top output FET for that phase is turned on. Both output FETs for that phase are turned off. Voltage on Ia, Ib, or Ic has exceeded Vth, which causes ILim/Dis1 to go high. 1 X High-Z This internally disables Top and Bottom output FETs for ALL phases. X 1 High-Z Dis2 pin pulled high, which disables all outputs. Pulled Pulling the ILim/Dis1 pin high externally acts as a second disable input, X High-Z High which disables ALL output FETs. Determined Pulling the Dis2 pin low externally disables the cycle-by-cycle current limit Pulled 0 by PWM function. The state of the outputs is strictly a function of the PWM inputs. Low inputs X X High-Z If VS is below the UVLO threshold all output FETs will be disabled. SA303 P r o d u c t I n n o v a t i o nF r o m 2.1 LAYOUT CONSIDERATIONS Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing ensures normal operation. Poor routing and bypassing can cause erratic and low efficiency operation as well as ringing at the outputs. The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to prevent noise from contaminating the logic control signals. A low ESR capacitor of at least 25F per ampere of output current should be placed near the SA303 as well. Capacitor types rated for switching applications are the only types that should be considered. Note that phases B & C share a VS connection and the bypass recommendation should reflect the sum of B & C phase current. The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1F to 0.47F surface mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufficient. SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way that there is no motor current flowing in the logic and signal ground traces as parasitic resistances in the small signal routing can develop sufficient voltage drops to erroneously trigger input transitions. Alternatively, a ground plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This isolates noise between signal and power ground traces and prevents high currents from passing between the plane sections. Unused area on the top and bottom PCB planes should be filled with solid or hatched copper to minimize inductive coupling between signals. The copper fill may be left unconnected, although a ground plane is recommended. 2.2 FAULT INDICATIONS In the case of either an over-temperature or short circuit fault, the SA303 will take no action to disable the outputs. Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made regarding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case, the processor would recognize the condition as an external interrupt, which could be processed in software via an Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the disable inputs on the SA303. Figure 6 shows an external SR flip-flop which provides a hard wired shutdown of all outputs in response to a fault indication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condition with a GPIO. This circuit can be used in safety critical applications to remove software from the fault-shutdown loop, or simply to reduce processor overhead. Figure 6. External Fault Latch Circuit PWm SA303 PROCESSOR DIS2 SC TEMP In applications which may not have available GPIO, FAULT RESET GPIO the TEMP pin may be externally connected to the adjacent DIS1 pin. If the device temperature reaches LATCHED FAULT INTERRUPT ~135C all outputs will be disabled, de-energizing the motor. The SA303 will re-energize the motor when the device temperature falls below approximately 95C. The TEMP pin hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the device. 2.3 UNDER-VOLTAGE LOCKOUT The undervoltage lockout condition results in the SA303 unilaterally disabling all output FETs until VS is above the UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock 10 SA303U SA303 P r o d u c t I n n o v a t i o nF r o m out condition is in progress. The SA303 has two VS connections: one for phase A, and another for phases B & C. The supply voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis on the UVLO circuit prevents oscillations with typical power supply variations. Figure 7. Start-up Voltage and Current NON-LIMITED MOTOR CURRENT NON-LIMITED BACK EMF 2.4 CURRENT SENSE External power shunt resistors are not required LIMITED BACK EMF with the SA303. Forward current in each top, Pchannel output FET is measured and mirrored to the respective current sense output pin, Ia, Ib and Ic. By connecting a resistor between each curLIMITED MOTOR CURRENT rent sense pin and a reference, such as ground, a voltage develops across the resistor that is proportional to the output current for that phase. An ADC can monitor the voltages on these resistors for protection or for closed loop torque control in some application configurations. The current sense pins source current from the VDD supply. TIME Headroom required for the current sense circuit is approximately .5V. The nominal scale factor for each proportional output current is shown in the typical performance plot on page 4 of this datasheet. 2.5 CYCLE-BY-CYCLE CURRENT LIMIT In applications where the current in the motor is not directly controlled, both the average current rating of the motor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at startup. Because the output current of each upper output FET is measured, the SA303 is able to provide a very robust current limit scheme. This enables the SA303 to safely and easily drive virtually any brushless motor through a startup inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows starting current and back EMF with and without current limit enabled. If the voltage of any of the three current sense pins exceeds the current limit threshold voltage (Vth), all outputs are disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase's top side input goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (At, Bt, or Ct). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the width of the pulse. Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscillation. This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the absence of rising edges of At, Bt, and Ct except when commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset the current limit latch. SA303U 11 SA303 The current limit feature may be disabled by tying the ILIM/DIS1 pin to GND. The current sense pins will continue to provide top FET output current information. Typically, the current sense pins source current into grounded resistors which provide voltages to the current limit comparators. If instead the current limit resistors are connected to a voltage output DAC, the current limit can be controlled dynamically from the system controller. This technique essentially reduces the current limit threshold voltage to (Vth-VDAC). During expected conditions of high torque demand, such as start-up or reversal, the DAC can adjust the current limit dynamically to allow periods of high current. In normal operation when low current is expected, the DAC output voltage can increase, reducing the current limit setting to provide more conservative fault protection. 2.6 EXTERNAL FLYBACK DIODES P r o d u c t I n n o v a t i o nF r o m Figure 8. Current Limit Waveforms At INPUT Vth Ia OUTA ILIM/DIS1 External fly-back diodes will offer superior reverse recovery characteristics and lower forward voltage drop than the internal back-body diodes. In high current applications, external flyback diodes can reduce power dissipation and heating during commutation of the motor current. Reverse recovery time and capacitance are the most important parameters to consider when selecting these diodes. Ultra-fast rectifiers offer better reverse recovery time and Schottky diodes typically have low capacitance. Individual application requirements will be the guide when determining the need for these diodes and for selecting the component which is most suitable. 12 Figure 9. Schottky Diodes VS VS VS OUTA SA303 OUTB OUTC SA303U SA303 P r o d u c t I n n o v a t i o nF r o m Figure 10. Timing Diagrams TOP INPUT BOTTOM INPUT DISABLE OUTPUT td(fall) DELAy TIMING td(rise) 3. POWER DISSIPATION The thermally enhanced package of the SA303 allows several options for managing the power dissipated in the three output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation and switching losses. Output power dissipation depends on the quadrant of operation and whether external flyback diodes are used to carry the reverse or commutating currents. Switching losses are dependent on the frequency of the PWM cycle as described in the typical performance graphs. td(dis) td(dis) td(dis) td(dis) Figure 11. OUTPUT RESPONSE 80% OUTPUT 20% The size and orientation of the heatsink must be selected to manage the average power dissipation t(rise) t(fall) of the SA303. Applications vary widely and various thermal techniques are available to match the reTOP INPUT quired performance. The patent pending mounting technique shown in Figure 12, with the SA303 inverted and suspended through a cutout in the PCB BOTTOM INPUT is adequate for power dissipation up to 17W with the HS33, a 1.5 inch long aluminum extrusion with four fins. In free air, mounting the PCB perpendicular to the ground, such that the heated air flows upward along the channels of the fins can provide a total JA of less than 14 C/W (9W max average PD). Mounting the PCB parallel to the ground impedes the flow of heated air and provides a JA of 16.66 C/W (7.5W max average PD). In applications in which higher power dissipation is expected or lower junction or case temperatures are required, a larger heatsink or circulated air can significantly improve the performance. 4. ORDERING AND PRODUCT STATUS INFORMATION MODEL TEMPERATURE PACKAGE PRODUCTION STATUS SA303-IHZ -25 to 85C 64 pin Power QFP (HQ package drawing) Samples Available 1Q09 SA303U 13 SA303 P r o d u c t I n n o v a t i o nF r o m Figure 12. Heatsink Technique Patent Pending Contacting Cirrus Logic Support For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact tucson.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex and Apex Precision Power are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 14 SA303U