! | 2 nt lr ADVANCE INFORMATION 270213 FAST PIPELINED 1M (64K x 16) EPROM a Pipelined Interface m Excellent Drive Capability Clock for Data Latching 4 mA Source/16 mA Sink Current Optional Synchronous Chip Select Handles Large Fanout m@ Quick-Pulse Programming g@ High-Performance/Low Power CMOS 4 Second Throughput for Automated High Density Memory With 100 mA Manufacturing Icc Maximum gw Very High Speed m Versatile Package Options Supports up to 20MHz Pipelined Standard DIP 80386/376s at Zero Wait-States Compact Surface-Mount PLCC** The intel 27C213 is a high performance 1 Megabit erasable programmable read-only memory organized as 64K words of 16 bits each. Its density and word-wide configuration, combined with its pipelined bus interface, provides a high integration firmware solution for todays speed-critical applications. ' The 27C213 supports the pipelined bus architectures of the Intel 80376 and 80386 microprocessors. Pipelin- ing relaxes memory interface requirements by utilizing an overlapping early address, effectively stretching the read operation an additional bus cycle. Thus, much higher bus bandwidths are achievable than with a standard interface. An 80386/376 design employing the 27C213 can accommodate system clock rates up to 20 MHz at zero wait-states, while utilizing slower, less expensive interface logic in 16 MHz versions. The 1M bit capacity is well suited for high-end embedded control applications. The 27C213s simple interface and X16 organization help minimize overall chip count. The 27C213 is available in two package versions. The standard 40-pin Dual-In-Line Package (DIP) provides for conventional device handling and socketing. The 44-lead OTPTM (One-Time-Programmable) Plastic Leaded Chip Carrier (PLCC) allows lowest cost, automated, surface-mount manufacturing. The 27C213 is manufactured on Intel's advanced CHMOS? III-E, a process optimized for high performance. *CHMOS is a patented process of Intel Corporation. **PLCC package availability TBD October 1989 4-322 Order Number: 290227-001! ADVANCE INFORMATION 270213 270213 4m | 2M <= 2m | 4M Vep | Vpp ver C1 40 vec Veo | Voc ce | ce C/ipC]2 397 Pu Pam | Av, SCs 38 FI nc Ow | O15 . A Are | Ate 1404 37415 O14 | Ore A Ais | Ais 130s 36f A14 O13 | O13 A Ava | Ata 12036 359 13 Ore | Ore C7 34 At2 Ais | Ata Pin Names Os | Ory 0 A Ai2 | Aiz oO . 10098 s3p11 A AM Ao-Ai7 ADDRESSES 10 | O10 sce 32P9 410 m4 CiEp CHIP ENABLE/CLOCK Os | Os sc] 10 31PAs Ato | Ato Og | Os q Ag | As Gp/S/Ss } CHIP SELECT/PROGRAM ono 11 30/2) GND OUTPUT ENABLE GND | GND ordi noha s GND | GND 09-015 OUTPUTS .. Sscqis 2847 n n P PROGRAM ENABLE Oo. o Oschi4 2746 he he NC. NO INTERNAL CONNECT O. }, Sacdis 264s ae | AS DU. DON'T USE 03 | Os 3c 16 2p 44 Aa | Ag 2417 24043 Os | Og Az | Ag Orta 23042 01 0; Ag Ao. Socata 22041 0 | % &p/S/S5 CI 20 21f940 Ar] Ay OE | OE prees Ao | Ao 290227-1 Figure 1. Cerdip Pin Configurations 4M (256K x 16) Atl f 2M (128K x 16) { j[4ts 27210 (64K x 16)| 913) | O14! | O15] [cep] | ver! | Nc] vec}! P ] | Nc] [Ass] 1 Arg Cor en et a ed od a he. 6 65 4 3 2 44 43 42 41 40 12 [} ' 39 | Arg O17 [Is 38 | Ay 10 [| 9 37 | Ay Og [}ro 36 | Ay os [| " 44 LEAD PLCC 38 | 9 GND [| 12 TOP VIEW 34 | IGN NC [| 13 33 | NC 07 [| 14 32 | Ag 0% [| 15 31 | Ay o5| [Ji sol] [As 04 [| 17 29 | As 18 #19 20 21 22 23 24 25 26 27 28 CID IL ID ILLICIT CT 03 | {Oz | O11} 90 oe NC} | Ao }] Ar} ] 42] As |] Aa 290227-2 Figure 2. PLCC Lead Configuration 4-323| SOS" PE Set eee Sua eee 2 270213 ADVANCE INFORMATION ABSOLUTE MAXIMUM RATINGS* Operating Temperature During *Notice: Stresses above those listed under Abso- lute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and Read...... 0. cece eee eee ne eens 0C to + 70C functional operation of the device at these or any Temperature Under Bias......... 10C to +80C other conditions above those indicated in the opera- Storage Temperature .......... 68C to + 125C tional sections of this specification is not implied. Ex- All Input or Output Voltages with posure to absolute maximum rating conditions for u wi extended periods may affect device reliability. Respect to Ground ...........- 0.6V to + 6.5V pe y device reliability Voltage on Ag with NOTICE: Specifications contained within the Respect to Ground........... 0.6V to + 13.0V following tables are subject to change. Vpp Supply Voltage with Respect to Ground During Programming .... 0.6V to + 14V Voc Supply Voltage with Respect to Ground........ 0.6V to + 7.0V READ OPERATION D.C. CHARACTERISTICS orc < Ta < +70C, Voc + 10% Symbol Parameter Notes Min Typ(3) Max Units Test Condition lu Input Load Current 0.01 1.0 BA | Vin = OV to Voc ILo Output Leakage Current +10 pA | Vout = OV to Voc loc, Voc Current Active 4 50 mA | Gp/S/Ss = Vit f = 5 MHz, lout = OMA Ipp1 Vpp Current Read 6 10 BA | Vpp = Voc Vit Input Low Voltage (+ 10% Supply) 1 -05 0.8 Vin input High Voltage (+ 10% Supply) 2.0 Voc + 0.5 VoL Output Low Voltage 0.4 lo = 2.1 mA Vou Output High Voltage Voc 0.8V lon = ~400 pA los Output Short Circuit Current 5 100 mA NOTES: 1. Minimum D.C. input voltage is 0.5V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. Maximum D.C. voltage on output pins is Voc + 0.5V which may overshoot to Vcc + 2V for periods less than 20 ns. 2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS and Automotive versions. 3. Typical limits are at Voc = 5V, Ta = 125C. 4. Maximum current value is with outputs Og to O15 unloaded. 5. Output shorted for no more than one second. No more than one output shorted at a time. log is sampled but not 100% tested. 6. Maximum active power usage is the sum of Ipp and Igc. The maximum current value is with no loading on outputs Oo to 0; 5. 4-324intel 270213 ADVANCE INFORMATION EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are available with 168 +8 hour, 125C dynamic burn-in PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS using Intels standard bias configuration. This pro- Type Operating Burn-in 125C cess exceeds or meets most industry specifications Temperature (hr) of burn-in. The standard EXPRESS EPROM operat- 0 ing temperature range is 0C to 70C. Extended op- Q OC to + 70C 168 +8 erating temperature range ( 40C to +85C) EX- T - 40C to + 85C None L 40C to +85C 168 +8 A.C. CHARACTERISTICS 270213-55V05 Symbol Characteristics 270213-45V05 270213-55V 10 Units Min Max Min Max tAVCH Address Valid to Clock 45 55 ns tCHAX Address Hold from Clock 0 0 ns tcHav) Clock to Valid Output 40 50 ns tcHoz'4) Clock to Output Tri-state for 15 21 ns Synchronous Chip Deselect, Ss tcHcL: tcLcH | Clock Pulse Width 25 25 ns tsvcH Setup Time to Clock for 10 - 10 ns Synchronous Chip Select, Ss tcHsx Hold Time for Sync. Select 10 10 ns tcnax'4) Data Hold Time From Clock ns tsHax'4) Data Hold Time From Select ns tsLav@) Valid Output Delay from 35 40 ns Asynchronous Chip Select, S . tsHaz'4) Output Tri-state from 10 10 ns Asynchronous Chip Deselect, S NOTES: 1. Voc current assumes no output loading, i.e., low = lo, = O mA. 2.D = Cerdip, N = PLCC. 3. A derating factor of 6 ns/100 pF should be used with output loading greater than 30 pF. This derating factor is only sampled and not 100% tested. 4. These parameters are only sampled and not 100% tested. 4-325At ce ER EE EPP intel w7e213 Ss: ADVANGE INFORMATION A.C. WAVEFORMSPIPELINED BUS APPLICATION (80376/80386) __ READ SETUP READ taveH tonax ADORESS ADDRESS 0 ADDRESS 1 -! Ol ol DATA 290227-3 A.C. WAVEFORMS (ASYNCHRONOUS CHIP SELECT) +_ READ SETUP READ ke tavcH tonax P tum tov . tlcH tsyoz! t Vv = SQ t sHox! . a, tcHov DATA i x DATA 0 DATA 1 > 290227 -4 NOTE: 1. These parameters are only sampled and not 100% tested. 4-326intel o7c21g Ss: AD WANE INFORMATION A.C. CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%)....... 5ns input Pulse Levels............. 0. cece OV to 3.0V Input Timing Reference Level ................ 15V Output Timing Reference Level .............. 1.5V CAPACITANCE(1) T, = 25C, f = 1MHz Parameter T Max | Unit | Conditions 4 8 Vin = OV 8 12 Vv = 0V 18 25 Vpp = OV A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT ; 2.01V INPUTS x TEST POINTS x OUTPUT off 1002 DEVICE 290227-5 UNDER ouT TEST AC. testing inputs are driven at 3.0V for a Logic 1 and OV for a eL Logic 0. Timing measurements are made at 1.5V. Rise and fall times are 5 ns or less. . = CL = 30 pF 290227-6 C, Includes Jig Capacitance Table 1. 27C213 Mode Selection Mode C/Ep P Gp/Ss/S Ao Ag Ag Vpp Vec OUT Read Async (S) Sf xX x xX x x x Voc Prior Setup Sync (Ss) ~ x Vit x x x xX Voc Prior Read Async (S) Xx X Vit X X X X Voc Dout Sync (Ss) a X X X X X X Voc Dout Deselect Async x x Vin x xX x xX Voc HiZ Sync / x Vin X x x X Voc Hi Z Programming VIL Vit Vin Xx x xX . * Din Program Verify Vit Vin Vit xX x xX * . Dout Program Inhibit Vin xX xX xX x x * . HiZ Program Sync Ss ViL ViL Vin X Vu xX * * Hi Z Program Verify Ss Vit Vin Vit xX Vy x . * Do ID: Manuf (#) ~ Vip Vie Vie Vit xX | Vy x Voc | 0089H Device (#) Vit Vin ViL Vin x Vu xX Voc 11EDH NOTES: X: can be either Vi_ or Vin *: See Table 2 for Voc and Vpp programming voltages Vy = 12.0V +0.5V #: A1-A8, A10-A16 = Vi_ ~~: Low to high transition 1. Sampled, but not 100% tested. 4-327! | intel 276213 ADVANCE INFORMATION READ MODE The 270213 read operation is synchronous. Data registers on the output buffers (Figure 3) allow high- bandwidth, pipelined read operations without the ad- ditional components that would normally be re- quired. The chip select (output enable) can be programmed to be synchronous (Sg) or left in the default asyn- chronous state (S) (Figure 3). The chip select is pro- grammed to be synchronous in pipelined bus appli- cations so the data output triggers off the rising edge of the clock (C) signal. PIPELINED BUS APPLICATION (80376 OR 80386) The 27C213 pipelined EPROM interfaces with the 80376/80386 pipelined bus when programmed in the synchronous chip select mode. Figure 4 shows a 376 embedded processor with the 27C213 in a simple embedded system. Valid address information must be stable for the minimum address setup time (tayvcH) before the data can be shifted to the outputs. The data is loaded in the data registers on the rising edge of the 27C213s C. The same C edge latches the synchronous chip select state into the chip select register. To activate the next output, the Ss input must be low before the C rising edge. Following the rising edge of the C, the outputs become valid (tcHav)- To deselect the device in the next output state, the Ss must be high for at least the synchronous select setup time (tgycH) before the C rising edge. Follow- ing the rising edge of the C, the outputs become tri- stated (tcHaz)- DATA INPUT BUFFERS REGISTER OUTPUT BUFFER 64K X 16 ADDRESS EPROM ARRAY DQ DATA PROGRAMMABLE > SYNCHRONOUS SELECT ak CHIP SELECT REGISTER Sg OR S 4 DQ ee 55 290227-7 Figure 3. 27C213 Functional Diagram 4-328a inte! 270213 ADVANGE INFORMATION cLK2 CLOCK PCLK | GENERATOR ADDRESS BUS , cLK 80376 | READY Bus | 270213 CONTROLLER |___S . DATA BUS 290227-8 Figure 4. 27C213 in Simple 80376 Embedded System Buffering may be needed to avoid bus contention when different types of pipelined memories are bussed together. For common 27C213s with syn- chronous chip selects, the chip deselect times are sufficiently fast to minimize active output overlap. The synchronization of one devices selection with anothers deselection is accomplished through com- mon clock inputs (C must be common with multiple synchronously selected devices). Upgrade Path Future upgrades to 4M-bits are easily accomplished due to the standardized pin configuration of the 270213. When the 27C213 is in the Read Mode (Vpp < Vcc) the P, N.C., and the Vpp inputs become non-functional and may be either Vi_ or Viz. This allows address lines A;gA17 to be routed directly to these inputs in anticipation of future density up- grades. Systems designed for 1M-bit program mem- ories today can be upgraded to higher densities (4M-bit) in the future with no circuit board changes. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. It is recom- mended that a 0.1 F ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor for low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 F bulk electrolytic capacitor should be used between Vcc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces. PROGRAMMING MODES (See Note) Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure (CERDIP EPROMs only). The device is in the programming mode when Vpp is raised to its programming voltage (See Table 2) and C/Ep and P are both at TTL tow. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. NOTE: Programming, Program Verify and Program Inhibit function asynchronously when Vpp is raised above 10V. When Vpp is in a very high voitage mode C/Ep converts. to Ep (similar to CE) and &,/8/8e functions similar to a standard OE pin. Program Inhibit Programming of multiple EPROMs in parallel with different data is easily accomplished by using the Program inhibit mode. A high-level C/Ep or P input inhibits the other devices from being programmed. Except for C/Ep, all like inputs (including Gp/S/Ss) of the parallel EPROMs may_be common. A TTL low-level pulse applied to the P input with Vpp at its programming voltage and C/Ep at TTL-Low will pro- gram the selected device. 4-329intel 27213 ADVANCE INFORMATION Program Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with C/Ep at Vic. Gp/S/Ssg at Vi_, P at Vin and Vpp and Vcc at their programming voltages. inteligent Identifier Mode The intgligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25C +5C am- bient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line Ag of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line Ag from Vj, to Viy. All other address lines must be held at Vi. during the intgligent Identifier Mode. Byte 0 (Ap = ViL) represents the manufacturer code and byte 1 (Ag = Vip) the device identifier code. These two identifier bytes are given in Table 1. ERASURE CHARACTERISTICS (FOR CERDIP EPROMS ONLY) The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range. Data shows that constant ex- posure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 .W/cm2 power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 nW/ cm2). Exposure of the device to high intensity UV light for longer periods may cause permanent dam- age. Quick-Pulse Programming Algorithm Intels 27C213 EPROMs are programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the throughput time in the production programming environment. This algo- rithm allows these devices to be programmed as fast as eight seconds. Actual programming time is a function of the PROM programmer being used. The Quick-Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a word veri- fication to determine when the addressed word has been successfully programmed. Up to 25 100 ys pulses per word are provided before a failure is rec- ognized. A flow chart of the Quick-Pulse Program- ming Algorithm is shown in Figure 5. For the Quick-Pulse Programming Algorithm, the en- tire sequence of programming pulses and word veri- fications is performed at Voc = 6.25V and Vpp at 12.75V. When programming of the EPROM has been completed, all data words should be compared to the original data with Vcc = Vpp = 5.0V. 4-330ia ADVANCE INFORMATION 27213 ADDRESS = FIRST LOCATION Voc = 6.254 Vpp = 12.75V PROGRAM ONE 100 ys PULSE INCREMENT X VERIFY WORD. LAST ADDRESS? Vv. DEVICE FAILED - INCREMENT ADDRESS Voc = Vpp = 5.0 COMPARE ALL WORDS TO ORIGINAL DATA PASS FAIL DEVICE PASSED 290227-9 Figure 5. Quick-Pulse Programming Algorithm 4-3311 inte! a7c21g Ss: ADVANCE INFORMATION D.C. PROGRAMMING CHARACTERISTICS 1, = 25C +5C Symbol Parameter Limits Conditions* Min | Max | Unit (Note 1) lu Input Current (All Inputs) 1 pA Vin = Vic or Vin ViL Input Low Level (All Inputs) 0.1 0.8 Vv Vin Input High Level 2.4 6.5 Vv VoL Output Low Voltage During Verify 0.45 Vv lo. = 2.1mA Vou Output High Voltage During Verify 3.5 Vv lon = 2.5mA loce) Voc Supply Current (Program & Verify) 50 mA Ippo Vpp Supply Current (Program) 50 mA C/Ep = Vit Vip Ag intgligent Identifier Voltage 11.5 12.5 Vv Vep Quick-Pulse Programming Algorithm 12.5 13.0 Vv C/E, = PGM = Vit Voc Quick-Pulse Programming Algorithm 6.0 6.5 Vv AC. PROGRAMMING CHARACTERISTICS Ta = 28C +5C (See Table 2 for Vcc and Vpp voltages.) Symbol Parameter Limits Conditions* Min | Typ | Max | Unit (Note 1) taveL Address Setup Time 2 ps toza- Gp/S/Sg Setup Time 2 ps tovec Data Setup Time 2 ps t6Hax Address Hold Time 0 ps tpHDx Data Hold Time 2 ps tcgHox | Gp/S/Sg High to Output Float Delay | 0 130 | ns | (Note 2) types Vpp Setup Time 2 ps tycs Voc Setup Time 2 ps teLPL C/Ep Setup Time 2 ps tpLPH P Initial Program Pulse Width 95 | 100 | 105 ps | Quick-Pulse Programming taLav Data Valid from Gp/S/Sg 150 | ns taHPL Souptime Addr 1 ys | A8=VH NOTES: 1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. This parameter is only sampied and is not 100% tested. Output Float is defined as the point where data is no longer drivensee timing diagram. 3. The maximum current value is with outputs Og~O45 unloaded. 4-332ia 270213 intel ADVANCE 1 NFORMATION PROGRAMMING WAVEFORMS VERIFY Vin ADDRESSES AODRESS STABLE Va. Ls r taver > DATA DATA IN STABLE L Ma r "over tpHox 12.754 HIGH Z DATA OUT vau } tonox 5.0V tyes ) 6.25V Voc 5.0V < z 3 ves ny) C/Ep Vi tepL *pLeH I- ozo. Yui &p/S/Ss \ [* *ecav "I Va. KY 290227-10 Figure 6. 27C213 Programming Waveforms NOTES: 1. The Input Timing Reference Level is 0.8V for Vi_ and 2V for a Viy. 2. tgtav and tguax are characteristics of the device but must be accommodated by the programmer. 3. When programming the 27C213, a 0.1 wF capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device. 4-333intel o7c213 Ss: ADVANCE INFORMATION PROGRAMMING WAVEFORMS PROGRAM VERIFY v 1H y - ADDRESSES x ADDRESS STABLE Vi kK 7 tavPL +| tonax y 1H y HIGH Z DATA DATA IN STABLE DATA OUT VALIO << Va X J teuox r- tove, *1 *cHax 12.75V r Vpp / 5.0V ves 6.25V V SJ 5. ves v ov 1H C/Ep Vi teepL *} y, a \ 7 tLe Vea &p/3/5 \ y tanpL *| 12.0 \ Van Figure 7. Synchronous Chip Select Programming Waveform 290227-11 NOTES: 1. The Input Timing Reference Level is 0.8V for Vi, and 2V for a Viy. 2. tog and tpgp are characteristics of the device but must be accommodated by the programmer. 3. When programming the 27C213, a 0.1 wF capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device. 4. Program verify for synchronous chip select is done on Do. 4-334