March 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C31026B
3.3 V 64K X 16 CMOS SRAM
3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10
Features
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 288 mW / max @ 10 ns
• Low power consumption: STANDBY
- 18 mW / max CMOS I/O
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
64 K × 16
Array
OE
CE
WE Column decoder
Row decoder
A0
A1
A2
A3
A4
A5
A7
VCC
GND
A8
A9
A10
A11
A12
A13
A14
A15
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6 5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3 3
A2 4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44 A6
A7
OE
A5
AS7C31026B
Selection guide -10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access ti me 5678ns
Maximum operating current 80 75 70 65 mA
Maximum CMOS standby current 5555mA
Pin arrangement
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Functional description
The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words
× 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications.
When CE is high, the device enters standby mode. A write cycle is accom plishe d by asse rting wr ite enable (WE ) an d chip ena ble (CE). Data
on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE ).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry
standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: H = high, L = low, X = don’t care.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT –20mA
Truth table
CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode
H X X X X High Z High Z Standby (ISB), ISBI)
LHLLHD
OUT High Z Read I/O0–I/O7 (ICC)
L H L H L High Z DOUT Read I/O8–I/O15 (ICC)
LHLLLD
OUT DOUT Read I/O0–I/O15 (I CC)
LLXLL D
IN DIN Write I/O0–I/O 15 (ICC)
LLXLHD
IN High Z Write I/O0–I/O7 (ICC)
L L X H L High Z DIN Write I/O8–I/O15 (ICC)
L
LH
XH
XX
HX
HHigh Z High Z Output disable (ICC)
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VIL = -1.0V for pulse width less than 5ns
VIH = VCC + 1.5V for pulse width less than 5ns
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 3.0 3.3 3.6 V
Input voltage VIH 2.0 – VCC + 0.5 V
VIL –0.5 – 0.8 V
Ambient operating temperature commercial TA0– 70o C
industrial TA–40 – 85 o C
DC operating characteristics (over the operating range)1
Parameter Sym Test conditions
-10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max
Input leakage
current | ILI | VCC = Max
VIN = GND to VCC –1–1–1–1µA
Output leakage
current | ILO |
VCC = Max
CE = VIH,
VOUT = GND to VCC
–1–1–1–1µA
Operating power
supply current ICC
VCC = Max,
CE ≤ VIL, IOUT = 0mA
f = fMax
–80–75– 70 – 65mA
Standby
power supply
current
ISB VCC = Max,
CE ≥ VIH, f = fMax –30–25–20–20
mA
ISB1
VCC = Max, CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or
VIN ≥ VCC–0.2 V, f = 0 –5–5–5–5
mA
Output
voltage VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0 V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF
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Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read cycle (over the operating range)3,9
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10–12–15–20–ns
Address access time tAA –10–12–15–20ns3
Chip enable (CE) access time tACE –10–12–15–20ns3
Output enable (OE) access time tOE –5–6–7–8ns
Output hold from address change tOH 3–3–3–3–ns5
CE low to output in low Z tCLZ 3–3–3–3–ns4, 5
CE high to output in high Z tCHZ –3–3–4–5ns4, 5
OE low to output in low Z tOLZ 0–0–0–0–ns4, 5
Byte select access time tBA –5–6–7–8ns
Byte select Low to low Z tBLZ 0–0–0–0–ns4, 5
Byte select High to high Z tBHZ –5–6–6–8ns4, 5
OE high to output in high Z tOHZ –5–6–7–8ns4, 5
Power up time tPU 0–0–0–0–ns4, 5
Power down time tPD – 10 – 12 – 15 20 ns 4, 5
Undefined output/don’t careFalling inpu tRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
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Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
Write cycle (over the operating range) 11
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10 – 12 – 15 – 20 – ns
Chip enable (CE) to write end tCW 8–9–10–12– ns
Address setup to write end tAW 8–9–10–12– ns
Address setup time tAS 0–0–0–0–ns
Write pulse width t WP 7 – 8 – 9 – 12 – ns
Write recovery time tWR 0–0–0–0–ns
Address hold from end of write tAH 0–0–0–0–ns
Data valid to write end tDW 5 – 6 – 8 – 10 – ns
Data hold time tDH 0–0–0–0–ns 5
Write enable to output in high Z tWZ – 5 – 6 – 7 – 8 ns 4, 5
Output active from write end tOW 1 – 1 – 1 – 2 – ns 4, 5
Byte select low to end of write tBW 7–8–9–9–ns
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
AS7C31026B
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Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data undefined high Z
Data valid
t
AH
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
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AC test conditions
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is high for read cycle.
7CE
and OE are low for read cycle.
8 Address is valid prior to or coincident with CE transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
255
Ω
C
13
320
Ω
GND
+3.3 V
Figure B: 3.3 V Output load
168
Ω
Thevenin Equivalent:
D
OUT
+1.728 V
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pulse
2 ns
D
OUT
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5
AS7C31026B
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Package dimensions
44-pin TSOP 2
Min
(mm) Max
(mm)
A1.2
A1 0.05 0.15
A2 0.95 1.05
b0.30 0.45
c0.120 0.21
D18.31 18.52
E10.06 10.26
He 11.68 11.94
e0.80 (typical)
l0.40 0.60
D
He
1234567891011121314
4443424140 3938 3736 35 343332 31
1516
3029
1718 1920
2827 2625
c
l
A1
A2
e
44-pin TSOP 2
0–5
°
21
24
22
23
E
A
b
Seating
plane
44-pin SOJ
44-pin SOJ
400 mil
Min (in) Max (in)
A0.128 0.148
A10.025 –
A20.105 0.115
B0.026 0.032
b0.015 0.020
c0.007 0.013
D1.120 1.130
E0.370 NOM
E10.395 0.405
E20.435 0.445
e0.050 NOM
e
Pin 1
A1
b
B
AA2
E2
E1
D
c
E
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Note:
Add suffix ‘N’ to the above part number for lead free parts (Ex. AS7C31026B-10JCN)
Ordering codes
Package\Access time Volt/Temp 10 ns 12 ns 15 ns 20 ns
Plastic SOJ, 400 mil 3.3 V commercial AS7C31026B-10JC AS7C31026B-12JC AS7C31026B-15JC AS7C31026B-20JC
3.3 V industrial AS7C31026B-10JI AS7C31026B-12JI AS7C31026B-15JI AS7C31026B-20JI
TSOP 2, 10.2 x 18.4 mm 3.3 V commercial AS7C31026B-10TC AS7C31026B-12TC AS7C31026B-15TC AS7C31026B-20TC
3.3 V industrial AS7C31026B-10TI AS7C31026B-12TI AS7C31026B-15TI AS7C31026B-20TI
Part numbering system
AS7C X 1026B –XX X X X
SRAM
prefix Voltage:
3 = 3.3 V CMOS
Device
number Access
time
Package:
J = SOJ 400 mil
T = TSOP 2, 10.2 x 18.4 mm
Temperature range:
C = commercial: 0° C to 70° C
I = industrial: -40° C to 85° C
N=Lead Free
Part
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C31026B
Document Ve rsion: v 1.3
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective c ompanies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Allianc e's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
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AS7C31026B
