Product Brief – JN5139
IEEE802.15.4 and ZigBee Wireless Microcontrollers
© Jennic Ltd 2008 – www.jennic.com JN5139-PB v1.22 Page 1 of 2
Features: Transceiver
2.4GHz IEEE802.15.4 compliant
128-bit AES security processor
MAC accelerator with packet
formatting, CRCs, address check,
auto-acks, timers
Integrated power management
and sleep oscillator for low power
On-
chip power regulation for 2.2V
to 3.6V battery operation
Deep sleep current 0.2µA
Sleep current with active sleep
timer 1.3µA
Needs minimum of external
components (< US$1 cost)
Rx current 34mA
Tx current 34mA
Receiver sensitivity -97dBm
Transmit power +3dBm
Features: Microcontroller
32-bit RISC processor sustains
16MIPs with low power
192kB ROM stores system code,
including protocol stack
96kB RAM stores system data
and optionally bootloaded
program code
48-byte OTP eFuse, stores MAC
ID on-chip, offers AES based
code encryption feature
4-input 12-bit ADC, 2 11-bit
DACs, 2 comparators
2 Application timer/counters,
3 system timers
2 UARTs (one for debug)
SPI port with 5 selects
2-wire serial interface
Up to 21 GPIO
Industrial temperature range
(-40°C to +85°C)
8x8mm 56-lead QFN
Lead
-free and RoHS compliant
Overview
The JN5139 is a low power, low cost wireless microcontroller suitable for
IEEE802.15.4 and ZigBee applications. The device integrates a 32-bit RISC
processor, with a fully compliant 2.4GHz IEEE802.15.4 transceiver, 192kB of ROM,
96kB of RAM, and a rich mixture of analogue and digital peripherals.
The cost sensitive ROM/RAM architecture supports the storage of system
software, including protocol stacks, routing tables and application code/data. An
external flash memory is used to store application code that is bootloaded into
internal RAM and executed at runtime.
The device integrates hardware MAC and AES encryption accelerators, power
saving and timed sleep modes, and mechanisms for security key and program
code encryption. These features all make for a highly efficient, low power, single
chip wireless microcontroller for battery-powered applications.
Block Diagram
Benefits
Single chip integrates transceiver
and microcontroller for wireless
sensor networks
Cost sensitive ROM/RAM
architecture, meets needs for
volume application
System BOM is low in component
count and cost
Hardware MAC ensures low
power consumption and low
processor overhead
Extensive user peripherals
Pin compatible with JN5121 for
easy migration
Applications
Robust and secure low power
wireless applications
Wireless sensor networks,
particularly IEEE802.15.4 and
ZigBee systems
Home and commercial building
automation
Remote Controls
Toys and gaming peripherals
Industrial systems
Telemetry and utilities
(e.g. AMR)
Optional
32-bit
RISC CPU
Timers
UARTs
12-bit ADC,
comparators
11-bit DACs,
temp sensor
2-wire serial
SPI
RAM
8kB - 96kB
128-bit AES
Encryption
Accelerator
2.4GHz
Radio
ROM
192kB
Power
Management
XTAL
O-QPSK
Modem
IEEE802.15.4
MAC
Accelerator
Bootloader
Flash
48-byte
OTP eFuse
© Jennic Ltd 2008 – www.jennic.com JN5139-PB v1.22 Page 2 of 2
Design Flexibility
Battery Optimisation
To maximise battery life, devices support a series of power
management and sleep modes. Used effectively, these will allow a
batteries life expectancy for a typical remote sensing application, to
be of the order of a few years.
Wireless Protocol Stacks in ROM
Two standard ROM configurations are available that integrate IEEE802.15.4b and ZigBee protocol stacks. The JN5139-000
integrates IEEE802.15.4b for development of proprietary systems, and the JN5139-Z01 integrates the ZigBee protocol stack,
this supporting co-ordinator, router and end device configurations. Custom ROM masks will support the integration of user
code into ROM, attractive to higher volume applications.
Application Diagram
The JN5139 device requires a minimum of external
components to support wireless applications; a crystal,
some decoupling components and printed antenna are
all that is required for the lowest cost bill of materials and
smallest size (an external bootloader flash may be used
for optional program code storage).
Evaluation Kits
To assist users with the development of wireless sensor networks, Jennic provide a series of Evaluation Kits. These contain
everything that is needed to carry out complete development and test, and include controller and sensor boards, interface
dongle to connect with a PC and a Software Developer Kit (SDK).
The SDK provides a comprehensive suite of tools to facilitate the development of application code. The kit includes a C
compiler, graphical and text debuggers, assembler, linker and flash programmer. A set of libraries provides a simple
Application Programming Interface (API) to drive the peripherals of the controller and sensor boards.
Power Saving Mode Typical
Current
Deep sleep 0.2µA
Sleep: wakeup on I/O or timer event 1.3µA
Sleep: wakeup on I/O or timer event and 96kB RAM retained 3.3µA
Corporate Headquarters
Furnival Street
Sheffield
S1 4QT
United Kingdom
Tel +44 (0)114 2812655
Fax +44 (0)114 2812951
E-mail info@jennic.com
Taiwan Sales Office
19F-1, 182, Sec.2
Tun Hwa S. Road
Taipei 106
Taiwan
Tel +886 2 2735 7357
Fax +886 2 2739 5687
E-mail info@tw.jennic.com
Japan Sales Office
Osakaya building 4F
1-11-8 Higashigotanda
Shinagawa-ku
Tokyo 141-0022, Japan
Tel +81 3 5449 7501
Fax +81 3 5449 0741
E-mail info@jp.jennic.com
United States Sales Office
1060 First Avenue, Suite 400
King of Prussia
PA 16406
USA
Tel +1 610 768 8071
Fax +1 484 971 5015
E-mail info@us.jennic.com
43
CTS1
VB_PROT
1
RTS1
TXD1
RXD1
VSS2
RESETN
VSSS
XTALOUT
CLK_OP
XTALIN
VB_SYN
VB_APP
ADC2
RFP
VB_RF
RFM
VREF
ADC1
ADC4
VB_A
DAC1
29
15
ADC3
VSS3
IBIAS
MISO
SPISEL0
SPISEL1
VSS1
VB_MEM
SPISEL2
SPISEL3
VCOTUNE
MOSI
VB_VCO
VDD1
COMP1M
COMP1P
DAC2
COMP2P
COMP2M
SPICLK
TIM0CK_GT
VDD2
TIM1CK_GT
TIM1CAP
TIM1OUT
SIF_CLK
SIF_D
SPISEL4
CTS0
RTS0
TXD0
RXD0
TIM0OUT
TIM0CAP
Jennic
JN513x
Vcc
UART 0
Timers
8
7
6
5
1
2
3
4
Vcc
Vcc
UART 1
RESET
Two Wire
Serial Port
SPI Selects
Analogue IO
SS
SDO
WP
Vss
Vcc
HOLD
CLK
SDI
Printed Antenna
CLK O/P
C2
C9
C8
R4
R9 C3 C1
C4
C5
C6
C15
C11
C10
C7
Y1
C12
C13
IC2 Serial Flash Memory
Optional Bootloader
Flash