SST39SF512-70-4C-WH - Silicon Storage Technology

S71149-05-000 11/03

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit (x8) Multi-Purpose Flash

SST39SF512

FEATURES:

• Organized as 64K x8

• Single 4.5-5.5V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 10 mA (typical)

– Standby Current: 10 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 70 ns

• Latched Address and Data

• Fast Erase and Byte-Program

– Sector-Erase Time: 7 ms (typical)

– Chip-Erase Time: 15 ms (typical)

– Byte-Program Time: 20 µs (typical)

– Chip Rewrite Time: 2 seconds (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm )

– 32-pin PDIP

PRODUCT DESCRIPTION

The S ST39SF51 2 are CMOS Multi -Pur pose F lash ( MPF)

manufactured with SST’s proprietary, high performance

CMOS SuperFlash technology. The split-gate cell design

and thic k-ox ide tunneling injector attain better reliability and

manufacturability compared with alternate approaches.

The SST39SF512 devices write (Program or Erase) with a

4.5-5.5V pow er supply. The SST39SF512 device conforms

to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the

SST39SF512 devices provide a maximum Byte-Program

time of 30 µsec. These devices use Toggle Bit or Data#

Polling to indicate the completion of Prog ram operation. To

protect against inadvertent write, they have on-chip hard-

ware and Software Data Protection schemes. Designed,

manufactured, and tested for a wide spectrum of applica-

tions, these devices are offered with a guaranteed typical

endurance of 100,000 cycles. Data retention is rated at

gr eat er t han 10 0 y e ar s.

The SST39SF512 devices are suited for applications that

require convenient and economical updating of program,

conf igu rat ion , or da ta mem ory. For all s ys te m a ppl i ca tio ns,

they signifi c ant ly i mp r ove performa nc e an d reli ab il it y, while

lowering power consumption. They inherently use less

energy during erase and program than alternative flash

technologies. The total energy consumed is a function of

the appl ied volta ge, curre nt, and time of ap plicati on. S inc e

for any given voltage range, the SuperFlash technology

uses less current to progr am and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternative flash technologies . These

devices also improve flexibility while lowering the cost for

program, data, and configuration storage applications .

The S upe r Flas h te ch no logy pr ovid es fi xed Erase an d P r o-

gram times, in depen dent o f the num ber of Erase/ Pro gram

cycles that have occurred. Therefore the system software

or hardware does not ha v e to be modified or de-rated as is

nec essary with al tern ativ e flas h techno logies , whose E rase

and Pr ogram tim es inc rease with accumul ated Erase/Pr o-

gr am cycles .

To meet high density, surface mount requirements, the

SST39SF512 are offered in 32-lead PLCC, 32-lead TS OP,

and a 600 mil, 32-pin PDIP packages. See Figures 1, 2,

and 3 f or pin assignments.

SST39SF512 5.0V 512Kb (x8) MPF memor y

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

Device Operatio n

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asse rtin g WE# low while keepi ng CE#

low. The address b us is latched on the f alling edge of WE#

or CE#, whichever oc curs l ast. T he data bus is latc hed o n

the rising edge of WE# or CE#, whichev er occurs first.

Read

The Read operation of the SST39SF512 is controlled by

CE# and OE#, both ha ve to be low for the system to obtain

data from the outputs. CE# is used for device selection.

When C E# is high , the chip is desele cted and only stand by

power is consu med . O E# is the out put co ntrol an d is us e d

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high. Refer to

the Read cycle timing diagram for further details (Figure 4) .

Byte-P rogram Opera ti on

The SST39SF512 are programmed on a byte-by-byte

basis. Before programming, the sector where the byte

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load byte address and byte data. During the Byte-

Prog ram o perat ion, th e address es are latched on the falli ng

edge of either CE# or WE#, whichever occurs last. The

data is latched on the rising edge of either CE# or WE#,

whichever occurs first. The third step is the internal Pro-

gram operation which is initiated after the rising edge of the

fourth WE# or CE#, whichever occurs first. The Program

operation, once initiated, will be completed, within 30 µs.

See F i gu re s 5 a nd 6 for WE # an d CE # co nt ro ll ed P rogram

operation timing diagrams and Figure 15 for flowcharts.

During the Program operation, the only valid reads are

Data# Polling and Toggle Bit . During the inter nal Program

operatio n, the host i s free to perfor m additio nal tasks. Any

commands written during the internal Program operation

will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector ba sis. The sector architecture

is based on uniform sector size of 4 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand load sequence for Software Data Protection with

Sector -Erase com mand (30 H) and s ector addr ess (S A) in

the last b us cycle. The sector address is latched on the fall-

ing edge of the sixth WE# pulse, whil e the command (30H)

is latched on the rising edge of the sixth WE# pulse. The

inter nal Erase ope ration begin s afte r the sixt h WE# pul se.

The end of Erase can be determined using either Data#

Polling or Toggle Bit methods. See Figure 9 for timing

waveforms. Any commands written during the Sector-

Erase operation will be ignored.

Chip-Erase Operation

The SST39SF512 provide Chip-Erase operation, which

allows the user to erase the entire memory arr ay to the “1s”

state. This is useful when the entire device must be quickly

erased.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The Erase ope ration begi ns wi th the ri sin g

edge of the sixth WE# or CE#, whiche ver occurs first. Dur-

ing the Erase operation, the only valid read is Toggle Bit or

Data# Polling. See Table 4 for the command sequence,

Figure 10 for timing diagram, and Figure 18 for the flow-

chart. Any commands written during the Chip-Erase opera-

tion will be ignor ed.

Write Opera ti on Status De te ct ion

The SST39SF512 provide two software means to detect

the completion of a Write (Program or Erase) cycle, in

order to optimize the system Write cycle time. The software

detection includes two status bits: Data# Polling (DQ7) and

Toggle Bit (DQ6). The End-of-Write detection mode is

enabled after the rising edge of WE#, which initiates the

Prog ram or Er ase cycle .

The actual completion of the nonv olatile write is asynchro-

nous with the system; the refore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to

conflict with eith er DQ7 or DQ6. In order to prevent spur i-

ous rejection , if an erroneous result occurs, the software

routine s hould include a loop to read t he accessed loc a-

tion an additional two (2) times. If both reads are valid,

then the device has completed the Write cycle, otherwise

the rejection is v alid.

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

Data# Polling (DQ7)

When the SST39SF512 are in the internal Program opera-

tion, any attempt to read DQ7 will produce the complement

of the true data. Once the Progr am operation is completed,

DQ7 will produce true data. Note that even thought DQ7

may have valid da ta immediately following the completion

of an in ternal Write o peration, the remaining data outputs

may still be invalid: valid data on the entire data bus will

appear in subsequent successive Read cycles after an

interval of 1 µs. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase o peration is complete d, DQ7 will prod uce a ‘ 1’. The

Data# P olling is v alid after the rising edge of f ourth WE# (or

CE#) pulse for Program Operation. For sector or Chip-

Erase, the Data# Polling is valid after the rising edge of

sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling

timing diagram and Figure 16 f or a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alter nating 0s

and 1s, i.e., tog gling betwe en 0 and 1. The To ggle Bit will

begin with “1”. When the internal Program or Erase opera-

tion is c om pl ete d, the to ggl in g will stop. The device i s then

ready f or the ne xt operation. The Toggle Bit is valid after the

rising edge of f ourth WE# (or CE#) pulse f or Program oper-

ation. For Sector or Chip-Erase, the Toggle Bit is valid after

the rising edge of sixth WE# (or CE#) pulse. See Figure 8

for Toggle Bit timing diagram and Figure 16 f or a flowchart.

Data Protection

The SST39SF512 pro vide both hardw are and softw are f ea-

tures to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pu lse of less t han 5

ns will not ini tiate a Wri te cycle .

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will in hi bit t he Write operation . T hi s prevents inadvert-

ent w rites durin g pow er-u p or po wer- dow n.

Software Data Protection (SDP)

The S ST39S F512 p rovide t he JEDE C ap proved Software

Data Protection scheme for all data alteration operations,

i.e., Program and Erase. Any Program operation requires

the inclusion of a series of three byte sequence. The three-

byte load seq uence is used to initiate the Program ope ra-

tion, providing optimal protection from inadvertent Write

operations, e.g., during the system power-up or power-

down. Any Erase operation requires the inclusion of six-

byte load sequence. The SST39SF512 device is shipped

with the Software Data Protection permanently enabled.

See Table 4 f or the specific software command codes. Dur-

ing SDP command sequence, inv alid commands will abort

the device to read mode, within TRC.

Product Identifica tion

The Product Identification mode identifies the de vice as the

SST39SF512 and SST39SF010 and manufacturer as

SST. This mode may be accessed by software operations.

Users may use the software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details,

Table 4 f or software operation, Figure 11 f or the software ID

entry and read timing diagram and Figure 17 for the ID

entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software

Produc t Ident ificati on mode must be exited. Exit is acco m-

plished by issuing the Software ID Exit command

sequence , which returns the device to the Read operation.

Please note that the software reset command is ignored

during an internal Program or Erase operation. See Table 4

for software command codes, Figure 12 for timing wave-

f orm and Fi gure 17 f or a flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39SF512 0001H B4H

T1.3 1149

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

Y-Decoder

I/O Buffers and Data Latches

1149 B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

VDD

WE#

32-lead PLCC

Top View

1149 F02b.6

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN P DIP

A11

A13

A14

WE#

VDD

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

1149 F01.3

Standard Pinout

Top View

Die Up

32-pin

PDIP

Top View

1149 F02a.4

A15

A12

DQ0

DQ1

DQ2

VSS

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Sector-Eras e AMS-A12 address lines will select the sector.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide 4.5-5.5V supply

VSS Ground

NC No Connection Unconnected pins.

T2.4 1149

1. AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector address,

XXH for Chip-Erase

Standby VIH XXHigh Z X

Write Inhibit X VIL XHigh Z/ D

OUT X

XXV

IH High Z/ DOUT X

Product Identification

Softw are Mode VIL VIL VIH See Table 4

T3.4 1149

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Softw are ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Softw are ID Exit6XXH F0H

Softw are ID Exit65555H AAH 2AAAH 55H 5555H F0H

T4.3 1149

1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence.

2. BA = Program By te address

3. SAX for Sector-Erase; uses AMS-A12 address lines

AMS = Most significant address

AMS = A15 for SST39SF512

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST39SF512 Device ID = B4H, is read with A0 = 1

6. Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on An y Pin to G round Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240° C

Output Short Circuit Cur rent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shor ted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 90 ns

See Figures 13 and 14

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min

VDD=VDD Max

Read230 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 50 mA CE#=WE#=VIL, O E#=VIH

ISB1 Standby VDD Current

(TTL input) 3µACE#=V

IH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input) 50 µA CE#=VDD -0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

T5.6 1149

1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C

(room temperature), and VDD = 5V for SF devices. Not 100% tested.

2. Values are for 70 ns conditions. See the

Multi-Purpose Flash P ower Rating

application note fo r further information.

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.1 1149

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 1149

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD m A JED EC Standard 78

T8.2 1149

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V

Symbol Parameter

SST39SF512-70

UnitsMin Max

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 25 ns

TOHZ1OE# High to Hi gh-Z Output 25 ns

TOH1Output Hold from Address Change 0 ns

T9.5 1149

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Byte-Program Time 30 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# Hi gh Setup Ti me 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 10 ms

TSCE Chip-Erase 20 ms

T10.1 1149

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

1149 F03.2

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH TCHZ HIGH-Z

D ATA VALIDD ATA VALID

TOHZ

Note: AMS = Most significant address

AMS = A15 for SST39SF512

1149 F04.2

ADDRESS AMS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 7: DATA# POLLING T IMING DIAGRAM

1149 F05.2

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS = A15 for SST39SF512

1149 F06.2

ADDRESS AMS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512

DQ7DD# D# D

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

1149 F07.2

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggle bit output is always high first.

AMS = Most significant address

AMS = A15 for SST39SF512

1149 F08.3

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

FIGURE 11: SOFTWARE ID ENTRY AND READ

1149 F17.2

ADDRESS AMS-0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

1149 F09.3

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

Three-byte sequence for

Software ID Entry

TWP

TWPH TAA

Device ID

55AA 90

Device ID = B4H for SST39SF512

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 12: SOFTWARE ID EXIT AND RESET

1149 F10.0

ADDRESS A14-0

DQ7-0

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 13: AC I NPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 14: A TEST LOAD EXAMPLE

1149 F11.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inpu ts ar e dri ven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0” . Measur emen t reference point s for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <1 0 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1149 F12.1

TO TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 15: BYTE-PROGRAM ALGORITHM

1149 F13.1

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Byte

Address/Byte

Data

Wait for end of

Program (TBP'

Data# Polling

bit or Toggle bit

operation)

Program

Completed

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 16: WAIT OPTIONS

1149 F14.0

W ait TBP,

TSCE, or TSE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Write

Completed

Write

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte-Program

Initiated

Byte-Program/

Sector Erase

Initiated

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS

1149 F15.1

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

FIGURE 18: ERASE COMMAND SEQUENCE

1149 F16.1

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

W ait TSCE

Chip-Erase

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

W ait TSE

Sector-Erase

to FFH

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

PRODUCT ORDERING INFORMATION

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Valid combinations for SST39SF512

SST39SF512-70-4C-NH SST39SF512-70-4C-WH SST39SF512-70-4C-PH

SST39SF512-70-4C-NHE SST39SF512-70-4C-WHE

SST39SF512-70-4I-NH SST39SF512-70-4I-WH

SST39SF512-70-4I-NHE SST39SF512-70-4I-WHE

Environmental Attribute

E = non-Pb

Package Modifier

H = 32 pins or leads

Package Type

N = PLCC

P = PDIP

W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Spee d

70 = 70 ns

Device Density

512 = 512 Kbit

Voltage

S = 4.5-5.5V

Product Seri es

39 = Multi-Purpose Flash

SST 39 SF 512 - 70 - 4C - WH E

XX XXXXXX -XXX -XX-XXX X

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

.040

.030

.021

.013 .530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30˚

32-tsop-WH-7

Note: 1.Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2.All linear dimensions are in millimeters (max/min).

3.Coplanarity: 0.1 mm

4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

http://store.iiic.cc/

Data Sheet

512 Kbit Multi-Purpose Flash

SST39SF512

32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

SST PACKAGE CODE: PH

TABLE 11: REVISION HISTORY

Number Description Date

03 •2002 Data Book Apr 2002

04 •Removed 1 Mbit part

•Added footnote for MPF power usage and Typical conditions to Table 5 on page 8

•Clarified the Test Conditions for Pow er Supply Current and Read parameters in Table 5

•Part number changes - see page 20 for additional information

•90 ns parts are no longer offered

•Clarifed IDD Write to be Program and Erase in Table 5 on page 8

Mar 2003

05 •2004 Data Book

•Added non-Pb MPNs and removed footnote (See page 20) No v 200 3

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7˚

4 PLCS.

.600 BSC

.100 BSC .150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065 1.655

1.645

.012

.008

0˚

15˚

.625

.600

.550

.530

Silicon Stor age Technol ogy, In c. • 117 1 Sonor a C ourt • Sunnyvale , CA 940 86 • Telephone 408-73 5-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

http://store.iiic.cc/