STSJ3NM50 N-CHANNEL 550V @ Tjmax- 2.5 - 3A PowerSO-8 Zener-Protected MDmeshTM MOSFET TYPE STSJ3NM50 VDSS (@Tjmax) RDS(on) ID 550 V <3 3A TYPICAL RDS(on) = 2.5 HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTORING YIELDS DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar completition's products. APPLICATIONS The MDmeshTM family is very suitable for increase the power density of high voltage converters allowing system miniaturization and higher efficiencies. PowerSO-8 INTERNAL SCHEMATIC DIAGRAM DRAIN CONTACT ALSO ON THE BACKSIDE ABSOLUTE MAXIMUM RATINGS Symbol VGS ID IDM (2) PTOT PTOT Parameter Value Unit Gate- source Voltage 30 V Drain Current (continuous) at TC = 25C Drain Current (continuous) at TA = 25C (1) Drain Current (continuous) at TC = 100C 3 0.63 1.89 A A A Drain Current (pulsed) 12 A Total Dissipation at TC = 25C Total Dissipation at TA = 25C (1) 70 3 W W 0.02 W/C 15 V/ns - 65 to 150 C Derating Factor (1) dv/dt (3) Tstg Tj February 2004 Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature 1/8 STSJ3NM50 THERMAL DATA Rthj-c Rthj-amb Tj Tstg Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max (1) Max. Operating Junction Temperature Storage Temperature 1.78 C/W 42 C/W 150 C - 65 to 150 C ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Test Conditions ID = 1 mA, VGS = 0 Min. Typ. Unit V VDS = Max Rating Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating, TC = 125 C Gate-body Leakage Current (VDS = 0) Max. 500 VGS = 20V 1 A 10 A 5 A ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250A RDS(on) Static Drain-source On Resistance Min. Typ. Max. Unit 3 4 5 V 2.5 3 Typ. Max. Unit VGS = 10 V, ID = 1.5 A DYNAMIC Symbol gfs (4) 2/8 Parameter Test Conditions Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 3 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. 0.7 S Ciss Input Capacitance 140 pF Coss Output Capacitance 40 pF Crss Reverse Transfer Capacitance 40 pF RG Gate Input Resistance 4 f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain STSJ3NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. VDD = 250 V, ID = 1.5 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) VDD = 400 V, ID = 3 A, VGS = 10 V Typ. Max. Unit 7 ns 10 ns 5.5 2.5 2.4 nC nC nC SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-Voltage Rise Time Fall Time Cross-Over Time Test Conditions Min. Typ. Max. 8 9 15 VDD = 480 V, ID = 3 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 3) Unit ns ns ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 3 A ISDM (2) Source-drain Current (pulsed) 12 A VSD (4) Forward On Voltage ISD = 3 A, VGS = 0 1.5 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3, di/dt = 100A/s, VDD = 100 V, Tj = 25C (see test circuit, Figure 5) 210 790 7.5 ns nC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3, di/dt = 100A/s, VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 282 1.1 7.7 ns nC A ISD trr Qrr IRRM trr Qrr IRRM Note: 1. 2. 3. 4. Parameter Test Conditions Min. Typ. When mounted on 1inch FR4 Board, 2oz of Cu, t 10 sec. Pulse width limited by safe operating area ISD<3.3A, di/dt<400A/s, VDD<V(BR)DSS, T J<T JMAX Pulsed: Pulse duration = 400 s, duty cycle 1.5 % GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 3/8 STSJ3NM50 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STSJ3NM50 Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVdss vs Temperature 5/8 STSJ3NM50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STSJ3NM50 PowerSO-8TM MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.25 a2 MAX. 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 e4 2.79 0.110 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 7/8 STSJ3NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 8/8