©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
HUF76121D3, HUF76121D3S
20A, 30V, 0.023 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76121.
Features
• Logic Level Gate Drive
• 20A, 30V
• Ultra Low On-Resistance, r
DS(ON)
= 0.023
Ω
• Temperature Compensating PSPICE
®
Model
• Temperature Compensating SABER
©
Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-251AA JEDEC TO-252AA
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76121D3 TO-251AA 76121D
HUF76121D3S TO-252AA 76121D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76121D3ST.
D
G
S
DRAIN
(FLANGE) DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
Data Sheet December 2001
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
30 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
30 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
16 V
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
20
20
20
Figure 4
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
0.6
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 12) 30 - - V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 25V, V
GS
= 0V - - 1
µ
A
V
DS
= 25V, V
GS
= 0V, T
C
= 150
o
C - - 250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
16V - -
±
100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 11) 1 - 3 V
Drain to Source On Resistance r
DS(ON)
I
D
= 20A, V
GS
= 10V (Figure 9, 10) - 0.017 0.023
Ω
I
D
= 20A, V
GS
= 5V (Figure 9) - 0.021 0.030
Ω
I
D
= 20A, V
GS
= 4.5V (Figure 9) - 0.023 0.033
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case R
θ
JC
(Figure 3) - - 1.66
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
TO-251AA, TO-252AA - - 100
o
C/W
SWITCHING SPECIFICATIONS
(V
GS
= 4.5V)
Turn-On Time t
ON
V
DD
= 15V, I
D
≅
20A,
R
L
= 0.75
Ω
, V
GS
=
4.5V,
R
GS
= 11.0
Ω
(Figures 15, 21, 22)
- - 275 ns
Turn-On Delay Time t
d(ON)
-18-ns
Rise Time t
r
- 165 - ns
Turn-Off Delay Time t
d(OFF)
-18-ns
Fall Time t
f
-40-ns
Turn-Off Time t
OFF
- - 87 ns
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time t
ON
V
DD
= 15V, I
D
≅
20A,
R
L
= 0.75
Ω
, V
GS
= 10V,
R
GS
= 12.0
Ω
(Figures 16, 21, 22)
- - 85 ns
Turn-On Delay Time t
d(ON)
-6-ns
Rise Time t
r
-50-ns
Turn-Off Delay Time t
d(OFF)
-45-ns
Fall Time t
f
-45-ns
Turn-Off Time t
OFF
- - 135 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
g(TOT)
V
GS
= 0V to 10V V
DD
= 15V,
I
D
≅
20A,
R
L
= 0.75
Ω
I
g(REF)
= 1.0mA
(Figures 14, 19, 20)
-2430nC
Gate Charge at 5V Q
g(5)
V
GS
= 0V to 5V - 13 16 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to 1V - 1.0 1.2 nC
Gate to Source Gate Charge Q
gs
- 2.40 - nC
Gate to Drain “Miller” Charge Q
gd
- 7.40 - nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
- 850 - pF
Output Capacitance COSS - 465 - pF
Reverse Transfer Capacitance CRSS - 100 - pF
Electrical Specifications TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 20A - - 1.25 V
Reverse Recovery Time trr ISD = 20A, dISD/dt = 100A/µs--58ns
Reverse Recovered Charge QRR ISD = 20A, dISD/dt = 100A/µs--70nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 175
0
5
10
15
20
25
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 10V
VGS = 4.5V
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
Typical Performance Curves (Continued)
0.01
0.1
1
2
10-5 10-4 10-3 10-2 10-1 100101
ZθJC, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
t, RECTANGULAR PULSE DURATION (s)
10
100
1000
10-5 10-4 10-3 10-2 10-1 100101
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10
100
1 10 100
500
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
10ms
1ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
BVDSS MAX = 30V
1
10
100
0.001 0.01 0.1 1 10 100
300
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
175oC
0
15
30
45
60
75
01 3452
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-55oC
25oC
VDD = 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
15
30
45
60
75
012345
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 4V
VGS = 3V
VGS = 3.5V
VGS = 4.5V
VGS = 10V
VGS = 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
15
20
25
30
35
246810
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(ON), ON-STATE RESISTANCE (mΩ)
ID = 20A
ID = 1A
ID = 10A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.8
1.0
1.2
1.4
1.6
-80 -40 0 40 80 120 160
0.6
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 250µs, VGS = 10V, ID = 20A
0.8
1.0
1.2
-80 -40 0 40 80 120 160
0.6
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
1.1
1.2
-80 -40 0 40 80 0.12k 0.16k
1.0
TJ, JUNCTION TEMPERATURE (oC)
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKOWN VOLTAGE
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves (Continued)
0
300
600
900
1200
0 5 10 15 20 25 30
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
0
2
4
6
8
10
0 5 10 15 20 25
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 15V
Qg, GATE CHARGE (nC)
ID = 20A
ID = 10A
ID = 1A
WAVEFORMS IN
DESCENDING ORDER:
0
100
200
300
400
0 1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 20A, RL = 0.75Ωtr
tf
td(ON)
SWITCHING TIME (ns)
td(OFF)
0
50
100
150
200
0 1020304050
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 10V, VDD = 15V, ID = 20A, RL = 0.75Ω
tr
td(OFF)
tf
td(ON)
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10V
VDS
VGS
IgREF)
0
0
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
PSPICE Electrical Model
.SUBCKT HUF76121D 2 1 3 ; rev May 1998
CA 12 8 1.3e-9
CB 15 14 1.25e-9
CIN 6 8 7.5e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 33.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 2.4e-9
LSOURCE 3 7 3.14e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.6e-3
RGATE 9 20 4
RLDRAIN 2 5 10
RLGATE 1 9 24
RLSOURCE 3 7 31.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 12.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*155),4))}
.MODEL DBODYMOD D (IS = 3.5e-13 RS = 8.7e-3 TRS1 = 2.2e-3 TRS2 = 2e-6 CJO = 1.34e-9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0.95 IKF = 3.7)
.MODEL DBREAKMOD D (RS = 1.3e-1 TRS1 = 2e-3 TRS2 = -2e-5)
.MODEL DPLCAPMOD D (CJO = 7.7e-10 IS = 1e-30 N = 10 M = 0.63)
.MODEL MMEDMOD NMOS (VTO = 1.9 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4)
.MODEL MSTROMOD NMOS (VTO = 2.23 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.64 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 2e-2 TC2 = 2.4e-5)
.MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 8e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -1.9e-3 TC2 = -5.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.2e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF= 1.8)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.8 VOFF= -1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
SABER Electrical Model
REV May 1998
template huf76121d n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 3.5e-13, xti = 4.3, cjo = 1.34e-9, tt = 2.8e-8, n = 0.95, m = 0.4)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 7.7e-10, is = 1e-30, n = 10, m = 0.63)
m..model mmedmod = (type=_n, vto = 1.9, kp = 3.5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.23, kp = 55, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.64, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -3)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1, voff = 1.8)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 1.8, voff = -1)
c.ca n12 n8 = 1.3e-9
c.cb n15 n14 = 1.25e-9
c.cin n6 n8 = 7.5e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.4e-9
l.lsource n3 n7 = 3.14e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 0
res.rdbody n71 n5 = 8.7e-3, tc1 = 2.2e-3, tc2 = 2e-6
res.rdbreak n72 n5 = 1.3e-1, tc1 = 2e-3, tc2 = -2e-5
res.rdrain n50 n16 = 2.6e-3, tc1 = 2e-2, tc2 = 2.4e-5
res.rgate n9 n20 = 4
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 24
res.rlsource n3 n7 = 31.4
res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 12.5e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.2e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -5.5e-6
spe.ebreak n11 n7 n17 n18 = 33.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/155))** 4))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76121D3, HUF76121D3S
©2001 Fairchild Semiconductor Corporation HUF76121D3, HUF76121D3S Rev. B
SPICE Thermal Model
REV May 1998
HUF76121D
CTHERM1 th 6 1.1e-3
CTHERM2 6 5 2.5e-3
CTHERM3 5 4 3.2e-3
CTHERM4 4 3 8.5e-3
CTHERM5 3 2 4.0e-2
CTHERM6 2 tl 2.2
RTHERM1 th 6 1.8e-3
RTHERM2 6 5 1.5e-2
RTHERM3 5 4 2.4e-1
RTHERM4 4 3 4.5e-1
RTHERM5 3 2 3.4e-1
RTHERM6 2 tl 7.0e-2
SABER Thermal Model
SABER thermal model HUF76121D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.1e-3
ctherm.ctherm2 6 5 = 2.5e-3
ctherm.ctherm3 5 4 = 3.2e-3
ctherm.ctherm4 4 3 = 8.5e-3
ctherm.ctherm5 3 2 = 4.0e-2
ctherm.ctherm6 2 tl = 2.2
rtherm.rtherm1 th 6 = 1.8e-3
rtherm.rtherm2 6 5 = 1.5e-2
rtherm.rtherm3 5 4 = 2.4e-1
rtherm.rtherm4 4 3 = 4.5e-1
rtherm.rtherm5 3 2 = 3.4e-1
rtherm.rtherm6 2 tl = 7.0e-2
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF76121D3, HUF76121D3S
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