AK5385AVSP - AKM Semiconductor, Inc.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 1 -

GENERAL DESCRIPTION

The AK5385A is a 24bit, 192kHz sampling 2ch A/D converter for high-end audio system. The modulator

in the AK5385A uses the Enhanced Dual Bit architecture and the AK5385A realizes high accuracy and

low cost. The AK5385A performs 114dB dynamic range, so the device is suitable for AV-amp, AV

recorder and musical instruments. The AK5385A is available in 28pin VSOP and SOP package, utilizing

less board space.

FEATURES

p Sampling Rate: 8kHz ~ 216kHz

p Full Differential Inputs

p S/(N+D): 103dB

p DR: 114dB

p S/N: 114dB

p High Performance Linear Phase Digital Anti-Alias filter

• Passband: 0~21.768kHz (@fs=48kHz)

• Ripple: 0.005dB

• Stopband: 100dB

p Digital HPF

p Power Supply: 5V

±

5%(Analog), 3.0 ~ 5.25V(Digital)

p Power Dissipation: 183mW (@fs=48kHz)

p Package: 28pin SOP / 28pin VSOP

p AK5383/AK5393/AK5394A Semi-Pin compatible

TEST

Decimation

Filter

Delta-Sigma

Modulator Decimation

Filter HPF

HPF

Audio I/F

Controller

DVDDAVDD DVSSAVSS

VREFR

VREFL

LIN+

LIN- Delta-Sigma

Modulator

RIN+

RIN-

DIF

PDN

LRCK

BICK

MCLK

SDTO

HPFE

M/S DFS1 DFS0 CKS1 CKS0VCOM

BVSS

OVF

Block diagram

24Bit 192kHz ∆Σ

ADC

AK5385A

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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n Ordering Guide

AK5385AVS –10 ~ +70°C 28pin SOP (1.27mm pitch)

AK5385AVF –40 ~ +85°C 28pin VSOP (0.65mm pitch)

AKD5385A Evaluation Board for AK5385A

n Pin Layout

VCOM

LIN+

DVDD

DVSS

VREFL

AVSS

LIN-

CKS0

PDN

DIF

M/S

LRCK

BICK

OVF

Top View

8

7

6

5

4

3

2

1

21

22

23

24

25

26

27

28

TEST

RIN+

AVSS

AVDD

RIN-

AVSS

VREFR

9

10

11

12

13

14

18

19

20 HPFE

15

16

17

SDTO

CKS1

MCLK

DFS1

BVSS

DFS0

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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n Compatibility with AK5383/AK5394A

AK5385A AK5383 AK5394A

Pin 1 VREFL VREFL VREFL+

Pin 2 AVSS GNDL VREFL−

Pin 3 VCOM VCOML VCOML

Pin 6 CKS0 ZCAL ZCAL

Pin 9 OVF CAL CAL

Pin 11 DIF SMODE2 SMODE2

Pin 12 M/S SMODE1 SMODE1

Pin 16 CKS1 FSYNC FSYNC

Pin 18 DFS0 DFS DFS0

Pin 20 DFS1 TEST DFS1

Pin 26 TEST VCOMR VCOMR

Pin 27 AVSS GNDR VREFR−

Pin 28 VREFR VREFR VREFR+

fs 8kHz ∼ 216kHz 1kHz ∼ 108kHz 1kHz ∼ 216kHz

MCLK at 48kHz 256/384/512fs 256fs 256fs

MCLK at 96kHz 256fs 128fs 128fs

MCLK at 192kHz 128fs Not Available 64fs

DR, S/N 114dB 110dB 123dB

Input Voltage ±2.9Vpp ±2.45Vpp ±2.4Vpp

Offset Calibration Not Available Available Available

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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n Compare PCB layout example between AK5385A and AK5383

3.0 ~ 5.25V

Digital

VREFL

GNDL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VCOML

AINL+

AINL-

ZCAL

VD

DGND

CAL

RSTN

SMODE2

SMODE1

LRCK

SCLK

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VREFR

GNDR

VCOMR

AINR+

AINR-

VA

AGND

BGND

TEST

HPFE

DFS

MCLK

FSYNC

SDATA

0.1µ

10µ

0.22µ

0.1µ

10µ

0.1µ

10µ

5V

Analog

Analog Ground 0.1µ10µ

0.22µ

3.0 ~ 5.25V

Digital

VREFL

AVSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VCOM

LIN+

LIN-

CKS0

DVDD

DVSS

OVF

PDN

M/S

DIF

LRCK

BICK

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VREFR

AVSS

TEST

RIN+

RIN-

AVDD

AVSS

BVSS

DFS1

HPFE

DFS0

MCLK

CKS1

SDTO

10µ

0.22µ

0.1µ

10µ

0.1µ

10µ

5V

Analog

10µ

AK5385AAK5383

0.1µ

Analog Ground

0.1µ

Pin # AK5383 AK5385A

VREFL VREFL

1 Lch Voltage Reference Output Pin, 3.75V

Normally, connected to GNDL with a 10µF

electrolytic capacitor and a 0.1µF ceramic capacitor.

Lch Voltage Reference Input Pin, AVDD

Normally, connected to AVSS with a 10µF

electrolytic capacitor and a 0.1µF ceramic capacitor.

ZCAL CKS0

6 Zero Calibration Control Pin

This pin controls the calibration reference signal. Master Clock Select 0 Pin

(Internal Pull-down Pin, typ. 100kΩ)

CAL OVF

9 Calibration Active Signal Pin Analog Input Overflow Detect Pin

SMODE2 DIF

11 Serial Interface Mode Select Pin Audio Interface Format Pin

SMODE1 M/S

12 Serial Interface Mode Select Pin Master / Slave Mode Pin

FSYNC CKS1

16 Frame Synchronization Signal Pin

Master Clock Select 1 Pin

(Internal Pull-down Pin, typ.100kΩ)

DFS DFS0

18 Double Speed Sampling Mode Pin Sampling Speed Select 0 Pin

TEST DFS1

20 Test Pin (Internal Pull-down Pin) Sampling Speed Select 1 Pin

VCOMR TEST

26 Rch Common Voltage Pin, 2.75V Test Pin (Internal Pull-down Pin, typ. 100kΩ)

VREFR VREFR

28 Rch Voltage Reference Output Pin, 3.75V

Normally, connected to GNDL with a 10µF

electrolytic capacitor and a 0.1µF ceramic capacitor.

Rch Voltage Reference Input Pin, AVDD

Normally, connected to AVSS with a 10µF

electrolytic capacitor and a 0.1µF ceramic capacitor.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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n Compare PCB layout example between AK5385A and AK5394A

3.0 ~ 5.25V

Digital

VREFL+

VREFL-

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VCOML

AINL+

AINL-

ZCAL

VD

DGND

CAL

RSTN

SMODE2

SMODE1

LRCK

SCLK

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VREFR+

VREFR-

VCOMR

AINR+

AINR-

VA

AGND

BGND

DFS1

HPFE

DFS0

MCLK

FSYNC

SDATA

0.1µ

10µ

0.22µ

0.1µ

10µ

0.1µ

10µ

5V

Analog

Analog Ground 0.1µ10µ

0.22µ

AK5394A

10µ10µ

3.0 ~ 5.25V

Digital

VREFL

AVSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VCOM

LIN+

LIN-

CKS0

DVDD

DVSS

OVF

PDN

M/S

DIF

LRCK

BICK

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VREFR

AVSS

TEST

RIN+

RIN-

AVDD

AVSS

BVSS

DFS1

HPFE

DFS0

MCLK

CKS1

SDTO

0.1µ

10µ

0.22µ

0.1µ

10µ

0.1µ

10µ

5V

Analog

0.1µ10µ

AK5385A

(short) (short)

Analog Ground

Pin # AK5394A AK5385A

VREFL+ VREFL

1 Lch Positive Voltage Reference Output Pin, 3.75V

Normally connected to AGND with a large

electrolytic capacitor and connected to VREFL−

with a 0.22µF ceramic capacitor.

Lch Voltage Reference Input Pin, AVDD

Normally, connected to AVSS with a 10µF

electrolytic capacitor and a 0.1µF ceramic capacitor.

VREFL− AVSS

2 Lch Negative Voltage Reference Output Pin, 1.25V

Normally connected to AGND with a large

electrolytic capacitor and connected to VREFL+

with a 0.22µF ceramic capacitor.

Analog Ground Pin

ZCAL CKS0

6 Zero Calibration Control Pin

This pin controls the calibration reference signal. Master Clock Select 0 Pin

(Internal Pull-down Pin, typ. 100kΩ)

CAL OVF

9 Calibration Active Signal Pin Analog Input Overflow Detect Pin

SMODE2 DIF

11 Serial Interface Mode Select Pin Audio Interface Format Pin

SMODE1 M/S

12 Serial Interface Mode Select Pin Master / Slave Mode Pin

FSYNC CKS1

16 Frame Synchronization Signal Pin

Master Clock Select 1 Pin

(Internal Pull-down Pin, typ. 100kΩ)

VREFR− AVSS

27 Rch Negative Voltage Reference Output Pin, 1.25V

Normally connected to AGND with a large

electrolytic capacitor and connected to VREFR+

with a 0.22µF ceramic capacitor.

Analog Ground Pin

VCOMR TEST

26 Rch Common Voltage Pin, 2.75V Test Pin (Internal Pull-down Pin, typ. 100kΩ)

VREFR+ VREFR

28 Rch Positive Reference Output Voltage, 3.75V

Normally connected to AGND with a large

electrolytic capacitor and connected to VREFR−

with a 0.22µF ceramic capacitor.

Rch Voltage Reference Input Pin, AVDD

Normally, connected to AVSS with a 10µF

electrolytic capacitor and a 0.1µF ceramic capacitor.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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PIN / FUNCTION

No. Pin Name I/O Function

1 VREFL I Lch Voltage Reference Input Pin, AVDD

Normally, connected to AVSS with a 10µF electrolytic capacitor and a 0.1µF

ceramic capacitor.

2 AVSS - Analog Ground Pin

3 VCOM O Common Voltage Output Pin, AVDD/2

4 LIN+ I Lch Analog Positive Input Pin

5 LIN− I Lch Analog Negative Input Pin

6 CKS0 I Master Clock Select 0 Pin (Internal Pull-down Pin, typ. 100kΩ)

7 DVDD - Digital Power Supply Pin, 3.0 ∼ 5.25V

8 DVSS - Digital Ground Pin

9 OVF O Analog Input Overflow Detect Pin

This pin goes to “H” if analog input overflows.

10 PDN I Power Down Mode Pin

“H”: Power up, “L”: Power down

11 DIF I Audio Interface Format Pin

“H” : 24bit I2S Compatible, “L” : 24bit MSB justified

12 M/S I Master / Slave Mode Pin

“H” : Master Mode, “L” : Slave Mode

13 LRCK I/O Output Channel Clock Pin

“L” Output in Master Mode at Power-down mode.

14 BICK I/O Audio Serial Data Clock Pin

“L” Output in Master Mode at Power-down mode.

15 SDTO O Audio Serial Data Output Pin

“L” Output at Power-down mode.

16 CKS1 I Master Clock Select 1 Pin (Internal Pull-down Pin, typ. 100kΩ)

17 MCLK I Master Clock Input Pin

18 DFS0 I Sampling Speed Select 0 Pin

19 HPFE I High Pass Filter Enable Pin

“H” : Enable, “L” : Disable

20 DFS1 I Sampling Speed Select 1 Pin

21 BVSS - Substrate Ground Pin

22 AVSS - Analog Ground Pin

23 AVDD - Analog Power Supply Pin, 4.75 ∼ 5.25V

24 RIN− I Rch Analog Negative Input Pin

25 RIN+ I Rch Analog Positive Input Pin

26 TEST I Test Pin (Internal Pull-down Pin, typ. 100kΩ)

27 AVSS - Analog Ground Pin

28 VREFR I Rch Voltage Reference Input Pin, AVDD

Normally, connected to AVSS with a 10µF electrolytic capacitor and a 0.1µF

ceramic capacitor.

Note: All digital input pins except pull-down pins should not be left floating.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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n Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification Pin Name Setting

LIN+, LIN− These pins should be connected to AVSS.

RIN+, RIN− These pins should be connected to AVSS.

Analog VREFL, VREFR These pins should be connected to AVDD.

OVF This pin should be open.

Digital TEST This pin should be connected to DVSS.

ABSOLUTE MAXIMUM RATINGS

(AVSS, BVSS, DVSS=0V; Note 1)

Parameter Symbol min max Units

Power Supplies:

Analog

Digital

|BVSS – DVSS| (Note 2)

AVDD

DVDD

∆GND

−0.3

-

6.0

0.3

V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Analog Input Voltage (LIN+/–, RIN+/–, VREFL/R pins) VINA −0.3 AVDD+0.3 V

Digital Input Voltage (All digital input pins) VIND −0.3 DVDD+0.3 V

Ambient Temperature (Power applied)

28SOP Package

28VSOP Package Ta

Ta −10

−40 70

85 °C

°C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. AVSS BVSS, and DVSS must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AVSS, BVSS, DVSS=0V; Note 1)

Parameter Symbol min typ max Units

Power Supplies

(Note 3) Analog

Digital AVDD

DVDD 4.75

3.0 5.0

3.3 5.25

AVDD V

V

Voltage Reference (VREFL/R pins) VREF 3.0 - AVDD V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD and DVDD is not critical.

WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=5.0V, DVDD=3.3V; AVSS=BVSS=DVSS=0V; VREFL=VREFR=AVDD; fs=48kHz, 96kHz,

192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz,

40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified)

Parameter min typ max Units

Analog Input Characteristics:

Resolution 24 Bits

Input Voltage (Note 4) ±2.7 ±2.9 ±3.1 Vpp

fs=48kHz

BW=20kHz

−1dBFS (Note 5)

−1dBFS

−20dBFS

−60dBFS

-

92

-

103

100

91

51

dB

fs=96kHz

BW=40kHz

−1dBFS

−20dBFS

−60dBFS

90

-

98

86

46

dB

S/(N+D)

fs=192kHz

BW=40kHz

−1dBFS

−20dBFS

−60dBFS

-

98

86

46

dB

Dynamic Range (−60dBFS with A-weighted) 107 114 dB

S/N (A-weighted) 107 114 dB

Input Resistance 9 13 kΩ

Interchannel Isolation 100 120 dB

Interchannel Gain Mismatch 0.1 0.5 dB

Power Supply Rejection (Note 6) 50 - dB

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H”)

AVDD

DVDD (fs=48kHz)

DVDD (fs=96kHz)

DVDD (fs=192kHz)

Power down mode (PDN pin = “L”) (Note 7)

AVDD+DVDD

30

10

17

20

10

45

15

25

30

100

mA

µA

Note 4. This value is (LIN+)−(LIN−) and (RIN+)−(RIN−). Input voltage is proportional to VREF voltage.

Vin = 0.58 x VREF (Vpp).

Note 5. 100µF capacitors are connected between the VREFL/R pins and AVSS.

Note 6. PSR is applied to AVDD and DVDD with 1kHz, 20mVpp. The VREFL and VREFR pins held a constant voltage.

Note 7. All digital input pins are held DVDD or DVSS.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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FILTER CHARACTERISTICS (fs=48kHz)

(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; DFS1 = “L”, DFS0 = “L”)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 8)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB

0

-

22.038

22.2

24.0

21.5

-

kHz

Stopband SB 26.5 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 9) GD 43.2 1/fs

Group Delay Distortion ∆GD 0 µs

ADC Digital Filter (HPF):

Frequency Response (Note 8)

−3dB

−0.1dB FR

1.0

6.5

Hz

FILTER CHARACTERISTICS (fs=96kHz)

(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; DFS1 = “L”, DFS0 = “H”)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 8)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB

0

-

44.081

44.5

48.0

43.0

-

kHz

Stopband SB 53.0 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 9) GD 43.1 1/fs

Group Delay Distortion ∆GD 0 µs

ADC Digital Filter (HPF):

Frequency Response (Note 8)

−3dB

−0.1dB FR

2.0

13.0

Hz

Note 8. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.

Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the

setting of 24bit data both channels to the ADC output register for ADC.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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FILTER CHARACTERISTICS (fs=192kHz)

(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; DFS1 = “H”, DFS0 = “L”)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 8)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB

0

-

88.183

89.0

96.0

86.0

-

kHz

Stopband SB 106.0 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 9) GD 38.2 1/fs

Group Delay Distortion ∆GD 0 µs

ADC Digital Filter (HPF):

Frequency Response (Note 8)

−3dB

−0.1dB FR

4.0

26.0

Hz

Note 8. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.

Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the

setting of 24bit data both channels to the ADC output register for ADC.

DC CHARACTERISTICS

(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V)

Parameter Symbol min typ Max Units

High-Level Input Voltage

Low-Level Input Voltage VIH

VIL 70%DVDD

- -

30%DVDD V

V

High-Level Output Voltage (Iout=−400µA)

Low-Level Output Voltage (Iout=400µA) VOH

VOL DVDD−0.4

- -

0.4 V

V

Input Leakage Current (Note 10) Iin - - ±10 µA

Note 10. CKS1, CKS0 and TEST pins are internally connected to a pull-down resistor. (typ. 100kΩ)

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

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SWITCHING CHARACTERISTICS

(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; CL=20pF)

Parameter Symbol min typ max Units

Master Clock Timing

Frequency

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

2.048

14.5

27.648

MHz

ns

LRCK Frequency

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

fsn

fsd

fsq

8

54

108

54

108

216

kHz

Duty Cycle

Slave mode

Master mode

45

50 55

%

Audio Interface Timing

Slave mode

BICK Period

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑” (Note 11)

BICK “↑” to LRCK Edge (Note 11)

LRCK to SDTO (MSB) (Except I2S mode)

BICK “↓” to SDTO

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

1/128fsn

1/64fsd

1/64fsq

33

20

ns

Master mode

BICK Frequency

BICK Duty

BICK “↓” to LRCK

BICK “↓” to SDTO

fBCK

dBCK

tMBLR

tBSD

−20

64fs

50

20

Hz

%

ns

Reset Timing

PDN Pulse Width (Note 12)

PDN “↑” to SDTO valid (Note 13)

tPD

tPDV

150

516

ns

1/fs

Note 11. BICK rising edge must not occur at the same time as LRCK edge.

Note 12. The AK5385A can be reset by bringing the PDN pin = “L”.

Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”. This value is in master mode

This value is longer 1/fs in slave mode than master mode.

ASAHI KASEI [AK5385A]

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n Timing Diagram

1/fCLK

MCLK

tCLKH tCLKL

VIH

VIL

1/fs

LRCK VIH

VIL

tBCK

BICK

tBCKH tBCKL

VIH

VIL

Clock Timing

LRCK VIH

VIL

tBLR

BICK VIH

VIL

tLRS

SDTO 50%DVDD

tLRB

tBSD

Audio Interface Timing (Slave mode)

ASAHI KASEI [AK5385A]

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LRCK

BICK 50%DVDD

SDTO 50%DVDD

tBSD

tMBLR dBCK

50%DVDD

Audio Interface Timing (Master mode)

tPD

PDN VIL

PDN VIH

VIL

tPDV

SDTO 50%DVDD

Power Down & Reset Timing

ASAHI KASEI [AK5385A]

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OPERATION OVERVIEW

n System Clock

MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must

be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling

frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in Table 2 and LRCK

frequency is selected by DFS1-0 pins as shown in Table 3.

As the AK5385A includes the phase detect circuit for LRCK, the AK5385A is reset automatically when the

synchronization is out of phase by changing the clock frequencies.

All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided, the

AK5385A may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not

present, place the AK5385A in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be

provided unless PDN pin = “L”.

MCLK

fs 128fs 256fs 384fs 512fs

32kHz N/A 8.192MHz 12.288MHz 16.384MHz

44.1kHz N/A 11.2896MHz 16.9344MHz 22.5792MHz

48kHz N/A 12.288MHz 18.432MHz 24.576MHz

96kHz N/A 24.576MHz N/A N/A

192kHz 24.576MHz N/A N/A N/A

Table 1. System Clock Example

CKS1 pin CKS0 pin MCLK Frequency

L L 256fs

L H 128fs

H L 512fs

H H 384fs

Table 2. MCLK Frequency

DFS1 pin DFS0 pin LRCK Frequency

L L 8kHz ≤ fs ≤ 54kHz

L H 54kHz < fs ≤ 108kHz

H L 108kHz < fs ≤ 216kHz

H H N/A

Table 3. Sampling Speed

When changing MCLK frequency in master/slave mode, the AK5385A should reset by PDN pin = “L”. (ex.

12.288MHz(@fs=48kHz) to 24.576MHz(@fs=96kHz) at CKS1 pin = CKS0 pin = “L”.

If the CKS1-0 and DFS1-0 pins are changed with same MCLK frequency in master/slave mode (ex. MCLK is fixed to

24.576MHz and fs is changed from 48kHz (CKS1 pin = “L”, CKS0 pin = “L”) to 96kHz (CKS1 pin = “L”, CKS0 pin =

“H”)), no reset by PDN pin = “L” is required.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 15 -

n Audio Interface Format

Two kinds of data formats can be chosen with the DIF pin (Table 4). In both modes, the serial data is in MSB first, 2’s

compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and

slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK frequency

fixed to 1fs.

Mode DIF pin SDTO LRCK BICK Figure

0 L 24bit, MSB justified H/L ≥ 48fs Figure 1

1 H 24bit, I2S Compatible L/H ≥ 48fs Figure 2

Table 4. Audio Interface Format

LRCK

BICK(64fs)

SDTO(o)

0

23 22

1 2

4 0

20 21 24 31 0 1 2

23 22 0

10

23

2220 21 31

23:MSB, 0:LSB

Lch Data Rch Data

24

3 2 1

22 23 23

1234

Figure 1. Mode 0 Timing

LRCK

BICK(64fs)

SDTO(o)

0

23 22

1 2

4 0

2521 24 0 1 2

23 22 0

1022 2521 24

3 2 1

22 23 23

1234

3

23:MSB, 0:LSB

Lch Data Rch Data

Figure 2. Mode 1 Timing

n Master Mode and Slave Mode

The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The

AK5385A outputs BICK and LRCK in master mode. In slave mode, provide MCLK, BICK and LRCK.

M/S pin Mode BICK, LRCK

L Slave Mode BICK = Input

LRCK = Input

H Master Mode BICK = Output

LRCK = Output

Table 5. Master mode/Slave mode

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 16 -

n Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz

(@fs=48kHz) and scales with sampling rate (fs).

HPF is controlled by HPFE pin. If HPF setting (ON/OFF) is changed at operating, click noise occurs by changing DC

offset. It is recommended that HPF setting is changed at PDN pin = “L”.

n Overflow Detection

The AK5385A has overflow detect function for analog input. OVF pin goes to “H” if Lch or Rch overflows (more than

−0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD=43.2/fs=0.9ms@fs=48kHz).

OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after PDN pin = “↑”, and then overflow detection is enabled.

n Power Down and Reset

The AK5385A is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same

time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog

initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 516

cycles of LRCK clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of

both channels are forced to “0”. The ADC outputs settle in the data corresponding to the input signals after the end of

initialization (Settling approximately takes the group delay time).

The AK5385A should be reset once by bringing PDN pin “L” after power -up. The internal timing starts clocking by the

rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.

Normal Operation

Internal

State

PDN

Power-down Initialize Normal Operation

(1)

Idle Noise

GD GD

“0”data

A/D In

(Analog)

A/D Out

(Digital)

Clock In

MCLK,LRCK,SCLK

(2)

(3)

(4)

“0”data Idle Noise

Notes:

(1) 517/fs in slave mode and 516/fs in master mode.

(2) Digital output corresponding to analog input has the group delay (GD).

(3) A/D output is “0” data at the power-down state.

(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5385A should be in the power-down state.

Figure 3. Power-down/up sequence example

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 17 -

SYSTEM DESIGN

Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,

the optimum layout, power supply arrangements and measurement results.

0.1µ

10µ

0.1µ

10µ

VREFL1

2

3

4

5

6

7

8

9

10

11

AVSS

VCOM

LIN+

LIN-

CKS0

DVDD

DVSS

OVF

PDN

DIF

AK5385A

DSP and uP

28

27

26

VREFR

AVSS

TEST

Digital Supply

3.0 ~ 5.25V

12 M/S

13 LRCK

14 BICK

Reset

25

24

RIN+

RIN-

23

22

AVDD

AVSS

21

20

BVSS

DFS1

19

18

HPFE

DFS0

17

16

MCLK

CKS1

15SDTO

Analog Supply

4.75 ~ 5.25V

0.1µ

10µ

0.22µ

0.1µ

10µ

Note:

- AVSS, BVSS and DVSS of the AK5385A should be distributed separately from the ground of external digital

devices (MPU, DSP etc.).

- All input pins except pull-down (CKS0, CKS1 and TEST pin) pin should not be left floating.

Figure 4. Typical Connection Diagram

Analog Ground Digital Ground

System

Controller

1

2

3

4

5

6

7

8

9

10

11

12

28

27

26

25

24

23

22

21

20

19

18

17

14

16

15

VREFL

AVSS

VCOM

LIN+

LIN-

CKS0

DVDD

DVSS

OVF

DIF

M/S

VREFR

AVSS

TEST

RIN+

RIN-

AVDD

AVSS

BVSS

DFS1

HPFE

DFS0

MCLK

AK5385A

LRCK

BICK

CKS1

SDTO

PDN

13

Figure 5. Ground Layout

Note:

- AVSS BVSS, and DVSS must be connected to the same analog ground plane.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 18 -

1. Grounding and Power Supply Decoupling

The AK5385A requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD

are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the AK5385A must be

connected to analog ground plane. System analog ground and digital ground should be connected together near to where

the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5385A as

possible, with the small value ceramic capacitor being the nearest.

2. Voltage Reference Inputs

The reference voltage for A/D converter is supplied from VREFL/R pins at AVSS reference. AVSS pin is connected to

analog ground and an electrolytic capacitor over 10µF parallel with a 0.1 µF ceramic capacitor between the VREFL/R pins

and the AVSS pin eliminate the effects of high frequency noise. Especially, a ceramic capacitor should be as near to the

pins as possible. And all digital signals, especially clocks, should be kept away from the VREFL/R pins in order to avoid

unwanted coupling into the AK5385A. No load current may be taken from the VREFL/R pins.

VCOM is a signal ground of this chip. An electrolytic capacitor 0.22µF attached to VCOM pin eliminates the effects of

high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept

away from the VCOM pin in order to avoid unwanted coupling into the AK5385A.

3. Analog Inputs

Analog signal is differentially input into the modulator via the LIN+ (RIN+) and the LIN− (RIN−) pins. The input voltage

is the difference between the LIN+ (RIN+) and LIN− (RIN−) pins. The full scale of each pin is nominally ±2.9Vpp(typ).

The AK5385A can accept input voltages from AVSS to AVDD. The ADC output data format is 2’s compliment. The

internal HPF removes the DC offset.

The AK5385A samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The digital filter rejects

noise above the stop band except for multiples of 128fs. The AK5385A includes an anti-aliasing filter (RC filter) to

attenuate a noise around 128fs.

The AK5385A accepts +5V supply voltage. Any voltage which exceeds the upper limit of AVDD+0.3V and lower limit of

AVSS−0.3V and any current beyond 10mA for the analog input pins (LIN+/−, RIN+/−) should be avoided. Excessive

currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these

limits. Use caution specially in case of using ±15V in other analog circuits.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 19 -

4. External Analog Circuit Examples

Figure 6 shows an input buffer circuit example 1. This is a full-differential input buffer circuit with an inverted-amp (gain:

−10dB). The capacitor of 10nF between LIN+/− (RIN+/−) decreases the clock feed through noise of modulator, and

composes a 1st order LPF (fc=360kHz) with 22Ω resistor before the capacitor. This circuit also has a 1st order LPF

(fc=370kHz) composed of op-amp. The evaluation board should be referred about the detail.

4

5

LIN+

LIN-

AK5385A

Analog In 4.7k

4.7k

VP+

VP-

NJM5532

47µ3k

470p

910

22

47µ3k

470p

910

22

Bias

10n

9.56Vpp

2.9Vpp

Bias

10µ

0.1µBias

10k

VA

VA = 5V

VP+ = 15V

VP- = -15V

Figure 6.Input Buffer example

Figure 7 shows an input buffer circuit example 2. (1st order HPF: fc=0.66Hz, Table 6; 1st order LPF: fc=590kHz,

gain=−14dB, Table 7). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC

input, open JP1 and JP2 for XLR input). The input level of this circuit is +/−14.7Vpp.

BNC

NJM5534

4

5

LIN+

LIN-

AK5385A

4.7k

JP1

JP2

91

1.5n

2.9Vpp

NJM5534

1k

22µ1k

22µ

10k

4.7k

VA

10µ

0.1µ

Vin-

Vin+

XLR 100

2.9Vpp

14.7Vpp

Bias

Figure 7.Input Buffer example

fin 1Hz 10Hz

Frequency Response −1.56dB −0.02dB

Table 6. Frequency Response of HPF

fin 20kHz 40kHz 6.144MHz

Frequency Response −0.005dB −0.02dB −15.6dB

Table 7. Frequency Response of LPF

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 20 -

5. Measurement Example

Figure 8 shows the S/(N+D) vs. VREF capacitor that is connected between VREFL/R pins and AVSS pin with the 0.1µF

capacitor in parallel. X-AXIS is the capacity for VREF; Y-AXIS is S/(N+D).

[Measurement Condition]

- AVDD = 5.0V, DVDD = 3.3V; AVSS = BVSS = DVSS = 0V

- fs = 48kHz

- Measurement Bandwidth = 10Hz ∼ 20kHz

- Ta = 25°C

- Using Audio Precision System Two Cascade

S/(N+D) vs. VREF Cap

100.0

101.0

102.0

103.0

104.0

105.0

106.0

050 100 150 200 250

VREF Cap [uF]

S/(N+D) [dB]

Lch Rch

Figure 8. S/(N+D) vs. VREF Cap

6. Synchronization of Multiple Devices

In system where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous

sampling, the MCLK and LRCK must be the same for all of the AK5385As in the system. The all AK5385As should be

reset at the same timing with preventing the reset signal for AK5385A from overlapping on the edge of MCLK, so that all

AK5385As begin sampling on the same clock edge.

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 21 -

PACKAGE (AK5385AVF)

0.1±0.1

0-10°

Detail A

Seating Plane

NOTE: Dimension "*" does not include mold flash.

| 0.10

0.15-0.05

0.22±0.1

0.65

*9.8±0.2

1.25±0.2

A

1

14

15

28

28pin VSOP (Unit: mm)

*5.6±0.2

7.6±0.2

0.5±0.2

+0.1

0.675

n Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 22 -

PACKAGE (AK5385AVS)

0-10°

0.10

0.15-0.05

1.095TYP

18.7±0.3

28pin SOP (Unit: mm)

7.5 ± 0.2

0.75

± 0.2

+0.1

10.4

± 0.3

2.2 ± 0.1

1.27

0.12 M

+0.1

0.1-0.05

0.4±0.1

n Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 23 -

MARKING (AK5385AVF)

AKM

AK5385AVF

XXXBYYYYC

XXXBYYYYC Date code identifier

XXXB : Lot number (X : Digit number, B : Alpha character)

YYYYC : Assembly date (Y : Digit number, C : Alpha character)

ASAHI KASEI [AK5385A]

MS0265-E-01 2003/11

- 24 -

MARKING (AK5385AVS)

AKM

AK5385AVS

XXXBYYYYC

XXXBYYYYC Date code identifier

XXXB : Lot number (X : Digit number, B : Alpha character)

YYYYC : Assembly date (Y : Digit number, C : Alpha character)

IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any

use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized

distributor concerning their current status.

• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the

application or use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license

or other official approval under the law and regulations of the country of export pertaining to customs

and tariffs, currency exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to any

such use, except with the express written consent of the Representative Director of AKM. As used

here:

a. A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its

failure to function or perform may reasonably be expected to result in loss of life or in significant

injury or damage to person or property.

b. A critical component is one whose failure to function or perform may reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or

system containing it, and which must therefore meet very high standards of performance and

reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or

otherwise places the product with a third party to notify that party in advance of the above content and

conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and

hold AKM harmless from any and all claims arising from the use of said product in the absence of such

notification.