LM5107
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
LM5107 100V / 1.4A Peak Half Bridge Gate Driver
Check for Samples: LM5107
1FEATURES DESCRIPTION
The LM5107 is a low cost high voltage gate driver,
• Drives Both a High Side and Low Side N- designed to drive both the high side and the low side
Channel MOSFET N-Channel MOSFETs in a synchronous buck or a
• High Peak Output Current (1.4A Sink / 1.3A half bridge configuration. The floating high-side driver
Source) is capable of working with rail voltages up to 100V.
The outputs are independently controlled with TTL
• Independent TTL compatible inputs compatible input thresholds. An integrated on chip
• Integrated Bootstrap Diode high voltage diode is provided to charge the high side
• Bootstrap Supply Voltage to 118V DC gate drive bootstrap capacitor. A robust level shifter
• Fast Propagation Times (27 ns Typical) technology operates at high speed while consuming
low power and providing clean level transitions from
• Drives 1000 pF Load with 15ns Rise and Fall the control input logic to the high side gate driver.
Times Under-voltage lockout is provided on both the low
• Excellent Propagation Delay Matching (2 ns side and the high side power rails. The device is
Typical) available in the SOIC and the thermally enhanced
WSON packages.
• Supply Rail Under-Voltage Lockout
• Low Power Consumption Package
• Pin Compatible with ISL6700 • SOIC
• WSON (4 mm x 4 mm)
TYPICAL APPLICATIONS
• Current Fed Push-Pull Converters
• Half and Full Bridge Power Converters
• Solid State Motor Drives
• Two Switch Forward Power Converters
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
HI
LI
VSS
HO
HS
LO
HB
VDD 1
2
3
4
8
7
6
5
HI
LI
VSS
HO
HS
LO
HB
VDD 1
2
3
4
8
7
6
5
DRIVER
DRIVER
LEVEL
SHIFT
UVLO
UVLO
HI
VDD
LI
VSS
HB
HO
HS
LO
HV
LM5107
SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
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Simplified Block Diagram
Connection Diagrams
Figure 1. 8-Lead SOIC Figure 2. 8-Lead WSON
See D Package See NGT0008A Package
PIN DESCRIPTIONS(1)
Pin # Name Description Application Information
SOIC WSON
Locally decouple to VSS using low ESR/ESL capacitor located as
1 1 VDD Positive gate drive supply close to IC as possible.
The LM5107 HI input is compatible with TTL input thresholds.
2 2 HI High side control input Unused HI input should be tied to ground and not left open
The LM5107 LI input is compatible with TTL input thresholds. Unused
3 3 LI Low side control input LI input should be tied to ground and not left open.
4 4 VSS Ground reference All signals are referenced to this ground.
5 5 LO Low side gate driver output Connect to the gate of the low side N-MOS device.
Connect to the negative terminal of the bootstrap capacitor and to the
6 6 HS High side source connection source of the high side N-MOS device.
7 7 HO High side gate driver output Connect to the gate of the low side N-MOS device.
Connect the positive terminal of the bootstrap capacitor to HB and
High side gate driver positive
8 8 HB the negative terminal of the bootstrap capacitor to HS. The bootstrap
supply rail capacitor should be placed as close to IC as possible.
(1) For WSON package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB
board and the ground plane should extend out from underneath the package to improve heat dissipation.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VDD to VSS -0.3V to 18V
HB to HS −0.3V to 18V
LI or HI to VSS −0.3V to VDD +0.3V
LO to VSS −0.3V to VDD +0.3V
HO to VSS VHS −0.3V to VHB +0.3V
HS to VSS(3) −5V to 100V
HB to VSS 118V
Junction Temperature -40°C to +150°C
Storage Temperature Range −55°C to +150°C
ESD Rating HBM(4) 2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics .
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
(4) The human body model is a 100 pF capacitor discharged through a 1.5kΩresistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at
500V.
Recommended Operating Conditions
VDD 8V to 14V
HS(1) −1V to 100V
HB VHS +8V to VHS +14V
HS Slew Rate < 50 V/ns
Junction Temperature −40°C to +125°C
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
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Electrical Characteristics
Specifications in standard typeface are for TJ= +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol Parameter Conditions Min(1) Typ Max(1) Units
SUPPLY CURRENTS
IDD VDD Quiescent Current LI = HI = 0V 0.3 0.6 mA
IDDO VDD Operating Current f = 500 kHz 2.1 3.4 mA
IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA
IHBO Total HB Operating Current f = 500 kHz 1.6 3.0 mA
IHBS HB to VSS Current, Quiescent VHS = VHB = 100V 0.1 10 µA
IHBSO HB to VSS Current, Operating f = 500 kHz 0.5 mA
INPUT PINS LI and HI
VIL Low Level Input Voltage Threshold 0.8 1.8 V
VIH High Level Input Voltage Threshold 1.8 2.2 V
RIInput Pulldown Resistance 100 180 500 kΩ
UNDER VOLTAGE PROTECTION
VDDR VDD Rising Threshold VDDR = VDD - VSS 6.0 6.9 7.4 V
VDDH VDD Threshold Hysteresis 0.5 V
VHBR HB Rising Threshold VHBR = VHB - VHS 5.7 6.6 7.1 V
VHBH HB Threshold Hysteresis 0.4 V
BOOT STRAP DIODE
VDL IVDD-HB = 100 µA
Low-Current Forward Voltage 0.58 0.9 V
VDL = VDD - VHB
VDH IVDD-HB = 100 mA
High-Current Forward Voltage 0.82 1.1 V
VDH = VDD - VHB
RDDynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω
LO GATE DRIVER
VOLL ILO = 100 mA
Low-Level Output Voltage 0.28 0.45 V
VOHL = VLO – VSS
VOHL ILO =−100 mA,
High-Level Output Voltage 0.45 0.75 V
VOHL = VDD– VLO
IOHL Peak Pullup Current VLO = 0V 1.3 A
IOLL Peak Pulldown Current VLO = 12V 1.4 A
HO GATE DRIVER
VOLH IHO = 100 mA
Low-Level Output Voltage 0.28 0.45 V
VOLH = VHO– VHS
VOHH IHO =−100 mA
High-Level Output Voltage 0.45 0.75 V
VOHH = VHB– VHO
IOHH Peak Pullup Current VHO = 0V 1.3 A
IOLH Peak Pulldown Current VHO = 12V 1.4 A
THERMAL RESISTANCE
θJA(2) SOIC 160
Junction to Ambient °C/W
WSON(3) 40
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
(3) 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
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Switching Characteristics
Specifications in standard typeface are for TJ= +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol Parameter Conditions Min(1) Typ Max(1) Units
LM5100A
tLPHL Lower Turn-Off Propagation Delay 27 56 ns
(LI Falling to LO Falling)
tHPHL Upper Turn-Off Propagation Delay 27 56 ns
(HI Falling to HO Falling)
tLPLH Lower Turn-On Propagation Delay 29 56 ns
(LI Rising to LO Rising)
tHPLH Upper Turn-On Propagation Delay 29 56 ns
(HI Rising to HO Rising)
tMON Delay Matching: Lower Turn-On and Upper 215 ns
Turn-Off
tMOFF Delay Matching: Lower Turn-Off and Upper 215 ns
Turn-On
tRC, tFC Either Output Rise/Fall Time CL= 1000 pF 15 - ns
tPW Minimum Input Pulse Width that Changes 50 ns
the Output
tBS Bootstrap Diode Turn-Off Time IF= 100 mA, IR= 100 mA 105 ns
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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8 10 12 14 16 18
0
100
200
300
400
500
600
CURRENT (PA)
VDD, VHB (V)
LI = HI = 0V
VDD = VHB
VSS= VHS = 0V
IHB
IDD
PROPAGATION DELAY (ns)
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
20
24
28
32
36
40
44 CL = 0 pF
VDD = VHB = 12V
VSS = VHS = 0V
tHPHL tLPHL
tLPLH
tHPLH
turn off
turn on
1.2
1.4
1.6
1.8
2.0
2.2
2.4
CL = 0 pF
f = 500 kHz
VDD = VHB = 12V
VSS = VHS = 0V
IDDO
IHBO
IDDO, IHBO (mA)
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
IDD, IHB (mA)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
IDDO
IHBO
LI = HI = 0V
VDD = VHB = 12V
VSS = VHS = 0V
110 100 1000
FREQUENCY (kHz)
0.01
0.1
1
10
100
IDDO (mA)
VDD = VHB = 12V
VSS = VHS = 0V
CL = 4400 pF
CL = 2200 pF
CL = 1000 pF
CL = 0 pF
CL = 470 pF
110 100 1000
FREQUENCY (kHz)
0.1
1
10
100
IDDO (mA)
CL = 4400 pF
CL = 2200 pF
CL = 1000 pF
CL = 0 pF
VDD = VHB = 12V
VSS = VHS = 0V
CL = 470 pF
LM5107
SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics
VDD Operating Current vs Frequency HB Operating Current vs Frequency
Figure 3. Figure 4.
Operating Current vs Temperature Quiescent Current vs Temperature
Figure 5. Figure 6.
Quiescent Current vs Voltage Propagation Delay vs Temperature
Figure 7. Figure 8.
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TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
THRESHOLD (V)
VDDR
VHBR
VDDR = VDD - VSS
VHBR = VHB - VHS
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
HYSTERESIS (V)
VDDH
VHBH
02 4 68 10 12
VLO, VHO (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
OUTPUT CURRENTS (A)
VDD = VHB = 12V
VSS = VHS = 0V
Pull-up Current
Pull-down Current
VOH (V)
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
VDD = VHB =16V
VDD = VHB = 12V
VDD = VHB = 8V
Output Current : -100 mA
VSS = VHS = 0V
0.1
0.2
0.3
0.4
0.5
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
VOL (V)
VDD = VHB = 12V
VDD = VHB = 8V
Output Current : -100 mA
VSS = VHS = 0V
VDD = VHB =16V
LM5107
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
LO and HO High Level Output Voltage vs Temperature LO and HO Low Level Output Voltage vs Temperature
Figure 9. Figure 10.
HO and LO Peak Output Current vs Output Voltage Doide Forward Voltage
Figure 11. Figure 12.
Undervoltage Rising Thresholds vs Temperature Undervoltage Hysteresis vs Temperature
Figure 13. Figure 14.
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INPUT THRESHOLD VOLTAGE (V)
1.70
1.75
1.80
1.85
1.90
1.95
2.00
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110 125
20 35 50 65
Rising
Falling
VDD = 12V
VSS = 0V
INPUT THRESHOLD VOLTAGE (V)
VDD (V)
89 10 14 15 16
11 12 13
Rising
Falling
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
1.91
1.92
LM5107
SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
Input Thresholds vs Temperature Input Thresholds vs Supply Voltage
Figure 15. Figure 16.
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LI
HI
tHPLH
tLPLH tHPHL
tLPHL
LO
HO
LI
HI
tMOFF
tMON
LO
HO
LM5107
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
Timing Diagram
Figure 17.
Layout Considerations
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
– The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate
parasitic transistors resulting in excessive current to flow from the HB supply possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less . Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. A low ESR bypass capacitor between HB to HS as well as VDD to VSS is essential for proper operation. The
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capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable operation.
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5107MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5107
MA
LM5107MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5107
MA
LM5107SD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L5107SD
LM5107SDX/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L5107SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5107MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5107SD/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5107SDX/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5107MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5107SD/NOPB WSON NGT 8 1000 210.0 185.0 35.0
LM5107SDX/NOPB WSON NGT 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
NGT0008A
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SDC08A (Rev A)
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