1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3 VOLT DUAL CMOS SyncFIFO™
DUAL 256 X 9, DUAL 512 X 9,
DUAL 1,024 X 9, DUAL 2,048 X 9,
DUAL 4,096 X 9 , DUAL 8,192 X 9
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
OCTOBER 2008
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4093/4
FEATURES:
••
••
•The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs
••
••
•The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs
••
••
•The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs
••
••
•The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs
••
••
•The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs
••
••
•The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs
••
••
•Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
••
••
•Ideal for prioritization, bidirectional, and width expansion
applications
••
••
•10 ns read/write cycle time
••
••
•5V input tolerant
••
••
•Separate control lines and data lines for each FIFO
••
••
•Separate Empty, Full, programmable Almost-Empty and
Almost-Full flags for each FIFO
••
••
•Enable puts output data lines in high-impedance state
••
••
•Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/
STQFP)
••
••
•Industrial temperature range (–40°°
°°
°C to +85 °°
°°
°C) is available
••
••
•Green parts available, see ordering information
DESCRIPTION:
The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are
dual synchronous (clocked) FIFOs. The device is functionally equivalent to
two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,
QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).
Data is written into each of the two arrays on every rising clock edge of the Write
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are
asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full
(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to Empty+7 for PAEA and
PAEB, and Full-7 for PAFA and PAFB.
The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture
lends itself to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
DA0 - DA8LDA
OFFSET REGISTERINPUT REGISTER
WRITE CONTROL
LOGIC
RESET LOGIC
OUTPUT REGISTER
OEA
RSA
QA0 - QA8RCLKA
RENA1
RENA2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFAPAEA
PAFA
FFA
4093 drw 01
WCLKB
WENB1
WENB2 DB0 - DB8LDB
OFFSET REGISTERINPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
OEB
RSB QB0 - QB8
RCLKB
RENB1
RENB2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFB
PAFB
FFB
PAEB
WRITE POINTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
2
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
PIN CONFIGURATION
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
QA
1
QA
2
QA
3
QA
4
QA
5
QA
6
QA
7
QA
8
V
CC
WENA
2
/LDA
WCLKA
WENA
1
RSA
DA
8
DA
7
DA
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QB0
FFB
EFB
OEB
RENB
2
RCLKB
RENB
1
GND
Vcc
PAEB
PAFB
DB
0
DB
1
DB
2
DB
3
DB
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
QA
0
FFA
EFA
OEA
RENA
2
RCLKA
RENA
1
GND
QB
8
QB
7
QB
6
QB
5
QB
4
QB
3
QB
2
QB
1
DA
5
DA
4
DA
3
DA
2
DA
1
DA
0
PAFA
PAEA
WENB
2
/LDB
WCLKB
WENB
1
RSB
DB
8
DB
7
DB
6
DB
5
4093 drw 02
3
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
PIN DESCRIPTIONS
The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs,
referred to as FIFO A and FIFO B, are identical in every respect. The following description defines the input and output signals for FIFO A. The corresponding
signal names for FIFO B are provided in parentheses.
Symbol Name I/O Description
DA0-DA8 A Data Inputs I 9-bit data inputs to RAM array A.
DB0-DB8 B Data Inputs I 9-bit data inputs to RAM array B.
RSA, RSB Reset I When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-
up, a reset of both FIFOs A and B is required before an initial WRITE.
WCLKA Write Clock I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)
WCLKB are asserted.
WENA1 Write Enable 1 I If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be
WENB1 used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is
LOW.
WENA2/LDA Write Enable 2/ I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at
WENB2/LDB Load reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates
as a control to load and read the programmable flag offsets for its respective array. If the FIFO is configured to have
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable
flags, LDA (LDB) is held LOW to write or read the programmable flag offsets.
QA0-QA8 A Data Outputs O 9-bit data outputs from RAM array A.
QB0-QB8 B Data Outputs O 9-bit data outputs from RAM array B.
RCLKA Read Clock I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and
RCLKB RENA2 (RENB2) are asserted.
RENA1 Read Enable 1 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH
RENB1 transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2 Read Enable 2 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-
RENB2 HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA Output Enable I When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-
DA8 (DB0-DB8) will be in a high-impedance state.
EFA Empty Flag O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA
EFB (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA Programmable O When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate
PAEB Almost-Empty Flag offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).
PAFA Programmable O When PAFA (PAFB) is LOW, FIFO A (B) is Almost-Full based on the offset programmed into the appropriate offset
PAFB Almost-Full Flag register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
FFA Full Flag O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is
FFB HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
VCC Power +3.3V power supply pin.
GND Ground 0V ground pin.
4
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
Symbol Rating Commercial Unit
VTERM Terminal Voltage with –0.5 to +5 V
Respect to GND
TSTG Storage Temperature –55 to +125
°
C
IOUT DC Output Current –50 to +50 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
CONDITIONS
VCC Supply Voltage(Com’l & Ind’l) 3 .0 3 .3 3 .6 V
GND Supply Voltage(Com’l & Ind’l) 0 0 — V
VIH Input High Voltage
(Com’l & Ind’l) 2 . 0 — 5 . 0 V
VIL Input Low Voltage
(Com’l & Ind’l) — — 0. 8 V
TAOperating Temperature 0 — 70
°
C
Commercial
TAOperating Temperature -40 ⎯85
°
C
Industrial
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
Commercial and Industrial (1)
tCLK = 10, 15, 20 ns
Symbol Parameter Min. Typ. Max. Unit
ILI(2) Input Leakage Current (Any Input) – 1 — – 1 µA
ILO(3) Output Leakage Current –10 — 10 µA
VOH Output Logic “1” Voltage, IOH = –2 mA 2 . 4 — — V
VOL Output Logic “0” Voltage, IOL = 8 mA — — 0 . 4 V
ICC1(4,5,6) Active Power Supply Current (both FIFOs) — — 40 mA
ICC2(3,7) Standby Current — — 10 mA
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OEA, OEB ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 2[0.17 + 0.48*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial :VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Symbol Parameter Conditions Max. Unit
CIN(2) Input Capacitance VIN = 0V 10 pF
COUT(1,2) Output Capacitance VOUT = 0V 10 pF
NOTE:
1. With output deselected (OEA, OEB ≥ VIH).
2. Characterized values, not currently tested.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Typ. Max Unit
CAPACITANCE (TA = +25
°
C, f = 1.0MHz)
5
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
Commercial Com’l & Ind’l Commercial
IDT72V801L10 IDT72V801L15 IDT72V801L20
IDT72V811L10 IDT72V811L15 IDT72V811L20
IDT72V821L10 IDT72V821L15 IDT72V821L20
IDT72V831L10 IDT72V831L15 IDT72V831L20
IDT72V841L10 IDT72V841L15 IDT72V841L20
IDT72V851L10 IDT72V851L15 IDT72V851L20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fSClock Cycle Frequency — 100 — 66.7 — 50 MHz
tAData Access Time 2 6.5 2 1 0 2 12 ns
tCLK Clock Cycle Time 10 — 15(1) —20—ns
tCLKH Clock High Time 4 .5 — 6 — 8 — ns
tCLKL Clock Low Time 4 . 5 — 6 — 8 — n s
tDS Data Set-up Time 3 — 4 — 5 — ns
tDH Data Hold Time 0.5 — 1 — 1 — ns
tENS Enable Set-up Time 3 — 4 — 5 — ns
tENH Enable Hold Time 0.5 — 1 — 1 — ns
tRS Reset Pulse Width(2) 10 — 15 — 20 — ns
tRSS Reset Set-up Time 8 — 10 — 12 — ns
tRSR Reset Recovery Time 8 — 1 0 — 1 2 — ns
tRSF Reset to Flag Time and Output Time — 1 0 — 15 — 2 0 ns
tOLZ Output Enable to Output in Low-Z(3) 0—0— 0—ns
tOE Output Enable to Output Valid 3 6 3 8 3 1 0 ns
tOHZ Output Enable to Output in High-Z(3) 3638 310ns
tWFF Write Clock to Full Flag — 6. 5 — 1 0 — 1 2 ns
tREF Read Clock to Empty Flag — 6. 5 — 10 — 12 n s
tPAF Write Clock to Programmable Almost-Full Flag — 6.5 — 10 — 12 ns
tPAE Read Clock to Programmable Almost-Empty Flag — 6.5 — 10 — 12 ns
tSKEW1 Skew Time Between Read Clock and Write Clock 5 — 6 — 8 — n s
for Empty Flag and Full Flag
tSKEW2 Skew Time Between Read Clock and Write Clock for 14 — 1 8 — 20 — ns
Programmable Almost-Empty Flag and Programmable
Almost-Full Flag
*Includes jig and scope capacitances.
Figure 1. Output Load
or equivalent circuit
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
30pF*
330Ω
3.3V
510Ω
D.U.T.
4093 drw 03
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
AC TEST CONDITIONS
6
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
LDA WENA1 WCLKA OPERATION ON FIFO A
LDB WENB1 WCLKB OPERATION ON FIFO B
0 0 Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
Figure 2. Writing to Offset Registers for FIFOs A and B
When either of the two Read Enable, RENA1, RENA2 (RENB1, RENB2)
associated with FIFO A (B) is HIGH, the output register holds the previous data
and no new data is allowed to be loaded into the register.
When all the data has been read from FIFO A (B), the Empty Flag, EFA
(EFB) will go LOW, inhibiting further read operations. Once a valid write
operation has been accomplished, EFA (EFB) will go HIGH after tREF and a
valid read can begin. The Read Enables, RENA1, RENA2 (RENB1, RENB2)
are ignored when FIFO A (B) is empty.
Output Enable (OEA, OEB) — When Output Enable, OEA (OEB) is
enabled (LOW), the parallel output buffers of FIFO A (B) receive data from their
respective output register. When Output Enable, OEA (OEB) is disabled
(HIGH), the QA (QB) output data bus is in a high-impedance state.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual-
purpose pin. FIFO A (B) is configured at Reset to have programmable flags
or to have two write enables, which allows depth expansion. If WENA2/LDA
(WENB2/LDB) is set HIGH at Reset, RSA = LOW (RSB = LOW), this pin operates
as a second Write Enable pin.
If FIFO A (B) is configured to have two write enables, when Write Enable
1, WENA1 (WENB1) is LOW and WENA2/LDA (WENB2/LDB) is HIGH, data can
be loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock, WCLKA (WCLKB). Data is stored in the array sequentially
and independently of any on-going read operation.
In this configuration, when WENA1 (WENB1) is HIGH and/or WENA2/LDA
(WENB2/LDB) is LOW, the input register of Array A holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag, FFA (FFB) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle, FFA (FFB)
will go HIGH after tWFF, allowing a valid write to begin. WENA1, (WENB1) and
WENA2/LDA (WENB2/LDB) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when the WENA2/
LDA (WENB2/LDB) is set LOW at Reset, RSA = LOW (RSB = LOW). Each FIFO
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The following description
explains the interaction of input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine data inputs
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
CONTROLS:
Reset (RSA, RSB) — Reset of FIFO A (B) is accomplished whenever RSA
(RSB) input is taken to a LOW state. During reset, the internal read and write
pointers associated with the FIFO are set to the first location. A reset is required
after power-up before a write operation can take place. The Full Flag, FFA
(FFB) and Programmable Almost-Full Flag, PAFA (PAFB) will be reset to HIGH
after tRSF. The Empty Flag, EFA (EFB) and Programmable Almost-Empty Flag,
PAEA (PAEB) will be reset to LOW after tRSF. During reset, the output register
is initialized to all zeros and the offset registers are initialized to their default
values.
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is initiated
on the LOW-to-HIGH transition of WCLKA (WCLKB). Data set-up and hold
times must be met with respect to the LOW-to-HIGH transition of WCLKA
(WCLKB). The Full Flag, FFA (FFB) and Programmable Almost-Full Flag,
PAFA (PAFB) are synchronized with respect to the LOW-to-HIGH transition of
the Write Clock, WCLKA (WCLKB).
The Write and Read clock can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags, WENA1 (WENB1) is the only enable control pin. In this
configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write
Clock, WCLKA (WCLKB). Data is stored in Array A (B) sequentially and
independently of any on-going read operation.
In this configuration, when WENA1 (WENB1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the
register.
If the FIFO is configured to have two write enables, which allows for depth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write
operations. Upon the completion of a valid read cycle, the FFA (FFB) will go
HIGH after tWFF, allowing a valid write to begin. WENA1 (WENB1) is ignored
when FIFO A (B) is full.
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B)
on the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag, EFA
(EFB) and Programmable Almost-Empty Flag, PAEA (PAEB) are synchronized
with respect to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clock can be asynchronous or coincident.
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
Enables, RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array
A (B) to the output register on the LOW-to-HIGH transition of the Read Clock,
RCLKA (RCLKB).
NOTE: 4093 tbl 08
1. For the purposes of this table, WENA2 and WENB2 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and RENA2
(RENB1 and RENB2) are enabled and read is performed on the LOW-to-HIGH transition
of RCLKA (RCLKB).
7
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
If FIFO A (B) is configured to have programmable flags, when the WENA1
(WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72V801 - 256 x 9 x 2 72V811 - 512 x 9 x 2
7
7
80
(MSB)
1
00
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72V831 - 2,048 x 9 x 2
7
7
8080
(MSB)
0000
2
(MSB)
000
3
8080
(MSB)
0000
2
(MSB)
000
3
80
8
0
80
(MSB)
1
0
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
72V821 - 1,024 x 9 x 2
80
(MSB)
00
1
80
(MSB)
00
1
4093 drw 05
72V841 - 4,096 x 9 x 2 80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
7
7
80
(MSB)
00000
4
72V851 - 8,192 x 9 x 2
(MSB)
00000
80
4
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing LDA (LDB) HIGH,
FIFO A (B) is returned to normal read/write operation. When LDA (LDB) is set
LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is
written.
The contents of the offset registers can be read on the QA (QB) outputs when
WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1,
RENA2 (RENB1, RENB2) are set LOW. Data can be read on the LOW-to-HIGH
transition of the Read Clock RCLKA (RCLKB).
A read and write should not be performed simultaneously to the offset
registers.
8
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
OUTPUTSOUTPUTS
OUTPUTSOUTPUTS
OUTPUTS::
::
:
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA (FFB) will go LOW after 256 writes to the IDT72V801's FIFO A (B), 512
writes to the IDT72V811's FIFO A (B), 1,024 writes to the IDT72V821's FIFO
A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the
IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of
the Write Clock WCLKA (WCLKB).
Empty Flag (EFA, EFB) — EFA (EFB) will go LOW, inhibiting further read
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
EFA (EFB) is synchronized with respect to the LOW-to-HIGH transition of
the Read Clock RCLKA (RCLKB).
Programmable Almost–Full Flag (PAFA, PAFB) —
PAFA (PAFB) will go
LOW when the amount of data in Array A (B) reaches the Almost-Full condition.
If no reads are performed after reset, PAFA (PAFB) will go LOW after (256-m)
writes to the IDT72V801's FIFO A (B), (512-m) writes to the IDT72V811's FIFO
A (B), (1,024-m) writes to the IDT72V821's FIFO A (B), (2,048-m) writes to
the IDT72V831's FIFO A (B), (4,096-m) writes to the IDT72V841's FIFO A
(B), or (8,1912-m) writes to the IDT72V851's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of
the Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
Registers.
If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words.
PAFA (PAFB) is synchronized with respect to the LOW-to-HIGH transition
of the Write Clock WCLKA (WCLKB).
Programmable Almost–Empty Flag (PAEA, PAEB) — PAEA (PAEB) will
go LOW when the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty Offset Registers. If no reads are performed
after reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B).
If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7
words.
PAEA (PAEB) is synchronized with respect to the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data
outputs for memory array A, QB0 - QB8 are the nine data outputs for memory
array B.
NUMBER OF WORDS IN ARRAY A FFA PAFA PAEA EFA
NUMBER OF WORDS IN ARRAY B FFB PAFB PAEB EFB
IDT72V801 IDT72V811 IDT72V821
000HHLL
1 to n(1) 1 to n(1) 1 to n(1) HHLH
(n+1) to (256-(m+1)) (n+1) to (512-(m+1)) (n+1) to (1,024-(m+1))
HHHH
(256-m)(2) to 255 (512-m)(2) to 511 (1,024-m)(2) to 1,023 H L H H
256 512 1,024 L L H H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
NUMBER OF WORDS IN ARRAY A FFA PAFA PAEA EFA
NUMBER OF WORDS IN ARRAY B FFB PAFB PAEB EFB
IDT72V831 IDT72V841 IDT72V851
000HHLL
1 to n(1) 1 to n(1) 1 to n(1) HHLH
(n+1) to (2,048-(m+1)) (n+1) to (4,096-(m+1)) (n+1) to (8,192-(m+1))
HHHH
(2,048-m)(2) to 2,047 (4,096-m)(2) to 4,095 (8,192-m)(2) to 8,191 H L H H
2,048 4,096 8,192 L L H H
T ABLE 1: ST A TUS FLAGS FOR A AND B FIFOS
9
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
Figure 4. Reset Timing
NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second Write Enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make
the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 5. Write Cycle Timing
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
t
DH
t
ENH
t
SKEW1(1)
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
WFF
t
WFF
WCLKA (WCLKB)
(DA
0
- DA
8
DB
0
- DB
8
)
WENA1
(WENB1)
WENA2 (WENB2)
(If Applicable)
FFA
(FFB)
RCLKA (RCLKB)
RENA1, RENA2
(RENB1, RENB2)
NO OPERATION
NO OPERATION
4093 drw 07
DATA IN VALID
t
ENS
t
ENH
t
RS
t
RSR
RSA (RSB)
RENA1, RENA2
(RENB1, RENB2)
t
RSF
t
RSF
OEA (OEB) = 1
OEA (OEB) = 0
(2)
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFA, PAFA)
QA
0
- QA
8
(QB
0
- QB
8
)
4093 drw 06
WENA1
(WENB1)
t
RSS
t
RSF
t
RSR
t
RSS
t
RSR
t
RSS
WENA2/LDA
(WENB2/LDB)
(1)
10
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
Figure 6. Read Cycle Timing
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or t CLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. First Data Word Latency Timing
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
t
ENH
t
ENS
NO OPERATION
t
OLZ
VALID DATA
t
SKEW1(1)
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
t
A
t
OE
t
OHZ
RCLKA (RCLKB)
RENA1, RENA2
(RENB1, RENB2)
EFA (EFB)
QA
0
- QA
8
(QB
0
- QB
8
)
OEA (OEB)
WCLKA, WCLKB
WENA1 (WENB1)
WENA2 (WENB2)
4093 drw 08
tDS
D0 (First Valid
tSKEW1
D0D1
D3D2D1
tENS
tFRL(1)
tREF
tA
tOLZ
tOE
tA
WCLKA
(WCLKB)
DA0 - DA8
(DB0 - DB8)
WENA2 (WENB2)
(If Applicable)
RCLKA
(RCLKB)
EFA (EFB)
RENA1, RENA2
(RENB1, RENB2)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
WENA1
(WENB1)
4093 drw 09
tENS
tENS
11
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
Figure 9. Empty Flag Timing
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + t SKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + t SKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
WCLKA
(WCLKB)
DA
0
- DA
8
(DB
0
- DB
8
)
FFA (FFB)
WENA1
(WENB1)
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
RENA1
(RENB2)
QA
0
- QA
8
(QB
0
- QB
8
)
OEA
(OEB)
4093 drw 10
t
SKEW1
t
DS
t
SKEW1
t
ENH
t
ENH
NEXT DATA READDATA READ
t
WFF
t
WFF
t
WFF
t
ENS
t
ENS
DATA IN OUTPUT REGISTER
LOW
NO WRITE NO WRITE
t
A
t
A
t
ENS
t
ENS
t
ENS(1)
t
ENS(1)
t
ENH
t
ENH
NO WRITE
t
DH
t
A
t
DS
t
DS
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
DATA WRITE 2
WCLKA (WCLKB)
DA
0
- DA
8
(DB
0
- DB
8
)
RCLKA (RLCKB)
EFA (EFB)
RENA1, RENA2
(RENB1, RENB2)
OEA (OEB)
QA
0
- QA
8
(QB
0
- QB
8
)DATA READ
t
SKEW1
(1)
t
FRL
t
FRL
DATA IN OUTPUT REGISTER
(1)
t
SKEW1
LOW
WENA2 (WENB2)
(If Applicable)
t
REF
t
REF
t
REF
WENA1, (WENB1)
4093 drw 11
DATA WRITE 1
12
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
NOTES:
1. m = PAF offset.
2 . (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841,
or (8,192-m) words for the IDT72V851.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB)
rising edge.
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
Figure 10. Programmable Full Flag Timing
Figure 11. Programmable Empty Flag Timing
NOTES:
1 . n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between
the rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB)
rising edge.
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
WCLKA
(WCLKB)
WENA1
(WENB1
WENA2
(WENB2)
(If Applicable)
PAFA
(PAFB)
RCLKA
(RCLKB)
RENA1, RENA2
(RENB1, RENB2)
(4)
t
PAF
(1)
Full - (m+1) words in FIFO Full - m words in FIFO
(2)
t
CLKH
t
CLKL
t
SKEW2
(3)
t
PAF
4093 drw 12
WCLKA
(WCLKB)
WENA1
(WENB1)
WENA2
(WENB2)
(If Applicable)
PAEA,
PAEB
RCLKA
(RCLKB)
RENA1, RENA2
(RENB1, RENB2)
t
ENS
t
ENH
t
ENS
t
ENH
t
SKEW2(2)
t
ENS
t
ENH
t
PAE
t
PAE
(3)
(1)
n words in FIFO n+1 words in FIFO
t
CLKH
t
CLKL
4093 drw 13
13
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
Figure 12. Write Offset Register Timing
Figure 13. Read Offset Register Timing
WCLKA (WCLKB)
LDA (LDB)
WENA1 (WENB1)
DA
0
- DA
7
(DB
0
- DB
7
)
4093 drw 14
t
ENS
t
ENH
t
ENS
t
DS
t
DH
PAF OFFSET
(MSB)
PAF OFFSET
(LSB)
PAE OFFSET
(MSB)
PAE OFFSET
(LSB)
t
CLK
t
CLKL
t
CLKH
RCLKA (RCLKB)
LDA (LDB)
RENA1, RENA2
(RENB1, RENB2)
QA0 - QA7
(QB0 - QB7)
4093 drw 15
tENS tENH
tENS
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
tCLK
tA
tCLKLtCLKH
14
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
Device Configuration, the Read Enable 2 RENA2 (RENB2) control input can
Figure 15. Block diagram of the two FIFOs contained in one IDT72V801/72V811/72V821/72V831/72V841/72V851
configured for an 18-bit width-expansion
be grounded (see Figure 14). In this configuration, the Write Enable 2/Load
WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Figure 14. Block Diagram of One of the IDT72V801/72V811/72V821/72V831/72V841/72V851's
two FIFOs configured as a single device
WIDTH EXPANSION CONFIGURATION — Word width may be in-
creased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the end-
point status flags EFA and EFB, also FFA and FFB). The partial status flags PAEA,
PAFB, PAEA and PAFB can be detected from any one device. Figure 15
demonstrates an 18-bit word width using the two FIFOs contained in one
IDT72V801/72V811/72V821/72V831/72V841/72V851. Any word width can
be attained by adding additional IDT72V801/72V811/72V821/72V831/
72V841/72V851s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (RENA2 and RENB2) control inputs can be grounded (see Figure
15). In this configuration, the Write Enable 2/Load (WENA2/LDA, WENB2/LDB)
pins are set LOW at Reset so that the pin operates as a control to load and read
the programmable flag offsets.
QA
0
- QA
8
(QB
0
- QB
8
)
DA
0
- DA
8
(DB
0
- DB
8
)
RSA (RSB)
RCLKA (RCLKB)
RENA1 (RENB1)
OEA (OEB)
EFA (EFB)
PAEA (PAEB)
RENA2 (RENB2)
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2/LDA (WENB2/LDB)
FFA (FFB)
PAFA (PAFB)
IDT
72V801
72V811
72V821
72V831
72V841
72V851
FIFO
A (B)
4093 drw 16
DATA IN
WRITE CLOCK
18
9
RSB
READ CLOCK
918
RENB2RENA2
WRITE ENABLE
FFA
EFB
OUTPUT ENABLE
READ ENABLE
9
WRITE ENABLE/LOAD
FFB
EFA
RSA
RAM
ARRAY
A
DATA OUT
RCLKA
EMPTY FLAG
RENB1
RENA1
OEB
OEA1
RCLKB
WCLKA WCLKB
WENA1 WENB1
DA0 - DA8
DB0 - DB8
QA0 - QA8
QB0 - QB8
WENA2/LDA 2WENB2/LDB
RESET
9
FULL FLAG
4093 drw 17
RAM
ARRAY
B
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
15
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
the intermixed data according to type, sending one kind to FIFO A and the other
kind to FIFO B. Then, at the outputs, each data type is transferred to its
appropriate destination. Additional IDT72V801/72V811/72V821/72V831/
72V841/72V851s permit more than two priority levels. Priority buffering is
particularly useful in network applications.
TWO PRIORITY DATA BUFFER
CONFIGURATION
The two FIFOs contained in the IDT72V801/72V811/72V821/72V831/
72V841/72V851 can be used to prioritize two different types of data shared
on a system bus. When writing from the bus to the FIFO, control logic sorts
Figure 16. Block Diagram of Two Priority Configuration
Figure 17. Block Diagram of Bidirectional Configuration
BIDIRECTIONAL CONFIGURATION
The two FIFOs of the IDT72V801/72V811/72V821/72V831/72V841/
72V851 can be used to buffer data flow in two directions. In the example that
follows, a processor can write data to a peripheral controller via FIFO A, and,
in turn, the peripheral controller can write the processor via FIFO B.
RAM ARRAY A
Processor
Data
D
A0
-D
A8
Q
A0
-Q
A8
OEA
RENA
Address
IDT
72V801
72V811
72V821
72V831
72V841
72V851
D
B0
-D
B8
Q
B0
-Q
B8
OEB2WENB1
Control
Logic
RAM
9-bit bus
RCLKA
WCLKB
Control
9
9
9
9
WCLKA
WENA1
RAM ARRAY B
RENB1
Clock
RCLKB
WENB2 RENB2
WENA2 RENA2
V
CC
V
CC
9
9
Voice
Processing
Card
Data
I/O Data
Clock
Control
Logic
Address
Control
Image
Processing
Card
Data
I/O Data
Clock
Control
Logic
Address
Control
4093 drw 18
RAM ARRAY A
Processor
Peripheral
Controller
Data
DA0-DA8
QA0-QA8
Data
OEA
RENA1
Address
I/O Data
IDT
72V801
72V811
72V821
72V831
72V841
72V851
DB0-DB8
QB0-QB8
OEB
WENB1
Control
Logic
RAM
9-bit bus
9-bit bus
RCLKA
WCLKB
Control
9
9
99
99
WCLKA
WENA1
RAM ARRAY B
RENB1
Clock
RCLKB
DMA Clock
Control
Logic
Address
Control
9
WENB2
RENB2
WENA2 RENA2
V
CC
V
CC
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16
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
DEPTH EXPANSION — These FIFOs can be adapted to applications that
require greater than 256/512/1,024/2,048/4,096/8,192 words. The exist-
ence of double enable pins on the read and write ports allow depth expansion.
The Write Enable 2/Load (WENA2, WENB2) pins are used as a second write
enables in a depth expansion configuration, thus the Programmable flags are
set to the default values. Depth expansion is possible by using one enable
input for system control while the other enable input is controlled by expansion
logic to direct the flow of data. A typical application would have the expansion
logic alternate data access from one device to the next in a sequential manner.
ORDERING INFORMATION
The IDT72V801/72V811/72V821/72V831/72V841/72V851 operates in the
Depth Expansion configuration when the following conditions are met:
1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that
these pins operate as second Write Enables.
2. External logic is used to control the flow of data.
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-
CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for
details of this configuration.
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Green parts available. For specific speeds and packages contact your local sales office.
BLANK
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XXXXX
Device Type
X XX XX
Power Speed Package Process/
Temperature
Range
Clock Cycle Time
(tCLK), speed in
Nanoseconds
Commercial (0°C to +70°C)
Commercial Only
I(1) Industrial (-40°C to +85°C)
PF
TF
Thin Quad Flatpack (TQFP, PN64-1)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
10
15
20 Commercial And Industrial
Commercial Only
LLow Power
72V801 256 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
72V811 512 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
72V821 1,024 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
72V831 2,048 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
72V841 4,096 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
72V851 8,192 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
X
X
G(2) Green
DATASHEET DOCUMENT HISTORY
04/24/2001 pgs. 4, 5 and 16
02/02/2006 pgs. 1 and 16.
10/22/2008 pg. 16.
