UC2841DWG4 - Texas Instruments

UC1841

UC2841

UC3841

Programma ble, Off-Line, PWM Controller

•All Control, Driving, Monitoring, an d

Protection Func tions Included

•Low-current , Off-line Start Circuit

•Voltage Feed Forward or Current

Mode Control

•Guaranteed Duty Cycle Clamp

•PWM Latch for Single Pulse per Period

•Pulse-by-Pulse Current Limiting Plus

Shutdown for Over- Current Fault

•No Start- up or Shutdown Transient s

•Slow Turn-on Both Init ially and After

Fault Shutdown

•Shutdown Upon Over- or

Under-Voltage Sensing

•Latch Of f or Continuous Retry Af ter

Fault

•PWM Output Switch Usable t o 1A

Peak Current

•1% Reference Accurac y

•500kHz Operation

•18 Pin DIL Package

The UC1841 family of PWM controllers has been designed to increase

the level of versatility while retaining all of the performance features of

the earl ier UC18 40 devices. While s till optimized for highly-efficient boot-

strapped primary-side operati on in forward or flyback power converters,

the UC 1841 is equall y adept in implementi ng both l ow and high voltage

input DC to DC converters. Important performance features include a

low-current starting circuit, linear feed-forward for constant volt-second

operation, and compatibility with either voltage or current mode topologies.

In addition to start-up and normal regulating PWM functions, these de-

vices include built in protection from over-voltage, under-voltage, and

over-current fau lt conditions with the option for either latch-of f or automat-

ic restart .

Whi le pi n compatib le with the UC1840 in all respects except that the po-

lari ty o f the External Stop has been re versed, the UC1841 offers the fol-

lowing improvements:

1. Fault latch reset is accompl ished with slow start discharge r ather

than recycling the input voltage to the chip.

2. The External Stop input can be used for a fault delay to r esist

shutdown from short durat ion transients.

3. The duty- cycle clamping funct ion has been characterized an d

specified.

The UC1841 is characterized for -55°C to +125°C operation while the

UC2841 and UC3841 are desi gned for -25°C to +85°C and 0°to +70°C,

respectively.

BL OCK DIAG RAM

No te : Positive tru e logic, latch out put s high with set , reset has prior ity.

6/93

DESCRIPTIONFEATURES

PARAMETER TEST CONDI TION S UC1841 / UC2841 UC3841 UNITS

MIN TYP MAX MIN TYP MAX

Power In puts

Start - Up Curr ent VIN = 30V, Pin 2 = 2.5 V 4.5 6 4.5 6 mA

Oper at ing Cur ren t VIN = 30V, Pin 2 = 3. 5V 10 14 10 14 mA

Supply OV Clamp IIN = 20mA 33 40 45 33 40 45 V

Refere nce S ec tio n

Reference Voltage TJ = 25°C 4. 95 5 .0 5. 05 4 .9 5.0 5 .1 V

Line Reg ulat ion VIN = 8 to 30V 10 15 10 20 mV

Load Regulat ion IL = 0 to 10mA 1020 1030mV

Tempe ratur e Stability Over Opera ting Temper ature Range 4.9 5.1 4.8 5 5.1 5 V

Short Circuit Current VREF = 0, TJ = 25°C -80 -100 -80 -100 mA

Oscillator

Nominal Fre quen cy T J = 25°C 47 50 53 45 50 55 kHz

Voltage St ability V IN = 8 to 30V 0.5 1 0.5 1 %

Tempe ratur e Stability Over Opera ting Temper ature Range 45 55 43 57 kH z

Maximum Frequency RT = 2k Ω, CT = 330pF 500 500 k Hz

UC1841

UC2841

UC3841

ELECTRICAL CHARACTERISTICS: Unless othe rwise st ated , thes e spec ifications apply f or TA = -55°C to +125°C f or the

UC1 841, -25°C to +85°C for the UC2841, and 0°C to +70 °C f or the UC3841 ; VIN = 20V, R T = 20kΩ, CT = .001mfd, RR = 10k Ω,

CR = .001mfd, Cur ren t Limit Th res hold = 200 mV, TA = T J.

Su pply Volt age, +V IN (Pin 15 ) (Note 2)

Voltage Driven. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 32V

Current Driven, 100mA maximum. . . . . . . . . . . . Self-limiting

PWM Out put Volta ge (Pin 12 ) . . . . . . . . . . . . . . . . . . . . . . . 40V

PW M O utput Current, Steady- Stat e (Pin 12). . . . . . . . . 400mA

PWM Output Peak E nergy Dischar ge . . . . . . . . . . . . 20µJoules

Driver Bias Current (Pin 14). . . . . . . . . . . . . . . . . . . . . -200m A

Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA

Slow-St art Sink Cur ren t (Pin 8) . . . . . . . . . . . . . . . . . . . . 20m A

VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA

Cu rrent Limit Input s (Pins 6 & 7) . . . . . . . . . . . . . -0. 5 to +5. 5V

Stop Inp ut (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5. 5 V

Co mp ara to r Inputs

(Pins 1, 7, 9-11, 16). . . . . . . . . . . . Int ernal ly clamp ed at 1 2 V

Po wer Dissipa tion at T A = 25°C (Not e 3) . . . . . . . . . . . 1000mW

Po wer Dissipa tion at T C = 25°C (Not e 3). . . . . . . . . . . 2000mW

Op era ting Junct ion Te mp era tu re . . . . . . . . . . -55 °C to +1 50°C

Storage Temper ature Range. . . . . . . . . . . . . . -65°C to +1 50°C

L ead Te mp era ture (Solder ing, 10 sec) . . . . . . . . . . . . . +3 00°C

Note 1: All voltages are with respect to ground, Pin 13.

Curre nt s are p osit ive-int o, neg ativ e-o ut o f the specif ie d

terminal.

No te 2: All pin number s are r efer ence d to DI L- 18 pa ckag e.

No te 3: Consult Packag in g Sect ion of Dat aboo k for ther ma l

limitat ions an d cons iderations of package.

CONNECTION DIAGRAMS

PLCC-20, LCC-20

(TOP VIEW)

Q or L Package

DIL -18, SO IC- 18 (T O P VI EW)

J or N, DW Package

PACKAGE PIN FUNCTIONS

FUNCTION PIN

Comp 1

Start/UV 2

OV Sense 3

Stop 4

Reset 5

CUR Thresh 7

CUR Sense 8

Slow Start 9

RT/CT10

Ramp 11

VIN Sense 12

PWM O ut 13

Ground 14

Drive Bias 15

+VIN Supply 17

5.0V REF 18

Inv. Input 19

N.I . In pu t 20

ABSOL UTE MAXIMUM RATING S

PARAMETER TEST CONDI TION S UC18 41 / UC2841 UC3841 UNITS

MIN TYP MAX MIN TYP MAX

Ram p G e nerator

Ramp Curren t, Minimum ISENSE = -10 µA -11 -14 -11 -14 µA

Ramp Cur ren t, Maximum ISENSE = 1. 0mA -0.9 -.95 -0.9 -.95 mA

Ramp Valley 0.3 0.4 0.6 0.3 0.4 0. 6 V

Ramp Peak Clamp ing Leve l 3.9 4.2 4. 5 3.9 4. 2 4.5 V

Error Amplifier

Input O ffset Volta ge VCM = 5.0V 0 .5 5 2 10 mV

Input Bias Current 0.5 2 1 5 µA

Input O ffset Curr ent 0.5 0.5 µA

Open Loop Gain ∆VO= 1 to 3V 60 66 60 66 dB

Output Swing (Max. Outpu t ≤

Ramp Peak - 100mV) Minimum Tot al Range 0.3 3.5 0. 3 3.5 V

CMRR VCM = 1.5 to 5.5V 70 80 70 80 dB

PSRR VIN = 8 to 30V 70 80 70 80 dB

Short Circuit Current VCOMP = 0V - 4 -10 - 4 -1 0 mA

Gain Band w idth* TJ = 25°C, AVOL = 0dB 1 2 1 2 MHz

Slew Rate* T J = 25°C, AVCL = 0 d B 0. 8 0. 8 V/µs

PWM Section

Continuo us Dut y Cycle

Range* (other than zero) Minimum Tot al Cont inuou s Range,

Ramp Peak < 4. 2V 495495%

50% Dut y Cycle Clamp R SENSE to VREF = 10k 42 47 52 42 47 52 %

Out put Satur at ion IOUT = 20mA 0.2 0.4 0.2 0.4 V

IOUT = 200 m A 1. 7 2. 2 1.7 2.2 V

Out put Lea kage V OUT = 40V 0.1 10 0.1 10 µA

Compar at or Dela y* Pin 8 t o Pin 12, T J = 25°C, RL = 1kΩ300 500 300 500 ns

Sequencing Functions

Compar at or Thre sholds P ins 2, 3, 5 2.8 3. 0 3.2 2. 8 3. 0 3.2 V

Input Bias Cur ren t Pins 3, 5 = 0V -1. 0 - 4. 0 -1.0 - 4. 0 µA

Input Leakage Pins 3, 5 = 10V 0.1 2.0 0.1 2.0 µA

Start /UV Hyst er esis Cur ren t Pin 2 = 2.5V 1 70 2 00 2 20 1 70 2 00 2 30 µA

Ext. Stop Threshold Pin 4 0.8 1.6 2.4 0.8 1.6 2.4 V

Error Latch Act ivat e Cur ren t P in 4 = 0V, Pin 3 > 3V -120 -20 0 -120 -20 0 µA

Driver Bias Satur at ion Volta ge,

VIN - V OH IB = -50mA 2 3 2 3 V

Driver Bias Leakage V B = 0V -0.1 -10 -0.1 -10 µA

Slow-Start Saturation IS = 10mA 0.2 0.5 0.2 0.5 V

Slow-Start Leakage VS = 4. 5V 0. 1 2. 0 0.1 2.0 µA

Curren t Contro l

Curren t Lim it Off set 0 5 0 1 0 mV

Curren t Shu tdown O ffs et 370 400 4 30 360 400 440 mV

Input Bias Current Pin 7 = 0V -2 -5 -2 -5 µA

Comm on M ode Ran ge* -0. 4 3. 0 -0. 4 3. 0 V

Curren t Limit Delay* T J = 25 °C, Pin 7 to 12, R L = 1k 200 400 200 400 ns

* Thes e par amet ers are guara nt eed by design bu t not 100% t es ted in p rod uct ion.

UC1841

UC2841

UC3841

ELECTRICAL CHARACTERISTICS: Unless othe rwise st ated , thes e spec ifications apply f or TA = -55°C to +125°C f or the

UC1 841, -25°C to +85°C for the UC2841, and 0°C to +70 °C f or the UC3841 ; VIN = 20V, R T = 20kΩ, CT = .001mfd, RR = 10k Ω,

CR = .001mf d, Current Lim it Threshold = 200mV, TA = TJ.

PWM CONTRO L

1. Oscillator Gen era tes a fixed-f requency inter nal clock f ro m an external RT and CT.

Frequency = KC

RTCT where K C is a first order correction factor ≈ 0.3 log (CT X 1012).

2. Ramp G enerat or Develops a linear ramp wit h a slope define d externally by dv

dt = sense voltage

RRCR

CR is normally se le ct ed ≤ CT and its valu e will have som e effect upon va lley voltage.

Limiting the minimum value for I SENSE will establish a maxim um duty cyc le clamp .

CR terminal can be used as an input por t for cur ren t mode cont ro l.

3. Error Am plifier Con vent iona l opera tion al amp lif ier for closed- loop ga in and phase com pe nsat ion.

Low output impedance; unity-gain stable.

The out put is held low by the slow star t voltag e at t urn on in or der to m inimize overshoo t.

4. Ref ere nce Ge n era tor Precision 5. 0V f or inter nal and ext ern al usage to 50 mA.

Track in g 3.0V ref erence for internal usage only w ith nomina l accur acy of ± 2%.

40 V clamp zener for chip OV prot ect ion, 100m A maxim um current .

5. PWM Compar at or Gen era tes out put pulse which start s at terminat ion of clock pulse and ends whe n the ramp

input cross es the lowest of two posit iv e input s.

6. PWM Latch Te rminat es the PW M out put pulse whe n set by input s from eit her the PWM compa rat or, t he

puls e-b y-p ulse cur re nt limit com pa rator , or the error la tch. Reset s with each inter nal clock

pulse.

7. PWM Out put Switch Trans is tor cap able of sinking cu rrent to ground which is of f during the PWM on- time and t ur ns

on to ter mina te the power pulse. Curr ent capacit y is 400m A sat ur ated with peak

capacit anc e discha rge in excess of one amp.

SEQUENCING FUNCTIONS

1. Sta rt/UV Se nse With an incre asing vo lta g e, it generat es a tur n- on signa l and relea ses the slow- st ar t clamp at

a start threshold.

With a decr easing voltage, it gen era tes a turn- off comma nd at a lower leve l separ at ed by a

200µA hy st ere sis cur ren t.

2. Drive Swit ch Disab les most of the chip to ho ld inter nal curre nt consump tion low, and Dr iver Bias OFF, until

input voltag e rea ches sta rt threshold.

3. Driver Bias Supp lies drive current to exter nal power switch to provide tu rn-on bias .

4. Slow Star t Clamps low to hold PW M OFF . Upo n release, rises with ra te cont ro lled by RSCS for slow

increas e of output pulse widt h.

Can also be use d as an alt ernat e m axim um duty cycle clam p with an ext er nal volt age divid er.

PROTECTI O N FUNCTIO NS

1. Error La tch When s et b y mome nt ary input , this latch insur es im me diat e PWM shutd own and hold of f until

reset . Input s t o Err or La tch are :

a. OV > 3.2V (typica lly 3V)

b. Stop > 2.4V (typically 1.6V)

c. Curren t Sense 400 mV over thr esho ld (typical) .

Error Latch r eset s whe n slow start voltage falls to 0.4V if Rese t Pin 5 < 2. 8V. With Pin 5 >

3.2V, Error Latch will remain set.

2. Curr ent Limiting Diffe rential input com parator te rm inates individu al o ut put pulses each time sense volta ge

ris es abo ve thre shold.

When sense volta ge rise s to 400m V (typica l) above th res hold, a shutdo wn signal is sent to

Error Latch.

3. Ext ern al Stop A voltage over 1.2 V will s et the Error Latch and hold t he ou tput off.

A voltage less than 0. 8V w i ll defea t the er ro r latch and prev ent shut do wn.

A capacit or he re will slow the ac tion of the erro r latch for transient pr otect ion by providing a

typical delay of 13ms/µF.

UC1841

UC2841

UC3841

F UNCTIO NAL DES CRIP TIO N

UC1841

UC2841

UC3841

Start/UV Hysteresis

PWM Outp ut Minimu m Pu lse W idthOscillator Frequency

PWM Output-Saturation Voltage

Shutdown TimingErro r Ampl ifier Op en L oo p Gain and P hase

FLYBACK APPL ICATION (A)

In this application (see Figure A, next page), complete

control is maintained on the primary side. Control power

is provided by RIN and CIN during start-up, and by a pri-

mary-referenced low voltage winding, N2, for efficient op-

eration after start. The error amplifier loop is closed to

regulate the DC voltage from N2 with other outputs fol-

lowing through their magnetic coupling − a task made

even easier with the UC1841’s feed−forward line regula-

tion.

An extension to this application for more precise regula-

tion would be the use of the UC1901 Isolated Feedback

Generat or for direct closed-loop control to an output.

Not shown, are protective snubbers or additional interface

circuitry whi ch may be requi red by the choice of the high-

voltage switch, Qs, or the application; however, one ex-

ample of power transistor interfacing is provided on the

following page.

RE GUL ATO R A PP LI C ATION ( B)

With the addition of a level shifting transistor, Q1, the

UC1841 is an ideal control circuit for DC to DC converters

such as the buck regulator shown in Figure B opposite. In

addition to providing constant current drive pulses to the

PIC661 power switch, this circuit has full fault protection

and high speed dynamic line regulation due to its feed-

forward capability. An additional feature is the ability to

UC1841

UC2841

UC3841

OPE N-LOO P TEST CIRCUIT

Nominal Fre quen cy = 1

RTCT = 50 kHz

St art Volta g e = 3 





R1 + R2 + R3

R2 + R3 



 +0.2R1 = 12V

UV Fault Voltage = 3 





R1 + R2 + R3

R2 + R3 



 = 8 V

OV Fault Voltage = 3 



R1 + R2 + R3

R3 



 = 32V

Cur ren t Limit = 200m V

Current Fault Voltag e = 600m V

Duty Cycle Clam p = 50%

UC1841

UC2841

UC3841

Figure A. UC1841 Pr ogr amma ble PW M Cont roller In A Simplified Flyback Regulat or

Figure B. Overall Schem at ic For A 300 Watt, Off-line Power Con ver te r Using The U C3841 For Co nt rol

Since Pin 10 is a direct input to the PWM comparator, this

point can also serve as a current sense port for current mode

control. In this application, current sensing is ground refer-

enced through RCS. Resistor R1 sets a 400mV offset across

R2 (assuming R2 > RCS) so that both the Error Amplifier and

Fault Shutdown can force the current com p lete ly to ze ro. R2 is

also used along with CF as a small filter to a ttenuate leading-

edge spikes on the load current waveform. In this mode,

current limiting can be accomplished by divider R3/R4 which

for ms a clam p o ver riding the out put of t he Er ror Am plifier.

In this circuit, R1 is used in conjunction with CR (not shown) to

establish a minimum ramp charging current such that the ram p

voltage reaches 4.2V at the required maximum output pulse

width.

The purpose of Q1 is to provide an increasing ramp current

above a threshold establis hed b y R2 and R3 su ch that t he d uty

cycle is furth er reduc ed with increa sing VIN.

The minimum ramp c urrent is:

lR(MIN) = VREF − VIN SENSE

R1 ≈ 4

The thresh old wher e VIN begins to add extra ram p cur ren t is:

VIN ≈ 5.6 V 



R2 + R3

R3 





Above th e thres hold, the ramp curr ent will be:

lR (VARIAB ) ≈ 4

R1 + VIN − 5.6

R2 − 5.6

UC1841

UC2841

UC3841

ERROR LATCH INT ERNAL CIRCUI TRY PROGRAMMABL E SOFT START AND

RESTART DEL AY CIRCUI T

The Error Latch consists of Q5 and Q6 which, when both on,

turns of f the PW M Output and pulls the Slow-Start pin low . This

latch is set by either the Over-Voltage or Current Shutdown

comparators, or by a high signal on Pin 4. Reset is accom-

plished by ei ther the Reset comparator or a low signal on Pin

4. An activation time delay can be provided with an external

capacitor on Pin 4 in conjunction with the ≈ 100µA collector

c urrent f rom Q4.

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

VOLTAGE FEED-F O RWARD COMBI NED WIT H

MAXIMUM DUTY-CYCLE CLAMP

CURRENT MODE CO NTRO L

PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

5962-8992002VA OBSOLETE CDIP J 18 TBD Call TI Call TI Samples Not Available

UC1841J OBSOLETE CDIP J 18 TBD Call TI Call TI Samples Not Available

UC1841J883B OBSOLETE CDIP J 18 TBD Call TI Call TI Samples Not Available

UC1841L OBSOLETE LCCC FK 20 TBD Call TI Call TI Samples Not Available

UC1841L883B OBSOLETE LCCC FK 20 TBD Call TI Call TI Samples Not Available

UC2841DW ACTIVE SOIC DW 18 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

UC2841DWG4 ACTIVE SOIC DW 18 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

UC2841J OBSOLETE CDIP J 18 TBD Call TI Call TI Samples Not Available

UC2841N ACTIVE PDIP N 18 20 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type Purchase Samples

UC2841NG4 ACTIVE PDIP N 18 20 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type Purchase Samples

UC3841DW ACTIVE SOIC DW 18 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

UC3841DWG4 ACTIVE SOIC DW 18 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

UC3841J OBSOLETE CDIP J 18 TBD Call TI Call TI Samples Not Available

UC3841N ACTIVE PDIP N 18 20 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples

UC3841NG4 ACTIVE PDIP N 18 20 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2010

Addendum-Page 2

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1841, UC3841 :

•Catalog: UC3841

•Military: UC1841

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Military - QML certified for Military and Defense Applications

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Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DLP® Products www.dlp.com Communications and www.ti.com/communications

Telecom

DSP dsp.ti.com Computers and www.ti.com/computers

Peripherals

Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps

Interface interface.ti.com Energy www.ti.com/energy

Logic logic.ti.com Industrial www.ti.com/industrial

Power Mgmt power.ti.com Medical www.ti.com/medical

Microcontrollers microcontroller.ti.com Security www.ti.com/security

RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defense

Defense

RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video

Wireless www.ti.com/wireless-apps

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265