Wideband, High Output Current
Fast Settling Op Amp
Data Sheet
AD842
FEATURES
AC performance
Gain bandwidth product: 80 MHz (gain = 2)
Fast settling: 100 ns to 0.01% for a 10 V step
Slew rate: 375 V/µs
Stable at gains of 2 or greater
Full power bandwidth: 6 MHz for 20 V p-p
DC performance
Input offset voltage: 1.5 mV maximum
Input offset drift: 14 µV/°C
Input voltage noise: 9 nV/√Hz
Open-loop gain: 90 V/mV into a 499 Ω load
Output current: 100 mA minimum
Quiescent supply current: 14 mA maximum
APPLICATIONS
Line drivers
DAC and ADC buffers
Video and pulse amplifiers
MIL-STD-883B parts available, see military data sheet
CONNECTION DIAGRAMS
Figure 1. PDIP (N-14) and CERDIP (Q-14)
Figure 2. SOIC_W (RW-16)
GENERAL DESCRIPTION
The AD842 is a member of the Analog Devices, Inc. family of
wide bandwidth operational amplifiers. This device is fabricated
using the Analog Device junction isolated complementary
bipolar (CB) process. This process permits a combination of dc
precision and wideband ac performance previously unobtain-
able in a monolithic op amp. In addition to its 80 MHz gain
bandwidth product, the AD842 offers extremely fast settling
characteristics, typically settling to within 0.01% of final value
in less than 100 ns for a 10 V step.
The AD842 also offers a low quiescent current of 13 mA, a high
output current drive capability (100 mA minimum), a low input
voltage noise of 9 nV√Hz, and a low input offset voltage
(1.5 mV maximum).
The 375 V/µs slew rate of the AD842, along with its 80 MHz
gain bandwidth product, ensures excellent performance in
video and pulse amplifier applications. This amplifier is ideally
suited for use in high frequency signal conditioning circuits and
wide bandwidth active filters. The extremely rapid settling time
of the AD842 makes this amplifier the preferred choice for data
acquisition applications requiring 12-bit accuracy. The AD842
is also appropriate for other applications, such as high speed
DAC and ADC buffer amplifiers and other wide bandwidth
circuitry.
PRODUCT HIGHLIGHTS
1. The high slew rate and fast settling time of the AD842
make it ideal for DAC and ADC buffers amplifiers, line
drivers, and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth, performance
previously available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
1.5 mV maximum, thus eliminating the need for external
offset nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain is 2 or greater.
NIC
NIC
BALANCE
–INPUT
+INPUT
V–
NIC
NIC
BALANCE
NIC
V+
OUTPUT
NIC
NIC
+
1
2
3
4
14
13
12
11
5
6
7
10
9
8
NOTES
1. NI C = NOT INT E RNALLY CONNECTED.
AD842
TOP VIEW
(No t t o Scal e)
09477-001
1
2
3
4
16
15
14
13
512
6 11
710
89
AD842
TOP VIEW
(No t t o Scal e)
09477-002
BALANCE
–INPUT
NIC
+INPUT
NIC
–VS
NIC
BALANCE
+VS
NIC
OUTPUT
NIC
NIC
NIC
+
NIC NIC
NOTES
1. NI C = NOT INT E RNALLY CONNECTED.
Rev. F Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1988–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
AD842 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics−±15 V Operation ............................ 3
Absolute Maximum Ratings ............................................................ 4
Thermal Characteristics .............................................................. 4
ESD Caution .................................................................................. 4
Metalization Photograph ............................................................. 4
Typical Performance Characteristics ..............................................5
Theory of Operation .........................................................................9
Offset Nulling ................................................................................9
Settling Time ..................................................................................9
Grounding and Bypassing ......................................................... 10
Capacitive Load Driving Ability ............................................... 10
Using a Heat Sink ....................................................................... 10
Terminated Line Driver ............................................................. 10
Overdrive Recovery ................................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
REVISION HISTORY
2/14—Rev. E to Rev. F
Updated Format .................................................................. Universal
Deleted 20-Terminal LCC and 12-Pin TO-8 .................. Universal
Changed NC Pin to NIC Pin Throughout .................................... 1
Changes to Features, General Description, Connection
Diagrams, and Product Highlights Sections ................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2, Thermal Characteristics Section, Table 3,
and Figure 3 ....................................................................................... 4
Changes to Figure 11, Figure 13, Figure 14, and Figure 15 ........ 6
Changes to Figure 18......................................................................... 7
Changes to Figure 22 Caption, Figure 23 Caption, Figure 24,
and Figure 27...................................................................................... 8
Changes to Figure 28......................................................................... 9
Changes to Using a Heat Sink Section and Figure 32 ................ 10
Changes to Figure 34...................................................................... 11
Updated Outline Dimensions ....................................................... 12
Added Ordering Guide .................................................................. 13
3/00—Rev. D to Rev. E
Rev. F | Page 2 of 16
Data Sheet AD842
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—±15 V OPERATION
TA = 25°C, unless otherwise specified. All minimum and maximum specifications are guaranteed. Specifications shown in boldface are
tested on all production units.
Table 1.
Parameter
Test Conditions/
Comments
AD842JN/AD842JQ/AD842JR1 AD842KN/AD842KQ AD842SQ
Unit
Min Typ Max Min Typ Max Min Typ Max
INPUT OFFSET VOLTAGE
2
0.5 1.5 0.3 1.0 0.5 1.5 mV
T
MIN
to T
MAX
2.5/2.5/3 1.5 3.5 mV
Offset Drift 14 14 14 µV/°C
INPUT BIAS CURRENT 4.2 8 3.5 5 4.2 8 µA
T
MIN
to T
MAX
10 6 12 µA
Input Offset Current 0.1 0.4 0.05 0.2 0.1 0.4 µA
T
MIN
to T
MAX
0.5 0.3 0.6 µA
INPUT CHARACTERISTICS Differential mode
Input Resistance 100 100 100 kΩ
Input Capacitance 2.0 2.0 2.0 pF
INPUT VOLTAGE RANGE
Common Mode
±10
±10
±10
V
Common-Mode Rejection V
CM
= ±10 V 86 115 90 115 86 115 dB
T
MIN
to T
MAX
80 86 80 dB
INPUT VOLTAGE NOISE f = 1 kHz 9 9 9 nV/√Hz
Wideband Noise
10 Hz to 10 MHz
28
28
28
µV rms
OPEN-LOOP GAIN V
OUT
= ±10 V
R
LOAD
≥ 499 Ω 40/40/30 90 50 90 40 90 V/mV
TMIN to TMAX 20/20/15 25 20 V/mV
OUTPUT CHARACTERISTICS
Voltage R
LOAD
≥ 499 Ω ±10 ±10 ±10 V
Current V
OUT
= ±10 V 100 100 100 mA
Open loop 5 5 5 Ω
FREQUENCY RESPONSE
Gain Bandwidth Product VOUT = 90 mV,
A
VCL
= 2
80 80 80 MHz
Full Power Bandwidth3 VOUT = 20 V p-p,
R
LOAD
≥ 499 Ω
4.7 6 4.7 6 4.7 6 MHz
Rise Time A
VCL
= −2 10 10 10 ns
Overshoot A
VCL
= −2 20 20 20 %
Slew Rate A
VCL
= −2 300 375 300 375 300 375 V/µs
Settling Time4 10 V step
To 0.1% 80 80 80 ns
To 0.01% 100 100 100 ns
Differential Gain
f = 4.4 MHz
0.015
0.015
0.015
%
Differential Phase
f = 4.4 MHz
0.035
0.035
0.035
Degree
POWER SUPPLY
Rated Performance ±15 ±15 ±15 V
Operating Range ±5 ±18 ±5 ±18 ±5 ±18 V
Quiescent Current 13/13/14 14/14/16 13 14 13 14 mA
TMIN to TMAX 16/16/19.5 16 19 mA
Power Supply Rejection
Ratio
±VS = ±5 V to
±18 V
86 100 90 105 86 100 dB
T
MIN
to T
MAX
80 86 80 dB
1 AD842JR specifications differ from those of the AD842JN and AD842JQ due to the thermal characteristics of the SOIC package.
2 Input offset voltage specifications are guaranteed after 5 minutes at TA = 25°C.
3 Full power bandwidth = slew rate/2 π V peak.
4 Refer to Figure 29 and Figure 30.
Rev. F | Page 3 of 16
AD842 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation1
PDIP (N-14), SOIC_W (RW-16) 1.3 W
CERDIP (Q-14) 1.1 W
Input Voltage ±VS
Differential Input Voltage ±6 V
Operating Temperature Range
CERDIP (Q-14, AD842SQ Only)
−55°C to +125°C
PDIP (N-14), SOIC_W (RW-16),
CERDIP (Q-14, AD842JQ and
AD842KQ Only)
0°C to 70°C
Storage Temperature Range
CERDIP (Q-14, All Models) −65°C to +150°C
PDIP (N-14), SOIC_W (RW-16)
−65°C to +125°C
Junction Temperature 175°C
Lead Temperature (Soldering 60 sec) 300°C
1 Maximum internal power dissipation is specified so that TJ does not exceed
150°C at an ambient temperature of 25°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Table 3.
Package θJC θJA θSA Unit
14-Lead PDIP 30 100 °C/W
14-Lead CERDIP 30 110 38 °C/W
16-Lead SOIC_W 30 100 °C/W
ESD CAUTION
METALIZATION PHOTOGRAPH
Figure 3. Contact Factory for Latest Dimensions,
Dimensions Shown in Inches and (Millimeters)
OUTPUT
V+
V–
0.067
(1.69)
BALANCE
0.106 ( 2.68)
BALANCE
+INPUT
–INPUT
09477-003
Rev. F | Page 4 of 16
Data Sheet AD842
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C and VS = ±15 V, unless otherwise noted.
Figure 4. Input Common-Mode Range vs. Supply Voltage
Figure 5. Output Voltage Swing vs. Supply Voltage
Figure 6. Output Voltage Swing vs. Load Resistance
Figure 7. Quiescent Current vs. Supply Voltage
Figure 8. Input Bias Current vs. Temperature
Figure 9. Output Impedance vs. Frequency
SUPPLY VOLT AGE (±V)
INPUT COMMON-MODE RANGE (V)
20
15
020151050
10
5
V
IN
09477-004
SUPPLY VOLT AGE (±V)
OUTPUT VOLTAGE SWING (V)
20
15
020151050
10
5
±V
OUT
09477-005
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE SWING (V p-p)
30
25
010k10010 1k
20
15
5
10
±15V SUPPL I ES
09477-006
SUPPLY VOLT AGE (±V)
QUI E S CE NT CURRENT (mA)
18
16
10 20151050
14
12
09477-007
TEMPERATURE (°C)
INPUT BI AS CURRE NT (µA)
–5
–4
–2
–60 –40 –20 020 140120100806040
–3
09477-008
FRE Q UE NCY ( Hz )
OUTPUT IMPEDANCE (Ω)
100
10
0.01 100M10M100k 1M
10k
1
0.1
09477-009
Rev. F | Page 5 of 16
AD842 Data Sheet
Figure 10. Quiescent Current vs. Temperature
Figure 11. Short-Circuit Current Limit vs. Temperature
Figure 12. Gain Bandwidth Product vs. Temperature
Figure 13. Open-Loop Gain and Phase Margin vs. Frequency
Figure 14. Open-Loop Gain vs. Supply Voltage
Figure 15. Power Supply Rejection vs. Frequency
TEMPERATURE (°C)
QUI E S CE NT CURRENT (mA)
18
15
10
17
16
13
11
14
12
–60 –40 –20 020 140120100806040
09477-010
TEMPERATURE (°C)
SHORT-CIRCUI T CURRENT L IMI T (mA)
300
225
100
275
250
175
125
200
150
–OUTPUT CURRE NT
+OUTPUT CURRENT
–60 –40 –20 020 140120100806040
09477-011
GAI N BANDWI DTH (M Hz )
85
80
65
75
70
TEMPERATURE (°C)
–60 –40 –20 020 140120100806040
09477-012
FRE Q UE NCY ( Hz )
OPEN-LOOP GAIN (dB)
120
0100M
100 1k 10k 100k 1M 10M
100
80
60
40
20
100
80
60
40
20
0
PHASE M ARGI N ( Degrees)
499Ω LOAD
09477-013
SUPPLY VOLT AGE (±V)
OPEN-LOOP GAIN (dB)
110
105
90 20151050
100
95
09477-014
499Ω LOAD
FRE Q UE NCY ( Hz )
POWER SUPPLY REJECTION (dB)
120
0100M100 1k 10k 100k 1M 10M
100
80
60
40
20
09477-015
–V
S
+V
S
Rev. F | Page 6 of 16
Data Sheet AD842
Figure 16. Common-Mode Rejection vs. Frequency
Figure 17. Large Signal Frequency Response
Figure 18. Output Swing vs. Settling Time
Figure 19. Harmonic Distortion vs. Frequency
Figure 20. Input Voltage vs. Frequency
Figure 21. Slew Rate vs. Temperature
FRE Q UE NCY ( Hz )
COM M ON-MODE RE JE CTI ON (dB)
120
20 100M1k 10k 100k 1M 10M
100
80
60
40
09477-016
V
S
= ±15V
V
CM
= 1V p-p
T
A
= 25° C
FRE Q UE NCY ( Hz )
OUTPUT VOLTAGE (V p-p)
30
25
01M 10M 100M
20
15
10
5
R
L
= 1kΩ
T
A
= 25° C
V
S
= ±15V
09477-017
SETTLING TIME (ns)
OUTPUT SWING (V)
10
–10 11040 50 60 70 80 90 10030
8
2
0
–4
–8
6
4
–2
–6
0.1%
0.1%
0.01%
0.01%
09477-018
FRE Q UE NCY ( Hz )
HARMO NIC DIS TO RTI ON (dB)
–80
–90
–140
100 1k 10k 100k
–100
–110
–130
–120
SECO ND HARM ONI C
09477-019
THIRD HARMO NIC
3V rms
R
L
= 1kΩ
FRE Q UE NCY ( Hz )
INPUT VOLTAGE (nV√Hz)
50
40
010 100 1k 10k 100k 1M 10M
30
20
10
09477-020
SLEW RATE (V/µs)
550
400
250
500
450
350
300
TEMPERATURE (°C)
–60 –40 –20 020 140120100806040
09477-021
Rev. F | Page 7 of 16
AD842 Data Sheet
Figure 22. Inverting Large Signal Pulse Response (see Figure 24)
Figure 23. Inverting Small Signal Pulse Response (see Figure 24)
Figure 24. Inverting Amplifier Configuration (PDIP)
Figure 25. Noninverting Large Signal Pulse Response (see Figure 27)
Figure 26. Noninverting Small Signal Pulse Response (see Figure 27)
Figure 27. Noninverting Amplifier Configuration (PDIP)
09477-022
100%
90%
0%
10%
2V 50ns
09477-023
100%
90%
0%
10%
50mV 50ns
+VS
–VS
VOUT
499Ω
332Ω
2.2µF
0.1µF
2.2µF
0.1µF
FUNCTION
GENERATOR
RIN =
499Ω
RF = 1kΩ
AD842
11
6
10
4
5
49.9Ω
09477-026
09477-024
100%
90%
0%
10%
2V 50ns
09477-025
100%
90%
0%
10%
50mV 50ns
+VS
–VS
VOUT
499Ω
2.2µF
0.1µF
2.2µF
0.1µF
FUNCTION
GENERATOR
100Ω
RF = 205ΩRF = 205Ω
VIN
AD842
11
6
10
4
5
49.9Ω
09477-027
Rev. F | Page 8 of 16
Data Sheet AD842
THEORY OF OPERATION
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 28 can be used.
SETTLING TIME
Figure 29 and Figure 31 show the settling performance of the
AD842 in the test circuit shown in Figure 30.
Settling time is the interval of time from the application of an
ideal step function input until the closed-loop amplifier output
enters and remains within a specified error band.
This definition encompasses the major components that
comprise settling time. They include the following:
• Propagation delay through the amplifier.
• Slewing time to approach the final output value.
• Time of recovery from the overload associated with
slewing.
• Linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time
must be accurate to assure the user that the amplifier is worth
consideration for the application.
Figure 28. Offset Nulling (PDIP)
Figure 29. 0.01% Settling Time
Figure 30 shows how measurement of the AD842 0.01% settling
in 100 ns is accomplished by amplifying the error signal from a
false summing junction with a very high speed proprietary
hybrid error amplifier specially designed to enable testing of
small settling errors. Under test, the device drives a 300 Ω load.
The input to the error amp is clamped to avoid possible
problems associated with the overdrive recovery of the
oscilloscope input amplifier. The error amp gains the error from
the false summing junction by 15, and it contains a gain vernier
to fine trim the gain.
Figure 31 shows the long-term stability of the settling
characteristics of the AD842 output after a 10 V step. There is
no evidence of settling tails after the initial transient recovery
time. The use of a junction isolated process, together with
careful layout, avoids these problems by minimizing the effects
of transistor isolation capacitance discharge and thermally
induced shifts in circuit operating points. These problems do
not occur even under high output current conditions.
Figure 30. Settling Time Test Circuit (PDIP)
+V
S
–V
S
V
OUT
RL
2.2µF
0.1µF
2.2µF
0.1µF
10kΩ
V
IN
AD842
11
313
6
10
4
5
09477-028
09477-029
100%
90%
0%
10%
10mV10V 20ns
OUTPUT:
10V/DIV
OUTPUT
ERROR:
0.02%/DIV
2.2µF
0.1µF
2.2µF
0.1µF 499Ω
499Ω
–15V
DDD5109
FLAT-TOP
PULSE
GENERATOR
50Ω
499Ω 1kΩ
499Ω 1kΩ
+15V
HP6263
ERROR
AMP
(×15) TEK
7603
OSCILLOSCOPE
TEK
7A13
TEK
7A16
FET PROBE
TE K P6201
AD842
11
6
10
4
5
09477-030
Rev. F | Page 9 of 16
AD842 Data Sheet
GROUNDING AND BYPASSING
In designing practical circuits with the AD842, the user must
take some special precautions whenever high frequencies are
involved.
Figure 31. AD842 Settling Demonstrating No Settling Tails
Circuits must be built with short interconnect leads. Use large
ground planes whenever possible to provide a low resistance,
low inductance circuit path; this also minimizes the effects of
high frequency coupling. Avoid sockets because the increased
interlead capacitance can degrade bandwidth.
Use feedback resistors of low enough value to ensure that the
time constant formed with the circuit capacitances does not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a
small (<10 pF) feedback capacitor connected in parallel with
the feedback resistor, RF, can be used to compensate for these
stray capacitances and to optimize the dynamic performance of
the amplifier in the particular application.
Bypass power supply leads to ground as close as possible to the
amplifier pins. A 2.2 μF capacitor in parallel with a 0.1 μF
ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD842 is sensitive to
capacitive loading. The AD842 is designed to drive capacitive
loads of up to 20 pF without degradation of its rated
performance. Capacitive loads of greater than 20 pF decrease
the dynamic performance of the device, although instability
does not occur unless the load exceeds 100 pF.
USING A HEAT SINK
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the
current to the load can be 10 times the quiescent current. This
creates a noticeable temperature rise. Use of a small heat sink
improves performance.
TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 32 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 V/μs, which means it can drive a ±10 V,
6.0 MHz signal, or a ±3 V, 19.9 MHz signal.
The termination resistor, RT, minimizes reflections from the far
end of the cable when equal to the characteristic impedance of
the cable. A back-termination resistor (RBT, also equal to the
characteristic impedance of the cable) can be placed between
the AD842 output and the cable to damp any stray signals
caused by a mismatch between RT and the characteristic
impedance of the cable. This configuration results in a cleaner
signal. With this circuit, the voltage on the line equals VIN
because one half of VOUT is dropped across RBT.
The AD842 has a 100 mA minimum output current and,
therefore, can drive ±5 V into a 50 Ω cable.
Choose the feedback resistors, R1 and R2, carefully. Large value
resistors are desirable to limit the amount of current drawn
from the amplifier output. Large resistors can cause amplifier
instability because the parallel resistance of R1||R2 combines
with the input capacitance (typically 2 pF to 5 pF) to create an
additional pole. The voltage noise of the AD842 is equivalent to
a 5 kΩ resistor; these large resistors can significantly increase
the system noise. Resistor values of 1 kΩ or 2 kΩ are
recommended.
If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.
Figure 32. Line Driver Configuration (PDIP)
09477-031
100%
90%
0%
10%
5mV 2µs
OUTPUT:
5V/DIV
OUTPUT
ERROR:
0.01%/DIV
2.2µF
0.1µF
50Ω OR 75Ω
CABLE
R
T
= R
BT
= CABLE
CHARACTE RI S TI C IMP E DANCE
2.2µF
0.1µF
R1
R2
–V
S
+V
S
V
IN
AD842
11
6
10
4
5
4
R
T
R
BT
TERMINATION
RESISTOR FOR
INPUT SIG NAL
09477-032
Rev. F | Page 10 of 16
Data Sheet AD842
OVERDRIVE RECOVERY
Figure 33 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.
Figure 33. Overdrive Recovery
Figure 34. Overdrive Recovery Test Circuit (PDIP)
09477-033
100%
90%
0%
10%
10V 1V 100ns
OVERDRIVEN
OUTPUT:
10V/DIV
INPUT SQUARE
WAVE:
1V/DIV
+V
S
–V
S
V
OUT
1kΩ
50Ω
2.2µF
0.1µF
2.2µF
0.1µF
PULSE
GENERATOR
1µs, ± 1V
SQUARE WAVE
INPUT
AD842
11
6
10
4
5
09477-034
Rev. F | Page 11 of 16
AD842 Data Sheet
OUTLINE DIMENSIONS
Figure 35. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions Shown in Inches and (Millimeters)
Figure 36. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions Shown in Inches and (Millimeters)
COMPLIANT TO JE DE C S TANDARDS MS - 001
CONTROLLING DIMENSIONSARE IN INCHES; MILLI MET ER DIMENSIONS
(IN PARENTHESES) ARE RO UNDE D- OF F INCH E QUIVALENTS FOR
REF ERE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIG URE D AS WHOL E OR HALF L E ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
0.150 ( 3.81)
0.130 ( 3.30)
0.110 (2.79)
0.070 ( 1.78)
0.050 ( 1.27)
0.045 ( 1.14)
14
17
8
0.100 ( 2.54)
BSC
0.775 ( 19.69)
0.750 ( 19.05)
0.735 ( 18.67)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 ( 0.38)
GAUGE
PLANE
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 ( 0.13)
MIN
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
PIN 1
17
8
14
Rev. F | Page 12 of 16
Data Sheet AD842
Figure 37. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions Shown in Inches and (Millimeters)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD842JNZ 0°C to 70°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD842JQ
0°C to 70°C
14-Lead Ceramic Dual In-Line Package [CERDIP]
Q-14
AD842KQ 0°C to 70°C 14-Lead Ceramic Dual In-Line Package [CERDIP] Q-14
AD842JR-16 0°C to 70°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD842JRZ-16 0°C to 70°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD842KNZ 0°C to 70°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD842SCHIPS Die
AD842SQ −55°C to +125°C 14-Lead Ceramic Dual In-Line Package [CERDIP] Q-14
1 Z = RoHS Compliant Part.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Rev. F | Page 13 of 16
AD842 Data Sheet
NOTES
Rev. F | Page 14 of 16
Data Sheet AD842
NOTES
Rev. F | Page 15 of 16
