NT1GD72S4PB0FU 1GB PC2700 and PC2100 Registered DDR DIMM 184 pin Registered DDR DIMM Based on DDR333/266 512M bit B Die device Features * 184 Dual In-Line Registered Memory Module (RDIMM) * Differential clock inputs * Registered DDR DIMM based on 110nm 512M bit die B device, * Data is read or written on both clock edges organized as 128Mx4 * DRAM DLL aligns DQ and DQS transitions with clock transitions * Address and control signals are fully synchronous to positive * Performance: clock edge PC2700 PC2100 Speed Sort 6K 75B - DIMM CAS Latency: 2.5, 2 DIMM CAS Latency 2.5 2.5 fCK Clock Frequency 166 133 MHz tCK Clock Cycle 6 7.5 ns 333 266 MHz fDQ DQ Burst Frequency * Programmable Operation: Unit - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Intended for 133 and 166 MHz applications * Auto Refresh (CBR) and Self Refresh Modes * Inputs and outputs are SSTL-2 compatible * Automatic and controlled precharge commands * Error Check Correction (ECC) support * 7.8 s Max. Average Periodic Refresh Interval * Phase lock loop (PLL) clock driver to reducing clock loading * Serial Presence Detect EEPROM * Registered inputs with one clock delay * Gold contacts on modules * VDD = VDDQ = 2.5V 0.2V * SDRAMs are packaged in BGA packages * SDRAMs have 4 internal banks for concurrent operation Description NT1GD72S4PB0FU are registered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM) with ECC organized as a single rank using eighteen 128Mx4 BGA devices. Depending on the speed grade, these DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC. REV 1.0 Nov 9, 2004 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Ordering Information Part Number Organization NT1GD72S4PB0FU-6K 128Mx72 Speed Power Leads 166MHz (6ns @ CL = 2.5) 2.5V Gold 133MHz (7.5ns @ CL = 2.5) 2.5V Gold PC2700 DDR333 2.5-3-3 NT1GD72S4PB0FU -75B PC2100 128Mx72 DDR266 2.5-3-3 Note: The registered inputs will add 1 initial clock delay to all modules For the closest sales office or information, please visit: www.nanya.com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 REV 1.0 Nov 9, 2004 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Pin Description CK0, CK1, CK2, Differential Clock Inputs. DQ0-DQ63 Data input/output CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes RAS Row Address Strobe DM0-DM7 Input Data Mask CAS Column Address Strobe VDD Power WE Write Enable VDDQ Supply voltage for DQs CK0, CK1, CK2 S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 93 VSS 32 A5 124 VSS 62 VDDQ 154 RAS 2 DQ0 94 DQ4 33 DQ24 125 A6 63 WE 155 DQ45 3 VSS 95 DQ5 34 VSS 126 DQ28 64 DQ41 156 VDDQ 4 DQ1 96 VDDQ 35 DQ25 127 DQ29 65 CAS 157 S0 5 DQS0 97 DM0/DQS9 36 DQS3 128 VDDQ 66 VSS 158 S1 6 DQ2 98 DQ6 37 A4 129 DM3/DQS12 67 DQS5 159 DM5/DQS14 7 VDD 99 DQ7 38 VDD 130 A3 68 DQ42 160 VSS 8 DQ3 100 VSS 39 DQ26 131 DQ30 69 DQ43 161 DQ46 9 NC 101 NC 40 DQ27 132 VSS 70 VDD 162 DQ47 10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC 11 VSS 103 NC 42 VSS 134 NC 72 DQ48 164 VDDQ 12 DQ8 104 VDDQ 43 A1 135 NC 73 DQ49 165 DQ52 13 DQ9 105 DQ12 44 NC 136 VDDQ 74 VSS 166 DQ53 14 DQS1 106 DQ13 45 NC 137 CK0 75 CK2 167 NC 15 VDDQ 107 DM1/DQS10 46 VDD 138 CK0 76 CK2 168 VDD 16 CK1 108 VDD 47 NC 139 VSS 77 VDDQ 169 DM6/DQS15 17 CK1 109 DQ14 48 A0 140 NC 78 DQS6 170 DQ54 18 VSS 110 DQ15 49 NC 141 A10 79 DQ50 171 DQ55 19 DQ10 111 CKE1 50 VSS 142 NC 80 DQ51 172 VDDQ 20 DQ11 112 VDDQ 51 NC 143 VDDQ 81 VSS 173 NC 52 BA1 144 NC 21 CKE0 113 NC 22 VDDQ 114 DQ20 23 DQ16 115 A12 53 DQ32 145 24 DQ17 116 VSS 54 VDDQ 146 KEY 82 VDDID 174 DQ60 83 DQ56 175 DQ61 VSS 84 DQ57 176 VSS DQ36 85 VDD 177 DM7/DQS16 KEY 25 DQS2 117 DQ21 55 DQ33 147 DQ37 86 DQS7 178 DQ62 26 VSS 118 A11 56 DQS4 148 VDD 87 DQ58 179 DQ63 27 A9 119 DM2/DQS11 57 DQ34 149 DM4/DQS13 88 DQ59 180 VDDQ 28 DQ18 120 VDD 58 VSS 150 DQ38 89 VSS 181 SA0 29 A7 121 DQ22 59 BA0 151 DQ39 90 WP 182 SA1 30 VDDQ 122 A8 60 DQ35 152 VSS 91 SDA 183 SA2 31 DQ19 123 DQ23 61 DQ40 153 DQ44 92 SCL 184 VDDSPD Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 Nov 9, 2004 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Input/Output Functional Description Symbol Type CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 (SSTL) (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands are RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to VREF Supply VDDQ Supply BA0, BA1 (SSTL) S0, S1 ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to A0 - A9 A10/AP A11, A12 (SSTL) - invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - Data and Check Bit input/output pins operate in the same manner as on conventional DQS0 - DQS7, DQS9 - DQS16 (SSTL) Active High Data strobes: Output with read data, input with write data. Edge aligned with read data, CB0 - CB7 (SSTL) - DM0 - DM8 Input Active High VDD, VSS Supply DRAMs. centered on write data. Used to capture write data. Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial SA0 - SA2 - SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be VDDSPD Supply Presence Detect EEPROM address. must be connected from the SDA bus line to V DD to act as a pull-up. connected from the SCL bus time to V DD to act as a pull-up. Serial EEPROM positive power supply. ! ! REV 1.0 Nov 9, 2004 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Functional Block Diagram 1 Rank, 18 devices, 128Mx4 DDR SDRAMs V SS RS0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB 0 CB 1 CB 2 CB 3 S0 BA0BA1 A0-A12 RAS CAS CKE 0 WE PCK Notes : REV 1.0 Nov 9, 2004 DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS R E G I S T E R PC K D M DQ4 DQ5 DQ6 DQ7 D0 DM1/DQS10 D M DQ12 DQ13 DQ14 DQ15 D1 DM2/DQS11 D M DQ20 DQ21 DQ22 DQ23 D2 DM3/DQS12 D M DQ28 DQ29 DQ30 DQ31 D3 DM4/DQS13 D M DQ36 DQ37 DQ38 DQ39 D4 DM5/DQS14 D M DQ44 DQ45 DQ46 DQ47 D5 DM6/DQS15 D M DQ52 DQ53 DQ54 DQ55 D6 DM7/DQS16 D M DQ60 DQ61 DQ62 DQ63 D7 DM8/DQS17 D M CB 4 CB 5 CB 6 CB 7 D8 RS0 RBA0RBA1 RA0-RA12 RRAS RCAS RCKE0 RWE DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S I/O 0 I/O 1 I/O 2 I/O 3 CS VDDSPD VDDQ VD D VREF VSS VDDID CS : SDRAMs D0-D17 BA0-BA1 : SDRAMs D0-D17 A0-A12 : SDRAMs D0-D17 RAS : SDRAMs D0-D17 CAS : SDRAMs D0-D17 CKE : SDRAMs D0-D17 WE : SDRAMs D0-D17 D M D10 D M D11 D M D12 D M D13 D M D14 D M D15 D M D16 D M D17 Serial PD WP 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/CS relationships are maintained as shown. 3. DQ/DQS resistors are 22 Ohms. 4. VDDID strap connections (for memory device VDD,VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ 5. Address and control resistors are 22 Ohms. D9 Serial PD D0-D17 D0-D17 D0-D17 D0-D17 Strap : see Note 4 SC L RESET D M A 0 SA 0 A 1 SA 1 A 2 SA 2 SD A CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Serial Presence Detect SPD Description Byte 0 Description Number of Serial PD Bytes Written during Production Byte 27 Description Minimum Row Precharge Time (tRP) 1 Total Number of Bytes in Serial PD device 28 Minimum Row Active to Row Active delay (tRRD) 2 Fundamental Memory Type 29 Minimum RAS to CAS delay (tRCD) 3 Number of Row Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS) 4 Number of Column Addresses on Assembly 31 Module Bank Density 5 Number of DIMM Rank 32 Address and Command Setup Time Before Clock 6 Data Width of Assembly 33 Address and Command Hold Time After Clock 7 Data Width of Assembly (cont') 34 Data Input Setup Time Before Clock 8 Voltage Interface Level of this Assembly 35 Data Input Hold Time After Clock 9 10 DDR SDRAM Device Cycle Time 36-40 CL=2.5 DDR SDRAM Device Access Time from Clock 41 CL=2.5 Reserved Minimum Active/Auto-refresh Time (tRC) Auto-refresh to Active/Auto-refresh Command Period 11 DIMM Configuration Type 42 12 Refresh Rate/Type 43 Max Cycle Time (tCK max) 13 Primary DDR SDRAM Width 44 Maximum DQS-DQ Skew Time (tDQSQ) Error Checking DDR SDRAM Device Width 45 Maximum Read Data Hold Skew Factor (tQHS) 46 Reserved 47 DIMM Height 14 15 16 17 18 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device 48-61 Banks DDR SDRAM Device Attributes: CAS Latencies Supported (tRFC) Reserved 62 SPD Revision Checksum Data 19 DDR SDRAM Device Attributes: CS Latency 63 20 DDR SDRAM Device Attributes: WE Latency 64-71 Manufacturer's JEDEC ID Code 21 DDR SDRAM Device Attributes: 72 Module Manufacturing Location 22 23 DDR SDRAM Device Attributes: General Minimum Clock Cycle CL=2.5 73-90 Module Part number 91-92 Module Revision Code Module Manufacturing Data 24 yy= Binary coded decimal year code, 0-99(Decimal), Maximum Data Access Time from Clock at 93-94 CL=2 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) 25 Minimum Clock Cycle Time at CL=1 95-98 Module Serial Number 26 Maximum Data Access Time from Clock at CL=1 99-127 Reserved REV 1.0 Nov 9, 2004 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM SPD Values for NT1GD72S4PB0FU PC2700 (6K) PC2100 (75B) Byte Value Hex Value Hex 0 128 80 128 80 1 256 08 256 08 2 SDRAM DDR 07 SDRAM DDR 07 3 13 0D 13 0D 4 12 0C 12 0C 5 01 01 01 01 6 x72 48 x72 48 7 x72 00 x72 00 8 SSTL 2.5V 04 SSTL 2.5V 04 9 6.0ns 60 7.5ns 75 10 7.0ns 70 7.5ns 75 11 Parity 02 Parity 02 12 SR/1x(7.8us) 82 SR/1x(7.8us) 82 13 x4 04 x4 04 14 x4 04 x4 04 15 1 Clock 01 1 Clock 01 16 2,4,8 0E 2,4,8 0E 17 4 04 4 04 18 2/2.5 0C 2/2.5 0C 19 0 01 0 01 20 1 02 1 02 21 Register 26 Register 26 22 0.2V Tolerance C0 0.2V Tolerance C0 23 7.5ns 75 10ns A0 24 0.75ns 75 0.75ns 75 25 N/A 00 N/A 00 26 N/A 00 N/A 00 27 18ns 48 20ns 50 28 12ns 30 15ns 3C 29 18ns 48 20ns 50 30 42ns 2A 45ns 2D 31 1GB 01 1GB 01 32 0.75ns 75 0.90ns 90 33 0.75ns 75 0.90ns 90 34 0.45ns 45 0.50ns 50 35 0.45ns 45 0.50ns 50 36-40 Reserved 00 Reserved 00 41 60ns 3C 65ns 41 42 72ns 48 75ns 4B 43 12ns 30 12ns 30 44 0.40ns 28 0.50ns 32 45 0.50ns 50 0.75ns 75 46 Reserved 00 Reserved 00 47 28.57mm 01 28.57 01 48-61 Reserved 00 Reserved 00 62 SPD 1.0 10 SPD 1.0 10 63 Checksum DF Checksum C6 64-71 NANYA 7F7F7F0B NANYA 00000000 7F7F7F0B 00000000 72 Assembly -- Assembly -- 73-90 Module PN -- Module PN -- 91-92 Revision -- Revision -- 93-94 Year/Week Code -- Year/Week Code -- 95-98 Serial Number -- Serial Number -- 99-127 Reserved -- Reserved -- REV 1.0 Nov 9, 2004 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to VSS Rating Units -0.5 to VDDQ +0.5 V VIN Voltage on Input relative to VSS -0.5 to +3.6 V VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 C -55 to +150 C TA TSTG Operating Temperature (Ambient) Storage Temperature (Plastic) PD Power Dissipation (per device component) 1 W IOUT Short Circuit Output Current 50 mA Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics and Operating Conditions TA= 0C ~ 70C; VDDQ= VDD= 2.5V0.2V(PC2100,PC2700) Symbol VDD VDDQ VSS, VSSQ VREF VTT 3. 4. Min Max Units Notes Supply Voltage 2.3 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 Supply Voltage, I/O Supply Voltage I/O Reference Voltage 0 0 V 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6 V 1, 4 Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) -5 5 uA 1 IOZ Output Leakage Current (DQs are disabled; 0V Vout VDDQ -5 5 uA 1 IOH Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) -16.8 - mA 1 IOL Output Low Current (VOUT = 0.373, max VREF, max VTT) 16.8 - mA 1 II 1. 2. Parameter Inputs are not recognized as valid until VREF stabilizes. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.0 Nov 9, 2004 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) Symbol Parameter/Condition VIH (AC) Input High (Logic 1) Voltage. Min Max VREF + 0.31 VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 1.0 Nov 9, 2004 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W Parameter/Condition clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Notes Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3 1,2 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. All IDD current values are calculated from device level and does not include any non memory devices. NT1GD72S4PB0FU Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 PC2700 PC2100 (6K) (75B) 1721 1787 60 445 207 812 1868 2097 3465 40 5530 REV 1.0 Nov 9, 2004 TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Package Dimensions ECC, 18 BGA devices Note: For all drawings, devices are drawn as a reference only REV 1.0 Nov 9, 2004 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD72S4PB0FU 1GB Registered DDR DIMM Revision Log Rev Date 0.1 Jun 11, 2004 1.0 Nov 9, 2004 Modification Release initial Update part numbers Update SPD & IDD 333 values Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must be validated for each customer application by the customer's technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation. Printed in Taiwan (c)2004 REV 1.0 Nov 9, 2004 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.