09005aef80818a4a
512mbSDRAMfront.fm - Rev. G 1/04 EN 1©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
MT48LC128M4A2 – 32 MEG x 4 x 4 BANKS
MT48LC64M8A2 – 16 MEG x 8 x 4 BANKS
MT48LC32M16A2 – 8 MEG x 16 x 4 BANKS
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Part Number Example:
MT48LC32M16A2TG-75
NOTE: 1. Refer to Micron Technical Note TN-48-05.
2. Off-center parting line.
3. Contact factory for availability.
NOTE: The # symbol indicates signal is active LOW. A
dash (-) indicates x8 and x4 pin function is
same as x16 pin function.
OPTIONS MARKING
•Configurations
128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8
32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
•WRITE Recovery (
tWR)
tWR = “2 CLK”1A2
• Plastic Package - OCPL2
54-pin TSOP II (400 mil) TG
54-pin TSOP II (400 mil) Lead-Free P
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133) -7E
7.5ns @ CL = 3 (PC133) -75
• Self Refresh
Standard None
Low-power L
•Operating Temperature
Commercial (0oC to +70oC) None
Industrial Temperature
(40oC +85oC)
IT3
Configuration 32 Meg x 4 x 4
banks
16 Meg x 8 x
4 banks
8 Meg x 16 x 4
banks
Refresh Count 8K 8K 8K
Row Addressing 8K (A0-A12) 8K (A0-A12) 8K (A0-A12)
Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Column
Addressing
4K (A0-A9,
A11, A12)
2K (A0-A9,
A11)
1K (A0-A9)
Key Timing Parameters
SPEED
GRADE
CLOCK
FREQUENCY
ACCESS TIME
SETUP
TIME
HOLD
TIME
CL = 2* CL = 3*
-7E 143 MHz – 5.4ns 1.5ns 0.8ns
-75 133 MHz – 5.4ns 1.5ns 0.8ns
-7E 133 MHz 5.4ns - 1.5ns 0.8ns
-75 100 MHz 6ns - 1.5ns 0.8ns
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VssQ
DQ10
DQ9
VDDQ
DQ8
Vss
NC
DQMH
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
x8x16 x16x8 x4x4
-
DQ0
-
NC
DQ1
-
NC
DQ2
-
NC
DQ3
-
NC
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
NC
DQ0
-
NC
NC
-
NC
DQ1
-
NC
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
Figure 1: Pin Assignment (Top View)
54-Pin TSOP
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAMfront.fm - Rev. G 1/04 EN 2©2000 Micron Technology, Inc. All rights reserved.
General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912-bits.
It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x4’s
134,217,728-bit banks is organized as 8,192 rows by
4,096 columns by 4-bits. Each of the x8’s 134,217,728-
bit banks is organized as 8,192 rows by 2,048 columns
by 8-bits. Each of the x16’s 134,217,728-bit banks is
organized as 8,192 rows by 1,024 columns by 16-bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A12 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The 512Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 512Mb SDRAM is designed to operate at 3.3V.
An auto refresh mode is provided, along with a power-
saving, power-down mode. All inputs and outputs are
LVTTL-compatib le.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and the
capability to randomly change column addresses on
each clock cycle during a burst access.
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAMTOC.fm - Rev. G 1/04 EN 3©2000 Micron Technology, Inc. All rights reserved.
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
POWER-DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAMLOF.fm - Rev. G 1/04 EN 4©2000 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2: Functional Block Diagram 128 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3: Functional Block Diagram 64 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4: Functional Block Diagram 32 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7: Activating a Specific Row In a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 8: Example Meeting RCD (MIN) When 2 < RCD (MIN)/CK 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9: Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 10: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 13: READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 14: READ to WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 15: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 16: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 17: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 18: WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 19: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 20: WRITE To READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 21: WRITE To PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 22: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 23: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 24: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 25: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 26: Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 27: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 28: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 29: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 31: Initialize And Load Mode Register2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 32: Power-down Mode1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 33: Clock Suspend Mode1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 34: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 35: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 36: READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 37: READ – With Auto Precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 38: Single READ – Without Auto Precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 39: Single READ – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 40: Alternating Bank Read Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 41: Read – Full-page Burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 42: Read DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 43: Write – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 44: Write – With Auto Precharge1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 45: Single Write – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 46: Single Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 47: Alternating Bank Write Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 48: Write – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 49: Write – DQM Operation1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 50: 54-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
512Mb: x4, x8, x16
SDRAM
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List of Tables
Table 1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 3: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 4: Truth Table 1 – Commands And DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 5: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 6: Truth Table 3 – Current State Bank n - Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 7: Truth Table 4 - Current State Bank n - Command To Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 8: DC Electrical Characteristics And Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 9: IDD Specifications And Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 10: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 11: Electrical Characteristics And Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .35
Table 12: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
512Mb: x4, x8, x16
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Figure 2: Functional Block Diagram 128 Meg x 4 SDRAM
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
12
COMMAND
DECODE
A0-A12,
BA0, BA1
DQM
13
ADDRESS
REGISTER
15
4096
(x4)
16384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 4,096 x 4)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ3
4
4
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
4
12
BANK1
BANK2
BANK3
13
12
2
1 1
2
REFRESH
COUNTER
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Figure 3: Functional Block Diagram 64 Meg x 8 SDRAM
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
11
COMMAND
DECODE
A0-A12,
BA0, BA1
DQM
13
ADDRESS
REGISTER
15
2048
(x8)
16384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ7
8
8
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
8
12
BANK1
BANK2
BANK3
13
11
2
1 1
2
REFRESH
COUNTER
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SDRAM
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Figure 4: Functional Block Diagram 32 Meg x 16 SDRAM
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
10
COMMAND
DECODE
A0-A12,
BA0, BA1
DQML,
DQMH
13
ADDRESS
REGISTER
15
1024
(x16)
16384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ15
16
16
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
16
12
BANK1
BANK2
BANK3
13
10
2
2 2
2
REFRESH
COUNTER
512Mb: x4, x8, x16
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Table 1: Pin Descriptions
PIN
NUMBERS SYMBOL TYPE DESCRIPTION
38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls
the output registers.
37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK
SUSPEND operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
18, 17, 16 RAS#,
CAS#, WE#
Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
39 x4, x8:
DQM
Input Input/Output Mask: DQM is an input mask signal for write accesses and an output
enable signal for read accesses. Input data is masked when DQM is sampled HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML
(Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and
DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state
when referenced as DQM.
15, 39 x16:
DQML,
DQMH
20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE,
or PRECHARGE command is being applied.
23-26, 29-
34, 22, 35,
36
A0-A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-
A12) and READ/WRITE command (column-address A0-A9, A11, A12 [x4]; A0-A9, A11
[x8]; A0-A9 [x16]; with A10 defining auto precharge) to select one location out of
the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 [HIGH]) or bank
selected by (A10 [LOW]). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
2, 4, 5, 7,
8, 10, 11,
13, 42, 44,
45, 47, 48,
50, 51, 53
DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are NCs for
x8; and 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4).
2, 5, 8, 11,
44, 47, 50,
53
DQ0-DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4).
5, 11, 44,
50
DQ0-DQ3 x4: I/O Data Input/Output: Data bus for x4.
40 NC - No Connect: This pin should be left unconnected.
3, 9, 43, 49 VDDQ Supply DQ Power: Isolated DQ power to the die for improved noise immunity.
6, 12, 46,
52
VSSQ Supply DQ Ground: Isolated DQ ground to the die for improved noise immunity.
1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V.
28, 41, 54 VSS Supply Ground.
512Mb: x4, x8, x16
SDRAM
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Functional Description
In general, the 512Mb SDRAMs (32 Meg x 4 x 4
banks, 16 Meg x 8 x 4 banks, and 8 Meg x 16 x 4 banks)
are quad-bank DRAMs that operate at 3.3V and
include a synchronous interface (all signals are regis-
tered on the positive edge of the clock signal, CLK).
Each of the x4’s 134,217,728-bit banks is organized as
8,192 rows by 4,096 columns by 4-bits. Each of the x8’s
134,217,728-bit banks is organized as 8,192 rows by
2,048 columns by 8-bits. Each of the x16’s 134,217,728-
bit banks is organized as 8,192 rows by 1,024 columns
by 16-bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0-A12 select the row).
The address bits (x4: A0-A9, A11, A12; x8: A0-A9, A11;
x16: A0-A9) registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, command descriptions and device opera-
tion.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to VDD and VDDQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Register Definition
Mode Register
The Mode Register is used to define the specific
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 1. The Mode Register is pro-
grammed via the LOAD MODE REGISTER command
and will retain the stored information until it is pro-
grammed again or the device loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be
driven LOW during loading of the Mode Register.
The Mode Register must be loaded when all banks
are idle, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both
the sequential and the interleaved burst types, and a
full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A9, A11, A12 (x4); A1-A9, A11 (x8); or A1-
A9 (x16) when the burst length is set to two; by A2-A9,
A11, A12 (x4); A2-A9, A11 (x8) or A2-A9 (x16) when the
512Mb: x4, x8, x16
SDRAM
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burst length is set to four; and by A3-A9, A11, A12 (x4);
A3-A9, A11 (x8) or A3-A9 (x16) when the burst length is
set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the
boundary is reached.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 2.
Figure 5: Mode Register Definition
NOTE: 1. For full-page accesses: y = 4,096 (x4); y = 2,048 (x8);
y = 1,024 (x16).
2. For a burst length of two, A1-A9, A11, A12 (x4); A1-A9,
A11 (x8); or A1-A9 (x16) select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11, A12 (x4); A2-A9,
A11 (x8); or A2-A9 (x16) select the block-of-four burst;
A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11, A12 (x4); A3-A9,
A11 (x8); or A3-A9 (x16) select the block-of-eight burst;
A0-A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A9,
A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) select the
starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A9, A11, A12 (x4); A0-A9,
A11 (x8); or A0-A9 (x16) select the unique column to be
accessed, and Mode Register bit M3 is ignored.
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst LengthCAS Latency BT
A9 A7 A6 A5 A4 A3
A8 A2 A1 A0
Mode Register (Mx)
Address Bus
976543
8210
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Op Mode
A10
A11
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
A12
12
Table 2: Burst Definition
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN A BURST
TYPE =
SEQUENTIAL TYPE = INTERLEAVED
2A0
00-1 0-1
11-0 1-0
4A1A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8A2A1A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
Page
(y)
n = A0-
A12/11/9
(location
0-y)
Cn, Cn + 1,
Cn + 2
Cn + 3,
Cn + 4…
…Cn - 1,
Cn…
Not Supported
512Mb: x4, x8, x16
SDRAM
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512mbSDRAM.fm - Rev. G 1/04 EN 12 ©2000 Micron Technology, Inc. All rights reserved.
CAS Latency
The CAS latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 6: CAS Latency
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
CLK
DQ
T2T1 T3T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2T1 T3T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
NOP
Table 3: CAS Latency
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
LATENCY = 2
CAS
LATENCY = 3
-7E ≤ 133 ≤ 143
-75 ≤ 100 ≤ 133
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Commands
Table 4: Truth Table 1 provides a quick reference of
available commands. This is followed by a written
description of each command. Three additional Truth
Tables appear following the Operation section; these
tables provide current state/next state information.
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 4: Truth Table 1 – Commands And DQM Operation
NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQS NOTES
COMMAND INHIBIT (NOP) HXXXX X X
NO OPERATION (NOP) LHHHX X X
ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3
READ (Select bank and column, and start READ burst) LHLH
L/H8Bank/Col X 4
WRITE (Select bank and column, and start WRITE
burst)
LHLL
L/H8Bank/Col Valid 4
BURST TERMINATE LHHLX X Active
PRECHARGE (Deactivate row in bank or banks) LLHLXCode X 5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LLLHX X X 6, 7
LOAD MODE REGISTER LLLLXOp-CodeX 4
Write Enable/Output Enable −−−−L−Active 8
Write Inhibit/Output High-Z −−−−H−High-Z 8
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COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM,
regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A11 (A12
should be driven LOW.) See Mode Register heading in
the Register Definition section. The LOAD MODE
REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRE-
CHARGE command must be issued before opening a
different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9
(x16) selects the starting column location. The value
on input A10 determines whether or not auto pre-
charge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the
DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was regis-
tered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst
write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-
A9 (x16) selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coinci-
dent with the data. If a given DQM signal is registered
LOW, the corresponding data will be written to mem-
ory; if the DQM signal is registered HIGH, the corre-
sponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the
same individual-bank PRECHARGE function
described above, without requiring an explicit com-
mand. This is accomplished by using A10 to enable
auto precharge in conjunction with a specific READ or
WRITE command. A PRECHARGE of the bank/row
that is addressed with the READ or WRITE command is
automatically performed upon completion of the
READ or WRITE burst, except in the full-page burst
mode, where auto precharge does not apply. Auto pre-
charge is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE com-
mand.
Auto precharge ensures that the precharge is initi-
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command
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was issued at the earliest possible time, as described
for each burst type in the Operation section of this
data sheet.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required. All active banks must be PRE-
CHARGED prior to issuing a AUTO REFRESH comand.
The AUTO REFRESH command should not be issued
until the minimum tRP has been met after the PRE-
CHARGE command as shown in the operations sec-
tion.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 512Mb
SDRAM requires 8,192 AUTO REFRESH cycles every
64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 7.81µs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (tRC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care” with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform
its own AUTO REFRESH cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to tRAS and may remain in self refresh mode for
an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (sta-
ble clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for tXSR because time is required for the com-
pletion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 7.81µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
Operation
Bank/Row Activation
Before any READ or WRITE commands can be
issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a tRCD
specification of 20ns with a 125 MHz clock (8ns
period) results in 2.5 clocks, rounded to 3. This is
reflected in Figure 4, which covers any case where 2 <
tRCD (MIN)/tCK - 3. (The same procedure is used to
convert other specification limits from time units to
clock cycles.) A subsequent ACTIVE command to a dif-
ferent row in the same bank can only be issued after
the previous active row has been “closed” (pre-
charged). The minimum time interval between succes-
sive ACTIVE commands to the same bank is defined by
tRC.
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Figure 7: Activating a Specific Row In a
Specific Bank
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
Figure 8: Example Meeting RCD (MIN)
When 2 < RCD (MIN)/CK 3
CS#
WE#
CAS#
RAS#
CKE
CLK
A0-A12
ROW
ADDRESS
DON’T CARE
HIGH
BA0, BA1
BANK
ADDRESS
CLK
T2T1 T3T0
t
C
OMMAND NOPACTIVE READ or
WRITE
T4
NOP
RCD
DON’T CARE
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READs
READ bursts are initiated with a READ command, as
shown in Figure 9.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the generic
READ commands used in the following illustrations,
auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 10 shows general tim-
ing for each possible CAS latency setting.
Figure 9: Read Command
Figure 10: CAS Latency
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go High-
Z. A full-page burst will continue until terminated. (At
the end of the page, it will wrap to the start address and
continue.) Data from any READ burst may be trun-
cated with a subsequent READ command, and data
from a fixed-length READ burst may be immediately
followed by data from a READ command. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst or the last desired
data element of a longer burst that is being truncated.
The new READ command should be issued x cycles
before the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for CAS latencies of two
and three; data element n + 3 is either the last of a
burst of four or the last desired of a longer burst. The
512Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initi-
ated on any clock cycle following a previous READ
command. Full-speed random read accesses can be
performed to the same bank, as shown in Figure 12, or
each subsequent READ may be performed to a differ-
ent bank.
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A9, A11, A12: x4
A0-A9, A11: x8
A0-A9: x16
A10
BA0,1
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A12: x8
A11, A12: x16
CLK
DQ
T2T1 T3T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2T1 T3T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
NOP
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Figure 11: Consecutive READ Bursts
DON’T CARE
NOTE: Each READ command may be to any bank. DQM is LOW.
CLK
DQ
DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ NOP
T7
X = 2 cycles
CAS Latency = 3
TRANSITIONING DATA
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Figure 12: Random READ Accesses
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, pro-
vided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a single-
cycle delay should occur between the last read data
and the WRITE command.
The DQM input is used to avoid I/O contention, as
shown in Figure 13 and Figure 14 on page 20. The
DQM signal must be asserted (HIGH) at least two
clocks prior to the WRITE command (DQM latency is
two clocks for output buffers) to suppress data-out
from the READ. Once the WRITE command is regis-
tered, the DQs will go High-Z (or remain High-Z),
regardless of the state of the DQM signal; provided the
DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not,
the second WRITE will be an invalid WRITE. For exam-
ple, if DQM was LOW during T4 in Figure 14 on
page 20, then the WRITEs at T5 and T7 would be valid,
while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for
input buffers) to ensure that the written data is not
masked. Figure 13 shows the case where the clock fre-
quency allows for bus contention to be avoided with-
out adding a NOP cycle, and Figure 14 shows the case
where the additional NOP is needed.
CLK
DQ
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP
BANK,
COL n
DON’T CARE
DOUT
n
DOUT
a
DOUT
x
DOUT
m
READ
NOTE: Each READ command may be to any bank. DQM is LOW.
READ READ NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ DOUT
n
T2T1 T4T3 T5T0
COMMAND
ADDRESS
READ NOP
BANK,
COL n
DOUT
a
DOUT
x
DOUT
m
READ READ READ NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CAS Latency = 2
CAS Latency = 3
TRANSITIONING DATA
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Figure 13: READ to WRITE Figure 14: READ to WRITE with Extra
Clock Cycle
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a PRE-
CHARGE command to the same bank. The PRE-
CHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Figure 11 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or
the last desired of a longer burst. Following the PRE-
CHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that
part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 12 for each possible CAS latency; data element
n + 3 is the last desired data element of a longer burst.
DON’T CARE
READ NOP NOP WRITE
NOP
CLK
T2T1 T4T3T0
DQM
DQ DOUT n
COMMAND
DIN b
ADDRESS BANK,
COL n
BANK,
COL b
DS
t
HZ
t
t
CK
NOTE: A CAS latency of three is used for illustration. The
READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
TRANSITIONING DATA
DON’T CARE
READ NOP NOPNOP NOP
DQM
CLK
DQ
D
OUT
n
T2T1 T4T3T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
D
IN
b
BANK,
COL b
T5
DS
t
HZ
t
NOTE: A CAS latency of three is used for illustration. The
READ command
may be to any bank, and the WRITE command may be to any bank.
TRANSITIONING DATA
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Figure 15: Terminating a READ Burst
CLK
DQ DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE NOP
T7
DON’T CARE
NOTE: DQM is LOW.
CLK
DQ DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE NOP
X = 1 cycle
CAS Latency = 2
CAS Latency = 3
X = 2 cycles
TRANSITIONING DATA
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WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13 Write command.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the generic
WRITE commands used in the following illustrations,
auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure 14
Write Burst. A full-page burst will continue until termi-
nated. (At the end of the page, it will wrap to the start
address and continue.) Data for any WRITE burst may
be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immedi-
ately followed by data for a WRITE command. The new
WRITE command can be issued on any clock following
the previous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 15 (Write to
Write). Data n + 1 is either the last of a burst of two or
the last desired of a longer burst. The 512Mb SDRAM
uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architec-
ture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-
speed random write accesses within a page can be per-
formed to the same bank, as shown in Figure 16, or
each subsequent WRITE may be performed to a differ-
ent bank.
Figure 16: WRITE Command Figure 17: WRITE Burst
Figure 18: WRITE to WRITE
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A10
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A0-A9, A11, A12: x4
A0-A9, A11: x8
A0-A9: x16
A12: x8
A11, A12: x16
BA0, BA, 1
BANK
ADDRESS
CLK
DQ DIN
n
T2T1 T3T0
COMMAND
ADDRESS
NOP NOP
DON’T CARE
WRITE
DIN
n + 1
NOP
BANK,
COL n
NOTE: Burst length = 2. DQM is LOW.
TRANSITIONING DATA
CLK
DQ
T2T1T0
COMMAND
ADDRESS
NOPWRITE WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN
n + 1
DIN
b
NOTE: DQM is LOW. Each WRITE command may
be to any bank.
DON’T CARE
TRANSITIONING DATA
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Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 20.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regard-
less of frequency. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock
edge coincident with, the PRECHARGE command. An
example is shown in Figure 18. Data n + 1 is either the
last of a burst of two or the last desired of a longer
burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued
until tRP is met. The precharge can be issued coinci-
dent with the first coincident clock edge (T2 in
Figure 21) on an A1 Version and with the second clock
on an A2 Version (Figure 21.) In the case of a fixed-
length burst being executed to completion, a PRE-
CHARGE command issued at the optimum time (as
described above) provides the same operation that
would result from the same fixed-length burst with
auto precharge. The disadvantage of the PRECHARGE
command is that it requires that the command and
address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-
length or full-page bursts.
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
Figure 19: Random WRITE Cycles
Figure 20: WRITE To READ
Figure 21: WRITE To PRECHARGE
DON’T CARE
CLK
DQ
D
IN
n
T2T1 T3T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
D
IN
a
D
IN
x
D
IN
m
WRITE WRITE WRITE
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOTE: Each WRITE command may be to any bank. DQM is LOW.
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2T1 T3T0
COMMAND
ADDRESS
NOPWRITE
BANK,
COL n
DIN
n
DIN
n + 1
DOUT
b
READ NOP NOP
BANK,
COL b
NOP
DOUT
b + 1
T4 T5
NOTE: The WRITE command may be to any bank, and the READ command
may be to any bank. DQM is LOW. CAS latency = 2 for illustration.
TRANSITIONING DATA
DON’T CARE
DQM
CLK
DQ
T2T1 T4T3T0
COMMAND
ADDRESS
BANK a,
COL n
T5
NOPWRITE PRECHARGE NOPNOP
D
IN
n
D
IN
n + 1
ACTIVE
tRP
BANK
(a or all)
tWR
BANK a,
ROW
DQM
DQ
COMMAND
ADDRESS
BANK a,
COL n
NOPWRITE PRECHARGE NOPNOP
D
IN
n
D
IN
n + 1
ACTIVE
tRP
BANK
(a or all)
tWR
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
BANK a,
ROW
T6
NOP
NOP
tWR @ tCLK ≥ 15ns
tWR = tCLK < 15ns
TRANSITIONING DATA
512Mb: x4, x8, x16
SDRAM
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Figure 22: Terminating a WRITE Burst
PRECHARGE
The PRECHARGE command (see Figure 20) is used
to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP)
after the precharge command is issued. Input A10
determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
POWER-DOWN
Power-down occurs if CKE is registered low coinci-
dent with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maxi-
mum power savings while in standby. The device may
not remain in the power-down state longer than the
refresh period (64ms) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS). (See Figure 21.)
Figure 23: PRECHARGE Command
Figure 24: Power-Down
DON’T CARE
CLK
DQ
T2T1T0
COMMAND
ADDRESS
BANK,
COL n
WRITE BURST
TERMINATE
NEXT
COMMAND
D
IN
n
(ADDRESS)
(DATA)
NOTE: DQMs are LOW.
TRANSITIONING DATA
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
HIGH
All Banks
Bank Selected
A0-A9, A11, A12
BA0, BA1 BANK
ADDRESS
DON’T CARE
tRAS
tRCD
tRC
All banks idle
Input buffers gated off
Exit power-down mode.
(
)(
)
(
)(
)
(
)(
)
tCKS > t
CKS
COMMAND
NOP ACTIVE
Enter power-down mode.
NOP
CLK
CKE
(
)(
)
(
)(
)
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CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered LOW.
In the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sam-
pled LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Fig-
ures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one), regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
Figure 25: Clock Suspend During WRITE
Burst
Figure 26: Clock Suspend During READ
Burst
DON’T CARE
D
IN
COMMAND
ADDRESS
WRITE
BANK,
COL n
D
IN
n
NOPNOP
CLK
T2T1 T4T3 T5T0
CKE
INTERNAL
CLOCK
NOP
D
IN
n + 1
D
IN
n + 2
NOTE: For this example, burst length = 4 or greater, and DM
is LOW.
TRANSITIONING DATA
DON’T CARE
CLK
DQ
D
OUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP
BANK,
COL n
NOP
D
OUT
n + 1
D
OUT
n + 2
D
OUT
n + 3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
CKE
INTERNAL
CLOCK
NOP
TRANSITIONING DATA
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CONCURRENT AUTO PRECHARGE
An access command to (READ or WRITE) another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRE-
CHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
READ with auto precharge
1. Interrupted by a READ (with or without auto pre-
charge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is
registered (Figure 24).
2. Interrupted by a WRITE (with or without auto pre-
charge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to pre-
vent bus contention. The PRECHARGE to bank n
will begin when the WRITE to bank m is registered
(Figure 25).
Figure 27: READ With Auto Precharge Interrupted by a READ
Figure 28: READ With Auto Precharge Interrupted by a WRITE
DON’T CARE
CLK
DQ D
OUT
a
T2T1 T4T3 T6T5T0
COMMAND READ - AP
BANK nNOP NOPNOPNOP
D
OUT
a + 1
D
OUT
d
D
OUT
d + 1
NOP
T7
BANK n
CAS Latency = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
NOTE: DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active READ with Burst of 4 Interrupt Burst, Precharge
Page Active READ with Burst of 4 Precharge
RP - BANK ntRP - BANK m
CAS Latency = 3 (BANK n)
TRANSITIONING DATA
CLK
DQ D
OUT
a
T2T1 T4T3 T6T5T0
COMMAND NOPNOPNOPNOP
D
IN
d + 1
D
IN
d
D
IN
d + 2
D
IN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a + 1 from contending with DIN-d at T4.
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active READ with Burst of 4 Interrupt Burst, Precharge
Page Active WRITE with Burst of 4 Write-Back
RP -
BANK
ntWR -
BANK
m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON’T CARETRANSITIONING DATA
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SDRAM
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512mbSDRAM.fm - Rev. G 1/04 EN 27 ©2000 Micron Technology, Inc. All rights reserved.
WRITE with auto precharge
3. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-
out appearing CAS latency later. The PRECHARGE
to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered.
The last valid WRITE to bank n will be data-in reg-
istered one clock prior to the READ to bank m
(Figure 26).
4. Interrupted by a WRITE (with or without auto pre-
charge): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRE-
CHARGE to bank n will begin after tWR is met,
where tWR begins when the WRITE to bank m is
registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE
to bank m (Figure 27).
Figure 29: WRITE With Auto Precharge Interrupted by a READ
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
DON’T CARE
CLK
DQ
T2T1 T4T3 T6T5T0
COMMAND WRITE - AP
BANK nNOPNOPNOPNOP
DIN
a + 1
DIN
a
NOP NOP
T7
BANK n
BANK m
ADDRESS
NOTE: 1. DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4
t
tRP - BANK m
DOUT
d
DOUT
d + 1
CAS Latency = 3 (BANK m)
RP - BANK n
WR - BANK n
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2T1 T4T3 T6T5T0
COMMAND WRITE - AP
BANK nNOPNOPNOPNOP
DIN
d + 1
DIN
d
DIN
a + 1
DIN
a + 2
DIN
a
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
WR - BANK ntRP - BANK n
tWR - BANK m
TRANSITIONING DATA
512Mb: x4, x8, x16
SDRAM
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512mbSDRAM.fm - Rev. G 1/04 EN 28 ©2000 Micron Technology, Inc. All rights reserved.
NOTE:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or
NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP com-
mands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
Table 5: Truth Table 2 – CKE
CKEN-1 CKENCURRENT STATE COMMANDNACTIONNNOTES
L L Power-Down X Maintain Power-Down
Self Refresh X Maintain Self Refresh
Clock Suspend X Maintain Clock Suspend
L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5
Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6
Clock Suspend X Exit Clock Suspend 7
H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry
All Banks Idle AUTO REFRESH Self Refresh Entry
Reading or Writing VALID Clock Suspend Entry
H H See Truth Table 3 (page 28)
512Mb: x4, x8, x16
SDRAM
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NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 5 on page 28) and after tXSR has been met (if the
previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP com-
mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Table 7
on page 31.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,
the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,
the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
Table 6: Truth Table 3 – Current State Bank n - Command To Bank n
(Notes: 1-6; notes appear below and on next page)
CURRENT
STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES
Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)
LHH H
NO OPERATION (NOP/Continue previous operation)
Idle L L H H ACTIVE (Select and activate row)
LLL H
AUTO REFRESH 7
LLL L
LOAD MODE REGISTER 7
LLH L
PRECHARGE 11
Row Active L H L H READ (Select column and start READ burst) 10
LHL L
WRITE (Select column and start WRITE burst) 10
LLH L
PRECHARGE (Deactivate row in bank or banks) 8
Read
(Auto
Precharge
Disabled)
LHL H
READ (Select column and start new READ burst) 10
LHL L
WRITE (Select column and start WRITE burst) 10
LLH L
PRECHARGE (Truncate READ burst, start PRECHARGE) 8
LHH L
BURST TERMINATE 9
Write
(Auto
Precharge
Disabled)
LHL H
READ (Select column and start READ burst) 10
LHL L
WRITE (Select column and start new WRITE burst) 10
LLH L
PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8
LHH L
BURST TERMINATE 9
512Mb: x4, x8, x16
SDRAM
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Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
512Mb: x4, x8, x16
SDRAM
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NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the pre-
vious state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com-
mands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command
is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
Table 7: Truth Table 4 - Current State Bank n - Command To Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT
STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES
Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)
LHH H
NO OPERATION (NOP/Continue previous operation)
Idle X X X X Any Command Otherwise Allowed to Bank m
Row
Activating,
Active, or
Precharging
LLHH
ACTIVE (Select and activate row)
LHL H
READ (Select column and start READ burst) 7
LHL L
WRITE (Select column and start WRITE burst) 7
LLH L
PRECHARGE
Read
(Auto
Precharge
Disabled)
LLHH
ACTIVE (Select and activate row)
LHL H
READ (Select column and start new READ burst) 7, 10
LHL L
WRITE (Select column and start WRITE burst) 7, 11
LLH L
PRECHARGE 9
Write
(Auto
Precharge
Disabled)
LLHH
ACTIVE (Select and activate row)
LHL H
READ (Select column and start READ burst) 7, 12
LHL L
WRITE (Select column and start new WRITE burst) 7, 13
LLH L
PRECHARGE 9
Read
(With Auto
Precharge)
LLHH
ACTIVE (Select and activate row)
LHL H
READ (Select column and start new READ burst) 7, 8, 14
LHL L
WRITE (Select column and start WRITE burst) 7, 8, 15
LLH L
PRECHARGE 9
Write
(With Auto
Precharge)
LLHH
ACTIVE (Select and activate row)
LHL H
READ (Select column and start READ burst) 7, 8, 16
LHL L
WRITE (Select column and start new WRITE burst) 7, 8, 17
LLH L
PRECHARGE 9
512Mb: x4, x8, x16
SDRAM
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512mbSDRAM.fm - Rev. G 1/04 EN 32 ©2000 Micron Technology, Inc. All rights reserved.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 11).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figure 13 and Figure 14 on page 20). DQM should be used one clock
prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 20 on page 23), with the data-out appearing CAS latency later.
The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 18 on page 22). The last valid WRITE to bank n will be data-
in registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is reg-
istered (Figure 27 on page 26).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 28 on page 26).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 29 on page 27).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to
the WRITE to bank m (Figure 30 on page 27).
512Mb: x4, x8, x16
SDRAM
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512mbSDRAM.fm - Rev. G 1/04 EN 33 ©2000 Micron Technology, Inc. All rights reserved.
Absolute Maximum Ratings
Voltage on VDD, VDDQ Supply
Relative to VSS -1V to . . . . . . . . . . . . . . . . . . . . . .+4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS . . . . . . . . . . . . . . . . . . . . . .-1V to +4.6V
Operating Temperature
TA (Commercial . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature (plastic). . . . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ω
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Table 8: DC Electrical Characteristics And Operating Conditions
(Notes: 1, 5, 6; notes appear on page 37) (VDD, VDDQ = +3.3V ±0.3V)
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Supply Voltage VDD, VDDQ33.6V
Input High Voltage: Logic 1; All inputs VIH 2VDD +
0.3
V22
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
VIL -0.3 0.8 V 22
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
II-5 5 µA
Output Leakage Current: DQs are disabled;
0V ≤ VOUT ≤ VDDQ
IOZ -5 5 µA
Output Levels:
Output High Voltage (IOUT = -4mA)
VOH 2.4 – V 26
Output Low Voltage (IOUT = 4mA) VOL –0.4V26
Table 9: IDD Specifications And Conditions
(Notes: 1, 5, 6, 11, 13; notes appear on page 37) (VDD, VDDQ = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION SYMBOL -7E -75 UNITS NOTES
Operating Current: Active Mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN)
IDD1120 110 mA 3, 18,
19, 29
Standby Current: Power-Down Mode;
CKE = LOW; All banks idle
IDD23.5 3.5 mA 29
Standby Current: Active Mode; CS# = HIGH;
CKE = HIGH; All banks active after tRCD met;
No accesses in progress
IDD345 45 mA 3, 12,
19, 29
Operating Current: Burst Mode; Page burst;
READ or WRITE; All banks active
IDD4125 115 mA 3, 18,
19, 29
Auto Refresh Current:
CS# = HIGH; CKE = HIGH
tRFC = tRFC
(MIN)
IDD5245 245 mA 3, 18, 19,
29,30
tRFC = 7.81µs IDD666mA
Self Refresh Current: CKE ≤ 0.2V Standard IDD766mA 4
Low-power
(L)
IDD733mA
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 34 ©2000 Micron Technology, Inc. All rights reserved.
Table 10: Capacitance
Note: 2; notes appear on page 37
PARAMETER SYMBOL MIN MAX UNITS
Input Capacitance: CLK CI12.5 3.5 pF
Input Capacitance: All other input-only pins CI22.5 3.8 pF
Input/Output Capacitance: DQs CIO 4.0 6.0 pF
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 35 ©2000 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics And Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11; notes appear on page 37
AC CHARACTERISTICS -7E -75
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from CLK (pos. edge) CL = 3 tAC(3) 5.4 5.4 ns 27
CL = 2 tAC(2) 5.4 6 ns
Address hold time tAH 0.8 0.8 ns
Address setup time tAS 1.5 1.5 ns
CLK high-level width tCH 2.5 2.5 ns
CLK low-level width tCL 2.5 2.5 ns
Clock cycle time CL = 3 tCK(3) 77.5ns23
CL = 2 tCK(2) 7.5 10 ns 23
CKE hold time tCKH 0.8 0.8 ns
CKE setup time tCKS 1.5 1.5 ns
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 ns
Data-in hold time tDH 0.8 0.8 ns
Data-in setup time tDS 1.5 1.5 ns
Data-out high-impedance time CL = 3 tHZ(3) 5.4 5.4 ns 10
CL = 2 tHZ(2) 5.4 6 ns 10
Data-out low-impedance time tLZ 11ns
Data-out hold time (load) tOH 2.7 2.7 ns
Data-out hold time (no load) tOHN1.8 1.8 ns 28
ACTIVE to PRECHARGE command tRAS 37 120K 44 120K ns
ACTIVE to ACTIVE command period tRC 60 66 ns
ACTIVE to READ or WRITE delay tRCD 15 20 ns
Refresh period (8,192 rows) tREF 64 64 ms
AUTO REFRESH period tRFC 66 66 ns
PRECHARGE command period tRP 15 20 ns
ACTIVE bank a to ACTIVE bank b command tRRD 14 15 ns
Transition time tT0.3 1.2 0.3 1.2 ns 7
WRITE recovery time tWR 1 CLK +
7ns
1 CLK +
7.5ns
-24
14 15 ns 14,
25
Exit SELF REFRESH to ACTIVE command tXSR 67 75 ns 20
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 36 ©2000 Micron Technology, Inc. All rights reserved.
Table 12: AC Functional Characteristics
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 37)
PARAMETER SYMBOL -7E -75 UNITS NOTES
READ/WRITE command to READ/WRITE command tCCD 11
tCK 17
CKE to clock disable or power-down entry mode tCKED 11
tCK 14
CKE to clock enable or power-down exit setup mode tPED 11
tCK 14
DQM to input data delay tDQD 00
tCK 17
DQM to data mask during WRITEs tDQM 00
tCK 17
DQM to data high-impedance during READs tDQZ 22
tCK 17
WRITE command to input data delay tDWD 00
tCK 17
Data-in to ACTIVE command tDAL 45
tCK 15, 21
Data-in to PRECHARGE command tDPL 22
tCK 16, 21
Last data-in to burst STOP command tBDL 11
tCK 17
Last data-in to new READ/WRITE command tCDL 11
tCK 17
Last data-in to PRECHARGE command tRDL 22
tCK 16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
tMRD 22
tCK 26
Data-out to high-impedance from PRECHARGE command CL = 3 tROH(3) 33
tCK 17
CL = 2 tROH(2) 22
tCK 17
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 37 ©2000 Micron Technology, Inc. All rights reserved.
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V; =
25°C; pin under test biased at 1.4V. f = 1 MHz, TA
3. IDD is dependent on output loading and cycle
rates.Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range (0°C ≤ ≤ 70°C) is
TA ensured.
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously.
VSS and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a mono-
tonic manner.
9. Outputs measured at 1.5V with equivalent load:
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at VIL (MAX) and VIH
(MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are other-
wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
14. Timing actually specified by tCKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will increase or decrease in a pro-
portional amount by the amount the frequency is
altered for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 7.5ns for -75 and -7E.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL under-
shoot: VIL (MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing tWR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7.5ns/7ns after the first clock
delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and
is guaranteed by design.
28. Parameter guaranteed by design.
29. For -75, CL = 3, tCK = 7.5ns; For -7E, CL = 2, tCK =
7.5ns
30. CKE is HIGH during refresh command period
tRFC(MIN) else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a
fail value.
Q
50pF
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 38 ©2000 Micron Technology, Inc. All rights reserved.
Figure 31: Initialize And Load Mode Register2
NOTE:
1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock high time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at tP + 1.
tCH
tCL
tCK
CKE
CK
COMMAND
DQ
BA0, BA1
BANK
tRFC tMRD
tRFC
AUTO REFRESH AUTO REFRESH Program Mode Register 1, 3, 4
tCMH
tCMS
Precharge
all banks
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tRP
(
)(
)
(
)(
)
tCKS
Power-up:
VDD and
CLK stable
T = 100µs
MIN
PRECHARGE NOP AUTO
REFRESH NOP
LOAD MODE
REGISTER ACTIVENOP NOPNOP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
AUTO
REFRESH
ALL
BANKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
High-Z
tCKH
(
)(
)
(
)(
)
DQM/
DQML, DQMH
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)(
)(
)
(
)(
)
(
)(
)
NOP
(
)(
)
(
)(
)
tCMH
tCMS tCMH
tCMS
A0-A9, A11, A12
ROW
tAH 5
tAS
CODE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
A10
ROW
tAH
tAS
CODE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
ALL BANKS
SINGLE BANK
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DON’T CARE
UNDEFINED
T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
-7E -75
SYMBOL MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (CL = 3) 77.5ns
tCK (CL = 2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tMRD322
tCK
tRFC 66 66 ns
tRP 15 20 ns
-7E -75
SYMBOL MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 39 ©2000 Micron Technology, Inc. All rights reserved.
Figure 32: Power-down Mode1
NOTE:
1. Violating refresh requirements during power-down may result in a loss of data.
2. CAS latency indicated in parentheses
tCH
tCL
tCK
CKE
CK
COMMAND
DQ
BA0, BA1 BANK
tRFC tMRD
tRFC
AUTO REFRESH AUTO REFRESH Program Mode Register 1, 3, 4
tCMH
tCMS
Precharge
all banks
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tRP
(
)(
)
(
)(
)
tCKS
Power-up:
VDD and
CLK stable
T = 100µs
MIN
PRECHARGE NOP AUTO
REFRESH NOP
LOAD MODE
REGISTER ACTIVENOP NOPNOP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
AUTO
REFRESH
ALL
BANKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
High-Z
tCKH
(
)(
)
(
)(
)
DQM/
DQML, DQMH
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)(
)(
)
(
)(
)
(
)(
)
NOP
(
)(
)
(
)(
)
tCMH
tCMS tCMH
tCMS
A0-A9, A11, A12 ROW
tAH 5
tAS
CODE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
A10 ROW
tAH
tAS
CODE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
ALL BANKS
SINGLE BANK
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DON’T CARE
UNDEFINED
T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
-7E -75
SYMBOL MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
-7E -75
SYMBOL MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 40 ©2000 Micron Technology, Inc. All rights reserved.
Figure 33: Clock Suspend Mode1
NOTE:
1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.
2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses
tCH
tCL
tCK
tAC
tLZ
DQM/
DQML, DQMU
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tOH
DOUT
m
tAH
tAS
tAH
tAS
tAH
tAS
BANK
tDH
Din
e
tAC
tHZ
D
OUT
m + 1
COMMAND
tCMH
tCMS
NOPNOP NOP NOPNOPREAD WRITE
DON T CARE
UNDEFINED
CKE
tCKS tCKH
BANK
COLUMN m
tDS
Din
+ 1
NOP
tCKH
tCKS
tCMH
tCMS
2
COLUMN e
2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11ns
tOH 2.7 2.7 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 41 ©2000 Micron Technology, Inc. All rights reserved.
Figure 34: Auto Refresh Mode
NOTE:
1. CAS latency indicated in parentheses
tCH
tCL
tCK
CKE
CLK
DQ
tRFC RFC
(
)(
)
(
)(
)
(
)(
)
tRP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
COMMAND
tCMH
tCMS
NOPNOP
(
)(
)
(
)(
)
BANK
ACTIVE
AUTO
REFRESH
(
)(
)
(
)(
)
NOPNOPPRECHARGE
Precharge all
active banks
AUTO
REFRESH
t
High-Z
BA0, BA1 BANK(S)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tAH
tAS
tCKH
tCKS
(
)(
)
NOP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DQM /
DQML, DQMH
A0-A9, A11, A12
ROW
(
)(
)
(
)(
)
ALL BANKS
SINGLE BANK
A10
ROW
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DON’T CARE
T0 T1 T2 Tn + 1 To + 1
-7E -75
SYMBOL1MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 0.8 ns
tRFC 66 66 ns
tRP 15 20 ns
-7E -75
SYMBOL1MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 42 ©2000 Micron Technology, Inc. All rights reserved.
Figure 35: Self Refresh Mode
NOTE:
1. No maximum time limit for Self Refresh. tRAS(MIN) applies to non-Self Refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency or timing.
3. CAS latency indicated in parentheses
tCH
tCL
t
CK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
(
)(
)(
)(
)
(
)(
)
(
)(
)
(
)(
)
DON’T CARE
COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE NOP NOP or COMMAND
INHIBIT
(
)(
)
(
)(
)
(
)(
)
(
)(
)
BA0, BA1 BANK(S)
(
)(
)
(
)(
)
High-Z
tCKS
AH
AS
AUTO
REFRESH
tRAS(MIN)
1
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tCKH
tCKS
DQM/
DQML, DQMU
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tt
A0-A9, A11,A12
(
)(
)
(
)(
)
(
)(
)
(
)(
)
ALL BANKS
SINGLE BANK
A10
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
T0 T1 T2 Tn + 1 To + 1 To + 2
(
)(
)
(
)(
)
≥
-7E -75
SYMBOL MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tRAS 37 120,000 44 120,000 ns
tRP 15 20 ns
tXSR 67 75 ns
-7E -75
SYMBOL MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 43 ©2000 Micron Technology, Inc. All rights reserved.
Figure 36: READ – Without Auto Precharge
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses
ALL BANKS
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD CAS Latency
tRC
DQM/
DQML, DQMU
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tOH
DOUT m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK BANK
ROW
ROW
BANK
tHZ
tOH
DOUT m + 3
tAC
tOH
tAC
tOH
tAC
DOUT m + 2DOUT m + 1
COMMAND
tCMH
tCMS
PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE
DISABLE AUTO PRECHARGE SINGLE BANK
DON’T CARE
UNDEFINED
tCKH
tCKS
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5 ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11 ns
tOH 2.7 2.7 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 44 ©2000 Micron Technology, Inc. All rights reserved.
Figure 37: READ – With Auto Precharge 1
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses 1
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD CAS Latency
tRC
DQM/
DQML, DQMU
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tOH
DOUT m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
DON’T CARE
UNDEFINED
tHZ
tOH
D
OUT
m + 3
tAC
tOH
tAC
tOH
tAC
D
OUT
m + 2D
OUT
m + 1
COMMAND
tCMH
tCMS
NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP
tCKH
tCKS
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5 ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11 ns
tOH 2.7 2.7 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 45 ©2000 Micron Technology, Inc. All rights reserved.
Figure 38: Single READ – Without Auto Precharge 1
NOTE:
1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses.
ALL BANKS
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD CAS Latency
tRC
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK(S) BANK
ROW
ROW
BANK
tHZ
tCMH
tCMS
NOPNOPNOP PRECHARGE
ACTIVE NOP READ ACTIVE NOP
DISABLE AUTO PRECHARGE SINGLE BANKS
DON’T CARE
UNDEFINED
COLUMN m
2
tCKH
tCKS
T0 T1 T2 T3 T4 T5 T6 T7 T8
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
COMMAND
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11ns
tOH 2.7 2.7 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 46 ©2000 Micron Technology, Inc. All rights reserved.
Figure 39: Single READ – With Auto Precharge1
NOTE:
1. For this example, the burst length = 1, and the CAS latency = 2.
2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care”
3. READ command not allowed else tRAS would be violated
4. CAS latency indicated in parentheses.
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRCD CAS Latency
tRC
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
DON’T CARE
UNDEFINED
tHZ
tOH
D
OUT
m
tAC
COMMAND
tCMH
tCMS
NOP3READACTIVE NOP NOP3ACTIVENOP
tCKH
tCKS
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8
NOP NOP
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11ns
tOH 2.7 2.7 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 47 ©2000 Micron Technology, Inc. All rights reserved.
Figure 40: Alternating Bank Read Accesses1
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses.
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tAC
tLZ
DQM/
DQML, DQMU
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
ROW
ROW
DON’T CARE
UNDEFINED
tOH
D
OUT
m + 3
tAC
tOH
tAC
tOH
tAC
D
OUT
m + 2D
OUT
m + 1
COMMAND
tCMH
tCMS
NOP NOPACTIVE NOP READ NOP ACTIVE
tOH
D
OUT
b
tAC tAC
READ
ENABLE AUTO PRECHARGE
ROW
ACTIVE
ROW
BANK 0 BANK 0 BANK 3 BANK 3 BANK 0
CKE
tCKH
tCKS
COLUMN m
2
COLUMN b
2
T0 T1 T2 T4T3 T5 T6 T7 T8
tRP - BANK 0
tRAS - BANK 0
tRCD - BANK 0 tRCD - BANK 0
CAS Latency - BANK 0
tRCD - BANK 1 CAS Latency - BANK 1
t
t
RC - BANK 0
RRD
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tLZ 11ns
tOH 2.7 2.7 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
tRRD 14 15 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 48 ©2000 Micron Technology, Inc. All rights reserved.
Figure 41: Read – Full-page Burst 1
NOTE:
1. For this example, the CAS latency = 2.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. Page left open; no tRP.
4. CAS latency indicated in parentheses.
tCH
tCL tCK
tAC
tLZ
tRCD CAS Latency
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAC
tOH
D
OUT
m+1
ROW
ROW
tHZ
t
AC
tOH
D
OUT
m
+1
tAC
tOH
D
OUT
m+2
tAC
tOH
D
OUT
m-1
tAC
tOH
Dout m
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Full page completed
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
DON’T CARE
UNDEFINED
COMMAND
tCMH
tCMS
NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP
(
)(
)
(
)(
)
NOP
(
)(
)
(
)(
)
tAH
tAS
BANK
(
)(
)
(
)(
)
BANK
tCKH
tCKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
COLUMN m
2
3
T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11ns
tOH 2.7 2.7 ns
tRCD 15 20 ns
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 49 ©2000 Micron Technology, Inc. All rights reserved.
Figure 42: Read DQM Operation1
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses.
tCH
tCL
tCK
tRCD CAS Latency
DQM/
DQML, DQMU
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMS
ROW
BANK
ROW
BANK
DON’T CARE
UNDEFINED
tAC
LZ
D
OUT
m
tOH
D
OUT
m + 3D
OUT
m + 2
ttHZ LZ
t
tCMH
COMMAND
NOPNOP NOPACTIVE NOP READ NOPNOP NOP
tHZ
tAC tOH
tAC
tOH
tAH
tAS
tCMS tCMH
tAH
tAS
tAH
tAS
tCKH
tCKS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns
tAC (2) 5.4 6 ns
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tHZ (3) 5.4 5.4 ns
tHZ (2) 5.4 6 ns
tLZ 11ns
tOH 2.7 2.7 ns
tRCD 15 20 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 50 ©2000 Micron Technology, Inc. All rights reserved.
Figure 43: Write – Without Auto Precharge1
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
4. CAS latency indicated in parentheses.
DISABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
DQM/
DQML, DQMU
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
BANK BANK
ROW
BANK
t
DON’T CARE
D
IN
m
tDH
tDS
D
IN
m + 1 D
IN
m + 2 D
IN
m + 3
COMMAND
t
CMH
t
CMS
NOPNOP NOPACTIVE NOP WRITE PRECHARGE
tAH
tAS
tAH
tAS
tDH
tDS tDH
tDS tDH
tDS
SINGLE BANK
tCKH
tCKS
COLUMN m
2
3
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
ROW
BANK
ROW
ACTIVE
NOP
WR
NOP
ALL BANKs
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
tWR 14 15 ns
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 51 ©2000 Micron Technology, Inc. All rights reserved.
Figure 44: Write – With Auto Precharge1
NOTE:
1. For this example, the burst length = 4.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses.
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
tWR
DON’T CARE
D
IN
m
tDH
tDS
D
IN
m + 1 D
IN
m + 2 D
IN
m + 3
COMMAND
t
CMH
t
CMS
NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS tDH
tDS tDH
tDS
tCKH
tCKS
NOP NOP
COLUMN
m
2
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
tWR 1 CLK
+7ns
1 CLK
+7.5ns
–
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 52 ©2000 Micron Technology, Inc. All rights reserved.
Figure 45: Single Write – Without Auto Precharge1
NOTE:
1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated
5. CAS latency indicated in parentheses.
DISABLE AUTO PRECHARGE
ALL BANKS
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
BANK BANK BANK
ROW
ROW
BANK
tWR
D
IN
m
tDH
tDS
COMMAND
t
CMH
t
CMS
NOP4
NOP4PRECHARGEACTIVE NOP WRITE ACTIVENOP NOP
tAH
tAS
tAH
tAS
SINGLE BANK
tCKH
tCKS
COLUMN m
3
2
T0 T1 T2 T4T3 T5 T6 T7 T8
DON’T CARE
UNDEFINED
-7E -75
SYMBOL5MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
tWR 14 15 ns
-7E -75
SYMBOL5MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 53 ©2000 Micron Technology, Inc. All rights reserved.
Figure 46: Single Write with Auto Precharge
NOTE:
1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
4. WRITE command not allowed else tRAS would be violated
5. CAS latency indicated in parentheses.
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRCD3
tRC
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
tWR2
D
IN
m
COMMAND
t
CMH
t
CMS
NOP4NOP4NOPACTIVE NOP4WRITE NOP
ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS
tCKH
tCKS
NOP NOP
COLUMN m
3
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
DON’T CARE
UNDEFINED
-7E -75
SYMBOL5MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
tWR 1 CLK
+
7ns
1 CLK
+
7ns
ns
-7E -75
SYMBOL5MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 54 ©2000 Micron Technology, Inc. All rights reserved.
Figure 47: Alternating Bank Write Accesses1
NOTE:
1. For this example, the burst length = 4.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
4. CAS latency indicated in parentheses.
tCH
tCL
tCK
CLK
DQ
DON’T CARE
D
IN
m
tDH
tDS
D
IN
m + 1 D
IN
m + 2 D
IN
m + 3
COMMAND
t
CMH
t
CMS
NOP NOPACTIVE NOP WRITE NOP NOP ACTIVE
tDH
tDS tDH
tDS tDH
tDS
ACTIVE WRITE
D
IN
b
tDH
tDS
D
IN
b + 1 D
IN
b + 3
tDH
tDS tDH
tDS
ENABLE AUTO PRECHARGE
DQM/
DQML, DQMU
A0-A9, A11, A12
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
ROW
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
BANK 0 BANK 0 BANK 1 BANK 0
BANK 1
CKE
tCKH
tCKS
D
IN
b + 2
tDH
tDS
COLUMN b
3
COLUMN m
3
tRP - BANK 0
tRAS - BANK 0
tRCD - BANK 0 t
t
RCD - BANK 0
tWR - BANK 0
WR - BANK 1
tRCD - BANK 1
t
t
RC - BANK 0
RRD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRAS 37 120,000 44 120,000 ns
tRC 60 66 ns
tRCD 15 20 ns
tRP 15 20 ns
tRRD 14 15 ns
tWR Note 2 Note 2 ns
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 55 ©2000 Micron Technology, Inc. All rights reserved.
Figure 48: Write – Full-page Burst
NOTE:
1. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
4. CAS latency indicated in parentheses.
tCH
tCL tCK
tRCD
DQM/
DQML, DQMH
CKE
CLK
A0-A9, A11, A12
BA0, BA1
A10
tCMS
tAH
tAS
tAH
tAS
ROW
ROW
Full-page burst does
not self-terminate.
Can use BURST TERMINATE
command to stop.2, 3
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Full page completed DON’T CARE
COMMAND
tCMH
tCMS
NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DQ
D
IN
m
tDH
tDS
D
IN
m + 1 D
IN
m + 2 D
IN
m + 3
tDH
tDS tDH
tDS tDH
tDS
D
IN
m - 1
tDH
tDS
tAH
tAS
BANK
(
)(
)
(
)(
)
BANK
tCMH
tCKH
tCKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
COLUMN
m
1
T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRCD 15 20 ns
-7E -75
SYMBOL4MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 56 ©2000 Micron Technology, Inc. All rights reserved.
Figure 49: Write – DQM Operation1
NOTE:
1. For this example, the burst length = 4.
2. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
3. CAS latency indicated in parentheses.
tCH
tCL
tCK
tRCD CAS Latency
DQM/
DQML, DQMU
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMS
ROW
BANK
ROW
BANK
DON’T CARE
UNDEFINED
tAC
LZ
D
OUT
m
tOH
D
OUT
m + 3D
OUT
m + 2
ttHZ LZ
t
tCMH
COMMAND NOPNOP NOPACTIVE NOP READ NOPNOP NOP
tHZ
tAC tOH
tAC
tOH
tAH
tAS
tCMS tCMH
tAH
tAS
tAH
tAS
tCKH
tCKS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns
tAS 1.5 1.5 ns
tCH 2.5 2.5 ns
tCL 2.5 2.5 ns
tCK (3) 77.5ns
tCK (2) 7.5 10 ns
tCKH 0.8 0.8 ns
tCKS 1.5 1.5 ns
tCMH 0.8 0.8 ns
tCMS 1.5 1.5 ns
tDH 0.8 0.8 ns
tDS 1.5 1.5 ns
tRCD 15 20 ns
-7E -75
SYMBOL3MIN MAX MIN MAX UNITS
512Mb: x4, x8, x16
SDRAM
09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifications without notice.
512mbSDRAM.fm - Rev. G 1/04 EN 57 ©2000 Micron Technology, Inc. All rights reserved.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Figure 50: 54-Pin Plastic TSOP (400 mil)
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.R
SEE DETAIL A
0.80 TYP 0.71
10.16 ±0.08
0.50 ±0.10
PIN #1 ID
DETAIL A
22.22 ±0.08
0.375 ±0.075
1.2 MAX
0.10
0.25
11.76 ±0.20
0.80
TYP
0.15 +0.03
-0.02
0.10 +0.10
-0.05
GAGE PLANE
PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC
LEAD FINISH: TIN/LEAD PLATE
PACKAGE WIDTH AND LENGTH DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 PER SIDE.
