STK621728SGE - ON SEMICONDUCTOR

October, 2017 − Rev. 3

1Publication Order Number:

ESD7421/D

ESD7421, SZESD7421

ESD Protection Diode

Micro−Packaged Diodes for ESD Protection

The ESD7421 is designed to protect voltage sensitive components

from ESD. Excellent clamping capability, low leakage, and fast

response time provide best in class protection on designs that are

exposed to ESD. Because of its small size, it is suited for use in cellular

phones, automotive sensors, infotainment, MP3 players, digital

cameras and many other applications where board space comes at a

premium.

Specification Features

•Low Capacitance 0.3 pF

•Low Clamping Voltage

•Low Leakage 100 nA

•Response Time is < 1 ns

•IEC61000−4−2 Level 4 ESD Protection

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

MAXIMUM RATINGS

Rating Symbol Value Unit

IEC 61000−4−2 (ESD) Contact

Air

±12

±15

Total Power Dissipation on FR−5 Board

(Note 1) @ TA = 25°C

Thermal Resistance, Junction−to−Ambient

°PD°

RqJA

300

400

°C/W

Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C

Lead Solder Temperature − Maximum

(10 Second Duration)

TL260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. FR−5 = 1.0 x 0.75 x 0.62 in.

See Application Note AND8308/D for further description of survivability specs.

Device Package Shipping†

ORDERING INFORMATION

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

www.onsemi.com

ESD7421N2T5G XDFN2

(Pb−Free)

8000 /

Tape & Reel

XDFN2

(SOD−882)

CASE 711AM

MARKING

DIAGRAM

Pin 2

5 = Specific Device Code

M = Date Code

G= Pb−Free Package

5 M

SZESD7421N2T5G XDFN2

(Pb−Free)

8000 /

Tape & Reel

Pin 1

ESD7421, SZESD7421

www.onsemi.com

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR1 Breakdown Voltage @ IT

VBR2 Breakdown Voltage @ IT

ITTest Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Bi−Directional

IPP

VRWM

VCVBR2

VRWM VC

VBR1

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working

Voltage

VRWM Pin 1 to GND

Pin 2 to GND

Breakdown Voltage VBR1 IT = 1 mA, Pin 1 to GND 16.5 V

Breakdown Voltage VBR2 IT = 1 mA, Pin 2 to GND 10.5 14 V

Reverse Leakage

Current

IRVRWM = 5 V, I/O Pin to GND

VRWM = 16 V, Pin 1 to GND

100 500

1.0

Clamping Voltage

(Note 2)

VCIEC61000−4−2, ±8 kV Contact See Figures 2 and 3

Clamping Voltage TLP

(Note 3)

VCIPP = 8 A

IPP = 16 A

IPP = −8 A

IPP = −16 A

38.1

−21

−29.5

Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.6 pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. For test procedure see Figure 5 and application note AND8307/D.

3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

ESD7421, SZESD7421

www.onsemi.com

1.0

Figure 1. Typical CV Characteristic Curve

Pin1 to GND (GND connected to Pin2)

VBias (V)

CAPACITANCE (pF)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Figure 2. IEC61000−4−2 +8 kV Contact ESD

Clamping Voltage

Pin1 to GND (GND connected to Pin2)

−25

120

TIME (ns)

VOLTAGE (V)

100

−20

25 50 75 150100 125

Figure 3. IEC61000−4−2 −8 kV Contact ESD

Clamping Voltage

Pin1 to GND (GND connected to Pin2)

−25

TIME (ns)

VOLTAGE (V)

0 25 50 150100 125

−20

−40

−60

−80

−100

−120

−5−4−201235

4−1−3

ESD7421, SZESD7421

www.onsemi.com

IEC 61000−4−2 Spec.

Level

Test Volt-

age (kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 4. IEC61000−4−2 Spec

Figure 5. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

Device

Under

Test Oscilloscope

ESD Gun

50 W

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD7421, SZESD7421

www.onsemi.com

Figure 6. Positive TLP IV Curve Figure 7. Negative TLP IV Curve

CURRENT (A)

VOLTAGE (V)

045353051015 2520

CURRENT (A)

VOLTAGE (V)

0−35−5−10 −15 −20 −30−25

−20

−16

−14

−12

−10

−8

−6

−4

−2

NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.

18 −18

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 8. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 9 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels.

Figure 8. Simplified Schematic of a Typical TLP

System

DUT

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

ESD7421, SZESD7421

www.onsemi.com

PACKAGE DIMENSIONS

XDFN2 1.0 x 0.6, 0.65P (SOD−882)

CASE 711AM

ISSUE O

ÉÉ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. EXPOSED COPPER ALLOWED AS SHOWN.

A B

BOTTOM VIEW

0.10 C

TOP VIEW

0.05 C

0.10 C

CSEATING

PLANE

SIDE VIEW

DIM MIN MAX

MILLIMETERS

A0.34 0.44

A1 −−− 0.05

b0.43 0.53

D1.00 BSC

E0.60 BSC

SOLDER FOOTPRINT*

DIMENSIONS: MILLIMETERS

1.20

0.60

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

L0.20 0.30

0.47

RECOMMENDED

PIN 1

INDICATOR

e0.65 BSC

0.05 BC

e/2

2X 2X

NOTE 3

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Phone: 421 33 790 2910

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Phone: 81−3−5817−1050

ESD7421/D

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