LTM4613 EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC Module Regulator DESCRIPTION FEATURES n n n n n n n n n n n n n n n n n n Complete Low EMI Switch Mode Power Supply EN55022 Class B Compliant Wide Input Voltage Range: 5V to 36V 8A Output Current 3.3V to 15V Output Voltage Range Low Input and Output Referred Noise Output Voltage Tracking and Margining PLL Frequency Synchronization 2% Maximum Total DC Error Power Good Tracks with Margining Current Foldback Protection Parallel/Current Sharing Ultrafast Transient Response Current Mode Control Programmable Soft-Start Output Overvoltage Protection -55C to 125C Operating Temperature Range (LTM4613MPV, LTM4613MPY) 15mm x 15mm x 4.32mm LGA and 15mm x 15mm x 4.92mm BGA Packages SnPb (BGA) or RoHS Compliant (LGA and BGA) Finish APPLICATIONS n n n The LTM(R)4613 is a complete, ultralow noise, 8A switch mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V, the LTM4613 supports an output voltage range of 3.3V to 15V, set by a single external resistor. Only bulk input and output capacitors are needed to finish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)--see Figure 7. Furthermore, the DC/DC Module(R) regulator can be synchronized with an external clock to reduce undesirable frequency harmonics and allow PolyPhase(R) operation for high load currents. The LTM4613 is offered in 15mm x 15mm x 4.32mm LGA and 15mm x 15mm x 4.92mm BGA packages. The LTM4613 is available with SnPb (BGA) or RoHS compliant terminal finish. L, LT, LTC, LTM, Module, PolyPhase, Linear Technology, and the Linear logo are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Telecom and Networking Equipment Industrial and Avionic Equipment RF Systems TYPICAL APPLICATION Radiated Emission Scan with 24VIN to 12VOUT at 8A 12V/8A Ultralow Noise Module with 24V to 36V Input 70 CLOCK SYNC VIN 24V TO 36V 51k CIN 0.1F 10F x3 VIN PLLIN VOUT PGOOD RUN LTM4613 COMP VFB INTVCC DRVCC FCB fSET MARG0 TRACK/SS MARG1 VD MPGM SGND PGND 60 22pF VOUT 12V 8A COUT 5.23k MARGIN CONTROL 392k 5% MARGIN 4613 TA01 For more information www.linear.com/LTM4613 SIGNAL AMPLITUDE (dB uV/m) n 50 EN55022B LIMIT 40 30 20 10 0 -10 30 226.2 422.4 613.6 814.3 1010.0 FREQUENCY (MHz) 4613 TA01b 4613fd 1 LTM4613 ABSOLUTE MAXIMUM RATINGS (Note 1) INTVCC, DRVCC.............................................. -0.3V to 6V VOUT............................................................ -0.3V to 16V PLLIN, FCB, TRACK/SS, MPGM, MARG0, MARG1, PGOOD.....................-0.3V to INTVCC + 0.3V RUN.............................................................. -0.3V to 5V VFB, COMP................................................. -0.3V to 2.7V VIN , VD........................................................ -0.3V to 36V Internal Operating Temperature Range (Note 2) E- and I-Grades................................... -40C to 125C MP-Grade........................................... -55C to 125C Storage Temperature Range................... -55C to 125C Peak Solder Reflow Package Body Temperature...... 245C PIN CONFIGURATION VIN A BANK 1 B C D E PGND BANK 2 F G H J VOUT K BANK 3 L M VD VIN A BANK 1 B C D E PGND BANK 2 F G H J VOUT K BANK 3 L M fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB VD SGND 1 2 3 4 5 6 7 8 9 10 11 12 fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB VD SGND 1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm x 15mm x 4.32mm) TJMAX = 125C, JCtop = 17C/w, JCbottom = 2.3C/W, JA = 10C/W, JB = 2.5C/W, JA DERIVED FROM 95mm x 76mm PCB WITH 4 LAYERS WEIGHT = 2.5g ORDER INFORMATION INTVCC PLLIN TRACK/SS RUN COMP MPGM TOP VIEW INTVCC PLLIN TRACK/SS RUN COMP MPGM VD TOP VIEW BGA PACKAGE 133-LEAD (15mm x 15mm x 4.92mm) TJMAX = 125C, JCtop = 17C/w, JCbottom = 2.3C/W, JA = 10C/W, JB = 2.5C/W, JA DERIVED FROM 95mm x 76mm PCB WITH 4 LAYERS WEIGHT = 2.7g http://www.linear.com/product/LTM4613#orderinfo PART NUMBER PAD OR BALL FINISH PART MARKING* LTM4613EV#PBF Au (RoHS) LTM4613V e4 LGA 3 -40C to 125C LTM4613IV#PBF Au (RoHS) LTM4613V e4 LGA 3 -40C to 125C DEVICE FINISH CODE PACKAGE TYPE MSL RATING TEMPERATURE RANGE (Note 2) LTM4613MPV#PBF Au (RoHS) LTM4613V e4 LGA 3 -55C to 125C LTM4613EY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 -40C to 125C LTM4613IY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 -40C to 125C LTM4613IY SnPb (63/37) LTM4613Y e0 BGA 3 -40C to 125C LTM4613MPY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 -55C to 125C LTM4613MPY SnPb (63/37) LTM4613Y e0 BGA 3 -55C to 125C * Consult Marketing for parts specified with wider operating temperature * Recommended LGA and BGA PCB Assembly and Manufacturing ranges. *Device temperature grade is indicated by a label on the shipping Procedures: www.linear.com/umodule/pcbassembly container. Pad or ball finish code is per IPC/JEDEC J-STD-609. * LGA and BGA Package and Tray Drawings: www.linear.com/packaging * Terminal Finish Part Marking: www.linear.com/leadfree 2 4613fd For more information www.linear.com/LTM4613 LTM4613 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25C (Note 2), VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration. SYMBOL PARAMETER VIN(DC) Input DC Voltage VOUT(DC) Output Voltage, Total Variation with Line and Load CONDITIONS CIN = 10F x 3, COUT = 47F x 4; FCB = 0, VIN = 24V to 36V, VOUT = 12V MIN l 5 l 11.83 TYP MAX UNITS 36 V 12.07 12.31 V 4.8 V Input Specifications VIN(UVLO) Undervoltage Lockout Threshold IOUT = 0A 3.2 IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A; CIN = 10F x 3, COUT = 47F x 4; CSS = 22nF VOUT = 12V VIN = 24V VIN = 36V 150 120 mA mA 78 60 50 mA mA A IQ(VIN) Input Supply Bias Current VIN = 36V, VOUT = 12V, Switching Continuous, IOUT = 0A VIN = 24V, VOUT = 12V, Switching Continuous, IOUT = 0A Shutdown, RUN = 0, VIN = 36V IS(VIN) Input Supply Current VIN = 36V, VOUT = 12V, IOUT = 8A VIN = 24V, VOUT = 12V, IOUT = 8A VINTVCC Internal VCC Voltage VIN = 36V, RUN > 2V, IOUT = 0A 2.90 4.26 4.7 5 A A 5.5 V 8 A Output Specifications IOUT(DC) VOUT(LINE) VOUT Output Continuous Current Range VIN = 24V, VOUT = 12V (Note 4) Line Regulation Accuracy VOUT = 12V, FCB = 0V, VIN = 24V to 36V, IOUT = 0A 0 l 0.05 0.3 % l l 0.5 0.5 0.75 0.75 % % VOUT(LOAD) VOUT Load Regulation Accuracy VIN(AC) Input Ripple Voltage IOUT = 0A, CIN = 1 x 10F X5R Ceramic and 1 x 100F Electrolytic, 3 x 10F X5R Ceramic on VD Pins VIN = 24V, VOUT = 12V (Note 5) 10 mVP-P VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 1 x 10F, 4 x 47F X5R Ceramic VIN = 24V, VOUT = 12V 19 mVP-P VIN = 24V, VOUT = 12V, IOUT = 0A 600 kHz COUT = 47F x 4, VOUT = 12V, IOUT = 0A, CSS = 22nF VIN = 36V VIN = 24V 20 20 mV mV fS Output Ripple Voltage Frequency VOUT(START) Turn-On Overshoot VOUT = 12V, FCB = 0V, IOUT = 0A to 8A (Note 4) VIN = 36V VIN = 24V tSTART Turn-On Time COUT = 47F x 4, VOUT = 12V, IOUT = 0A, CSS = Open VIN = 36V VIN = 24V 0.3 0.3 ms ms VOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 1 x 10F, 3 x 47F X5R Ceramic, 1 x 47F POSCAP VIN = 24V, VOUT = 12V 250 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load COUT = 1 x 10F, 3 x 47F X5R Ceramic, 1 x 47F POSCAP VIN = 24V, VOUT = 12V 100 s IOUT(PK) Output Current Limit COUT = 47F x 4 VIN = 36V, VOUT = 12V VIN = 24V, VOUT = 12V 12 12 A A 4613fd For more information www.linear.com/LTM4613 3 LTM4613 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25C (Note 2), VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.591 0.6 0.609 V 1 1.5 1.9 V -1 -1.5 -2 A 0.57 0.6 0.63 V Control Section VFB Voltage at VFB Pin VRUN RUN Pin On/Off Threshold IOUT = 0A, VOUT = 12V l ITRACK/SS Soft-Start Charging Current VFCB Forced Continuous Threshold VTRACK/SS = 0V IFCB Forced Continuous Pin Current VFCB = 0V -1 -2 A tON(MIN) Minimum On-Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off-Time (Note 3) 250 400 ns 22 30 mA 100 100.5 k RPLLIN PLLIN Input Resistor IDRVCC Current into DRVCC Pin 50 RFBHI Resistor Between VOUT and VFB Pins VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V VOUT = 12V, IOUT = 0A, DRVCC = 5V 99.5 k PGOOD VFBH PGOOD Upper Threshold VFB Rising 7 10 13 % VFBL PGOOD Lower Threshold VFB Falling -7 -10 -13 % VFB(HYS) PGOOD Hysteresis VFB Returning 1.5 VPGL PGOOD Low Voltage IPGOOD = 5mA 0.2 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4613 is tested under pulsed load conditions such that TJ TA. The LTM4613E is guaranteed to meet performance specifications over the 0C to 125C internal operating temperature range. Specifications over the -40C to 125C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4613I is guaranteed to meet specifications over the -40C to 125C internal operating temperature range. The LTM4613MP 4 % 0.4 V is guaranteed and tested over the full -55C to 125C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See the Output Current Derating curves for different VIN, VOUT and TA. Note 5: Guaranteed by design. 4613fd For more information www.linear.com/LTM4613 LTM4613 TYPICAL PERFORMANCE CHARACTERISTICS (Refer to Figure 18) Efficiency vs Load Current with 5VOUT (FCB = 0) Efficiency vs Load Current with 12VOUT (FCB = 0) 100 100 95 95 95 90 90 90 85 80 75 70 60 0 1 2 4 5 3 6 LOAD CURRENT (A) 80 75 60 0 1 2 4 5 3 6 LOAD CURRENT (A) 4613 G01 80 75 20VIN, 12VOUT 24VIN, 12VOUT 28VIN, 12VOUT 36VIN, 12VOUT 65 60 8 7 85 70 12VIN, 5VOUT 24VIN, 5VOUT 36VIN, 5VOUT 65 8 7 85 70 5VIN, 3.3VOUT 12VIN, 3.3VOUT 24VIN, 3.3VOUT 36VIN, 3.3VOUT 65 EFFICIENCY (%) 100 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current with 3.3VOUT (FCB = 0) 0 1 2 4 5 3 6 LOAD CURRENT (A) 4613 G02 4613 G03 Transient Response from 12VIN to 3.3VOUT Efficiency vs Load Current with 15VOUT (FCB = 0) 8 7 Transient Response from 12VIN to 5VOUT 100 95 EFFICIENCY (%) 90 85 80 75 70 60 0 1 2 4 5 3 6 LOAD CURRENT (A) IOUT 5A/DIV VOUT 100mV/DIV AC VOUT 100mV/DIV AC 100s/DIV LOAD STEP: 0A TO 4A COUT = 1 x 47F POSCAP 1 x 10F CERAMIC CAPACITOR AND 3 x 47F CERAMIC CAPACITORS 24VIN, 15VOUT 28VIN, 15VOUT 32VIN, 15VOUT 36VIN, 15VOUT 65 IOUT 5A/DIV 4613 G05 100s/DIV LOAD STEP: 0A TO 4A COUT = 1 x 47F POSCAP 1 x 10F CERAMIC CAPACITOR AND 3 x 47F CERAMIC CAPACITORS 4613 G06 8 7 4613 G04 Transient Response from 24VIN to 12VOUT IOUT 5A/DIV VOUT 200mV/DIV AC 100s/DIV LOAD STEP: 0A TO 4A COUT = 1 x 47F POSCAP 1 x 10F CERAMIC CAPACITOR AND 3 x 47F CERAMIC CAPACITORS 4613 G07 Start-Up with 24VIN to 12VOUT at IOUT = 0A Start-Up with 24VIN to 12VOUT at IOUT = 8A IIN 200mA/DIV IIN 1A/DIV VOUT 5V/DIV VOUT 5V/DIV 4613 G08 10ms/DIV SOFT-START CAPACITOR: 0.1F CIN = 2 x 10F CERAMIC CAPACITORS AND 1 x 100F OS-CON CAPACITOR 4613 G09 10ms/DIV SOFT-START CAPACITOR: 0.1F CIN = 2 x 10F CERAMIC CAPACITORS AND 1 x 100F OS-CON CAPACITOR 4613fd For more information www.linear.com/LTM4613 5 LTM4613 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up with 24VIN to 12VOUT at IOUT = 8A, TA = -55C Short-Circuit with 24VIN to 12VOUT at IOUT = 0A IIN 500mA/DIV IOUT 2A/DIV VOUT 5V/DIV IIN 2A/DIV VOUT 5V/DIV VOUT 5V/DIV 4613 G10 Short-Circuit with 24VIN to 12VOUT at IOUT = 8A 20ms/DIV SOFT-START CAPACITOR: 0.1F CIN = 2 x 10F CERAMIC CAPACITORS AND 1 x 100F OS-CON CAPACITOR 20s/DIV COUT = 1 x 47F POSCAP, 1 x 10F CERAMIC CAPACITORS AND 3 x 47F CERAMIC CAPACITORS VIN to VOUT Step-Down Ratio Input Ripple 4613 G11 20s/DIV COUT = 1 x 47F POSCAP, 1 x 10F CERAMIC CAPACITORS AND 3 x 47F CERAMIC CAPACITORS 4613 G12 Output Ripple 36 INPUT VOLTAGE (V) 30 VIN 100mV/DIV AC 24 VOUT 10mV/DIV AC 18 12 4613 G14 1s/DIV VIN = 24V VOUT = 12V AT 8A RESISTIVE LOAD CIN = 2 x 10F CERAMIC CAPACITORS AND 1 x 100F OS-CON CAPACITOR 6 0 3.3 5 7 9 11 OUTPUT VOLTAGE (V) 13 15 1s/DIV 4613 G15 VIN = 24V VOUT = 12V AT 8A RESISTIVE LOAD COUT = 1 x 47F POSCAP 1 x 10F CERAMIC CAPACITOR AND 3 x 47F CERAMIC CAPACITORS 4613 G13 6 4613fd For more information www.linear.com/LTM4613 LTM4613 PIN FUNCTIONS (See Package Description for Pin Assignments) VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at light load or to INTVCC to enable discontinuous mode operation at light load. PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. TRACK/SS (Pin A9): Output Voltage Tracking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins (see the LTM4613 Pin Configuration below). VD (Pins C1 to C7, B6 to B7, A6): Top FET Drain Pins. Add more high frequency ceramic decoupling capacitors between VD and PGND to handle the input RMS current and reduce the input ripple further. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. Leave floating if margining is not used. See the Applications Information section. To parallel LTM4613s, each requires an individual MPGM resistor. Do not tie MPGM pins together. DRVCC (Pins C10, E11, E12): These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves efficiency at the higher input voltages by reducing power dissipation in the module. See the Applications Information section. INTVCC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. fSET (Pin B12): Frequency Set Internally to 600kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency or from this pin to VIN to reduce frequency. See the Applications Information section for frequency adjustment. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTVCC subject to minimum on-time and minimum off-time requirements. See the Applications Information section. VIN A BANK 1 B C D E PGND BANK 2 F G H J VOUT K BANK 3 L M INTVCC PLLIN TRACK/SS RUN COMP MPGM VD TOP VIEW VD SGND fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB 1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm x 15mm x 4.32mm) LTM4613 Pin Configuration For more information www.linear.com/LTM4613 4613fd 7 LTM4613 PIN FUNCTIONS VFB (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT with a 100k 0.5% precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. COMP (Pins A11, D11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. PGOOD (Pin G12): Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires. MARG1 (Pins C11, D12): MSB Logic Input for the Margining Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. 8 RUN (Pins A10, B9): Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be accomplished with a resistor from VIN to this pin that has a 5.1V Zener to ground. Maximum pin voltage is 5V. MTP (Pins J12, K12, L12): No Connect Pins. Leave floating. Used for mounting to PCB. 4613fd For more information www.linear.com/LTM4613 LTM4613 BLOCK DIAGRAM VIN UVLO FUNCTION > 1.9V = ON RA < 1V = OFF MAX = 5V RUN VOUT PGOOD RB 5.1V ZENER COMP 1F INPUT FILTER + VIN 24V TO 36V CIN 100k VD 10F 50V x3 INTERNAL COMP POWER CONTROL SGND M1 2.2H VOUT 12V AT 8A MARG1 MARG0 VFB RFB 5.23k 50k 50k fSET M2 NOISE CANCELLATION 10F 133k + COUT PGND FCB 10k MPGM TRACK/SS CSS PLLIN 50k 4.7F INTVCC DRVCC 4613 F01 = SGND = PGND Figure 1. Simplified Block Diagram DECOUPLING REQUIREMENTS Specifications are at TA = 25C. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS MIN TYP CIN External Input Capacitor Requirement (VIN = 24V to 36V, VOUT = 12V) COUT External Output Capacitor Requirement (VIN = 24V to 36V, VOUT = 12V) MAX UNITS IOUT = 8A 30 100 F IOUT = 8A 100 220 F 4613fd For more information www.linear.com/LTM4613 9 LTM4613 OPERATION Power Module Description The LTM4613 is a standalone nonisolated switch mode DC/DC power supply. It can deliver 8A of DC output current with minimal external input and output capacitors. This module provides a precisely regulated output voltage programmable via one external resistor from 3.3VDC to 15VDC over a wide 5V to 36V input voltage. The typical application schematic is shown in Figure 18. off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input filter and noise cancellation circuitry reduce the noise coupling to inputs and outputs, and ensure the electromagnetic interference (EMI) meets the limits of EN55022 Class B (see Figure 7). Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At light load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous mode (CCM) by setting FCB pin higher than 0.6V. The LTM4613 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 600kHz at full load at 12V output. With current mode control and internal feedback loop compensation, the LTM4613 module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. When the DRVCC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the higher input voltage range. Current mode control provides cycle-by-cycle fast current limiting. Moreover, foldback current limiting is provided in an overcurrent condition when VFB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a 10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned The MPGM, MARG0, and MARG1 pins are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, while the MARG0 and MARG1 select positive or negative margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. APPLICATIONS INFORMATION The typical LTM4613 application circuit is shown in Figure 18. External component selection is primarily determined by the input voltage, the maximum load current and the output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristic curve labeled "VIN to VOUT Step-Down Ratio." Note that additional thermal derating may be applied. See the Thermal Considerations and Output Current Derating section in this data sheet. 10 Output Voltage Programming and Margining The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 100k 0.5% internal feedback resistor connects the VOUT and VFB pins together. Adding a resistor, RFB, from the VFB pin to the SGND pin programs the output voltage. VOUT = 0.6V * 100k +RFB RFB or equivalently, RFB = 100k VOUT -1 0.6V 4613fd For more information www.linear.com/LTM4613 LTM4613 APPLICATIONS INFORMATION Operating Frequency VOUT (V) 3.3 5 6 8 10 12 14 15 RFB (k) 22.1 13.7 11.0 8.06 6.34 5.23 4.42 4.12 The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference offset for margining. A 1.18V reference divided by the RPGM resistor on the MPGM pin programs the current. Calculate VOUT(MARGIN): VOUT(MARGIN) = %VOUT * VOUT 100 Where %VOUT is the percentage of VOUT to be margined, and VOUT(MARGIN) is the margin quantity in volts: V 1.18V RPGM = OUT * *10k 0.6V VOUT(MARGIN) Where RPGM is the resistor value to place on the MPGM pin to ground. The margining voltage, VOUT(MARGIN), will be added or subtracted from the nominal output voltage as determined by the state of the MARG0 and MARG1 pins. See the truth table below: MARG1 MARG0 MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN The operating frequency of the LTM4613 is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. As shown in Figure 2, the frequency is linearly increased with larger output voltages to keep the low output current ripple. Figure 3 shows the inductor current ripple I with different output voltages. In most applications, no additional frequency adjusting is required. If lower output ripple is required, the operating frequency f can be increased by adding a resistor RfSET between fSET pin and SGND, as shown in Figure 19. f= VOUT 1.5 *10 -10 (R fSET ||133k ) [Hz] 1000 800 FREQUENCY (kHz) Table 1. RFB Standard 1% Resistor Values vs VOUT 600 400 200 0 2 4 10 6 12 8 OUTPUT VOLTAGE (V) 16 14 4613 F02 Figure 2. Operating Frequency vs Output Voltage Parallel Operation The LTM4613 device is an inherently current mode controlled device. This allows the paralleled modules to have very good current sharing and balanced thermals on the design. Figure 21 shows a schematic of the parallel design. The voltage feedback equation changes with the variable N as modules are paralleled: 100k N RFB = VOUT -1 0.6V PK-PK INDUCTOR CURRENT RIPPLE (A) 9 8 7 6 5 4 3 VIN = 16V VIN = 24V VIN = 28V VIN = 36V 2 1 0 2 4 6 8 10 12 OUTPUT VOLTAGE (V) 14 16 4613 F03 where N is the number of paralleled modules. Figure 3. Pk-Pk Inductor Current Ripple vs Output Voltage 4613fd For more information www.linear.com/LTM4613 11 LTM4613 APPLICATIONS INFORMATION For output voltages more than 12V, the frequency can be higher than 600kHz, thus reducing the efficiency significantly. Additionally, the minimum off-time of 400ns normally limits the operation when the input voltage is close to the output voltage. Therefore, it is recommended to lower the frequency in these conditions by connecting a resistor (RfSET) from the fSET pin to VIN as shown in Figure 20, where: f= VOUT 3 *R fSET *133k 5 *10-11 R fSET - 2 *133k [Hz] The load current can affect the frequency due to its constant on-time control. If constant frequency is a necessity, the PLLIN pin can be used to synchronize the frequency of the LTM4613 to an external clock subject to minimum on-time and off-time limits, as shown in Figures 21 to 23. Input Capacitors LTM4613 is designed to achieve low input conducted EMI noise due to the fast switching of turn-on and turnoff. Additionally, a high-frequency inductor is integrated into the input line for noise attenuation. VD and VIN pins are available for external input capacitors to form a high frequency filter. As shown in Figure 18, the ceramic capacitors, C1-C3, on the VD pins are used to handle most of the RMS current into the converter, so careful attention is needed for capacitors C1-C3 selection. For a buck converter, the switching duty cycle can be estimated as: V D = OUT VIN Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: IOUT(MAX) ICIN(RMS) = * D* (1-D) In this equation, is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, 12 or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In a typical 8A output application, three very low ESR, X5R or X7R, 10F ceramic capacitors are recommended for C1-C3. This decoupling capacitance should be placed directly adjacent to the module VD pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10F ceramic is typically good for 2A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. To attenuate the high frequency noise, extra input capacitors should be connected to the VIN pads and placed before the high frequency inductor to form the filter. One of these low ESR ceramic input capacitors is recommended to be close to the connection into the system board. A large bulk 100F capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. Output Capacitors The LTM4613 is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical capacitance is 4 x 47F if all ceramic output capacitors are used. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4A load transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. Multiphase operation with multiple LTM4613 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 4 for the normalized output ripple current versus the duty cycle. Figure 4 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each 4613fd For more information www.linear.com/LTM4613 LTM4613 APPLICATIONS INFORMATION Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 19) TYPICAL MEASURED VALUES VENDORS PART NUMBER VENDORS PART NUMBER Murata GRM32ER61C476KEI5L (47F, 16V) Murata GRM32ER71H106K (10F, 50V) Murata GRM32ER61C226KE20L (22F, 16V) TDK C3225X5RIC226M (22F, 16V) CIN (BULK) 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V COUT1 (CERAMIC) 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V COUT2 (BULK) 150F 16V None 150F 16V None 150F 16V None 150F 16V None 150F 16V None 150F 16V None 150F 16V None 150F 16V None VIN (V) 5 5 12 12 24 24 12 12 24 24 36 36 24 24 36 36 DROOP (mV) 84 91 100 100 113 103 109 122 119 122 125 128 178 238 181 244 PK-TO-PK RECOVERY LOAD (mV) TIME (s) STEP (A) 175 50 4 181 40 4 188 50 4 191 40 4 200 50 4 197 40 4 222 60 4 238 50 4 228 60 4 238 50 4 231 60 4 247 50 4 363 150 4 488 90 4 369 150 4 500 90 4 1.00 LOAD STEP SLEW RATE (A/S) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 RFB (k) 22.1 22.1 22.1 22.1 22.1 22.1 13.7 13.7 13.7 13.7 13.7 13.7 5.23 5.23 5.23 5.23 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.95 0.90 0.85 0.80 PEAK-TO-PEAK OUTPUT RIPPLE CURRENT IL CIN (CERAMIC) 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V RATIO = VOUT (V) 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 12 12 12 12 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VO/VIN) 4612 F04 Figure 4. Normalized Output Ripple Current vs Duty Cycle, IL = VOT/LI For more information www.linear.com/LTM4613 4613fd 13 LTM4613 APPLICATIONS INFORMATION phase's inductor ripple current IL is ~5.0A for a 36V to 12V design. The duty cycle is about 0.33. The 2-phase curve shows a ratio of ~0.33 for a duty cycle of 0.33. This 0.33 ratio of output ripple current to the inductor ripple current IL at 5.0A equals 1.65A of output ripple current (IO). cess. The soft-start function can also be used to control the output ramp rise time, so that another regulator can be easily tracked to it. The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. The equation is: ESR * I I O + O VOUT(P-P) 8 * f *N*C N OUT Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. Figure 5 shows an example of coincident tracking where the master regulator's output is divided down with an external resistor divider that is the same as the slave regulator's feedback divider. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for coincident tracking to work. Figure 6 shows the coincident output tracking characteristics. where f is the frequency and N is the number of paralleled phases. This calculation process can be easily accomplished by using LTpowerCADTM. Output Voltage Tracking Fault Conditions: Current Limit and Overcurrent Foldback VIN LTM4613 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady state operation, but also in response to transients. To further limit current in the event of an overload condition, the LTM4613 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. Soft-Start and Tracking The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5A current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference plus or minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: ( ) tSOFTSTART 0.8 * 0.6V VOUT(MARGIN) * CSS 1.5A If the RUN pin falls below 1.5V, then the TRACK/SS pin is reset to allow for proper soft-start control when the regulator is enabled again. Current foldback and forced continuous mode are disabled during the soft-start pro- 14 10F x3 51k VD PGOOD CIN MASTER OUTPUT TRACK CONTROL R1 5.23k PLLIN VOUT RUN VFB COMP FCB INTVCC R2 100k VIN LTM4613 DRVCC SLAVE OUTPUT COUT MARG0 MARG1 fSET MPGM TRACK/SS SGND RFB 5.23k PGND 4613 F05 Figure 5. Coincident Tracking Schematic MASTER OUTPUT SLAVE OUTPUT OUTPUT VOLTAGE TIME 4613 F06 Figure 6. Coincident Output Tracking Characteristics For more information www.linear.com/LTM4613 4613fd LTM4613 APPLICATIONS INFORMATION Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master's TRACK/SS pin. The TRACK/SS pin has a control range from 0 to 0.6V. The master's TRACK/SS pin slew rate is directly equal to the master's output slew rate in Volts/ Time. The equation: MR *100k =R2 SR where MR is the master's output slew rate and SR is the slave's output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R2 is equal to 100k. R1 is derived from equation: R1= 0.6V VFB VFB VTRACK + - 100k RFB R2 The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin. The equation for UVLO threshold: R +R VUVLO = A B *1.5V RB where RA is the top resistor, and RB is the bottom resistor. Refer to Figure 1, Simplified Block Diagram. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point and tracks with margining. COMP Pin where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since R2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R1 is equal to RFB with VFB = VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 5. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R2 can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then R2 = 125k. Solve for R1 to equal 5.18k. Each of the TRACK/SS pins will have the 1.5A current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK/SS pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 100k is used then a 10k value can be used to reduce the TRACK/SS pin offset to a negligible value. RUN Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with 5V logic levels. This pin is the external compensation pin. The module has already been internally compensated for most output voltages. LTpowerCAD is available for other control loop optimization. FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. PLLIN Pin The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of an external clock. The external clock frequency range must be within 30% around the set operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns. The clock high level must be above 2V and clock low level below 0.3V. The PLLIN pin 4613fd For more information www.linear.com/LTM4613 15 LTM4613 APPLICATIONS INFORMATION must be driven from a low impedance source such as a logic gate located close to the pin. During the start-up of the regulator, the phase-locked loop function is disabled. INTVCC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4613 can be directly powered by VIN . The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA * (VIN - 5V) The LTM4613 also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect the DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. Radiated EMI Noise High radiated EMI noise is a disadvantage for switching regulators by nature. Fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. LTM4613 integrates the feature to minimize the radiated EMI noise for applications with low noise requirements. An optimized gate driver for the MOSFET and a noise cancellation network are installed inside the LTM4613 to achieve the low radiated EMI noise. Figure 7 shows a typical example for the LTM4613 to meet the EN55022 Class B radiated emission limit. Thermal Considerations and Output Current Derating In different applications, LTM4613 operates in a variety of thermal environments. The maximum output current is limited by the environment thermal condition. Sufficient cooling should be provided to help ensure reliable operation. When the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-12. They are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation and correlation to hardware evaluation performed on a Module package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD51-12, "Guidelines for Reporting and Using Electronic Package Thermal Information." Many designers may opt to use laboratory equipment and a test vehicle, such as the demo board, to predict the Module regulator's thermal performance in their 70 SIGNAL AMPLITUDE (dB uV/m) 60 50 EN55022B LIMIT 40 30 20 10 0 -10 30 226.2 422.4 613.6 814.3 FREQUENCY (MHz) 1010.0 4613 F07 Figure 7. Radiated Emission Scan with 24VIN to 12VOUT at 8A Measured in 10 Meter Chamber 16 4613fd For more information www.linear.com/LTM4613 LTM4613 APPLICATIONS INFORMATION application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance. Instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one's application-usage, and can be adapted to correlate thermal performance to one's own application. The Pin Configuration section gives four thermal coefficients, explicitly defined in JESD5112. These coefficients are quoted or paraphrased below: * JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as "still air" although natural convection causes the air to move. This value is determined with the part mounted to a 95mm x 76mm PCB with 4 layers. * JCbottom, the thermal resistance from the junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical Module regulator, the bulk of the heat flows out of the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages, but the test conditions do not generally match the user's application. * JCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the Module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of JCbottom, this value may be useful for comparing packages, but the test conditions do not generally match the user's application. * JB, the thermal resistance from the junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the Module regulator and into the board. It is really the sum of the JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package. A graphical representation of the aforementioned thermal resistances is given in Figure 8. Blue resistances are contained within the Module package, whereas green resistances are external to the Module package. JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS JUNCTION-TO-CASE (TOP) RESISTANCE JUNCTION CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION-TO-CASE (BOTTOM) RESISTANCE CASE (BOTTOM)-TO-BOARD RESISTANCE AMBIENT BOARD-TO-AMBIENT RESISTANCE Module REGULATOR 4613 F08 Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients 4613fd For more information www.linear.com/LTM4613 17 LTM4613 APPLICATIONS INFORMATION As a practical matter, it should be clear to the reader that no individual or subgroup of the four thermal resistance parameters defined by JESD51-12, or provided in the Pin Configuration section, replicates or conveys normal operating conditions of a Module regulator. For example, in normal board-mounted applications, never does 100% of the device's total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the package--as the standard defines for JCtop and JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package. Granted, in the absence of a heat sink and airflow, the majority of the heat flow is into the board. Within the LTM4613, be aware that there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity--but also, not ignoring practical realities--an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: 1. Initially, FEA software is used to accurately build the mechanical geometry of the LTM4613 and the specified PCB with all of the correct material coefficients, along with accurate power loss source definitions. 2. This model simulates a software-defined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDECdefined thermal resistance values. 18 3. The model and FEA software is used to evaluate the LTM4613 with heat sink and airflow. 4. Having solved for, and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in this data sheet. The power loss curves in Figures 9 and 10 can be used in coordination with the load current derating curves in Figures 11 to 16 for calculating an approximate JA for the LTM4613. Each figure has three curves that are taken at three different airflow conditions. Graph designation delineates between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 120C maximum. This will maintain the maximum operating temperature below 125C. Table 3 provides the approximate JA for Figures 11 to 16. A complete explanation of the thermal characteristics is provided in the thermal application note, AN110. Safety Considerations The LTM4613 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. 4613fd For more information www.linear.com/LTM4613 LTM4613 7 6 6 5 5 4 3 2 1 0 2 4 6 6 3 2 4 3 0 2 0 4 6 0 10 8 Figure 10. Power Loss at 5VOUT 7 7 6 6 6 LOAD CURRENT (A) 7 LOAD CURRENT (A) 8 3 5 4 3 2 2 OLFM 200LFM 400LFM 55 65 75 95 85 AMBIENT TEMPERATURE (C) 105 65 95 85 AMBIENT TEMPERATURE (C) 55 75 Figure 12. BGA Heat Sink with 36VIN to 5VOUT 3 OLFM 200LFM 400LFM 1 0 105 55 65 75 95 85 AMBIENT TEMPERATURE (C) Figure 14. BGA Heat Sink with 24VIN to 12VOUT 8 8 7 7 6 6 5 4 3 105 4613 F14 Figure 13. No Heat Sink with 24VIN to 12VOUT LOAD CURRENT (A) LOAD CURRENT (A) 4 4613 F13 4613 F12 5 4 3 2 2 OLFM 200LFM 400LFM 1 0 5 2 OLFM 200LFM 400LFM 1 0 105 Figure 11. No Heat Sink with 36VIN to 5VOUT 8 4 75 95 85 AMBIENT TEMPERATURE (C) 4613 F11 8 5 65 4613 F10 Figure 9. Power Loss at 12VOUT and 15VOUT 0 55 LOAD CURRENT (A) 4613 F09 1 OLFM 200LFM 400LFM 1 LOAD CURRENT (A) LOAD CURRENT (A) 5 2 1 10 8 7 4 36VIN TO 15VOUT 24VIN TO 12VOUT 0 8 36VIN TO 5VOUT LOAD CURRENT (A) 7 POWER LOSS (W) POWER LOSS (W) APPLICATIONS INFORMATION 25 35 45 55 OLFM 200LFM 400LFM 1 65 75 85 95 AMBIENT TEMPERATURE (C) 105 0 25 45 55 65 75 85 95 AMBIENT TEMPERATURE (C) 105 4613 F16 4613 F15 Figure 15. No Heat Sink with 36VIN to 15VOUT 35 Figure 16. BGA Heat Sink with 36VIN to 15VOUT For more information www.linear.com/LTM4613 4613fd 19 LTM4613 APPLICATIONS INFORMATION Table 3. 12V and 15V Outputs DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK JA (C/W) Figures 13, 15 24, 36 Figure 9 0 None 10 Figures 13, 15 24, 36 Figure 9 200 None 8 Figures 13, 15 24, 36 Figure 9 400 None 7 Figures 14, 16 24, 36 Figure 9 0 BGA Heat Sink 9.5 Figures 14, 16 24, 36 Figure 9 200 BGA Heat Sink 6.5 Figures 14, 16 24, 36 Figure 9 400 BGA Heat Sink 6.5 VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK JA (C/W) Figure 11 36 Figure 10 0 None 8.5 Figure 11 36 Figure 10 200 None 6.5 Table 4. 5V Output DERATING CURVE Figure 11 36 Figure 10 400 None 6.5 Figure 12 36 Figure 10 0 BGA Heat Sink 8 Figure 12 36 Figure 10 200 BGA Heat Sink 6 Figure 12 36 Figure 10 400 BGA Heat Sink 6 Table 5. Heat Sink Manufacturers HEAT SINK MANUFACTURER PART NUMBER WEBSITE AAVID Thermalloy 375424B00034G www.aavidthermalloy.com Cool Innovations 4-050503P to 4-050508P www.coolinnovations.com Layout Checklist/Example The high integration of LTM4613 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. * Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. * Place high frequency ceramic input and output capacitors next to the VD, PGND and VOUT pins to minimize high frequency noise. * Place a dedicated power ground layer underneath the unit. * Use round corners for the PCB copper layer to minimize the radiated noise. 20 * To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. * Do not put vias directly on pads. * If vias are placed onto the pads, the the vias must be capped. * Interstitial via placement can also be used if necessary. * Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. * Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout. 4613fd For more information www.linear.com/LTM4613 LTM4613 APPLICATIONS INFORMATION VIN CIN CVD CVD SGND GND COUT COUT VOUT 4613 F17 Figure 17. Recommended PCB Layout (LGA Shown, for BGA Use Circle Pads) PULL-UP SUPPLY 5V CLOCK SYNC VIN 22V TO 36V R4 51k R3 51k ON/OFF CIN 10F 50V CERAMIC C4 0.1F C1 TO C3 10F 50V x3 VD VIN PLLIN VOUT PGOOD RUN LTM4613 VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND C5 22pF RFB 5.23k MARGIN CONTROL COUT1 22F 16V + VOUT 12V COUT2 8A 180F 16V REFER TO TABLE 2 R1 392k 5% MARGIN 4613 F18 Figure 18. Typical 22V to 36VIN, 12V at 8A Design 4613fd For more information www.linear.com/LTM4613 21 LTM4613 APPLICATIONS INFORMATION PULL-UP SUPPLY 5V CLOCK SYNC VIN 5V TO 36V R4 51k C1 TO C3 10F 50V x3 R3 51k CIN 10F ON/OFF 50V CERAMIC EXTERNAL 5V SUPPLY IMPROVES EFFICIENCY-- ESPECIALLY FOR HIGH INPUT VOLTAGES VD VIN PLLIN VOUT PGOOD RUN VFB COMP LTM4613 INTVCC FCB C5 22pF RFB 22.1k RfSET 93.1k C4 0.1F SGND + REFER TO TABLE 2 DRVCC fSET TRACK/SS COUT1 22F 6.3V VOUT 3.3V COUT2 8A 180F 6.3V MARG0 MARG1 MPGM PGND MARGIN CONTROL R1 392k 5% MARGIN 4613 F19 Figure 19. Typical 5V to 36VIN, 3.3V at 8A Design with 400kHz Frequency PULL-UP SUPPLY 5V CLOCK SYNC VIN 26V TO 36V R4 51k C1 TO C3 10F 50V x3 R3 51k ON/OFF RfSET 1.32M CIN 10F 50V CERAMIC C4 0.1F VD VIN PLLIN VOUT PGOOD RUN LTM4613 VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND C5 22pF RFB 4.12k MARGIN CONTROL COUT1 22F 16V + VOUT 15V COUT2 5A 220F 16V REFER TO TABLE 2 R1 392k 5% MARGIN 4613 F20 Figure 20. 26V to 36VIN, 15V at 5A Design with 600kHz Frequency 22 4613fd For more information www.linear.com/LTM4613 LTM4613 APPLICATIONS INFORMATION PULL-UP SUPPLY 5V VIN 20V TO 36V R4 51k C2 10F 50V + 2-PHASE OSCILLATOR R5 166k C11 0.1F C5 100F 50V R2 51k C1 10F 50V x3 CLOCK SYNC 0 PHASE VD VIN PLLIN PGOOD VOUT RUN LTM4613 VFB COMP FCB INTVCC DRVCC MARG0 fSET TRACK/SS MARG1 MPGM C7 SGND PGND 0.33F C6 47pF C3 22F 16V R1 392k RFB 2.61k VOUT = 0.6V * C11 10F 50V x3 LTC6908-1 C8 10F 50V 100k/N + RFB RFB CLOCK SYNC 180 PHASE VD VIN PLLIN VOUT PGOOD RUN LTM4613 VFB COMP FCB INTVCC DRVCC fSET TRACK/SS SGND C4 180F 16V MARGIN CONTROL 5% MARGIN V+ OUT1 GND OUT2 SET MOD + VOUT 12V 16A C9 22F 16V MARG0 MARG1 MPGM PGND + C10 180F 16V R6 392k 4613 F21 Figure 21. 2-Phase, Parallel 12V at 16A Design with 600kHz Frequency 4613fd For more information www.linear.com/LTM4613 23 LTM4613 APPLICATIONS INFORMATION PULL-UP SUPPLY 5V VIN 22V TO 36V R4 51k + C5 100F 50V R2 51k C2 10F 50V C7 0.1F C1 10F 50V x3 VD VIN R5 166k C11 0.1F PLLIN PGOOD VOUT RUN LTM4613 VFB COMP FCB INTVCC DRVCC MARG0 fSET TRACK/SS MARG1 MPGM SGND PGND 2-PHASE OSCILLATOR V+ OUT1 GND OUT2 SET MOD CLOCK SYNC 0 PHASE C6 22pF C3 22F 16V + C9 22F 16V + 12V 6A C4 180F 16V MARGIN CONTROL RFB1 5.23k R1 392k 5% MARGIN PULL-UP SUPPLY 5V LTC6908-1 R3 51k R7 51k 12V TRACK C8 10F 50V R8 100k R9 6.34k C11 10F 50V x3 CLOCK SYNC 180 PHASE VD VIN PLLIN VOUT PGOOD RUN LTM4613 VFB COMP FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND C1 22pF C10 180F 16V 10V 6A MARGIN CONTROL R6 392k RFB2 6.34k 4613 F22 Figure 22. 2-Phase, 12V and 10V at 6A Design with 600kHz Frequency and Output Voltage Tracking 24 4613fd For more information www.linear.com/LTM4613 LTM4613 APPLICATIONS INFORMATION 5V VIN 7V TO 36V R2 51k R4 51k C2 10F 50V + C5 100F 50V RfSET1 133k C7 0.15F C1 10F 50V x3 PLLIN VD VIN VOUT PGOOD RUN LTM4613 VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND 2-PHASE OSCILLATOR R5 200k C11 0.1F CLOCK SYNC 0 PHASE C6 22pF C3 22F 6.3V + C9 22F 6.3V + C4 180F 6.3V 5V 8A MARGIN CONTROL R1 392k RFB1 13.7k 5% MARGIN V+ OUT1 GND OUT2 SET MOD 3.3V LTC6908-1 R3 51k R7 51k 5V TRACK C8 10F 50V R8 100k R9 22.1k RfSET2 64.9k C11 10F 50V x3 CLOCK SYNC 180 PHASE VIN VD PLLIN VOUT PGOOD RUN VFB COMP LTM4613 FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND C1 22pF C10 180F 6.3V 3.3V 8A MARGIN CONTROL R6 392k RFB2 22.1k 4613 F23 Figure 23. 2-Phase, 5V and 3.3V at 8A Design with 500kHz Frequency and Output Voltage Tracking 4613fd For more information www.linear.com/LTM4613 25 LTM4613 PACKAGE DESCRIPTION Pin Assignment Tables (Arranged by Pin Function) PIN NAME 26 A1 A2 A3 A4 A5 VIN VIN VIN VIN VIN B1 B2 B3 B4 B5 VIN VIN VIN VIN VIN PIN NAME D1 D2 D3 D4 D5 D6 PGND PGND PGND PGND PGND PGND E1 E2 E3 E4 E5 E6 E7 E8 PGND PGND PGND PGND PGND PGND PGND PGND F1 F2 F3 F4 F5 F6 F7 F8 F9 PGND PGND PGND PGND PGND PGND PGND PGND PGND G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A6 A7 A8 A9 A10 A11 A12 VD INTVCC PLLIN TRACK/SS RUN COMP MPGM B6 B7 B8 B9 B10 B11 B12 VD VD - RUN - MPGM fSET C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 VD VD VD VD VD VD VD - - DRVCC MARG1 MARG0 D7 D8 D9 D10 D11 D12 - - SGND - COMP MARG1 E9 E10 E11 E12 - - DRVCC DRVCC F10 F11 F12 - - VFB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB 4613fd For more information www.linear.com/LTM4613 aaa Z 0.630 0.025 O 133x 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PACKAGE TOP VIEW E 0.6350 0.0000 0.6350 4 1.9050 PAD "A1" CORNER 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 Y For more information www.linear.com/LTM4613 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D // bbb Z 0.27 3.95 MIN 4.22 0.60 NOM 4.32 0.63 15.0 15.0 1.27 13.97 13.97 0.32 4.00 DIMENSIONS 0.37 4.05 0.15 0.10 0.05 MAX 4.42 0.66 DETAIL B A TOTAL NUMBER OF LGA PADS: 133 SYMBOL A b D E e F G H1 H2 aaa bbb eee DETAIL A H1 SUBSTRATE eee S X Y DETAIL B H2 MOLD CAP 0.630 0.025 SQ. 133x aaa Z Z NOTES (Reference LTC DWG # 05-08-1884 Rev A) LGA Package 133-Lead (15mm x 15mm x 4.32mm) F e b 11 b 10 9 7 G 6 5 e PACKAGE BOTTOM VIEW 8 4 3 2 1 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL COMPONENT PIN "A1" 7 ! M L K J H G F E D C B A PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module 3 SEE NOTES C(0.30) PAD 1 7 SEE NOTES LGA 133 1212 REV A PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG Module PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. THE TOTAL NUMBER OF PADS: 133 5. PRIMARY DATUM -Z- IS SEATING PLANE LAND DESIGNATION PER JESD MO-222, SPP-010 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 12 DETAIL A LTM4613 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4613#packaging for the most recent package drawings. 4613fd 27 aaa Z 0.630 0.025 O 133x 4 E PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PIN "A1" CORNER 0.6350 0.0000 0.6350 Y For more information www.linear.com/LTM4613 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D aaa Z NOM 4.92 0.60 4.32 0.75 0.63 15.0 15.0 1.27 13.97 13.97 0.32 4.00 0.37 4.05 0.15 0.10 0.20 0.30 0.15 MAX 5.12 0.70 4.42 0.90 0.66 NOTES DETAIL B PACKAGE SIDE VIEW DIMENSIONS b1 A A2 TOTAL NUMBER OF BALLS: 133 0.27 3.95 MIN 4.72 0.50 4.22 0.60 0.60 DETAIL A SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee H1 SUBSTRATE A1 ddd M Z X Y eee M Z DETAIL B H2 MOLD CAP ccc Z Ob (133 PLACES) // bbb Z (Reference LTC DWG # 05-08-1992 Rev O) Z 28 1.9050 BGA Package 133-Lead (15mm x 15mm x 4.92mm) Z e b 11 10 9 7 G 6 e 5 PACKAGE BOTTOM VIEW 8 4 3 2 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 7 TRAY PIN 1 BEVEL ! PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module M L K J H G F E D C B A 7 SEE NOTES PIN 1 BGA 133 1114 REV O PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG Module PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN "A1" 3 SEE NOTES F b 12 DETAIL A LTM4613 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4613#packaging for the most recent package drawings. 4613fd 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 LTM4613 REVISION HISTORY REV DATE DESCRIPTION A 06/15 Added BGA Package PAGE NUMBER B 09/15 Added LTM4613IY (SnPb) 2 C 07/16 Added MP-Grade 2 D 09/16 Changed Max value of VINTVCC of 5.3 to 5.5 3 2, 28 4613fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTM4613 29 LTM4613 PACKAGE PHOTOGRAPH DESIGN RESOURCES SUBJECT DESCRIPTION Module Design and Manufacturing Resources Design: * Selector Guides * Demo Boards and Gerber Files * Free Simulation Tools Module Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. Manufacturing: * Quick Start Guide * PCB Design, Assembly and Manufacturing Guidelines * Package and Board Level Reliability 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of Module products. Digital Power System Management Linear Technology's family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4612 Lower IOUT Than LTM4613, EN55022B Compliant, 36VIN, 5A Module Regulator 5V VIN 36V, 3.3V VOUT 15V, 15mm x 15mm x 2.82mm (LGA) LTM4606 EN55022B Compliant, 28VIN, 6A Module Regulator 4.5V VIN 28V, 0.5V VOUT 5V, 15mm x 15mm x 2.82mm (LGA), 15mm x 15mm x 3.42mm (BGA) LTM8031 EN55022B Compliant, 36VIN, 1A Module Regulator 3.6V VIN 36V, 0.8V VOUT 10V, 9mm x 15mm x 2.82mm (LGA), 9mm x 15mm x 3.42mm (BGA) LTM8032 EN55022B Compliant, 36VIN, 2A Module Regulator 3.6V VIN 36V, 0.8V VOUT 10V, 9mm x 15mm x 2.82mm (LGA), 9mm x 15mm x 3.42mm (BGA) LTM8033 EN55022B Compliant, 36VIN, 3A Module Regulator 3.6V VIN 36V, 0.8V VOUT 24V, 11.25mm x 15mm x 4.32mm (LGA), 11.25mm x 15mm x 4.92mm (BGA) LTM8028 Low Output Noise, 36VIN, 5A Module Regulator 6V VIN 36V, 0.8V VOUT 1.8V, 15mm x 15mm x 4.92mm (BGA) LTM4601AHV 28VIN, 12A Module Regulator with PLL, Tracking and Margining 4.5V VIN 28V, 0.6V VOUT 5V, 15mm x 15mm x 2.82mm (LGA), 15mm x 15mm x 3.42mm (BGA) LTM4641 38VIN, 10A Module Regulator with Input and Load Protection 4.5V VIN 38V, 0.6V VOUT 6V, 15mm x 15mm x 5.01mm (BGA) LTM8003 FMEA Compliant Pinout, 150C Operation, 40VIN, 3.5A Module Regulator 3.4V VIN 40V, 0.97V VOUT 18V, 6.25mm x 9mm x 3.32mm (BGA) LTM8053 40VIN, 3.5A Module Regulator in 6.25mm x 9mm BGA 3.4V VIN 40V, 0.97V VOUT 15V, 6.25mm x 9mm x 3.32mm (BGA) Package 30 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTM4613 FAX: (408) (408)434-0507 434-0507 www.linear.com/LTM4613 www.linear.com (408) 432-1900 FAX: 4613fd LT 0916 REV D * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 2011