S1D13742 Mobile Graphics Engine
Hardware Functional Specification
Document Number: X63A-A-001-06
Status: Revision 6.2
Issue Date: 2008/07/07
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Revision 6.2
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Hardware Functional Specification S1D13742
Issue Date: 2008/07/07 X63A-A-001-06
Revision 6.2
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Integrated Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 Intel 80 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.2 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.4 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.5 Power And Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 18
5 Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Intel 80 Data Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 LCD Interface Data Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . 22
6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1.2 PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 RESET# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3 Host interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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7.3.1 Intel 80 Interface Timing - 1.8 Volt . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.2 Intel 80 Interface Timing - 3.3 Volt . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.3.3 Definition of Transition Time to Hi-Z State . . . . . . . . . . . . . . . . . . . . . . 34
7.4 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.4.1 TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4.2 TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4.3 18/36-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.1 Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.2 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.3 Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .42
8.4 Setting SYSCLK and PCLK . . . . . . . . . . . . . . . . . . . . . . . . .43
9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
9.3.1 Read-Only Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3.2 Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3.3 Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3.4 Input Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.3.5 Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.3.6 Window Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3.7 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.3.8 Gamma Correction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3.9 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.3.10 General Purpose IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
11 Intel 80, 8-bit Interface Color Formats . . . . . . . . . . . . . . . . . . . . . . . . .75
11.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors . . . . . . . . . . . . . . .75
11.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . . . . . . . . . . . . . . . .76
11.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . . . . . .77
12 Intel 80, 16-bit Interface Color Formats . . . . . . . . . . . . . . . . . . . . . . . . .78
12.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors . . . . . . . . . . . . . . . . . .78
12.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . . . . . . . . . . . . .79
12.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . . . . . . . . . . . . .80
12.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . .81
12.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . .82
13 YUV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
13.1 YUV 4:2:2 with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . . . . . .84
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13.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . 84
13.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . 85
13.4 YUV 4:2:2 with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . . . . . . 86
13.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . 87
13.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . 88
14 Gamma Correction Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . 89
14.1 Gamma Correction Example Programming . . . . . . . . . . . . . . . . . . . 90
15 Display Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
16 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.2 90° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.2.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.3 180° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
16.3.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
16.4 270° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
16.4.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
17 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
17.1 Using the Intel 80 Interface . . . . . . . . . . . . . . . . . . . . . . . . . 98
17.1.1 Register write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
17.1.2 Register read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
17.1.3 New Window Aperture Write procedure . . . . . . . . . . . . . . . . . . . . . . . 100
17.1.4 Opening Multiple Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
17.1.5 Individual Memory Location Reads . . . . . . . . . . . . . . . . . . . . . . . . . . 102
18 Double Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
18.1 Double Buffer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19 Interfacing the S1D13742 and a TFT Panel . . . . . . . . . . . . . . . . . . . . . . 106
19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.1.1 Electrical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
19.1.2 S1D13742 Register Settings for 352x416 TFT Panel . . . . . . . . . . . . . . . . . 107
19.1.3 S1D13742 Register Settings for 800x480 TFT Panel . . . . . . . . . . . . . . . . . 109
19.2 Host Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
19.2.1 Host Bus Timing for 352x416 TFT Panel . . . . . . . . . . . . . . . . . . . . . . . 112
19.2.2 Host Bus Timing for 800x480 TFT Panel . . . . . . . . . . . . . . . . . . . . . . . 113
19.3 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
19.3.1 Panel Timing for 352x416 Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
19.3.2 Panel Timing for 800x480 Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
19.4 Example Play.exe Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . 116
19.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
19.5.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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20 PLL Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 123
20.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 123
21 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
22 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
23 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
23.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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Hardware Functional Specification S1D13742
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1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13742 Embedded Memory LCD
Controller. Included in this document are timing diagrams, AC and DC characteristics,
register descriptions, and power management descriptions. This document is intended for
two audiences: Video Subsystem Designers and Software Developers.
This document is updated as appropriate. Please check the Epson Research and Devel-
opment Website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
documentation@erd.epson.com.
1.2 Overview Description
The S1D13742 is a color LCD graphics controller with an embedded 768K byte display
buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high
performance bandwidth into display memory allowing for fast screen updates.
Products requiring a rotated display image can take advantage of the SwivelView™ feature
which provides hardware rotation of the display memory transparent to the software appli-
cation. Resolutions supported include 800x480 single buffered and 352x416 double
buffered.
The S1D13742 uses a double-buffer architecture to prevent any visual tearing during
streaming video screen updates.
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2 Features
2.1 Integrated Frame Buffer
• Embedded 768K byte SRAM display buffer.
2.2 CPU Interface
• 8/16-bit Intel 80 interface (used for display or register data).
• Chip select is used to select device. When inactive, any input data/command will be
ignored.
2.3 Input Data Formats
• RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp).
• YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp).
Note
All input data must be internally converted to the same format before being stored in the
display buffer. Different data types can not be mixed within a common display buffer.
2.4 Display Support
• Active Matrix TFT interface.
• 18/36-bit interface.
• Supports resolutions up to 800x480.
2.5 Display Modes
• 16/18 bit-per-pixel (bpp) color depths.
• 16 bpp to 18 bpp conversion: Input data can be converted from 16 bpp to 18 bpp in one
of three ways.
1. RGB (5:6:5) msb copying to create new lsb for the Red and Blue components.
This conversion is done prior to storing in memory, as this allows for 16 bpp and
18 bpp input data to be mixed.
2. Gamma Correction Look-Up-Tables: there are three, 64 position, 8-bit wide
LUT’s. The data stored in memory can be used as an index into these tables. The
LUT’s are placed on the display side and therefore do not affect the data stored in
memory.
3. RGB (5:6:5) stored in memory: LUT is by-passed. Copy msb to lsb for red and
blue during the display read from memory.
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2.6 Display Features
• All display writes will be handled by window apertures/position for complete or partial
display updates. All window coordinates are referenced to top left corner of the
displayed image (even in a rotated display, the top-left corner is maintained and no host
side translation need take place).
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
All displayed windows can have independent rotation. No additional programming
necessary when enabling these modes.
• Double-Buffer available to prevent image tearing during streaming input. Resolutions
supported must fit inside 384K bytes (½ of total available display buffer). Typical reso-
lution of 352x416.
• Pixel Doubling: Horizontal and Vertical averaging for smooth doubling of a single
window.
• Pixel Halving: no limitation on number of windows.
2.7 Clock Source
• Internal programmable PLL.
• Single MHz clock input: CLKI.
• CLKI available as CLKOUT (separate CLKOUTEN pin associated with output).
• output state = 0 when disabled.
2.8 Miscellaneous
• Hardware / Software Power Save mode.
• Input pin to Enable/Disable Power Save Mode.
• General Purpose Input/Output pins are available (GPIO[7:0]).
• INT pin associated with selectable GPIO inputs.
• Package: FCBGA 121-pin package
QFP20 144-pin package
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3 Block Diagram
Figure 3-1: Block Diagram
LCD Disp
Pipe
Intel 80
8/16 IF
YUV
Converter
YUV
to
RGB
Gamma
Correction
Memory
Controller
LCD
IF
LCD Ctc
Registers
Clocks Test
Mux
PClk PClk
PClk
MClk
MClk
MClk
Double
MClk
MClk MClk
RegWrClk
Buffer
Controller
Rotation
(Pixel
Halving)
MClk PClk
Data
Control
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4 Pinout Diagram
4.1 Pin-Out
Figure 4-1: S1D13742 FCBGA Pinout (Top View)
ANC NC CLKOUT CLKI MD3 MD4 MD5 MD6 MD7 NC NC
BNC MD2 MD12 CLKOUTEN MD13 MD14 MD15 MD8 MD9 MD10 NC
CMD0 MD11 MD1 IOVDD VSS VSS CS# WE# RD# D/C# DE
DRESET# TE GPIO_INT PLLVDD VCP PLLVSS COREVDD IOVDD HS VS PCLK
ETEST1 TEST2 TESTEN COREVDD VSS VSS VSS PIOVDD NC VD35 VD34
FTEST0 SCANEN CNF0 VSS VSS VSS VSS VD33 VD32 VD31 VD30
GGPIO0 GPIO1 CNF1 PIOVDD VSS VSS COREVDD VD29 VD28 VD27 VD26
HGPIO2 GPIO3 CNF2 IOVDD PIOVDD COREVDD PIOVDD VD25 VD24 VD23 VD22
JGPIO4 GPIO5 PWRSVE VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14
KNC GPIO6 GPIO7 VD13 VD12 VD11 VD10 VD9 VD8 VD7 NC
LNC NC VD6 VD5 VD4 VD3 VD2 VD1 VD0 NC NC
1234567891011
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Figure 4-2: S1D13742 QFP20 Pinout (Top View)
INDEX
PIOVDD
VSS
COREVDD
VSS
DE
HS
VS
PCLK
VD34
VD35
VD33
VD32
VD31
PIOVDD
VSS
VD30
PIOVDD
VSS
VD26
VD27
VD28
VD29
VD24
VD23
VD22
VD15
VD14
COREVDD
VSS
PIOVDD
PIOVDD
GPIO7
VSS
PIOVDD
VSS
COREVDD
VD6
VD5
VD13
VD21
VD4
VD12
VD20
VD3
VD11
VD19
PIOVDD
VD2
VSS
PIOVDD
VD10
VSS
VD18
VD1
VD9
VD17
VD25
VD0
VD8
VD16
VD7
VSS
COREVDD
VSS
VSS
73
72
37
36
1
144
109
108
VSS
COREVDD
VSS
IOVDD
MD0
MD11
GPIO_INT
TE
RESET#
TESTEN
SCANEN
TEST2
TEST1
TEST0
CNF0
VSS
COREVDD
GPIO0
GPIO1
CNF1
CNF2
GPIO3
GPIO2
GPIO4
GPIO5
PWRSVE
GPIO6
VSS
IOVDD
MD2
MD1
MD12
VSS
IOVDD
CLKOUT
CLKOUTEN
VSS
COREVDD
CLKI
VSS
IOVDD
PLLVDD
VCP
PLLVSS
MD13
MD3
MD4
MD14
IOVDD
VSS
CS#
MD15
MD5
MD6
COREVDD
VSS
MD8
WE#
RD#
MD9
MD7
MD10
D/C#
IOVDD
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
123456789101112131415161718192021222324252627282930313233343536
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108 1 07 106 105 10 4 103 102 10 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
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Hardware Functional Specification S1D13742
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Revision 6.2
4.2 Pin Descriptions
Key:
1 H System is IOVDD and PIOVDD (see Section 6, “D.C. Characteristics”).
2 L System is COREVDD (see Section 6, “D.C. Characteristics”).
3 LVCMOS is Low Voltage CMOS (see Section 6, “D.C. Characteristics”).
Pin Types
I = Input
O=Output
IO = Bi-Directional (Input/Output)
P=Power pin
RESET# / Power Save Status
H = High level output
L = Low level output
Hi-Z = High Impedance
Table 4-1: Cell Description
Item Description
HI H System1 LVCMOS3 Input Buffer
HIS H System LVCMOS Schmitt Input Buffer
HID H System LVCMOS Input Buffer with pull-down resistor
HO H System LVCOMOS Output buffer
HB H System LVCMOS Bidirectional Buffer
HBD H System LVCMOS Bidirectional Buffer with pull-down resistor
HB_DSEL H System LVCMOS Bidirectional Buffer with Drive Selector
LIDS L System2 LVCMOS Schmitt Input Buffer with pull-down resistor
LITR L System Transparent Input Buffer
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Revision 6.2
4.2.1 Intel 80 Host Interface
Table 4-2: Host Interface Pin Descriptions
Pin Name Type FCBGA
Pin # QFP
Pin # Cell IO
Voltage RESET#
State
Power
Save
Status Description
MD[15:0] IO
B7,B6,
B5,B3,
C2,B10,
B9, B8,
A9,A8,A7,
A6,A5,B2,
C3,C1
131,127,
124,111,
100,141,
139,136,
140,133,
132,126,
125,109,
110,101
HB IOVDD Hi-Z Hi-Z
Intel 80 Data lines.
• For the S1D13742B00, when the 8-bit
bus interface is selected by CNF1,
MD[15:8] are pulled low by internal
resistors.
• For the S1D13742B01, when the 8-bit
bus interface is selected by CNF1,
MD[15:8] should be connected to VSS.
Note: The Host Data lines can be swapped
(i.e. MD15 = MD0) using the CNF0 pin. For
details, see Section 4.3, “Summary of
Configuration Options” on page 18.
WE# I C8 137 HI IOVDD Input Input This input pin is the Write Enable signal.
RD# I C9 138 HI IOVDD Input Input This input pin is the Read Enable signal.
CS# I C7 130 HI IOVDD Input Input This input pin is the Chip Select signal.
D/C# I C10 142 HI IOVDD Input Input This input pin is used to select between
Intel 80 address and data
TE O D2 98 HO IOVDD L L Tearing Effect: this pin will reflect the
VSYNC, HSYNC or the OR’d combination
status of the display.
GPIO_INT O D3 99 HO IOVDD L Output
This interrupt pin is associated with
selected GPIO pins when configured as
inputs or outputs. Interrupt functionality is
not affected by Power Save. See Section
9.3.10, “General Purpose IO Pins
Registers” on page 72 for operational
description.
RESET# I D1 97 HI IOVDD Input Input Active low input to set all internal registers
to the default state and to force all signals to
their inactive states.
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4.2.2 LCD Interface
Note
The LCD interface requires a separate power rail (PIOVDD) to support the configurable
IO drive. For details, see the CNF2 description in Section 4.3, “Summary of Configura-
tion Options” on page 18.
Note
Input of VD[35:0] is used for production test only.
Table 4-3: LCD Interface Pin Descriptions
Pin Name Type FCBGA
Pin # QFP
Pin # Cell IO
Voltage RESET#
State
Power
Save
Status Description
VD[35:0] IO
E10,E11,
F8,F9,F10,
F11,G8,
G9,G10,
G11,H8,
H9,H10,
H11,J4,J5,
J6,J7,J8,J9,
J10,J11,K4,
K5,K6, K7,
K8,K9,K10,
L3,L4,L5,L6,
L7,L8,L9
13,12,14,15,
16,19,25,24,
23,22,46,26,
27,28,63,60,
57,50,47,43,
29,30,64,61,
58,51,48,44,
42,66,65,62,
59,54,49,45
HB_
DSEL PIOVDD L L
Panel Data bits 35-0. VD[35: 0] are used
for all modes. In 2 pixels/clock mode,
VD[17:0] represent the 1st pixel sent in
a 2 pixel/clock operation.
Note: The Panel Data Lines can be
swapped (i.e. VD23 = VD0) using the
VD Data Swap bit, REG[14h] bit 7.
Note: The VD output driv e is sel ectab le
between 2.5mA and 6.5mA using the
CNF2 pin. For details, see Section 4.3,
“Summary of Configuration Options” on
page 18.
VS O D10 10 HO PIOVDD H L This output pin is the V erti cal Sync
pulse
HS O D9 9 HO PIOVD D H L This output is the Horizontal Sync pul s e
PCLK O D11 11 HO PIOVDD CLKI L This output pin is the Data Cl ock
DE O C11 8 HO PIOVDD L L This outpu t pin is the Data Enable
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S1D13742 Hardware Functional Specification
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Revision 6.2
4.2.3 Clocks
4.2.4 Miscellaneous
Table 4-4: Clock Input Pin Descriptions
Pin Name Type FCBGA
Pin # QFP
Pin # Cell IO
Voltage RESET#
State
Power
Save
Status Description
CLKI I A4 118 HIS IOVDD Input Input MHz in put for PLL opera tion or MHz inp ut if PLL
is bypas s ed
Input frequency range: 1MHz ~ 33MHz
CLKOUT O A3 114 HO IOVDD L CLKI
This output pin represents the CLKI pin if
enabled by CLKOUTEN. When disabled the
output is low.
Note: this output is not affect ed by the various
power save mo des
CLKOUTEN I B4 115 HI IOVDD Input Input This pin enables/disables the CLKOUT pin.
Table 4-5: Miscellaneous Pin Descriptions
Pin Name Type FCBGA
Pin # QFP
Pin # Cell IO
Voltage RESET#
State
Power
Save
Status Description
CNF[2:0] I H3,G3,F
385,86,91 HI IOVDD Input Input
These inputs are used for power-up
configuration. For details, see Section 4.3,
“Summary of Configuration Options” on page
18.
Note: These pins must be connected
directly to IOVDD or VSS.
TESTEN I E3 96 LIDS IOVDD — — Test Enable input used for production test only
This pin should be left unconnected for normal
use.
GPIO[7:0] IO
K3,K2,
J2,J1,
H2,H1,G
2, G1
71,79,81,
82,84,83,
87,88 HBD IOVDD L Pull
Down
Active
These pins are general purpose input/output
pins. These pins have internal pull-down
resistors which can be controlled using
REG[64h].
PWRSVE I J3 80 HI IOVDD Input Input
This pin enables/disables the Standby Power
Save Mode
When unused this pin must be connected to
VSS.
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4.2.5 Power And Ground
TEST[2:0] I E2,E1,F1 94,93,92 HID IOVDD — —
These are Test Function pins and are used for
produ cti on tes t only .
These pins should be left unconnected for
normal operation.
SCANEN I F2 95 HID IOVDD — —
This is the Test Scan Enable input and is used
for production test only.
This pin should be left unconnected for normal
operation.
VCP I D5 122 LITR PLLVDD — —
This is the PLL VCP Test pin and is used for
produ cti on tes t only .
This pin should be left unconnected for normal
operation.
NC —
A1,A2,
A10,A11,
B1,B11,
E9,K1,K
11,L1,L2,
L10,L11
1,2,3,
35,36,
37,72,
73,74,
75,76,
106,107,
108
— — — — These pins are not connected.
Table 4-6: Power And Ground Pin Descriptions
Pin Name Type FCBGA
Pin # QFP
Pin # Cell Description
COREVDD P D7,E4,G7,H6 6,31,40,67,89,
104,117,134 P Core power supply
IOVDD P C4,D8,H4 77,102,113,
120,128,143 P IO power supply for the host interface
PIOVDD P E8,G4,H5,H7 4,17,20,33,38,
52,55,69 P IO power supply for the panel interface
PLLVDD P D4 121 P PLL power supply
PLLVSS P D6 1 23 P GND for PLL
VSS P C5,C6,E5,E6,
E7,F4, F5,F6 ,
F7,G5,G6
5,7,18,21,32,
34,39,41,53,
56,68,70,78,
90,103,105,
112,116,119,
129, 135,144
PGND
Table 4-5: Miscellaneous Pin Descriptions (Continued)
Pin Name Type FCBGA
Pin # QFP
Pin # Cell IO
Voltage RESET#
State
Power
Save
Status Description
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Revision 6.2
4.3 Summary of Configuration Options
These pins are used for power-up configuration and must be connected directly to IOVDD
or VSS. The state of CNF[2:0] may be changed at any time.
Note
When CNF1=0, all Register access is 8-bit only.
When CNF1 =1 (16-bit): All Register access is 8-bit ONLY (the most significant
byte on the data bus is ignored) except the Memory Data Port. Access to the Mem-
ory Data Port is 16-bit.
Table 4-7: Summary of Power-On/Reset Options
Configuration
Input
Power-On/Reset State
1 (connected to IOVDD) 0 (Connected to VSS)
CNF0
Host Data Lines are normal:
If CNF1 = 1, then D15 = D15, etc.
If CNF1 = 0, then D7 = D7, etc.
Host Data Lines are swapped:
If CNF1 = 1, then D15 = D0, etc.
If CNF1 = 0, then D7 = D0, etc.
CNF1 Host Data is 16-bit Host Data is 8-bit
CNF2 PIOVDD output current (IOL2) = 6.5mA PIOVDD output current (IOL2) = 2.5mA
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5 Pin Mapping
5.1 Intel 80 Data Pins
This function is controlled by CNF [1:0]
Table 5-1: S1D13742B00 Intel 80 Data Pin Mapping
Pin Name
16-Bit Data
No Swap
(CNF1=1, CNF0=1)
16-Bit Data
Swapped
(CNF1=1, CNF0=0)
8-Bit Data
No Swap
(CNF1=0, CNF0=1)
8-Bit Data
Swapped
(CNF1=0, CNF0=0)
MD15 MD15 MD0 Pulled Low by
Internal Resistor
Pulled Low by
Internal Resistor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MD8 MD8 MD7 Pulled Low by
Internal Resistor
Pulled Low by
Internal Resistor
MD7 MD7 MD8 MD7 MD0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MD0 MD0 MD15 MD0 MD7
Table 5-2: S1D13742B01 Intel 80 Data Pin Mapping
Pin Name
16-Bit Data
No Swap
(CNF1=1, CNF0=1)
16-Bit Data
Swapped
(CNF1=1, CNF0=0)
8-Bit Data
No Swap
(CNF1=0, CNF0=1)
8-Bit Data
Swapped
(CNF1=0, CNF0=0)
MD15 MD15 MD0 Hi-Z Hi-Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MD8 MD8 MD7 Hi-Z Hi-Z
MD7 MD7 MD8 MD7 MD0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MD0 MD0 MD15 MD0 MD7
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S1D13742 Hardware Functional Specification
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Revision 6.2
5.2 LCD Interface Pin Mapping
Table 5-3: LCD Interface Pin Mapping for Mode 1 and Mode 2
Pin
Name
16bpp 18bpp
Single (18-bit) Double (36-bit) Single (18-bit) Double (36-bit)
Normal Swap Normal Swap Normal Swap Normal Swap
VS Vertical Sync
HS Horizontal Sync
PCLK Pixel Clock
DE Data Enable
VD0B4R4B4R4B0 R5 B0R5
VD1B0R3B0R3B1 R4 B1R4
VD2B1R2B1R2B2 R3 B2R3
VD3B2R1B2R1B3 R2 B3R2
VD4B3R0B3R0B4 R1 B4R1
VD5B4R4B4R4B5 R0 B5R0
VD6G0G5G0G5G0 G5 G0G5
VD7G1G4G1G4G1 G4 G1G4
VD8G2G3G2G3G2 G3 G2G3
VD9G3G2G3G2G3 G2 G3G2
VD10 G4 G1 G4 G1 G4 G1 G4 G1
VD11 G5 G0 G5 G0 G5 G0 G5 G0
VD12 R4 B4 R4 B4 R0 B5 R0 B5
VD13 R0 B3 R0 B3 R1 B4 R1 B4
VD14 R1 B2 R1 B2 R2 B3 R2 B3
VD15 R2 B1 R2 B1 R3 B2 R3 B2
VD16 R3 B0 R3 B0 R4 B1 R4 B1
VD17 R4 B4 R4 B4 R5 B0 R5 B0
VD18 driven 0 driven 0 B4 R4 driven 0 driven 0 B0 R5
VD19 driven 0 driven 0 B0 R3 driven 0 driven 0 B1 R4
VD20 driven 0 driven 0 B1 R2 driven 0 driven 0 B2 R3
VD21 driven 0 driven 0 B2 R1 driven 0 driven 0 B3 R2
VD22 driven 0 driven 0 B3 R0 driven 0 driven 0 B4 R1
VD23 driven 0 driven 0 B4 R4 driven 0 driven 0 B5 R0
VD24 driven 0 driven 0 G0 G5 driven 0 driven 0 G0 G5
VD25 driven 0 driven 0 G1 G4 driven 0 driven 0 G1 G4
VD26 driven 0 driven 0 G2 G3 driven 0 driven 0 G2 G3
VD27 driven 0 driven 0 G3 G2 driven 0 driven 0 G3 G2
VD28 driven 0 driven 0 G4 G1 driven 0 driven 0 G4 G1
VD29 driven 0 driven 0 G5 G0 driven 0 driven 0 G5 G0
VD30 driven 0 driven 0 R4 B4 driven 0 driven 0 R0 B5
VD31 driven 0 driven 0 R0 B3 driven 0 driven 0 R1 B4
VD32 driven 0 driven 0 R1 B2 driven 0 driven 0 R2 B3
VD33 driven 0 driven 0 R2 B1 driven 0 driven 0 R3 B2
VD34 driven 0 driven 0 R3 B0 driven 0 driven 0 R4 B1
VD35 driven 0 driven 0 R4 B4 driven 0 driven 0 R5 B0
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5.3 LCD Interface Data Pins
This function is controlled by REG[14h] bit 7.
Table 5-4: LCD Interface Data Pin Mapping
Pin Name
36-Bit Data
No Swap
REG[14] b7=0
36-Bit Data
Swapped
REG[14] b7=1
18-Bit Data
No Swap
REG[14] b7=0
18-Bit Data
Swapped
REG[14] b7=1
VD35 VD35 VD0 Driven Low Driven Low
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VD18 VD18 VD17 Driven Low Driven Low
VD17 VD17 VD18 VD17 VD0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VD0 VD0 VD35 VD0 VD17
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Revision 6.2
6 D.C. Characteristics
6.1 Absolute Maximum Ratings
6.2 Recommended Operating Conditions
Note
There are no special Power On/Off requirements with respect to sequencing the various
VDD pins. There are also no special requirements for the IO signals, however Inputs
should not be floating. If the input signals were to power up in a valid cycle, the
S1D13742 would decode the cycle.
Table 6-1: Absolute Maximum Ratings
Symbol Parameter Rating Units
Core VDD Core Supply Voltage VSS - 0.3 ~ 2.0 V
PLL VDD PLL Supply Voltage VSS - 0.3 ~ 2.0 V
IO VDD Host IO Supply Voltage COREVDD ~ 4.0 V
PIO VDD Panel IO Supply Voltage COREVDD ~ 4.0 V
VIN Input Signal Voltage VSS - 0.3 ~ IOVDD + 0.3 V
VOUT Output Signal Voltage VSS - 0.3 ~ IOVDD + 0.3 V
IOUT Output Signal Current ±10 mA
Table 6-2: Recommended Operating Conditions
Symbol Parameter Condition Min Typ Max Units
Core VDD Core Supply Voltage VSS = 0 V 1.40 1.50 1.60 V
PLL VDD PLL Supply Voltage VSS = 0 V 1.40 1.50 1.60 V
IO VDD Host IO Supply Voltage VSS = 0 V 1.65 — 3.6 V
PIO VDD Panel IO Supply Voltage VSS = 0 V 1.65 —3.6V
VIN Input Voltage — VSS — IOVDD V
TOPR Operating Temperature — -40 +25 +85 °C
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6.3 Electrical Characteristics
The following characteristics are for: IOVDD. VSS = 0V, TOPR = -40 to +85°C.
Note
1. Typical Operating Current Environment:
352x416 K2 TFT panel with PCLK divide by 4. SYSCLK=48.5MHz from PLL,
PLL Source from 19.2MHz CLKI input. 18bpp memory storage.
COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 1.8V
2. Typical Operating Current Environment:
800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL
Source from 12MHz CLKI input. 16bpp memory storage.
COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 1.8V
Table 6-3: Electrical Characteristics for IOVDD or PIOVDD = 1.8V ± 0.15V
Symbol Parameter Condition Min Typ Max Units
IQALL Quiescent Current CLKI stopped (grounded), Sleep Mode
enabled, all power supplies active — 100 — μA
IPLL PLL Current fPLL = 54MHz — 500 1000 μA
ICORE Operation Peak Current COREVDD Power Pin — — 62 mA
PCORE Core Typical Operating Power
see Note 1
—9.15—mW
PPLL PLL Typical Operating Power — 0.7 — mW
PPIO PIO Typical Operating Power — 2.8 — mW
PHIO HIO Typical Operating Power — 0.018 — mW
PCORE Core Typical Operating Power
see Note 2
— 10.9 — mW
PPLL PLL Typical Operating Power — 0.77 — mW
PPIO PIO Typical Operating Power — 2.124 — mW
PHIO HIO Typical Operating Power — 0.001 — mW
IIZ Input Leakag e Curre nt — -5 — 5 μA
IOZ Output Leakage Current — -5 — 5 μA
IOVOH2 High Level Output Voltage IOVDD = min
IOH2 = -2.5mA IOVDD - 0.40 — IOVDD V
PIOVOH2 High Level Output Voltage PIOVDD = min
IOH2 = -2.5mA PIOVDD - 0.40 — PIOVDD V
PIOVOH4 High Level Output Voltage PIOVDD = min
IOH2 = -6.5mA PIOVDD - 0.40 — PIOVDD V
IOVOL2 Low Level Output Voltage IOVDD = min
IOL2 = 2.5mA VSS — 0.40 V
PIOVOL2 Low Level Output Voltage PIOVDD = min
IOL2 = 2.5mA VSS — 0.40 V
PIOVOL4 Low Level Output Voltage PIOVDD = min
IOL2 = 6.5mA VSS — 0.40 V
IOVIH High Level Input Voltage CMOS Input 1.27 — — V
PIOVIH High Level Input Voltage CMOS Input 1.27 — — V
IOVIL Low Level Input Voltage CMOS Input — — 0.57 V
PIOVIL Low Level Input Voltage CMOS Input — — 0.57 V
IOVT+ Posi tive Trigg er Vol tag e CMOS Schm itt 0.57 — 1.5 6 V
IOVT- Negative Trigger Voltage CMOS Schmitt 0.33 — 1.27 V
IO VHHysteresis Voltage CMOS Schmitt 0.24 — — V
RPU1 Pull-Up Resistance Type1 VI = VSS 40 100 240 k Ω
RPD1 Pull-Down Resistance Type1 VI = VDD 40 100 240 k Ω
RPU2 Pull-Up Resistance Type2 VI = VSS 80 200 480 k Ω
RPD2 Pull-Down Resistance Type2 VI = VDD 80 200 480 k Ω
CIO Pin Capacitance f = 1MHz, VDD = 0V — — 8 pF
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The following characteristics are for: IOVDD. VSS = 0V, TOPR = -40 to +85°C.
Note
1. Typical Operating Current Environment:
352x416 K2 TFT panel with PCLK divide by 4. SYSCLK=48.5MHz from PLL,
PLL Source from 19.2MHz CLKI input. 18bpp memory storage.
COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V
2. Typical Operating Current Environment:
800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL
Source from 12MHz CLKI input. 16bpp memory storage.
COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V
Table 6-4: Electrical Characteristics for IOVDD or PIOVDD = 2.8V ± 0.14V
Symbol Parameter Condition Min Typ Max Units
IQALL Quiescent Current CLKI stopped (grounded),
Sleep Mode enabled, all power
supplies active —120—μA
IPLL PLL Current fPLL = 54MHz — 500 1000 μA
ICORE Operation Peak Current COREVDD Power Pin — — 62 m A
IIZ Input Leakage Current — -5 — 5 μA
IOZ Output Leakage Current — -5 — 5 μA
IOVOH2 High Level Output Voltage IOVDD = min
IOH2 = -3.6mA IOVDD - 0.40 — IOVDD V
PIOVOH2 High Level Output Voltage PIOVDD = min
IOH2 = -3.6mA PIOVDD -
0.40 —PIOVDDV
PIOVOH4 High Level Output Voltage PIOVDD = min
IOH2 = -10.8mA PIOVDD -
0.40 —PIOVDDV
IOVOL2 Low Level Output Voltage IOVDD = min
IOL2 = 3.6mA VSS — 0.40 V
PIOVOL2 Low Level Output Voltage PIOVDD = min
IOL2 = 3.6mA VSS — 0.40 V
PIOVOL4 Low Level Output Voltage PIOVDD = min
IOL2 = 10.8mA VSS — 0.40 V
IOVIH High Level Input Voltage CMOS Input 1.75 — — V
PIOVIH High Level Input Voltage CMOS Input 1.75 — — V
IOVIL Low Level Input Voltage CMOS Input — — 0.70 V
PIOVIL Low Level Input Voltage CMOS Input — — 0. 70 V
IOVT+ Positive Trigger Voltage CMOS Schmitt 0.93 — 2.36 V
IOVT- Negative Trigger Voltage CMOS Schmitt 0.53 — 1.92 V
IO VHHysteresis Voltage CMOS Schmitt 0.40 — — V
RPU1 Pull-Up Resistance Type1 VI = VSS 24 60 144 kΩ
RPD1 Pull-Down Resistance Type1 VI = VDD 24 60 144 kΩ
RPU2 Pull-Up Resistance Type2 VI = VSS 48 120 288 kΩ
RPD2 Pull-Down Resistance Type2 VI = VDD 48 120 28 8 kΩ
CIO Pin Capacitance f = 1MHz, VDD = 0V — — 8 pF
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The following characteristics are for: IOVDD, VSS = 0V, TOPR = -40 to +85°C.
Table 6-5: Electrical Characteristics for IOVDD or PIOVDD = 3.3V ± 0.3V
Symbol Parameter Condition Min Typ Max Units
IQALL Quiescent Current Quiescent Conditions — 160 — μA
IPLL PLL Current fPLL = 54MHz — 500 1 000 μA
ICORE Operation Peak Current COREVDD Power Pin — — 62 m A
IIZ Input Leakage Current — -5 — 5 μA
IOZ Output Leakage Current — -5 — 5 μA
IOVOH2 High Level Output Voltage IOVDD = min
IOH2 = -4.0mA IOVDD - 0.40 — IOVDD V
PIOVOH2 High Level Output Voltage PIOVDD = min
IOH2 = -4.0mA PIOVDD -
0.40 —PIOVDDV
PIOVOH4 High Level Output Voltage PIOVDD = min
IOH2 = -12.0mA PIOVDD -
0.40 —PIOVDDV
IOVOL2 Low Level Output Voltage IOVDD = min
IOL2 = 4.0mA VSS — 0.40 V
PIOVOL2 Low Level Output Voltage PIOVDD = min
IOL2 = 4.0mA VSS — 0.40 V
PIOVOL4 Low Level Output Voltage PIOVDD = min
IOL2 = 12.0mA VSS — 0.40 V
IOVIH High Level Input Voltage CMOS Input 2 .20 — — V
PIOVIH High Level Input Voltage CMOS Input 2.20 — — V
IOVIL Low Level Input Voltage CMOS Input — — 0.80 V
PIOVIL Low Level Input Voltage CMOS Input — — 0.80 V
IOVT+ Positive Trigger Voltage CMOS Schmitt 1.40 — 2.70 V
IOVT- Negative Trigger Voltage CMOS Schmitt 0.60 — 1.80 V
IO VHHysteresis Voltage CMOS Schmitt 0.45 — — V
RPU1 Pull-Up Resistance Type1 VI = VSS 20 50 120 kΩ
RPD1 Pull-Down Resistance Type1 V I = VDD 20 50 120 kΩ
RPU2 Pull-Up Resistance Type2 VI = VSS 40 100 240 kΩ
RPD2 Pull-Down Resistance Type2 V I = VDD 40 1 00 240 kΩ
CIO Pin Capacitance f = 1MHz, VDD = 0V — — 8 pF
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7 A.C. Characteristics
Conditions:
IOVDD = PIOVDD = 1.8V ± 0.15V or 2.8V ± 0.14V
TA = -40° C to 85° C
Trise and Tfall for all inputs except Schmitt and CLKI must be < 50 ns (10% ~ 90%)
Trise and Tfall for all Schmitt must be < 5 ms (10% ~ 90%)
CL = 8pF ~ 30pF (MD[15:0])
CL = 15pF (TE, GPIO_INT, CLKOUT)
CL = 30pF (LCD Panel/GPIO Interface)
7.1 Clock Timing
7.1.1 Input Clocks
Figure 7-1 Clock Input Required (CLKI)
90%
10%
VIH
VIL
t1 t2
t3 t4
tOSC
tOSC tOSC
t5
CLKI
CLKI
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1. t6 = 2*tOSC
2. The input clock period jitter is the displacement relative to the center period (reciprocal of the center
frequency).
3. The input clock cycle jitter is the difference in period between adjacent cycles.
4. The jitter characteristics must satisfy both the t5 and t6 characteristics
5. Input Duty cycle is not critical and can be 40/60
6. The minimum System Clock frequency required for correct operation depends on the cycle length of the
Intel 80 interface. See Section 8.4, “Setting SYSCLK and PCLK” on page 43 for more details.
7.1.2 PLL Clock
The PLL circuit is an analog circuit and is very sensitive to noise on the input clock
waveform or the power supply. Noise on the clock or the supplied power may cause the
operation of the PLL circuit to become unstable or increase the jitter.
Due to these noise constraints, it is highly recommended that the power supply traces or the
power plane for the PLL be isolated from those of other power supplies. Filtering should
also be used to keep the power as clean as possible. The jitter of the input clock waveform
should be as small as possible.
Table 7-1 Clock Input Requirements (CLKI)
Symbol Parameter Min Typ Max Units
fOSC
(see note 6)
Input clock frequency - PLL used for System Clock 1 — 66 MHz
Input clock frequency - CLKI used for System Clock 0 — 68.90 MHz
tOSC Input clock period — 1/fOSC —μs
t1 Input clock pulse width high 0.4tOSC —0.6t
OSC μs
t2 Input clock pulse width low 0.4tOSC —0.6t
OSC μs
t3 Input clock rise time (10% - 90%) — — 5.0 ns
t4 Input clock fall time (90% - 10%) — — 5.0 ns
t5 Input clock period jitter (see notes 2 and 4) -300 300 ps
t6
(see note 1) Input clock cycle jitter (see notes 3 and 4) -300 300 ps
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Figure 7-2: PLL Start-Up Time
1 Refer to Section 8.4, “Setting SYSCLK and PCLK” on page 43.
Table 7-2: PLL Clock Requirements
Symbol Parameter Min Max Units
fPLL PLL output clock frequency 44.26166.95 MHz
tPJref PLL output clock period jitter -3 3 %
tPDuty PLL output clock duty cycle 40 60 %
tPStal PLL output stable time ⎯10 ms
MHz PLL xxMHz Output (xx = 44.26~66.95MHz)
10 ms
Note: PLL minimum frequency = 44.26MHz
PLL maximum frequency = 66.95MHz
The PLL frequency will ramp between the OFF state and the programmed frequency.
To guarantee the lowest possible clock jitter, 10ms is required for stabilization.
Jitter (ns)
Time (ms)
PLL Enable
Lock in time
Lock In Time
Reference Clock
10 ms
PLL Stable
(Based on Intel 80 cycle length. Refer to Section 8.4 for more information)
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7.2 RESET# Timing
Figure 7-3 S1D13742 RESET# Timing
Table 7-3 S1D13742 RESET# Timing
Symbol Parameter Min Max Units
t1 Active Reset Pulse Width 1—CLKI
t1
RESET#
CLKI
tCLKI
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Revision 6.2
7.3 Host interface Timing
7.3.1 Intel 80 Interface Timing - 1.8 Volt
Figure 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt
D/C#
CS#
WE#
MD[15:0] write
RD#
MD[15:0] read
tast
twah
twcs
tcsf
tcsf
twc
twl twh
tdst tdht
trcs
trc
trl
trh
trah
trodh
trdd
Note 1: The D/C# input pin is used to distinguish between Address and Data.
Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment.
The register address will auto-increment in word increments for all register access except the Memory
Data Port. Writes to the Memory Data Port will not increment the register address to support burst data
writes to memory.
trdv trrdz
tch
tch
tw2r
tr2w
tcrdz
tcodh
(Note 1)
(Note 2)
(Note 3)
(Note 3)
Note 3: When CNF1=0, only MD[7:0] are used.
When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses.
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Note
1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum
of trdd after the falling edge of RD#.
2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host
until trrdz after the rising edge of RD#.
3. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all
accesses except for the Memory Data Port when MD[15:0] are used.
Table 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt
Signal Symbol Parameter Min Max Unit Description
D/C# tast Address setup time (read/write) 1 — ns
twah Address hold time (write) 5 — ns
trah Address hold time (read) 29 — ns
CS#
twcs Chip Select setup time (write) twl —ns
trcs Chip Select setup time (read) trl —ns
tch Chip Select hold time (read/write) 0 — ns
tcsf Chip Select Wait time (read/write) 1 — ns
WE#
twc
Register Write cycle 12 — ns
LUT write cycle 2SYSCLK + 1 — ns
Memory write cycle 2SYSCLK + 1 — ns
twl Pulse low durat ion 5 — ns
twh Pulse high durati on twc - twl —ns
tw2r WR# rising edge to RD# falling edge 11 — ns Note 1
RD#
tr2w RD# rising edge to WR# falling edge 26 — ns Note 2
trc Read cycle trl + trh —ns
trl Pulse low duration trdv —ns
trh Pulse high duration for Registers 35 — ns
Pulse high duration for Memory and LUT 1SYSCLK + 26 — ns
MD[15:0]
(Not e 3)
tdst Write data setup tim e 4 — ns
tdht Write data hold time 5 — ns
trodh Read data hold time from RD# rising edge 11 — ns
trrdz RD# rising edge to MD Hi-Z — 31 ns
tcodh Read data hold time from CS# rising edge 1 — ns
tcrdz CS# rising edge to MD Hi-Z — 8 ns
trdv
RD# falling edge to MD valid for Registers — 16 ns CL=30pFRD# falling edge to MD valid for LUT — 4SYSCLK + 26 ns
RD# falling edge to MD valid for Memory — 5SYSCLK + 19 ns
RD# falling edge to MD valid for Registers — 11 ns CL = 8pFRD# falling edge to MD valid for LUT — 4SYSCLK + 21 ns
RD# falling edge to MD valid for Memory — 5SYSCLK + 14 ns
trdd RD# falling edge to MD driven 4 — ns CL=30pF
RD# falling edge to MD driven 3 — ns CL = 8pF
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Revision 6.2
7.3.2 Intel 80 Interface Timing - 3.3 Volt
Figure 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt
D/C#
CS#
WE#
MD[15:0] write
RD#
MD[15:0] read
tast
twah
twcs
tcsf
tcsf
twc
twl twh
tdst tdht
trcs
trc
trl
trh
trah
trodh
trdd
Note 1: The D/C# input pin is used to distinguish between Address and Data.
Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment.
The register address will auto-increment in word increments for all register access except the Memory
Data Port. Writes to the Memory Data Port will not increment the register address to support burst data
writes to memory.
trdv trrdz
tch
tch
tw2r
tr2w
tcrdz
tcodh
(Note 1)
(Note 2)
(Note 3)
(Note 3)
Note 3: When CNF1=0, only MD[7:0] are used.
When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses.
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Note
1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum
of trdd after the falling edge of RD#.
2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host
until trrdz after the rising edge of RD#.
3. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all
accesses except for the Memory Data Port when MD[15:0] are used.
Table 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt
Signal Symbol Parameter Min Max Unit Description
D/C# tast Address setup time (read/write) 1 — ns
twah Address hold time (write) 5 — ns
trah Addr ess hold time (read) 29 — ns
CS#
twcs Chip Select setup time (write) twl —ns
trcs Chip Select setup time (read) trl —ns
tch Chip Select hold time (read/write) 0 — ns
tcsf Chip Select Wait time (read/write) 1 — ns
WE#
twc
Register Write cycle 12 — ns
LUT write cycle 2SYSCLK + 1 — ns
Memory write cycle 2SYSCLK + 1 — ns
twl Pulse low durat ion 5 — ns
twh Pulse high duration twc - twl —ns
tw2r WR# rising edge to RD# falling edge 16 — ns Note 1
RD#
tr2w RD# rising edge to WR# falling edge 26 — ns Note 2
trc Read cycle trl + trh —ns
trl Pulse low duration trdv —ns
trh Pulse high duration for Registers 36 — ns
Pulse high duration for Memory and LUT 1SYSCLK + 26 — ns
MD[15:0]
(Not e 3)
tdst Write data setup time 4 — ns
tdht Write data hold time 5 — ns
trodh Read data hold time from RD# rising edge 11 — ns
trrdz RD# rising edge to MD Hi-Z — 31 ns
tcodh Read data hold time from CS# rising edge 1 — ns
tcrdz CS# rising edge to MD Hi-Z — 8 ns
trdv
RD# falling edge to MD valid for Registers — 11 ns CL=30pFRD# falling edge to MD valid for LUT — 4SYSCLK + 21 ns
RD# falling edge to MD valid for Memory — 5SYSCLK + 14 ns
RD# falling edge to MD valid for Registers — 9 ns CL = 8pFRD# falling edge to MD valid for LUT — 4SYSCLK + 18 ns
RD# falling edge to MD valid for Memory — 5SYSCLK + 11 ns
trdd RD# falling edge to MD driven 3 — ns CL=30pF
RD# falling edge to MD driven 2 — ns CL = 8pF
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7.3.3 Definition of Transition Time to Hi-Z State
Due to the difficulty of Hi-Z impedance measurement for high speed signals, transition
time from High/Low to Hi-Z specified as follows.
•High to Hi-Z delay time: tpHZ, delay time when a gate voltage of final stage of the Pch-MOSFET
turns to 0.8 x IOVDD (Pch-MOSFET is off). Total delay time to Hi-Z is calculated as follows:
Internal logic delay + tpHZ (from High to Hi-Z)
• Low to Hi-Z delay time: tpLZ, delay time when a gate voltage of final stage of the Nch-
MOSFET turns to 0.2 x IOVDD (Nch-MOSFET is off). Total delay time to Hi-Z is
calculated as follows:
Internal logic delay + tpHZ (from High to Hi-Z)
The functional model of a final stage of the Tri state Output Cell is shown in Figure 7-6:
“Definition of transition time to Hi-Z state”.
Figure 7-6: Definition of Transition Time to Hi-Z State
EN
A
X
P
N
IOVDD
VSS
to measure tpHZ
to measur e tpLZ
EN
½IOVDD
tpHZ
0.8 IOVDD
IOVDD
Volt
P
Time
EN
½IOVDD
tpLZ
0.2 IOVDD
IOVDD
Volt
N
Time
Tri s t a te Output Cell
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7.4 Display Interface
The timing parameters required to drive a flat panel display are shown below. Timing
details for each supported panel type are provided in the remainder of this section.
Note
All timing measurements are taken to/from the ½PIOVDD level in the following Dis-
play Interface timing diagrams.
Figure 7-7: Panel Timing Parameters
Note
TS = 1/PCLK
Table 7-6: Panel Timing Parameter Definition and Register Summary
Symbol Description Derived From Units
HDISP Horizontal Display Width (REG[16h] bits 6-0) x 8
Ts
HNDP Horizontal Non-Display Period (REG[18h] bits 6-0)
HPS HS Pulse Start Position REG[22h] bits 6-0
HSW HS Pulse Width (REG[20h] bits 6-0)
VDISP Vertical Display Height (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0)
Lines
(HT)
VNDP Vertical Non-Display Period REG[1Eh] bits 7-0
VPS VS Pulse Start Position REG[26h] bits 7-0
VSW VS Pulse Width REG[24h] bits 6-0
VDISP
HDISP
HPS
DE
HDISP
VSW
HSW
HNDP
VPS
VDISP
VNDP
TE
TE
HT
DE
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7.4.1 TFT Power-On Sequence
Figure 7-8: TFT Power-On Sequence Timing
Table 7-7: TFT Power-On Sequence Timing
Symbol Parameter Min Max Units
t1 Power Save Mode disabled to LCD signals active 020ns
LCD Signals***
Power Save t1
**The LCD power-on sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 0.
***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE.
(REG[56h] bits 1-0)
Mode Enable**
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7.4.2 TFT Power-Off Sequence
Figure 7-9: TFT Power-Off Sequence Timing
Table 7-8: TFT Power-Off Sequence Timing
Symbol Parameter Min Max Units
t1 Power Save Mode enabled to LCD signals low 020ns
LCD Signals***
**The LCD power-off sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 1.
***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE.
t1
Power Save
(REG[56h] bits 1-0)
Mode Enable**
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7.4.3 18/36-Bit TFT Panel Timing
Figure 7-10: 18/36-Bit TFT A.C. Timing
Note
HS, VS, PCLK all have Polarity Select bits via registers
t3
t5
HS
t1
t4
VS
DE
PCLK
320
t2
HS
21
t13
t10 t11 t14
t15 t16
t7
t8
t9 t12
VD[17:0]
Note: 2 pixels/clock Mode
t6
invalid
invalid
n+13-4
1-2
VD[35:0] invalid
invalid
Note: 1 pixel/clock Mode
PCLK
t13
t10 t11 t14
t9 t12
REG[28h] b7=1
REG[28h] b7=0
DE
t17 t18
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1. Ts = pixel clock period
Note
In 36-bit mode, the data is always guaranteed to be launched on the correct edge of
PCLK. In this mode, the frequency of PCLK is ½ the programmed internal value. If it is
desired that HS and VS are always launched on the same edge of PCLK as the data, then
HNDP, HSW, and HSS should be programmed with even values.
Table 7-9: 18/36-Bit TFT A.C. Timing
Symbol Parameter Min Typ Max Units
t1 VS cycle time — VDISP + VNDP — Lines
t2 VS pulse width low — VSW — Lines
t3 VS falling edge to HS falling edge phase difference — HPS — Ts
t4 HS cycle time — HDISP + HNDP — Ts
t5 HS pulse width low — HSW — Ts
t6 HS Falling edge to DE active — HNDP-HPS — Ts
t7 DE pulse width — HDISP — Ts
t8 DE falling edge to HS falling edge — HPS — Ts
t9 PCLK period 1 — — Ts
t10 PCLK pulse width low 0.5 — — Ts
t11 PCLK pulse width high 0.5 — — Ts
t12 HS setup to PCLK active edge 0.5 — — Ts
t13 DE to PCLK rising edge setup time 0.5 — — Ts
t14 DE hold from PCLK active edge 0.5 — — Ts
t15 Data setup to PCLK active edge 0.5 — — Ts
t16 Data hold from PCLK active edge 0.5 — — Ts
t17 DE Stop setup to VS start — VPS — Ts
t18 Vertical Non-Display Period — VNDP — Ts
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8 Clocks
8.1 Clock Descriptions
Figure 8-1: S1D13742 Clock Block Diagram
CLKI
External Clock Source
PLL
Internal PLL Enable Clock Source Select (REG[12h] bit 0)
1
0
SYSCLK
MHz
Glitch Free
Divider
Internal
32
1
2
3
CLKOUTEN
CLKOUT
PCLK Divide Select
(REG[12h] bits 7-3)
•
•
•
1
0
PCLK
External
PCLK
÷
2
Panel Data Width Select
(REG[14h] bit 0)
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8.2 PLL Block Diagram
Figure 8-2: PLL Block Diagram
CP VC
AMON
VCP
VCO
MUX
Loop Filter
RS
CS
CPPFD
M-DividerCLKI
TCK
L-Counter N-Counter
V-Divider
MUX SYSCLK
TOUT
1/32
REFCK
MUX
PFD = Phase Frequency Detector
CP = Charge Pump
VCO = Voltage Controlled Oscillator
Loop Filter = Low Pass Filter
TEST Control = Internal Control Logic
Where:
REG[04h] REG[08h] REG[0Ah]
REG[0Ah]
REG[0Ch]
REG[0Eh]
REG[08h]
PLLCLK
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8.3 Clocks versus Functions
This table lists the internal clocks required for the following S1D13742 functions.
Note
Register access does not require an internal clock as the S1D13742 creates a clock from
the bus cycle alone.
Internal Clock Requirements
Function Internal SYSCLK Internal PCLK
Register Read/Write No No
Memory Read/Write Yes No
Look-Up Table Register
Read/Write Yes No
Power Save No No
LCD Output Yes Yes
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8.4 Setting SYSCLK and PCLK
The period of the system clock, TSYSCLK, must be set such that it falls within the following
range:
For PLL: 14.94ns < TSYSCLK < (TBBC - 0.914) x 0.485 ns
For CLKI: 14.50ns < TSYSCLK < (TBBC - 0.914) x 0.5ns
where TBBC is the minimum back-to-back cycle time of the Intel 80 Interface.
For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 5 x 9.5 =
47.5ns, then:
For PLL: 14.94ns < TSYSCLK < 22.594ns
For CLKI: 14.50ns < TSYSCLK < 23.293ns
Therefore,
For PLL: 44.26MHz < fSYSCLK < 66.95MHz
For CLKI: 42.94MHz < fSYSCLK < 68.96MHz
Care should be taken when setting TSYSCLK so that the desired PCLK frequency, fPCLK,
can be achieved. PCLK is an integer divided version of SYSCLK. The following graph
shows the suggested setting for SYSCLK for a given value of PCLK for TBBC = 47.5ns.
Figure 8-3: Setting of SYSCLK For a Desired PCLK
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
6 8 10 12 14 16 18 20 22 24 26
PCLK Frequency (MHz)
SYSC
L
K
F
r
equ
e
n
cy
(
M
Hz)
SysClk/2
SysClk/3
SysClk/4
SysClk/5
SysClk/6
SysClk/7
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9 Registers
This section discusses how and where to access the S1D13742 registers. It also provides
detailed information about the layout and usage of each register.
Burst data writes to the register space is supported. This applies to all register write access
except the Memory Data Port (REG[48h - 49h]) and the Gamma Correction Table Data
Register [REG[54h]). All writes to these two registers will auto-increment the internal
memory address only.
9.1 Register Mapping
All registers and memory are accessed via the Intel 80 interface. All access is 8-bit only
except for the Memory Data Port (REG[48h - 49h]) which is accessed as 16-bit (if
CNF1=1) or 8-bit (if CNF1=0).
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9.2 Register Set
The S1D13742 registers are listed in the following table.
Table 9-1: S1D13742 Register Set
Register Pg Register Pg
Read-Only Configuration Registers
REG[00h] Revision Code Register 46 REG[02h] Configuration Readback Register 46
Clock Configuration Registers
REG[04h] PLL M-Divider Register 47 REG[06h] PLL Setting Register 0 48
REG[08h] PLL Setting Register 1 48 REG[0Ah ] PLL Set ting Register 2 48
REG[0Ch] PLL Setting Register 3 49 REG[0Eh] PLL Setting Register 4 49
REG[10h] 49 REG[12h] Clock Source Select Register 50
Panel Configuration Registers
REG[14h] Panel Type Register 52 REG[16h] Horizontal Display Width Register (HDISP) 52
REG[18h] Horizontal Non-Display Period Register (HNDP) 52 REG[1Ah] Vertical Display Height Register 0 (VDISP) 53
REG[1Ch] Vertical Display Height Register 1 (VDISP) 53 REG[1Eh] Vertical Non-Display Period Registe r (VNDP) 53
REG[20h] HS Pulse Width Register (HSW) 53 REG[22h] HS Pulse Start Position Register 0 (HPS) 54
REG[24h] VS Pulse Width Register (VSW) 54 REG[26h] VS Pulse Start Position Register 0 (VPS) 54
REG[28h] PCLK Polarity Register 54
Input Mode Register
REG[2Ah] Input Mode Register 55 REG[2Ch] Input YUV/RGB Translate Mode Register 0 57
REG[2Eh] YUV/ RGB T ranslate Mode Register 1 57 REG[30h] U Data Fix Register 59
REG[32h] V Data Fix Register 59
Display Mode Register s
REG[34h] Display Mode Register 60 REG[36h] Special Effects Register 61
Window Settings
REG[38h] Window X Start Position Register 0 64 RE G [3Ah ] Window X Start Position Register 1 64
REG[3Ch] Window Y Start Position Register 0 64 RE G[3Eh ] Window Y Start Position Register 1 64
REG[40h] Window X End Position Register 0 65 REG[42h] Window X End Position Register 1 65
REG[44h] Window Y End Position Register 0 65 REG[46h] Window Y End Position Register 1 65
Memory Access
REG[48h] Memory Data Port Register 0 66 REG[49h] Memory Data Port Register 1 66
REG[4Ah] Memory Read Address Register 0 67 REG[4Ch] Memory Read Address Register 1 67
REG[4Eh] Memory Read A ddress Register 2 67
Gamma Correction Registers
REG[50h] Gamma Correction Enable Register 68 REG[52h] Gamma Correction Table Index Register 69
REG[54h] Gamma Correction Table Data Register 69
Miscellaneous Registers
REG[56h] Power Save Register 70 RE G[58h] Non-Display Period Control / Status Register 70
General Purpose IO Pins Registers
REG[5Ah] Gener al Purpose IO Pins Configuration Register 0 72 REG[5Ch] General Purpose IO Pins Status/Control Register 0 72
REG[5Eh] GPIO Positi ve Edge Interrupt Trigger Register 72 REG[60h] GPIO Negative Edge Interrupt Trigger Register 73
REG[62h] GPIO Interrupt Status Register 73 REG[64h] GPIO Pull Down Control Register 0 73
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9.3 Register Descriptions
All reserved bits must be set to the default value. Writing a non-default value to a reserved
bit may produce undefined results. Bits marked as n/a have no hardware effect. Unless
specified otherwise, all register bits are set to 0 during power-on reset.
9.3.1 Read-Only Configuration Registers
bits 7-2 Product Code bits [5:0]
These are read-only bits that indicates the product code. The product code is 100000b.
bits 1-0 Revision Code bits [1:0]
These are read-only bits that indicates the revision code. The revision code for the
S1D13742B00 is 00b, and for the S1D13742B01 is 01b.
bits 2-0 CNF[2:0] Status
These read-only status bits return the status of the configuration pins CNF[2:0].
REG[00h] Revision Code Register
Default = 80h for S1D13742B00 or 81h for S1D13742B01 Read Only
Product Code bits 5-0 Revision Code bits 1-0
76543210
REG[02h] Configuration Readback Register
Default = xxh Read Only
n/a CNF2 Status CNF1 Status CNF0 Status
7 6 5 4 3210
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9.3.2 Clock Configuration Registers
bit 7 PLL Lock Bit (read only)
When this bit = 0, the PLL output is not stable. In this state R/W access to the display
buffer is prohibited.
When this bit = 1, the PLL output is stable.
bits 5-0 M-Divider bits [5:0]
These bits determine the divide ratio between CLKI and the actual input clock to the PLL
Note
The internal input clock to the PLL (PLLCLK) must be between 1 MHz and 2 MHz. De-
pending on CLKI, these bits will have to be set accordingly.
Note
Values higher then 20h are not allowed.
REG[04h] PLL M-Divider Register
Default = 00h Read/Write
PLL Lock Bit (RO) n/a M-Divider bits 5-0
76543210
Table 9-2: PLL M-Divide Selection
REG[04h] bits 5-0 M-Divide Ratio
0h 1:1
01h 2:1
02h 3:1
03h 4:1
•
•
•
•
•
•
20h 33:1
21h to 3Fh Reserved
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This register must be programmed with the value F8h.
This register must be programmed with the value 80h.
This register must be programmed with the value 28h.
REG[06h] PLL Setting Register 0
Default = 00h Read/Write
PLL Setting Register 0 bits 7-0
76543210
REG[08h] PLL Setting Register 1
Default = 00h Read/Write
PLL Setting Register 1 bits 7-0
76543210
REG[0Ah] PLL Setting Register 2
Default = 00h Read/Write
PLL Setting Register 2 bits 7-0
76543210
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This register must be programmed with the value 00h.
bits 6-0 L-Counter bits [6:0]
These bits are used to configure the PLL Output (in MHz) and must be set according to the
following formula.
PLL Output = (L-Counter +1) x PLLCLK
= LL x PLLCLK
Where:
PLL Output is the desired PLL output frequency (in MHz).
L-Counter is the value of this register (in decimal).
PLLCLK is the internal input clock to the PLL (in MHz).
Please refer to Section 8.4, “Setting SYSCLK and PCLK” on page 43 for restrictions on
PLL Output frequencies.
Writes to this register have no effect on hardware. During Auto Increment, a dummy write
needs to be performed to this register.
REG[0Ch] PLL Setting Register 3
Default = 00h Read/Write
PLL Setting Register 3 bits 7-0
76543210
REG[0Eh] PLL Setting Register 4
Default = 00h Read/Write
n/a L-Counter bits 6-0
76543210
Table 9-3 PLL Setting Example
Target Frequency
(MHz) LL
CLKI
Input Clock
(MHz)
M-Divider
REG[04]
bits 5-0
M-Divide
Ratio
PLLCLK
(MHz) POUT (MHz)
53 53 12 0Bh 12:1 1.0 53
60 60 12 0Bh 12:1 1.0 60
• ••••••
53 53 19.2 12h 19:1 1.0105 53.53
60 60 19.2 12h 19:1 1.0105 60.63
REG[10h]
Default = 00h Read/Write
n/a
76543210
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bits 7-3 PCLK Divide Select bits [5:0]
These bits specify the divide ratio for the panel clock (PCLK).
The clock source for PCLK is SYSCLK.
All resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio.
REG[12h] Clock Source Select Register
Default = 00h Read/Write
PCLK Divide Select bits 4-0 n/a SYSCLK Source
Select
76543210
Table 9-4 PCLK Divide Ratio Selection
REG[0012h] bits 7-3 PCLK Divide Ratio
00h Reserved
01h 2:1
02h 3:1
03h 4:1
04h 5:1
05h 6:1
06h 7:1
07h 8:1
08h 9:1
09h 10:1
0Ah 11:1
0Bh 12:1
0Ch 13:1
0Dh 14:1
0Eh 15:1
0Fh 16:1
10h 17:1
11h 18:1
•
•
•
•
•
•
1Fh 32:1
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bit 0 SYSCLK Source Select
This bit selects the system clock (SYSCLK) source for the controller.
When this bit = 0, the SYSCLK source is the external CLKI input.
When this bit = 1, the SYSCLK source is the internal PLL.
If the PLL is selected as the SYSCLK source (bit 0 = 1), the PLL must be configured using
REG[06h], REG[08h], REG[0Ah], REG[0Ch], REG[0Eh] and REG[10h] before setting
this bit.
Note
To use PLL as system clock source (SYSCLK), Sleep Mode needs to be first enabled,
REG[56h] bit 1 = 1. Once in Sleep Mode, REG[04h] and REG[0Eh] can be changed to
set the desired PLL frequency. Once REG[04h] and REG[0Eh] have been set,
REG[12h] bit 0 can be set to 1b to select PLL as the system clock source. The PLL out-
put will only be active after exiting the Sleep Mode (REG[56h] bit 1 = 0). The PLL out-
put will become stable after 10msec. The display memory or the Gamma Correction
Table must not be accessed before this time. REG[04h] bit 7, the PLL Lock Bit, can be
used to determine if the PLL output is stable.
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9.3.3 Panel Configuration Registers
bit 7 VD Data Swap
When this bit = 0, data lines are normal (i.e.: output pin VD35 = VD35, etc.)
When this bit = 1, data lines are swapped (i.e.: output pin VD35 = VD0, etc.)
Note
The Data swap will always go from the msb to the lsb on the active output pins. See
“LCD Interface Data Pins” on page 21.
bit 0 Panel Data Width
When this bit = 0, the LCD interface is configured as 18-bit.
When this bit = 1, the LCD interface is configured as 36-bit.
bits 6-0 Horizontal Display Width bits [6:0]
These bits specify the LCD panel Horizontal Display Width (HDISP), in 8 pixel resolu-
tion.
Horizontal Display Width in number of pixels = ((REG[16h] bits 6-0) × 8
Note
Minimum value of 8 pixels (register programmed to 1).
bits 6-0 Horizontal Non-Display Period bits [6:0]
These bits specify the horizontal non-display period in pixels. For 36-bit wide panels,
there are 2 pixels per external PCLK.
HNDP is calculated using the following formula.
HNDP = (REG[18h] bits 6-0)
Note
The minimum Horizontal Non-Display Period is 3 Pixels (REG[18h] bits 6-0 = 03h).
HS Start + HS Width <= HNDP
REG[14h] Panel Type Register
Default = 00h Read/Write
VD Data Swap n/a Panel Data Width
76543210
REG[16h] Horizontal Display Width Register (HDISP)
Default = 01h Read/Write
n/a Horizontal Display Period bits 6-0
76543210
REG[18h] Horizontal Non-Display Period Register (HNDP)
Default = 00h Read/Write
n/a Horizontal Non-Display Period bits 6-0
76543210
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REG[1Ch] bits 1-0
REG[1Ah] bits 7-0 Vertical Display Height bits [9:0]
These bits specify the LCD panel Vertical Display Height, in 1 line resolution.
Vertical Display Height in number of lines = (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0)
Note
Minimum value = 1 line
bits 7-0 Vertical Non-Display Period bits [7:0]
These bits specify the Vertical Non-Display Period for panels in 1 line resolution.
Note
Minimum value = 2 lines
bit 7 HS Pulse Polarity
This bit selects the polarity of the horizontal sync signal. This bit is set according to the
horizontal sync signal of the panel.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
bits 6-0 HS Pulse Width bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The
horizontal sync signal is typically HS, depending on the panel type. The minimum value
for these bits is 1.
HS Pulse Width in number of pixels = (REG[20h] bits 6-0)
For 36-bit wide panels, there are 2 pixels per external PCLK.
REG[1Ah] Vertical Display Height Register 0 (VDISP)
Default = 01h Read/Write
Vertical Display Height bits 7-0
76543210
REG[1Ch] Vertical Display Height Register 1 (VDISP)
Default = 00h Read/Write
n/a Vertical Display Height bits 9-8
7 6 5 4 3 210
REG[1Eh] Vertical Non-Display Period Register (VNDP)
Default = 01h Read/Write
Vertical Non-Display Period bits 7-0
76543210
REG[20h] HS Pulse Width Register (HSW)
Default = 00h Read/Write
HS Pulse Polarity HS Pulse Width bits 6-0
76543210
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bits 6-0 HS Pulse Start Position bits [6:0]
These bits specify the start position of the horizontal sync signal with respect to the start of
Horizontal Non-Display period, in 1 pixel resolution. For 36-bit wide panels, there are 2
pixels per external PCLK.
HPS = (REG[22h] bits 6-0)
bit 7 VS Pulse Polarity
This bit selects the polarity of the vertical sync signal. This bit is set according to the ver-
tical sync signal of the panel.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
bits 5-0 VS Pulse Width bits [5:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The ver-
tical sync signal is typically VS, depending on the panel type.
VS Pulse Width in number of lines = REG[24h] bits 5-0
bits 7-0 VS Pulse Start Position bits [7:0]
These bits specify the start position of the vertical sync signal with respect to the start of
Vertical Non-Display period, in 1 line resolution.
VPS is calculated using the following formula:
VPS = (REG[26h] bits 7-0)
bit 7 PCLK Polarity
When this bit = 0, the PCLK outputs data transitions on the rising edge
When this bit = 1, the PCLK outputs data transitions on the falling edge
REG[22h] HS Pulse Start Position Register 0 (HPS)
Default = 00h Read/Write
n/a HS Pulse Start Position bits 6-0
76543210
REG[24h] VS Pulse Width Register (VSW)
Default = 00h Read/Write
VS Pulse Polarity n/a VS Pulse Width bits 5-0
76543210
REG[26h] VS Pulse Start Position Register 0 (VPS)
Default = 00h Read/Write
VS Pulse Start Position bits 7-0
76543210
REG[28h] PCLK Polarity Register
Default = 00h Read/Write
PCLK Polarity n/a
76543210
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9.3.4 Input Mode Register
bit 7 Memory Data Format
This bit determines how the data is stored in memory
When this bit = 0, the data stored in memory is 16 bpp. In this case 18 bpp input data will
be truncated to 16 bpp
When this bit = 1, the data stored in memory is 18 bpp. In this case 16 bpp input data (as
determined by bits 3-0) will be expanded to 18 bpp.
Note
In 18-bpp mode, memory above $A0000h is reserved for 2 bits of each 18 bit pixel.
Therefore the maximum display resolution supported can be calculated as follows:
X x Y x 2 ≤ 640KB
In 16-bpp mode the entire 768K Byte display buffer is available and therefore the maxi-
mum display resolution is X x Y x 2 ≤ 768KB
REG[2Ah] Input Mode Register
Default = 01h Read/Write
Memory Data
Format n/a Input Data Format
76 5 43210
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bits 4-0 Input Data Format bits [4:0]
Note
For YUV 4:2:2 and YUV 4:2:0 settings, the image width must be a multiple of 2 and 4
respectively. For YUV 4:2:0 the height must be a multiple of 2.
For RGB 6:6:6 and RGB 8:8:8 Mode 1, if the image width is odd, the red pixel data in
the last word in each line will be ignored. The red pixel data will need to be re-written
on the following transfer along with the green data. See Figure 12-2: “18 bpp Mode 1(R
6-bit, G 6-bit, B 6-bit), 262,144 colors,” on page 79 or Figure 12-4: “24 bpp Mode 1(R
8-bit, G 8-bit, B 8-bit), 16,777,216 colors,” on page 81.
Note
For further information on Input Data Format and Memory Data Format, see Section 11,
“Intel 80, 8-bit Interface Color Formats” on page 75, Section 12, “Intel 80, 16-bit Inter-
face Color Formats” on page 78 and Section 13, “YUV Timing” on page 83.
Table 9-5: Input Data Type Selection
REG[2Ah] bits 3-0 Input Data Type
0000 Reserved
0001 RGB 5:6:5
0010 RGB 6:6:6 Mode 1
0011 RGB 8:8:8 Mode 1
(LSBs will be truncated to 16 bpp or 18 bpp)
0100 Reserved
0101 Reserved
0110 RGB 6:6:6 Mode 2
0111 RGB 8:8:8 Mode 2
(LSBs will be truncated to 16 bpp or 18 bpp)
1000 YUV 4:2:2
1001 YUV 4:2:0
1010
•
•
•
1111
Reserved
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bit 7 Reserved
The default value for this bit is 0.
bit 6 YUV/RGB Converter Reset
This bit performs a software reset of the YUV to RGB Converter (YRC). To perform a
reset, write a 1 to enter reset, and then write a 0 to return from the reset state.
For Reads:
When this bit = 0, the YRC is not in a reset state.
When this bit = 1, the YRC is in a reset state.
For Writes:
Writing a 0 to this bit returns the YRC from the reset state.
Writing a 1 to this bit initiates a software reset of the YRC.
bits 5-4 UV Fix Select bits [1:0]
These bits control the UV input to the YUV/RGB Converter (YRC).
bits 7-6 Reserved
The default value for these bits is 0.
REG[2Ch] Input YUV/RGB Translate Mode Register 0
Default = 00h Read/Write
Reserved YUV/RGB
Converter Reset UV Fix bits 1-0 n/a
7654
3 2 1 0
Table 9-6: UV Fix Selection
REG[2Ch] bits 5-4 UV Input to the YUV/RGB Converter
00 Original U data, original V data
01 U data = REG[30h] bits 7-0, original V data
10 Original U data, V data = REG[032h] bits 7-0
11 U data = REG[30h] bits 7-0, V data = REG[32h] bits 7-0
REG[2Eh] YUV/RGB Translate Mode Register 1
Default = 05h Read/Write
Reserved YUV Input Data Type Select bits 1-0 Reserved YUV/RGB Transfer Mode bits 2-0
7 6 543210
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bits 5-4 YUV Input Data Type Select bits [1:0]
These bits specify the data type of the YUV input to the YUV to RGB Converter (YRC).
bit 3 Reserved
The default value for this bit is 0.
bits 2-0 YUV/RGB Transfer Mode bits [2:0]
These bits specify the YUV/RGB Transfer mode. Recommended settings are provided for
various specifications.
Table 9-7: YUV Data Type Selection
REG[2Eh] bits 5-4 YRC Input Data Range
00
0 ≤ Y ≤ 255
-128 ≤ U ≤ 127
-128 ≤ V ≤ 127
01
16 ≤ Y ≤ 235
-113 ≤ U ≤ 112
-113 ≤ V ≤ 112
10
0 ≤ Y ≤ 255
0 ≤ U ≤ 255
0 ≤ V ≤ 255
11
16 ≤ Y ≤ 235
16 ≤ U ≤ 240
16 ≤ V ≤ 240
Table 9-8: YUV/RGB Transfer Mode Selection
REG[2Eh] bits 2-0 YUV/RGB Specification
000 Reserved
001 Recommended for ITU-R BT.709
010 Reserved
011 Reserved
100 Recommended for ITU-R BT.470-6 System M
101 (Default) Recommended for all other systems in ITU-R BT.470-6
(Recommended for ITU-R BT.601-5)
110 SMPTE 170M
111 SMPTE 240M(1987)
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bits 7-0 U Data Fix bits [7:0]
These bits only have an effect when the UV Fix Select bits are set to 01 or 11
(REG[2Ch] bits 5-4 = 01 or 11). The U Data Input of the YUV/RGB Converter data is
fixed to the value of these bits.
bits 7-0 V Data Fix bits [7:0]
These bits only have an effect when the UV Fix Select bits are set to 10 or 11
(REG[2Ch] bits 5-4 = 10 or 11). The V Data Input of YUV/RGB Converter data is fixed
to the value of these bits.
REG[30h] U Data Fix Register
Default = 00h Read/Write
U Data Fix bits 7-0
76543210
REG[32h] V Data Fix Register
Default = 00h Read/Write
V Data Fix bits 7-0
76543210
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9.3.5 Display Mode Registers
bit 7 Display Blank
When this bit = 0, the LCD display pipeline is enabled.
When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are
forced to zero (i.e., the screen is blanked).
bits 1-0 Window SwivelView Mode Select bits [1:0]
These bits select different SwivelView™ orientations:
Note
All windows written to the active display can have independent rotation as the rotation
is performed prior to writing to the display buffer.
REG[34h] Display Mode Register
Default = 00h Read/Write
Display Blank n/a SwivelView Mode Select
bits 1-0
76543210
Table 9-9: SwivelView™ Mode Select Options
REG[34h] bits 1-0 SwivelView Orientation
00 0° (Normal)
01 90°
10 180°
11 270°
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bit 7 Window Data Type
When this bit = 0, the data being written from the Host is intended for single buffer only.
When this bit = 1, the data being written from the Host is intended for double buffer oper-
ation.
If the Input Data Format is YUV 4:2:0 (REG[2Ah] bits 4-0 = 1001), the Window Data
Type should not be changed while the YYC is busy (REG[58h] bit 4 = 1).
Note
This bit must be set before the window being written. The window coordinates will be
latched internally to be used by the display pipe during display cycles.
Note
This bit setting is necessary for the Double-Buffer architecture when enabled (bit 6=1)
Note
While double buffering is enabled, the window coordinates should not be modified.
REG[36h] Special Effects Register
Default = 00h Read/Write
Window Data
Type
Double Buffer
Enable n/a Window Pixel Sizing bits 1-0
765 4 3 210
Table 9-10: Window Data Type/Buffer Selection
REG[36h] Bit 7 REG[36h] Bit 6 Use Case
0 0 Single buffered window with no double buffering anywhere on the display.
01
Use this to write a single buffered window while preventing tearing in a
previously defined double buffered window.
10Reserved
1 1 Use this to write data to be double buffered.
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bit 6 Double Buffer Enable
This bit enables the Double Buffer architecture.
When this bit = 0, the double buffer is disabled.
When this bit =1, the double buffer is enabled. This feature is only available if the memory
size resulting from the display size and color depth will fit within the 1/2 the allowable
size for the display buffer.
When enabled, this feature is intended for streaming input sources to prevent visual tear-
ing when updating the display.
Note
This bit must be set before the window being written. The window coordinates will be
latched internally to be used by the display pipe during display cycles.
Note
While double buffering is enabled, the window coordinates should not be modified.
Note
Only one window can be double-buffered. All other windows are single buffered.
Table 9-11: Window Data Type Selection
REG[36h] Bit 7 REG[36h] Bit 6 Use Case
0 0 Single buffered window with no double buffering anywhere on the display.
01
Use this to write a single buffered window while preventing tearing in a
previously defined double buffered window.
10Reserved
1 1 Use this to write data to be double buffered.
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bits 1-0 Window Pixel Sizing bits [1:0]
Note
These bits must be set before the window being written. The window coordinates will be
latched internally to be used by the display pipe during display cycles.
Note
Only 1 active window can be pixel doubled. The pixel doubling design uses horizontal
and vertical averaging for smooth doubling.
Note
The sizing is performed with respect to the top left corner
Figure 9-1: Sizing Example
Note
To turn off pixel doubling for a currently pixel doubled window, either:
1. Overwrite any part of the pixel doubled window with a new window.
2. Write a new pixel doubled window.
Table 9-12: Window Pixel Sizing
REG[36h] bits 1-0 Result
00 No Resizing
01 Pixel Doubling
10 Pixel Halving
11 Reserved
Original Window
Pixel Doubled Window
Pixel Halved Window
Display
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9.3.6 Window Settings
REG[3Ah] bits 1-0
REG[38h] bits 7-0 Window X Start Position bits [9:0]
These bits determine the X start position of the window in relation to the top left corner of
the displayed image. Even in a rotated orientation, the top left corner is still relative to the
displayed image.
Note
When pixel doubling or pixel halving is enabled, these registers should be programmed
with the pre-resized coordinates.
REG[3Eh] bits 1-0
REG[3Ch] bits 7-0 Window Y Start Position bits [9:0]
These bits determine the Y start position of the window in relation to the top left corner of
the displayed image. Even in a rotated orientation, the top left corner is still relative to the
displayed image.
Note
When pixel doubling or pixel halving is enabled, these registers should be programmed
with the pre-resized coordinates.
REG[38h] Window X Start Position Register 0
Default = 00h Read/Write
Window X Start Position bits 7-0
76543210
REG[3Ah] Window X Start Position Register 1
Default = 00h Read/Write
n/a Window X Start Position bits 9-8
76543210
REG[3Ch] Window Y Start Position Register 0
Default = 00h Read/Write
Window Y Start Position bits 7-0
76543210
REG[3Eh] Window Y Start Position Register 1
Default = 00h Read/Write
n/a Window Y Start Position bits 9-8
76543210
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REG[42h] bits 1-0
REG[40h] bits 7-0 Window X End Position bits [9:0]
These bits determine the X end position of the window in relation to the top left corner of
the displayed image. Even in a rotated orientation, the top left corner is still relative to the
displayed image.
Note
When pixel doubling or pixel halving is enabled, these registers should be programmed
with the pre-resized coordinates.
REG[46h] bits 1-0
REG[44h] bits 7-0 Window Y End Position bits [9:0]
These bits determine the Y end position of the window in relation to the top left corner of
the displayed image. Even in a rotated orientation, the top left corner is still relative to the
displayed image.
Note
When pixel doubling or pixel halving is enabled, these registers should be programmed
with the pre-resized coordinates.
REG[40h] Window X End Position Register 0
Default = 00h Read/Write
Window X End Position bits 7-0
76543210
REG[42h] Window X End Position Register 1
Default = 00h Read/Write
n/a Window X End Position bits 9-8
7 6 5 4 3 210
REG[44h] Window Y End Position Register 0
Default = 00h Read/Write
Window Y End Position bits 7-0
76543210
REG[46h] Window Y End Position Register 1
Default = 00h Read/Write
n/a Window Y End Position bits 9-8
7 6 5 4 3 210
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9.3.7 Memory Access
REG[48h] bits 7-0 Memory Data Port bits [7:0]
These specify the lsb for the data word
REG[49h] bits 7-0 Memory Data Port bits [15:8]
These bits specify the msb of the data word.
Note
If CNF1=0 (8-bit interface), REG[49h] is not used.
The data read back from memory will be byte swapped (i.e. if 12 34 56 78 is written to
memory, data read back will be 34 12 78 56).
Note
Burst data writes are supported through this register. Register auto-increment is auto-
matically disabled once reaching this address. All writes to this register will auto-incre-
ment the internal memory address only.
Note
Panel dimension registers must be set before writing any window data.
Note
Upon writing the last pixel in the defined window, this register will automatically point
back to the first pixel in the window. Therefore there is no need to re-initialize the point-
ers.
REG[48h] Memory Data Port Register 0
Default = XXh Read/Write
Memory Data Port bits [7:0]
76543210
REG[49h] Memory Data Port Register 1
Default = XXh Read/Write
Memory Data Port bits [15:8]
76543210
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REG[4Eh] bits 3-0
REG[4Ch] bits 7-0
REG[4Ah] bits 7-0 Memory Read Address bits [19:0]
This register is only used for individual memory location reads.
Individual memory location writes are not supported.
After a completed memory access, this register is incremented automatically.
To perform memory reads:
• perform a register address write to point to this register
• followed by 3 data writes to set-up the memory address
• read the Memory Data Port (REG[48h - 49h])
Note
All write data uses the Memory Data Port and the Window coordinates.
Note
For Intel 80, 16-bit interface, the least significant bit is not used (data is fetched on word
boundaries).
For Intel 80, 8-bit interface, the least significant bit is used (data is fetched on byte
boundaries)
REG[4Ah] Memory Read Address Register 0
Default = 00h Read/Write
Memory Address bits 7-0
76543210
REG[4Ch] Memory Read Address Register 1
Default = 00h Read/Write
Memory Address bits 15-8
76543210
REG[4Eh] Memory Read Address Register 2
Default = 00h Read/Write
n/a Memory Address bit 19-16
76543210
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Revision 6.2
9.3.8 Gamma Correction Registers
Note
Gamma correction is implemented as a look-up table. RGB input data (if the input is
YUV, it will be converted to RGB first) is used to look-up the values from the pro-
grammed tables. The Gamma LUT’s are placed on the display read path and the 18-bit
(6 msb’s from each channel) output goes to the LCD interface.
Note
The Gamma Correction Tables should not be accessed during display period as this will
result in visual anomalies. All updates to the LUT’s should be performed during non-
display period or when the LUT’s are disabled and not in use.
bits 2-1 Look-Up Table Access Mode bits [1:0]
bit 0 Gamma Correction Enable
When this bi t = 0, gamma correc tion is disabl ed and the inp ut da ta will by pass the gamma
correction look-up table. In this case, data stored as 16 bpp will automatically be con-
verted to 18 bpp by copying the Red and Blue msb to create new lsb’s. This will be per-
formed on the display read therefore not requiring any additional memory.
When this bit = 1, gamma correction is enabled and the input data will go through the
gamma correction look-up table.
Note
The Gamma Correction Tables should not be accessed during display period as this will
result in visual anomalies. All updates to the LUT’s should be performed during non-
display period or when the LUT’s are disabled and not in use.
REG[50h] Gamma Correction Enable Register
Default = 00h Read/Write
n/a Look-Up Table Access Mode bits 1-0 Gamma
Correction Enable
7 6 5 4 3210
Table 9-13: Look-Up Table Access Mode
REG[50h] bits 2-1 Description
00 Writing will be done to all Red, Green, & Blue tables.
Reading will be done from Red table.
01 Reading and writing will be done to Red table.
10 Reading and writing will be done to Green table.
11 Reading and writing will be done to Blue table.
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Revision 6.2
bits 5-0 Gamma Correction Table Index bits [5:0]
These bi t s wi ll s pecify the index of th e g amma correction look-up t abl e whic h subsequent
read/write will start at.
bits 7-0 Gamma Correction Table Data bits [7:0]
When writing to Gamma Correction Table Data register, the index to the internal table will
be automatically incremented. For continuous update to the table, the Gamma Correction
Table Index register needs only to be written once. The index will incremented by 1 for
every write to Gamma Correction Table Data register.
Note
Although bits 7 and 6 are programmed to the LUT, they are ignored in the final output
from the LUT.
Note
All 64 positions of each LUT must be written when using auto-increment writes.In the
5:6:5 case, the first 32 positions of the Red and Blue LUT’s will be used.
REG[52h] Gamma Correction Table Index Register
Default = 00h Read/Write
n/a Gamma Correction Table Index bits 5-0
76543210
REG[54h] Gamma Correction Table Data Register
Default = XXh Read/Write
Gamma Correction Table Data bits 5-0
76543210
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Revision 6.2
9.3.9 Miscellaneous Registers
bit 7 PWRSVE Input Pin Function
When this bit = 0, the PWRSVE pin is OR’d with bit 1 (setting either to 1 will enable
Sleep Mode)
When this bit = 1, the PWRSVE pin is OR’d with bit 0 (setting either to 1 will enable
Standby Mode)
bit 1 Sleep Mode Enable/Disable
When this bit = 0, Sleep Mode is disabled (normal operation)
When this bit = 1, Sleep Mode is enabled.
Sleep Mode disables all internal blocks including the PLL. When Sleep Mode is disabled
(low), the PLL requires approximately 10msec lock time before any memory access
should be attempted. The PLL Lock bit, REG[04] bit 7, can be read to verify when the
PLL becomes stable.
bit 0 Standby Mode Enable/Disable
When this bit = 0, Standby Mode is disabled (normal operation)
When this bit = 1, Standby Mode is enabled
Standby Mode disables all internal blocks except the PLL. Using this mode, the chip can
be accessed immediately when Standby is disabled.
Note
Standby Mode can also be enabled/disabled using the PWRSVE input pin.
bit 7 Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Non-Display Period.
When this bit = 1, the LCD panel output is in a Vertical Display Period.
Note
VNDP is defined as time between the last pixel on the last line of one frame to the first
pixel on the first line of the next frame.
REG[56h] Power Save Register
Default = 00h Read/Write
PWRSVE Input
Pin Function n/a Sleep Mode
Enable/Disable
Standby Mode
Enable/Disable
7654321 0
REG[58h] Non-Display Period Control / Status Register
Default = 00h Read/Write
Vertical Non-
Display Period
Status (RO)
Horizontal Non-
Display Period
Status (RO)
VS OR’d with HS
Status
(RO)
YYC Last Line n/a TE Output Pin
Enable TE Output Pin Function Select bits 1-0
76543210
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bit 6 Horizontal Non-Display Period Status
This is a read only status bit
When this bit = 0, the LCD panel output is in a Horizontal Non-Display Period
When this bit = 1, the LCD panel output is in a Horizontal Display Period
Note
HNDP is defined as the time between the last pixel in line n to the first pixel in line n+1.
bit 5 VDP OR’d with HDP Status
This bit is a read only status bit.
When this bit = 0, the LCD panel output is in either the Horizontal or Vertical Non-Dis-
play period.
When this bit = 1, the LCD panel output is in a Display period.
bit 4 YYC Last Line
If the input data type is YUV 4:2:0, this bit will go high 5 MClk’s after the Intel 80 inter-
face has finished writing the last pixel of the current window.
This bit will go low once the YYC is idle. At this point, a new window can be written.
When doing back-to-back window writes with a different dimension or format, and the
first window is YUV 4:2:0, before starting to write the second window, make sure this bit
is low.
Note
It can take up to five SYSCLKs from the rising edge of WE# of the last byte/word of a
frame before this bit is set.
bit 2 TE Output Pin Enable
When this bit = 0, the TE output pin is disabled
When this bit = 1, the TE output pin is enabled.
bits 1-0 TE Output Pin Function Select bits [1:0]
Table 9-14: TE Output Pin Function Select
REG[58h] bits 1-0 TE Output Pin Function
00 Reserved
01 Horizontal Non-Display Period
10 Vertical Non-Display Period
11 HS OR’d with VS
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Revision 6.2
9.3.10 General Purpose IO Pins Registers
bits 7-0 GPIO[7:0] Configuration
When this bit = 0 (normal operation), the associated GPIO is configured as an input pin.
When this bit = 1, the associated GPIO is configured as an output pin.
Note
When configured as an input or an output, the associated GPIO can also be configured
to produce an interrupt (GPIO_INT) based on selectable Interrupt Trigger conditions
(see REG[5E], [60])
bits 7-0 GPIO[7:0] Status
When the associated GPIO is configured as an output, writing a 1 to this bit drives it high
and writing a 0 to this bit drives it low.
When the associated GPIO is configured as an input, a read from this bit returns the raw
status.
Note
When configured as an output, the GPIO_INT pin can still be toggled by writing the ap-
propriate value to this register if enabled by REG[5E],[60].
bits 7-0 GPIO[7:0] Positive Edge Interrupt Trigger
Setting these bits = 1, will enable the associated interrupt.
This bit determines whether the associated GPIO interrupt is triggered on the positive edge
(when the GPIOx pin changes from 0 to 1).
When this bit = 0, the associated GPIO interrupt (GPIO_INT) is disabled.
When this bit = 1, the associated GPIO interrupt (GPIO_INT) is triggered on the positive
edge.
Once triggered, the GPIO_INT pin will toggle from 0 to 1. The GPIO_INT pins is cleared
(non-active state (0)) by clearing the associated GPIO Interrupt Status bit (REG[62])
REG[5Ah] General Purpose IO Pins Configuration Register 0
Default =00h Read/Write
GPIO7
Configuration
GPIO6
Configuration
GPIO5
Configuration
GPIO4
Configuration
GPIO3
Configuration
GPIO2
Configuration
GPIO1
Configuration
GPIO0
Configuration
76543210
REG[5Ch] General Purpose IO Pins Status/Control Register 0
Default = 00h Read/Write
GPIO7 Status GPIO6 Status GPIO5 Status GPIO4 Status GPIO3 Status GPIO2 Status GPIO1 Status GPIO0 Status
76543210
REG[5Eh] GPIO Positive Edge Interrupt Trigger Register
Default = 00h Read/Write
GPIO7 Positive
Edge Interrupt
Trigger
GPIO6 Positive
Edge Interrupt
Trigger
GPIO5 Positive
Edge Interrupt
Trigger
GPIO4 Positive
Edge Interrupt
Trigger
GPIO3 Positive
Edge Interrupt
Trigger
GPIO2 Positive
Edge Interrupt
Trigger
GPIO1 Positive
Edge Interrupt
Trigger
GPIO0 Positive
Edge Interrupt
Trigger
76543210
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bits 7-0 GPIO[7:0] Negative Edge Interrupt Trigger
Setting these bits = 1, will enable the associated interrupt.
This bit determines whether the associated GPIO interrupt is triggered on the negative
edge (when the GPIOx pin changes from 1 to 0).
When this bit = 0, the associated GPIOx interrupt (GPIO_INT) is disabled.
When this bit = 1, the associated GPIOx interrupt (GPIO_INT) is triggered on the negative
edge.
Once triggered, the GPIO_INT pin will toggle from 0 to 1. The GPIO_INT pins is cleared
(non-active state (0)) by clearing the associated GPIO Interrupt Status bit (REG[62])
bits 7-0 GPIO[7:0] Interrupt Status
If configured to generate an Interrupt (GPIO_INT), this status bit will show which GPIO
generated the interrupt. To clear this status bit, you must perform two writes to it: first
write = 1, the second write = 0.
Note
The GPIO_INT pin will also toggle back to 0 upon clearing the status. However, if the
original interrupt condition still exists on the GPIO input pin, the GPIO_INT will imme-
diately set again.
bits 7-0 GPIO[7:0] Pull-down Control
All GPIO pins have internal pull-down resistors. These bits individually control the state
of the pull-down resistors.
When the bit = 0, the pull-down resistor for the associated GPIO pin is inactive.
When the bit = 1, the pull-down resistor for the associated GPIO pin is active.
REG[60h] GPIO Negative Edge Interrupt Trigger Register
Default = 00h Read/Write
GPIO7 Negative
Edge Interrupt
Trigger
GPIO6 Negative
Edge Interrupt
Trigger
GPIO5 Negative
Edge Interrupt
Trigger
GPIO4 Negative
Edge Interrupt
Trigger
GPIO3 Negative
Edge Interrupt
Trigger
GPIO2 Negative
Edge Interrupt
Trigger
GPIO1 Negative
Edge Interrupt
Trigger
GPIO0 Negative
Edge Interrupt
Trigger
76543210
REG[62h] GPIO Interrupt Status Register
Default = 00h Read/Write
GPIO7 Interrupt
Status
GPIO6 Interrupt
Status
GPIO5 Interrupt
Status
GPIO4 Interrupt
Status
GPIO3 Interrupt
Status
GPIO2 Interrupt
Status
GPIO1 Interrupt
Status
GPIO0 Interrupt
Status
76543210
REG[64h] GPIO Pull Down Control Register 0
Default = FFh Read/Write
GPIO7 Pull-down
Control GPIO6 Pull-down
Control GPIO5 Pull-down
Control GPIO4 Pull-down
Control GPIO3 Pull-down
Control GPIO2 Pull-down
Control GPIO1 Pull-down
Control GPIO0 Pull-down
Control
76543210
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Revision 6.2
10 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
Where:
fPCLK = PClk frequency (Hz)
HT = Horizontal Total
= Horizontal Display Width + Horizontal Non-Display Period
VT = Vertical Total
= Vertical Display Height + Vertical Non-Display Period
Note
For definitions of panel timing parameters, see Section 7.4, “Display Interface” on page
35.
FrameRate fPCLK
HT()VT()×
--------------------------------
=
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Revision 6.2
11 Intel 80, 8-bit Interface Color Formats
11.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors
Figure 11-1: 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors
Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for
Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data.
CS#
D/C#
WR#
RD#
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R1, Bit 4
R1, Bit 3
R1, Bit 2
R1, Bit 1
R1, Bit 0
G1, Bit 5
G1, Bit 4
G1, Bit 3
G1, Bit 2
G1, Bit 1
G1, Bit 0
B1, Bit 4
B1, Bit 3
B1, Bit 2
B1, Bit 1
B1, Bit 0
R2, Bit 4
R2, Bit 3
R2, Bit 2
R2, Bit 1
R2, Bit 0
G2, Bit 5
G2, Bit 4
G2, Bit 3
G2, Bit 2
G2, Bit 1
G2, Bit 0
B2, Bit 4
B2, Bit 3
B2, Bit 2
B2, Bit 1
B2, Bit 0
R1, Bit 1
PixelPixel n
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11.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors
Figure 11-2: 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors
Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0.
CS#
D/C#
WRX
RD#
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R1, Bit 4
R1, Bit 3
R1, Bit 2
R1, Bit 0
R1, Bit 1
R1, Bit 5
R1, Bit 3
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
B1, Bit 4
B1, Bit 2
B1, Bit 0
B1, Bit 1
B1, Bit 5
B1, Bit 3
R2, Bit 4
R2, Bit 2
R2, Bit 0
R2, Bit 1
R2, Bit 5
R2, Bit 3
Pixel n + 1Pixel n
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11.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors
Figure 11-3: 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors
Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0.
CS#
D/C#
WR#
RD#
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R1, Bit 4
R1, Bit 2
R1, Bit 0
R1, Bit 1
R1, Bit 5
R1, Bit 3
R1, Bit 7
R1, Bit 6
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
G1, Bit 7
G1, Bit 6
B1, Bit 4
B1, Bit 2
B1, Bit 0
B1, Bit 1
B1, Bit 5
B1, Bit 3
B1, Bit 7
B1, Bit 6
R2, Bit 4
R2, Bit 2
R2, Bit 0
R2, Bit 1
R2, Bit 5
R2, Bit 3
R2, Bit 7
R2, Bit 6
Pixel n + 1Pixel n
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12 Intel 80, 16-bit Interface Color Formats
12.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors
Figure 12-1: 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors
Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for
Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data.
Pixel n + 2Pixel n Pixel n + 1
CS#
D/C#
WR#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
R1, Bit 4
R1, Bit 3
R1, Bit 2
R1, Bit 0
R1, Bit 1
R2, Bit 4
R2, Bit 3
R2, Bit 2
R2, Bit 0
R2, Bit 1
R3, Bit 4
R3, Bit 3
R3, Bit 2
R3, Bit 0
R3, Bit 1
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
G2, Bit 4
G2, Bit 2
G2, Bit 0
G2, Bit 1
G2, Bit 5
G2, Bit 3
G3, Bit 4
G3, Bit 2
G3, Bit 0
G3, Bit 1
G3, Bit 5
G3, Bit 3
B1, Bit 4
B1, Bit 3
B1, Bit 2
B1, Bit 0
B1, Bit 1
B2, Bit 4
B2, Bit 3
B2, Bit 2
B2, Bit 0
B2, Bit 1
B3, Bit 4
B3, Bit 3
B3, Bit 2
B3, Bit 0
B3, Bit 1
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12.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors
Figure 12-2: 18 bpp Mode 1(R 6-bit, G 6-bit, B 6-bit), 262,144 colors
Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0.
Pixel n Pixel n + 1
CS#
D/C#
WR#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
R1, Bit 4
R1, Bit 2
R1, Bit 0
R1, Bit 1
R1, Bit 5
R1, Bit 3
G2, Bit 4
G2, Bit 2
G2, Bit 0
G2, Bit 1
G2, Bit 5
G2, Bit 3
B1, Bit 4
B1, Bit 2
B1, Bit 0
B1, Bit 1
B1, Bit 5
B1, Bit 3
R2, Bit 4
R2, Bit 2
R2, Bit 0
R2, Bit 1
R2, Bit 5
R2, Bit 3
B2, Bit 4
B2, Bit 2
B2, Bit 0
B2, Bit 1
B2, Bit 5
B2, Bit 3
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
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12.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors
Figure 12-3: 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors
Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0.
Pixel n Pixel n + 1
CS#
D/C#
WR#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
B2, Bit 4
B2, Bit 2
B2, Bit 0
B2, Bit 1
B2, Bit 5
B2, Bit 3
R2, Bit 4
R2, Bit 2
R2, Bit 0
R2, Bit 1
R2, Bit 5
R2, Bit 3
R1, Bit 4
R1, Bit 2
R1, Bit 0
R1, Bit 1
R1, Bit 5
R1, Bit 3
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12.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors
Figure 12-4: 24 bpp Mode 1(R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors
Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0.
CS#
D/C#
WR#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
R1, Bit 4
R1, Bit 2
R1, Bit 0
R1, Bit 1
R1, Bit 5
R1, Bit 3
R1, Bit 7
R1, Bit 6
G2, Bit 4
G2, Bit 2
G2, Bit 0
G2, Bit 1
G2, Bit 5
G2, Bit 3
G2, Bit 7
G2, Bit 6
B1, Bit 4
B1, Bit 2
B1, Bit 0
B1, Bit 1
B1, Bit 5
B1, Bit 3
B1, Bit 7
B1, Bit 6
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
G1, Bit 7
G1, Bit 6
R2, Bit 4
R2, Bit 2
R2, Bit 0
R2, Bit 1
R2, Bit 5
R2, Bit 3
R2, Bit 7
R2, Bit 6
B2, Bit 4
B2, Bit 2
B2, Bit 0
B2, Bit 1
B2, Bit 5
B2, Bit 3
B2, Bit 7
B2, Bit 6
Pixel n Pixel n + 1
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12.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors
Figure 12-5: 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors
Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0.
CS#
D/C#
WR#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
G1, Bit 4
G1, Bit 2
G1, Bit 0
G1, Bit 1
G1, Bit 5
G1, Bit 3
G1, Bit 7
G1, Bit 6
R1, Bit 4
R1, Bit 2
R1, Bit 0
R1, Bit 1
R1, Bit 5
R1, Bit 3
R1, Bit 7
R1, Bit 6
B1, Bit 4
B1, Bit 2
B1, Bit 0
B1, Bit 1
B1, Bit 5
B1, Bit 3
B1, Bit 7
B1, Bit 6
R2, Bit 4
R2, Bit 2
R2, Bit 0
R2, Bit 1
R2, Bit 5
R2, Bit 3
R2, Bit 7
R2, Bit 6
Pixel n Pixel n + 1
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13 YUV Timing
Format Definition
• The number of pixels per line is always even
•The YC
BCR colorspace is defined in ITU-R BT601.4
• YUV 4:2:2 format
U11Y11V11Y12U13Y13V13Y14...
• YUV 4:2:0 format
Odd Line: UY11Y12...
Even Line: VY21Y22...
Note
When a window is setup for YUV data, the data must always alternate between odd and
even lines, starting with an odd line.
Figure 13-1: YUV Format Definition
Odd Line
Even Line
YUV 4:2:2
Y13 Y14
Y24
U/V
Y23
YUV 4:2:0
Y11 Y12
Y22
U/V
Y21
Odd Line
Even Line
(must start with this line)
U11
Y12
U13
Y14
Y11 Y13
V11 V13
U21
Y22
U23
Y24
Y21 Y23
V21 V23
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13.1 YUV 4:2:2 with Intel 80, 8-bit Interface
Figure 13-2: YUV 4:2:2 with Intel 80, 8-bit Interface
13.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface
Figure 13-3: YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface
D/C#
WR#
Bit0
CS#
RD#
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
UY14
V
Y13
U
Y12
V
Y11
(11,12)(11,12)(13,14)(13,14)
RESET#
D/C#
WR#
Bit0
CS#
RD#
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
U
(11,12,21,22)
Y15
U
(15,16,25,26)
Y14
Y13
U
(13,14,23,24)
Y12
Y11
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
RESET#
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13.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface
Figure 13-4: YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface
D/C#
WR#
Bit0
CS#
RD#
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
V
(11,12,21,22)
Y25
V
(15,16,25,26)
Y24
Y23
V
(13,14,23,24)
Y22
Y21
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
RESET#
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13.4 YUV 4:2:2 with Intel 80, 16-bit Interface
Figure 13-5: YUV 4:2:2 with Intel 80, 16-bit Interface
Bit8
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
U11V17
U17
V15
U15
V13
U13
V11
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Y11Y18
Y17
Y16
Y15
Y14
Y13
Y12
D/C#
WR#
CS#
RESET#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
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13.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface
Figure 13-6: YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface
Bit8
Bit
15
Bit14
Bit13
B
it12
Bit
11
B
it10
Bit
9
U
(11,12
,
21,
2
2)
Y17
Y
16
U
(15,16,25,26)
Y
1
3
Y
1
2
Bit
0
B
it7
Bit
6
Bit5
Bit
4
Bit3
Bit
2
B
it1
Y1
1
Y18
U
(17,1
8
,27,2
8
)
Y
15
Y
1
4
U
(13,14,23,24))
D/C#
WR#
CS#
RESET#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
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13.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface
Figure 13-7: YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface
Bit8
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
V
(11,12,21,22)
Y27
Y26
V
(15,16,25,26)
Y23
Y22
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Y21Y28
V
(17,18,27,28)
Y25
Y24
V
(13,14,23,24)
D/C#
WR#
CS#
RESET#
RD#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
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14 Gamma Correction Look-Up Table Architecture
The following figures are intended to show the display data output path only.
The following diagram shows the architecture for 18 bpp using LUT.
Figure 14-1: Look-Up Table Architecture
Red Look-Up Table 64x8
00 0000
00 0001
6-bit Red Data
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111
00 0000
00 0001
6-bit Green Data
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111
00 0000
00 0001
6-bit Blue Data
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111
Green Look-Up Table 64x8
00
01
02
03
04
05
06
07
38
39
3A
3B
3C
3D
3E
3F
Blue Look-Up Table 64x8
00
01
02
03
04
05
06
07
38
39
3A
3B
3C
3D
3E
3F
00
01
02
03
04
05
06
07
38
39
3A
3B
3C
3D
3E
3F
Note:
Only the 6 LSB’s from each table are used to construct an 18-bit pixel.
6-bit Red Data
from Display Buffer
6-bit Green Data
from Display Buffer
6-bit Blue Data
from Display Buffer
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14.1 Gamma Correction Example Programming
• Disable the LUT’s or ensure you are in a non-display period when accessing to avoid
visual anomalies.
• Write register “address” for Gamma Correction Enable Register.
• Write data to set LUT Access Mode.
• Write data to set LUT Index to “x” (auto-increment is already enabled therefore the
LUT Index Register address does not have to be written).
• Write data to Gamma Correction Data Register (data value for Index “x”).
• Write data to Gamma Correction Data Register (data value for Index “x+1”).
• Continue until complete (64 positions). Even in the case of 5:6:5, all 64 positions of
each RGB LUT must be programmed when using the auto-increment method.
• Enable Gamma Correction.
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15 Display Data Format
Table 15-1: 36-Bi t Data Format (Non-S wapped)
Cycle Count
1 2 3 ... n
VD35 R15R35R55... Rn+15
VD34 R14R34R54... Rn+14
VD33 R13R33R53... Rn+13
VD32 R12R32R52... Rn+12
VD31 R11R31R51... Rn+11
VD30 R10R30R50... Rn+10
VD29 G15G35G55... Gn+15
VD28 G14G34G54... Gn+14
VD27 G13G33G53... Gn+13
VD26 G12G32G52... Gn+12
VD25 G11G31G51... Gn+11
VD24 G10G30G50... Gn+10
VD23 B15B35B55... Bn+15
VD22 B14B34B54... Bn+14
VD21 B13B33B53... Bn+13
VD20 B12B32B52... Bn+12
VD19 B11B31B51... Bn+11
VD18 B10B30B50... Bn+10
VD17 R05R25R45... Rn5
VD16 R04R24R44... Rn4
VD15 R03R23R43... Rn3
VD14 R02R22R42... Rn2
VD13 R01R21R41... Rn1
VD12 R00R20R40... Rn0
VD11 G05G25G45... Gn5
VD10 G04G24G44... Gn4
VD9 G03G23G43... Gn3
VD8 G02G22G42... Gn2
VD7 G01G21G41... Gn1
VD6 G00G20G40... Gn0
VD5 B05B25B45... Bn5
VD4 B04B24B44... Bn4
VD3 B03B23B43... Bn3
VD2 B02B22B42... Bn2
VD1 B01B21B41... Bn1
VD0 B00B20B40... Bn0
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Table 15-2: 36-Bit Data Format (Swapped)
Cycle Count
1 2 3 ... n
VD35 B00B20B40... Bn0
VD34 B01B21B41... Bn1
VD33 B02B22B42... Bn2
VD32 B03B23B43... Bn3
VD31 B04B24B44... Bn4
VD30 B05B25B45... Bn5
VD29 G00G20G40... Gn0
VD28 G01G21G41... Gn1
VD27 G02G22G42... Gn2
VD26 G03G23G43... Gn3
VD25 G04G24G44... Gn4
VD24 G05G25G45... Gn5
VD23 R00R20R40... Rn0
VD22 R01R21R41... Rn1
VD21 R02R22R42... Rn2
VD20 R03R23R43... Rn3
VD19 R04R24R44... Rn4
VD18 R05R25R45... Rn5
VD17 B10B30B50... Bn+10
VD16 B11B31B51... Bn+11
VD15 B12B32B52... Bn+12
VD14 B13B33B53... Bn+13
VD13 B14B34B54... Bn+14
VD12 B15B35B55... Bn+15
VD11 G10G30G50... Gn+10
VD10 G11G31G51... Gn+11
VD9 G12G32G52... Gn+12
VD8 G13G33G53... Gn+13
VD7 G14G34G54... Gn+14
VD6 G15G35G55... Gn+15
VD5 R10R30R50... Rn+10
VD4 R11R31R51... Rn+11
VD3 R12R32R52... Rn+12
VD2 R13R33R53... Rn+13
VD1 R14R34R54... Rn+14
VD0 R15R35R55... Rn+15
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Table 15-3: 18-Bi t Data Format (Non-S wapped)
Cycle Count
1 2 3 ... n
VD[35:18] Driven Low
VD17 R05R15R25... Rn5
VD16 R04R14R24... Rn4
VD15 R03R13R23... Rn3
VD14 R02R12R22... Rn2
VD13 R01R11R21... Rn1
VD12 R00R10R20... Rn0
VD11 G05G15G25... Gn5
VD10 G04G14G24... Gn4
VD9 G03G13G23... Gn3
VD8 G02G12G22... Gn2
VD7 G01G11G21... Gn1
VD6 G00G10G20... Gn0
VD5 B05B15B25... Bn5
VD4 B04B14B24... Bn4
VD3 B03B13B23... Bn3
VD2 B02B12B22... Bn2
VD1 B01B11B21... Bn1
VD0 B00B10B20... Bn0
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Table 15-4: 18-Bit Data Format (Swapped)
Cycle Count
1 2 3 ... n
VD[35:18] Driven Low
VD17 B00B10B20... Bn0
VD16 B01B11B21... Bn1
VD15 B02B12B22... Bn2
VD14 B03B13B23... Bn3
VD13 B04B14B24... Bn4
VD12 B05B15B25... Bn5
VD11 G00G10G20... Gn0
VD10 G01G11G21... Gn1
VD9 G02G12G22... Gn2
VD8 G03G13G23... Gn3
VD7 G04G14G24... Gn4
VD6 G05G15G25... Gn5
VD5 R00R10R20... Rn0
VD4 R01R11R21... Rn1
VD3 R02R12R22... Rn2
VD2 R03R13R23... Rn3
VD1 R04R14R24... Rn4
VD0 R05R15R25... Rn5
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16 SwivelView™
16.1 Concept
Most computer displays are refreshed in landscape orientation – from left to right and top
to bottom. Computer images are stored in the same manner. SwivelView™ is designed to
rotate the displayed image on an LCD by 90°, 180°, or 270° in a counter-clockwise
direction. The rotation is done in hardware and is transparent to the user for all display
buffer writes. By processing the rotation in hardware, SwivelView™ offers a performance
advantage over software rotation of the displayed image.
The actual address translation is performed during the Host Write and is therefore stored in
memory as rotated. Because of where the rotation logic is, each Window written to the
S1D13742 can be independently rotated with respect to each other.
16.2 90° SwivelView™
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13742 in the
following sense: A–B–C–D. The display is refreshed in the following sense: B-D-A-C.
Figure 16-1: Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView.
16.2.1 Register Programming
There is no special programming requirements other than simply enabling the rotation
itself. All start addresses and Line Offset’s are automatically calculated by hardware.
image seen by programmer
= image in display buffer
480
SwivelView
window
480
320
AB
CD
D
C
B
A
320
SwivelView
window
display start address
image refreshed by the S1D13742
(panel origin)
physical memory
start address
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16.3 180° SwivelView™
The following figure shows how the programmer sees a 480x320 landscape image and how
the image is being displayed. The application image is written to the S1D13742 in the
following sense: A–B–C–D. The display is refreshed in the following sense: D-C-B-A.
Figure 16-2: Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.
16.3.1 Register Programming
There is no special programming requirements other than simply enabling the rotation
itself. All start addresses and Line Offset’s are automatically calculated by hardware.
image seen by programmer
= image in display buffer
480
SwivelView
window
480
320
AB
CD
320
image refreshed by the S1D13742
SwivelView
window
AB
CD
display start address
(panel origin)
physical memory
start address
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16.4 270° SwivelView™
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13742 in the
following sense: A–B–C–D. The display is refreshed in the following sense: C-A-D-B.
Figure 16-3: Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.
16.4.1 Register Programming
There is no special programming requirements other than simply enabling the rotation
itself. All start addresses and Line Offset’s are automatically calculated by hardware.
image seen by programmer
= image in display buffer
480
SwivelView
window
480
320
AB
CD
D
C
B
A
320
SwivelView
window
image refreshed by the S1D13742
physical memory
display start address
(panel origin)
start address
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17 Host Interface
17.1 Using the Intel 80 Interface
Accessing the S1D13742 through the Intel 80 interface is a multiple step process. All
Registers and Memory are accessed through register space.
Note
All Register accesses, except the Memory Data Port, are 8-bit only. If the Host in-
terface is 16-bits wide, the lsb’s (MD[7:0]) are used for all registers except the
Memory Data Port.
The Memory Data Port (REG[48h, 49h]) is handled as 8-bit if CNF1 = 0
(REG[49h] not used) or 16-bit if CNF1 =1.
First, perform a single “Address Write” to setup the register address. Next a “Data
Read/Write” is performed that specifies the data to be stored or read from the registers or
memory specified in the “Address Write” cycle. Subsequent data Read/Writes without a
Address Write to change the register address, will automatically “auto” increment the
register address or the internal memory address if accessing the Memory Data Port.
To write display data to a Window Aperture, simply set-up the Window coordinates
followed by the burst data writes to the Memory Data Port to fill the window. In this
sequence, the internal memory addressing is automatic (see examples). The Memory Data
Port is located directly following the Window coordinates to minimize the number of
Address Writes.
To Read display data, perform an Address Write to the Memory Address Port (3 bytes) and
then read data from the Memory Data Port. Sequential reads will auto-increment the
internal memory address
17.1.1 Register write procedure
1. Perform address write to setup register address bits 7-0.
2. Perform data write to update the register.
3. Additional data writes are supported. In this case, the register addresses will be auto-
incremented.
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Figure 17-1: Register Write Example Sequence
17.1.2 Register read procedure
1. Perform address write to setup register address bits 7-0.
2. Perform data read to get the register value.
3. Additional data reads are supported. In this case, the register addresses will be auto-in-
cremented.
Figure 17-2: Register Read Example Sequence
D/C#
CS#
WE#
RD#
MD[7:0]
Address
bits 7-0
Write
1
Data
Write
3
Data
Write
4
Data
Write
2
D/C#
CS#
RD#
MD[7:0]
WE#
MD[7:0]
Write
Read Address
bits 7-0
Write
1
Data
Read
3
Data
Read
4
Data
Read
2
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17.1.3 New Window Aperture Write procedure
The S1D13742 has a special procedure to minimize set-up accesses when bursting window
data.
1. The panel dimension registers must be set before writing any Window data.
2. Perform an Address Write to point to the first Window Register (Window X Start Po-
sition).
3. Perform eight “data” writes to the next eight, 8-bit registers (this will set-up all the
Window coordinates.
Note
In this case the register addresses will be auto-incremented until you reach the Memory
Data Port Register
4. Perform burst data writes to fill the window (the register address will already be point-
ing at the Memory Data Port)
The Memory Data Port Register is located in the 9th register address after the Window X
Start Position. Every write to the Memory Data Port will auto-increment the internal
memory address only.
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Figure 17-3: Sequential Memory Write Example Sequence
D/C#
CS#
WE#
RD#
MD[7:0]
Window X Start
Register Address
Window X Start Data
Window x Start Data
Window Y Start Data
Window Y Start Data
Window X End Data
Window X End Data
Window Y End Data
Window Y End Data
Display Data
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17.1.4 Opening Multiple Windows
1. Repeat steps above (New Window Aperture write procedure) with new window coor-
dinates for each new window.
2. Non-pixel doubled windows can overlap with the last one being written considered
the top.
Update Window using existing Window Coordinates:
1. Perform an Address Write to point to the Memory Data Port
2. Perform burst data writes to fill the window.
Note
In this case the previous coordinates of the Window Aperture will be used. Every write
to the Memory Data Port will auto-increment the internal memory address only.
17.1.5 Individual Memory Location Reads
Note
This function is for test purposes only and serves no practical use in a system.
1. Set the Memory Data Format to 16bpp.
2. Write the physical address of the memory location to read from, to the Memory Read
Address Registers (for a 16bit bus, the LSB of this address is ignored).
3. Perform a read from the Memory Data Port Register.
4. Continuous reads from the Memory Data Port Register will cause the address in the
Memory Read Address Registers to increment, thereby supporting burst reads.
Note
To access the 2 msb’s for each 18-bit value, you must know the physical address as they
are stored at different locations as compared to the lower 16-bits.
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18 Double Buffer Description
18.1 Double Buffer Controller
Double buffering is provided to prevent tearing of streaming video data. All static (non-
video) image data will always be written to the upper half (Buffer 1) of the frame buffer.
When video is being input, the first frame will be written to the lower half (Buffer 2) of the
double buffer. The second frame will be written to Buffer 1. While video data is being
input, the static part of the image going to the LCD will still always come from Buffer 1.
The source of the video window will come from either Buffer 1 or Buffer 2, depending on
which one was the last to be completely updated.
The switching of the buffer read/write pointers can only occur once per frame, at the
beginning of the vertical non-display period. The pointers will only switch if: a video frame
had completed being updated within the last output frame period, and no new video frame
is currently being written. Because of this, each time the user finishes writing a frame of
video data, they should wait until the next vertical non-display period before writing the
next frame. This can be accomplished by using the TE pin or by polling the Vertical Display
Period Status (REG[58h] bit 7). Alternatively, if the user can guarantee that the maximum
input video frame rate is 1/2 the LCD frame rate and that the burst length for writing a video
frame is less than one LCD frame period, then no checking for the vertical non-display
period is required. If attention is not paid to allowing the pointers to switch, then frames
may be dropped.
Figure 18-1: Switching of Buffer Pointers
To use the double buffer feature:
• Set the Special Effects Register REG[36h] bits 7-6 to 11.
• Setup the Window Position Registers REG[38h] - REG[46h].
• Write the video data to the Memory Data Port REG[48h] - REG[49h].
Vertical Non-Display Period
Input Video Frame Burst
Switch buffer pointers Don’t switch buffer pointers
since a frame is currently being
written.
Read Buffer Pointer
Write Buffer Pointer
since a frame completed
being updated in the last
LCD frame period
Switch buffer pointers
since a frame completed
being updated in the last
LCD frame period
Switch buffer pointers
since a frame completed
being updated in the last
LCD frame period
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It is also possible to update a static window while double buffering is enabled, even in the
middle of a video stream. To do this:
• Write the last pixel of the current frame of video data.
• Set the Special Effects Register REG[36h] bits 7-6 to 01.
• Setup the Window Position Registers REG[38h] - REG[46h].
• Write the static data to the Memory Data Port REG[48h] - REG[49h].
This allows a static image to be written at any time, while still preventing the double
buffered window from tearing. Once the static window has been written, the user can go
back to writing the streaming video data by following the steps described above for using
the double buffer feature.
Figure 18-2: Double Buffer Example
Background
image
Background
image
Background
image
Background
image
Buffer 1 Buffer 1 Buffer 1 Buffer 1
Buffer 2 Buffer 2 Buffer 2 Buffer 2
Output Output
Input
Input
Time 1:
The main/background image is
in Buffer 1. Buffer 2 is empty.
The data output to the LCD
comes entirely from Buffer 1.
Time 2:
The main/background image is
in Buffer 1. Buffer 2 is written
with video data. The data output
to the LCD comes entirely from
Buffer 1.
Time 3:
The main/background image is
in Buffer 1, but part of this data is
destructively overwritten by the
second frame of video data. The
static image data from Buffer 1 is
sent to the LCD, but the video
window comes from Buffer 2.
Output
PIP
Time 4:
A static PIP is destructively written
Output
Input
into Buffer 1. Since the most recently
updated video frame is in Buffer 1, the
entire image output to the LCD comes
from Buffer 1. There may be tearing in
the PIP window, but the video window
will not tear.
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There are some limitations to double buffering:
• Consider the case where there is a video stream being input and the user wants to place a
static PIP over all or some part of the video window. The user can write the PIP, but
when the video stream is continued, it will destructively overwrite the PIP, so that it will
appear as though the PIP is under the video window.
• Consider the case where there is a video stream which stops after the last frame of video
is sent. The final frame of video will continue to be displayed on the LCD. Assume that
this last frame is stored in Buffer 2. Now, if the user disables double buffering, the
buffer read pointer will immediately reset to Buffer 1. This means that the 2nd to last
frame will now be displayed instead of the last frame.
• The user must either wait for a vertical non-display period between writing frames of
video data, or guarantee that their maximum input frame rate is 1/2 the LCD frame rate
and that the length of time it takes to burst write a frame of video data is less than one
LCD frame period.
• Only one window can be double buffered at a time.
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19 Interfacing the S1D13742 and a TFT Panel
This section describes the hardware and software environment required to interface the
S1D13742 Mobile Graphics Engine and a 352x416 or 800x480 TFT Panel.
The designs described in this section are presented only as examples of how such interfaces
might be implemented.
19.1 Overview
The S1D13742 was designed to directly support the Sanyo LC13015 and requires no
additional hardware and minimal programming. The S1D13742 register settings and
electrical interface is described below.
19.1.1 Electrical Interface
Table 19-1: Pin Mapping
S1D13742
Pin Name
S1D13742
Pin Number
LCD13015
Pin Name
HS D9 HS
VS D10 VS
PCLK D11 PCLK
DE C11 DE
VD[17:0]
J8,J9,J10,J11,K4,K5,K6,K
7,K8,K9,K10,L3,L4,L5,L6,
L7,L8,L9
R5,R4,R3,R2,R1,R0,G5,G
4,G3,G2,G1,G0,B5,B4,B3,
B2,B1,B0
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19.1.2 S1D13742 Register Settings for 352x416 TFT Panel
Note
The registers listed below are only those associated with panel specific timing issues All
other registers are not shown here.
Note
When a window is setup for YUV data, the data must always alternate between odd and
even lines, starting with an odd line.
Table 19-2: Example Register Settings for 352x416 TFT Panel
Register Value Comment
All default Come out of reset - all registers set to default values
REG[56h] 02h enter sleep mode (or use PWRSVE pin)
REG[04h] 12h
set PLL M-Divider.
CLKI = 19.2MHz,
PLL input clock = CLKI/19 = 1.01MHz.
REG[06h] F8h
REG[08h] 80h
REG[0Ah] 28h
REG[0Ch] 00h
REG[0Eh] 2Fh LL = 48, resulting SYSCLK = LL x PLL input clock = 48MHz
REG[12h] 19h set PCLK divide, PCLK = 12.1MHz
set SYSCLK source = PLL
REG[14h] 0h no panel data swap, 18-bit panel
REG[16h] 2Ch HDP = 352 pixels
REG[18h] 5Ah HNDP = 90 pixels
REG[1Ah] A0h VDP = 416 lines
REG[1Ch] 01h
REG[1Eh] 06h VNDP = 6 lines
REG[20h] 14h HS Pulse Width = 20 pixels
REG[22h] 2Dh HS Start Position = 45 pixels
REG[24h] 02h VS Width = 2 lines
REG[26h] 01h VS Start Position (VFP) = 1 line
REG[28h] 80h PCLK Polarity: data output on falling edge
REG[2Ah] 01h set memory to 16 bpp,
set input data mode to RGB 5:6:5
REG[56h] 00h disable sleep mode
REG[04h] bit 7 — wait for PLL to lock - poll REG[04h] bit 7
REG[38h] 00h Window X Start Position = 0
REG[3Ah] 00h
REG[3Ch] 00h Window Y Start Position = 0
REG[3Eh] 00h
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Note
The above values are intended as examples. This example assumes that CLKI =
19.2MHz and that the PLL is used to generate SYSCLK. Actual settings can vary and
still remain within the LCD panel timing requirements.
REG[40h] 5Fh Window X End Position = 351
REG[42h] 01h
REG[44h] 9Fh Window Y End Position = 415
REG[46h] 01h
REG[48h] Write the image data to the Memory Data Port, REG[48h] and REG[49h]. The image
will immediately begin to appear on the LCD.
REG[49h]
Table 19-2: Example Register Settings for 352x416 TFT Panel (Continued)
Register Value Comment
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19.1.3 S1D13742 Register Settings for 800x480 TFT Panel
Note
The registers listed below are only those associated with panel specific timing issues All
other registers are not shown here.
Note
When a window is setup for YUV data, the data must always alternate between odd and
even lines, starting with an odd line.
Table 19-3: Example Register Settings for 800x480 TFT Panel
Register Value Comment
All default Come out of reset - all registers set to default values
REG[56h] 02h enter sleep mode (or use PWRSVE pin)
REG[04h] 0Bh
set PLL M-Divider.
CLKI = 12MHz,
PLL input clock = CLKI/12 = 1.0MHz.
REG[06h] F8h
REG[08h] 80h
REG[0Ah] 28h
REG[0Ch] 00h
REG[0Eh] 2Dh LL = 45, resulting SYSCLK = LL x PLL input clock = 45MHz
REG[12h] 09h set PCLK divide, PCLK = 22.5MHz
set SYSCLK source = PLL
REG[14h] 0h no panel data swap, 18-bit panel
REG[16h] 64h HDP = 800 pixels
REG[18h] 14h HNDP = 20 pixels
REG[1Ah] E0h VDP = 480 lines
REG[1Ch] 01h
REG[1Eh] 06h VNDP = 6 lines
REG[20h] 14h HS Pulse Width = 20 pixels
REG[22h] 2Dh HS Start Position = 45 pixels
REG[24h] 02h VS Width = 2 lines
REG[26h] 01h VS Start Position (VFP) = 1 line
REG[28h] 80h PCLK Polarity: data output on falling edge
REG[2Ah] 01h set memory to 16 bpp,
set input data mode to RGB 5:6:5
REG[56h] 00h disable sleep mode
REG[04h] bit 7 — wait for PLL to lock - poll REG[04h] bit 7
REG[38h] 00h Window X Start Position = 0
REG[3Ah] 00h
REG[3Ch] 00h Window Y Start Position = 0
REG[3Eh] 00h
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Note
The above values are intended as examples. This example assumes that CLKI = 12MHz
and that the PLL is used to generate SYSCLK. Actual settings can vary and still remain
within the LCD panel timing requirements.
REG[40h] 1Fh Window X End Position = 799
REG[42h] 03h
REG[44h] DFh Window Y End Position = 479
REG[46h] 01h
REG[48h] Write the image data to the Memory Data Port, REG[48h] and REG[49h]. The image
will immediately begin to appear on the LCD.
REG[49h]
Table 19-3: Example Register Settings for 800x480 TFT Panel (Continued)
Register Value Comment
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19.2 Host Bus Timing
Figure 19-1: Intel 80 Input A.C. Characteristics
D/C#
CS#
WE#
MD[15:0]
RD#
MD[15:0]
tast taht
tcs
tcsf
tcsf
twc
twrl twrh
tdst tdht
trcs trc
trdl
trdh
taht
todh
trat
Note: The D/C# input pin is used to distinguish between Address and Data.
Note: The register address will auto-increment in word increments for all register access except the
Gamma Correction Table Data register and Memory Data Port. Writes to the Gamma Correction Table
Data register and Memory Data Port will not increment the register address to support burst data
writes to the gamma correction table and to memory.
tddt
write
read
½IOVDD
½IOVDD
½IOVDD
½IOVDD
½IOVDD
½IOVDD
½IOVDD
½IOVDD
½IOVDD
½IOVDD ½IOVDD
½IOVDD
½IOVDD
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19.2.1 Host Bus Timing for 352x416 TFT Panel
SYSCLK = 48MHz, PCLK = 12MHz, CLKI = 12MHz
1. twrh min = long enough to satisfy twc
2. trdh min = long enough to satisfy trc
Table 19-4: Intel 80 Input A.C. Characteristics (352x416 Panel Timings)
Signal Symbol Parameter Min Max Unit Description
D/C# tast Address setup time 1.4 — nsec
taht Address hold time 0.3 — nsec
CS# tcs Chip Select setup time (write) 0.6 + twrl — nsec
trcs Chip Select setup time (read) 1.3 + trdl — nsec
tcsf Chip Select Wait time 9.2 — nsec
WE# twc Write cycle (rising edge to next rising edge) 42.6 — nsec
twrh Pulse high duration Note 1 —
twrl Pulse low duration 0.1 — nsec
RD#
trc
Read cycle for Registers 42.6 — nsec
Read cycle for Memory 122.1 + trdh — nsec
Read cycle for LUT 108.1 + trdh — nsec
trdh Pulse high duration Note 2 —
trdl
Pulse low duration for Registers 10.2 — nsec
Pulse low duration for Memory 122.1 — nsec
Pulse low duration for LUT 108.1 — nsec
MD[15:0]
tdst Data setup time 0 .3 — nsec
For maximum
CL=30pF
For minimum
CL=8pF
tdht D ata hol d time 6.4 — nsec
trat
(See note)
Read falling edge to Data valid for Registers — 12.2 nsec
Read falling edge to Data valid for Memory — 122.1 nsec
Read falling edge to Data valid for LUT — 108.1 nsec
todh
(See note) Read hold time 10.7 32.1 nsec
tddt
(See note) Read falling edge to Data driven 3.0 12.3 nsec
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19.2.2 Host Bus Timing for 800x480 TFT Panel
SYSCLK = 59 MHz, PCLK = 19.67 MHz, CLKI = 12MHz
1. twrh min = long enough to satisfy twc
2. trdh min = long enough to satisfy trc
Table 19-5: Intel 80 Input A.C. Characteristics (800x480 Panel Timings)
Signal Symbol Parameter Min Max Unit Description
D/C# tast Address setup time 1.4 — nsec
taht Address hold time 0.3 — nsec
CS# tcs Chip Select setup time (write) 0.6 + twrl — nsec
trcs Chip Select setup time (read) 1.3 + trdl — nsec
tcsf Chip Select Wait time 9.2 — nsec
WE# twc Write cycle (rising edge to next rising edge) 34.8 — nsec
twrh Pulse high duration Note 1 —
twrl Pulse low duration 0.1 — nsec
RD#
trc
Read cycle for Regi ster s 34.8 — nsec
Read cycle for Memory 102.7 + trdh — nsec
Read cycle for LUT 92.5 + trdh — nsec
trdh Pulse high duration Note 2 —
trdl
Pulse low duration for Registers 10.2 — nsec
Pulse low duration for Memory 102.7 — nsec
Pulse low duration for LUT 92.5 — nsec
MD[15:0]
tdst Data setup time 0.3 — nsec
For maximum
CL=30pF
For minimum
CL=8pF
tdht Data hold time 6.4 — nsec
trat
(See note)
Read falling edge to Data valid for Registers — 12.2 nsec
Read fallin g edge to Data valid for Memory — 102.7 nsec
Read fal lin g edge to Data va lid for LUT — 92 .5 nsec
todh
(See note) Read hold time 10.7 32.1 nsec
tddt
(See note) Read falling edge to Data driven 3.0 12.3 nsec
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19.3 Panel Timing
Figure 19-2: 18/36-Bit TFT A.C. Timing
t3
t5
HS
t1
t4
VS
DE
PCLK
320
t2
HS
21
t13
t10 t11 t14
t15 t16
t7
t8
t9 t12
VD[17:0]
Note: 2 pixels/clock Mode
t6
invalid
invalid
n+13-4
1-2
VD[35:0] invalid
invalid
Note: 1 pixel/clock Mode
PCLK
t13
t10 t11 t14
t9 t12
REG[28h] b7=1
REG[28h] b7=0
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19.3.1 Panel Timing for 352x416 Panel
1. Ts = pixel clock period = 83.3 ns (12MHz PCLK)
19.3.2 Panel Timing for 800x480 Panel
1. Ts = pixel clock period = 50.84 (19.67 PCLK)
Table 19-6: 18/36-Bit TFT A.C. Timing (352x416 Panel Timing)
Symbol Parameter Min Typ Max Units
t1 VS cycle time 15.54 — ms
t2 VS pulse width low 73.67 — us
t3 VS falling edge to HS falling edge phase difference 0 — 36.75 us
t4 HS cycle time 36.83 — us
t5 HS pulse width low 1.67 — us
t6 HS Falling edge to DE active 3.75 — us
t7 DE pulse width 29.3 — us
t8 DE falling edge to HS falling edge 3.75 — us
t9 PCLK period 83.3 — — ns
t10 PCLK pulse width low 41.7 — — ns
t11 PCLK pulse width high 41.7 — — ns
t12 HS setup to PCLK falling edge 41.7 — — ns
t13 DE to PCLK rising edge setup time 41.7 — — ns
t14 DE hold from PCLK rising edge 41.7 — — ns
t15 Data setup to PCLK rising edge 41.7 — — ns
t16 Data hold from PCLK rising edge 41.7 — — ns
Table 19-3 18/36-Bit TFT A.C. Timing (800x480 Panel Timings)
Symbol Parameter Min Typ Max Units
t1 VS cycle time 20.34 — ms
t2 VS pulse width low 83.4 — us
t3 VS falling edge to HS falling edge phase difference 0 — 41.63 us
t4 HS cycle time 41.68 — us
t5 HS pulse width low 1.02 — us
t6 HS Falling edge to DE active 966 — ns
t7 DE pulse width 40.67 — us
t8 DE falling edge to HS falling edge 50.84 — ns
t9 PCLK period 50.84 — — ns
t10 PCLK pulse width low 25.42 — — ns
t11 PCLK pulse width high 25.42 — — ns
t12 HS setup to PCLK falling edge 25.42 — — ns
t13 DE to PCLK rising edge setup time 25.42 — — ns
t14 DE hold from PCLK rising edge 25.42 — — ns
t15 Data setup to PCLK rising edge 25.42 — — ns
t16 Data hold from PCLK rising edge 25.42 — — ns
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19.4 Example Play.exe Scripts
The following example scripts are written for the PLAY.EXE program. The script
Demo.txt will initialize the S1D13742, then display horizontal bars at different rotations,
and then display a PIP+ window.
Demo.txt
verbose cmd:off out:on set:off
halt 0
'==============================================================================
' _DEMO_.txt - Play script for 13742 to demonstrate various features.
'
' This demonstration code is written in the Play.exe script language so that
' various steps can be easily observed. Some steps such as the initialization
' and the memory fills use Play intrinsic commands. These operation of these
' commands are easily determined.
'==============================================================================
' Initialize the registers to the default state by
' running the register list generated by 13742CFG
'----------------------------------------------------------
init
' Set the window to the full screen and clear the display
'----------------------------------------------------------
SetWin.txt
f WIN 0
' ROTATE 0
'----------------------------------------------------------
print "Color bars at SwivelView 0\n"
x 34 0
DrawBarsA.txt
Pause.txt
' ROTATE 90
' NOTE: There is a bug with the Fill WINdow command in
' Play which causes the 90 and 270 degree fills
' to be filled incorrectly. This will be corrected.
'----------------------------------------------------------
print "Color bars at SwivelView 90\n"
x 34 1
DrawBarsB.txt
Pause.txt
' ROTATE 180
'----------------------------------------------------------
print "Color bars at SwivelView 180\n"
x 34 2
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DrawBarsA.txt
Pause.txt
' ROTATE 270
' NOTE: There is a bug with the Fill WINdow command in
' Play which causes the 90 and 270 degree fills
' to be filled incorrectly. This will be corrected.
'----------------------------------------------------------
print "Color bars at SwivelView 270\n"
x 34 3
DrawBarsB.txt
Pause.txt
' PIP
'----------------------------------------------------------
print "Draw Color bars in a PIP (small window)\n"
x 34 0
SetWin.txt
f WIN 0
DrawBarsA.txt
DrawPIP.txt 50 50 100 128
Pause.txt
section END
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DrawBarsA.txt
verbose cmd:off out:on set:off
'==============================================================================
' DrawBars.txt - Play script for the 13742
'
' This script draws eight equally sized horizontal
' bars on the display.
'==============================================================================
set $Height ((reg[1C] << 8) + (reg[1A]))
set $Lines ($Height / 8)
set $StartX 0
set $StartY 0
set $EndX width
set $EndY $Lines
set $Color 0
set $Bars 8
section LOOP
SetWin.txt $StartX $StartY $EndX $EndY
f WIN $Color
set $StartY ($StartY + $Lines)
set $EndY ($EndY + $Lines)
set $Color ($Color + 0821)
set $Bars ($Bars - 1)
if $Bars!=0 then goto LOOP
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DrawBarsB.txt
verbose cmd:off out:on set:off
'==============================================================================
' DrawBarsB.txt - Play script for the 13742
'
' This script draws horizontal bars in SwivelView 90 and SwivelView 270
' display modes.
'==============================================================================
set $Height (reg[16] * 8)
set $Lines ($Height / 8)
set $StartX 0
set $StartY 0
set $EndX height
set $EndY $Lines
set $Color 0
set $Bars 8
section LOOP
SetWin.txt $StartX $StartY $EndX $EndY
f WIN $Color
set $StartY ($StartY + $Lines)
set $EndY ($EndY + $Lines)
set $Color ($Color + 0821)
set $Bars ($Bars - 1)
if $Bars!=0 then goto LOOP
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DrawPIP.txt
verbose cmd:off out:on set:off
'==============================================================================
' DrawPIP.txt - Play script for the 13742
'
' This script draws eight equally sized horizontal bars on the display.
'==============================================================================
set $StartX arg[1].nt
set $StartY arg[2].nt
set $Width arg[3].nt
set $Height arg[4].nt
set $Lines ($Height / 8)
set $Color 0
set $Bars 8
section LOOP
SetWin.txt $StartX $StartY $Width $Lines
f WIN $Color
set $StartY ($StartY + $Lines)
set $Color ($Color + 0821)
set $Bars ($Bars - 1)
if $Bars!=0 then goto LOOP
Pause.txt
verbose cmd:off out:on set:off
halt 0
print "Paused . . . press any key to continue\n"
input line
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SetWin.txt
verbose cmd:off out:on set:off
'------------------------------------------------------------------------------
' SetWin.txt - Play script for the 13742
'
' This script is functionally identical to the Play command 'win'. Call this
' script to set the 13742 window co-ordinates as specified by the arguments.
'
' Syntax: SetWin X Y W H
' Where: X - Left edge window X position
' Y - Top edge window Y position
' W - Window width
' H - Window height
'
' Example: SetWin 0 0 100 100
' Sets the window to start at 0,0 and end at 100, 100
'
' SetWin
' Sets the window size to the size of the display
'
' win SX:0 SY:0 EX:width EY:height
'------------------------------------------------------------------------------
' Set the default window values to the display size.
set $SX 0
set $SY 0
set $EX (width - 1)
SET $EY (height - 1)
' Use non-default values ONLY if all four arguments are given
if (argn!=5) then goto SETWINDOW
set $SX arg[1].n
set $SY arg[2].n
set $EX (arg[1].n + arg[3].n - 1)
set $EY (arg[2].n + arg[4].n - 1)
section SETWINDOW
' Change the register window settings
x 38 $SX
x 3A ($SX >> 8)
x 3C $SY
x 3E ($SY >> 8)
x 40 $EX
x 42 ($EX >> 8)
x 44 $EY
x 46 ($EY >> 8)
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19.5 References
19.5.1 Documents
• Sanyo Electric Co., Ltd. Display Company, LC13015 Low Temperature P-Si TFT-LCD
Specification, Document Number LC13015-040302
• Epson Research and Development, Inc., S1D13742 Hardware Functional Specification,
Document Number X63A-A-001-xx.
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20 PLL Power Supply Considerations
The PLL circuit is an analog circuit which is very sensitive to noise on the input clock
waveform or the power supply. Noise on the clock or the supplied power may cause the
operation of the PLL circuit to become unstable or increase the jitter.
Due to these noise constraints, it is highly recommended that the power supply traces or the
power plane for the PLL be isolated from those of other power supplies. Filtering should
also be used to keep the power as clean as possible.
The following are guidelines which, if followed, will result in cleaner power to the PLL,
this will result in a cleaner and more stable clock. Even a partial implementation of these
guidelines will give results.
20.1 Guidelines for PLL Power Layout
The PLL circuit is an analog circuit and is very sensitive to noise on the input clock
waveform or the power supply. Noise on the clock or the supplied power may cause the
operation of the PLL circuit to become unstable or increase the jitter.
Due to these noise constraints, it is highly recommended that the power supply traces or the
power plane for the PLL be isolated from those of other power supplies. Filtering should
also be used to keep the power as clean as possible.
The following are guidelines which, if followed, will result in cleaner power to the PLL,
resulting in a cleaner and more stable clock. Even a partial implementation of these guide-
lines will give results.
Figure 20-1: PLL Power Layout
Voltage
Regulator
S1D13742
PLLVDD
PLLVSS
Optional, but recommended
Notes:
L1
L2
C2
C3 C1
To Digital VSS Plane
To Digital IOVDD Plane
PLL power traces
must split from the
digital traces very
close to the regulator
• PLLVDD and PLLVSS traces should be as short as possible
• PLLVDD and PLLVSS must be separated from the digital supply
• Digital power and ground to L1 and L2 should be short parallel traces
on the same side of the board to reduce any loop area that can induce noise
Typical Values:
L1, L2
C1
C2
C3
isolation bead
~10uf bypass
1nf bypass
.1uf bypass
Actual values may be different and
subject to validation
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• Place the ferrite beads (L1 and L2) parallel to each other with minimal clearance
between them. Both bypass caps (C2 and C3) should be as close as possible to the
inductors. The traces from C3 to the power planes should be short parallel traces on the
same side of the board with just the normal small clearance between them. Any signifi-
cant loop area here will induce noise. If there is a voltage regulator on the board, try to
run these power traces directly to the regulator instead of dropping to the power planes
(still follow above rules about parallel traces).
• The analog ground point where bypass cap (C2) connects to the ground isolation
inductor (L2) becomes the analog ground central point for a ground star topology. None
of the components connect directly to the analog ground pin of the MGE (PLLVSS)
except for a single short trace from C2 to the PLLVSS pin. The ground side of the large
bypass capacitor (C1) should also have a direct connection to the star point.
• The same star topology rules used for analog ground apply to the analog power connec-
tion where L2 connects to C2.
• All of the trace lengths should be as short as possible.
• If possible, have all the PLL traces on the same outside layer of the board. The only
exception is C1, which can be put on the other side of the board if necessary. C1 does
not have to be as close to the analog ground and power star points as the other compo-
nents.
• If possible, include a partial plane under the PLL area only (area under PLL components
and traces). The solid analog plane should be grounded to the C2 (bypass) pad. This
plane won’t help if it is too large. It is strictly an electrostatic shield against coupling
from other layers’ signals in the same board area. If such an analog plane is not possible,
try to have the layer below the PLL components be a digital power plane instead of a
signal layer.
• If possible, keep other board signals from running right next to PLL pin vias on any
layer.
• Wherever possible use thick traces, especially with the analog ground and power star
connections to either side of C2. Try to make them as wide as the component pads – thin
traces are more inductive.
It is likely that manufacturing rules will prohibit routing the ground and power star connec-
tions as suggested. For instance, four wide traces converging on a single pad could have
reflow problems during assembly because of the thermal effect of all the copper traces
around the capacitor pad. One solution might be to have only a single trace connecting to
the pad and then have all the other traces connecting to this wide trace a minimum distance
away from the pad. Another solution might be to have the traces connect to the pad, but
with thermal relief around the pad to break up the copper connection. Ultimately the board
must also be manufacturable, so best effort is acceptable.
Epson Research and Development Page 125
Vancouver Design Center
Hardware Functional Specification S1D13742
Issue Date: 2008/07/07 X63A-A-001-06
Revision 6.2
21 Mechanical Data
Figure 21-1: S1D13742 FCBGA 121-pin Package
0.65 0.75
0.3
±0.05
0.65
units = mm
0.75
1234567891011
A
B
C
D
E
F
G
H
J
K
L
TOP VIEW
SIDE VIEW
BOTTOM
VIEW
A1 corner
A1 corner
8.0
±0.20
Die Size
Die Size
8.0
±0.20
1.0 max.
0.28
±0.05
Page 126 Epson Research and Development
Vancouver Design Center
S1D13742 Hardware Functional Specification
X63A-A-001-06 Issue Date: 2008/07/07
Revision 6.2
Figure 21-2: S1D13742 QFP20 144-pin Package
INDEX
units = mm
73108
37
72
361
144
109
D
H
D
H
E
E
eb
Amax
A1
A2
θ
c
L
Symbol Dimension in Millimeters
Min Nom Max
E—20—
D—20—
HE—22—
HD—22—
Amax ——1.7
A1—0.1—
A2—1.4—
e—0.5—
b 0.17 — 0.27
c0.09—0.2
θ0° — 10°
L0.3—0.75
L1—1—
y——0.08
L
1
yS
Epson Research and Development Page 127
Vancouver Design Center
Hardware Functional Specification S1D13742
Issue Date: 2008/07/07 X63A-A-001-06
Revision 6.2
Figure 21-3: S1D13742 FCBGA 121-pin Package Marking
units = mm
(1)
(2)(3)(4)(5)(6)(7)(8)(9)(10)
(11)(12)(13)(14)(15)(16)(17)(18)(19)
C0.74
2.28
3.18
CCAAA
(20)(21)(22)(23)(24)
Y
X’
X
Y’
Package Center Line
Package Center Line
A = 0.3
B = 0.4
C = 0.6
D = 0.1
E = 0.2
Number of row and
column not fixed
Index Mark
0.8
2.2
2.13
Φ 0.8
3.03
DDD
DDDDD
BEE B B B
BBBB
J
A
P
N
A
D
7
4
2
Item No. Notes
Logo Specified (1)
Device Name (2) ~ (5)
Die Revision Code (6)
Package Type (7) C: FCBGA
Process and Package Revision Code (8)
[Blank] (9) ~ (10)
Control Code (11) ~ (19)
Year of Manufacture (12) ~ (13) Last two numbers of A.D.
Month of Manufacture (14) ~ (15) 1-9: Jan - Sep
x: Oct, Y: Nov, Z: Dec
W/F Lot No. (16) ~ (19)
JAPAN (20) ~ (24)
Page 128 Epson Research and Development
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S1D13742 Hardware Functional Specification
X63A-A-001-06 Issue Date: 2008/07/07
Revision 6.2
Figure 21-4: S1D13742 QFP 144-pin Package Marking
units = mm
8.0
Y
X’
X
Y’
Package Center Line
Package Center Line
A = 0.8
B = 0.25
C = 1.0
D = 0.5
Item No. Notes
Logo Specified (1) EPSON
JAPAN (2) ~ (6)
Device Name (7) ~ (19) S1D13742F01A2
Control Code (20) ~ (28)
Year of Manufacture (21) ~ (22) Last two numbers of A.D.
Week of Manufacture (23) ~ (24) Calendar Week of the Year
W/F Lot No. (25) ~ (28)
(1)
(2) (3) (4) (5) (6)
(7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19)
(20) (21) (22) (23) (24) (25) (26) (27) (28)
2.0
AAAAA
0.3
BBBB
1.2
A
1.5
AAAAABBBB AAAABBBB
A
1.2
CCCCCC CCCCCCBBBBBBBBBBBBDD
Pin 1
XX’
Y
Y’
Epson Research and Development Page 129
Vancouver Design Center
Hardware Functional Specification S1D13742
Issue Date: 2008/07/07 X63A-A-001-06
Revision 6.2
22 References
The following documents contain additional information related to the S1D13742.
Document numbers are listed in parenthesis after the document name. All documents can
be found at the Epson Research and Development Website at www.erd.epson.com.
• S1D13742 Product Brief (X63A-C-001-xx)
• S5U13742P00C100 Evaluation Board User Manual (X63A-G-002-xx)
Page 130 Epson Research and Development
Vancouver Design Center
S1D13742 Hardware Functional Specification
X63A-A-001-06 Issue Date: 2008/07/07
Revision 6.2
23 Sales and Technical Support
23.1 Ordering Information
To ord er the S1 D13742 Mobil e Graphic s Engine, c ontact t he Epson sa les repr esentat ive in
your area.
AMERICA
EPSON ELECTRONICS AMERICA, INC.
HEADQUARTERS
2580 Orchard Parkway
San Jose , CA 95131,USA
Phone: +1-800-228-3964 FAX: +1-408-922-0238
SALES OFFICES
Northeast
301 Edgewater Place, Suite 210
Wakefield, MA 01880, U.S.A.
Phone: +1-800-922-7667 FAX: +1-781-246-5443
EUROPE
EPSON EUROPE ELECTRONICS GmbH
HEADQUARTERS
Riesstrasse 15
80992 Munich, GERMANY
Phone: +49-89-14005-0 FAX: +49-89-14005-110
ASIA
EPSON (CHINA) CO., LTD.
23F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
Phone: +86-10-6410-6655 FAX: +86-10-6410-7320
SHANGHAI BRANCH
7F, High-Tech Bldg., 900, Yishan Road,
Shanghai 200233, CHINA
Phone: +86-21-5423-5522 FAX: +86-21-5423-5512
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 FAX: +852-2827-4346
Telex: 65542 EPSCO HX
EPSON Electronic Technology Development (Shenzhen)
LTD.
12/F, Dawning Mansion, Keji South 12th Road,
Hi- Tech Park, Shenzhen
Phone: +86-755-2699-3828 FAX: +86-755-2699-3838
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road,
Taipei 110
Phone: +886-2-8786-6688 FAX: +886-2-8786-6660
EPSON SINGAPORE PTE., LTD.
1 HarbourFront Place,
#03-02 HarbourFront Tower One, Singapore 098633
Phone: +65-6586-5500 FAX: +65-6271-3182
SEIKO EPSON CORPORATION
KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: +82-2-784-6027 FAX: +82-2-767-3677
GUMI OFFICE
2F, Grand B/D, 457-4 Songjeong-dong,
Gumi-City, KOREA
Phone: +82-54-454-6027 FAX: +82-54-454-6093
SEIKO EPSON CORPORATION
SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Dept.
IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814 FAX: +81-42-587-5117
Epson Research and Development Page 131
Vancouver Design Center
Hardware Functional Specification S1D13742
Issue Date: 2008/07/07 X63A-A-001-06
Revision 6.2
Change Record
X63A-A-001-06 Revision 6.2 - Issued: 2008/07/07
• all changes from the last revision of the spec are highlighted in Red
• Set revision to 6.2 to align with Japan revision numbering
• section 8.4 Setting SYSCLK and PCLK - add CLKI information to this section
X63A-A-001-06 Revision 6.01 - Issued: 2007/09/18
• all changes from the last revision of the spec are highlighted in Red
• section 5.1, for the Intel 80 Data Pin Mapping tables, swapped the MD[15:8] descrip-
tions for CNF1=0, B00 should be “internal resistors” and B01 should be “Hi-Z”
• section 7.3.1 ~ 7.3.2, added note and clarified the usage of MD[15:8] pins in the Host
Timing figures and tables
• section 17.1.3, updated the X/Y Start/End data order in the Sequential Memory Write
Example Sequence figure and moved it to section 17.1.3
• section 22, added References
• section 23, added Sales and Technical Support addresses
X63A-A-001-06 Revision 6.0 (Issued 2007/05/29)
• all changes from the last revision of the spec are highlighted in Red
• section 14 Gamma Correction Look-Up Table Architecture - correct typos in Figure 14 -
1; change data from display buffers to 6 bit, change the multiplexers to 64 positions
from 256
• section 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel - correct typo in
Table 19-3, change the REG[04h] value to 0Bh
X63A-A-001-05 Revision 5.02 (Issued 2006/08/23)
• all changes from the last revision of the spec are highlighted in Red
• globally add QFP20 144-pin package information
• section 5.3 LCD Interface Data Pins - correct typos in table, change Hi-Z to Driven Low
• section 6.3 Electrical Characteristics - add table 6-5 Electrical Characteristics for
IOVDD or PIOVDD = 3.3V ± 0.3V
• section 7.2 RESET# Timing - add CLKI signal to figure
• section 7.3.1 Intel 80 Interface Timing - 1.8 Volt - rewrite section for 1.8 volts
• section 7.3.2 Intel 80 Interface Timing - 3.3 Volt - add this section
• REG[2Ah] bits 4-0 - add note “RGB 6:6:6 mode 2 and RGB 8:8:8 mode 2...”
X63A-A-001-05 Revision 5.01 (Issued 2006/04/28)
Page 132 Epson Research and Development
Vancouver Design Center
S1D13742 Hardware Functional Specification
X63A-A-001-06 Issue Date: 2008/07/07
Revision 6.2
• updated EPSON tagline
• all changes from the last revision of the spec are highlighted in Red
• section 4.2.1 Intel 80 Host Interface - for MD[15:0] rewrite the note in pin description,
for GPIO_INT add reference to General Purpose IO Pins Registers to pin description.
• section 4.2.2 LCD Interface - for VD[35:0] rewrite both notes in pin description
• section 4.2.4 Miscellaneous - for GPIO[7:0] rewrite pin description, for PWRSVE
rewrite pin description for no pull-down resistor
• section 4.2.4, change SCANEN pin description IO Voltage from “VSS” to “IOVDD”
• section 7.2 RESET# Timing - add this section
• section 17.1.2 and 17.1.5, for the Host Interface section changed the references in the
figures from “D[15:0]” to “MD[15:0]”
• fixed typo in change record, document numbers should be listed as “X63...” instead of
“X59...”
• section 6.3 Electrical Characteristics - in tables 6-3 and 6-4, define the conditions for
Quiescent Current
X63A-A-001-04 Revision 4.0 (Issued 2005/11/29)
• section 7.3.3 18/36-Bit TFT Panel Timing - correct typos in figure 7-8 18/36-Bit TFT
A/C Timing - change references to REG[2Ah] to REG[28h], change t17 reference to
falling edge of VS, and in table 7-7 18/36-Bit TFT A/C Timing change PCLK edge
references to “active”
X63A-C-001-03 1
Revision 3.01
GRAPHICS
S1D13742
S1D13742 Mobile Graphics Engine August 2007
The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742
supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory
allowing for fast screen updates.
Products requiring a rotated display image can take advantage of the SwivelView™ feature which provides
hardware rotation of the display memory transparent to the software application. Resolutions supported include
800x480 single buffered and 352x416 double buffered.
The S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen
updates.
■FEATURES
■SYSTEM BLOCK DIAGRAM
•Embedded 768K byte SRAM Display Buffer
•Low Operating Voltage
•8/16-bit Intel 80 interface (used for display or regis-
ter data).
•RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to
16 or 18 bpp).
•YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter
stored as 16 or 18 bpp).
•Active Matrix TFT interface - 18/36-bit interface.
•Supports resolutions up to 800x480.
•Hardware / Software Power Save mode.
•16/18 bit-per-pixel (bpp) color depths.
•SwivelView™: 90°, 180°, 270° counter-clockwise
hard ware rotation of display image
•Double-Buffer available to prevent image tearing
during streaming input
•Pixel Doubling: Horizontal and Vertical averaging
for smooth doubling of a single window
•Pixel Halving: no limitation on number of windows
•Internal programmable PLL.
•Single MHz clock input: CLKI.
•General Purpose Input/Output pins.
Data and
CPU
Control Signals
13742
Activ e Ma trix TFT Display
• 768K Bytes SRAM
S1D13742 Includes:
• Pixel Doubling
• Pixel Halving
• Swivelview™
Revision 3.01 X63A-C-001-03 2
GRAPHICS
S1D13742
■DESCRIPTION
Integrated Frame Buffer
•Embedded 768K byte SRAM display buffer.
CPU Interface
•8/16-bit Intel 80 interface (used for display or register
data).
•Chip select is used to select device. When inactive, any
input data/ command w ill be ign ored .
Panel Support
•Active Matrix TFT interface.
•18/36-bit interface.
•Supports resolutions up to 800x480.
Miscellaneous
•Internal programmable PLL.
•Single MHz clock input: CLKI.
•CLKI available as CLKOUT (separate CLKOUTEN pin
assoc ia ted with output).
•Hardware / Software Power Save mode.
•Input pin to Enable/Disable Power Save Mode.
•General Purpose Input/Output pins are available
(GPIO[7:0]).
•COREVDD 1.5 volts and IOVDD 1.65 ~ 3.6 volts
•FCBGA 121-pin or QFP20 144-pin package
Digital Video
•RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18
bpp).
•YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as
16 or 18 bpp).
Display Features
•16/18 bit- per-p ix el (bpp ) color depths .
•16 bpp to 18 bpp Input Data conversion.
•All display writes are handled by window apertures/position
for complete or partial display updates. All window coordi-
nates are r eferenc ed to top lef t corn er of the displ ayed im age
(even in a rotated display, the top-left corner is maintained
and no host side translation need take place).
•SwivelView™: 90°, 180°, 270° counter-clockwise hardware
rotation of display image. All displayed windows can have
independent rotation. No additional programming necessary
when enabling these modes.
•Double-Buffer available to prevent image tearing during
streaming input. Resolutions supported must fit inside 384K
bytes (½ of tot al availab le display bu ffer). T ypic al resolution of
352x416.
•Pixel Doubling: Horizontal and Vertical averaging for smooth
doubling of a single window.
•Pixel Halving: no limitation on number of windows.
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS
• S1D13742 Technical
Documentation • CPU Independent
Software Utilities
• S1D13742 Evaluation
Boards • Royalty Free source level
driver code
©SEIKO EPSON CORPORATION 2005 - 2007. All rights reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You
may not modify the document. Epson Research and Devel opment, Inc. disclaims a ny representati on that the conte nts of this document are accura te or current . The Program s/Technologies
described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wa nchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4 34 6
http://www.epson.com.hk/
Singapore
Epson Singapore Pte Ltd
1 HarbourFront Place #03-02
HarbourFront Tower One
Singapore, 098633
Tel: (65) 6586-5500
Fax: (65) 6271-3182
http://www.epson.com.sg/
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
http://www.epson-electronics.de/
Japan
Seiko Epson Corporation
IC International Sales Group
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp/
Taiwan
Epson Taiwan Technology & Trading Ltd.
14F, No. 7
Song Ren Road
Taipei 110
Tel: 02-8786-6688
Fax: 02-87 86- 667 7
http://www.epson.com.tw/
North America
Epson Electronics America, Inc.
2580 Orchar d Par kway
San Jose, CA 95131, USA
Tel: (40 8) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com/
