NAND Flash and Mobile LPDRAM
168-Ball Package-on-Package (PoP) MCP
Combination Memory (TI OMAP™)
MT29CxGxxMAxxxxx
Features
•Micron® NAND Flash and LPDRAM components
•RoHS-compliant, “green” package
•Separate NAND Flash and LPDRAM interfaces
•Space-saving multichip package/package-on-package
combination
•Low-voltage operation (1.70–1.95V)
•Industrial temperature range: –40°C to +85°C
NAND Flash-Specific Features
Organization
•Page size
–x8: 2112 bytes (2048 + 64 bytes)
–x16: 1056 words (1024 + 32 words)
•Block size: 64 pages (128K + 4K bytes)
Mobile LPDRAM-Specific Features
•No external voltage reference required
•No minimum clock rate requirement
•1.8V LVCMOS-compatible inputs
•Programmable burst lengths
•Partial-array self refresh (PASR)
•Deep power-down (DPD) mode
•Selectable output drive strength
•STATUS REGISTER READ (SRR) supported1
Figure 1: PoP Block Diagram
NAND Flash
Device
NAND Flash
Power
NAND Flash
Interface
LPDRAM Power LPDRAM
Interface
LPDRAM
Device
Options2Marking
•Mobile LPDRAM
–200 MHz CL33-5
–166 MHz CL3 -6
–133 MHz CL3 -75
Notes: 1. Contact factory for remapped SRR output.
2. For part numbering and physical part mark-
ings, see Figure 2 (page 2) and Table 1
(page 3).
3. CL = CAS (READ) latency.
Preliminary‡
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Features
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Part Numbering Information
Micron NAND Flash and LPDRAM devices are available in different configurations and
densities.
Figure 2: 168-Ball Part Number Chart
MT 29C 2G 24M A K L A JG -6 IT ES
Micron Technology
Product Family
29C = NAND + LPDRAM MCP
NAND Density
1G = 1Gb
2G = 2Gb
4G = 4Gb
LPDRAM Density
12M = 512Mb
24M = 1024Mb
48M = 2048Mb
Operating Voltage Range
A = 1.8V (1.70–1.95V)
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
Operating Temperature Range
IT = Industrial (–40° to +85°C)
LPDRAM Self Refresh Current
Blank = Standard
LPDRAM Access Time
-5 = 200 MHz CL3
-6 = 166 MHz CL3
-75 = 133 MHz CL3
Package Codes
JG = 168-ball PoP (TI OMAP) (12 x 12 x 0.9mm)
JI = 168-ball PoP (TI OMAP) (12 x 12 x 1.1mm)
KQ = 168-ball PoP (TI OMAP) (12 x 12 x 0.75mm)
NAND Flash Configuration
Width Density Generation
C x8 1Gb First
D x16 1Gb First
J x8 2Gb Second
K x16 2Gb Second
N x8 4Gb First
P x16 4Gb First
Y x8 4Gb Second
Z x16 4Gb Second
Chip Count
CE#, CS# Chip Count
A 1, 1 1 NAND, 1 LPDRAM
B 1, 1 2 NAND, 1 LPDRAM
C 1, 2 1 NAND, 2 LPDRAM
D 1, 2 2 NAND, 2 LPDRAM
LPDRAM Configuration
Type Width Density Generation
J DDR x16 1Gb First
L DDR x32 1Gb First
N DDR x16 512Mb Second
R DDR x32 512Mb Second
AM DDR x16 2Gb First
AP DDR x32 2Gb First
Note: 1. Not all possible combinations are available. Contact factory for availability.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Part Numbering Information
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Table 1: Production Part Numbers
Part Number NAND Product LPDDR Product Physical Part Marking
MT29C2G24MAKLAJG-6 IT MT29F2G16ABDHC-ET MT46H32M32LFJG-6 IT JW192
MT29C2G24MAKLAJG-75 IT MT29F2G16ABDHC-ET MT46H32M32LFJG-6 IT JW193
MT29C2G48MAKLCJI-6 IT MT29F2G16ABDHC-ET MT46H32M32LFJG-6 IT JW256
MT29C2G48MAKLCJI-75 IT MT29F2G16ABDHC-ET MT46H32M32LFJG-6 IT JW255
MT29C4G48MAPLCJG-6 IT MT29F4G16ABCWC-ET MT46H32M32LFJG-6 IT JW426
MT29C4G48MAPLCJI-6 IT MT29F4G16ABCWC-ET MT46H32M32LFJG-6 IT JW295
MT29C4G48MAPLCJI-75 IT MT29F4G16ABCWC-ET MT46H32M32LFJG-6 IT JW294
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To
view the location of the abbreviated mark on the device, refer to customer service note
CSN-11, “Product Mark/Label,” at www.micron.com/csn.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Part Numbering Information
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
MCP General Description
Micron package-on-package (PoP) MCP products combine NAND Flash and Mobile
LPDRAM devices in a single MCP. These products target mobile applications with low-
power, high-performance, and minimal package-footprint design requirements. The
NAND Flash and Mobile LPDRAM devices are also members of the Micron discrete mem-
ory products portfolio.
The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces
(no shared address, control, data, or power balls). This bus architecture supports an op-
timized interface to processors with separate NAND Flash and Mobile LPDRAM buses.
The NAND Flash and Mobile LPDRAM devices have separate core power connections
and share a common ground (that is, Vss is tied together on the two devices).
The bus architecture of this device also supports separate NAND Flash and Mobile
LPDRAM functionality without concern for device interaction. Operational characteris-
tics for the NAND Flash and Mobile LPDRAM devices are found in the standard Micron
data sheets for each of the discrete devices.
For device specifications and complete Micron NAND Flash features documentation,
refer to the component data sheet at www.micron.com/nand, or contact your local Mi-
cron sales office.
For device specifications and complete Mobile LPDRAM features documentation, refer
to the component data sheet at www.micron.com/products/mobiledram, or contact
your local Micron sales office.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
MCP General Description
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Ball Assignments and Descriptions
Figure 3: 168-Ball VFBGA (NAND x8; LPDDR x16) Ball Assignments
1
DNU
DNU
NC
NC
Vddq
NC
NC
Vddq
NC
Vdd
Vcc
I/O1
I/O3
Vcc
I/O5
I/O7
Vcc
WE#
ALE
CE1#
Vcc
DNU
DNU
1
2
DNU
DNU
NC
NC
Vssq
NC
NC
Vssq
NC
Vss
Vss
I/O0
I/O2
Vss
I/O4
I/O6
Vss
RE#
NC
CE0#
Vss
DNU
DNU
2
4
Vddq
Vssq
RFU
RFU
4
3
DQ14
DQ15
RFU
RFU
3
5
DQ12
DQ13
Vss
Vcc
5
6
UDM
UDQS
RFU
RFU
6
7
Vddq
Vssq
RFU
RFU
7
8
DQ10
DQ11
Vss
Vcc
8
12
Vdd
Vss
R/B#
CLE
12
13
DQ6
DQ7
Vss
Vcc
13
14
DQ4
DQ5
Vss
TQ
14
15
Vddq
Vssq
NC
NC
15
16
DQ2
DQ3
NC
NC
16
17
LDM
LDQS
NC
NC
17
18
Vddq
Vssq
NC
NC
18
19
DQ0
DQ1
NC
NC
19
20
NC
NC
Vss
NC
20
21
NC
NC
BA0
BA1
21
22
DNU
DNU
Vssq
NC
NC
Vssq
NC
Vss
CKE0
Vss
CAS#
CS0#
A0
A2
A4
A6
A8
A10
A12
A14
Vss
DNU
DNU
22
23
DNU
DNU
Vddq
NC
NC
Vddq
NC
Vdd
CKE1
WE#
RAS#
CS1#
A1
A3
A5
A7
A9
A11
A13
Vdd
Vdd
DNU
DNU
23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Top View – Ball Down
9
DQ8
DQ9
LOCK
NC
9
10
Vddq
Vssq
WP#
NC
10
11
CK
CK#
NC
NC
11
NAND LPDDR Supply Ground
Note: 1. Contact factory for availability of x16 LPDDR configuration.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Figure 4: 168-Ball VFBGA (NAND x16; LPDDR x32) Ball Assignments
1
DNU
DNU
DM0
DQ7
Vddq
DQ5
DQ3
Vddq
DQ1
Vdd
Vcc
I/O1
I/O3
Vcc
I/O5
I/O7
Vcc
WE#
ALE
CE1#
Vcc
DNU
DNU
1
2
DNU
DNU
DQS0
DQ6
Vssq
DQ4
DQ2
Vssq
DQ0
Vss
Vss
I/O0
I/O2
Vss
I/O4
I/O6
Vss
RE#
NC
CE0#
Vss
DNU
DNU
2
4
Vddq
Vssq
I/O10
I/O11
4
3
DQ17
DQ16
I/O8
I/O9
3
5
DQ19
DQ18
Vss
Vcc
5
6
DM2
DQS2
I/O12
I/O13
6
7
Vddq
Vssq
I/O14
I/O15
7
8
DQ21
DQ20
Vss
Vcc
8
12
Vdd
Vss
R/B#
CLE
12
13
DQ9
DQ8
Vss
Vcc
13
14
DQ11
DQ10
Vss
TQ
14
15
Vddq
VSSq
NC
NC
15
16
DQ13
DQ12
NC
NC
16
17
DM1
DQS1
NC
NC
17
18
Vddq
VSSq
NC
NC
18
19
DQ15
DQ14
NC
NC
19
20
DM3
DQS3
Vss
NC
20
21
DQ25
DQ24
BA0
BA1
21
22
DNU
DNU
VSSq
DQ26
DQ28
Vssq
DQ30
Vss
CKE0
Vss
CAS#
CS0#
A0
A2
A4
A6
A8
A10
A12
A14
Vss
DNU
DNU
22
23
DNU
DNU
Vddq
DQ27
DQ29
Vddq
DQ31
Vdd
CKE1
WE#
RAS#
CS1#
A1
A3
A5
A7
A9
A11
A13
Vdd
Vdd
DNU
DNU
23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Top View – Ball Down NAND LPDDR Supply Ground
9
DQ23
DQ22
LOCK
NC
9
10
Vddq
Vssq
WP#
NC
10
11
CK
CK#
NC
NC
11
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Table 2: x8, x16 NAND Ball Descriptions
Symbol Type Description
ALE Input Address latch enable: When ALE is HIGH, addresses can be
transferred to the on-chip address register.
CE0#, CE1# Input Chip enable: Gates transfers between the host system and
the NAND device.
CE1# is used when a second CE# is required and is RFU in all
other configurations.
CLE Input Command latch enable: When CLE is HIGH, commands can be
transferred to the on-chip command register.
LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK func-
tion is enabled. To disable BLOCK LOCK, connect LOCK to Vss
during power-up, or leave it unconnected (internal pull-down).
RE# Input Read enable: Gates information from the NAND device to the
host system.
WE# Input Write enable: Gates information from the host system to the
NAND device.
WP# Input Write protect: Driving WP# LOW blocks ERASE and
PROGRAM operations.
I/O[7:0] (x8)
I/O[15:0] (x16)
Input/
output
Data inputs/outputs: The bidirectional I/Os transfer address,
data, and instruction information. Data is output only during
READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU1 for NAND x8 devices.
R/B# Output Ready/busy: Open-drain, active-LOW output that indicates
when an internal operation is in progress.
Vcc Supply Vcc: NAND power supply.
Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be
used. Contact factory for details.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 7Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Table 3: x16, x32 LPDDR Ball Descriptions
Symbol Type Description
A[14:0] (x16)
A[14:0] (x32)
Input Address inputs: Specifies the row or column address. Also
used to load the mode registers. The maximum LPDDR ad-
dress is determined by density and configuration. Consult the
LPDDR product data sheet for the maximum address for a giv-
en density and configuration. Unused address balls
become RFU.1
BA0, BA1 Input Bank address inputs: Specifies one of the 4 banks.
CAS# Input Column select: Specifies which command to execute.
CK, CK# Input CK is the system clock. CK and CK# are differential clock
inputs. All address and control signals are sampled and
referenced on the crossing of the rising edge of CK with the
falling edge of CK#.
CKE0, CKE1 Input Clock enable.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products and is considered RFU
for single LPDDR MCPs.
CS0#, CS1# Input Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU
for single LPDDR MCPs.
UDM, LDM (x16)
DM[3:0] (x32)
Input Data mask: Determines which bytes are written
during WRITE operations.
For x16 LPDDR, unused DM balls become RFU.
RAS# Input Row select: Specifies the command to execute.
WE# Input Write enable: Specifies the command to execute.
DQ[15:0] (x16)
DQ[31:0] (x32)
Input/
output
Data bus: Data inputs/outputs.
DQ[31:16] are RFU for x16 LPDDR devices.
UDQS, LDQS (x16)
DQS[3:0] (x32)
Input/
output
Data strobe: Coordinates READ/WRITE transfers of data; one
DQS per DQ byte.
For x16 LPDDR, unused DQS balls become RFU.
TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ
exceeds 85°C.
Vdd Supply Vdd: LPDDR power supply.
Vddq Supply Vddq: LPDDR I/O power supply.
Vssq Supply Vssq: LPDDR I/O ground.
Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be
used. Contact factory for details.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 8Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Table 4: Non-Device-Specific Descriptions
Symbol Type Description
Vss Supply Vss: Shared ground.
Symbol Type Description
DNU –Do not use: Must be grounded or left floating.
NC –No connect: Not internally connected.
RFU1–Reserved for future use.
Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be
used. Contact factory for details.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 9Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Table 5: Absolute Maximum Ratings
Parameters/Conditions Symbol Min Max Unit
Vcc, Vdd, Vddq supply voltage
relative to Vss
Vcc, Vdd,
Vddq
–1.0 2.4 V
Voltage on any pin
relative to Vss
Vin –0.5 2.4 or (supply voltage1 +
0.3V), whichever is less
V
Storage temperature range ––55 +150 °C
Note: 1. Supply voltage references Vcc, Vdd, or Vddq.
Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
Table 6: Recommended Operating Conditions
Parameters Symbol Min Typ Max Unit
Supply voltage Vcc, Vdd 1.70 1.80 1.95 V
I/O supply voltage Vddq 1.70 1.80 1.95 V
Operating temperature range ––40 –+85 °C
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Electrical Specifications
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Device Diagrams
Figure 5: 168-Ball (Single LPDDR) Functional Block Diagram
CE0#
CLE
ALE
RE#
WE#
WP#
LOCK
CS0#
CK
CK#
CKE0
RAS#
CAS#
WE#
Address,
BA0, BA1
Vcc
I/O
R/B#
Vss
Vdd
Vddq
DM
DQ
DQS
TQ
Vss
Vssq
NAND Flash
LPDDR
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Device Diagrams
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Figure 6: 168-Ball (Dual LPDDR) Functional Block Diagram
CE0#
CLE
ALE
RE#
WE#
WP#
CS0, CS1#
CK
CK#
CKE0, CKE1
RAS#
CAS#
WE#
Address,
BA0, BA1
Vcc
I/O
R/B#
Vss
Vdd
Vddq
DM
DQ
DQS
TQ
Vss
Vssq
NAND Flash
LPDDR
(Die 0 and 1)
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Device Diagrams
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Package Dimensions
Figure 7: 168-Ball VFBGA (Package Code: JG)
0.6 ±0.1
0.08 AA
11 CTR
Ball A1 ID
Ball A1 ID
0.5 TYP
12 ±0.1
11 CTR
Seating
plane
12 ±0.1
168X Ø0.33
0.5 TYP
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.27 SMD
ball pads.
0.9 MAX
0.25 MIN
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
2322212019 17161518 14 910111213 8 7 6 5 4 3 2 1
Note: 1. All dimensions are in millimeters.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Package Dimensions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Figure 8: 168-Ball VFBGA (Package Code: JI)
0.75 ±0.1
0.08 AA
11 CTR
Ball A1 ID
Ball A1 ID
0.5 TYP
12 ±0.1
11 CTR
Seating
plane
12 ±0.1
168X Ø0.33
0.5 TYP
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.27
SMD ball pads.
1.1 MAX
0.25 MIN
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
212223 1920 18 1716 151413 1211 10 9 8 7 6 54 3 2 1
Note: 1. All dimensions are in millimeters.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Package Dimensions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Figure 9: 168-Ball WFBGA (Package Code: KQ)
0.43 ±0.05
0.08 AA
11 CTR
Ball A1 ID
Ball A1 ID
0.5 TYP
12 ±0.1
11 CTR
Seating
plane
12 ±0.1
0.5 TYP
168X Ø0.34
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.28
SMD ball pads.
0.75 MAX
0.23 MIN
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Note: 1. All dimensions are in millimeters.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Package Dimensions
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Revision History
Rev. I, Preliminary – 6/09
•Updated Figure 2 (page 2) for NAND Flash Configuration codes by adding "y" informa-
tion: y (x8, 4Gb, Second) and z (x16, 4Gb, second).
•Changed ball Y22 from NC to A14 in Figure 4 (page 6).
•Changed A[13:0] to A[14:0] in Table 3 (page 8).
Rev. H, Preliminary – 5/09
•Deleted "Device size" bullets from NAND-Flash-Specific Features on the page 1.
•Added 200 MHz CL3 (-5) to Options/Marking table on page 1.
•Updated Figure 2 (page 2) to list "-5 = 200 MHz CL3" under "LPDRAM Access Time."
Udated the Package Codes to show the preferred format. Added "CS#" after "CE#" in
the Chip Count. Changed row B under Chip Count to "1, 1" and row D to "1, 2." Add-
ed "AM" and "AP" under "LPDRAM Configuration." Added "KQ" under "Package
Codes." Deleted "L = Low-Power Option."
•Modified Figure 5 (page 11) to change "CS#" to "CSO#," "CKE" to "CKE0," and "CE#"
to "CE0#."
•Modified Figure 6 (page 12) to change "CE#" to "CE0#."
•Added new Figure 9 (page 15).
Rev. G, Preliminary – 3/09
•Added MT29C4G48MAPLCJG-6 IT to part number table.
Rev. F, Preliminary – 11/08
•Updated template for external publication
Rev. E, Preliminary – 09/08
• “MT29CxGxxMAxxxJG, MT29CxGxxMAxxxJI”: As the third-from-the-last character in
the part number, replaced “A” with an “x.”
•Figure 3, Ball Assignment: 168-Ball VFBGA (x8 NAND Flash and x16 LPDRAM): Upda-
ted figure by replacing “NC”s in lower-left corner with “RFU”s.
•Table 2, “NAND Flash Ball Descriptions,” In CE1#/CE0# row, reversed order of ball
numbers to reflect correct highest-to-lowest order; changed “NC” to “RFU1” in the I/
O row; added note 1.
•Table 3, “LPDDR Ball Descriptions,”: In BA1/BA0, CKE1/CKE0, and CS1#/CS0# rows,
reversed order of ball numbers to reflect correct highest-to-lowest order; in NC row,
removed AE-indicated ball assignments and created a new RFU row.
•Figure 6, 168-Ball Dual LPDDR Functional Block Diagram: Added figure adapted from
152-ball.
•Figure 7, 168-Ball VFBGA (Package Code: JG): Updated figure with current version
from MDM.
•Figure 8, 168-Ball VFBGA (Package Code: JI): Updated figure with current version
from MDM.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Revision History
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Rev. D, Preliminary – 04/08
•Changed status to preliminary.
•Figure 2: 168-Ball Part Number Chart on page 2: Added JI part number and package
code.
•Figure 3: Ball Assignment: 168-Ball VFBGA (x8 NAND Flash and x16 LPDRAM); Figure
4: 168-Ball VFBGA (NAND x16; LPDDR x32) Ball Assignments; Table 2, “NAND Flash
Ball Descriptions,”; Table 3, “LPDDR Ball Descriptions,”; and Table 4, “Non-Device-
Specific Ball Descriptions,”: Updated ball assignments.
•Removed former capacitance tables. See component data sheets for capacitance.
•Figure 8: 168-Ball VFBGA (Package Code: JI): Added figure.
Rev. C, Advance – 02/08
•Figure 2: 168-Ball Part Number Chart: Updated self-refresh current definition.
•Figure 7: 168-Ball VFBGA (Package Code: JG): Updated package diagram with 0.15 tol-
erance.
Rev. B – 12/07
• “LP-DRAM-Specific Features”: Added SRR feature.
•Separated original single ball-assignment table into separate tables: Table 2, “NAND
Flash Ball Descriptions,” Table 3, “LPDDR Ball Descriptions,” and Table 4, “Non-De-
vice-Specific Ball Descriptions.”
•Figure 3, 137-Ball TFBGA (LPDDR) Ball Assignments, on page 4: changed pin P1 from
NC to RFU.
•Removed “Mobile” from LP-DRAM references.
Rev. A – 12/07
•Initial release.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
Preliminary
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Revision History
PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
