SST32HF402-70-4E-L3KE - Silicon Storage Technology

S71209-07-EOL 02/08

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Data Sheet

FEATURES:

• MPF + SRAM ComboMemory

– SST32HF202: 128K x16 Flash + 128K x16 SRAM

– SST32HF402: 256K x16 Flash + 128K x16 SRAM

– SST32HF802: 512K x16 Flash + 128K x16 SRAM

• Single 2.7-3.3V Read and Write Operations

• Concurrent Operation

– Read from or write to SRAM while

Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 15 mA (typical) for

Flash or SRAM Read

– Standby Current: 20 µA (typical)

• Flexible Erase Capability

– Uniform 2 KWord sectors

– Uniform 32 KWord size blocks

• Fast Read Access Times:

– Flash: 70 ns

–SRAM: 70 ns

• Latched Address and Data for Flash

• Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time:

SST32HF202: 2 seconds (typical)

SST32HF402: 4 seconds (typical)

SST32HF802: 8 seconds (typical)

• Flash Automatic Erase and Program Timing

– Internal VPP Generation

• Flash End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Conforms to Flash pinout

• Packages Available

– 48-ball LFBGA (6mm x 8mm)

– 48-ball LBGA (10mm x 12mm)

(SST32HF802 only)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST32HF202/402/802 ComboMemory devices inte-

grate a 128K x16, 256K x16, 512K x16 CMOS flash mem-

ory bank with a 128K x16 CMOS SRAM memory bank in a

Multi-Chip Package (MCP), manufactured with SST’s pro-

prietary, high performance SuperFlash technology.

Featuring high performance Word-Program, the flash

memory bank provides a maximum Word-Program time of

14 µsec. The entire flash memory bank can be erased and

programmed word-by-word in typically 2 seconds for the

SST32HF202, 4 seconds for the SST32HF402, and 8 sec-

onds for the SST32HF802, when using interface features

such as Toggle Bit or Data# Polling to indicate the comple-

tion of Program operation. To protect against inadvertent

flash write, the SST32HF202/402/802 devices contain on-

chip hardware and software data protection schemes. The

SST32HF202/402/802 devices offer a guaranteed endur-

ance of 10,000 cycles. Data retention is rated at greater

than 100 years.

The SST32HF202/402/802 devices consist of two inde-

pendent memory banks with respective bank enable sig-

nals. The Flash and SRAM memory banks are

superimposed in the same memory address space. Both

memory banks share common address lines, data lines,

WE# and OE#. The memory bank selection is done by

memory bank enable signals. The SRAM bank enable sig-

nal, BES# selects the SRAM bank. The flash memory

bank enable signal, BEF# selects the flash memory bank.

The WE# signal has to be used with Software Data Protec-

tion (SDP) command sequence when controlling the Erase

and Program operations in the flash memory bank. The

SDP command sequence protects the data stored in the

flash memory bank from accidental alteration.

The SST32HF202/402/802 provide the added functionality

of being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Word-Program concurrently. All

flash memory Erase and Program operations will automati-

cally latch the input address and data signals and complete

the operation in background without further input stimulus

requirement. Once the internally controlled Erase or Pro-

gram cycle in the flash bank has commenced, the SRAM

bank can be accessed for Read or Write.

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

SST32HF202 / 402 / 8022Mb Flash + 2Mb SRAM, 4Mb Flash + 2Mb SRAM, 8Mb Flash + 2Mb SRAM

(x16) MCP ComboMemory

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

The SST32HF202/402/802 devices are suited for applica-

tions that use both flash memory and SRAM memory to

store code or data. For systems requiring low power and

small form factor, the SST32HF202/402/802 devices signif-

icantly improve performance and reliability, while lowering

power consumption, when compared with multiple chip

solutions. The SST32HF202/402/802 inherently use less

energy during erase and program than alternative flash

technologies. The total energy consumed is a function of

the applied voltage, current, and time of application. Since

for any given voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternative flash technologies.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

Device Operation

The ComboMemory uses BES# and BEF# to control oper-

ation of either the SRAM or the flash memory bank. When

BES# is low, the SRAM Bank is activated for Read and

Write operation. When BEF# is low the flash bank is acti-

vated for Read, Program or Erase operation. BES# and

BEF# cannot be at low level at the same time. If BES# and

BEF# are both asserted to low level bus contention will

result and the device may suffer permanent damage.

All address, data, and control lines are shared by SRAM

Bank and flash bank which minimizes power consumption

and loading. The device goes into standby when both bank

enables are high.

SRAM Operation

With BES# low and BEF# high, the SST32HF202/402/802

operate as 128K x16 CMOS SRAM, with fully static opera-

tion requiring no external clocks or timing strobes. The

SST32HF202/402/802 SRAM is mapped into the first 128

KWord address space. When BES# and BEF# are high,

both memory banks are deselected and the device enters

standby mode. Read and Write cycle times are equal. The

control signals UBS# and LBS# provide access to the

upper data byte and lower data byte. See Table 3 for SRAM

Read and Write data byte control modes of operation.

SRAM Read

The SRAM Read operation of the SST32HF202/402/802 is

controlled by OE# and BES#, both have to be low with

WE# high for the system to obtain data from the outputs.

BES# is used for SRAM bank selection. OE# is the output

control and is used to gate data from the output pins. The

data bus is in high impedance state when OE# is high. See

Figure 3 for the Read cycle timing diagram.

SRAM Write

The SRAM Write operation of the SST32HF202/402/802 is

controlled by WE# and BES#, both have to be low for the

system to write to the SRAM. During the Word-Write oper-

ation, the addresses and data are referenced to the rising

edge of either BES# or WE#, whichever occurs first. The

write time is measured from the last falling edge to the first

rising edge of BES# or WE#. See Figures 4 and 5 for the

Write cycle timing diagrams.

Flash Operation

With BEF# active, the SST32HF202 operates as 128K x16

flash memory, the SST32HF402 operates as 256K x16

flash memory, and the SST32HF802 operates as 512K

x16 flash memory. The flash memory bank is read using

the common address lines, data lines, WE# and OE#.

Erase and Program operations are initiated with the

JEDEC standard SDP command sequences. Address and

data are latched during the SDP commands and during the

internally-timed Erase and Program operations.

Flash Read

The Read operation of the SST32HF202/402/802 devices

is controlled by BEF# and OE#. Both have to be low, with

WE# high, for the system to obtain data from the outputs.

BEF# is used for flash memory bank selection. When

BEF# and BES# are high, both banks are deselected and

only standby power is consumed. OE# is the output con-

trol and is used to gate data from the output pins. The data

bus is in high impedance state when OE# is high. Refer to

Figure 6 for further details.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

Flash Erase/Program Operation

SDP commands are used to initiate the flash memory bank

Program and Erase operations of the SST32HF202/402/

802. SDP commands are loaded to the flash memory bank

using standard microprocessor Write sequences. A com-

mand is loaded by asserting WE# low while keeping BEF#

low and OE# high. The address is latched on the falling

edge of WE# or BEF#, whichever occurs last. The data is

latched on the rising edge of WE# or BEF#, whichever

occurs first.

Flash Word-Program Operation

The flash memory bank of the SST32HF202/402/802

devices is programmed on a word-by-word basis. Before

Program operations, the memory must be erased first. The

Program operation consists of three steps.

The first step is the three-byte load sequence for Software

Data Protection. The second step is to load word address

and word data. During the Word-Program operation, the

addresses are latched on the falling edge of either BEF# or

WE#, whichever occurs last. The data is latched on the ris-

ing edge of either BEF# or WE#, whichever occurs first. The

third step is the internal Program operation which is initiated

after the rising edge of the fourth WE# or BEF#, whichever

occurs first.

The Program operation, once initiated, will be completed,

within 20 µs. See Figures 7 and 8 for WE# and BEF# con-

trolled Program operation timing diagrams and Figure 18 for

flowcharts. During the Program operation, the only valid

flash Read operations are Data# Polling and Toggle Bit.

During the internal Program operation, the host is free to

perform additional tasks. Any SDP commands loaded dur-

ing the internal Program operation will be ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32HF202/402/802 offer both Sector-

Erase and Block-Erase mode. The sector architecture is

based on uniform sector size of 2 KWord. The Block-Erase

mode is based on uniform block size of 32 KWord. The

Sector-Erase operation is initiated by executing a six-byte

command sequence with Sector-Erase command (30H)

and sector address (SA) in the last bus cycle.

The address lines A16-A11, for SST32HF202, A17-A11, for

SST32HF402, and A18-A11, for SST32HF802, are used to

determine the sector address. The Block-Erase operation

is initiated by executing a six-byte command sequence with

Block-Erase command (50H) and block address (BA) in

the last bus cycle. The address lines A16-A15, for

SST32HF202, A17-A15, for SST32HF402, and A18-A15, for

SST32HF802, are used to determine the block address.

The sector or block address is latched on the falling edge of

the sixth WE# pulse, while the command (30H or 50H) is

latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE# pulse.

The End-of-Erase operation can be determined using

either Data# Polling or Toggle Bit methods. See Figures 12

and 13 for timing waveforms. Any commands issued during

the Sector- or Block-Erase operation are ignored.

Flash Chip-Erase Operation

The SST32HF202/402/802 provide a Chip-Erase opera-

tion, which allows the user to erase the entire memory

array to the “1” state. This is useful when the entire device

must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 10 for timing diagram,

and Figure 21 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST32HF202/402/802 provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

Flash Data# Polling (DQ7)

When the SST32HF202/402/802 flash memory banks are

in the internal Program operation, any attempt to read DQ7

will produce the complement of the true data. Once the

Program operation is completed, DQ7 will produce true

data. Note that even though DQ7 may have valid data

immediately following the completion of an internal Write

operation, the remaining data outputs may still be invalid:

valid data on the entire data bus will appear in subsequent

successive Read cycles, after an interval of 1 µs. During

internal Erase operation, any attempt to read DQ7 will pro-

duce a ‘0’. Once the internal Erase operation is completed,

DQ7 will produce a ‘1’. The Data# Polling is valid after the

rising edge of the fourth WE# (or BEF#) pulse for Program

operation. For Sector- or Block-Erase, the Data# Polling is

valid after the rising edge of the sixth WE# (or BEF#) pulse.

See Figure 9 for Data# Polling timing diagram and Figure

19 for a flowchart.

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘1’s

and ‘0’s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the toggling will

stop. The flash memory bank is then ready for the next

operation. The Toggle Bit is valid after the rising edge of the

fourth WE# (or BEF#) pulse for Program operation. For

Sector- or Bank-Erase, the Toggle Bit is valid after the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 10 for

Toggle Bit timing diagram and Figure 19 for a flowchart.

Flash Memory Data Protection

The SST32HF202/402/802 flash memory bank provides

both hardware and software features to protect nonvolatile

data from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

Flash Software Data Protection (SDP)

The SST32HF202/402/802 provide the JEDEC approved

software data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32HF202/402/802 devices are shipped with the soft-

ware data protection permanently enabled. See Table 4 for

the specific software command codes. During SDP com-

mand sequence, invalid SDP commands will abort the

device to the Read mode, within Read cycle time (TRC).

Concurrent Read and Write Operations

The SST32HF202/402/802 provide the unique benefit of

being able to read from or write to SRAM, while simulta-

neously erasing or programming the Flash. This allows

data alteration code to be executed from SRAM, while alter-

ing the data in Flash. The following table lists all valid states.

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

CONCURRENT READ/WRITE STATE TABLE

Flash SRAM

Program/Erase Read

Program/Erase Write

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

Product Identification

The Product Identification mode identifies the devices as

the SST32HF202/402/802 and manufacturer as SST. This

mode may be accessed by software operations only.

The hardware device ID Read operation, which is typi-

cally used by programmers, cannot be used on this

device because of the shared lines between flash and

SRAM in the multi-chip package. Therefore, applica-

tion of high voltage to pin A9 may damage this device.

Users may use the software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details, see

Tables 3 and 4 for software operation, Figure 14 for the

software ID entry and Read timing diagram, and Figure 20

for the ID entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the software reset command is ignored during an

internal Program or Erase operation. See Table 4 for soft-

ware command codes, Figure 15 for timing waveform and

Figure 20 for a flowchart.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between VDD and

VSS, e.g., less than 1 cm away from the VDD pin of the

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from VDD to VSS should be placed within 1 cm of

the VDD pin.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST32HF202 0001H 2789H

SST32HF402 0001H 2780H

SST32HF802 0001H 2781H

T1.2 1209

I/O Buffers

1209 B1.0

Address Buffers

DQ15 - DQ8

AMS-A0

WE#

SuperFlash

Memory

SRAM

Control Logic

BES#

BEF#

OE#

Address Buffers

& Latches

LBS#

UBS#

DQ7 - DQ0

FUNCTIONAL BLOCK DIAGRAM

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA

1209 48-lfbga L3K P1a.3

SST32HF202

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

BES#

A12

A14

A10

LBS#

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

UBS#

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1209 48-lfbga L3K P1b.3

SST32HF402

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

BES#

A12

A17

A14

A10

LBS#

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

UBS#

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1209 48-lfbga L3K P1c.3

SST32HF802

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

BES#

A12

A17

A14

A10

LBS#

A18

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

UBS#

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM)

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

Address Inputs To provide flash addresses, A16-A0 for 2M, A17-A0 for 4M, and A18-A0 for 8M.

To provide SRAM addresses, A16-A0 for 2M.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle.

The outputs are in tri-state when OE# or BES# and BEF# are high.

BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply 2.7-3.3V power supply (for L3K package only)

VDDF2

2. For SST32HF802 in the LBK package only

Power Supply (Flash) 2.7-3.3V power supply to flash only

VDDS2Power Supply (SRAM) 2.7-3.3V power supply to SRAM only

VSS Ground

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0

NC No Connection Unconnected Pins

T2.4 1209

BES#

A10

OE#

A11

A13

WE#

VSS

DQ5

DQ7

A17

VDDS

DQ1

DQ2

DQ4

UBS#

A16

DQ0

DQ8

BEF#

VSS

DQ3

DQ10

DQ9

A18

DQ12

VDDF

DQ11

A12

DQ6

DQ13

A14

A15

LBS#

DQ15

DQ14

A B C D E F G H

SST32HF802

TOP VIEW (balls facing down)

1209 48-tbga LBK P2.0

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

TABLE 3: OPERATION MODES SELECTION

Mode BES#1BEF#1OE# WE# UBS# LBS# DQ15 to DQ8DQ7 to DQ0Address

Not Allowed VIL VIL X2XX X X X X

Flash

Read VIH VIL VIL VIH XX D

OUT DOUT AIN

Program VIH VIL VIH VIL XX D

IN DIN AIN

Erase X VIL VIH VIL X X X X Sector or Block address,

XXH for Chip-Erase

SRAM

Read VIL VIH VIL VIH VIL VIL DOUT DOUT AIN

VIL VIH VIL VIH VIL VIH DOUT High Z AIN

VIL VIH VIL VIH VIH VIL High Z DOUT AIN

Write VIL VIH XV

IL VIL VIL DIN DIN AIN

VIL VIH XV

IL VIL VIH DIN High Z AIN

VIL VIH XV

IL VIH VIL High Z DIN AIN

Standby VIHC VIHC X X X X High Z High Z X

Flash Write Inhibit X X VIL X X X High Z / DOUT High Z / DOUT X

XXXV

IH X X High Z / DOUT High Z / DOUT X

IH X X X X High Z / DOUT High Z / DOUT X

Output Disable VIH VIL VIH VIH X X High Z High Z X

VIL VIH XXV

IH VIH High Z High Z X

VIL VIH VIH VIH X X High Z High Z X

Product Identification

Software Mode VIH VIL VIL VIH X X Manufacturer’s ID (00BFH)

Device ID3

AMSF4-A1=VIL, A0=VIH

(See Table 4)

T3.5 1209

1. Do not apply BES#=VIL and BEF#=VIL at the same time

2. X can be VIL or VIH, but no other value.

3. Device ID for: SST32HF202 = 2789H, SST32HF402 = 2780H, and SST32HF802 = 2781H

4. AMS = Most significant flash address

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA2Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX350H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit XXH F0H

Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H

T4.4 1209

1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.

2. WA = Program Word address

3. SAX for Sector-Erase; uses AMS-A11 address lines

BAX for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address

AMS = A16 for SST32HF202, A17 for SST32HF402, and A18 for SST32HF802

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

SST32HF202 Device ID = 2789H, is read with A0 = 1,

SST32HF402 Device ID = 2780H, is read with A0 = 1

SST32HF802 Device ID = 2781H, is read with A0 = 1.

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.3V

Extended -20°C to +85°C 2.7-3.3V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 16 and 17

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=5 MHz,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

BEF#=VIL, BES#=VIH

Flash 30 mA

SRAM 30 mA BEF#=VIH, BES#=VIL

Concurrent Operation 55 mA BEF#=VIH, BES#=VIL

Write

Flash 30 mA

WE#=VIL

BEF#=VIL, BES#=VIH, OE#=VIH

SRAM 30 mA BEF#=VIH, BES#=VIL

ISB Standby VDD Current

SST32HF202/402 30 µA VDD=VDD Max, BEF#=BES#=VIHC

SST32HF802 40 µA VDD=VDD Max, BEF#=BES#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOLF Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOHF Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

VOLS Output Low Voltage 0.4 V IOL=1 mA, VDD=VDD Min

VOHS Output High Voltage 2.2 V IOH=-500 µA, VDD=VDD Min

T5.7 1209

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.0 1209

TABLE 7: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 24 pF

CIN1Input Capacitance VIN = 0V 12 pF

T7.0 1209

TABLE 8: FLASH RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T8.0 1209

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

AC CHARACTERISTICS

TABLE 9: SRAM READ CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TRCS Read Cycle Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 0 25 ns

TBYHZS1UBS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T9.3 1209

TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to End-of-Write 60 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 ns

T10.3 1209

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

TABLE 11: FLASH READ CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TBE Bank Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TBLZ1BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TBHZ1BEF# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

T11.2 1209

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TBS WE# and BEF# Setup Time 0 ns

TBH WE# and BEF# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TBPW BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH WE# Pulse Width High 30 ns

TBPH BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH Data Hold Time 0 ns

TIDA Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T12.0 1209

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM

FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1

ADDRESSES AMSS-0

DQ15-0

UBS#, LBS#

Note: WE# remains High (VIH) for the Read cycle

MSS = Most Significant SRAM Address

OE#

BES#

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS TBYES

TBYLZS TBYHZS

DATA VALID

TOHZS

TBHZS

TOHS

1209 F02.0

AWS

ADDRESSES AMSS-0

BES#

WE#

UBS#, LBS#

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.

If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.

Because D

signals may be in the output state at this time, input signals of reverse polarity must not be applied.

WPS

WRS

WCS

ASTS

BWS

BYWS

ODWS

OEWS

DSS

DHS

1209 F03.1

DQ15-8, DQ7-0 VALID DATA IN

NOTE 2 NOTE 2

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1

FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM

ADDRESSES A

MSS-0

WE#

BES#

BWS

AWS

WCS

WPS

WRS

ASTS

BYWS

15-8

, DQ

7-0

VALID DATA IN

DSS

DHS

UBS#, LBS#

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because D

signals may be in the output state at this time, input signals of reverse polarity must not be applied.

1209 F04.0

NOTE 2 NOTE 2

1209 F05.0

ADDRESSES AMSF-0

DQ15-0

WE#

OE#

BEF#

TBE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TBLZ TOH TBHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

MSF

= Most Significant Flash Address

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 8: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM

1209 F06.0

ADDRESSES AMSF-0

DQ15-0

TDH

TWPH TDS

TWP

TAH

TAS

TCH

TCS

BEF#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

AMSF = Most Significant Flash Address

Note: X can be VIL or VIH, but no other value

1209 F07.0

ADDRESSES AMSF-0

DQ15-0

TDH

TCPH TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

BEF#

TBP

AMSF = Most Significant Flash Address

Note: X can be VIL or VIH, but no other value

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM

FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM

1209 F08.0

ADDRESSES A

MSF-0

Data Data# Data# Data

WE#

OE#

BEF#

OEH

OES

AMSF = Most Significant Flash Address

1209 F09.0

ADDRESSES AMSF-0

DQ6

WE#

OE#

BEF#

TOE

TOEH

TBE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

MSF

= Most Significant Flash Address

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM

1209 F10.0

ADDRESS AMSF-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 12)

X can be VIL or VIH, but no other value

AMSF = Most Significant Flash Address

1209 F11.0

ADDRESSES AMSF-0

DQ15-0

WE#

SW0

Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12)

X can be VIL or VIH, but no other value

SAX = Sector Address

MSF = Most Significant Flash Address

SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

BEF#

SIX-WORD CODE FOR SECTOR-ERASE

TSE

TWP

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 13: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM

FIGURE 14: SOFTWARE ID ENTRY AND READ

1209 F12.1

ADDRESSES AMSF-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-WORD CODE FOR BLOCK-ERASE

TBE

TWP

Note: The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12)

X can be V

or V

, but no other value

= Block Address

MSF

= Most Significant Flash Address

1209 F13.4

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2 MFG ID

5555 2AAA 5555 0000 0001

OE#

BEF#

THREE-WORD SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

DEVICE ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value

Device ID = 2789H for SST32HF202,

2780H for SST32HF402,

2781H for SST32HF802

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 15: SOFTWARE ID EXIT AND RESET

1209 F14.0

ADDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-WORD SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

BEF#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 16: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 17: A TEST LOAD EXAMPLE

1209 F15.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te s t

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1209 F16.0

TO TESTER

TO DUT

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 18: WORD-PROGRAM ALGORITHM

1209 F17.0

Start

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXA0H

Address: 5555H

Write Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be V

or V

, but no other value.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 19: WAIT OPTIONS

1209 F18.0

Wait TBP,

TSCE, or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 20: SOFTWARE PRODUCT COMMAND FLOWCHARTS

1209 F19.0

Write data: XXAAH

Address: 5555H

Software Product ID Entry

Command Sequence

Write data: XX55H

Address: 2AAAH

Write data: XX90H

Address: 5555H

Wait TIDA

Read Software ID

Write data: XXAAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Write data: XX55H

Address: 2AAAH

Write data: XXF0H

Address: 5555H

Write data: XXF0H

Address: XXXXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 21: ERASE COMMAND SEQUENCE

1209 F20.0

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

X can be VIL or VIH, but no other value.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

FIGURE 22: CONCURRENT OPERATION FLOWCHART

1209 F21.0

Load SDP

Command

Sequence

Concurrent

Operation

Flash

Program/Erase

Initiated

Wait for End of

Write Indication

Flash Operation

Completed

End Concurrent

Operation

Read or Write

SRAM

End

Wait

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

SST32HFxxx- XXX -XX-XXXX

Package Attribute

E1 = non-Pb

Package Modifier

K = 48 balls

Package Type

L3 = LFBGA (6mm x 8mm x 1.4mm)

LB = LBGA (10mm x 12mm x 1.4mm)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

SRAM

2 = 2 Mbit SRAM

Density

20 = 2 Mbit Flash

40 = 4 Mbit Flash

80 = 8 Mbit Flash

Voltage

H = 2.7-3.3V

Product Series

32 = MPF + SRAM ComboMemory

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

Valid combinations for SST32HF202

SST32HF202-70-4C-L3K

SST32HF202-70-4C-L3KE

SST32HF202-70-4E-L3K

SST32HF202-70-4E-L3KE

Valid combinations for SST32HF402

SST32HF402-70-4C-L3K

SST32HF402-70-4C-L3KE

SST32HF402-70-4E-L3K

SST32HF402-70-4E-L3KE

Valid combinations for SST32HF802

SST32HF802-70-4C-L3K SST32HF802-70-4C-LBK

SST32HF802-70-4C-L3KE SST32HF802-70-4C-LBKE

SST32HF802-70-4E-L3K SST32HF802-70-4E-LBK

SST32HF802-70-4E-L3KE SST32HF802-70-4E-LBKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

PACKAGING DIAGRAMS

48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM

SST PACKAGE CODE: L3K

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.30 ± 0.10

0.12

0.80

4.00

0.80

5.60

48-lfbga-L3K-6x8-450mic-5

Note: 1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1',

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

0.45 ± 0.05

(48X)

A1 CORNER

6.00 ± 0.20

A1 CORNER

8.00 ± 0.20

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM

SST PACKAGE CODE: LBK

H G F E D C B A

A B C D E F G H

BOTTOM VIEW

SIDE VIEW

SEATING PLANE

0.40 ± 0.05

1.4 Max

0.12

0.50 ± 0.05

(48X)

1.0

5.0

1.0

7.0

48-lbga-LBK-10x12-500mic-2

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.4 mm (± 0.05 mm)

1mm

TOP VIEW

10.00 ± 0.20

12.00 ± 0.20

A1 CORNER A1 CORNER

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EOL Data Sheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

TABLE 13: REVISION HISTORY

Number Description Date

00 •2002 Data Book Feb 2002

01 •Document Control Release (SST Internal): No technical changes Apr 2002

02 •Removed the 1 Mbit SRAM devices Apr 2002

03 •Added the 0 Mbit SRAM parts

•Migrated the 8 Mbit parts from S71171 to S71209

•Added L3K package for 8 Mb parts

•Changes to Table 5 on page 10

–I

DD active Read and Write current increased to 30 mA for SRAM and Flash

– Test Conditions for Power Supply Current corrected

–I

DD active Concurrent Operation increased to 55 mA

–I

SB Standby current decreased to 40 µA on SST32HF802

– Output leakage current increased to 10 µA

Mar 2003

04 •Removed all MPNs for 0 Mbit SRAM parts and 90 ns parts (See page 27) Sep 2003

05 •2004 Data Book

•Updated L3K and LBK package diagrams

Nov 2003

06 •Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz

See Table 5 on page 10

•Added RoHS compliance information on page 1 and in the “Product Ordering Infor-

mation” on page 26

•Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on

page 9.

May 2005

07 •End-of-Life data sheet for all devices in S71209

•Recommended replacement device is SST34HF1641J in S71336

Feb 2008

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

http://store.iiic.cc/