4-Channel, 200 kSPS 12-Bit ADC
with Sequencer in 16-Lead TSSOP
Enhanced Product AD7923-EP
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-
compatible
Shutdown mode: 0.5 μA max
16-lead TSSOP package
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
Aerospace and defense
Milcom
Avionics
Unmanned systems
GENERAL DESCRIPTION
The AD7923-EP is a 12-bit, high speed, low power, 4-channel,
successive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled by
CS and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS; the conversion is also initiated at this point.
The AD7923-EP uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum with
3 V supplies and 1.5 mA maximum with 5 V supplies.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN,
with either straight binary or twos complement output coding.
FUNCTIONAL BLOCK DIAGRAM
•
•
•
•
•
•
•
•
•
•
•
•
•
V
IN
3
T/H
INPUT
MUX
SEQUENCER CONT RO L L O GIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
GND
SCLK
DOUT
DIN
CS
V
DRIVE
A
V
DD
AD7923-EP
REF
IN
V
IN
0
10190-001
Figure 1.
The AD7923-EP features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of channels
to be converted sequentially.
The serial clock (SCLK) frequency determines the conversion
time for the AD7923-EP because this is used as the master clock
to control the conversion. The conversion time can be as short
as 800 ns with a 20 MHz SCLK. Additional application and
technical information can be found in the AD7923 data sheet.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption. The
AD7923-EP offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7923-EP
dissipates just 3.6 mW of power.
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with VDRIVE Function. The VDRIVE
function allows the serial interface to connect directly to
either 3 V or 5 V processor systems independent of AVDD.
4. Flexible Power/Serial Clock Speed Management. The serial
clock determines the conversion rate, allowing the conversion
time to reduce through the serial clock speed increase. The
device also features various shutdown modes to maximize
power efficiency at lower throughput rates. Current
consumption is 0.5 μA maximum when in full shutdown.
5. No Pipeline Delay. The device features a SAR ADC with
accurate control of the sampling instant via a CS input and
once off conversion control.
AD7923-EP Enhanced Product
Rev. A | Page 2 of 9
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Description ...............................7
Typical Performance Characteristics ..............................................8
Outline Dimensions ..........................................................................9
Ordering Guide .............................................................................9
REVISION HISTORY
4/2018—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Added Enhanced Product Features Section .................................. 1
Changes to Ordering Guide ............................................................ 9
10/2011—Revision 0: Initial Version
Enhanced Product AD7923-EP
Rev. A | Page 3 of 9
SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range (EP
version): −55°C to +125°C.
Table 1.
Parameter EP Version1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
f
IN
= 50 kHz sine wave, f
SCLK
= 20 MHz
Signal-to-(Noise + Distortion) (SINAD) 70 dB min At 5 V, –40°C to +85°C
69 dB min At 5 V, 85°C to 125°C, typ 70 dB
69 dB min At 3 V typ 70 dB, –40°C to +125°C
Signal-to-Noise (SNR) 70 dB min
Total Harmonic Distortion (THD) −77 dB max At 5 V typ, −84 dB
−73 dB max At 3 V typ,−77 dB
Peak Harmonic or Spurious Noise −78 dB max At 5 V typ, −86 dB
(SFDR) −76 dB max At 3 V typ, −80 dB
Intermodulation Distortion (IMD) fA = 40.1 kHz, fB = 41.5 kHz
Second Order Terms −90 dB typ
Third Order Terms
−90
dB typ
Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel to Channel Isolation −85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ at 3 dB
1.6 MHz typ At 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity ±1 LSB max
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error ±8 LSB max Typ ±0.5 LSB
Offset Error Match ±0.5 LSB max
Gain Error ±1.5 LSB max
Gain Error Match
±0.5
LSB max
0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos
complement output coding
Positive Gain Error ±1.5 LSB max
Positive Gain Error Match ±0.5 LSB max
Zero Code Error ±8 LSB max Typ ±0.8 LSB
Zero Code Error Match ±0.5 LSB max
Negative Gain Error ±1 LSB max
Negative Gain Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to REFIN V Range bit set to 1
0 to 2 × REFIN V Range bit set to 0, AVDD = 4.75 V to 5.25 V
DC Leakage Current ±1 µA max
Input Capacitance 20 pF typ
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 µA max
REF
IN
Input Impedance
36
kΩ typ
f
SAMPLE
= 200 kSPS
AD7923-EP Enhanced Product
Rev. A | Page 4 of 9
Parameter EP Version1 Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VINH 0.7 × VDRIVE V min
Input Low Voltage, VINL 0.3 × VDRIVE V max
Input Current, IIN ±1 µA max Typ 10 nA, VIN = 0 V or VDRIVE
Input Capacitance, C
IN
2
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE – 0.2 V min ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4
V max
I
SINK
= 200 µA
Floating State Leakage Current ±1 µA max
Floating State Output Capacitance2 1 pF max
Output Coding Twos Complement Coding bit set to 0
Straight (Natural)
Binary
Coding bit set to 1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz
300 ns max Sinewave input
300 ns max Full-scale step Input
Throughput Rate 200 kSPS max
POWER REQUIREMENTS
AVDD 2.7/5.25 V min/max
VDRIVE 2.7/5.25 V min/max
IDD Digital I/Ps = 0 V or VDRIVE
During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
2.0
mA max
AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) fSAMPLE = 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
1.2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900 µA typ AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS
650 µA typ AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS
Auto Shutdown (Static) 0.5 µA max SCLK on or off (20 nA typ)
Full Shutdown Mode 0.5 µA max SCLK on or off (20 nA typ)
Power Dissipation
Normal Mode (Operational) fSAMPLE = 200 kSPS 7.5 mW max AVDD = 5 V, fSCLK = 20 MHz
3.6 mW max AVDD = 3 V, fSCLK = 20 MHz
Auto Shutdown (Static)
2.5
µW max
AV
DD
= 5 V
1.5 µW max AVDD = 3 V
Full Shutdown Mode 2.5 µW max AVDD = 5 V
1.5 µW max AVDD = 3 V
1 Temperature range: EP Version: −55°C to +125°C.
2 Sample tested at 25°C to ensure compliance.
Enhanced Product AD7923-EP
Rev. A | Page 5 of 9
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Limit at TMIN, TMAX
Parameter AVDD = 3 V AVDD = 5 V Unit Description
fSCLK2 10 10 kHz min
20 20 MHz max
tCONVERT 16 × tSCLK 16 × tSCLK
tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next
conversion
t2 10 10 ns min CS to SCLK set up time
t
33
35
ns max
Delay from CS until DOUT three-state disabled
t43 40 40 ns max Data access time after SCLK falling edge
t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width
t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width
t7 10 10 ns min SCLK to DOUT valid hold time
t
8
4
15/45
ns min/max
SCLK falling edge to DOUT high impedance
t9 10 10 ns min DIN set up time prior to SCLK falling edge
t10 5 5 ns min DIN hold time after SCLK falling edge
t11 20 20 ns min Sixteenth SCLK falling edge to CS high
t12 1 1 µs max Power-Up time from full power-down/auto shutdown mode
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 The mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish
time of the device and is independent of the bus loading.
200µA IOL
200µA IOH
1.6V
TO OUTPUT
PIN CL
50pF
10190-002
Figure 2. Load Circuit for Digital Output Timing Specification
AD7923-EP Enhanced Product
Rev. A | Page 6 of 9
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND −0.3 V to +7 V
VDRIVE to AGND −0.3 V to AVDD + 0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND −0.3 V to +7 V
Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V
REFIN to AGND
−0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except
Supplies1 ±10 mA
Operating Temperature Range (EP
Version)
−55°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package, Power Dissipation
450 mW
θJA Thermal Impedance
150.4°C/W (TSSOP)
θJC Thermal Impedance
27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec)
220°C
Pb-free Temperature, Soldering
Reflow 260(+0)°C
ESD 1.5 kV
1 Transient currents of up to 100 mA do not cause SCR latchup.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Enhanced Product AD7923-EP
Rev. A | Page 7 of 9
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIN
CS
A
GND
REF
IN
AV
DD
AV
DD
SCLK
V
DRIVE
DOUT
AGND
V
IN
2
A
GND V
IN
3
V
IN
1
V
IN
0
AGND
AD7923-EP
TOP VIEW
(Not to Scale)
10190-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the device. This clock input is also
used as the clock source for the AD7923-EP conversion process.
2 DIN Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the register on
the falling edge of SCLK.
3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923-EP
and framing the serial data transfer.
4, 8,
13, 16
AGND Analog Ground. Ground reference point for all analog circuitry on the AD7923-EP. All analog input signals and any
external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
5, 6 AVDD Analog Power Supply Input. The AVDD range for the AD7923-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range,
AVDD should be from 4.75 V to 5.25 V.
7 REFIN Reference Input for the AD7923-EP. An external reference must be applied to this input. The voltage range for the
external reference is 2.5 V ± 1% for specified performance.
12 to 9 VIN0 to VIN3 Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-
chip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and ADD0 of
the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to be programmed.
The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 × REFIN as selected via the range
bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup.
14 DOUT Data Out. Logic Output. The conversion result from the AD7923-EP is provided on this output pin as a serial data
stream. The AD7923-EP serial data stream consists of two leading 0s, and two address bits indicating which channel
the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be
selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked
out of the AD7923-EP on the SCLK falling edge.
15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface
operates.
AD7923-EP Enhanced Product
Rev. A | Page 8 of 9
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (kHz)
SNR (dB)
–10
–50
–30
–70
–90
–110
0 10203040 6070809050 100
4096 POINT FFT
AVDD = 4.75V
fSAMPLE = 200kSPS
fIN = 50 kHz
SINAD = 70.714dB
THD = –82.853dB
SFDR = –84.815dB
10190-004
Figure 4. Dynamic Performance at 200 kSPS
INPUT FREQUENCY (kHz)
THD (dB)
–
55
–95
–90
–85
–80
–75
–70
–65
–60
10 100
f
SAMPLE
= 200kSPS
T
A
= 25°C
AV
DD
= 5.25V
RANGE = 0V TO REF
IN
R
IN
= 100Ω
R
IN
= 1000Ω
R
IN
= 10Ω
R
IN
=50Ω
10190-005
Figure 5. THD vs. Analog Input Frequency for Various Source Impedances
CODE
INL ERROR (LSB)
1.0
0.6
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 3584 4096
AV
DD
= V
DRIVE
= 5V
TEMP = 25°C
10190-006
Figure 6. Typical INL
CODE
DNL ERROR (LSB)
1.0
0.6
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 3584 4096
AV
DD
= V
DRIVE
= 5V
TEMP = 25°C
10190-007
Figure 7. Typical DNL
Enhanced Product AD7923-EP
Rev. A | Page 9 of 9
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM PLI ANT T O JEDEC S TANDARDS M O-153-AB
Figure 8. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Linearity Error (LSB)2 Package Description
Package
Option
AD7923SRU-EP −55°C to +125°C ±1 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
AD7923SRU-EP-RL7 −55°C to +125°C ±1 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
AD7923SRUZ-EP
−55°C to +125°C
±1
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
AD7923SRUZ-EP-RL7 −55°C to +125°C ±1 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
1 Z = RoHS Compliant Part
2 Linearity error refers to integral linearity error.
©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10190-0-4/18(A)