DS1644/DS1644P
Nonvolatile Timekeeping RAM
DS1644/DS1644P
031698 1/12
FEATURES
•Integrated NV SRAM, real time clock, crystal, power–
fail control circuit and lithium energy source
•Clock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
•Totally nonvolatile with over 10 years of operation in
the absence of power
•Access time of 120 ns and 150 ns
•BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100
•Power–fail write protection allows for ±10% VCC pow-
er supply tolerance
•DS1644 only (DIP Module)
– Upward compatible with the DS1643 Timekeep-
ing RAM to achieve higher RAM density
– Standard JEDEC Byte–wide 32K x 8 static RAM
pinout
•DS1644P only (PowerCap Module Board)
– Surface mountable package for direct connec-
tion to PowerCap containing battery and crystal
– Replaceable battery (PowerCap)
– Power–fail Output
– Pin for pin compatible with other densities of
DS164XP Timekeeping RAM
ORDERING INFORMATION
DS1644–XXX
–120 120 ns access
150 ns access–150
*DS1644P–XXX
–120 120 ns access
150 ns access–150
28–pin DIP module
34–pin PowerCap Module Board
*DS9034PCX (Power Cap) Required;
must be ordered separately
PIN ASSIGNMENT
OE
CE
WE
PFO
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A13
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
WE
OE
CE
28–PIN ENCAPSULATED PACKAGE
(720 MIL EXTENDED)
1
2
3
4
5
6
7
8
9
10
11
12
13
34
33
32
31
30
29
28
27
26
25
24
23
22
14
15
16
17
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
NC
NC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
34–PIN POWERCAP MODULE BOARD
X1 GND VBAT X2
(USES DS9034PCX POWERCAP)
PIN DESCRIPTION
A0–A14 – Address Input
CE – Chip Enable
OE – Output Enable
WE – Write Enable
VCC – +5 Volts
GND – Ground
DQ0–DQ7 – Data Input/Output
NC – No Connection
PFO – Power–fail Output (DS1644P only)
X1, X2 – Crystal Connection
VBAT – Battery Connection
DS1644/DS1644P
031698 2/12
DESCRIPTION
The DS1644 is a 32K x 8 nonvolatile static RAM with a
full function real time clock which are both accessible in
a Byte–wide format. The nonvolatile timekeeping RAM
is function equivalent to any JEDEC standard 32K x 8
SRAM. The device can also be easily substituted for
ROM, EPROM and EEPROM, providing read/write
nonvolatility and the addition of the real time clock func-
tion. The real time clock information resides in the eight
uppermost RAM locations. The R TC registers contain
year, month, date, day, hours, minutes, and seconds
data in 24 hour BCD format. Corrections for the day of
the month and leap year are made automatically. The
RTC clock registers are double buffered to avoid access
of incorrect data that can occur during clock update
cycles. The double buffered system also prevents time
loss as the timekeeping countdown continues unabated
by access to time register data. The DS1644 also con-
tains its own power–fail circuitry which deselects the de-
vice when the VCC supply is in an out–of–tolerance
condition. This feature prevents loss of data from un-
predictable system operation brought on by low VCC as
errant access and update cycles are avoided.
PACKAGES
The DS1644 is available in two packages (28–pin DIP
and 34–pin PowerCap module). The 28–pin DIP style
module integrated the crystal, lithium energy source,
and silicon all in one package. The 34–pin PowerCap
Module Board is designed with contacts for connection
to a separate PowerCap (DS9034PCX) that contains
the crystal and battery. This design allows the Power-
Cap to be mounted on top of the DS1644P after the
completion of the surface mount process. Mounting the
PowerCap after the surface mount process prevents
damage to the crystal and battery due to the high tem-
peratures required for solder reflow. The PowerCap is
keyed to prevent reverse insertion. The PowerCap
Module Board and PowerCap are ordered separately
and shipped in seperate containers. The part number
for the PowerCap is DS9034PCX.
CLOCK OPERATIONS –
READING THE CLOCK
While the double buffered register structure reduces the
chance of reading incorrect data, internal updates to the
DS1644 clock registers should be halted before clock
data is read to prevent reading of data in transition.
However, halting the internal clock register updating
process does not affect clock accuracy. Updating is
halted when a one is written into the read bit, the seventh
most significant bit in the control register. As long as a
one remains in that position, updating is halted. After a
halt is issued, the registers reflect the count, that is day ,
date, and time that was current at the moment the halt
command was issued. However , the internal clock reg-
isters of the double buffered system continue to update
so that the clock accuracy is not affected by the access
of data. All of the DS1644 registers are updated simul-
taneously after the clock status is reset. Updating is
within a second after the read bit is written to zero.
DS1644 BLOCK DIAGRAM Figure 1
OSCILLA TOR AND
CLOCK COUNTDOWN
CHAIN
POWER MONITOR,
SWITCHING, AND
WRITE PROTECTION
VCC
CLOCK
REGISTERS
CE
WE
A0–A14
DQ0–DQ7
32.768 KHz
+
OE
32K X 8
NV SRAM
PFO
VBAT
DS1644/DS1644P
031698 3/12
DS1644 TRUTH TABLE Table 1
VCC CE OE WE MODE DQ POWER
5 VOLTS 10%
VIH X X DESELECT HIGH–Z STANDBY
5 VOLTS 10%
X X X DESELECT HIGH–Z STANDBY
5 VOLTS ± 10% VIL X VIL WRITE DATA IN ACTIVE
VIL VIL VIH READ DATA OUT ACTIVE
VIL VIH VIH READ HIGH–Z ACTIVE
<4.5 VOLTS
>VBAT X X X DESELECT HIGH–Z CMOS STANDBY
<VBAT X X X DESELECT HIGH–Z DATA RETENTION
MODE
SETTING THE CLOCK
The eighth bit of the control register is the write bit. Set-
ting the write bit to a one, like the read bit, halts updates
to the DS1644 registers. The user can then load them
with the correct day , date and time data in 24 hour BCD
format. Resetting the write bit to a zero then transfers
those values to the actual clock counters and allows
normal operation to resume.
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The clock oscillator may be stopped at any time. To in-
crease the shelf life, the oscillator can be turned off to
minimize current drain from the battery. The OSC bit is
the MSB for the seconds registers. Setting it to a one
stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the
frequency test bit is set to logic “1” and the oscillator is
running, the LSB of the seconds register will toggle at
512 Hz. When the seconds register is being read, the
DQ0 line will toggle at the 512 Hz frequency as long as
conditions for access remain valid (i.e., CE low , OE low,
and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1644 is guaranteed to keep time accuracy to
within ±1 minute per month at 25°C. The clock is cali-
brated at the factory by Dallas Semiconductor using
special calibration nonvolatile tuning elements. The
DS1644 does not require additional calibration, and
temperature deviations will have a negligible effect in
most applications. For this reason, methods of field
clock calibration are not available and not necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1644P and DS9034PCX are each individually
tested for accuracy . Once mounted together, the mod-
ule is guaranteed to keep time accuracy to within ±1.53
minutes per month (35 ppm) at 25°C.
DS1644/DS1644P
031698 4/12
DS1644 REGISTER MAP - BANK1 Table 2
ADDRESS
DATA
FUNCTION
ADDRESS
B7B6B5B4B3B2B1B0
FUNCTION
7FFF – – – – – – – – YEAR 00–99
7FFE X X X – – – – – MONTH 01–12
7FFD X X – – – – – – DATE 01–31
7FFC X FT X X X – – – DAY 01–07
7FFB X X – – – – – – HOUR 00–23
7FFA X – – – – – – – MINUTES 00–59
7FF9 OSC – – – – – – – SECONDS 00–59
7FF8 W R X X X X X X CONTROL A
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever WE (write
enable) is high, and CE (chip enable) is low . The device
architecture allows ripple–through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within tAA after the last address
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (tCEA) or at output enable access
time (tOEA). The state of the data input/output pins (DQ)
is controlled by CE and OE. If the outputs are activated
before tAA, the data lines are driven to an intermediate
state until tAA. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever WE and CE
are in their active state. The start of a write is referenced
to the latter occurring high to low transition of WE or CE.
The addresses must be held valid throughout the cycle.
CE or WE must return inactive for a minimum of tWR
prior to the initiation of another read or write cycle. Data
in must be valid tDS prior to the end of write and remain
valid for tDH afterward. In a typical application, the OE
signal will be high during a write cycle. However, OE
can be active provided that care is taken with the data
bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with
read data defined by the address inputs. A low transi-
tion on WE will then disable the outputs tWEZ after WE
goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the
DS1644 can be accessed as described above with read
or write cycles. However , when V CC is below the pow-
er–fail point VPF (point at which write protection occurs)
the internal clock registers and RAM are blocked from
access. This is accomplished internally by inhibiting ac-
cess via the CE signal. At this time the power–fail output
signal (PFO) will be driven active low and will remain
active until VCC returns to nominal levels. When VCC
falls below the level of the internal battery supply , power
input is switched from the VCC pin to the internal battery
and clock activity , RAM, and clock data are maintained
from the battery until VCC is returned to nominal level.
DS1644/DS1644P
031698 5/12
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –20°C to +70°C
Soldering Temperature 260°C for 10 seconds (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.0 5.5 V 1
Logic 1 Voltage All Inputs VIH 2.2 VCC+0.3 V
Logic 0 Voltage All Inputs VIL –0.3 0.8 V
DC ELECTRICAL CHARACTERISTICS (0°C ≤ tA ≤ 70°C; VCC=5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Average VCC Power Supply Cur-
rent ICC1 75 mA 3
TTL Standby Current (CE = VIH) ICC2 6mA 3
CMOS Standby Current
(CE=VCC–0.2V) ICC3 4.0 mA 3
Input Leakage Current (any input) IIL –1 +1 µA
Output Leakage Current IOL –1 +1 µA
Output Logic 1 Voltage
(IOUT = –1.0 mA) VOH 2.4 V
Output Logic 0 Voltage
(IOUT = +2.1 mA) VOL 0.4 V
Write Protection Voltage VPF 4.0 4.25 4.5 V
DS1644/DS1644P
031698 6/12
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
DS1644–120 DS1644–150
UNITS
NOTES
PARAMETER
SYMBOL
MIN MAX MIN MAX
UNITS
NOTES
Read Cycle Time tRC 120 150 ns
Address Access Time tAA 120 150 ns
CE Access Time tCEA 120 150 ns
CE Data Off Time tCEZ 40 50 ns
Output Enable Access T ime tOEA 100 120 ns
Output Enable Data Off Time tOEZ 40 50 ns
Output Enable to DQ Low–Z tOEL 5 5 ns
CE to DQ Low–Z tCEL 5 5 ns
Output Hold from Address tOH 5 5 ns
Write Cycle Time tWC 120 150 ns
Address Setup T ime tAS 0 0 ns
CE Pulse Width tCEW 100 120 ns
Address Hold from End of Write tAH1
tAH2 5
30 5
30 ns
ns 5
6
Write Pulse Width tWEW 75 90 ns
WE Data Off Time tWEZ 40 50 ns
WE or CE Inactive T ime tWR 10 10 ns
Data Setup T ime tDS 85 110 ns
Data Hold T ime High tDH1
tDH2 0
15 0
15 ns
ns 5
6
AC TEST CONDITIONS
Input Levels: 0V to 3V
T ransition Times: 5 ns
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on all pins
(except DQ) CI7 pF
Capacitance on DQ pins CDQ 10 pF
DS1644/DS1644P
031698 7/12
AC ELECTRICAL CHARACTERISTICS (POWER–UP/DOWN TIMING) (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH before Power
Down tPD 0µs
VPF (Max) to VPF (Min) VCC Fall
Time tF300 µs
VPF (Min) to VSO VCC Fall Time tFB 10 µs
VSO to VPF (Min) VCC Rise Time tRB 1µs
VPF (Min) to VPF (Max) VCC Rise
Time tR0µs
Power–Up tREC 15 25 35 ms
Expected Data Retention Time
(Oscillator On) tDR 10 years 4
DS1644 READ CYCLE TIMING
tRC tRC tWC
READ READ WRITE
tAH
tAS
tWEW
VALID INVALID OUTVALID OUT
tOEZ
tAA
tOH
tCEA
tCEL
tOEA
tOEL
A0–A14
CE
OE
WE
DQ0–DQ7
tWR
DS1644/DS1644P
031698 8/12
DS1644 WRITE CYCLE TIMING
tWC tWC tRC
WRITE WRITE READ
A0–A14
CE
OE
WE
DQ0– VALID OUTVALID INVALID IN
VALID
OUT
tAA
tAH1
tOEA
tWEZ
tAS
tCEW
tCEZ tDS tDH2
tDH1
tDS
DQ7
tWR
tWEW
tWR
tAH2
POWER–DOWN/POWER–UP TIMING
VCC
tPD
tFB
CE
DATA RETENTION
tDR
IBATT
tF
VPF (MAX)
VPF (MIN)
tREC
tR
tRB
VPF (MIN)
VSO
VSO
PFO PFO
VPF (MAX)
VPFVPF
DS1644/DS1644P
031698 9/12
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is calculated from
the date code on the device package. The date code
XXYY is the year followed by the week of the year
in which the device was manufactured. For exam-
ple, 9225, would mean the 25th week of 1992.
5. tAH1, tDH1 are measured from WE going high.
6. tAH2, tDH2 are measured from CE going high.
OUTPUT LOAD +5 VOLTS
100 pF
D.U.T.
1.8KΩ
1KΩ
7. Real–Time Clock Modules (DIP) can be successfully processed through conventional wave–soldering tech-
niques as long as temperatures as long as temperature exposure to the lithium energy source contained within
does not exceed +85°C. Post solder cleaning with water washing techniques is acceptable, provided that ultra-
sonic vibration is not used.
In addition, for the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow
oriented with the label side up (“live – bug”).
b. Hand Soldering and touch – up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds. T o solder , apply flux to the pad, heat the lead frame pad and apply solder. T o remove the part, apply
flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1644 28–PIN PACKAGE
A
1
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
1.470
37.34 1.490
37.85
0.715
18.16 0.740
18.80
0.335
8.51 0.365
9.27
0.075
1.91 0.105
2.67
0.015
0.38 0.030
0.76
0.140
3.56 0.180
4.57
0.090
2.29 0.110
2.79
0.590
14.99 0.630
16.00
0.010
0.25 0.018
0.45
0.015
0.38 0.025
0.64
C
F
GKD
H
B
E
J
28–PINPKG
DS1644/DS1644P
031698 10/12
DS1644P
DIM MIN NOM
A 0.920 0.925
B 0.980 0.985
C– –
D 0.052 0.055
E 0.048 0.050
F 0.015 0.020
G 0.025 0.027
PKG INCHES
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE: For the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow
oriented with the label side up (“live – bug”).
b. Hand Soldering and touch – up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds. T o solder , apply flux to the pad, heat the lead frame pad and apply solder. T o remove the part, apply
flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1644/DS1644P
031698 11/12
DS1644P WITH DS9034PCX ATTACHED
DIM MIN NOM
A 0.920 0.925
B 0.955 0.960
C 0.240 0.245
D 0.052 0.055
E 0.048 0.050
F 0.015 0.020
G 0.020 0.025
PKG INCHES
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DS1644/DS1644P
031698 12/12
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
INCHES
MIN NOM MAX
A – 1.050 –
B – 0.826 –
C – 0.050 –
D – 0.030 –
E – 0.112 –
A
D
B
C
E
16 PL
