935268373118 - NXP SEMICONDUCTORS

DATA SH EET

Product specification

Supersedes data of 2001 Feb 14 2001 Apr 17

INTEGRATED CIRCUITS

TDA1517ATW

8W BTL or 2×4W SEpower

amplifier

2001 Apr 17 2

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

FEATURES

•Requires very few external components

•Flexibility in use: mono Bridge-Tied Load (BTL) and

stereo Single-Ended (SE); it should be noted that in

stereo applications the outpu t s of both amplifiers are in

opposite ph as e

•High output powe r

•Low offset voltag e at ou tput (important for BTL)

•Fixed gain

•Good ripple rejection

•Mode select switch (operating, mute and standby)

•AC and DC short-circuit safe to ground and VP

•Electrostatic discharge protection

•Thermal protection

•Reverse polarity safe

•Capable of handlin g high energy on outputs (VP=0V)

•No switch-on/sw itch -off plop

•Low thermal resis ta nce.

GENERAL DESCRIPTION

The TDA1517ATW is an integrated class-AB output

amplifier contained in a plastic heatsink thin shrink small

outline package (HTSSOP20). The device is primarily

developed for multimedia applications.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VPsupply voltage 6 12 18 V

IORM repetitive peak output current −−2.5 A

Iq(tot) total quiescent current −40 80 mA

Istb standby current −0.1 100 μA

SE application

Pooutput power THD = 10%; RL=4Ω−4−W

SVRR supply voltage ripple rejection RS=0Ω46 −−dB

αcs channel separation RS=10kΩ40 55 −dB

Vn(o) noise output voltage RS=0Ω−50 −μV

⎪Zi⎪input impedance 50 −−kΩ

BTL application

Pooutput power THD = 10%; RL=8Ω−8−W

SVRR supply voltage ripple rejection RS=0Ω50 −−dB

⎪ΔVOO⎪output offset voltage −−150 mV

Vn(o)(offset) noise output offset voltage RS=0Ω−70 −μV

⎪Zi⎪input impedance 25 −−kΩ

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

TDA1517ATW HTSSOP20 plastic thermal enhanced thin shrink small outline package;

20 leads; body width 4.4 mm; exposed die pad SOT527-1

2001 Apr 17 3

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

BLOCK DIAGRAM

handbook, full pagewidth

MODE

MGU303

OUT1a

OUT1b

15 kΩ

x 1

standby

switch

mute

switch

standby

reference

voltage

18 kΩ

kΩ

mute switch Cm

power stage

VP1 VP2

not

connected

mute switch

kΩ

power stage

410 11

SGND PGND1 PGND2

OUT2a

OUT2b

non-inverting

input 1

inverting

input 2 18

SVRR 5

−

TDA1517ATW

mute

reference

voltage

input

reference

voltage

Fig.1 Block diagram.

2001 Apr 17 4

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connecte d

n.c. 2 not connecte d

IN1+ 3 non-inverting input 1

SGND 4 signal ground

SVRR 5 supply voltage ripple rejection

n.c. 6 not connecte d

n.c. 7 not connecte d

OUT1a 8 output 1a

OUT1b 9 output 1b

PGND1 10 power ground 1

PGND2 11 power ground 2

OUT2a 12 output 2a

OUT2b 13 output 2b

n.c. 14 not connecte d

VP1 15 supply voltage 1

VP2 16 supply voltage 2

MODE 17 mode select switch

IN2−18 inverting input 2

n.c. 19 not connecte d

n.c. 20 not connecte d

handbook, halfpage

TDA1517ATW

MGU302

n.c.

IN1+

SGND

SVRR

n.c.

OUT1a

OUT1b

PGND1

n.c.

IN2−

MODE

VP2

VP1

n.c.

OUT2b

OUT2a

PGND2

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

The TDA1517ATW contains two identical amplifiers with differential input stages. This device can be used for Bridge-Tied

Load (BTL) or Single-Ended (SE) applications. The gain of each amplifier is fixed at 20 dB. A special feature of this

device is the mode select switch. Since this pin has a very low input current (<4 0 μA), a low cost supply switch can be

used. With this s witch the TDA1517ATW can be switched into three modes:

•Standby: low supply current

•Mute: input signal suppressed

•Operating: normal on condition.

2001 Apr 17 5

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

LIMITING VALUES

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

THERMAL CHARACTE RISTICS

DC CHARACTERISTICS

VP=12V; T

amb =25°C; measured in Fig.3; unless otherwise specified.

Note

1. The circuit is DC adjusted at VP= 6 to 18 V an d AC operating at VP= 8.5 to 18 V.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT.

VPsupply voltage −18 V

VPSC AC and DC short-circuit-safe voltage −18 V

Vrp reverse polar ity voltage −6V

ERGoenergy handling capability at outputs VP=0V −200 mJ

IOSM non-repetitive pea k ou tput current −4A

IORM repetitive peak output current −2.5 A

Ptot total power dissipation −5W

Tvj virtual junction temperature −150 °C

Tstg storage temperature −55 +150 °C

Tamb ambient temperature −40 +85 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

tbf −−

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VPsupply voltage note 1 6.0 12 18 V

Iqquiescent current RL=∞−40 80 mA

Operating condition

VMODE(oper) mode switch voltage level 8.5 −VPV

IMODE(oper) mode switch current VMODE =12V −15 40 μA

VODC output voltage −5.7 −V

⎪ΔVOO⎪DC output offset voltage −−150 mV

Mute condition

VMODE(mute) mode switch voltage level 3.3 −6.4 V

VODC output voltage −5.7 −V

⎪ΔVOO⎪DC output offset voltage −−150 mV

Standby condition

VMODE(stb) mode switch voltage level 0 −2V

Istb standby current −0.1 100 μA

2001 Apr 17 6

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

AC CHARACTERISTICS

VP=12V; f=1kHz; T

amb =25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SE application; note 1

Pooutput power note 2

THD = 1% 2.5 3.3 −W

THD = 10% 3 4 −W

THD total harmonic distortion Po=1W −0.1 −%

fro(L) low frequency roll-off −1dB; note3 −25 −Hz

fro(H) high frequenc y roll off −1dB 20 −−kHz

GVvoltage gain 19 20 21 dB

⎪ΔGV⎪channel balance −−1dB

SVRR supply voltage ripple rejection note 4

on 46 −−dB

mute 46 −−dB

standby 80 −−dB

⎪Zi⎪input impedance 50 60 75 kΩ

Vn(o)(rms) noise output voltage (RMS value) note 5

on; RS=0Ω−50 −μV

on; RS=10kΩ−70 100 μV

mute; note 6 −50 −μV

αcs channel separation RS=10kΩ40 55 −dB

Vo(mote) output voltage in mute note 7 −−2mV

BTL application; note 8

POoutput power note 2

THD = 1% 5 6.6 −W

THD = 10% 6.5 8.0 −W

THD total harmonic distortion Po=1W −0.03 −%

fro(L) low frequency roll-off −1dB; note3 −25 −Hz

fro(H) high frequenc y roll off −1dB 20 −−kHz

GVvoltage gain 25 26 27 dB

SVRR supply voltage ripple rejection note 4

on 50 −−dB

mute 50 −−dB

standby 80 −−dB

⎪Zi⎪input impedance 25 30 38 kΩ

Vn(o)(rms) noise output voltage (RMS value) note 5

on; RS=0Ω−70 −μV

on; RS=10kΩ−100 200 μV

mute; note 6 −60 −μV

Vo(mute) output voltage in mute note 7 −−2mV

2001 Apr 17 7

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

Notes to the characteristics

1. RL=4Ω, measured in Fig.4.

2. Output power is measured directly at the output pins of the IC.

3. Frequency re sponse externally fixe d.

4. Vripple =V

ripple(max) = 2 V (p-p); RS=0Ω.

5. Noise voltage measu red in a bandwidth of 20 Hz to 20 kHz .

6. Noise output vo ltage indepe ndent of RS.

7. Vi=V

i(max) = 1 V (RMS).

8. RL=8Ω, measured in Fig.3.

APPLICATION INFORMATION

handbook, full pagewidth

MGU304

41011

8+OUT

−OUT

PGND

SGND

100

nF 1000

μF

8 Ω

VCC

TDA1517ATW

15 kΩ

10 kΩ

8.2

kΩ

15 kΩ

+IN1

MODE

470 nF

60 kΩ

VCC

STANDBY/

MUTE LOGIC

MICRO-

CONTROLLER

μc1

μc2

μc1

Mute

Standby

μc2

SHORT CIRCUIT

AND

TEMPERATURE

PROTECTION

input

reference

voltage

60 kΩ

Fig.3 BTL ap plication block diagram.

2001 Apr 17 8

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

handbook, full pagewidth

MGU305

41011

+OUT

−OUT

PGND

SGND

100

nF 1000

μF

4 Ω

VCC

TDA1517ATW

15 kΩ

10 kΩ

8.2

kΩ

15 kΩ

100

μF

1000 μF

4 Ω

1000 μF

IN1+

MODE

220 nF

60 kΩ

IN2−

220 nF

VCC

STANDBY/

MUTE LOGIC

MICRO-

CONTROLLER

μc1

μc2

μc1

Mute

Standby

μc2

SHORT CIRCUIT

AND

TEMPERATURE

PROTECTION

input

reference

voltage

60 kΩ

Fig.4 SE application block diagram.

Test conditions

Tamb =25°C; unless othe r wise specified: VP=12V, BTL

application, f = 1 kHz, RL=8Ω, fixed gain = 26 dB, audio

band-pass: 22 Hz to 22 kHz. In the figures as a function of

frequency a band-pass of 10 Hz to 80 kHz was applied.

The BTL application block diagram is shown in Fig.3. The

PCB layout [which accommodates both the mono (BTL)

and stereo (single-ended) application] is shown in Fig.6.

Printed-Circuit Board (PCB) layout and grounding

For high system perfor ma nce levels certain gro un di ng

techniques are imperative. The input reference grounds

have to be tied to their respec tive source grounds and

must have separate traces from the power ground traces;

this will separate the large (output) signal currents from

interfering with the small AC input signals. The small signal

ground traces should be located physically as far as

possible from the power ground traces. Supply and output

traces should be as w i de as possible for delivering

maximum output power.

Proper supply byp as sin g is critical for low noise

performance and high power supp ly rejection. The

respective capacitor locations sh ould be as close as

possible to the device and grounded to the power ground.

Decoupling the power supply also prevents unwanted

oscillations. For suppressing higher frequency transients

(spikes) on the supply line a capacitor with low ESR

(typical 0.1 μF) has to be placed as close as possible to the

device. For suppressing lower frequency noise and ripple

signals, a large electrolytic capacitor (e.g. 1000 μF or

greater) must be placed close to the IC.

In single-ended (stereo) applica t ion a bypass capacitor

connected to pin SVR reduc es the noise an d ripple on th e

midrail voltage. For good THD and noise performance a

low ESR capacitor is recommended.

Input configuration

It should be noted that the DC level of the input pins is

approximately 2.1 V; a coupling c apacitor is therefore

necessary.

2001 Apr 17 9

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

The formula for the cut-off frequency at the inpu t is as

follows:

thus

As can be seen it is not necessary to use high capacitor

values for the input; so th e delay during switch-on, which

is necessary for charging the input capacitors, can be

minimized. This resu lts in a goo d low freque ncy respon se

and good switch-on behavio ur.

In stereo applications (single-ende d) coupling capacitors

on both input and output are necessary. It should be noted

that the outputs of both amplifiers are in op posite phase.

Built-in protection circuits

The IC contains two types of protectio n c ircuits:

•Short-circuits the outp uts to ground, the supply to

ground and across the load: short-circuit is detected and

controlled by a SO AR protection circuit

•Thermal shut-down protection: the junction temperature

is measured by a temperature sensor. Thermal foldback

is activated at a junc tion temperature of >150 °C.

Output power

The output power as a function of supply voltage has been

measured on the output pins and at THD = 10%. The

maximum output power is limited by the maximum

allowable power dis s ip ation and the maximum ava i lable

output current, 2.5 A repetitive peak current.

Supply voltage ripple rejection

The SVRR has been measured without an electrolytic

capacitor on pin 5 and at a bandwidth of 10 Hz to 80 kHz.

The curves for operating and mute condition (respectively)

were measured with Rsource =0Ω. Only in single-ended

applications is an electrolytic capacitor (e.g. 100 μF) on

pin 5 necessary to improve th e SVRR behaviour.

Headroom

A typical music CD requires at least 12 dB (is factor 15.85)

dynamic headro om (c ompared with the average power

output) for passing the loudest portions without distortion.

The following calculation can be made for this application

at VP= 12 V and RL=8Ω: Po at THD = 0.1% is

approximately 5 W (see Fig.7).

Average listen ing level without any di stortion yields:

The power dissipation can be derived from Fig.11 for 0 dB

and 12 dB headroom.

Table 1 Power ra ting

Thus for the average listening level (music power) a power

dissipation of 2.0 W can be used for the thermal PCB

calculation; see Sectio n “Therma l behavi our ( PCB design

considerations)”.

Mode pin

For the 3 functional modes : standby, mute and operate,

the MODE pin can be driven by a 3-state logic output

stage, e.g. a microc ontroll er with some ex tra compo nents

for DC-level shifting; see Fig.10 for the respective

DC levels.

•Standby mode is activate d by a low DC lev el between

0 and 2 V. The power consumption of the IC will be

reduced to <0.12 mW.

•Mute mode is activated by a DC level between

3.3 and 6.4 V. The outputs of the amplifier will be muted

(no audio output); however the amplifier is DC biased

and the DC level of the output pins s ta ys at half the

supply voltage. The input coupling capacitors are

charged when in mute mode to avoi d pop-noise .

•The IC will be in the operating condition when the

voltage at pin MODE is between 8.5 V and VCC.

Switch-on/switch-off

To avoid audible plo ps dur i ng switch-on and switch-off of

the supply volt age, the MODE pin has to be set in standby

condition (VCC level) before the voltage is applied

(switch-on ) or removed (switch-o f f). The input and SVRR

capacitors are smoothly charged during mute mode.

The turn-on and turn -off time can be influence d by an

RC-circuit connected to the MODE pin. Switching the

device or the MODE pin rapidly on and off may cause ‘click

and pop’ no ise. This can be preven ted by proper timing on

the MODE pin. Further improvement in the BTL application

can be obtained by connecting an electrolytic capacitor

(e.g. 100 μF) between the SVRR pin and signal ground.

fIC 1

2π× RiCi

------------------------------

fIC 1

2π× 30×10 3–

×470×10 9–

------------------------------------------------------------------------------11 Hz==

RATING HEADROOM POWER

DISSIPATION

Po=5W

(THD = 0.1%) 0dB 3.5W

12 dB 2.0 W

PALL Ptot

factor

-----------------5

15.85

---------------315 mW===

2001 Apr 17 10

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

Thermal behaviour (PCB design considerations)

The typical thermal resistance [Rth(j-a)] of the IC in the

HTSSOP20 package is 37 K/W if the IC is soldered on a

printed-circuit board with double sided 35 μm copper with

a minimum area of approximately 30 cm2. The actual

usable thermal resist ance depends strongly on the

mounting method of the device on th e printed-circuit

board, the soldering method and the area and thickness of

the copper on the prin ted-circuit board.

The bottom ‘heat-spreader’ of the IC has to be soldered

efficiently on the ‘thermal land’ of the copper area of the

printed-circuit board using the re-flow so lder technique.

A number of thermal vias in the ‘thermal land’ prov ide a

thermal path to the op posite copper site of the

printed-circuit board. The size of the surface layers should

be as large as needed to dissipate the heat.

The thermal vias (0.3 mm ∅) in the ‘thermal land’ sh ou ld

not use web constru ction techniques, because those will

have high thermal resistance; continuous connection

completely around the via-h ole is re commended.

For a maximum ambient temperature of 60 °C the

following calculation can be made: for the application at

VP= 12 V and RL=8Ω the (ALL-) music power

dissipation appr oximately 2.0 W;

Tj(max) =T

amb +P×Rth(j-a) =60°C+2.0×37 = 134 °C.

Note: the above calculation ho lds for application at

‘average listening level’ music outp ut signals. Applying (or

testing) with sine wave signals will produce approximately

twice the music p ower dissipation; at worst case cond ition

this can activate the maximum temperature protection.

handbook, full pagewidth 60

K/W

10 number of 35 μm copper layers

234

CU-LAYER 2-4

MGU306

ON-BOARD-COOLING

COPPER DESIGN

CU-LAYER 1

Rth(j-a)

Rth(j-p)

Fig.5 Thermal resistance of the HTSSOP20 mounted on printed-circuit board.

Rth(j-p) curve is given for practical calculation purpose.

L = 30 mm plus vias

2001 Apr 17 11

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

handbook, full pagewidth

MGU312

IN1

sept −2000

IN2

−OUT2

Std By

+OUT1

+VP

100 nF

220 nF

1000 μF

25 V

1000 μF

16 V

100 μF/16 V

TDA

1517ATW

top view

bottom copper layout

top view

component layout

top view

top copper layout

Fig.6 Printed-circuit board layout for BTL and SE application.

For BTL applications the two 1000 μF/16 V capacitors must be replaced by 0 Ω jumpers.

2001 Apr 17 12

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

Typical performance ch aracteristics for BTL

application at VP= 12 V and RL=8Ω

handbook, halfpage

10−1

10−2

MGU307

10−210−11

THD

(%)

Po (W) 10

Fig.7 THD as a function of P o.

handbook, halfpage

10−1

10−2

MGU308

10−210−11

THD

(%)

10 f (kHz) 102

Po = 1 W

Fig.8 THD as a function of frequency.

handbook, halfpage

−80

−60

−40

−20

0MGU309

10−210−1110

f (kHz)

SVRR

(dB)

102

mute

Fig.9 SVRR as a function of frequency.

handbook, halfpage

1240810

(V)

VMODE (V)

−1

−2

−3

−4

MGU310

Fig.10 Vo as a function of VMODE.

2001 Apr 17 13

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

handbook, halfpage

010

(W)

468

Po (W)

MGU311

VP = 15 V

RL = 16 Ω

VP = 12 V

RL = 8 Ω

Fig.11 Power diss ipation as a function of Po.

handbook, halfpage

(W)

10 12 18

14 16VP (V)

MGU323

RL = 4 Ω8 Ω16 Ω

Fig.12 Po as a function of VP.

2001 Apr 17 14

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(2) Z(1)

DheLL

pywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.20

0.09 6.6

6.4 4.3

4.1

EhHE

3.1

2.9

4.5

4.3 0.65 6.6

6.2 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT527-1 MO-153

03-04-07

05-11-02

exposed die pad side

0.25

110

20 11

detail X

(A )

vMA

0 2.5 5 mm

scale

HTSSOP20: plastic thermal enhanced thin shrink small outline package; 20 leads;

body width 4.4 mm; exposed die pad SOT527-

max.

1.1

pin 1 index

2001 Apr 17 15

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth acco un t of sold er ing ICs can be found in

our “Data Handbook IC26; Integra te d Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method tha t is idea l for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-s yringe dispensing before packag e plac ement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Through put times (preheating, soldering a nd

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatur es range from

215to250°C. The top-surface temperature of the

packages sh ould preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditio ns must be

observed for optimal res ults:

•Use a double-wa ve soldering method comprising a

turbulent wave with high up ward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axi s is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board .

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be plac ed at a 45° angle to the transp ort direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adh esive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 s econ ds at up to

300 °C.

When using a dedicated tool, all other leads ca n be

soldered in one ope ration within 2 t o 5 seconds between

270 and 320 °C.

2001 Apr 17 16

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with res pect to time) and body size of th e package, there is a risk th at internal or external pack age

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circu it Packages; Section: Packing Methods ” .

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be place d at a 45° angle to the solder wave direction.

The package footprin t must incorporate solder thieves down stream and at the side cor ners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or sma ller than 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2001 Apr 17 17

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

DATA SHEET STATUS

Notes

1. Please consult the most recently issued document befor e initiating or co mpleting a design.

2. The product s ta tus of device(s) described in this do cument may have changed since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This doc ument contains data from the objective specification for product

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Production This document contains the pr oduct specification.

DISCLAIMERS

Limited warranty and liability ⎯ Information in this

document is believed to be accurate and reliable.

However, NXP Semiconduc tors does not give any

representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and

shall have no liability for the consequences of use of such

information.

In no event shall NXP Semiconductors be liable for any

indirect, incidental, punitive, special or consequential

damages (including - without limitation - lost profits, lost

savings, busin es s interru ption, costs related to the

removal or replacement of any products or rework

charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any

other legal theory.

Notwithstanding any damages that customer might incur

for any reason whatsoever, NXP Semiconductors’

aggregate and cu mulative liability towards customer for

the products described herein shall be limited in

accordance with the Terms and conditio ns of comme rcial

sale of NXP Semiconductors.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to informa tion

published in this doc ument, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereo f.

Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are

not designed, au thorized or warran ted to be suitable for

use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reasonably be

expected to result in pe rs onal injury, death or seve re

property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP

Semiconductor s pr oducts in such equi pme nt or

application s and therefor e such inclusion and / o r use is at

the customer’s own risk.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors pro du ct is su itable and fit for the

customer’s applications and products planned, as well as

for the planned a pplication and use of customer’s third

party customer(s). Customers should provide appropriate

design and opera t ing saf eg ua rd s to minimize the risks

associated with their applications and products.

NXP Semiconduc tors does n ot a ccept any liabil ity rela ted

to any default, damage, costs or problem which is based

on any weakne ss or default in t he customer’s applic ations

or products, or the application or use by customer’s third

party customer( s) . C us to m er is responsible for doing all

necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applic ations and the products or of

the application or use by customer’s third party

customer(s). NXP does not accept any liability in this

respect.

2001 Apr 17 18

NXP Semiconductors Product specification

8 W BTL or 2 ×4 W SE power amplifier TDA1517ATW

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratings only and

(proper) operation of the device at these or any other

conditions abo ve those given in th e Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the qua l ity and

reliability of the device.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold subject to the general

terms and conditio ns of commercial sale, as published at

http://www.nxp.com/profile/terms, unless other wise

agreed in a valid written ind i vidual agreement. In case an

individual agreeme nt is co nc luded only the terms and

conditions of the resp ective agreement shall apply. NXP

Semiconductors hereby expressly objects to applying the

customer’s general terms and conditions with regard to the

purchase of NXP Semicon ductors products by customer.

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyance or

implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control ⎯ This document as well as the item(s)

described he re in may be subject to export control

regulations. Export might require a prior authorization from

national auth or itie s.

Quick refer ence data ⎯ The Quick reference data is an

extract of th e product data given in the Limiting values and

Characteristics sections of this document, and as such is

not complete, exhaus tive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is au tomotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor te sted in accordanc e with automot ive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified prod ucts in automotive eq uip m en t or

applications.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such au t omo tive application s, use and

specifications, and (b) whenever customer uses the

product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at

customer’s own ris k, and (c) customer fully inde m nifies

NXP Semiconductors for any liability, damages or failed

product clai ms r esult ing fr om custo mer desi gn an d us e o f

the product for automotive ap plic ations beyond NXP

Semiconductors ’ st andard warranty and NXP

Semiconductors’ product specifications.

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Contact information

For additional information p lease visit: http://www.nxp.com

For sales offices addresses send e-mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information pr e sent ed in this documen t d oes not form part o f an y q uotation or contra ct, is b elieve d to be accurate a nd re li a ble and may be chan ged

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual pr operty rights.

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimer s. No changes were made to the tech nical content, except for package outline

drawings which were updated to the latest version. The Ordering information was modified accordingly.

Printed in The Netherlands 753503/02/pp19 Date of release : 2001 Apr 17 Document order number: 9397 750 08264