COP224C - National Semiconductor

TL/DD/8422

COP224C/COP225C/COP226C/COP244C/COP245C

Single-Chip 1k and 2k CMOS Microcontrollers

May 1992

COP224C/COP225C/COP226C/COP244C/COP245C

Single-Chip 1k and 2k CMOS Microcontrollers

General Description

The COP224C, COP225C, COP226C, COP244C and

COP245C fully static, Single-Chip CMOS Microcontrollers

are members of the COPSTM family, fabricated using dou-

ble-poly, silicon gate microCMOS technology. These Con-

troller Oriented Processors are complete microcomputers

containing all system timing, internal logic, ROM, RAM, and

I/O necessary to implement dedicated control functions in a

variety of applications. Features include single supply oper-

ation, a variety of output configuration options, with an in-

struction set, internal architecture and I/O scheme de-

signed to facilitate keyboard input, display output and BCD

data manipulation. The COP224C and COP244C are 28 pin

chips. The COP225C and COP245C are 24-pin versions (4

inputs removed) and COP226C is 20-pin version with 15 I/O

lines. Standard test procedures and reliable high-density

techniques provide the medium to large volume customers

with a customized microcontroller at a low end-product cost.

These microcontrollers are appropriate choices in many de-

manding control environments especially those with human

interface.

COPSTM, MicrobusTM, and MICROWIRETM are trademarks of National Semiconductor Corp.

TRI-STATEÉis a registered trademark of National Semiconductor Corp.

Features

YLowest power dissipation (600 mW typical)

YFully static (can turn off the clock)

YPower saving IDLE state and HALT mode

Y4.4 ms instruction time

Y2k x 8 ROM, 128 x 4 RAM (COP244C/COP245C)

Y1k x 8 ROM, 64 x 4 RAM (COP224C/COP225C/

COP226C)

Y23 I/O lines (COP244C and COP224C)

YTrue vectored interrupt, plus restart

YThree-level subroutine stack

YSingle supply operation (4.5V to 5.5V)

YProgrammable read/write 8-bit timer/event counter

YInternal binary counter register with MICROWIRETM

serial I/O capability

YGeneral purpose and TRI-STATEÉoutputs

YLSTTL/CMOS output compatible

YSoftware/hardware compatible with COP400 family

YMilitary temperature (b55§Ctoa

125§C) operation

Block Diagram

*Not available on COP226C

TL/DD/8422– 1

FIGURE 1

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)6V

Voltage at any Pin b0.3V to VCC a0.3V

Total Allowable Source Current 25 mA

Total Allowable Sink Current 25 mA

Total Allowable Power Dissipation 150 mW

Operating Temperature Range b55§Ctoa

125§C

Storage Temperature Range b65§Ctoa

150§C

Lead Temperature

(soldering, 10 seconds) 300§C

Note:

Absolute maximum ratings indicate limits beyond

which damage to the device may occur. DC and AC electri-

cal specifications are not ensured when operating the de-

vice at absolute maximum ratings.

DC Electrical Characteristics b55§CsTAsa125§C, a4.5VsVCCsa5.5V unless otherwise specified

Parameter Conditions Min Max Units

Operating Voltage 4.5 5.5 V

Power Supply Ripple (Notes 4, 5) Peak to Peak 0.25 VCC V

Supply Current VCCe5.0V, tce4.4 ms5mA

(Note 1) (tc is instruction cycle time)

HALT Mode Current (Note 2) VCCe5.0V, FINe0 kHz 200 mA

Input Voltage Levels

RESET, CKI, D0(clock input)

Logic High 0.9 VCC V

Logic Low 0.1 VCC V

All Other Inputs

Logic High 0.7 VCC V

Logic Low 0.2 VCC V

Hi-Z Input Leakage b10 a10 mA

Input Capacitance (Note 4) 7pF

Output Voltage Levels (except CKO) Standard Outputs

LSTTL Operation VCCe5.0Vg10%

Logic High IOHeb100 mA 2.7 V

Logic Low IOLe400 mA 0.6 V

CMOS Operation

Logic High IOHeb10 mAV

CCb0.2 V

Logic Low IOLe10 mA 0.2 V

CKO Current Levels (As Clock Out)

Sink d4 0.2 mA

d8 CKIeVCC,V

OUTeVCC 0.4 mA

d16 (0.8 mA

Source d4b0.2 mA

d8 CKIe0V, VOUTe0V b0.4 mA

d16 (b0.8 mA

Allowable Sink/Source Current per Pin 5 mA

(Note 6)

Allowable Loading on CKO (as HALT) 50 pF

Current Needed to Over-Ride HALT

(Note 3)

To Continue VINe0.2 VCC 2.0 mA

To Halt VINe0.7 VCC 3.0 mA

TRI-STATE or Open Drain

Leakage Current b10 a10 mA

AC Electrical Characteristics b55§CsTAsa125§C, a4.5VsVCCsa5.5V unless otherwise specified.

Parameter Conditions Min Max Units

Instruction Cycle Time (tc) 4.4 DC ms

Operating CKI d4 mode DC 0.9 MHz

Frequency d8 mode DC 1.8 MHz

d16 mode (DC 3.6 MHz

Duty Cycle (Note 4) f1e3.6 MHz 40 60 %

Rise Time (Note 4) f1e3.6 MHz External Clock 60 ns

Fall Time (Note 4) f1e3.6 MHz External Clock 40 ns

Instruction Cycle Time Re30k g5%

RC Oscillator (Note 4) Ce82 pF g5% (d4 Mode) 6 18 ms

Inputs: (See

Figure 3

) (Note 4)

tSETUP G Inputs tc/4a0.8 ms

SI Input 0.33 ms

All Others 1.9 ms

tHOLD 0.4 ms

Output Propagation Delay VOUTe1.5V, CLe100 pF, RLe5k

tPD1,t

PD0 1.4 ms

Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k

resistors. See current drain equation on page 13.

Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to VCC, L lines in TRI-STATE mode and

tied to ground, all outputs low and tied to ground.

Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.

Note 4: This parameter is not tested but guaranteed by design. Variation due to the device included.

Note 5: Voltage change must be less than 0.25 volts ina1msperiod.

Note 6: SO output sink current must be limited to keep VOL less than 0.2 VCC when part is running in order to prevent entering test mode.

RETS COP244CX DC Parameters Test Conditions 5.3V sVCC s3V Unless Otherwise Specified

Symbol Parameter

(Note 1) VCC Conditions TestÝ

SBGRP 1 SBGRP 2 SBGRP 3

Limits

(25§C)

Drift

Units

a25§Ca125§Cb55§C

Min Max Min Max Min Max

IDD1 Supply Current VDD e4V, 85 155 85 mA

FIN e64 kHz

IDD2 Halt Current VDD e4V 35 125 35 mA

Input Voltage

Reset, CKI:

VIH1 Logic High 9 VCC 9V

CC 9V

CC V

VIL1 Logic Low 1 VCC 1V

CC 1V

CC V

All Other Inputs:

VIH2 Logic High 7 VCC 7V

CC 7V

CC V

VIL2 Logic Low 2 VCC 2V

CC 2V

CC V

Output Voltage

LSTTL Operation:

VOH1 Logic High 4.75V IOH eb

100 mA 2.7 2.7 2.7 V

VOL1 Logic Low 4.75V IOL e400 mA 0.4 0.4 0.4 V

CMOS Operation:

VOH2 Logic High 4.75V IOH eb

10 mAV

CC b0.2 VCC b0.2 VCC b0.2 V

VOL2 Logic Low 4.75V IOL e10 mA 0.2 0.2 0.2 V

Output Current

IOH Logic High 3V V e0V b100 b100 b100 mA

IOL Logic Low 3V V e3V 200 200 200 mA

Input Leakage

IIN1 High-Z b2.5 2.5 b2.5 2.5 b2.5 2.5 mA

IIN2 TRI-STATE or b44b

44b

44 mA

Open Drain

RETS COP244CX DEVICE: COP244C-XXX/883 FUNCTION: 4-BIT CMOS MICROCONTROLLER

RETS COP244CX AC Parameters Test Conditions 5.3V sVCC s3V Unless Otherwise Specified

Symbol Parameter VCC Conditions TestÝ

SBGRP 9 SBGRP 10 SBGRP 11

Limits

(25§C)

Drift

Units

a25§Ca125§Cb55§C

Min Max Min Max Min Max

tCC Instruction Cycle Mode Divided by 8, 80 125 80 125 80 125 ms

Time (Note 1) VDD e3V

FIN Operating Clock VDD e3V, 64 100 64 100 64 100 kHz

Frequency (Note 1) 30% sDuty Cycle s50%

Inputs

tSETUP (Note 2) V e4.5V 2 2 2 ms

tSETUP-G Inputs 32 32 32 ms

For SKGZ & SKGBZ

(Note 2)

tHOLD (Note 1) 0.6 0.6 0.6 ms

tPD1 Output Prop Delay 4.5V RLe5k, CLe100 pF 6 6 6 ms

tPD2 (Note 1) VOUT e1.5V 6 6 6 ms

RETS COP244CX DEVICE: COP244C-XXXD/883 FUNCTION: 4-BIT CMOS MICROCONTROLLER

Note 1: Parameter tested go-no-go only.

Note 2: Guaranteed by design and not tested.

Connection Diagrams

S.O. Wide and DIP

Top View

TL/DD/8422– 2

Order Number COP226C-XXX/N

See NS Molded Package Number N20A

Order Number COP226C-XXX/D

See NS Hermetic Package Number D20A

Order Number COP226C-XXX/WM

See NS Surface Mount Package Number M20B

S.O. Wide and DIP

Top View TL/DD/8422– 3

Order Number COP225C-XXX/N

or COP245C-XXX/N

See NS Molded Package Number N24A

Order Number COP225C-XXX/D

or COP245C-XXX/D

See NS Hermetic Package Number D24C

DIP

Top View

TL/DD/8422– 4

Order Number COP224C-XXX/N

or COP244C-XXX/N

See NS Molded Package Number N28B

Order Number COP224C-XXX/D

or COP244C-XXX/D

See NS Hermetic Package Number D28C

28 PLCC

TL/DD/8422– 13

Order Number COP224C-XXX/V

or COP244C-XXX/V

See NS PLCC Package Number V28A

FIGURE 2

Pin Descriptions

Pin Description

L7–L0 8-bit bidirectional

port with TRI-STATE

G3–G0 4-bit bidirectional

I/O port

D3–D0 4-bit output port

IN3–IN0 4-bit input port

(28 pin package only)

SI Serial input or

counter input

SO Serial or general

purpose output

Pin Description

SK Logic controlled

clock output

CKI Chip oscillator input

CKO Oscillator output,

HALT I/O port or

general purpose input

RESET Reset input

VCC Most positive

power supply

GND Ground

Functional Description

The internal architecture is shown in

Figure 1

. Data paths

are illustrated in simplified form to depict how the various

logic elements communicate with each other in implement-

ing the instruction set of the device. Positive logic is used.

When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a

logic ‘‘0’’.

Caution:

The output options available on the COP224C/225C/226C

and COP244C/245C are not the same as those available

on the COP324C/325C/326C, COP344C/345C, COP424C/

425C/426C and COP444C/445C. Options not available on

the COP224C/225C/226C and COP244C/245C are: Option

2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value

0; Option 17 value 1; Option 30, Dual Clock, all values; Op-

tion 32, MicrobusTM , all values; Option 33 values 2, 4, and 6;

Option 34 all values; and Option 35 all values.

PROGRAM MEMORY

Program Memory consists of ROM, 1024 bytes for the

COP224C/225C/226C and 2048 bytes for the COP244C/

245C. These bytes of ROM may be program instructions,

constants or ROM addressing data.

ROM addressing is accomplished by an 11-bit PC register

which selects one of the 8-bit words contained in ROM. A

new address is loaded into the PC register during each in-

struction cycle. Unless the instruction is a transfer of control

instruction, the PC register is loaded with the next sequen-

tial 11-bit binary count value.

Three levels of subroutine nesting are implemented by a

three level deep stack. Each subroutine call or interrupt

pushes the next PC address into the stack. Each return

pops the stack back into the PC register.

DATA MEMORY

Data memory consists of a 512-bit RAM for the COP244C/

245C, organized as 8 data registers of 16 c4-bit digits.

RAM addressing is implemented by a 7-bit B register whose

upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits

(Bd) select 1 of 16 4-bit digits in the selected data register.

Data memory consists of a 256-bit RAM for the COP224C/

225C/226C, organized as 4 data registers of 16 c4-bits

digits. The B register is 6 bits long. Upper 2 bits (Br) select 1

of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit

digits in the selected data register. While the 4-bit contents

of the selected RAM digit (M) are usually loaded into or

from, or exchanged with, the A register (accumulator), it

may also be loaded into or from the Q latches or T counter

or loaded from the L ports. RAM addressing may also be

performed directly by the LDD and XAD instructions based

upon the immediate operand field of these instructions.

The Bd register also serves as a source register for 4-bit

data sent directly to the D outputs.

INTERNAL LOGIC

The processor contains its own 4-bit A register (accumula-

tor) which is the source and destination register for most I/O,

arithmetic, logic, and data memory access operations. It can

also be used to load the Br and Bd portions of the B regis-

ter, to load and input 4 bits of the 8-bit Q latch or T counter,

to input 4 bits of L I/O ports data, to input 4-bit G, or IN

ports, and to perform data exchanges with the SIO register.

A 4-bit adder performs the arithmetic and logic functions,

storing the results in A. It also outputs a carry bit to the 1-bit

C register, most often employed to indicate arithmetic over-

flow. The C register in conjunction with the XAS instruction

and the EN register, also serves to control the SK output.

The 8-bit T counter is a binary up counter which can be

loaded to and from M and A using CAMT and CTMA instruc-

tions. This counter may be operated in two modes depend-

ing on a mask-programmable option: as a timer or as an

external event counter. When the T counter overflows, an

Functional Description (Continued)

overflow flag will be set (see SKT and IT instructions below).

The T counter is cleared on reset. A functional block dia-

gram of the timer/counter is illustrated in

Figure 7

Four general-purpose inputs, IN3–IN0, are provided.

The D register provides 4 general-purpose outputs and is

used as the destination register for the 4-bit contents of Bd.

The G register contents are outputs to a 4-bit general-pur-

pose bidirectional I/O port.

The Q register is an internal, latched, 8-bit register, used to

hold data loaded to or from M and A, as well as 8-bit data

from ROM. Its contents are outputted to the L I/O ports

when the L drivers are enabled under program control.

The 8 L drivers, when enabled, output the contents of

latched Q data to the L I/O port. Also, the contents of L may

be read directly into A and M.

The SIO register functions as a 4-bit serial-in/serial-out shift

binary counter (depending on the contents of the EN regis-

ter). Its contents can be exchanged with A.

The XAS instruction copies C into the SKL latch. In the

counter mode, SK is the output of SKL; in the shift register

mode, SK outputs SKL ANDed with the clock.

EN is an internal 4-bit register loaded by the LEI instruction.

The state of each bit of this register selects or deselects the

particular feature associated with each bit of the EN regis-

ter:

0. The least significant bit of the enable register, EN0, se-

lects the SIO register as either a 4-bit shift register or a

4-bit binary counter. With EN0 set, SIO is an asynchro-

nous binary counter, decrementing its value by one upon

each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI

input. Each pulse must be at least two instruction cycles

wide. SK outputs the value of SKL. The SO output equals

the value of EN3. With EN0 reset, SIO is a serial shift

data present at SI goes into the least significant bit of

SIO. SO can be enabled to output the most significant bit

of SIO each cycle time. The SK outputs SKL ANDed with

the instruction cycle clock.

1. With EN1 set, interrupt is enabled. Immediately following

an interrupt, EN1 is reset to disable further interrupts.

2. With EN2 set, the L drivers are enabled to output the data

in Q to the L I/O port. Resetting EN2 disables the L driv-

ers, placing the L I/O port in a high-impedance input

state.

3. EN3, in conjunction with EN0, affects the SO output. With

EN0 set (binary counter option selected) SO will output

the value loaded into EN3. With EN0 reset (serial shift

output of the SIO shift register, outputting serial shifted

data each instruction time. Resetting EN3 with the serial

shift register option selected disables SO as the shift reg-

ister output; data continues to be shifted through SIO and

can be exchanged with A via an XAS instruction but SO

remains set to ‘‘0’’.

INTERRUPT

The following features are associated with interrupt proce-

dure and protocol and must be considered by the program-

mer when utilizing interrupts.

a. The interrupt, once recognized as explained below,

pushes the next sequential program counter address

(PCa1) onto the stack. Any previous contents at the bot-

tom of the stack are lost. The program counter is set to

hex address 0FF (the last word of page 3) and EN1 is

reset.

b. An interrupt will be recognized only on the following con-

ditions:

1. EN1 has been set.

2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction

cycles wide has occurred on the IN1input.

3. A currently executing instruction has been completed.

TL/DD/8422– 5

FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode)

TABLE I. Enable Register Modes Ð Bits EN0 and EN3

EN0 EN3 SIO SI SO SK

0 0 Shift Input to Shift 0 If SKLe1,SKeclock

0 1 Shift Input to Shift Serial If SKLe1,SKeclock

1 0 Binary Input to 0 SKeSKL

Counter Counter

1 1 Binary Input to 1 SKeSKL

Counter Counter

Functional Description (Continued)

4. All successive transfer of control instructions and suc-

cessive LBIs have been completed (e.g. if the main

program is executing a JP instruction which transfers

program control to another JP instruction, the interrupt

will not be acknowledged until the second JP instruc-

tion has been executed).

c. Upon acknowledgement of an interrupt, the skip logic

status is saved and later restored upon popping of the

stack. For example, if an interrupt occurs during the exe-

cution of ASC (Add with Carry, Skip on Carry) instruction

which results in carry, the skip logic status is saved and

program control is transferred to the interrupt servicing

routine at hex address 0FF. At the end of the interrupt

routine, a RET instruction is executed to pop the stack

and return program control to the instruction following the

original ASC. At this time, the skip logic is enabled and

skips this instruction because of the previous ASC carry.

Subroutines should not be nested within the interrupt

service routine, since their popping of the stack will en-

able any previously saved main program skips, interfering

with the orderly execution of the interrupt routine.

d. The instruction at hex address 0FF must be a NOP.

e. An LEI instruction may be put immediately before the

RET instruction to re-enable interrupts.

INITIALIZATION

The internal reset logic will initialize the device upon power-

up if the power supply rise time is less than 1 ms and if the

operating frequency at CKI is greater than 32 kHz, other-

wise the external RC network shown in

Figure 4

must be

connected to the RESET pin (the conditions in

Figure 4

must be met). The RESET pin is configured as a Schmitt

trigger input. If not used, it should be connected to VCC.

Initialization will occur whenever a logic ‘‘0’’ is applied to the

RESET input, providing it stays low for at least three instruc-

tion cycle times.

Note: If CKI clock is less than 32 kHz, the internal reset logic (option

Ý29e1) MUST be disabled and the external RC circuit must be used.

TL/DD/8422– 6

FIGURE 4. Power-Up Circuit

Upon initialization, the PC register is cleared to 0 (ROM ad-

dress 0) and the A, B, C, D, EN, IL, T and G registers are

cleared. The SKL latch is set, thus enabling SK as a clock

output. Data Memory (RAM) is not cleared upon initializa-

tion. The first instruction at address 0 must be a CLRA

(clear A register).

TIMER

There are two modes selected by mask option:

a. Time-base counter. In this mode, the instruction cycle fre-

quency generated from CKI passes through a 2-bit divide-

by-4 prescaler. The output of this prescaler increments

the 8-bit T counter thus providing a 10-bit timer. The pre-

scaler is cleared during execution of a CAMT instruction

and on reset.

For example, using a 3.58 MHz crystal with a divide-by-16

option, the instruction cycle frequency of 223.70 kHz in-

crements the 10-bit timer every 4.47 ms. By presetting the

counter and detecting overflow, accurate timeouts be-

tween 17.88 ms (4 counts) and 4.577 ms (1024 counts)

are possible. Longer timeouts can be achieved by accu-

mulating, under software control, multiple overflows.

b. External event counter. In this mode, a low-going pulse

(‘‘1’’ to ‘‘0’’) at least 2 instruction cycles wide on the IN2

input will increment the 8-bit T counter.

Note: The IT instruction is not allowed in this mode.

TL/DD/8422– 7

Crystal or Resonator

Crystal Component Values

Value R1 R2 C1(pF) C2(pF)

32 kHz 220k 20M 30 6–36

455 kHz 5k 10M 80 40

2.096 MHz 2k 1M 30 6–36

3.6 MHz 1k 1M 30 6–36

RC Controlled Oscillator

RC Cycle VCC

Time

30k 82 pF 6–18 mst4.5V

Note: 15ksRs150k

50 pFsCs150 pF

FIGURE 5. Oscillator Component Values

Functional Description (Continued)

HALT MODE

The COP244C/245C/224C/225C/226C is a FULLY STAT-

IC circuit; therefore, the user may stop the system oscillator

at any time to halt the chip. The chip may also be halted by

the HALT instruction or by forcing CKO high when it is

mask-programmed as a HALT I/O port. Once in the HALT

mode, the internal circuitry does not receive any clock sig-

nal and is therefore frozen in the exact state it was in when

halted. All information is retained until continuing. The chip

may be awakened by one of two different methods:

#Continue function: by forcing CKO low, if it mask-pro-

grammed as a HALT I/O port, the system clock is re-en-

abled and the circuit continues to operate from the point

where it was stopped.

#Restart: by forcing the RESET pin low (see Initializa-

tion).

The HALT mode is the minimum power dissipation state.

CKO PIN OPTIONS

a. Two-pin oscillatorÐ(Crystal). See

Figure 6a

In a crystal controlled oscillator system, CKO is used as

an output to the crystal network. The HALT mode may be

entered by program control (HALT instruction) which

forces CKO high, thus inhibiting the crystal network. The

circuit can be awakened only by forcing the RESET pin to

a logic ‘‘0’’ (restart).

b. One-pin oscillatorÐ(RC or external). See

Figure 6b

If a one-pin oscillator system is chosen, two options are

available for CKO:

#CKO can be selected as the HALT I/O port. In that

case, it is an I/O flip-flop which is an indicator of the

HALT status. An external signal can over-ride this pin

to start and stop the chip. By forcing a high level to

CKO, the chip will stop as soon as CKI is high and

CKO output will stay high to keep the chip stopped if

the external driver returns to high impedance state.

By forcing a low level to CKO, the chip will continue

and CKO will stay low.

#As another option, CKO can be a general purpose in-

put, read into bit 2 of A (accumulator) upon execution

of an INIL instruction.

OSCILLATOR OPTIONS

There are three basic clock oscillator configurations avail-

able as shown by

Figure 5

a. Crystal Controlled Oscillator. CKI and CKO are connect-

ed to an external crystal. The instruction cycle time equals

the crystal frequency optionally divided by 4, 8 or 16.

b. External Oscillator. The external frequency is optionally

divided by 4, 8 or 16 to give the instruction cycle time.

CKO is the HALT I/O port or a general purpose input.

c. RC Controlled Oscillator. CKI is configured as a single pin

RC controlled Schmitt trigger oscillator. The instruction

cycle equals the oscillation frequency divided by 4. CKO

is the HALT I/O port or a general purpose input.

Figure 7

shows the clock and timer diagram.

COP245C AND COP225C 24-PIN PACKAGE OPTION

If the COP244C/224C is bonded in a 24-pin package, it be-

comes the COP245C/225C, illustrated in

Figure 2

, Connec-

tion diagrams. Note that the COP245C/225C does not con-

tain the four general purpose IN inputs (IN3–IN0). Use of

this option precludes, of course, use of the IN options, inter-

rupt feature, external event counter feature.

Note: If user selects the 24-pin package, options 9, 10, 19 and 20 must be

selected as a ‘‘2’’. See option list.

COP226C 20-PIN PACKAGE OPTION

If the COP225C is bonded as 20-pin device it becomes the

COP226C. Note that the COP226C contains all the

COP225C pins except D0,D

, and G1.

Block Diagram

TL/DD/8422– 8

FIGURE 6a. Halt ModeÐTwo-Pin Oscillator

Block Diagrams (Continued)

TL/DD/8422– 9

FIGURE 6b. Halt ModeÐOne-Pin Oscillator

TL/DD/8422– 10

FIGURE 7. Clock and Timer

Instruction Set

Table II is a symbol table providing internal architecture, in-

struction operand and operation symbols used in the in-

struction set table.

TABLE II. Instruction Set Table Symbols

Symbol Definition

Internal Architecture Symbols

A 4-bit accumulator

B 7-bit RAM address register (6-bit for COP224C)

Br Upper 3 bits of B (register address)

(2-bit for COP224C)

Bd Lower 4 bits of B (digit address)

C 1-bit carry register

D 4-bit data output port

EN 4-bit enable register

G 4-bit general purpose I/O port

IL two 1-bit (IN0 and IN3) latches

IN 4-bit input port

L 8-bit TRI-STATE I/O port

M 4-bit contents of RAM addressed by B

PC 11-bit ROM address program counter

Q 8-bit latch for L port

SA,SB,SC 11-bit 3-level subroutine stack

SIO 4-bit shift register and counter

SK Logic-controlled clock output

SKL 1-bit latch for SK output

T 8-bit timer

Instruction Operand Symbols

d 4-bit operand field, 0 – 15 binary (RAM digit select)

r 3(2)-bit operand field, 0– 7(3) binary

(RAM register select)

a 11-bit operand field, 0–2047 (1023)

y 4-bit operand field, 0–15 (immediate data)

RAM(x) RAM addressed by variable x

ROM(x) ROM addressed by variable x

Operational Symbols

aPlus

bMinus

Replaces

Is exchanged with

eIs equal to

AOne’s complement of A

ZExclusive-or

: Range of values

Table III provides the mnemonic, operand, machine code

data flow, skip conditions and description of each instruc-

tion.

TABLE III. COP244C/245C Instruction Set

Machine

Mnemonic Operand Hex Language Data Flow Skip Description

Code Code Conditions

(Binary)

ARITHMETIC INSTRUCTIONS

ASC 30 À0011 À0000 ÀAaCaRAM(B)

A Carry Add with Carry, Skip on

Carry

C Carry

ADD 31 À0011 À0001 ÀAaRAM(B)

A None Add RAM to A

ADT 4A À0100 À1010 ÀAa1010

A None Add Ten to A

AISC y 5bÀ0101 ÀyÀAay

A Carry Add Immediate. Skip on

Carry (y i0)

CASC 10 À0001 À0000 ÀAaRAM(B)aC

A Carry Complement and Add with

Carry

C Carry, Skip on Carry

CLRA 00 À0000 À0000 À0

A None Clear A

COMP 40 À0100 À0000 ÀA

A None Ones complement of A to A

NOP 44 À0100 À0100 ÀNone None No Operation

RC 32 À0011 À0010 À‘‘0’’

C None Reset C

SC 22 À0010 À0010 À‘‘1’’

C None Set C

XOR 02 À0000 À0010 ÀAZRAM(B)

A None Exclusive-OR RAM with A

Instruction Set (Continued)

TABLE III. COP244C/245C Instruction Set (Continued)

Machine

Mnemonic Operand Hex Language Data Flow Skip Description

Code Code Conditions

(Binary)

TRANSFER CONTROL INSTRUCTIONS

JID FF À1111 À1111 ÀROM (PC10:8 A,M)

PC7:0 None Jump Indirect (Notes 1, 3)

JMP a 6bÀ0110 À0Àa10:8 Àa

PC None Jump

bb Àa7:0 À

JP a bb À1Àa6:0 Àa

PC6:0 None Jump within Page (Note 4)

(pages 2, 3 only)

bb À11 Àa5:0 Àa

PC5:0

(all other pages)

JSRP a bb À10 Àa5:0 ÀPCa1

SC None Jump to Subroutine Page

00010

PC10:6 (Note 5)

PC5:0

JSR a 6bÀ0110 À1Àa10:8 ÀPCa1

SC None Jump to Subroutine

bb Àa7:0 Àa

RET 48 À0100 À1000 ÀSC

PC None Return from Subroutine

RETSK 49 À0100 À1001 ÀSC

PC Always Skip Return from Subroutine

on Return then Skip

HALT 33 À0011 À0011 ÀNone HALT Processor

38 À0011 À1000 À

IT 33 À0011 À0011 ÀIDLE till Timer

39 À0011 À1001 ÀNone Overflows then Continues

MEMORY REFERENCE INSTRUCTIONS

CAMT 33 À0011 À0011 ÀA

T7:4

3F À0011 À1111 ÀRAM(B)

T3:0 None Copy A, RAM to T

CTMA 33 À0011 À0011 ÀT7:4

RAM(B)

2F À0010 À1111 ÀT3:0

A None Copy T to RAM, A

CAMQ 33 À0011 À0011 ÀA

Q7:4 None Copy A, RAM to Q

3C À0011 À1100 ÀRAM(B)

Q3:0

CQMA 33 À0011 À0011 ÀQ7:4

RAM(B) None Copy Q to RAM, A

2C À0010 À1100 ÀQ3:0

LD r b5À00 ÀrÀ0101 ÀRAM(B)

A None Load RAM into A,

(re0:3) Br Zr

Br Exclusive-OR Br with r

LDD r,d 23 À0010 À0011 ÀRAM(r,d)

A None Load A with RAM pointed

bb À0ÀrÀdÀto directly by r,d

LQID BF À1011 À1111 ÀROM(PC10:8,A,M)

Q None Load Q Indirect (Note 3)

RMB 0 4C À0100 À1100 À0

RAM(B)0None Reset RAM Bit

145

0100 À0101 À0

RAM(B)1

242

0100 À0010 À0

RAM(B)2

343

0100 À0011 À0

RAM(B)3

SMB 0 4D À0100 À1101 À1

RAM(B)0None Set RAM Bit

147

0100 À0111 À1

RAM(B)1

246

0100 À0110 À1

RAM(B)2

34B

0100 À1011 À1

RAM(B)3

Instruction Set (Continued)

TABLE III. COP244C/245C Instruction Set (Continued)

Machine

Mnemonic Operand Hex Language Data Flow Skip Description

Code Code Conditions

(Binary)

MEMORY REFERENCE INSTRUCTIONS (Continued)

STII y 7bÀ0111 ÀyÀy

RAM(B) None Store Memory Immediate

Bd a1

Bd 1 and Increment Bd

00 ÀrÀ0110 ÀRAM(B)

A None Exchange RAM with A,

(re0:3) Br Zr

Br Exclusive-OR Br with r

XAD r,d 23 À0010 À0011 ÀRAM(r,d)

A None Exchange A with RAM

bb À1ÀrÀdÀPointed to Directly by r,d

XDS r b7À00 ÀrÀ0111 ÀRAM(B)

A Bd Exchange RAM with A

(re0:3) Bdb1

Bd decrements and Decrement Bd.

Br Zr

Br past 0 Exclusive-OR Br with r

XIS r b4À00 ÀrÀ0100 ÀRAM(B)

A Bd Exchange RAM with A

(re0:3) Bda1

Bd increments and Increment Bd,

Br Zr

Br past 15 Exclusive-OR Br with r

CAB 50 À0101 À0000 ÀA

Bd None Copy A to Bd

CBA 4E À0100 À1110 ÀBd

A None Copy Bd to A

LBI r,d bb À00 ÀrÀ(d–1) Àr,d

B Skip until Load B Immediate with r,d

(re0:3: not a LBI (Note 6)

de0,9:15)

33 À0011 À0011 À

bb À1ÀrÀdÀ

(any r, any d)

LEI y 33 À0011 À0011 Ày

EN None Load EN Immediate (Note 7)

6bÀ0110 ÀyÀ

XABR 12 À0001 À0010 ÀA

Br None Exchange A with Br (Note 8)

TEST INSTRUCTIONS

SKC 20 À0010 À0000 ÀCe‘‘1’’ Skip if C is True

SKE 21 À0010 À0001 ÀAeRAM(B) Skip if A Equals RAM

SKGZ 33 À0011 À0011 ÀG3:0e0 Skip if G is Zero

21 À0010 À0001 À(all 4 bits)

SKGBZ 33 À0011 À0011 À1st byte Skip if G Bit is Zero

001

0000 À0001 ÀG0e0

111

0001 À0001 ÀG1e0

203

0000 À0011 À2nd byte G2e0

313

0001 À0011 À*G3e0

SKMBZ 0 01 À0000 À0001 ÀRAM(B)0e0 Skip if RAM Bit is Zero

111

0001 À0001 ÀRAM(B)1e0

203

0000 À0011 ÀRAM(B)2e0

313

0001 À0011 ÀRAM(B)3e0

SKT 41 À0100 À0001 ÀA time-base Skip on Timer

counter carry (Note 3)

has occurred

since last test

Instruction Set (Continued)

TABLE III. COP244C/245C Instruction Set (Continued)

Machine

Mnemonic Operand Hex Language Data Flow Skip Description

Code Code Conditions

(Binary)

INPUT/OUTPUT INSTRUCTIONS

ING 33 À0011 À0011 ÀG

A None Input G Ports to A

2A À0010 À1010 À

ININ 33 À0011 À0011 ÀIN

A None Input IN Inputs to A

28 À0010 À1000 À(Note 2)

INIL 33 À0011 À0011 ÀIL3, CKO,‘‘0’’, IL0

A None Input IL Latches to A

29 À0010 À1001 À(Note 3)

INL 33 À0011 À0011 ÀL7:4

RAM(B) None Input L Ports to RAM,A

2E À0010 À1110 ÀL3:0

OBD 33 À0011 À0011 ÀBd

D None Output Bd to D Outputs

3E À0011 À1110 À

OGI y 33 À0011 À0011 Ày

G None Output to G Ports

5bÀ0101 ÀyÀImmediate

OMG 33 À0011 À0011 ÀRAM(B)

G None Output RAM to G Ports

3A À0011 À1010 À

XAS 4F À0100 À1111 ÀA

SIO, C

SKL None Exchange A with SIO

(Note 3)

Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where

0 signifies the least significant bit (low-order, right-most bit). For example, A3indicates the most significant (left-most) bit of the 4-bit A register.

Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs.

Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.

Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,

otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.

Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP

may not jump to the last word in page 2.

Note 6: LBI is a single-byte instruction if d e0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data

minus 1

e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI

instruction should equal 15 (11112).

Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds

with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)

Note 8: For 2K ROM devices, A

Br (0

A3). For 1K ROM devices, A

Br (0,0

A3, A2).

Description of Selected Instructions

XAS INSTRUCTION

XAS (Exchange A with SIO) copies C to the SKL latch and

exchanges the accumulator with the 4-bit contents of the

SIO register. The contents of SIO will contain serial-in/seri-

al-out shift register or binary counter data, depending on the

value of the EN register. If SIO is selected as a shift register,

an XAS instruction can be performed once every 4 instruc-

tion cycles to effect a continuous data stream.

LQID INSTRUCTION

LQID (Load Q Indirect) loads the 8-bit Q register with the

contents of ROM pointed to by the 11-bit word

PC10:PC8,A,M. LQID can be used for table lookup or code

conversion such as BCD to seven-segment. The LQID in-

struction ‘‘pushes’’ the stack (PCa1

SC)

and replaces the least significant 8 bits of the PC as follows:

PC7:4, RAM(B)

PC3:0, leaving PC10, PC9 and

PC8 unchanged. The ROM data pointed to by the new ad-

dress is fetched and loaded into the Q latches. Next, the

stack is ‘‘popped’’ (SC

PC), restoring the

saved value of PC to continue sequential program execu-

tion. Since LQID pushes SB

SC, the previous contents

of SC are lost.

Note: LQID uses 2 instruction cycles if executed, one if skipped.

JID INSTRUCTION

JID (Jump Indirect) is an indirect addressing instruction,

transferring program control to a new ROM location pointed

to indirectly by A and M. It loads the lower 8 bits of the ROM

address register PC with the contents of ROM addressed by

the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not

affected by JID.

Note: JID uses 2 instruction cycles if executed, one if skipped.

SKT INSTRUCTION

The SKT (Skip On Timer) instruction tests the state of the T

counter overflow latch (see internal logic, above), executing

the next program instruction if the latch is not set. If the

latch has been set since the previous test, the next program

instruction is skipped and the latch is reset. The features

associated with this instruction allow the processor to gen-

erate its own time-base for real-time processing, rather than

relying on an external input signal.

Note: If the most significant bit of the T counter is a 1 when a CAMT instruc-

tion loads the counter, the overflow flag will be set. The following

sample of codes should be used when loading the counter:

; load T counterCAMT

; skip if overflow flag is set and reset itSKT

NOP

IT INSTRUCTION

The IT (idle till timer) instruction halts the processor and

puts it in an idle state until the time-base counter overflows.

This idle state reduces current drain since all logic (except

the oscillator and time base counter) is stopped. IT instruc-

tion is not allowed if the T counter is mask-programmed as

an external event counter (option Ý31e1).

INIL INSTRUCTION

INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0,

CKO and 0 into A. The IL3 and IL0 latches are set if a low-

going pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0

inputs since the last INIL instruction, provided the input

pulse stays low for at least two instruction cycles. Execution

of an INIL inputs IL3 and IL0 into A3 and A0 respectively,

and resets these latches to allow them to respond to subse-

quent low-going pulses on the IN3 and IN0 lines. If CKO is

mask programmed as a general purpose input, an INIL will

input the state of CKO into A2. If CKO has not been so

programmed, a ‘‘1’’ will be placed in A2. A0 is input into A1.

IL latches are cleared on reset. IL latches are not available

on the COP245C/225C, and COP226C.

INSTRUCTION SET NOTES

a. The first word of a program (ROM address 0) must be a

CLRA (Clear A) instruction.

b. Although skipped instructions are not executed, they are

still fetched from the program memory. Thus program

paths take the same number of cycles whether instruc-

tions are skipped or executed except for JID, and LQID.

c. The ROM is organized into pages of 64 words each. The

Program Counter is a 11-bit binary counter, and will count

through page boundaries. If a JP, JSRP, JID, or LQID is

the last word of a page, it operates as if it were in the next

page. For example: a JP located in the last word of a

page will jump to a location in the next page. Also, a JID

or LQID located in the last word of every fourth page (i.e.

hex address 0FF, 1FF, 2FF, 3FF, 4FF, etc.) will access

data in the next group of four pages.

Note: The COP224C/225C/226C needs only 10 bits to address its ROM.

Therefore, the eleventh bit (P10) is ignored.

Power Dissipation

The lowest power drain is when the clock is stopped. As the

frequency increases so does current. Current is also lower

at lower operating voltages. Therefore, the user should run

at the lowest speed and voltage that his application will al-

low. The user should take care that all pins swing to full

supply levels to insure that outputs are not loaded down and

that inputs are not at some intermediate level which may

draw current. Any input with a slow rise or fall time will draw

additional current. A crystal or resonator generated clock

input will draw additional current. For example, a 500 kHz

crystal input will typically draw 100 mA more than a square-

wave input. An R/C oscillator will draw even more current

since the input is a slow rising signal.

If using an external squarewave oscillator, the following

equation can be used to calculate operating current drain.

ICOeIQaVc70cFiaVc2400cFi/Dv where:

ICOechip operating current drain in microamps

IQequiescent leakage current (from curve)

FieCKI frequency in MegaHertz

Vechip VCC in volts

Dvedivide by option selected

For example at 5 volts VCC and 400 kHz (divide by 4)

ICOe120a5c70c0.4a5c2400c0.4/4

ICOe120a140a1200e1460 mA

Power Dissipation (Continued)

If an IT instruction is executed, the chip goes into the IDLE

mode until the timer overflows. In IDLE mode, the current

drain can be calculated from the following equation:

IcieIQaVc70cFi

For example, at 5 volts VCC and 400 kHz

Icie120a5c70c0.4e260 mA

The total average current will then be the weighted average

of the operating current and the idle current:

Ita eICO cTo

ToaTi aIci cTi

ToaTi

where: Itaetotal average current

ICOeoperating current

Icieidle current

Toeoperating time

Tieidle time

I/O OPTIONS

Outputs have the following optional configurations, illustrat-

ed in

Figure 8

a. Standard Ð A CMOS push-pull buffer with an N-channel

device to ground in conjunction with a P-channel device

to VCC, compatible with CMOS and LSTTL.

b. Open Drain Ð An N-channel device to ground only, al-

lowing external pull-up as required by the user’s applica-

tion.

c. Standard TRI-STATE L Output Ð A CMOS output buffer

similar to a. which may be disabled by program control.

d. Open-Drain TRI-STATE L Output Ð This has the N-chan-

nel device to ground only.

All inputs have the following option:

e. Hi-Z input which must be driven by the users logic.

All output drivers use two common devices numbered 1 to

2. Minimum and maximum current (IOUT and VOUT) curves

are given in

Figure 9

for each of these devices to allow the

designer to effectively use these I/O configurations.

a. Standard Push-Pull Output b. Open-Drain Output

TL/DD/8422– 11

c. Standard TRI-STATE ‘‘L’’ Output d. Open Drain TRI-STATE

‘‘L’’ Output

e. Hi-Z Input

FIGURE 8. Input/Output Configurations

Power Dissipation (Continued)

Minimum Sink Current

(Except CKO)

Minimum Source Current

(Except CKO) Maximum Quiescent Current

TL/DD/8422– 12

FIGURE 9. Input/Output Characteristics

Option List

The COP244C/245C/224C/225C/COP226C mask-pro-

grammable options are assigned numbers which corre-

spond with the COP244C/224C pins.

The following is a list of options. The options are pro-

grammed at the same time as the ROM pattern to provide

the user with the hardware flexibility to interface to various

I/O components using little or no external circuitry.

Caution:

The output options available on the COP224C/225C/226C

and COP244C/245C are not the same as those available

on the COP324C/325C/326C, COP344C/345C, COP424C/

425C/426C and COP444C/445C. Options not available on

the COP224C/225C/226C and COP244C/245C are: Option

2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value

0; Option 17 value 1; Option 30, Dual Clock, all values; Op-

tion 32, Microbus, all values; Option 33 values 2 4, and 6;

Option 34 all values; and Option 35 all values.

PLEASE FILL OUT THE OPTION TABLE on the next page.

Photocopy the option data and send it in with your disk or

EPROM.

Option 1e0: Ground Pin Ð no options available

Option 2: CKO Pin

e0: clock generator output to crystal/resonator

e1: HALT I/O port

e3: general purpose input, high-Z

Option 3: CKI input

e0: Crystal controlled oscillator input divide by 4

e1: Crystal controlled oscillator input divide by 8

e2: Crystal controlled oscillator input divide by 16

e4: Single-pin RC controlled oscillator (divide by 4)

e5: External oscillator input divide by 4

e6: External oscillator input divide by 8

e7: External oscillator input divide by 16

Option 4: RESET input

e1: Hi-Z input

Option 5: L7 Driver

e0: Standard TRI-STATE push-pull output

e2: Open-drain TRI-STATE output

Option 6: L6 Driver Ð (same as option 5)

Option 7: L5 Driver Ð (same as option 5)

Option 8: L4 Driver Ð (same as option 5)

Option 9: IN1 input

e1: Hi-Z input, mandatory for 28 Pin Package

e2: Mandatory for 20 and 24 Pin Packages

Option 10: IN2 input Ð (same as option 9)

Option 11e0: VCC Pin Ð no option available

Option 12: L3 Driver Ð (same as option 5)

Option 13: L2 Driver Ð (same as option 5)

Option 14: L1 Driver Ð (same as option 5)

Option 15: L0 Driver Ð (same as option 5)

Option 16: SI input Ð (same as option 4)

Option 17: SO Driver

e0: Standard push-pull output

e2: Open-drain output

Option 18: SK Driver Ð (same as option 17)

Option 19: IN0 Input Ð (same as option 9)

Option 20: IN3 Input Ð (same as option 9)

Option 21: G0 I/O Port Ð (same as option 17)

Option 22: G1 I/O Port Ð (same as option 17)

Option 23: G2 I/O Port Ð (same as option 17)

Option 24: G3 I/O Port Ð (same as option 17)

Option 25: D3 Output Ð (same as option 17)

Option 26: D2 Output Ð (same as option 17)

Option 27: D1 Output Ð (same as option 17)

Option List (Continued)

Option 28: D0 Output Ð (same as option 17)

Option 29: Internal Initialization Logic

e0: Normal operation

e1: No internal initialization logic

Option 30e0: No Option Available

Option 31: Timer

e0: Time-base counter

e1: External event counter

Option 32e0: No Option Available

Option 33: COP bonding. See note.

(1k and 2k Microcontroller)

e0: 28-pin package

e1: 24-pin package

(1k Microcontroller only)

e3: 20-pin package

e5: 24- and 20-pin package

Note:ÐIf opt. Ý33e0 then opt. Ý9, 10, 19, and 20

muste1.

If opt. Ý33e1 then opt. Ý9, 10, 19 and 20 muste2, and

option Ý31 muste0.

If opt. Ý33e3 or 5 then opt. Ý9, 10, 19, 20 muste2 and

opt. Ý21, 22, 31 muste0.

Option 34e0: No Option Available

Option 35e0: No Option Available

Option Table

The following option information is to be sent to National along with the EPROM.

OPTION DATA

OPTION 1 VALUE e0IS: GROUND PIN

OPTION 2 VALUE eIS: CKO PIN

OPTION 3 VALUE eIS: CKI INPUT

OPTION 4 VALUE e1IS: RESET INPUT

OPTION 5 VALUE eIS: L7 DRIVER

OPTION 6 VALUE eIS: L6 DRIVER

OPTION 7 VALUE eIS: L5 DRIVER

OPTION 8 VALUE eIS: L4 DRIVER

OPTION 9 VALUE eIS: IN1 INPUT

OPTION 10 VALUE eIS: IN2 INPUT

OPTION 11 VALUE e0IS: VCC PIN

OPTION 12 VALUE eIS: L3 DRIVER

OPTION 13 VALUE eIS: L2 DRIVER

OPTION 14 VALUE eIS: L1 DRIVER

OPTION 15 VALUE eIS: L0 DRIVER

OPTION 16 VALUE e1IS: SI INPUT

OPTION 17 VALUE eIS: SO DRIVER

OPTION 18 VALUE eIS: SK DRIVER

OPTION DATA

OPTION 19 VALUE eIS: IN0 INPUT

OPTION 20 VALUE eIS: IN3 INPUT

OPTION 21 VALUE eIS: G0 I/O PORT

OPTION 22 VALUE eIS: G1 I/O PORT

OPTION 23 VALUE eIS: G2 I/O PORT

OPTION 24 VALUE eIS: G3 I/O PORT

OPTION 25 VALUE eIS: D3 OUTPUT

OPTION 26 VALUE eIS: D2 OUTPUT

OPTION 27 VALUE eIS: D1 OUTPUT

OPTION 28 VALUE eIS: D0 OUTPUT

OPTION 29 VALUE eIS: INT INIT LOGIC

OPTION 30 VALUE e0IS: N/A

OPTION 31 VALUE eIS: TIMER

OPTION 32 VALUE e0IS: N/A

OPTION 33 VALUE eIS: COP BONDING

OPTION 34 VALUE e0IS: N/A

OPTION 35 VALUE e0IS: N/A

Physical Dimensions inches (millimeters)

20-Lead Hermetic Dual-In-Line Package (D)

Order Number COP226C-XXX/D

NS Package Number D20A

Physical Dimensions inches (millimeters) (Continued)

24-Lead Hermetic Dual-In-Line Package (D)

Order Number COP225C-XXX/D or COP245C-XXX/D

NS Package Number D24C

28-Lead Hermetic Dual-In-Line Package (D)

Order Number COP224C-XXX/D or COP244C-XXX/D

NS Package Number D28C

Physical Dimensions inches (millimeters) (Continued)

20-Lead Surface Mount Package (M)

Order Number COP226C-XXX/WM

NS Package Number M20B

20-Lead Molded Dual-In-Line Package (N)

Order Number COP226C-XXX/N

NS Package Number N20A

Physical Dimensions inches (millimeters) (Continued)

24-Lead Molded Dual-In-Line Package (N)

Order Number COP225C-XXX/N or COP245C-XXX/N

NS Package Number N24A

28-Lead Molded Dual-In-Line Package (N)

Order Number COP224C-XXX/N or COP244C-XXX/N

NS Package Number N28B

COP224C/COP225C/COP226C/COP244C/COP245C

Single-Chip 1k and 2k CMOS Microcontrollers

Physical Dimensions inches (millimeters) (Continued)

Plastic Leaded Chip Carrier (V)

Order Number COP224C-XXX/V or COP244C-XXX/V

NS Package Number V28A

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SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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