COP224C/COP225C/COP226C/COP244C/COP245C Single-Chip 1k and 2k CMOS Microcontrollers General Description Features The COP224C, COP225C, COP226C, COP244C and COP245C fully static, Single-Chip CMOS Microcontrollers are members of the COPSTM family, fabricated using double-poly, silicon gate microCMOS technology. These Controller Oriented Processors are complete microcomputers containing all system timing, internal logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD data manipulation. The COP224C and COP244C are 28 pin chips. The COP225C and COP245C are 24-pin versions (4 inputs removed) and COP226C is 20-pin version with 15 I/O lines. Standard test procedures and reliable high-density techniques provide the medium to large volume customers with a customized microcontroller at a low end-product cost. These microcontrollers are appropriate choices in many demanding control environments especially those with human interface. Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Lowest power dissipation (600 mW typical) Fully static (can turn off the clock) Power saving IDLE state and HALT mode 4.4 ms instruction time 2k x 8 ROM, 128 x 4 RAM (COP244C/COP245C) 1k x 8 ROM, 64 x 4 RAM (COP224C/COP225C/ COP226C) 23 I/O lines (COP244C and COP224C) True vectored interrupt, plus restart Three-level subroutine stack Single supply operation (4.5V to 5.5V) Programmable read/write 8-bit timer/event counter Internal binary counter register with MICROWIRETM serial I/O capability General purpose and TRI-STATEE outputs LSTTL/CMOS output compatible Software/hardware compatible with COP400 family Military temperature (b55 C to a 125 C) operation COPSTM , MicrobusTM , and MICROWIRETM are trademarks of National Semiconductor Corp. TRI-STATEE is a registered trademark of National Semiconductor Corp. Block Diagram * Not available on COP226C TL/DD/8422 - 1 FIGURE 1 C1995 National Semiconductor Corporation TL/DD/8422 RRD-B30M105/Printed in U. S. A. COP224C/COP225C/COP226C/COP244C/COP245C Single-Chip 1k and 2k CMOS Microcontrollers May 1992 Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) b 55 C to a 125 C b 65 C to a 150 C Lead Temperature (soldering, 10 seconds) 300 C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 6V Voltage at any Pin Total Allowable Source Current Total Allowable Sink Current Total Allowable Power Dissipation Operating Temperature Range Storage Temperature Range b 0.3V to VCC a 0.3V 25 mA 25 mA 150 mW DC Electrical Characteristics b55 CsTAs a 125 C, a 4.5VsVCCs a 5.5V unless otherwise specified Parameter Conditions Operating Voltage Power Supply Ripple (Notes 4, 5) Peak to Peak Supply Current (Note 1) VCC e 5.0V, tc e 4.4 ms (tc is instruction cycle time) HALT Mode Current (Note 2) VCC e 5.0V, FIN e 0 kHz Input Voltage Levels RESET, CKI, D0 (clock input) Logic High Logic Low All Other Inputs Logic High Logic Low Min Max Units 4.5 5.5 0.25 VCC V V 5 mA 200 mA 0.1 VCC V V 0.2 VCC V V a 10 mA 7 pF 0.6 V V 0.2 V V 0.9 VCC 0.7 VCC Hi-Z Input Leakage b 10 Input Capacitance (Note 4) Output Voltage Levels (except CKO) LSTTL Operation Logic High Logic Low CMOS Operation Logic High Logic Low CKO Current Levels (As Clock Out) d4 Sink d8 d 16 d4 Source d8 d 16 ( ( Standard Outputs VCC e 5.0V g 10% IOH eb100 mA IOL e 400 mA IOH eb10 mA IOL e 10 mA 2.7 VCCb0.2 CKI e VCC, VOUT e VCC CKI e 0V, VOUT e 0V 0.2 0.4 0.8 b 0.2 b 0.4 b 0.8 mA mA mA mA mA mA Allowable Sink/Source Current per Pin (Note 6) 5 mA Allowable Loading on CKO (as HALT) 50 pF 2.0 3.0 mA mA a 10 mA Current Needed to Over-Ride HALT (Note 3) To Continue To Halt VIN e 0.2 VCC VIN e 0.7 VCC TRI-STATE or Open Drain Leakage Current b 10 2 AC Electrical Characteristics b55 CsTAs a 125 C, a 4.5VsVCCs a 5.5V unless otherwise specified. Parameter Conditions Min Max Instruction Cycle Time (tc) 4.4 DC ms Operating CKI Frequency DC DC DC 0.9 1.8 3.6 MHz MHz MHz 40 d 4 mode d 8 mode d 16 mode Duty Cycle (Note 4) ( f1 e 3.6 MHz Units 60 % Rise Time (Note 4) f1 e 3.6 MHz External Clock 60 ns Fall Time (Note 4) f1 e 3.6 MHz External Clock 40 ns Instruction Cycle Time RC Oscillator (Note 4) R e 30k g 5% C e 82 pF g 5% ( d 4 Mode) 18 ms Inputs: (See Figure 3 ) (Note 4) tSETUP 6 G Inputs SI Input All Others tc/4 a 0.8 0.33 1.9 0.4 tHOLD Output Propagation Delay tPD1, tPD0 ms ms ms ms VOUT e 1.5V, CL e 100 pF, RL e 5k 1.4 ms Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k resistors. See current drain equation on page 13. Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to VCC, L lines in TRI-STATE mode and tied to ground, all outputs low and tied to ground. Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop. Note 4: This parameter is not tested but guaranteed by design. Variation due to the device included. Note 5: Voltage change must be less than 0.25 volts in a 1 ms period. Note 6: SO output sink current must be limited to keep VOL less than 0.2 VCC when part is running in order to prevent entering test mode. RETS COP244CX DC Parameters Test Conditions 5.3V s VCC s 3V Unless Otherwise Specified Symbol Parameter (Note 1) VCC Conditions SBGRP 1 a 25 C SBGRP 2 a 125 C SBGRP 3 b 55 C Min Min Min TestY Max Max Drift Limits Units Max (25 C) IDD1 Supply Current VDD e 4V, FIN e 64 kHz 85 155 85 mA IDD2 Halt Current VDD e 4V 35 125 35 mA 1 VCC V V 2 VCC V V 0.4 V V 0.2 V V VIH1 VIL1 VIH2 VIL2 Input Voltage Reset, CKI: Logic High Logic Low All Other Inputs: Logic High Logic Low VOH2 VOL2 Output Voltage LSTTL Operation: Logic High Logic Low CMOS Operation: Logic High Logic Low IOH IOL Output Current Logic High Logic Low VOH1 VOL1 IIN1 IIN2 9 VCC 7 VCC 4.75V IOH e b100 mA 4.75V IOL e 400 mA 2.7 4.75V IOH e b10 mA 4.75V IOL e 10 mA VCC b 0.2 3V 3V V e 0V V e 3V 7 VCC 7 VCC 2 VCC 2.7 0.4 2.7 0.4 VCC b 0.2 0.2 VCC b 0.2 0.2 b 100 b 100 b 100 200 200 200 b 2.5 b4 DEVICE: COP244C-XXX/883 9 VCC 1 VCC 2 VCC Input Leakage High-Z TRI-STATE or Open Drain RETS COP244CX 9 VCC 1 VCC 2.5 b 2.5 4 b4 2.5 b 2.5 2.5 mA 4 b4 4 mA FUNCTION: 4-BIT CMOS MICROCONTROLLER 3 mA mA RETS COP244CX AC Parameters Test Conditions 5.3V s VCC s 3V Unless Otherwise Specified SBGRP 9 a 25 C SBGRP 10 a 125 C SBGRP 11 b 55 C Min Max Min Max Min Drift Limits Units Max (25 C) tCC Instruction Cycle Time (Note 1) Mode Divided by 8, VDD e 3V 80 125 80 125 80 125 FIN Operating Clock Frequency (Note 1) VDD e 3V, 30% s Duty Cycle s 50% 64 100 64 100 64 100 Symbol Parameter VCC Inputs tSETUP (Note 2) tSETUP-G Inputs For SKGZ & SKGBZ (Note 2) tHOLD (Note 1) tPD1 tPD2 Output Prop Delay (Note 1) RETS COP244CX Conditions TestY V e 4.5V 2 32 2 32 0.6 R e 5k, CL e 100 pF 4.5V L VOUT e 1.5V 0.6 6 6 DEVICE: COP244C-XXXD/883 2 32 ms 6 6 FUNCTION: 4-BIT CMOS MICROCONTROLLER Note 1: Parameter tested go-no-go only. Note 2: Guaranteed by design and not tested. 4 kHz ms ms 0.6 6 6 ms ms ms Connection Diagrams S.O. Wide and DIP S.O. Wide and DIP Top View Top View TL/DD/8422 - 3 Order Number COP225C-XXX/N or COP245C-XXX/N See NS Molded Package Number N24A TL/DD/8422-2 Order Number COP226C-XXX/N See NS Molded Package Number N20A Order Number COP225C-XXX/D or COP245C-XXX/D See NS Hermetic Package Number D24C Order Number COP226C-XXX/D See NS Hermetic Package Number D20A Order Number COP226C-XXX/WM See NS Surface Mount Package Number M20B DIP 28 PLCC Top View TL/DD/8422 - 13 TL/DD/8422-4 Order Number COP224C-XXX/V or COP244C-XXX/V See NS PLCC Package Number V28A Order Number COP224C-XXX/N or COP244C-XXX/N See NS Molded Package Number N28B Order Number COP224C-XXX/D or COP244C-XXX/D See NS Hermetic Package Number D28C FIGURE 2 5 Pin Descriptions Pin Description Pin Description L7 - L0 8-bit bidirectional port with TRI-STATE SK Logic controlled clock output G3 - G0 4-bit bidirectional I/O port CKI Chip oscillator input CKO Oscillator output, HALT I/O port or general purpose input D3 - D0 4-bit output port IN3 - IN0 4-bit input port (28 pin package only) RESET Reset input SI Serial input or counter input VCC Most positive power supply SO Serial or general purpose output GND Ground Functional Description The internal architecture is shown in Figure 1 . Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic ``1'', when a bit is reset, it is a logic ``0''. Caution: The output options available on the COP224C/225C/226C and COP244C/245C are not the same as those available on the COP324C/325C/326C, COP344C/345C, COP424C/ 425C/426C and COP444C/445C. Options not available on the COP224C/225C/226C and COP244C/245C are: Option 2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value 0; Option 17 value 1; Option 30, Dual Clock, all values; Option 32, MicrobusTM , all values; Option 33 values 2, 4, and 6; Option 34 all values; and Option 35 all values. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. Data memory consists of a 256-bit RAM for the COP224C/ 225C/226C, organized as 4 data registers of 16 c 4-bits digits. The B register is 6 bits long. Upper 2 bits (Br) select 1 of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the Q latches or T counter or loaded from the L ports. RAM addressing may also be performed directly by the LDD and XAD instructions based upon the immediate operand field of these instructions. The Bd register also serves as a source register for 4-bit data sent directly to the D outputs. PROGRAM MEMORY Program Memory consists of ROM, 1024 bytes for the COP224C/225C/226C and 2048 bytes for the COP244C/ 245C. These bytes of ROM may be program instructions, constants or ROM addressing data. ROM addressing is accomplished by an 11-bit PC register which selects one of the 8-bit words contained in ROM. A new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequential 11-bit binary count value. Three levels of subroutine nesting are implemented by a three level deep stack. Each subroutine call or interrupt pushes the next PC address into the stack. Each return pops the stack back into the PC register. INTERNAL LOGIC The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most I/O, arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch or T counter, to input 4 bits of L I/O ports data, to input 4-bit G, or IN ports, and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic functions, storing the results in A. It also outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction and the EN register, also serves to control the SK output. The 8-bit T counter is a binary up counter which can be loaded to and from M and A using CAMT and CTMA instructions. This counter may be operated in two modes depending on a mask-programmable option: as a timer or as an external event counter. When the T counter overflows, an DATA MEMORY Data memory consists of a 512-bit RAM for the COP244C/ 245C, organized as 8 data registers of 16 c 4-bit digits. 6 Functional Description (Continued) overflow flag will be set (see SKT and IT instructions below). The T counter is cleared on reset. A functional block diagram of the timer/counter is illustrated in Figure 7 . SIO. SO can be enabled to output the most significant bit of SIO each cycle time. The SK outputs SKL ANDed with the instruction cycle clock. Four general-purpose inputs, IN3-IN0, are provided. The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd. The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port. The Q register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are outputted to the L I/O ports when the L drivers are enabled under program control. The 8 L drivers, when enabled, output the contents of latched Q data to the L I/O port. Also, the contents of L may be read directly into A and M. The SIO register functions as a 4-bit serial-in/serial-out shift register for MICROWIRE I/O and COPS peripherals, or as a binary counter (depending on the contents of the EN register). Its contents can be exchanged with A. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock. EN is an internal 4-bit register loaded by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register: 0. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or a 4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse (``1'' to ``0'') occurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output equals the value of EN3. With EN0 reset, SIO is a serial shift register left shifting 1 bit each instruction cycle time. The data present at SI goes into the least significant bit of 1. With EN1 set, interrupt is enabled. Immediately following an interrupt, EN1 is reset to disable further interrupts. 2. With EN2 set, the L drivers are enabled to output the data in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input state. 3. EN3, in conjunction with EN0, affects the SO output. With EN0 set (binary counter option selected) SO will output the value loaded into EN3. With EN0 reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains set to ``0''. INTERRUPT The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts. a. The interrupt, once recognized as explained below, pushes the next sequential program counter address (PC a 1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to hex address 0FF (the last word of page 3) and EN1 is reset. b. An interrupt will be recognized only on the following conditions: 1. EN1 has been set. 2. A low-going pulse (``1'' to ``0'') at least two instruction cycles wide has occurred on the IN1 input. 3. A currently executing instruction has been completed. TL/DD/8422 - 5 FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode) TABLE I. Enable Register Modes Bits EN0 and EN3 EN0 EN3 0 0 0 1 1 0 1 1 SIO Shift Register Shift Register Binary Counter Binary Counter SI SO SK Input to Shift 0 If SKL e 1,SK e clock Register If SKL e 0,SK e 0 Input to Shift Serial If SKL e 1,SK e clock Register out If SKL e 0,SK e 0 Input to 0 SK e SKL Counter Input to 1 SK e SKL Counter 7 Functional Description (Continued) 4. All successive transfer of control instructions and successive LBIs have been completed (e.g. if the main program is executing a JP instruction which transfers program control to another JP instruction, the interrupt will not be acknowledged until the second JP instruction has been executed). c. Upon acknowledgement of an interrupt, the skip logic status is saved and later restored upon popping of the stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved and program control is transferred to the interrupt servicing routine at hex address 0FF. At the end of the interrupt routine, a RET instruction is executed to pop the stack and return program control to the instruction following the original ASC. At this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Subroutines should not be nested within the interrupt service routine, since their popping of the stack will enable any previously saved main program skips, interfering with the orderly execution of the interrupt routine. d. The instruction at hex address 0FF must be a NOP. e. An LEI instruction may be put immediately before the RET instruction to re-enable interrupts. TIMER There are two modes selected by mask option: a. Time-base counter. In this mode, the instruction cycle frequency generated from CKI passes through a 2-bit divideby-4 prescaler. The output of this prescaler increments the 8-bit T counter thus providing a 10-bit timer. The prescaler is cleared during execution of a CAMT instruction and on reset. For example, using a 3.58 MHz crystal with a divide-by-16 option, the instruction cycle frequency of 223.70 kHz increments the 10-bit timer every 4.47 ms. By presetting the counter and detecting overflow, accurate timeouts between 17.88 ms (4 counts) and 4.577 ms (1024 counts) are possible. Longer timeouts can be achieved by accumulating, under software control, multiple overflows. b. External event counter. In this mode, a low-going pulse (``1'' to ``0'') at least 2 instruction cycles wide on the IN2 input will increment the 8-bit T counter. Note: The IT instruction is not allowed in this mode. INITIALIZATION The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 4 must be connected to the RESET pin (the conditions in Figure 4 must be met). The RESET pin is configured as a Schmitt trigger input. If not used, it should be connected to VCC. Initialization will occur whenever a logic ``0'' is applied to the RESET input, providing it stays low for at least three instruction cycle times. Note: If CKI clock is less than 32 kHz, the internal reset logic (option Y29 e 1) MUST be disabled and the external RC circuit must be used. TL/DD/8422 - 7 Crystal or Resonator Crystal Value R1 Component Values R2 C1(pF) C2(pF) 32 kHz 455 kHz 2.096 MHz 3.6 MHz 220k 5k 2k 1k 20M 10M 1M 1M 30 80 30 30 6 - 36 40 6 - 36 6 - 36 TL/DD/8422-6 FIGURE 4. Power-Up Circuit RC Controlled Oscillator Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, IL, T and G registers are cleared. The SKL latch is set, thus enabling SK as a clock output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA (clear A register). R C Cycle Time VCC 30k 82 pF 6 - 18 ms t 4.5V Note: 15k s R s 150k 50 pF s C s 150 pF FIGURE 5. Oscillator Component Values 8 Functional Description (Continued) the external driver returns to high impedance state. By forcing a low level to CKO, the chip will continue and CKO will stay low. HALT MODE The COP244C/245C/224C/225C/226C is a FULLY STATIC circuit; therefore, the user may stop the system oscillator at any time to halt the chip. The chip may also be halted by the HALT instruction or by forcing CKO high when it is mask-programmed as a HALT I/O port. Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted. All information is retained until continuing. The chip may be awakened by one of two different methods: # As another option, CKO can be a general purpose input, read into bit 2 of A (accumulator) upon execution of an INIL instruction. OSCILLATOR OPTIONS There are three basic clock oscillator configurations available as shown by Figure 5 . a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals the crystal frequency optionally divided by 4, 8 or 16. b. External Oscillator. The external frequency is optionally divided by 4, 8 or 16 to give the instruction cycle time. CKO is the HALT I/O port or a general purpose input. c. RC Controlled Oscillator. CKI is configured as a single pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO is the HALT I/O port or a general purpose input. # Continue function: by forcing CKO low, if it mask-programmed as a HALT I/O port, the system clock is re-enabled and the circuit continues to operate from the point where it was stopped. # Restart: by forcing the RESET pin low (see Initialization). The HALT mode is the minimum power dissipation state. CKO PIN OPTIONS a. Two-pin oscillator(Crystal). See Figure 6a . In a crystal controlled oscillator system, CKO is used as an output to the crystal network. The HALT mode may be entered by program control (HALT instruction) which forces CKO high, thus inhibiting the crystal network. The circuit can be awakened only by forcing the RESET pin to a logic ``0'' (restart). b. One-pin oscillator(RC or external). See Figure 6b . Figure 7 shows the clock and timer diagram. COP245C AND COP225C 24-PIN PACKAGE OPTION If the COP244C/224C is bonded in a 24-pin package, it becomes the COP245C/225C, illustrated in Figure 2 , Connection diagrams. Note that the COP245C/225C does not contain the four general purpose IN inputs (IN3 - IN0). Use of this option precludes, of course, use of the IN options, interrupt feature, external event counter feature. If a one-pin oscillator system is chosen, two options are available for CKO: Note: If user selects the 24-pin package, options 9, 10, 19 and 20 must be selected as a ``2''. See option list. # CKO can be selected as the HALT I/O port. In that case, it is an I/O flip-flop which is an indicator of the HALT status. An external signal can over-ride this pin to start and stop the chip. By forcing a high level to CKO, the chip will stop as soon as CKI is high and CKO output will stay high to keep the chip stopped if COP226C 20-PIN PACKAGE OPTION If the COP225C is bonded as 20-pin device it becomes the COP226C. Note that the COP226C contains all the COP225C pins except D0, D1, G0, and G1. Block Diagram TL/DD/8422 - 8 FIGURE 6a. Halt ModeTwo-Pin Oscillator 9 Block Diagrams (Continued) TL/DD/8422 - 9 FIGURE 6b. Halt ModeOne-Pin Oscillator TL/DD/8422 - 10 FIGURE 7. Clock and Timer 10 Instruction Set Table II is a symbol table providing internal architecture, instruction operand and operation symbols used in the instruction set table. Instruction Operand Symbols d r 4-bit operand field, 0 - 15 binary (RAM digit select) 3(2)-bit operand field, 0 - 7(3) binary (RAM register select) a 11-bit operand field, 0 - 2047 (1023) y 4-bit operand field, 0 - 15 (immediate data) RAM(x) RAM addressed by variable x ROM(x) ROM addressed by variable x TABLE II. Instruction Set Table Symbols Symbol Definition Internal Architecture Symbols A B Br 4-bit accumulator 7-bit RAM address register (6-bit for COP224C) Upper 3 bits of B (register address) (2-bit for COP224C) Bd Lower 4 bits of B (digit address) C 1-bit carry register D 4-bit data output port EN 4-bit enable register G 4-bit general purpose I/O port IL two 1-bit (IN0 and IN3) latches IN 4-bit input port L 8-bit TRI-STATE I/O port M 4-bit contents of RAM addressed by B PC 11-bit ROM address program counter Q 8-bit latch for L port SA,SB,SC 11-bit 3-level subroutine stack SIO 4-bit shift register and counter SK Logic-controlled clock output SKL 1-bit latch for SK output T 8-bit timer Operational Symbols a b x Y e A Z : Plus Minus Replaces Is exchanged with Is equal to One's complement of A Exclusive-or Range of values Table III provides the mnemonic, operand, machine code data flow, skip conditions and description of each instruction. TABLE III. COP244C/245C Instruction Set Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description ARITHMETIC INSTRUCTIONS ASC 30 A 0011 A 0000 A A a C a RAM(B) x A Carry x C Carry Add with Carry, Skip on Carry ADD 31 A 0011 A 0001 A A a RAM(B) x A None Add RAM to A ADT 4A A 0100 A 1010 A A a 1010 x A None Add Ten to A 5b A 0101 A AayxA Carry Add Immediate. Skip on Carry (y i 0) CASC 10 A 0001 A 0000 A A a RAM(B) a C x A Carry x C Carry Complement and Add with Carry, Skip on Carry CLRA 00 A 0000 A 0000 A 0xA None Clear A COMP 40 A 0100 A 0000 A AxA None Ones complement of A to A NOP 44 A 0100 A 0100 A None None No Operation RC 32 A 0011 A 0010 A ``0'' x C None Reset C SC 22 A 0010 A 0010 A ``1'' x C None Set C XOR 02 A 0000 A 0010 A A Z RAM(B) x A None Exclusive-OR RAM with A AISC y y A 11 Instruction Set (Continued) TABLE III. COP244C/245C Instruction Set (Continued) Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description TRANSFER CONTROL INSTRUCTIONS JID FF A 1111 A 1111 A ROM (PC10:8 A,M) x PC7:0 None Jump Indirect (Notes 1, 3) JMP a 6b bb A 0110 A 0 A a10:8 A A a7:0 A a x PC None Jump JP a bb A 1 A a6:0 A (pages 2, 3 only) or A 11 A a5:0 A (all other pages) a x PC6:0 None Jump within Page (Note 4) bb a x PC5:0 JSRP a bb A 10 A a5:0 A PC a 1 x SA x SB x SC 00010 x PC10:6 a x PC5:0 None Jump to Subroutine Page (Note 5) JSR a 6b bb A 0110 A 1 A a10:8 A A a7:0 A PC a 1 x SA x SB x SC a x PC None Jump to Subroutine RET 48 A 0100 A 1000 A SC x SB x SA x PC None Return from Subroutine RETSK 49 A 0100 A 1001 A SC x SB x SA x PC Always Skip on Return Return from Subroutine then Skip HALT 33 38 33 39 A 0011 A 0011 A A 0011 A 1000 A A 0011 A 0011 A A 0011 A 1001 A None HALT Processor None IDLE till Timer Overflows then Continues IT MEMORY REFERENCE INSTRUCTIONS CAMT 33 3F A 0011 A 0011 A A 0011 A 1111 A A x T7:4 RAM(B) x T3:0 None Copy A, RAM to T CTMA 33 2F A 0011 A 0011 A A 0010 A 1111 A T7:4 x RAM(B) T3:0 x A None Copy T to RAM, A CAMQ 33 3C A 0011 A 0011 A A 0011 A 1100 A A x Q7:4 RAM(B) x Q3:0 None Copy A, RAM to Q CQMA 33 2C A 0011 A 0011 A A 0010 A 1100 A Q7:4 x RAM(B) Q3:0 x A None Copy Q to RAM, A b5 A 00 A r A 0101 A (r e 0:3) RAM(B) x A Br Z r x Br None Load RAM into A, Exclusive-OR Br with r 23 A 0010 A 0011 A A0 A r A d A RAM(r,d) x A None bb Load A with RAM pointed to directly by r,d BF A 1011 A 1111 A ROM(PC10:8,A,M) x Q SB x SC None Load Q Indirect (Note 3) LD LDD r r,d LQID RMB 0 1 2 3 4C 45 42 43 A 0100 A 1100 A A 0100 A 0101 A A 0100 A 0010 A A 0100 A 0011 A 0 x RAM(B)0 0 x RAM(B)1 0 x RAM(B)2 0 x RAM(B)3 None Reset RAM Bit SMB 0 1 2 3 4D 47 46 4B A 0100 A 1101 A A 0100 A 0111 A A 0100 A 0110 A A 0100 A 1011 A 1 x RAM(B)0 1 x RAM(B)1 1 x RAM(B)2 1 x RAM(B)3 None Set RAM Bit 12 Instruction Set (Continued) TABLE III. COP244C/245C Instruction Set (Continued) Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description MEMORY REFERENCE INSTRUCTIONS (Continued) y x RAM(B) Bd a 1 x Bd None Store Memory Immediate 1 and Increment Bd A 00 A r A 0110 A (r e 0:3) RAM(B) Y A Br Z r x Br None Exchange RAM with A, Exclusive-OR Br with r A 0010 A 0011 A A1A r A d A RAM(r,d) Y A None Exchange A with RAM Pointed to Directly by r,d STII y 7b A 0111 A X r b6 23 XAD r,d bb y A XDS r b7 A 00 A r A 0111 A (r e 0:3) RAM(B) Y A Bdb1 x Bd Br Z r x Br Bd decrements past 0 Exchange RAM with A and Decrement Bd. Exclusive-OR Br with r XIS r b4 A 00 A r A 0100 A (r e 0:3) RAM(B) Y A Bd a 1 x Bd Br Z r x Br Bd increments past 15 Exchange RAM with A and Increment Bd, Exclusive-OR Br with r REGISTER REFERENCE INSTRUCTIONS CAB 50 A 0101 A 0000 A A x Bd None Copy A to Bd CBA 4E A 0100 A 1110 A Bd x A None Copy Bd to A bb A 00 A r A (d- 1) A (r e 0:3: d e 0,9:15) or A 0011 A 0011 A A1A r A d A (any r, any d) r,d x B Skip until not a LBI Load B Immediate with r,d (Note 6) 33 6b A 0011 A 0011 A A 0110 A y A y x EN None Load EN Immediate (Note 7) 12 A 0001 A 0010 A A Y Br None Exchange A with Br (Note 8) SKC 20 A 0010 A 0000 A C e ``1'' Skip if C is True SKE 21 A 0010 A 0001 A A e RAM(B) Skip if A Equals RAM 33 21 A 0011 A 0011 A A 0010 A 0001 A G3:0 e 0 Skip if G is Zero (all 4 bits) 0 1 2 3 33 01 11 03 13 A 0011 A 0011 A A 0000 A 0001 A A 0001 A 0001 A A 0000 A 0011 A A 0001 A 0011 A 0 1 2 3 01 11 03 13 A 0000 A 0001 A A 0001 A 0001 A A 0000 A 0011 A A 0001 A 0011 A RAM(B)0 e 0 RAM(B)1 e 0 RAM(B)2 e 0 RAM(B)3 e 0 Skip if RAM Bit is Zero 41 A 0100 A 0001 A A time-base counter carry has occurred since last test Skip on Timer (Note 3) LBI r,d 33 bb LEI y XABR TEST INSTRUCTIONS SKGZ SKGBZ SKMBZ SKT 1st byte * 2nd byte 13 Skip if G Bit is Zero G0 e 0 G1 e 0 G2 e 0 G3 e 0 Instruction Set (Continued) TABLE III. COP244C/245C Instruction Set (Continued) Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description INPUT/OUTPUT INSTRUCTIONS ING 33 2A A 0011 A 0011 A A 0010 A 1010 A GxA None Input G Ports to A ININ 33 28 A 0011 A 0011 A A 0010 A 1000 A IN x A None Input IN Inputs to A (Note 2) INIL 33 29 A 0011 A 0011 A A 0010 A 1001 A IL3, CKO,``0'', IL0 x A None Input IL Latches to A (Note 3) INL 33 2E A 0011 A 0011 A A 0010 A 1110 A L7:4 x RAM(B) L3:0 x A None Input L Ports to RAM,A OBD 33 3E A 0011 A 0011 A A 0011 A 1110 A Bd x D None Output Bd to D Outputs 33 5b A 0011 A 0011 A A 0101 A y A yxG None Output to G Ports Immediate OMG 33 3A A 0011 A 0011 A A 0011 A 1010 A RAM(B) x G None Output RAM to G Ports XAS 4F A 0100 A 1111 A A Y SIO, C x SKL None Exchange A with SIO (Note 3) OGI y Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where 0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register. Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs. Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below. Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page. Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP may not jump to the last word in page 2. Note 6: LBI is a single-byte instruction if d e 0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ``d'' data minus 1 , e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112). Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ``1'' or ``0'' in each bit of EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.) Note 8: For 2K ROM devices, A Y Br (0 x A3). For 1K ROM devices, A Y Br (0,0 x A3, A2). 14 Description of Selected Instructions pulse stays low for at least two instruction cycles. Execution of an INIL inputs IL3 and IL0 into A3 and A0 respectively, and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and IN0 lines. If CKO is mask programmed as a general purpose input, an INIL will input the state of CKO into A2. If CKO has not been so programmed, a ``1'' will be placed in A2. A0 is input into A1. IL latches are cleared on reset. IL latches are not available on the COP245C/225C, and COP226C. XAS INSTRUCTION XAS (Exchange A with SIO) copies C to the SKL latch and exchanges the accumulator with the 4-bit contents of the SIO register. The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the EN register. If SIO is selected as a shift register, an XAS instruction can be performed once every 4 instruction cycles to effect a continuous data stream. LQID INSTRUCTION LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 11-bit word PC10:PC8,A,M. LQID can be used for table lookup or code conversion such as BCD to seven-segment. The LQID instruction ``pushes'' the stack (PC a 1 x SA x SB x SC) and replaces the least significant 8 bits of the PC as follows: A x PC7:4, RAM(B) x PC3:0, leaving PC10, PC9 and PC8 unchanged. The ROM data pointed to by the new address is fetched and loaded into the Q latches. Next, the stack is ``popped'' (SC x SB x SA x PC), restoring the saved value of PC to continue sequential program execution. Since LQID pushes SB x SC, the previous contents of SC are lost. INSTRUCTION SET NOTES a. The first word of a program (ROM address 0) must be a CLRA (Clear A) instruction. b. Although skipped instructions are not executed, they are still fetched from the program memory. Thus program paths take the same number of cycles whether instructions are skipped or executed except for JID, and LQID. c. The ROM is organized into pages of 64 words each. The Program Counter is a 11-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID, or LQID is the last word of a page, it operates as if it were in the next page. For example: a JP located in the last word of a page will jump to a location in the next page. Also, a JID or LQID located in the last word of every fourth page (i.e. hex address 0FF, 1FF, 2FF, 3FF, 4FF, etc.) will access data in the next group of four pages. Note: LQID uses 2 instruction cycles if executed, one if skipped. JID INSTRUCTION JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower 8 bits of the ROM address register PC with the contents of ROM addressed by the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not affected by JID. Note: The COP224C/225C/226C needs only 10 bits to address its ROM. Therefore, the eleventh bit (P10) is ignored. Power Dissipation The lowest power drain is when the clock is stopped. As the frequency increases so does current. Current is also lower at lower operating voltages. Therefore, the user should run at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full supply levels to insure that outputs are not loaded down and that inputs are not at some intermediate level which may draw current. Any input with a slow rise or fall time will draw additional current. A crystal or resonator generated clock input will draw additional current. For example, a 500 kHz crystal input will typically draw 100 mA more than a squarewave input. An R/C oscillator will draw even more current since the input is a slow rising signal. If using an external squarewave oscillator, the following equation can be used to calculate operating current drain. Note: JID uses 2 instruction cycles if executed, one if skipped. SKT INSTRUCTION The SKT (Skip On Timer) instruction tests the state of the T counter overflow latch (see internal logic, above), executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than relying on an external input signal. Note: If the most significant bit of the T counter is a 1 when a CAMT instruction loads the counter, the overflow flag will be set. The following sample of codes should be used when loading the counter: CAMT ; load T counter SKT ICO e IQ a V c 70 c Fi a V c 2400 c Fi/Dv where: ICO e chip operating current drain in microamps IQ e quiescent leakage current (from curve) Fi e CKI frequency in MegaHertz V e chip VCC in volts Dv e divide by option selected ; skip if overflow flag is set and reset it NOP IT INSTRUCTION The IT (idle till timer) instruction halts the processor and puts it in an idle state until the time-base counter overflows. This idle state reduces current drain since all logic (except the oscillator and time base counter) is stopped. IT instruction is not allowed if the T counter is mask-programmed as an external event counter (option Y31 e 1). For example at 5 volts VCC and 400 kHz (divide by 4) ICO e 120 a 5 c 70 c 0.4 a 5 c 2400 c 0.4/4 ICO e 120 a 140 a 1200 e 1460 mA INIL INSTRUCTION INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0, CKO and 0 into A. The IL3 and IL0 latches are set if a lowgoing pulse (``1'' to ``0'') has occurred on the IN3 and IN0 inputs since the last INIL instruction, provided the input 15 Power Dissipation (Continued) If an IT instruction is executed, the chip goes into the IDLE mode until the timer overflows. In IDLE mode, the current drain can be calculated from the following equation: I/O OPTIONS Outputs have the following optional configurations, illustrated in Figure 8 : a. Standard A CMOS push-pull buffer with an N-channel device to ground in conjunction with a P-channel device to VCC, compatible with CMOS and LSTTL. b. Open Drain An N-channel device to ground only, allowing external pull-up as required by the user's application. c. Standard TRI-STATE L Output A CMOS output buffer similar to a. which may be disabled by program control. d. Open-Drain TRI-STATE L Output This has the N-channel device to ground only. Ici e IQ a V c 70 c Fi For example, at 5 volts VCC and 400 kHz Ici e 120 a 5 c 70 c 0.4 e 260 mA The total average current will then be the weighted average of the operating current and the idle current: Ita e ICO c where: To Ti a Ici c To a Ti To a Ti Ita e total average current ICO e operating current Ici e idle current To e operating time Ti e idle time All inputs have the following option: e. Hi-Z input which must be driven by the users logic. All output drivers use two common devices numbered 1 to 2. Minimum and maximum current (IOUT and VOUT) curves are given in Figure 9 for each of these devices to allow the designer to effectively use these I/O configurations. b. Open-Drain Output a. Standard Push-Pull Output TL/DD/8422 - 11 c. Standard TRI-STATE ``L'' Output d. Open Drain TRI-STATE ``L'' Output FIGURE 8. Input/Output Configurations 16 e. Hi-Z Input Power Dissipation (Continued) Minimum Sink Current (Except CKO) Minimum Source Current (Except CKO) Maximum Quiescent Current TL/DD/8422 - 12 FIGURE 9. Input/Output Characteristics Option List Option 4: RESET input e 1: Hi-Z input Option 5: L7 Driver e 0: Standard TRI-STATE push-pull output e 2: Open-drain TRI-STATE output Option 6: L6 Driver (same as option 5) Option 7: L5 Driver (same as option 5) Option 8: L4 Driver (same as option 5) Option 9: IN1 input e 1: Hi-Z input, mandatory for 28 Pin Package e 2: Mandatory for 20 and 24 Pin Packages Option 10: IN2 input (same as option 9) Option 11 e 0: VCC Pin no option available Option 12: L3 Driver (same as option 5) Option 13: L2 Driver (same as option 5) Option 14: L1 Driver (same as option 5) Option 15: L0 Driver (same as option 5) Option 16: SI input (same as option 4) Option 17: SO Driver e 0: Standard push-pull output e 2: Open-drain output Option 18: SK Driver (same as option 17) Option 19: IN0 Input (same as option 9) Option 20: IN3 Input (same as option 9) Option 21: G0 I/O Port (same as option 17) Option 22: G1 I/O Port (same as option 17) Option 23: G2 I/O Port (same as option 17) Option 24: G3 I/O Port (same as option 17) Option 25: D3 Output (same as option 17) Option 26: D2 Output (same as option 17) Option 27: D1 Output (same as option 17) The COP244C/245C/224C/225C/COP226C mask-programmable options are assigned numbers which correspond with the COP244C/224C pins. The following is a list of options. The options are programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various I/O components using little or no external circuitry. Caution: The output options available on the COP224C/225C/226C and COP244C/245C are not the same as those available on the COP324C/325C/326C, COP344C/345C, COP424C/ 425C/426C and COP444C/445C. Options not available on the COP224C/225C/226C and COP244C/245C are: Option 2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value 0; Option 17 value 1; Option 30, Dual Clock, all values; Option 32, Microbus, all values; Option 33 values 2 4, and 6; Option 34 all values; and Option 35 all values. PLEASE FILL OUT THE OPTION TABLE on the next page. Photocopy the option data and send it in with your disk or EPROM. Option 1 e 0: Ground Pin no options available Option e 0: e 1: e 3: Option e 0: e 1: e 2: e 4: e 5: e 6: e 7: 2: CKO Pin clock generator output to crystal/resonator HALT I/O port general purpose input, high-Z 3: CKI input Crystal controlled oscillator input divide by 4 Crystal controlled oscillator input divide by 8 Crystal controlled oscillator input divide by 16 Single-pin RC controlled oscillator (divide by 4) External oscillator input divide by 4 External oscillator input divide by 8 External oscillator input divide by 16 17 Option List (Continued) Option 33: COP bonding. See note. Option 28: D0 Output (same as option 17) (1k and 2k Microcontroller) Option 29: Internal Initialization Logic e 0: Normal operation e 1: No internal initialization logic Option 30 e 0: No Option Available Option 31: Timer e 0: Time-base counter e 1: External event counter Option 32 e 0: No Option Available e 0: 28-pin package e 1: 24-pin package (1k Microcontroller only) e 3: 20-pin package e 5: 24- and 20-pin package Note:If opt. Y33 e 0 then opt. Y9, 10, 19, and 20 must e 1. If opt. Y33 e 1 then opt. Y9, 10, 19 and 20 must e 2, and option Y31 must e 0. If opt. Y33 e 3 or 5 then opt. Y9, 10, 19, 20 must e 2 and opt. Y21, 22, 31 must e 0. Option 34 e 0: No Option Available Option 35 e 0: No Option Available Option Table The following option information is to be sent to National along with the EPROM. OPTION DATA OPTION DATA 0 IS: GROUND PIN OPTION 19 VALUE e IS: IN0 INPUT 2 VALUE e IS: CKO PIN OPTION 20 VALUE e IS: IN3 INPUT OPTION 3 VALUE e IS: CKI INPUT OPTION 21 VALUE e IS: G0 I/O PORT OPTION 4 VALUE e IS: RESET INPUT OPTION 22 VALUE e IS: G1 I/O PORT OPTION 5 VALUE e IS: L7 DRIVER OPTION 23 VALUE e IS: G2 I/O PORT OPTION 6 VALUE e IS: L6 DRIVER OPTION 24 VALUE e IS: G3 I/O PORT OPTION 7 VALUE e IS: L5 DRIVER OPTION 25 VALUE e IS: D3 OUTPUT OPTION 8 VALUE e IS: L4 DRIVER OPTION 26 VALUE e IS: D2 OUTPUT OPTION 9 VALUE e IS: IN1 INPUT OPTION 27 VALUE e IS: D1 OUTPUT IS: IN2 INPUT OPTION 28 VALUE e IS: D0 OUTPUT IS: VCC PIN OPTION 29 VALUE e OPTION 1 VALUE e OPTION 1 OPTION 10 VALUE e OPTION 11 VALUE e 0 OPTION 12 VALUE e IS: L3 DRIVER OPTION 30 VALUE e OPTION 13 VALUE e IS: L2 DRIVER OPTION 31 VALUE e OPTION 14 VALUE e OPTION 15 VALUE e OPTION 32 VALUE e IS: L0 DRIVER OPTION 33 VALUE e IS: N/A IS: COP BONDING IS: SI INPUT OPTION 34 VALUE e OPTION 17 VALUE e IS: SO DRIVER OPTION 35 VALUE e 0 OPTION 18 VALUE e IS: SK DRIVER 18 IS: N/A IS: TIMER 0 0 OPTION 16 VALUE e 1 IS: L1 DRIVER IS: INT INIT LOGIC 0 IS: N/A IS: N/A 19 Physical Dimensions inches (millimeters) 20-Lead Hermetic Dual-In-Line Package (D) Order Number COP226C-XXX/D NS Package Number D20A 20 Physical Dimensions inches (millimeters) (Continued) 24-Lead Hermetic Dual-In-Line Package (D) Order Number COP225C-XXX/D or COP245C-XXX/D NS Package Number D24C 28-Lead Hermetic Dual-In-Line Package (D) Order Number COP224C-XXX/D or COP244C-XXX/D NS Package Number D28C 21 Physical Dimensions inches (millimeters) (Continued) 20-Lead Surface Mount Package (M) Order Number COP226C-XXX/WM NS Package Number M20B 20-Lead Molded Dual-In-Line Package (N) Order Number COP226C-XXX/N NS Package Number N20A 22 Physical Dimensions inches (millimeters) (Continued) 24-Lead Molded Dual-In-Line Package (N) Order Number COP225C-XXX/N or COP245C-XXX/N NS Package Number N24A 28-Lead Molded Dual-In-Line Package (N) Order Number COP224C-XXX/N or COP244C-XXX/N NS Package Number N28B 23 COP224C/COP225C/COP226C/COP244C/COP245C Single-Chip 1k and 2k CMOS Microcontrollers Physical Dimensions inches (millimeters) (Continued) Plastic Leaded Chip Carrier (V) Order Number COP224C-XXX/V or COP244C-XXX/V NS Package Number V28A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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