1
DS9101-01 April 2011 www.richtek.com
RT9101
Ordering Information
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
WDFN-8L 3x3
2.65W PWM Class-D Power Amplifier
Features
zz
zz
zWide Operating Voltage : 2.5V to 5.5V
zz
zz
zHigh Efficiency With an 8ΩΩ
ΩΩ
Ω Speaker :
``
``
` 88% at 400mW
``
``
` 80% at 100mW
zz
zz
zLow Quiescent Current and Shutdown Current
zz
zz
zOptimized PWM Output Stage Eliminates LC Filter
zz
zz
zFully Differential Design Reduces RF Rectification
and Eliminates Bypass Capacitor
zz
zz
zInternally Generated 250kHz Switching Frequency
zz
zz
zIntegrated Pop and Click Suppression Circuitry
zz
zz
zRoHS Compliant and Halogen Free
Applications
zMobile Phones
zHandsets
zPDAs
zPortable multimedia devices
WL-CSP-9B 1.45x1.45 (BSC)
General Description
The RT9101 is a 2.65W, high efficiency Class-D audio
a mplifier featuring low-resistance internal power MOSFET s
and the gain can be set by an external input resistance.
The filter free topology eliminates the output filter and
reduces the external component count, footprint area, and
system costs.
Operating from a single 5V supply , the RT9101 is capable
of driving 4Ω speaker load at a continuous average output
of 2.65W/10% THD+N or 2W/0.5% THD+N. The RT9101
has a higher ef f iciency with speaker loa d compared to a
typical class AB amplifier. With a 3.6V supply driving an
8Ω speaker, the efficiency for a 400mW power level is
88%.
It is very suitable for power sensitive a pplication, such a s
cellular handsets and battery powered devices. In addition
to these features, the RT9101 provides a fast startup time
to minimize audible popping during device turn-on and turn-
off. Moreover, the RT9101 also integrates thermal and over
current protection circuits.
The RT9101 is available in WDFN-8L 3x3, and
WL-CSP-9B 1.45x1.45 (BSC) pa ckages.
INP
INN
OUTN
GND
OUTP
VDD
GND
VDD
A1 A2 A3
B3B1
C1 C2 C3
B2
SHDN
NC
INN
OUTN
GND
VDD
OUTP
INP 7
6
5
1
2
3
4
8
GND
9
SHDN
RT9101
Package Type
QW : WDFN-8L 3x3 (W-Type)
WSC : WL-CSP-9B 1.45x1.45 (BSC)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
()
Default : WDFN-8L 3x3
C : WL-CSP-9B 1.45x1.45 (BSC)
2DS9101-01 April 2011www.richtek.com
RT9101
Typical Application Circuit
Figure 1. Application Circuit with Differential Input
Figure 2. Application Circuit with Single-Ended Input
Marking Information
FL : Product Code
YMDNN : Date Code
21 : Product Code
W : Date Code
FL YM
DNN
21W
RT9101GQW
RT9101ZQW
FL=YM
DNN
FL= : Product Code
YMDNN : Date Code
RT9101CWSC
INN
OUTN
GND
VDD
OUTP
INP
RT9101
SHDN
RI
CI
RI
CICS
150k
150k
2.2µF
2.2µF
Audio Input
from DAC 1µF
RL
INN
OUTN
GND
VDD
OUTP
INP
RT9101
SHDN
RI
CI
RI
CICS
150k
150k
2.2µF
2.2µF
Audio Input
1µF
RL
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DS9101-01 April 2011 www.richtek.com
RT9101
Function Block Diagram
Gate
Driver
Gate
Driver
+
-
+
-
+
-
+
-
Protection Circuit
INN
OUTN
GND
VDD
OUTP
INP
SHDN
VDD
Functional Pin Description
Pin No .
WDF N-8L 3x3 WL-CSP -9B
1.4 5x1.45 (B SC ) Pi n Nam e Pin Funct i on
1 C 2 S HD N S hutdow n Control (Ac ti ve Low).
2 - - N C N o I nternal Con nec t ion.
3 A1 I NP P os i tiv e Input of Differ entia l A udio Si gnal.
4 C 1 I NN N egative Input of Dif f erent ial Audi o Si gnal.
5 C3 OUTP Positive Output.
6 B1, B2 VDD Supply Voltage Input.
7,
9 (E xposed Pad) A2, B3 GND G r ound. The exp os ed pad must be s old er ed to a large PCB and
connected t o GN D fo r maximum ther mal di s sipa ti on.
8 A3 OUTN Negative Output.
4DS9101-01 April 2011www.richtek.com
RT9101
Electrical Characteristics
(VDD = 5V, TA = 25°C, unless otherwise specified)
Absolute Maximum Ratings (Note 1)
zSupply Voltage, VDD ------------------------------------------------------------------------------------------------- −0.3V to 6V
zInput V oltage, INP, INN ---------------------------------------------------------------------------------------------- −0.3V to(VDD + 0.3V)
zPower Dissipation, PD @ TA = 25°C
WDFN-8L 3x3 --------------------------------------------------------------------------------------------------------- 1.429W
WL-CSP-9B 1.45x1.45 (BSC)------------------------------------------------------------------------------------- 1.250W
zPa ckage Thermal Re sistance (Note 2)
WDFN-8L 3x3, θJA ---------------------------------------------------------------------------------------------------- 70°C/W
WDFN-8L 3x3, θJC --------------------------------------------------------------------------------------------------- 8.2°C/W
WL-CSP-9B 1.45x1.45 (BSC), θJA ------------------------------------------------------------------------------- 80°C/W
zJunction T emperature------------------------------------------------------------------------------------------------ 150°C
zLead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------- 260°C
zStorage T emperature Range --------------------------------------------------------------------------------------- −65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Ma chine Mode) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
zSupply Voltage, VDD ------------------------------------------------------------------------------------------------- 2.7V to 5.5V
zJunction T emperature Range--------------------------------------------------------------------------------------- −40°C to 125°C
zAmbient T emperature Range--------------------------------------------------------------------------------------- −40°C to 85°C
Parameter Symbol Test Conditions Min Typ Max Unit
Outp ut Offset Vol ta g e VOS VDD = 2. 5V to 5. 5V - - 1 25 m V
Power Supply Rejection Ratio PSRR VDD = 2. 5V to 5.5V (N ot e 5) - - −70 −55 dB
High Lev el Inp ut Cu rrent ⎪ IIH ⎪ VDD = 5.5V , VI = 5.8V -- - - 100 μA
Low Level Input Current ⎪ IIL ⎪ V
DD = 5.5V , VI = −0.3V -- -- 5 μA
Logic-High VIH 2 -- --
SH DN Inpu t
Thres hold Vo ltage Logic-Low VIL -- -- 0.4
V
VDD = 5.5V , No Load -- 3.4 4.9
VDD = 3.6V , No Load -- 2.8 -- Q uiescent Curr ent IQ VDD = 2.5V , No Load -- 2.2 3.2 mA
Shu tdow n C ur ren t I SHDN V
SHDN = 0V, VDD = 2. 5V t o 5.5V - - -- 1 μA
VDD = 2.5V -- 600 --
VDD = 3.6V -- 500 --
Static Drain- Sour ce O n- St ate
Resistance RDS(ON) VDD = 5V -- 400 -- mΩ
Outpu t Impe danc e i n S HDN VSHDN = 0V -- >1 -- kΩ
Sw itching Fr equency VDD = 2. 5V to 5.5V 200 250 300 kHz
Gain VDD = 2.5V to 5. 5V 284k/ R I 300k/RI 316k/RI V/V
Resistance from SH DN to
GND -- 200 -- kΩ
To be continued
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DS9101-01 April 2011 www.richtek.com
RT9101
Note 1. Stresses listed a s the above “Absolute Maximum Ratings” may cause permanent da mage to the device. These
are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may remain possibility to af fect device reli ability.
Note 2. θJA is mea sured in natural convection at TA = 25°C on a high-effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of
the pa ckage.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guara nteed to function outside its operating conditions.
Note 5. Guara ntee by design.
Operating Characteristics
(Gain = 2V/V,RL= 8Ω, TA = 25°C, unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max Unit
VDD = 5V -- 2.65 --
VDD = 3.6V -- 1.5 --
TH D+N = 10%, f = 1kHz,
RL = 4Ω VDD = 2.5V -- 0.52 -- W
VDD = 5V -- 2.08 --
VDD = 3.6V -- 1.06 --
THD+N = 1%, f = 1kHz,
RL = 4Ω VDD = 2.5V -- 0.42 -- W
VDD = 5V -- 1.45 --
VDD = 3.6V -- 0.73 --
TH D+N = 10%, f = 1kHz,
RL = 8Ω VDD = 2.5V -- 0.33 -- W
VDD = 5V -- 1.19 --
VDD = 3.6V -- 0.59 --
Output Power PO
THD+N = 1%, f = 1kHz,
RL = 8Ω VDD= 2.5V -- 0.26 -- W
VDD = 5 V, PO = 1W, RL = 8Ω, f = 1kH z - - 0. 06 --
VDD = 3. 6V, PO = 0.5W , R L = 8 Ω,
f = 1kHz -- 0.05 --
Tota l Harmoni c
Di stortion Plus Noise THD+N VDD = 2. 5V, PO = 20 0m W, RL = 8Ω,
f = 1kHz -- 0.04 --
%
S upply Ri ppl e
R ej ec ti on R ati o PSRR VDD = 5 V, f = 21 7 H z,
VDD-Ripple = 200mVpp -- −70 -- dB
S ignal-t o- Noi se Rat i o S NR VDD = 5 V, PO = 1W, RL = 8Ω,
A W e ighting Filter -- 95 -- dB
I nput Impedance ZI 142 150 158 kΩ
St ar t- U p T im e from
Shutdown V
DD = 3.6V -- 1 -- ms
6DS9101-01 April 2011www.richtek.com
RT9101
Typical Operating Characteristics
Output Power vs. Load Resistance
0.0
0.5
1.0
1.5
2.0
2.5
4 8 12 16 20 24 28 32
Load Resist ance ( dB )
Output Power (W)
VDD = 5V
Gain = 2V/V, f = 1kHz, THD+N = 10%
VDD = 2.5V
VDD = 3.6V
Output Power vs. Load Resistance
0.0
0.5
1.0
1.5
2.0
2.5
4 8 12 16 20 24 28 32
Load Resistance (dB)
Output Power (W)
VDD = 5V
Gain = 2V/V, f = 1kHz, THD+N = 1%
VDD = 2.5V
VDD = 3.6V
Efficiency vs. Output Power
0
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Output Power (W)
Eff iciency ( %)
VDD = 5V
Gain = 2V/V, f = 1kHz, RL = 4Ω, 33μH
VDD = 2.5V VDD = 3.6V
Efficiency vs. Output Power
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2
Output Power (W)
Eff iciency ( %)
VDD = 5V
Gain = 2V/V, f = 1kHz, RL = 8Ω, 33μH
VDD = 2.5V
VDD = 3.6V
Supply Current vs. Output Power
0
100
200
300
400
500
600
700
00.511.522.53
Output Power (W)
Suppl y C urrent (mA )
VDD = 5V
Gain = 2V/V, RL = 4Ω, 33μH
VDD = 2.5V
VDD = 3.6V
Supply Current vs . Output Power
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Output Power (W)
Suppl y C urrent (mA)
VDD = 5V
Gain = 2V/V, RL = 8Ω, 33μH
VDD = 2.5V
VDD = 3.6V
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DS9101-01 April 2011 www.richtek.com
RT9101
RL = 4Ω, f = 1kHz, Gain = 2V/V
THD+N vs. Output Power
10m 20m 50m 100m 200m 500m 1 2 5
THD+N (%/Div)
Output Power (W/Div)
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
VDD = 2.5V
VDD = 3.6V
VDD = 5V
THD+N vs. Frequency
20 50 100 200 500 1k 2k 5k 10k 20k
THD+N (%/Div)
Frequency (Hz/Div)
PO = 50mW
PO = 250mW
PO = 1W
VDD = 5V, CI = 2.2μF, RL= 8 Ω, Gain = 2V/V
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
THD+N vs. Frequency
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz/Div)
PO = 25mW
PO = 125mW
PO = 500mW
THD+N (%/Div)
VDD = 3.6V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
THD+N vs. Frequency
20 50 100 200 500 1k 2k 5k 10k 20k
THD+N (%/Div)
Frequency (Hz/Div)
PO = 15mW
PO = 75mW
PO = 200mW
VDD = 2.5V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
THD+N vs. Frequency
20 50 100 200 500 1k 2k 5k 10k 20k
THD+N (%/Div)
Frequency (Hz/Div)
VDD = 2.5V
VDD = 3.6V VDD = 5V
VDD = 4V
PO = 250mW, CI = 2.2μF, RL= 4Ω, Gain = 2V/V
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
RL = 8Ω, f = 1kHz, Gain = 2V/V
THD+N vs. Output Power
10m 20m 50m 100m 200m 500m 1 2 5
THD+N (%/Div)
Output Power (W/Div)
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
VDD = 2.5V
VDD = 3.6V
VDD = 5V
8DS9101-01 April 2011www.richtek.com
RT9101
Power Dissipation vs . Output Power
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
00.511.522.5
Output Power (W)
Power Di ssi pation ( W )
RL = 8Ω + 33μH
VDD = 5V, f = 1kHz, Gain = 2V/V
RL = 4Ω + 33μH
Power Dissipation vs. Output Power
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1 1.2
Output Power (W)
Power Dissi pation ( W )
RL = 8Ω + 33μH
VDD = 3.6V, f = 1kHz, Gain = 2V/V
RL = 4Ω + 33μH
GSM Power Supply Rejection vs. Time
Gain = 2V/V, CI = 2.2μF, RL = 8Ω,
f = 217Hz, Duty = 12%
Time (2.5ms/Div)
VDD
(1V/Div)
VOUT
(20mV/Div)
VDD = 3.6V, P K -PK = 512mV
GSM Power Supply Rejection vs. Frequency
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
(dB/Div)
Frequency (Hz/Div)
+0
-20
-40
-60
-80
-100
-120
-140
-150
Supply Voltage
Output Voltage
VDD = 3.6V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V
PSRR vs. Frequency
20 50 100 200 500 1k 2k 5k 10k 20k
PSRR (dB/Div)
Frequency (Hz/Div)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VDD = 2.5V
VDD = 3.6V
VDD = 5V
VP-P = 200mV, CI = 2.2 μF, RL= 4 Ω, Gain = 2V/V
PSRR vs. Frequency
20 50 100 200 500 1k 2k 5k 10k 20k
PSRR (dB/Div)
Frequency (Hz/Div)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VDD = 2.5V
VDD = 3.6V
VDD = 5V
VP-P = 200mV, CI = 2.2μF, RL= 8Ω, Gain = 2V/V
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DS9101-01 April 2011 www.richtek.com
RT9101
Application information
The RT9101 is a fully differential a mplifier with differential
inputs a nd outputs. The R T9101 integrates a differenti al
amplifier and a common mode voltage controller. The
differential amplifier ensures that the amplifier outputs a
differential voltage on the output that is equal to the
differential input times the gain. The RT9101 can support
differenti al input and single ended input a pplications.
Components Selection
Input Resistors (RI)
Amplifier ca n be resistors and the gain can be calculated
as the f ollowing equation :
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the input resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminish if resistor mismatch occurs.
Therefore, it is recommended to use 1% tolerance or better
resistors to keep the performance opti mized.
The input resistors should be placed very close to the
RT9101 to limit noise injection on the high impedance
nodes. It is recommended to set the gain at 2V/V or lower
for better performance.
Decoupling Capacitor
The RT9101 is a high performance Class-D audio amplifier
that requires adequate power supply decoupling to ensure
the eff iciency is high and total harmonic distortion (THD)
is low. For higher frequency tra n sients, spikes, or digital
ha sh on the line, a good low Equivalent-Series-Resistance
(ESR) ceramic capacitor, typically 1μF, placed as close
as possible to the VDD pin can achieve the best
performance. Placing this decoupling capacitor close to
the RT9101 is very important for the efficiency of the Cla ss-
D amplifier , be cause a ny re sista nce or inductance in the
tra ce between the device and the capa citor can cause a
loss in efficiency. For filtering lower frequency noise
signals, it is recommended to use a 10μF or greater
ca pacitor placed near the audio power amplifier .
Input Capacitor
In the typical a pplication, a n input coupling ca p acitor (CI)
is required to allow the input signal to the proper dc level
for optimum operation.
However, the RT9101 is a fully differential amplifier with
good CMRR so that the RT9101 does not require input
coupling ca pacitors if using a differential input source that
is biased from 0.5 V to VDD − 0.8 V. Use 1% tolera nce or
better gain-setting resistors if input coupling capacitors
are not used.
In the single-ended input application, an input capa citor,
(CI), is required to allow the amplifier to bias the input
signal to the proper dc level. In this ca se, CI and RI form a
high-pa ss filter with the corner frequency a s shown in the
following equation :
CII
1
f2RC
π
=
f (Hz )
fC
-3dB
Gain (dB)
The value of CI is important to consider a s it directly affects
the bass (low frequency) performance of the circuit. For
exa mple, the flat bass response requirement is 10 Hz a nd
RI is 20kΩ, the value of CI can be calculated by the
following equation :
IIC
1
C2Rf
π
=
In this example, CI is 0.8μF. A ca p a cita nce1μF or larger
ca n be used.
Under Voltage Lockout
The under voltage lock out circuit operates as a voltage
detector and always monitors the supply voltage (VDD)
while SHND = 1. While powered on, the chip is kept still
in shutdown mode until VDD rises to greater than 2.2V
(typ). While powered off, the chip does not leave operation
mode until VDD falls to less than 2.1V (typ).
I
2 x 150k
Gain = RΩ
10 DS9101-01 April 2011www.richtek.com
RT9101
Layout Considerations
For best performance of the RT9101, the following PCB
Layout guidelines must be strictly followed.
` Pla ce the decoupling ca pa citors a s close a s possible to
the V DD and GND pins.
` Keep the differenti al input a nd output traces as wide
a nd short a s possible. The tra ce s of (INP & INN) a nd
(OUTP & OUT N) should be kept equal width a nd length
respectively.
` Connect the GND and Exposed Pad to a strong ground
pla ne for maxi mum thermal dissipation a nd noise
protection.
Figure 4. PCB Layout Guide
NC
INN
OUTN
GND
VDD
OUTP
INP 7
6
5
1
2
3
4
8
GND
9
SHDN
CS
RI
CI
RI
CI
Audio
Input The decoupling capacitor (C S)
must be placed as close to the
IC as po ssib le
GND
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to a mbient
thermal resistance.
For recommended operating condition specifications of
the RT9101, the maximum junction temperature is 125°C
and TA is the a mbient temperature. The junction to a mbient
thermal resista nce, θJA, is layout dependent. For WDFN-
8L 3x3 pa ckages, the thermal resista nce, θJA, is 70°C/W
on a standard JEDEC 51-7 four-layer thermal test board.
For WL-CSP-9B 1.45x1.45 (BSC) pa ckages, the thermal
resistance, θJA, is 80°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formula :
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
W DF N-8L 3x3 package
PD(MAX) = (125°C − 25°C) / (80°C/W) = 1.250W for
WL-CSP-9B 1.45x1.45 (BSC) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT9101 packages, the derating
curves in Figure 3 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Figure 3. Derating Curves for RT9101 Pa ckages
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0 25 50 75 100 125
Ambient Tem perat ure (°C)
Maximum Power Di ssipation ( W) 1
Four-Layer PCB
WDFN-8L 3x3
WL-CSP-9B 1.45x1.45 (BSC)
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DS9101-01 April 2011 www.richtek.com
RT9101
Outline Dimension
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.200 0.300 0.008 0.012
D 2.950 3.050 0.116 0.120
D2 2.100 2.350 0.083 0.093
E 2.950 3.050 0.116 0.120
E2 1.350 1.600 0.053 0.063
e 0.650 0.026
L 0.425 0.525
0.017 0.021
W-Type 8L DFN 3x3 Package
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID a nd T ie Bar M ark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A
12 DS9101-01 April 2011www.richtek.com
RT9101
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
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9B WL-CSP 1.45x1.45 Package (BSC)
Symbol Dimensions In Millime ters Dimen sio ns In Inches
Min Max Min Max
A 0.525 0.625 0.021 0.025
A1 0.200 0.260 0.008 0.010
b 0.290 0.350 0.011 0.014
D 1.400 1.500 0.055 0.059
D1 1.000 0.039
E 1.400 1.500 0.055 0.059
E1 1.000 0.039
e 0.500 0.020
