PIC12CE67 - Microchip Technology



1998 Microchip Technology Inc.

Preliminary

DS40181B-page 1

Devices Included in this Data Sheet:

• PIC12CE673

• PIC12CE674

High-Performance RISC CPU:

• Only 35 single word instructions to learn

• All instructions are single cycle (400 ns) except f or

program branches which are two-cycle

• Operating speed: DC - 10 MHz clock input

DC - 400 ns instruction cycle

• 14-bit wide instructions

• 8-bit wide data path

• Interrupt capability

• Special function hardware registers

• 8-level deep hardware stack

• Direct, indirect and relative addressing modes for

data and instructions

Peripheral Features:

• Four-channel, 8-bit A/D converter

• 8-bit real time clock/counter (TMR0) with 8-bit

programmable prescaler

• Interrupt on pin change (GP0, GP1, GP3)

• 1,000,000 erase/write cycle EEPROM data

memory

• EEPROM data retention > 40 years

Device

Memory

Program Data

RAM Data

EEPROM

PIC12CE673 1024 x 14 128 x 8 16 x 8

PIC12CE674 2048 x 14 128 x 8 16 x 8

Pin Diagram:

Special Microcontroller Features:

• In-Circuit Serial Programming (ICSP™)

• Internal 4 MHz oscillator with programmable

calibration

• Selectable clockout

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Internal pull-ups on I/O pins (GP0, GP1, GP3)

• Internal pull-up on MCLR pin

• Selectable oscillator options:

- INTRC: Precision internal 4 MHz oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High speed crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

• Low-power, high-speed CMOS EPROM/

EEPROM technology

• Fully static design

• Wide operating voltage range 2.5V to 5.5V

• Commercial, Industrial, and Extended

temperature ranges

• Low power consumption

< 2 mA @ 5V, 4 MHz

A typical @ 3V, 32 kHz

< 1

A typical standby current

PDIP, Windowed CERDIP

PIC12CE673

PIC12CE674

GP5/OSC1/CLKIN

GP4/OSC2/AN3/CLKOUT

GP3/MCLR/VPP

VDD VSS

GP0/AN0

GP1/AN1/VREF

GP2/T0CKI/AN2/INT

8-Pin, 8-Bit CMOS Microcontroller with A/D Converter

and EEPROM Data Memory

PIC12CE67X

DS40181B-page 2

Preliminary



1998 Microchip Technology Inc.

Table of Contents

1.0 General Description....................................................................................................................................................................... 3

2.0 PIC12CE67X Device Varieties....................................................................................................................................................... 5

3.0 Architectural Overview................................................................................................................................................................... 7

4.0 Memory Organization................................................................................................................................................................... 11

5.0 I/O Port......................................................................................................................................................................................... 25

6.0 EEPROM Peripheral Operation................................................................................................................................................... 27

7.0 Timer0 Module............................................................................................................................................................................. 31

8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................... 37

9.0 Special Features of the CPU ....................................................................................................................................................... 45

10.0 Instruction Set Summary.............................................................................................................................................................. 61

11.0 Development Support.................................................................................................................................................................. 75

12.0 Electrical Characteristics for PIC12CE67X.................................................................................................................................. 81

13.0 DC and AC Characteristics - PIC12CE67X ................................................................................................................................. 99

14.0 Packaging Information............................................................................................................................................................... 103

Index .................................................................................................................................................................................................. 107

PIC12CE67X Product Identification System ..................................................................................................................................... 113

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended

workarounds. As device/documentation issues become known to us, w e will publish an errata sheet. The errata will specify the re vi-

sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales ofﬁce or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure

that this document is correct. Ho wev er, we realize that we ma y ha v e missed a fe w things . If you ﬁnd any inf ormation that is missing

or appears in error, please:

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We appreciate your assistance in making this a better document.



1998 Microchip Technology Inc.

Preliminary

DS40181B-page 3

PIC12CE67X

1.0 GENERAL DESCRIPTION

The PIC12CE67X devices are low-cost, high-perfor-

mance, CMOS, fully-static, 8-bit microcontroller with

integrated analog-to-digital (A/D) converter and

EEPROM data memory in the PIC12CEXXX Micro-

controller family.

All PICmicro™ microcontrollers employ an advanced

RISC architecture. The PIC12C67X microcontrollers

have enhanced core features, eight-level deep stack,

and multiple internal and external interrupt sources.

The separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two stage instruction

pipeline allows all instructions to execute in a single

cycle, except for program branches which require two

cycles. A total of 35 instructions (reduced instruction

set) are av ailable. Additionally, a large register set gives

some of the architectural innov ations used to achie v e a

very high performance.

PIC12C67X microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

The PIC12CE67X de vices hav e 128 bytes of RAM, 16

bytes of EEPR OM data memory, 5 I/O

pins and 1 input

pin. In addition a timer/counter is available. Also a 4-

channel high-speed 8-bit A/D is provided. The 8-bit res-

olution is ideally suited for applications requiring low-

cost analog interf ace , e .g. thermostat control, pressure

sensing, etc.

The PIC12CE67X device has special features to

reduce external components, thus reducing cost,

enhancing system reliability and reducing power con-

sumption. The Power-On Reset (POR), Power-up

Timer (PWRT), and Oscillator Start-up Timer (OST)

eliminate the need f or external reset circuitry. There are

five oscillator conﬁgurations to choose from, including

INTRC precision internal oscillator mode and the

power-saving LP (Low Power) oscillator mode. Power

saving SLEEP mode, Watchdog Timer and code

protection features improve system cost, power and

reliability.The SLEEP (power-down) feature provides a

power saving mode. The user can wake up the chip

from SLEEP through several external and internal

interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against softw are lock-

up.

A UV erasable windowed package version is ideal for

code development while the cost-effective One-Time-

Programmable (OTP) version is suitable for production

in any v olume. The customer can tak e full advantage of

Microchip’s price leadership in OTP microcontrollers

while beneﬁting from the OTP’s ﬂexibility.

The PIC12CE67X device ﬁts perfectly in applications

ranging from security and remote sensors to appliance

control and automotive. The EPROM technology

makes customization of application programs (trans-

mitter codes, motor speeds , receiver frequencies, etc.)

extremely fast and convenient. The small footprint

packages make this microcontroller series perfect for

all applications with space limitations. Low cost, low

power, high performance, ease of use and I/O ﬂe xibility

make the PIC12CE67X very versatile even in areas

where no microcontroller use has been considered

before (e.g. timer functions, communications and

coprocessor applications).

1.1 Family and Upward Compatibility

The PIC12CE67X products are compatible with other

members of the 14-Bit, PIC12C67X and PIC16CXXX

families.

1.2 Development Support

The PIC12CE67X device is supported by a full-fea-

tured macro assembler, a software simulator, an in-cir-

cuit emulator , a low-cost de v elopment programmer and

a full-featured programmer. A “C” compiler and fuzzy

logic support tools are also available.

PIC12CE67X

DS40181B-page 4

Preliminary



1998 Microchip Technology Inc.

TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES

PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674

Clock

Maximum

Frequency

of Operation

(MHz)

4 4 4 4 10 10 10 10

Memory

EPROM

Program

Memory

512 x 12 1024 x 12 512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14

RAM Data

Memory

(bytes)

25 41 25 41 128 128 128 128

Peripherals

EEPROM

Data Memory

(bytes)

— — 16 16 — —

16 16

Timer

Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0

A/D Con-

verter (8-bit)

Channels

— — — — 4 4 4 4

Features

Wake-up

from SLEEP

on pin

change

Yes Yes Yes Yes Yes Yes Yes Yes

Interrupt

Sources — — — — 4 4 4 4

I/O Pins 5 5 5 5 5 5 5 5

Input Pins 1 1 1 1 1 1 1 1

Internal

Pull-ups Yes Yes Yes Yes Yes Yes Yes Yes

In-Circuit

Serial

Programming

Yes Yes Yes Yes Yes Yes Yes Yes

Number of

Instructions 33 33 33 33 35 35 35 35

Packages 8-pin DIP,

JW, SOIC 8-pin DIP,

JW 8-pin DIP,

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable

code protect and high I/O current capability.

All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.



1998 Microchip Technology Inc.

Preliminary

DS40181B-page 5

PIC12CE67X

2.0 PIC12CE67X DEVICE

VARIETIES

A variety of frequency ranges and packaging options

are av ailable . Depending on application and production

requirements, the proper de vice option can be selected

using the information in the PIC12CE67X Product Iden-

tiﬁcation System section at the end of this data sheet.

When placing orders, please use that page of the data

sheet to specify the correct part number.

For example, the PIC12CE67X device “type” is indi-

cated in the device number:

, as in PIC12

674. These devices have

OTP program memory, EEPROM data memory

and operate over the standard voltage range.

2.1 UV Erasable Devices

The UV erasable version, offered in windowed pack-

age, is optimal f or prototype de velopment and pilot pro-

grams.

The UV erasable version can be erased and repro-

grammed to any of the conﬁguration modes.

Microchip's PICSTART



Plus and PRO MATE



pro-

grammers both support the PIC12CE67X. Third party

programmers also are available; refer to the Microchip

Third Party Guide for a list of sources.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates and small volume applications.

The OTP devices, packaged in plastic packages, per-

mit the user to program them once. In addition to the

program memory, the conﬁguration bits must also be

programmed.

Note:

Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the inter nal oscillator.

The calibration value must be saved prior

to erasing the part.

2.3 Quick-Turn-Programming (QTP)

Devices

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices are identical to the OTP devices but

with all EPROM locations and conﬁguration options

already programmed by the factory. Cer tain code and

prototype veriﬁcation procedures apply before produc-

tion shipments are available. Please contact your local

Microchip Technology sales ofﬁce for more details.

2.4 Serialized Quick-Turn Programming

(SQTP

) Devices

Microchip offers a unique programming ser vice where

a few user-deﬁned locations in each device are pro-

grammed with diff erent serial numbers. The serial num-

bers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password, or ID number.

PIC12CE67X

DS40181B-page 6

Preliminary



1998 Microchip Technology Inc.

NOTES:



1998 Microchip Technology Inc.

Preliminary

DS40181B-page 7

PIC12CE67X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC12CE67X family can

be attributed to a number of architectural f eatures com-

monly found in RISC microprocessors. To begin with,

the PIC12CE67X uses a Harvard architecture , in which

program and data are accessed from separate memo-

ries using separate buses. This improves bandwidth

over traditional v on Neumann architecture in which pro-

gram and data are fetched from the same memory

using the same bus. Separating program and data

buses also allow instructions to be sized differently than

the 8-bit wide data word. Instruction opcodes are 14-

bits wide making it possible to have all single word

instructions. A 14-bit wide program memory access

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions (35)

execute in a single cycle (400 ns @ 10 MHz) e xcept f or

program branches.

The table below lists program memory (EPROM), data

memory (RAM), and non-volatile memory (EEPROM)

for each PIC12CE67X device.

Device Program

Memory

RAM

Data

Memory

EEPROM

Data

Memory

PIC12CE673 1K x 14 128 x 8 16x8

PIC12CE674 2K x 14 128 x 8 16x8

The PIC12CE67X can directly or indirectly address its

ters, including the program counter, are mapped in the

data memory. The PIC12CE67X has an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make programming with the

PIC12CE67X simple yet efﬁcient. In addition, the learn-

ing curve is reduced signiﬁcantly.

PIC12CE67X devices contain an 8-bit ALU and work-

ing register. The ALU is a general purpose arithmetic

unit. It performs arithmetic and Boolean functions

between the data in the working register and any regis-

ter ﬁle.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the working register (W register). The

other operand is a ﬁle register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register . The C and DC bits

operate as a borrow bit and a digit borrow out bit,

respectively, in subtraction. See the

SUBLW

and

SUBWF

instructions for examples.

PIC12CE67X

DS40181B-page 8

Preliminary



1998 Microchip Technology Inc.

FIGURE 3-1: PIC12CE67X BLOCK DIAGRAM

Power-up

Timer

Oscillator

Start-up Timer

EPROM

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

Timer0

GPIO

GP4/OSC2/AN3/CLKOUT

GP3/MCLR/Vpp

GP2/T0CKI/AN2/INT

GP1/AN1/VREF

GP0/AN0

GP5/OSC1/CLKIN

8 Level Stack

(13 bit) 128 bytes

Note 1: Higher order bits are from the STATUS register.

A/D

Watchdog

Timer

Power-on

Reset

Device

PIC12CE673

PIC12CE674

Program Memory Data Memory (RAM)

1K x 14

2K x 14 128 x 8

128 x 8

4 MHz Clock

Internal

Non-Volatile Memory (EEPROM)

16 x 8

Data

Memory

16x8

EEPROM

SCL

SDA



1998 Microchip Technology Inc.

Preliminary

DS40181B-page 9

PIC12CE67X

TABLE 3-1: PIC12CE67X PINOUT DESCRIPTION

Name DIP Pin

#I/O/P

Type Buffer

T ype Description

GP0/AN0 7 I/O TTL/ST Bi-directional I/O port/serial programming data/analog input

0. Can be software programmed for internal weak pull-up

and interrupt on pin change. This b uffer is a Schmitt Trigger

input when used in serial programming mode.

GP1/AN1/V

REF

6 I/O TTL/ST Bi-directional I/O port/serial programming clock/analog

input 1/voltage ref erence . Can be software programmed f or

internal weak pull-up and interrupt on pin change. This

buffer is a Schmitt Trigger input when used in serial pro-

gramming mode.

GP2/T0CKI/AN2/INT 5 I/O ST Bi-directional I/O port/analog input 2. Can be conﬁgured as

T0CKI or external interrupt.

GP3/MCLR/V

4 I TTL/ST Input port/master clear (reset) input/programming voltage

input. When conﬁgured as MCLR, this pin is an active low

reset to the de vice. V oltage on MCLR /V

must not exceed

during normal device operation. Can be software pro-

grammed for internal weak pull-up and interrupt on pin

change. Weak pull-up always on if conﬁgured as MCLR .

This buffer is Schmitt Trigger when in MCLR mode.

GP4/OSC2/AN3/

CLKOUT 3 I/O TTL Bi-directional I/O port/oscillator crystal output/analog input

3. Connections to crystal or resonator in crystal oscillator

mode (HS, XT and LP modes only, GPIO in other modes).

In EXTRC and INTRC modes, the pin output can be conﬁg-

ured to CLK OUT which has 1/4 the frequency of OSC1 and

denotes the instruction cycle rate.

GP5/OSC1/CLKIN 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external clock

source input (GPIO in INTRC mode only, OSC1 in all other

oscillator modes). Schmitt trigger in EXTRC mode only.

1 P — Positive supply for logic and I/O pins

8 P — Ground reference for logic and I/O pins

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,

ST = Schmitt Trigger input

PIC12CE67X

DS40181B-page 10

Preliminary



1998 Microchip Technology Inc.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(EXTRC and

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

INTRC modes)

All instructions are single cycle, e xcept f or an y prog ram br anches . These tak e two cycles since the fetch instruc-

tion is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF GPIO Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF GPIO, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution ﬂow

is shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute

are pipelined such that fetch takes one instruction

cycle while decode and execute takes another

instruction cycle. Howe ver , due to the pipelining, each

instruction effectively executes in one cycle. If an

instruction causes the program counter to change

(e.g.

GOTO

) then two cycles are required to complete

the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the “Instruction Register" (IR) in cycle

Q1. This instruction is then decoded and executed

during the Q2, Q3, and Q4 cycles. Data memory is

read during Q2 (operand read) and written during Q4

(destination write).



1998 Microchip Technology Inc.

Preliminary

DS40181B-page 11

PIC12CE67X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC12CE67X has a 13-bit program counter capa-

ble of addressing an 8K x 14 program memory space.

For the PIC12CE673 the ﬁrst 1K x 14 (0000h-03FFh) is

implemented.

For the PIC12CE674, the ﬁrst 2K x 14 (0000h-07FFh)

is implemented. Accessing a location above the physi-

cally implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 4-1: PIC12CE67X PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

0400h

03FFh

Peripheral

(PIC12CE674 only)

4.2 Data Memory Organization

The data memory is par titioned into two Banks which

contain the General Purpose Registers and the Special

Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1

→

Bank 1

RP0 (STATUS<5>) = 0

→

Bank 0

Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers implemented as

static RAM. Both Bank 0 and Bank 1 contain special

function registers. Some "high use" special function

registers from Bank 0 are mirrored in Bank 1 for code

reduction and quicker access.

Also note that F0h through FFh on the PIC12CE67X is

mapped into Bank 0 registers 70h-7Fh as common

RAM.

4.2.1 GENERAL PURPOSE REGISTER FILE

The register ﬁle can be accessed either directly, or indi-

rectly through the File Select Register FSR

(Section 4.5).

PIC12CE67X

DS40181B-page 12

Preliminary  1998 Microchip Technology Inc.

FIGURE 4-2: PIC12CE67X REGISTER FILE

MAP

INDF(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH

INTCON

PIR1

ADRES

ADCON0

INDF(1)

OPTION

PCL

STATUS

FSR

TRIS

PCLATH

INTCON

PIE1

PCON

ADCON1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

File

Address

OSCCAL

F0h

EFh

Mapped

in Bank 0

70h

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The special function registers can be classiﬁed into two

sets (core and peripheral). Those registers associated

with the “core” functions are described in this section,

and those related to the operation of the peripheral

features are described in the section of that per ipheral

feature.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 13

PIC12CE67X

TABLE 4-1: PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Value on

all other

Resets(3)

Bank 0

00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h(1) PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000

03h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h GPIO SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

06h — Unimplemented — —

07h — Unimplemented — —

08h — Unimplemented — —

09h — Unimplemented — —

0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh(1) INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

0Ch PIR1 — ADIF — — — — — — -0-- ---- -0-- ----

0Dh — Unimplemented — —

0Eh — Unimplemented — —

0Fh — Unimplemented — —

10h — Unimplemented — —

11h — Unimplemented — —

12h — Unimplemented — —

13h — Unimplemented — —

14h — Unimplemented — —

15h — Unimplemented — —

16h — Unimplemented — —

17h — Unimplemented — —

18h — Unimplemented — —

19h — Unimplemented — —

1Ah — Unimplemented — —

1Bh — Unimplemented — —

1Ch — Unimplemented — —

1Dh — Unimplemented — —

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 r CHS1 CHS0 GO/DONE r ADON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.

PIC12CE67X

DS40181B-page 14 Preliminary  1998 Microchip Technology Inc.

Bank 1

80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h(1) PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000

83h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRIS — — GPIO Data Direction Register 0011 1111 0011 1111

86h — Unimplemented — —

87h — Unimplemented — —

88h — Unimplemented — —

89h — Unimplemented — —

8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000

8Bh(1) INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

8Ch PIE1 — ADIE — — — — — — -0-- ---- -0-- ----

8Dh — Unimplemented — —

8Eh PCON — — — — — — POR — ---- --0- ---- --u-

8Fh OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- uuuu uu--

90h — Unimplemented — —

91h — Unimplemented — —

92h — Unimplemented — —

93h — Unimplemented — —

94h — Unimplemented — —

95h — Unimplemented — —

96h — Unimplemented — —

97h — Unimplemented — —

98h — Unimplemented — —

99h — Unimplemented — —

9Ah — Unimplemented — —

9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh — Unimplemented — —

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Value on

all other

Resets(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 15

PIC12CE67X

4.2.2.1 STATUS REGISTER

The STATUS register, shown in Figure 4-3, contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Further more, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

affect the Z, C or DC bits from the STATUS register . For

other instructions, not aff ecting any status bits, see the

"Instruction Set Summary."

Note 1: Bits IRP and RP1 (STATUS<7:6>) are not

used by the PIC12CE67X and should be

maintained clear. Use of these bits as

general purpose R/W bits is NOT recom-

mended, since this may affect upward

compatibility with future products.

Note 2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

FIGURE 4-3: STATUS REGISTER (ADDRESS 03h, 83h)

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved, always maintain this bit clear.

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

PIC12CE67X

DS40181B-page 16 Preliminary  1998 Microchip Technology Inc.

4.2.2.2 OPTION REGISTER

The OPTION register is a readable and writable regis-

ter which contains various control bits to conﬁgure the

TMR0/WDT prescaler, the External INT Interrupt,

TMR0, and the weak pull-ups on GPIO.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

the Watchdog Timer by setting bit PSA

(OPTION<3>).

FIGURE 4-4: OPTION REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GPPU: Weak pullup enable

1 = Weak pullups disabled

0 = Weak pullups enabled (GP0, GP1, GP3)

bit 6: INTEDG: Interrupt edge

1 = Interrupt on rising edge of GP2/T0CKI/AN2/INT pin

0 = Interrupt on falling edge of GP2/T0CKI/AN2/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on GP2/T0CKI/AN2/INT pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin

0 = Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 1998 Microchip Technology Inc. Preliminary DS40181B-page 17

PIC12CE67X

4.2.2.3 INTCON REGISTER

The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the

TMR0 register overﬂow, GPIO Por t change and Exter-

nal GP2/INT Pin interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

FIGURE 4-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4: INTE: INT External Interrupt Enable bit

1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin

0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin

bit 3: GPIE: GPIO Interrupt on Change Enable bit

1 = Enables the GPIO Interrupt on Change

0 = Disables the GPIO Interrupt on Change

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

bit 1: INTF: INT External Interrupt Flag bit

1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)

0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur

bit 0: GPIF: GPIO Interrupt on Change Flag bit

1 = GP0, GP1, or GP3 pins changed state (must be cleared in software)

0 = Neither GP0, GP1, nor GP3 pins have changed state

PIC12CE67X

DS40181B-page 18 Preliminary  1998 Microchip Technology Inc.

4.2.2.4 PIE1 REGISTER

This register contains the individual enable bits for the

Peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-6: PIE1 REGISTER (ADDRESS 8Ch)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— ADIE — — — — — — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0'

bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5-0: Unimplemented: Read as '0'

 1998 Microchip Technology Inc. Preliminary DS40181B-page 19

PIC12CE67X

4.2.2.5 PIR1 REGISTER

This register contains the individual ﬂag bits for the

Peripheral interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt ﬂag bits are clear prior to enabling an

interrupt.

FIGURE 4-7: PIR1 REGISTER (ADDRESS 0Ch)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— ADIF — — — — — — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0'

bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed

0 = The A/D conversion is not complete

bit 5-0: Unimplemented: Read as '0'

PIC12CE67X

DS40181B-page 20 Preliminary  1998 Microchip Technology Inc.

4.2.2.6 PCON REGISTER

The Power Control (PCON) register contains a ﬂag bit

to allow differentiation between a Power-on Reset

(POR), an external MCLR Reset, and WDT Reset.

FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — POR — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0'

bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: Unimplemented: Read as '0'

 1998 Microchip Technology Inc. Preliminary DS40181B-page 21

PIC12CE67X

4.2.2.7 OSCCAL REGISTER

The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal 4 MHz oscillator. It contains six

bits for calibration. Increasing the cal value increases

the frequency.

FIGURE 4-9: OSCCAL REGISTER (ADDRESS 8Fh)

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: CAL<5:0>: Calibration

bit 1-0: Unimplemented, read as 0

PIC12CE67X

DS40181B-page 22 Preliminary  1998 Microchip Technology Inc.

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide . The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any reset, the PC is cleared. Figure 4-10 shows the

two situations for the loading of the PC. The upper

example in the ﬁgure shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lo wer e xam-

ple in the ﬁgure shows how the PC is loaded during a

CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-10: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an off-

set to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be e x ercised if the tab le location crosses a PCL

memory boundar y (each 256 byte block). Refer to the

application note

“Implementing a Table Read"

(AN556).

PC 12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

PC 12 11 10 0

PCLATH<4:3>

PCH PCL

8 7

PCLATH

PCH PCL

PCL as

Destination

4.3.2 STACK

The PIC12C67X family has an 8 level deep x 13-bit

wide hardware stack. The stack space is not part of

either program or data space and the stack pointer is

not readable or writable. The PC is PUSHed onto the

stack when a CALL instruction is executed or an inter-

rupt causes a branch. The stack is POPed in the event

of a RETURN, RETLW or a RETFIE instruction ex ecution.

PCLATH is not affected by a PUSH or POP operation.

The stack oper ates as a circular buff er . This means that

after the stack has been PUSHed eight times , the ninth

push ov erwrites the v alue that w as stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

4.4 Program Memory Paging

The PIC12CE67X ignores both paging bits

PCLATH<4:3>, which are used to access program

memory when more than one page is available. The

use of PCLATH<4:3> as general purpose read/write

bits for the PIC12CE67X is not recommended since

this may affect upward compatibility with future prod-

ucts.

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the e xecution of the CALL,

RETURN, RETLW, and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 23

PIC12CE67X

4.5 Indirect Addressing, INDF and FSR

Registers

The INDF register is not a ph ysical register . Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses the register pointed to by the File Select Reg-

ister , FSR. Reading the INDF register itself indirectly

(FSR = '0') will read 00h. Writing to the INDF register

indirectly results in a no-operation (although status bits

may be affected). An effectiv e 9-bit address is obtained

by concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 4-11. However, IRP

is not used in the PIC12CE67X.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

CONTINUE

: ;yes continue

FIGURE 4-11: DIRECT/INDIRECT ADDRESSING

For register ﬁle map detail see Figure 4-2.

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

bank select location select

(1)RP1 RP0 6 0

from opcode IRP(1) FSR register

bank select location select

00 01 10 11 180h

1FFh

00h

7Fh Bank 0 Bank 1 Bank 2 Bank 3

not used

PIC12CE67X

DS40181B-page 24 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 25

PIC12CE67X

5.0 I/O PORT

As with any other register, the I/O register can be

written and read under program control. However,

read instructions (e.g., MOVF GPIO,W) always read the

I/O pins independent of the pin’s input/output modes.

On RESET, all I/O ports are deﬁned as input (inputs

are at hi-impedance) since the I/O control registers are

all set.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits

are used (GP5:GP0). Bits 6 and 7 (SDA and SCL) are

used by the EEPROM peripheral. Refer to Section 6.0

and Appendix A for use of SDA and SCL. Please note

that GP3 is an input only pin. The conﬁguration word

can set several I/O’s to alternate functions. When

acting as alternate functions the pins will read as ‘0’

during port read. Pins GP0, GP1, and GP3 can be

conﬁgured with weak pull-ups and also with interrupt

on change. The interrupt on change and weak pull-up

functions are not pin selectable. If pin 4 is conﬁgured

as MCLR, the weak pull-up is always on. Interrupt on

change for this pin is not set and GP3 will read as '0'.

Interrupt on change is enabled by setting INTCON<3>.

Note that external oscillator use overrides the GPIO

functions on GP4 and GP5.

5.2 TRIS Register

This register controls the data direction for GPIO. A '1'

from a TRIS register bit puts the corresponding output

driver in a hi-impedance mode. A '0' puts the contents

of the output data latch on the selected pins, enabling

the output buffer. The exceptions are GP3 which is

input only and its TRIS bit will always read as '1'.

Upon reset, the TRIS register is all '1's, making all pins

inputs.

TRIS for pins GP4 and GP5 is forced to a 1 where

appropriate. Writes to TRIS <5:4> will have an effect

in EXTRC and INTRC oscillator modes only. When

GP4 is conﬁgured as CLKOUT, changes to TRIS<4>

will have no effect.

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-2. All port pins, except GP3 which is input

only, may be used for both input and output

operations. For input operations these ports are non-

latching. Any input must be present until read by an

input instruction (e.g., MOVF GPIO,W). The outputs are

latched and remain unchanged until the output latch is

Note: A read of the por ts reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the por t will indicate that the pin is

low.

rewritten. To use a port pin as output, the

corresponding direction control bit in TRIS must be

cleared (= 0). For use as an input, the corresponding

TRIS bit must be set. Any I/O pin (except GP3) can be

programmed individually as input or output.

Port pins GP6 and GP7 are used for the serial

EEPROM interface. These por t pins are not available

externally on the package. Users should avoid writing

to pins GP6 and GP7 when not communicating with

the serial EEPROM memory. Please see section 6.0,

EEPROM Peripheral Operation, for information on

serial EEPROM communication.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note: On a Power-on Reset, GP0, GP1, GP2,

GP4 are conﬁgured as analog inputs and

read as '0'.

Note 1: I/O pins have protection diodes to VDD and VSS.

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

pin(1)

Reg

Latch

Reset

GP3 is input only with no data latch and no

output drivers.

PIC12CE67X

DS40181B-page 26 Preliminary  1998 Microchip Technology Inc.

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

85h TRIS — — GPIO Data Direction Register --11 1111 --11 1111

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 000q quuu

05h GPIO SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,

q = see tables in Section 9.4 for possible values.

Note 1: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result back

to the register. Caution must be used when these

instructions are applied to a por t with both inputs and

outputs deﬁned. For example, a BSF operation on bit5

of GPIO will cause all eight bits of GPIO to be read into

the CPU. Then the BSF operation takes place on bit5

and GPIO is written to the output latches. If another bit

of GPIO is used as a bi-directional I/O pin (e.g., bit0)

and it is deﬁned as an input at this time, the input signal

present on the pin itself would be read into the CPU

and rewritten to the data latch of this particular pin,

overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However,

if bit0 is switched to an output, the content of the data

latch may now be unknown.

Reading the por t register, reads the values of the por t

pins. Writing to the port register wr ites the value to the

port latch. When using read-modify-write instructions

(ex. BCF, BSF, etc.) on a port, the value of the port pins

is read, the desired operation is done to this v alue , and

this value is then written to the port latch.

Example 5-1 shows the effect of two sequential read-

modify-write instructions on an I/O port.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

;Initial GPIO Settings

; GPIO<5:3> Inputs

; GPIO<2:0> Outputs

;

; GPIO latch GPIO pins

; ---------- ----------

BCF GPIO, 5 ;--01 -ppp --11 pppp

BCF GPIO, 4 ;--10 -ppp --11 pppp

MOVLW 007h ;

TRIS GPIO ;--10 -ppp --11 pppp

;

;Note that the user may have expected the pin

;values to be --00 pppp. The 2nd BCF caused

;GP5 to be latched as the pin value (High).

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the le vel on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

GP5:GP0

MOVWF GPIO NOP

Port pin

sampled here

NOP

MOVF GPIO,W

Instruction

executed MOVWF GPIO

(Write to

GPIO)

NOP

MOVF GPIO,W

This example shows a write to GPIO follo wed

by a read from GPIO.

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle.

TPD = propagation delay

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

(Read

GPIO)

Port pin

written here

 1998 Microchip Technology Inc. Preliminary DS40181B-page 27

PIC12CE67X

6.0 EEPROM PERIPHERAL

OPERATION

The PIC12CE673 and PIC12CE674 each have 16

bytes of EEPROM data memor y. The EEPROM mem-

ory has an endurance of 1,000,000 erase/write cycles

and a data retention of greater than 40 years. The

EEPROM data memory supports a bi-directional 2-wire

bus and data transmission protocol. These two-wires

are serial data (SDA) and serial clock (SCL), that are

mapped to bit6 and bit7, respectively, of the GPIO reg-

ister (SFR 06h). Unlike the GP0-GP5 that are con-

nected to the I/O pins, SDA and SCL are only

connected to the internal EEPROM peripheral. For

most applications, all that is required is calls to the fol-

lowing functions:

; Byte_Write: Byte write routine

; Inputs: EEPROM Address EEADDR

; EEPROM Data EEDATA

; Outputs: Return 01 in W if OK, else

return 00 in W

;

; Read_Current: Read EEPROM at address

currently held by EE device.

; Inputs: NONE

; Outputs: EEPROM Data EEDATA

; Return 01 in W if OK, else

return 00 in W

;

; Read_Random: Read EEPROM byte at supplied

address

; Inputs: EEPROM Address EEADDR

; Outputs: EEPROM Data EEDATA

; Return 01 in W if OK,

else return 00 in W

The code for these functions is available on our web

site (www.microchip.com). The code will be accessed

by either including the source code FL67XINC.ASM or

by linking FLASH67X.ASM. FLASH62.IMC provides

external deﬁnition to the calling program.

6.0.1 SERIAL DATA

SDA is a bi-directional pin used to transfer addresses

and data into and data out of the device.

For normal data transf er SD A is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

6.0.2 SERIAL CLOCK

This SCL input is used to synchroniz e the data transf er

from and to the EEPROM.

6.1 BUS CHARACTERISTICS

The following bus protocol is to be used with the

EEPROM data memory. In this section, the term “pro-

cessor” is used to denote the portion of the

PIC12CE67X that interfaces to the EEPROM via soft-

ware.

•Data transfer may be initiated only when the bus

is not busy.

During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH will be interpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 6-1).

6.1.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

6.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

6.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

6.1.4 DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the processor

device and is theoretically unlimited.

6.1.5 ACKNOWLEDGE

The EEPROM, when addressed, will generate an

acknowledge after the reception of each byte . The pro-

cessor must generate an extra clock pulse which is

associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. The processor must signal an end of data to

the EEPROM by not generating an ac kno wledge bit on

the last byte that has been cloc ked out of the EEPROM.

In this case, the EEPROM must leave the data line

HIGH to enable the processor to generate the STOP

condition (Figure 6-2).

Note: Acknowledge bits are not generated if an

internal programming cycle is in progress.

PIC12CE67X

DS40181B-page 28 Preliminary  1998 Microchip Technology Inc.

FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 6-2: ACKNOWLEDGE TIMING

(A) (B) (C) (D) (A)(C)

SCL

SDA

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL 987654321 1 2 3

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Data from transmitter Data from transmitter

SDA

Acknowledge

Bit

6.2 Device Addressing

After generating a START condition, the processor

transmits a control byte consisting of a EEPROM

address and a Read/Write bit that indicates what type

of operation is to be perf ormed. The EEPROM address

consists of a 4-bit de vice code (1010) f ollowed b y three

don't care bits.

The last bit of the control byte determines the operation

to be perf ormed. When set to a one a read operation is

selected, and when set to a zero a write operation is

selected. (Figure 6-3). The bus is monitored for its cor-

responding EEPROM address all the time. It generates

an acknowledge bit if the EEPROM address was true

and it is not in a programming mode.

FIGURE 6-3: CONTROL BYTE FORMAT

1 0 1 0 X X XS ACKR/W

Device Select

Bits Don’t Care

Bits

EEPROM Address

Acknowledge Bit

Start Bit

Read/Write Bit

 1998 Microchip Technology Inc. Preliminary DS40181B-page 29

PIC12CE67X

6.3 WRITE OPERATIONS

6.3.1 BYTE WRITE

Following the start signal from the processor, the

device code (4 bits), the don't care bits (3 bits), and the

R/W bit (which is a logic low) are placed onto the bus

by the processor. This indicates to the addressed

EEPROM that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the processor is the w ord address and will be written

into the address pointer. Only the lower four address

bits are used by the device, and the upper four bits are

don’t cares. The address byte is acknowledgeable and

the processor will then transmit the data word to be

written into the addressed memory location. The mem-

ory acknowledges again and the processor generates

a stop condition. This initiates the inter nal write cycle,

and during this time will not generate ackno wledge sig-

nals (Figure 6-5). After a byte write command, the inter-

nal address counter will not be incremented and will

point to the same address location that was just written.

If a stop bit is transmitted to the device at any point in

the write command sequence before the entire

sequence is complete, then the command will abort

and no data will be written. If more than 8 data bits are

transmitted before the stop bit is sent, then the device

will clear the previously loaded byte and begin loading

the data buffer again. If more than one data byte is

transmitted to the de vice and a stop bit is sent before a

full eight data bits hav e been transmitted, then the write

command will abort and no data will be written. The

EEPROM memory employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below minimum VDD. Byte write operations

must be preceded and immediately followed by a bus

not busy bus cycle where both SDA and SCL are held

high.

6.4 ACKNOWLEDGE POLLING

Since the EEPROM will not ac knowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the processor, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the proces-

sor sending a start condition followed by the control

byte f or a write command (R/W = 0). If the device is still

busy with the write cycle, then no A CK will be returned.

If no A CK is returned, then the start bit and control byte

must be re-sent. If the cycle is complete, then the

device will retur n the ACK and the processor can then

proceed with the next read or write command. See

Figure 6-4 for ﬂow diagram.

FIGURE 6-4: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did EEPROM

Acknowledge

(ACK = 0)?

Operation

YES

FIGURE 6-5: BYTE WRITE

BUS ACTIVITY

PROCESSOR

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS DATA

1 0 X1 0 XX X

X = Don’t Care Bit

X X X

PIC12CE67X

DS40181B-page 30 Preliminary  1998 Microchip Technology Inc.

6.5 READ OPERATIONS

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

EEPROM address is set to one. There are three basic

types of read operations: current address read, random

read, and sequential read.

6.5.1 CURRENT ADDRESS READ

It contains an address counter that maintains the

address of the last word accessed, internally incre-

mented by one. Therefore, if the previous read access

was to address n, the ne xt current address read oper a-

tion would access data from address n + 1. Upon

receipt of the EEPROM address with the R/W bit set to

one, the EEPROM issues an acknowledge and trans-

mits the eight bit data word. The processor will not

acknowledge the transfer but does generate a stop

condition and the EEPROM discontinues transmission

(Figure 6-6).

6.5.2 RANDOM READ

Random read operations allow the processor to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address m ust

be set. This is done by sending the word address to the

EEPROM as part of a write operation. After the word

address is sent, the processor generates a start condi-

tion following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the processor issues the control

byte again but with the R/W bit set to a one. It will then

issue an acknowledge and transmits the eight bit data

word. The processor will not acknowledge the transfer

but does generate a stop condition and the EEPROM

discontinues transmission (Figure 6-7). After this com-

mand, the internal address counter will point to the

address location following the one that was just read.

6.5.3 SEQUENTIAL READ

Sequential reads are initiated in the same wa y as a ran-

dom read e xcept that after the device tr ansmits the ﬁrst

data byte, the processor issues an acknowledge as

opposed to a stop condition in a random read. This

directs the EEPROM to transmit the next sequentially

addressed 8-bit word (Figure 6-8).

To provide sequential reads, it contains an internal

address pointer which is incremented by one at the

completion of each read operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

FIGURE 6-6: CURRENT ADDRESS READ

FIGURE 6-7: RANDOM READ

FIGURE 6-8: SEQUENTIAL READ

BUS ACTIVITY

PROCESSOR

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA

1 10 0 X X X 1

X = Don’t Care Bit

BUS ACTIVITY

PROCESSOR

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n) CONTROL

BYTE

DATA (n)

X X X X

S 1 10 0 X X X 0 S 1 10 0 X X X 1

X = Don’t Care Bit

BUS ACTIVITY

PROCESSOR

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

 1998 Microchip Technology Inc. Preliminary DS40181B-page 31

PIC12CE67X

7.0 TIMER0 MODULE

The Timer0 module timer/counter has the following f ea-

tures:

•8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simpliﬁed block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increment e very instruction cycle (without prescaler). If

the TMR0 register is wr itten, the increment is inhibited

for the following two instruction cycles (Figure 7-2 and

Figure 7-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In counter mode, Timer0 will increment

either on e very rising or falling edge of pin RA4/T0CKI.

The incrementing edge is determined by the Timer0

Source Edge Select bit T0SE (OPTION<4>). Clear ing

bit T0SE selects the rising edge. Restrictions on the

external clock input are discussed in detail in

Section 7.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The pres-

caler assignment is controlled in software b y control bit

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readable or writable . When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, ...,

1:256 are selectable. Section 7.3 details the operation

of the prescaler.

7.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overﬂows from FFh to 00h. This overﬂow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software b y the Timer0 module interrupt ser-

vice routine bef ore re-enabling this interrupt. The TMR0

interrupt cannot awaken the processor from SLEEP

since the timer is shut off during SLEEP. See Figure 7-

4 for Timer0 interrupt timing.

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).

GP2/T0CKI/

T0SE

AN2/INT

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks TMR0

PSout

(2 TCY delay)

PSout

Data bus

PSA

PS2, PS1, PS0 Set interrupt

ﬂag bit T0IF

on overﬂow

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PIC12CE67X

DS40181B-page 32 Preliminary  1998 Microchip Technology Inc.

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 7-4: TIMER0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit

(INTCON<2>)

FEh

GIE bit

(INTCON<7>)

INSTRUCTION

Instruction

fetched

PC PC +1 PC +1 0004h 0005h

Instruction

executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 3Tcy where Tcy = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

FLOW

 1998 Microchip Technology Inc. Preliminary DS40181B-page 33

PIC12CE67X

7.2 Using Timer0 with an External Clock

When an e xternal clock input is used f or Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the exter nal clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 7-5).

Therefore, it is necessary for T0CKI to be high for at

least 2Tosc (and a small RC delay of 20 ns) and lo w f or

at least 2Tosc (and a small RC dela y of 20 ns). Ref er to

the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple-counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4Tosc (and a small RC delay of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to par am-

eters 40, 41 and 42 in the electrical speciﬁcation of the

desired device.

7.2.2 TMR0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0 mod-

ule is actually incremented. Figure 7-5 shows the dela y

from the e xternal clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or

Prescaler output (2)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

(3) (1)

PIC12CE67X

DS40181B-page 34 Preliminary  1998 Microchip Technology Inc.

7.3 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 7-6). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

available which is m utually e xclusiv ely shared betw een

the Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer, and

vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler . When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the Watchdog Timer. The prescaler is not

readable or writable.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

GP2/T0CKI/

T0SE

AN2/INT

CLKOUT (=Fosc/4)

SYNC

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

 1998 Microchip Technology Inc. Preliminary DS40181B-page 35

PIC12CE67X

7.3.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program

execution.

EXAMPLE 7-1: CHANGING PRESCALER

(TIMER0→WDT)

BCF STATUS, RP0 ;Bank 0

CLRF TMR0 ;Clear TMR0 & Prescaler

BSF STATUS, RP0 ;Bank 1

CLRWDT ;Clears WDT

MOVLW b'xxxx1xxx' ;Select new prescale

MOVWF OPTION_REG ;value & WDT

BCF STATUS, RP0 ;Bank 0

Note: To av oid an unintended de vice RESET, the

following instruction sequence (shown in

Example 7-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This sequence must

be followed even if the WDT is disabled.

To change prescaler from the WDT to the Timer0 mod-

ule use the sequence shown in Example 7-2.

EXAMPLE 7-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW b'xxxx0xxx' ;Select TMR0, new

;prescale value and

MOVWF OPTION_REG ;clock source

BCF STATUS, RP0 ;Bank 0

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRIS — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC12CE67X

DS40181B-page 36 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 37

PIC12CE67X

FIGURE 8-1: ADCON0 REGISTER (ADDRESS 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0 r CHS1 CHS0 GO/DONE r ADON R =Readable bit

W =Writable bit

U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = FOSC/2

01 = FOSC/8

10 = FOSC/32

11 = FRC (clock derived from an RC oscillation)

bit 5: Reserved

bit 4-3: CHS1:CHS0: Analog Channel Select bits

00 = channel 0, (GP0/AN0)

01 = channel 1, (GP1/AN1)

10 = channel 2, (GP2/AN2)

11 = channel 3, (GP4/AN3)

bit 2: GO/DONE: A/D Conversion Status bit

If ADON = 1

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete)

bit 1: Reserved

bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

8.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has four

analog inputs.

The A/D allows conversion of an analog input signal to

a corresponding 8-bit digital number (refer to Applica-

tion Note AN546 for use of A/D Converter). The output

of the sample and hold is the input into the conver ter,

which generates the result via successive approxima-

tion. The analog reference voltage is software select-

able to either the de vice’s positive supply voltage (V DD)

or the voltage lev el on the GP1/AN1/ VREF pin. The A/D

converter has a unique feature of being ab le to operate

while the device is in SLEEP mode.

The A/D module has three registers. These registers

are: • A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Figure 8-1, controls

the operation of the A/D module. The ADCON1 regis-

ter, shown in Figure 8-2, conﬁgures the functions of the

port pins. The port pins can be conﬁgured as analog

inputs (GP1 can also be a voltage reference) or as dig-

ital I/O.

Note: If the port pins are conﬁgured as analog

inputs (reset condition), reading the port

(MOVF GP,W) results in reading '0's.

Note: Changing ADCON1 register can cause the

GPIF and INTF ﬂags to be set in the

INTCON register. These interrupts should

be disabled prior to modifying ADCON1.

PIC12CE67X

DS40181B-page 38 Preliminary  1998 Microchip Technology Inc.

FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

W =Writable bit

U =Unimplemented

bit, read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0'

bit 1-0: PCFG2:PCFG0: A/D Port Conﬁguration Control bits

A = Analog input

D = Digital I/O

Note 1: Value on reset.

Note 2: Any instruction that reads a pin conﬁgured as an analog input will read a '0'.

PCFG2:PCFG0 GP4 GP2 GP1 GP0 VREF

000(1) A AAAVDD

001 A A VREF A GP1

010 D AAAVDD

011 D A VREF A GP1

100 D D A A VDD

101 D D VREF A GP1

110 D D D A VDD

111 D DDDVDD

 1998 Microchip Technology Inc. Preliminary DS40181B-page 39

PIC12CE67X

The ADRES register contains the result of the A/D con-

version. When the A/D conversion is complete, the

result is loaded into the ADRES register , the GO/DONE

bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit

ADIF (PIE1<6>) is set. The block diagrams of the A/D

module are shown in Figure 8-3.

After the A/D module has been conﬁgured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine sample time, see Section 8.1. After

this acquisition time has elapsed the A/D conversion

can be star ted. The following steps should be followed

for doing an A/D conversion:

1. Conﬁgure the A/D module:

• Conﬁgure analog pins / voltage reference /

and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit

ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

deﬁned as TAD. A minimum wait of 2TAD is

required before next acquisition starts.

FIGURE 8-3: A/D BLOCK DIAGRAM

(Input voltage)

VIN

VREF

(Reference

voltage)

VDD

PCFG2:PCFG0

CHS1:CHS0

000 or

010 or

100 or

001 or

GP4/AN3

GP0/AN0

GP2/AN2

GP1/AN1/VREF

A/D

Converter

011 or

101

110 or

PIC12CE67X

DS40181B-page 40 Preliminary  1998 Microchip Technology Inc.

8.1 A/D Sampling Requirements

For the A/D converter to meet its speciﬁed accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), see

Figure 8-4. The maximum recommended imped-

ance for analog sources is 10 kΩ. After the analog

input channel is selected (changed) this acquisition

must be done before the conversion can be started.

To calculate the minimum acquisition time, Equation 8-

1 may be used. This equation assumes that 1/2 LSb

error is used (512 steps f or the A/D). The 1/2 LSb error

is the maximum error allowed for the A/D to meet its

speciﬁed resolution.

EQUATION 8-1: A/D MINIMUM CHARGING

TIME

VHOLD = (VREF - (VREF/512)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))

Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)

Example 8-1 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following system assumptions.

Rs = 10 kΩ

1/2 LSb error

VDD = 5V → Rss = 7 kΩ

Temp (system max.) = 50°C

VHOLD = 0 @ t = 0

EXAMPLE 8-1: CALCULATING THE

MINIMUM REQUIRED

SAMPLE TIME

TACQ = Ampliﬁer Settling Time +

Holding Capacitor Charging Time +

Temperature Coefﬁcient

TACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]

TC = -CHOLD (RIC + RSS + RS) ln(1/512)

-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)

-51.2 pF (18 kΩ) ln(0.0020)

-0.921 µs (-6.2146)

5.724 µs

TACQ = 5 µs + 5.724 µs + [(50°C - 25°C)(0.05 µs/°C)]

10.724 µs + 1.25 µs

11.974 µs

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

Note 2: The charge holding capacitor (CHOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 kΩ. This is

required to meet the pin leakage speciﬁ-

cation.

Note 4: After a conversion has completed, a

2.0 TAD delay must complete before

acquisition can begin again. During this

time the holding capacitor is not con-

nected to the selected A/D input channel.

FIGURE 8-4: ANALOG INPUT MODEL

CPIN

Rs RAx

5 pF

VDD

VT = 0.6V

VT = 0.6V I leakage

RIC ≤ 1k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

5 6 7 8 9 10 11

( kΩ )

VDD

= 51.2 pF

± 500 nA

Legend CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

 1998 Microchip Technology Inc. Preliminary DS40181B-page 41

PIC12CE67X

8.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is deﬁned as TAD. The

A/D conversion requires 9.5 TAD per 8-bit conversion.

The source of the A/D conversion clock is software

selected. The four possible options for TAD are:

• 2TOSC

• 8TOSC

• 32TOSC

• Internal ADC RC oscillator

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 1.6 µs.

Table 8-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

8.3 Configuring Analog Port Pins

The ADCON1 and TRIS registers control the operation

of the A/D por t pins. The por t pins that are desired as

analog inputs must have their corresponding TRIS bits

set (input). If the TRIS bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

Note 1: When reading the port register, all pins

conﬁgured as analog input channel will

read as cleared (a low level). Pins conﬁg-

ured as digital inputs, will convert an ana-

log input. Analog levels on a digitally

conﬁgured input will not aff ect the conv er-

sion accuracy.

Note 2: Analog le vels on an y pin that is deﬁned as

a digital input (including the AN3:AN0

pins), may cause the input buffer to con-

sume current that is out of the devices

speciﬁcation.

TABLE 8-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)Device Frequency

Operation ADCS1:ADCS0 4 MHz 1.25 MHz 333.33 kHz

2TOSC 00 500 ns(2) 1.6 µs 6 µs

8TOSC 01 2.0 µs 6.4 µs24 µs(3)

32TOSC 10 8.0 µs25.6 µs(3) 96 µs(3)

Internal ADC RC Oscillator(5) 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1)

Note 1: The RC source has a typical TAD time of 4 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of speciﬁcation.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

PIC12CE67X

DS40181B-page 42 Preliminary  1998 Microchip Technology Inc.

8.4 A/D Conversions

Example 8-2 show how to perform an A/D conversion.

The GP pins are conﬁgured as analog inputs. The ana-

log reference (VREF) is the device VDD. The A/D inter-

rupt is enabled, and the A/D conversion clock is FRC.

The conversion is performed on the GP0 channel.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The ADRES register will

NOT be updated with the partially completed A/D con-

version sample. That is, the ADRES register will con-

tinue to contain the value of the last completed

conversion (or the last v alue written to the ADRES reg-

ister). After the A/D conversion is aborted, a 2TAD wait

is required before the next acquisition is started. After

this 2TAD wait, an acquisition is automatically started

on the selected channel.

EXAMPLE 8-2: DOING AN A/D CONVERSION

BSF STATUS, RP0 ; Select Page 1

CLRF ADCON1 ; Configure A/D inputs

BSF PIE1, ADIE ; Enable A/D interrupts

BCF STATUS, RP0 ; Select Page 0

MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected

MOVWF ADCON0 ;

BCF PIR1, ADIF ; Clear A/D interrupt flag bit

BSF INTCON, PEIE ; Enable peripheral interrupts

BSF INTCON, GIE ; Enable all interrupts

;

; Ensure that the required sampling time for the selected input channel has elapsed.

; Then the conversion may be started.

;

BSF ADCON0, GO ; Start A/D Conversion

: ; The ADIF bit will be set and the GO/DONE bit

: ; is cleared upon completion of the A/D Conversion.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 43

PIC12CE67X

8.5 A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switching noise from the conversion. When the conv er-

sion is completed the GO/DONE bit will be cleared, and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interrupt is not enabled, the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clock source is another cloc k option (not

RC), a SLEEP instruction will cause the present conv er-

sion to be aborted and the A/D module to be turned off,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current consumption state.

8.6 A/D Accuracy/Error

The ov er all accuracy of the A/D is less than ± 1 LSb f or

VDD = 5V ± 10% and the analog VREF = VDD. This over-

all accuracy includes offset error, full scale error, and

integral error. The A/D converter is guaranteed to be

monotonic. The resolution and accuracy may be less

when either the analog reference (VDD) is less than

5.0V or when the analog reference (VREF) is less than

VDD.

The maximum pin leakage current is ± 5 µA.

In systems where the device frequency is low, use of

the A/D RC clock is preferred. At moderate to high fre-

quencies, TAD should be derived from the device oscil-

lator. TAD must not violate the minimum and should be

≤ 8 µs for preferred operation. This is because TAD,

when derived from TOSC, is kept away from on-chip

phase clock tr ansitions. This reduces, to a large extent,

the eff ects of digital switching noise. This is not possible

with the RC derived clock. The loss of accuracy due to

digital switching noise can be signiﬁcant if many I/O

pins are active.

In systems where the device will enter SLEEP mode

after the start of the A/D conversion, the RC clock

source selection is required. In this mode, the digital

noise from the modules in SLEEP are stopped. This

method gives high accuracy.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To perfor m an A/D

conversion in SLEEP, the GO/DONE bit

must be set, f ollowed b y the SLEEP instruc-

tion.

8.7 Effects of a RESET

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conversion is abor ted. The value that is in the ADRES

ter will contain unknown data after a Power-on Reset.

8.8 Connection Considerations

If the input voltage e xceeds the rail v alues (VSS or VDD)

by greater than 0.2V, then the accuracy of the conver-

sion is out of speciﬁcation.

An e xternal RC ﬁlter is sometimes added for anti-alias-

ing of the input signal. The R component should be

selected to ensure that the total source impedance is

kept under the 10 kΩ recommended speciﬁcation. Any

external components connected (via hi-impedance) to

an analog input pin (capacitor , zener diode, etc.) should

have very little leakage current at the pin.

8.9 Transfer Function

The ideal transf er function of the A/D converter is as fol-

lows: the first transition occurs when the analog input

voltage (VAIN) is 1 LSb (or Analog VREF / 256)

(Figure 8-5).

FIGURE 8-5: A/D TRANSFER FUNCTION

Note: For the PIC12CE67X, care must be taken

when using the GP4 pin in A/D conver-

sions due to its proximity to the OSC1 pin.

Digital code output

FFh

FEh

04h

03h

02h

01h

00h

0.5 LSb

1 LSb

2 LSb

3 LSb

4 LSb

255 LSb

256 LSb

(full scale)

Analog input voltage

PIC12CE67X

DS40181B-page 44 Preliminary  1998 Microchip Technology Inc.

FIGURE 8-6: FLOWCHART OF A/D OPERATION

TABLE 8-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Value on

all other

Resets(1)

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

0Ch PIR1 — ADIF — — — — — — -0-- ---- -0-- ----

8Ch PIE1 — ADIE — — — — — — -0-- ---- -0-- ----

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 r CHS1 CHS0 GO/DONE r ADON 0000 0000 0000 0000

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

85h TRIS — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', r = reserved. Shaded cells are not used for A/D conv ersion.

Note 1: These registers can be addressed from either bank.

Acquire

ADON = 0

ADON = 0?

GO = 0?

A/D Clock

GO = 0

ADIF = 0

Abort Conversion

SLEEP

Power-down A/D Wait 2 TAD

Wake-up

Yes

Finish Conversion

GO = 0

ADIF = 1

Device in

Yes

Finish Conversion

GO = 0

ADIF = 1

Wait 2 TAD

Stay in Sleep

Selected Channel

= RC? SLEEP

Yes

Instruction?

Start of A/D

Conversion Delayed

1 Instruction Cycle

From Sleep?

Power-down A/D

Yes

Wait 2 TAD

Finish Conversion

GO = 0

ADIF = 1

SLEEP?

 1998 Microchip Technology Inc. Preliminary DS40181B-page 45

PIC12CE67X

9.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits to deal with the needs of real-

time applications. The PIC12CE67X family has a host

of such features intended to maximize system reliabil-

ity, minimize cost through elimination of external com-

ponents, provide power saving operating modes and

offer code protection. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

The PIC12CE67X has a W atchdog Timer which can be

shut off only through conﬁguration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that off er necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable . The

other is the Po w er-up Timer (PWRT), which provides a

ﬁxed delay of 72 ms (nominal) on power-up only,

designed to keep the part in reset while the power sup-

ply stabilizes. With these two timers on-chip, most

applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wak e-up from SLEEP

through external reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to ﬁt the application.

The EXTRC oscillator option saves system cost while

the LP crystal option saves power. A set of conﬁgura-

tion bits are used to select various options.

9.1 Conﬁguration Bits

The conﬁguration bits can be progr ammed (read as '0')

or left unprogrammed (read as '1') to select various

device conﬁgurations. These bits are mapped in pro-

gram memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special test/conﬁguration memory space (2000h-

3FFFh), which can be accessed only during

programming.

FIGURE 9-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0 Register: CONFIG

Address 2007h

bit13 bit0

bit 13-8, CP1:CP0: Code Protection bit pairs (1)

6-5: 11 = Code protection off

10 = Locations 400h through 7FEh code protected (do not use for PIC12CE673)

01 = Locations 200h through 7FEh code protected

00 = All memory is code protected

bit 7: MCLRE: Master Clear Reset Enable bit

1 = Master Clear Enabled

0 = Master Clear Disabled

bit 4: PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3: WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0: FOSC2:FOSC0: Oscillator Selection bits

111 = EXTRC, Clockout on OSC2

110 = EXTRC, OSC2 is I/O

101 = INTRC, Clockout on OSC2

100 = INTRC, OSC2 is I/O

011 = Invalid Selection

010 = HS Oscillator

001 = XT Oscillator

000 = LP Oscillator

Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

PIC12CE67X

DS40181B-page 46 Preliminary  1998 Microchip Technology Inc.

9.2 Oscillator Conﬁgurations

9.2.1 OSCILLATOR TYPES

The PIC12CE67X can be operated in seven different

oscillator modes. The user can program three

conﬁguration bits (FOSC2:FOSC0) to select one of

these seven modes:

• LP: Low Power Crystal

• HS: High Speed Crystal Resonator

• XT: Crystal/Resonator

• INTRC*: Internal 4 MHz Oscillator

• EXTRC*: External Resistor/Capacitor

*Can be conﬁgured to support CLKOUT

9.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, HS or LP modes, a crystal or ceramic resonator

is connected to the GP5/OSC1/CLKIN and GP4/OSC2

pins to establish oscillation (Figure 9-2). The

PIC12CE67X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal ma y giv e

a frequency out of the crystal manufacturers

speciﬁcations. When in XT, HS or LP modes, the

device can have an external clock source drive the

GP5/OSC1/CLKIN pin (Figure 9-3).

FIGURE 9-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR)

(XT, HS OR LP OSC

CONFIGURATION)

FIGURE 9-3: EXTERNAL CLOCK INPUT

OPERATION (XT, HS OR LP

OSC CONFIGURATION)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required f or

AT strip cut crystals.

3: RF varies with the crystal chosen

(approx. value = 10 MΩ).

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To internal

logic

RS(2)

PIC12CE67X

Clock from

ext. system OSC1

OSC2PIC12CE67X

Open

TABLE 9-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC12CE67X

TABLE 9-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC12CE67X

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Range

XT 455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15-68 pF

HS 4.0 MHz

8.0 MHz

10.0 MHz

15-68 pF

10-68 pF

10-22 pF

15-68 pF

10-68 pF

10-22 pF

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

Osc

Type Resonator

Freq Cap.Range

C1 Cap. Range

LP 32 kHz(1)

100 kHz

200 kHz

15 pF

15-30 pF

15 pF

30-47 pF

15-82 pF

XT 100 kHz

200 kHz

455 kHz

1 MHz

2 MHz

4 MHz

15-30 pF

15-47 pF

200-300 pF

100-200 pF

15-100 pF

15-30 pF

15-47 pF

HS 4 MHz

8 MHz

10 MHz

15-30 pF

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to a v oid

overdriving crystals with low drive lev el speciﬁ cation.

Since each crystal has its own characteristics, the

user should consult the crystal manufacturer for

appropriate values of external components.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 47

PIC12CE67X

9.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used: one with parallel

resonance, or one with series resonance.

Figure 9-4 shows implementation of a parallel

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 kΩ resistor

provides the negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This circuit could be used for external oscillator

designs.

FIGURE 9-4: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 9-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inver ter performs a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 9-5: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04 PIC12CE67X

CLKIN

To Other

Devices

330

74AS04 74AS04 PIC12CE67X

CLKIN

To Other

Devices

XTAL

330

74AS04

0.1 µF

9.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) and capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between pac kage

types will also affect the oscillation frequency,

especially for low Cext values. The user also needs to

take into account variation due to tolerance of exter nal

R and C components used.

Figure 9-6 shows how the R/C combination is

connected to the PIC12CE67X. For Rext values below

2.2 kΩ, the oscillator operation may become unstable,

or stop completely. For very high Rext values

(e.g., 1 MΩ) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

The Electrical Speciﬁcations sections show RC

frequency variation from part to part due to normal

process variation. The variation is larger for larger R

(since leakage current variation will affect RC

frequency more for large R) and for smaller C (since

variation of input capacitance will affect RC frequency

more).

Also, see the Electrical Speciﬁcations sections for

variation of oscillator frequency due to VDD for given

Rext/Cext values as well as frequency variation due to

operating temperature for given R, C , and V DD values.

FIGURE 9-6: EXTERNAL RC OSCILLATOR

MODE

VDD

Rext

Cext

VSS

OSC1 Internal

clock

PIC12CE67X

OSC2/CLKOUT

FOSC/4

PIC12CE67X

DS40181B-page 48 Preliminary  1998 Microchip Technology Inc.

9.2.5 INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator provides a ﬁxed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C, see "Electri-

cal Speciﬁcations" section for information on variation

over voltage and temperature.

In addition, a calibration instruction is programmed into

the last address of the program memory which contains

the calibration value for the internal RC oscillator. This

value is programmed as a RETLW XX instruction where

XX is the calibration value. In order to retr ieve the cali-

bration value, issue a CALL YY instruction where YY is

the last location in program memory (03FFh for the

PIC12CE673, 07FFh f or the PIC12CE674). Control will

be returned to the user’s program with the calibration

value loaded into the W register. The program should

then perform a MOVWF OSCCAL instruction to load

the value into the internal RC oscillator trim register.

OSCCAL, when written to with the calibration value , will

“trim” the internal oscillator to remov e process v ariation

from the oscillator frequency. Only bits <7:2> of OSC-

CAL are implemented, and bits <1:0> should be written

as 0 f or compatibility with future de vices. The oscillator

calibration location is not code protected.

9.2.6 CLKOUT

The PIC12CE67X can be conﬁgured to provide a cloc k

out signal (CLKOUT) on pin 3 when the conﬁguration

word address (2007h) is programmed with FOSC2,

FOSC1, FOSC0 equal to 101 for INTRC or 111 for

EXTRC. The oscillator frequency, divided by 4 can be

used for test purposes or to synchronize other logic.

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the inter nal oscillator.

The calibration value must be saved prior

to erasing the part.

9.3 Reset

The PIC12CE67X diff erentiates betw een various kinds

of reset:

• Power-on Reset (POR)

• MCLR reset during normal operation

• MCLR reset during SLEEP

• WDT Reset (normal operation)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in an y

other reset. Most other registers are reset to a “reset

state” on Power-on Reset (POR), MCLR Reset, WDT

Reset, and MCLR Reset during SLEEP. They are not

affected by a WDT Wake-up, which is viewed as the

resumption of normal operation. The TO and PD bits

are set or cleared diff erently in different reset situations

as indicated in Table 9-4. These bits are used in

software to determine the nature of the reset. See

Table 9-5 for a full description of reset states of all

registers.

A simpliﬁed bloc k diagr am of the on-chip reset circuit is

shown in Figure 9-7.

The PIC12CE67X has a MCLR noise ﬁlter in the MCLR

reset path. The ﬁlter will detect and ignore small pulses.

It should be noted that a WDT Reset

does not drive

MCLR pin low.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 49

PIC12CE67X

FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Weak

Pull-up

GP3/MCLR/VPP Pin

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

On-chip(1)

RC OSC

WDT Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT

SLEEP

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

CLKIN

10-bit Ripple-counter

MCLRE

INTERNAL MCLR

PIC12CE67X

DS40181B-page 50 Preliminary  1998 Microchip Technology Inc.

9.4 Power-on Reset (POR), Power-up

Timer (PWRT) and Oscillator Start-up

Timer (OST)

9.4.1 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in reset until

VDD has reached a high enough le v el f or proper opera-

tion. To take advantage of the POR, just tie the MCLR

pin through a resistor to VDD. This will eliminate exter-

nal RC components usually needed to create a Power-

on Reset. A maximum rise time for VDD is speciﬁed.

See Electrical Speciﬁcations for details.

When the device starts normal operation (exits the

reset condition), de vice operating par ameters (voltage,

frequency, temperature, ...) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met.

For additional information, refer to Application Note

AN607, "

Power-up Trouble Shooting

9.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms nominal

time-out on power-up only, from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in reset as long as the PWR T is active. The

PWRT’s time dela y allo ws VDD to rise to an acceptab le

level. A conﬁguration bit is provided to enable/disable

the PWRT.

The power-up time dela y will v ary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

9.4.3 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is o v er . This ensures that the crystal oscil-

lator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

9.4.4 TIME-OUT SEQUENCE

On power-up the time-out sequence is as follows: First

PWRT time-out is inv oked after the POR time delay has

expired. Then OST is activated. The total time-out will

vary based on oscillator conﬁguration and the status of

the PWRT. For example, in RC mode with the PWRT

disabled, there will be no time-out at all. Figure 9-8,

Figure 9-9, and Figure 9-10 depict time-out sequences

on power-up.

Since the time-outs occur from the POR pulse, if MCLR

is kept lo w long enough, the time-outs will expire . Then

bringing MCLR high will begin execution immediately

(Figure 9-9). This is useful for testing purposes or to

synchronize more than one PIC12CE67X device oper-

ating in parallel.

Table 9-5 shows the reset conditions for all the regis-

ters.

9.4.5 POWER CONTROL (PCON)/STATUS

The power control/status register, PCON (address

8Eh) has one bit. See Figure 4-8 for register.

Bit1 is POR (P o wer-on Reset). It is cleared on a Power-

on Reset and is unaff ected otherwise. The user set this

bit following a Power-on Reset. On subsequent resets

if POR is ‘0’, it will indicate that a Power-on Reset must

have occurred.

TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE

Oscillator Conﬁguration Power-up Wake-up from SLEEP

PWRTE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024TOSC 1024TOSC 1024TOSC

INTRC, EXTRC 72 ms — —

POR TO PD

0 1 1 Power-on Reset

0 0 x Illegal, TO is set on POR

0 x 0 Illegal, PD is set on POR

1 0 u WDT Reset

1 0 0 WDT Wake-up

1 u u MCLR Reset during normal operation

1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP

 1998 Microchip Technology Inc. Preliminary DS40181B-page 51

PIC12CE67X

TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS

TABLE 9-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0 -

MCLR Reset during normal operation 000h 000u uuuu ---- --u-

MCLR Reset during SLEEP 000h 0001 0uuu ---- --u-

WDT Reset during normal operation 000h 0000 uuuu ---- --u-

WDT Wake-up from SLEEP PC + 1 uuu0 0uuu ---- --u-

Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u-

Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

WDT Reset Wake-up via

WDT or Interrupt

Wxxxx xxxx uuuu uuuu uuuu uuuu

INDF 0000 0000 0000 0000 0000 0000

TMR0 xxxx xxxx uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 PC + 1(2)

STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu

GPIO 11xx xxxx 11uu uuuu 11uu uuuu

PCLATH ---0 0000 ---0 0000 ---u uuuu

INTCON 0000 000x 0000 000u uuuu uqqq(1)

PIR1 -0-- ---- -0-- ---- -q-- ----(4)

ADCON0 0000 0000 0000 0000 uuuu uquu(5)

OPTION 1111 1111 1111 1111 uuuu uuuu

TRIS --11 1111 --11 1111 --uu uuuu

PIE1 -0-- ---- -0-- ---- -u-- ----

PCON ---- --0- ---- --u- ---- --u-

OSCCAL 1000 00-- uuuu uu-- uuuu uu--

ADCON1 ---- -000 ---- -000 ---- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 9-5 for reset value for speciﬁc condition.

4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause

bit 6 = u.

5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause

bit 3 = u.

PIC12CE67X

DS40181B-page 52 Preliminary  1998 Microchip Technology Inc.

FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

 1998 Microchip Technology Inc. Preliminary DS40181B-page 53

PIC12CE67X

FIGURE 9-11: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if VDD pow er-up slope is too slow . The

diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate

the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC12CE67X

FIGURE 9-12: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 9-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where Vz = Zener

voltage.

2: Internal brown-out detection should be

disabled when using this circuit.

3: Resistors should be adjusted for the char-

acteristics of the transistor.

VDD 33k

10k

4.3k

VDD

MCLR

PIC12CE67X

Note 1: This brown-out circuit is less e xpensiv e ,

albeit less accurate. Transistor Q1 turns

off when VDD is below a certain level

such that:

2: Internal brown-out detection should be

disabled, if available, when using this

circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD • R1

R1 + R2 = 0.7V

VDD

R2 4.3k PIC12CE67X

VDD

MCLR

PIC12CE67X

DS40181B-page 54 Preliminary  1998 Microchip Technology Inc.

9.5 Interrupts

There are four sources of interrupt:

The interrupt control register (INTCON) records individ-

ual interrupt requests in ﬂag bits. It also has individual

and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s ﬂag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

Interrupt Sources

TMR0 overﬂow interrupt

External interrupt GP2/INT pin

GPIO Port change interrupts (pins GP0, GP1, GP3)

A/D Interrupt

Note: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables interrupts.

The GP2/INT, GPIO port change interrupt and the

TMR0 overﬂow interrupt ﬂags are contained in the

INTCON register.

The peripheral interrupt ﬂag ADIF, is contained in the

special function register PIR1. The corresponding

interrupt enable bit is contained in special function reg-

ister PIE1, and the peripheral interrupt enable bit is

contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as GPIO change

interrupt, the interrupt latency will be three or four

instruction cycles. The e xact latency depends when the

interrupt event occurs (Figure 8-15). The latency is the

same for one or two cycle instructions. Individual inter-

rupt ﬂag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 9-14: INTERRUPT LOGIC

GPIF

GPIE

T0IF

T0IE

GIE

Wakeup

(If in SLEEP mode)

Interrupt to CPU

PEIE

ADIF

ADIE

INTF

INTE

 1998 Microchip Technology Inc. Preliminary DS40181B-page 55

PIC12CE67X

FIGURE 9-15: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTRC and EXTRC oscillator modes.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

PIC12CE67X

DS40181B-page 56 Preliminary  1998 Microchip Technology Inc.

9.5.1 TMR0 INTERRUPT

An overﬂow (FFh → 00h) in the TMR0 register will set

ﬂag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 7.0)

9.5.2 INT INTERRUPT

External interrupt on GP2/INT pin is edge triggered:

either rising if bit INTEDG (OPTION<6>) is set, or fall-

ing, if the INTEDG bit is clear. When a valid edge

appears on the GP2/INT pin, ﬂag bit INTF

(INTCON<1>) is set. This interr upt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interr upt

can wak e-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP. The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 9.8 for details on SLEEP mode.

9.5.3 GPIO INTCON CHANGE

An input change on GP3, GP1 or GP0 sets ﬂag bit

GPIF (INTCON<0>). The interr upt can be enabled/dis-

abled by setting/clearing enable bit GPIE

(INTCON<3>). (Section 5.1)

9.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users ma y wish to sa v e k e y reg-

isters during an interrupt i.e., W register and STATUS

The example:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Executes the ISR code.

d) Restores the STATUS register (and bank select

bit).

e) Restores the W register.

Example 9-1 store and restore the STATUS and W

registers. The register, W_TEMP, must be deﬁned in

both banks and must be deﬁned at the same offset

from the bank base address (i.e., if W_TEMP is

deﬁned at 0x20 in bank 0, it must also be deﬁned at

0xA0 in bank 1).

EXAMPLE 9-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero

SWAPF STATUS,W ;Swap status to be saved into W

BCF STATUS,RP0 ;Change to bank zero, regardless of current bank

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

:(ISR)

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

 1998 Microchip Technology Inc. Preliminary DS40181B-page 57

PIC12CE67X

9.7 Watchdog Timer (WDT)

The Watchdog Timer is a free running on-chip RC oscil-

lator which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the OSC1/CLKIN pin. That means that the WDT will

run, even if the clock on the OSC1/CLKIN and OSC2/

CLKOUT pins of the device has been stopped, for

example, by execution of a SLEEP instruction. During

normal operation, a WDT time-out generates a device

RESET (Watchdog Timer Reset). If the device is in

SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The WDT can be permanently

disabled by clearing conﬁguration bit WDTE

(Section 9.1).

9.7.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out per iods var y with tempera-

ture, VDD and process variations from part to part (see

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler , if assigned to the WDT, and pre vent

it from timing out early and generating a premature

device RESET condition.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

9.7.2 WDT PROGRAMMING CONSIDERATIONS

It should also be taken into account that under worst

case conditions (VDD = Min., Temperature = Max., and

max. WDT prescaler) it may take several seconds

before a WDT time-out occurs.

Note: When the prescaler is assigned to the

WDT, alwa ys execute a CLRWDT instruction

before changing the prescale value, other-

wise a WDT reset may occur.

FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 9-17: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits(1) MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.

From TMR0 Clock Source

(Figure 7-5)

To TMR0 (Figure 7-5)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS2:PS0

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

PIC12CE67X

DS40181B-page 58 Preliminary  1998 Microchip Technology Inc.

9.8 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (STATUS<3>) is cleared, the

TO (STATUS<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D, disable external clocks. Pull all I/O pins, that

are hi-impedance inputs, high or lo w externally to av oid

switching currents caused by ﬂoating inputs. The

T0CKI input if enabled should also be at V DD or VSS for

lowest current consumption. The contribution from on-

chip pull-ups on GPIO should be considered.

The MCLR pin if enabled must be at a logic high level

(VIHMC).

9.8.1 WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. GP2/INT interrupt, interr upt GPIO port change,

or some Peripheral Interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a "wake-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred (and caused

wake-up).

The following peripheral interrupt can wake the device

from SLEEP:

1. A/D conversion (when A/D clock source is RC).

Other peripherals can not generate interrupts since

during SLEEP, no on-chip Q clocks are present.

When the SLEEP instruction is being ex ecuted, the ne xt

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOP after the SLEEP instruction.

9.8.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt ﬂag bit set, one of the follo wing will occur:

•If the interrupt occurs before the the execution of

a SLEEP instruction, the SLEEP instruction will

complete as a NOP. Therefore, the WDT and

WDT postscaler will not be cleared, the T O bit will

not be set and PD bits will not be cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will imme-

diately wake up from sleep . The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

postscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the ﬂag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set bef ore the SLEEP instruction completes. To

determine whether a SLEEP instr uction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 59

PIC12CE67X

FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

GPIO pin

GPIF ﬂag

(INTCON<0>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.

9.9 Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for veriﬁcation purposes.

9.10 ID Locations

Four memory locations (2000h - 2003h) are designated

as ID locations where the user can store checksum or

other code-identiﬁcation numbers. These locations are

not accessible during normal execution but are read-

able and writable during program/verify. It is recom-

mended that only the 4 least signiﬁcant bits of the ID

location are used.

9.11 In-Circuit Serial Programming

PIC12CE67X microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines f or clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent ﬁrmware or a custom ﬁrm-

ware to be programmed.

The device is placed into a program/verify mode by

holding the GP1 and GP0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

speciﬁcation). GP1 (clock) becomes the programming

clock and GP0 (data) becomes the prog ramming data.

Both GP0 and GP1 are Schmitt Trigger inputs in this

mode.

Note: Microchip does not recommend code pro-

tecting windowed devices.

After reset, to place the de vice into programming/v erify

mode, the progr am counter (PC) is at location 00h. A 6-

bit command is then supplied to the de vice. Depending

on the command, 14-bits of program data are then sup-

plied to or from the device, depending if the command

was a load or a read. For complete details of serial pro-

gramming, please refer to the PIC12CE67X Program-

ming Speciﬁcations.

FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC12CE67X

VDD

VSS

MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

PIC12CE67X

DS40181B-page 60 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 61

PIC12CE67X

10.0 INSTRUCTION SET SUMMARY

Each PIC12CE67X instruction is a 14-bit word divided

into an OPCODE which speciﬁes the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC12CE67X instr uc-

tion set summary in Table 10-2 lists byte-oriented, bit-

oriented, and literal and control oper ations. Table 10-

1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle reg-

ister designator and 'd' represents a destination desig-

nator. The ﬁle register designator speciﬁes which ﬁle

The destination designator speciﬁes where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register . If 'd' is one , the result is placed

in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit aff ected

by the oper ation, while 'f' represents the number of the

ﬁle in which the bit is located.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

Field Description

fRegister ﬁle address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit ﬁle register

kLiteral ﬁeld, constant data or label

xDon't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in ﬁle register f.

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

PCLATH Program Counter High Latch

GIE Global Interrupt Enable bit

WDT Watchdog Timer/Counter

TO Time-out bit

PD Power-down bit

dest Destination either the W register or the speciﬁed

[ ] Options

( ) Contents

→Assigned to

< > Register bit ﬁeld

∈In the set of

talics

User deﬁned term (font is courier)

The instruction set is highly orthogonal and is grouped

into three basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle e x ecuted as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an oscillator frequency of 4 MHz, the normal instruction

execution time is 1 µs . If a conditional test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 µs.

Table 10-2 lists the instructions recognized by the

MPASM assembler.

Figure 10-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future PIC12CE67X products, do not use

the OPTION and TRIS instructions.

Byte-oriented ﬁle register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC12CE67X

DS40181B-page 62 Preliminary  1998 Microchip Technology Inc.

10.1 Special Function Registers as

Source/Destination

The PIC12CE67X’s orthogonal instruction set allows

read and write of all ﬁle registers, including special

function registers. There are some special situations

the user should be aware of:

10.1.1 STATUS AS DESTINATION

If an instruction writes to STATUS, the Z, C and DC bits

may be set or cleared as a result of the instruction and

overwrite the original data bits written. For example,

executing CLRF STATUS will clear register STATUS, and

then set the Z bit leaving 0000 0100b in the register.

10.1.2 TRIS AS DESTINATION

Bit 3 of the TRIS register always reads as a '1' since

GP3 is an input only pin. This fact can aff ect some read-

modify-write operations on the TRIS register.

10.1.3 PCL AS SOURCE OR DESTINATION

Read, write or read-modify-write on PCL ma y hav e the

following results:

Read PC: PCL → dest

Write PCL: PCLATH → PCH;

8-bit destination value → PCL

Read-Modify-Write: PCL→ ALU operand

PCLATH → PCH;

8-bit result → PCL

Where PCH = program counter high byte (not an

addressable register), PCLATH = Program counter

high holding latch, dest = destination, WREG or f.

10.1.4 BIT MANIPULATION

All bit manipulation instructions are done by ﬁrst read-

ing the entire register , operating on the selected bit and

writing the result back (read-modify-write). The user

should keep this in mind when operating on special

function registers, such as ports.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 63

PIC12CE67X

TABLE 10-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is ex ecuted on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

PIC12CE67X

DS40181B-page 64 Preliminary  1998 Microchip Technology Inc.

10.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [

label

] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Encoding: 11 111x kkkk kkkk

Description: The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

Words: 1

Cycles: 1

Example ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 00 0111 dfff ffff

Description: Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1

Cycles: 1

Example ADDWF FSR, 0

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0xD9

FSR = 0xC2

ANDLW And Literal with W

Syntax: [

label

] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Encoding: 11 1001 kkkk kkkk

Description: The contents of W register are

AND’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Encoding: 00 0101 dfff ffff

Description: AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

back in register 'f'.

Words: 1

Cycles: 1

Example ANDWF FSR, 1

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0x17

FSR = 0x02

 1998 Microchip Technology Inc. Preliminary DS40181B-page 65

PIC12CE67X

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared.

Words: 1

Cycles: 1

Example BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 01 01bb bfff ffff

Description: Bit 'b' in register 'f' is set.

Words: 1

Cycles: 1

Example BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 01 10bb bfff ffff

Description: If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address TRUE

if FLAG<1>=1,

PC = address FALSE

PIC12CE67X

DS40181B-page 66 Preliminary  1998 Microchip Technology Inc.

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 01 11bb bfff ffff

Description: If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSS

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address FALSE

if FLAG<1> = 1,

PC = address TRUE

CALL Call Subroutine

Syntax: [

label

] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Encoding: 10 0kkk kkkk kkkk

Description: Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two cycle instruction.

Words: 1

Cycles: 2

Example HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS = Address HERE+1

CLRF Clear f

Syntax: [

label

] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Encoding: 00 0001 1fff ffff

Description: The contents of register 'f' are cleared

and the Z bit is set.

Words: 1

Cycles: 1

Example CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00

Z = 1

CLRW Clear W

Syntax: [

label

] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Encoding: 00 0001 0000 0011

Description: W register is cleared. Zero bit (Z) is

set.

Words: 1

Cycles: 1

Example CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z = 1

 1998 Microchip Technology Inc. Preliminary DS40181B-page 67

PIC12CE67X

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0100

Description: CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

Words: 1

Cycles: 1

Example CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescaler= 0

TO = 1

PD = 1

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1001 dfff ffff

Description: The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

W. If 'd' is 1 the result is stored back in

Words: 1

Cycles: 1

Example COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W = 0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest)

Status Affected: Z

Encoding: 00 0011 dfff ffff

Description: Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1

Cycles: 1

Example DECF CNT, 1

Before Instruction

CNT = 0x01

Z = 0

After Instruction

CNT = 0x00

Z = 1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest); skip if result = 0

Status Affected: None

Encoding: 00 1011 dfff ffff

Description: The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded. A

NOP is executed instead making it a tw o

cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1

if CNT = 0,

PC = address CONTINUE

if CNT ≠0,

PC = address HERE+1

PIC12CE67X

DS40181B-page 68 Preliminary  1998 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: [

label

] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Encoding: 10 1kkk kkkk kkkk

Description: GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two cycle instruction.

Words: 1

Cycles: 2

Example GOTO THERE

After Instruction

PC = Address THERE

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 00 1010 dfff ffff

Description: The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example INCF CNT, 1

Before Instruction

CNT = 0xFF

Z = 0

After Instruction

CNT = 0x00

Z = 1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 00 1111 dfff ffff

Description: The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is ex ecuted instead making it a

two cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1

if CNT= 0,

PC = address CONTINUE

if CNT≠0,

PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [

label

] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Encoding: 11 1000 kkkk kkkk

Description: The contents of the W register is

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF

Z = 1

 1998 Microchip Technology Inc. Preliminary DS40181B-page 69

PIC12CE67X

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest)

Status Affected: Z

Encoding: 00 0100 dfff ffff

Description: Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example IORWF RESULT, 0

Before Instruction

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z = 1

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 11 00xx kkkk kkkk

Description: The eight bit literal 'k' is loaded into W

as 0’s.

Words: 1

Cycles: 1

Example MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1000 dfff ffff

Description: The contents of register f is moved to

a destination dependant upon the sta-

tus of d. If d = 0, destination is W reg-

ister. If d = 1, the destination is ﬁle

ﬁle register since status ﬂag Z is

affected.

Words: 1

Cycles: 1

Example MOVF FSR, 0

After Instruction

W = value in FSR register

Z = 1

MOVWF Move W to f

Syntax: [

label

] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affected: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to register

'f'.

Words: 1

Cycles: 1

Example MOVWF OPTION

Before Instruction

OPTION = 0xFF

W = 0x4F

After Instruction

OPTION = 0x4F

W = 0x4F

PIC12CE67X

DS40181B-page 70 Preliminary  1998 Microchip Technology Inc.

NOP No Operation

Syntax: [

label

] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

Words: 1

Cycles: 1

Example NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 00 0000 0110 0010

Description: The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code com-

patibility with PIC16C5X products.

Since OPTION is a readable/writable

it.

Words: 1

Cycles: 1

Example To maintain upward compatibility

with future PIC12C67X products,

do not use this instruction.

RETFIE Return from Interrupt

Syntax: [

label

] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words: 1

Cycles: 2

Example RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with Literal in W

Syntax: [

label

] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1

Cycles: 2

Example

TABLE

CALL TABLE ;W contains table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

 1998 Microchip Technology Inc. Preliminary DS40181B-page 71

PIC12CE67X

RETURN Return from Subroutine

Syntax: [

label

] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Encoding: 00 0000 0000 1000

Description: Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two cycle instruction.

Words: 1

Cycles: 2

Example RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1101 dfff ffff

Description: The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1

Cycles: 1

Example RLF REG1,0

Before Instruction

REG1 = 1110 0110

C= 0

After Instruction

REG1 = 1110 0110

W= 1100 1100

C= 1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1100 dfff ffff

Description: The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example RRF REG1,0

Before Instruction

REG1 = 1110 0110

C= 0

After Instruction

REG1 = 1110 0110

W= 0111 0011

C= 0

SLEEP

Syntax: [

label

] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0011

Description: The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

Words: 1

Cycles: 1

Example: SLEEP

PIC12CE67X

DS40181B-page 72 Preliminary  1998 Microchip Technology Inc.

SUBLW Subtract W from Literal

Syntax: [

label

] SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status

Affected: C, DC, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s com-

plement method) from the eight bit literal

'k'. The result is placed in the W register.

Words: 1

Cycles: 1

Example 1: SUBLW 0x02

Before Instruction

W = 1

C = ?

After Instruction

W = 1

C = 1; result is positive

Example 2: Before Instruction

W = 2

C = ?

After Instruction

W = 0

C = 1; result is zero

Example 3: Before Instruction

W = 3

C = ?

After Instruction

W = 0xFF

C = 0; result is nega-

tive

SUBWF Subtract W from f

Syntax: [

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected: C, DC, Z

Encoding: 00 0010 dfff ffff

Description: Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1

Cycles: 1

Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3

W = 2

C = ?

After Instruction

REG1 = 1

W = 2

C = 1; result is positive

Example 2: Before Instruction

REG1 = 2

W = 2

C = ?

After Instruction

REG1 = 0

W = 2

C = 1; result is zero

Example 3: Before Instruction

REG1 = 1

W = 2

C = ?

After Instruction

REG1 = 0xFF

W = 2

C = 0; result is negative

 1998 Microchip Technology Inc. Preliminary DS40181B-page 73

PIC12CE67X

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0 the

result is placed in W register. If 'd' is 1

the result is placed in register 'f'.

Words: 1

Cycles: 1

Example SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0x5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f;

Status Affected: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable , the user can directly

address them.

Words: 1

Cycles: 1

Example To maintain upward compatibility

with future PIC12C67X products,

do not use this instruction.

XORLW Exclusive OR Literal with W

Syntax: [

label

] XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the W regis-

ter.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 00 0110 dfff ffff

Description: Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1

Cycles: 1

Example XORWF REG 1

Before Instruction

REG = 0xAF

W = 0xB5

After Instruction

REG = 0x1A

W = 0xB5

PIC12CE67X

DS40181B-page 74 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 75

PIC12CE67X

11.0 DEVELOPMENT SUPPORT

11.1 Development Tools

The PICmicrο microcontrollers are supported with a

full range of hardware and softw are de velopment tools:

• MPLAB™-ICE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

• PRO MATE II Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

• SIMICE

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

•Fuzzy Logic De velopment System

(

fuzzy

TECH−MP)

• KEELOQ® Evaluation Kits and Programmer

11.2 MPLAB-ICE: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers (MCUs). MPLAB-ICE is sup-

plied with the MPLAB Integrated De velopment En viron-

ment (IDE), which allows editing, “make” and

download, and source debugging from a single envi-

ronment.

Interchangeable processor modules allow the system

to be easily reconﬁgured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support all new Microchip micro-

controllers.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive

development tools . The PC compatible 386 (and higher)

machine platform and Microsoft Windows 3.x or

Windows 95 environment were chosen to best make

these features available to you, the end user.

MPLAB-ICE is available in two versions.

MPLAB-ICE 1000 is a basic, lo w-cost emulator system

with simple trace capabilities. It shares processor mod-

ules with the MPLAB-ICE 2000. This is a full-featured

emulator system with enhanced trace , trigger, and data

monitoring features. Both systems will operate across

the entire operating speed reange of the PICmicro

MCU.

11.3 ICEPIC: Low-Cost PICmicro™

In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible

machines ranging from 386 through Pentium based

machines under Windows 3.x, Windows 95, or Win-

dows NT environment. ICEPIC features real time, non-

intrusive emulation.

11.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

gram PIC12CXXX, PIC14C000, PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

conﬁguration and code-protect bits in this mode.

11.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efﬁcient. PICSTART Plus is

not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 ma y be sup-

ported with an adapter socket. PICSTART Plus is CE

compliant.

PIC12CE67X

DS40181B-page 76 Preliminary  1998 Microchip Technology Inc.

11.6 SIMICE Entry-Level Hardware

Simulator

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIM-

ICE and MPLAB-SIM run under Microchip Technol-

ogy’s MPLAB Integrated Development Environment

(IDE) software . Speciﬁcally, SIMICE provides hardware

simulation for Microchip’s PIC12C5XX, PIC12CE5XX,

and PIC16C5X families of PICmicro™ 8-bit microcon-

trollers. SIMICE works in conjunction with MPLAB-SIM

to provide non-real-time I/O port emulation. SIMICE

enables a developer to run simulator code for driving

the target system. In addition, the target system can

provide input to the simulator code. This capability

allows for simple and interactive debugging without

having to manually generate MPLAB-SIM stimulus

ﬁles. SIMICE is a valuable debugging tool for entry-

level system development.

11.7 PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test ﬁrm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and do wnload the

ﬁrmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

11.8 PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus, and easily test ﬁrmware .

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test ﬁrmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage of the I2C b us and separate headers f or connec-

tion to an LCD module and a keypad.

11.9 PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test ﬁrmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test ﬁrm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller sock et(s). Some of the f eatures include

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a ke ypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and da y of the w eek. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiple xed LCD signals on a PC . A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 77

PIC12CE67X

11.10 MPLAB Integrated Development

Environment Software

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

11.11 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and sev eral source and listing f ormats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

MPASM allows full symbolic debugging from MPLAB-

ICE, Microchip’s Universal Emulator System.

MPASM has the follo wing features to assist in de velop-

ing software for speciﬁc use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and

special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful in

making the development of y our assemble source code

shorter and more maintainable.

11.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be perf ormed in; single step, e xecute until break, or

in a trace mode.

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPASM. The Software Simulator

offers the low cost ﬂe xibility to de v elop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

11.13 MPLAB-C17 Compiler

The MPLAB-C17 Code Development System is a

complete ANSI ‘C’ compiler and integrated develop-

ment environment f or Microchip’ s PIC17CXXX family of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

11.14 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version,

fuzzy

TECH-MP, Edition for imple-

menting more complex systems.

Both versions include Microchip’s

fuzzy

LAB demon-

stration board f or hands-on experience with fuzzy logic

systems implementation.

11.15 SEEVAL Evaluation and

Programming System

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessar y to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

signiﬁcantly reduce time-to-market and result in an

optimized system.

PIC12CE67X

DS40181B-page 78 Preliminary  1998 Microchip Technology Inc.

11.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS e v al-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 79

PIC12CE67X

TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 24CXX

25CXX

93CXX

HCS200

HCS300

HCS301

Emulator Products

MPLAB™-ICE üüüüüüüüüü

ICEPIC Low-Cost

In-Circuit Emulator üüüüüü

Software Tools

MPLAB

Integrated

Development

Environment

üüüüüüüüüü

MPLAB C17*

Compiler ü ü

fuzzy

TECH-MP

Explorer/Edition

Fuzzy Logic

Dev. Tool

üüüüüüüüü

Total Endurance

Software Model ü

Programmers

PICSTARTPlus

Low-Cost

Universal Dev. Kit üüüüüüüüüü

PRO MATE II

Universal

Programmer üüüüüüüüüüüü

KEELOQ

Programmer ü

Demo Boards

SEEVAL

Designers Kit ü

SIMICE ü ü

PICDEM-14A ü

PICDEM-1 ü ü ü ü

PICDEM-2 ü ü

PICDEM-3 ü

KEELOQ®

Evaluation Kit ü

KEELOQ

Transponder Kit ü

PIC12CE67X

DS40181B-page 80 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 81

PIC12CE67X

12.0 ELECTRICAL CHARACTERISTICS FOR PIC12CE67X

Absolute Maximum Ratings †

Ambient temperature under bias............................................................................................................. .–40° to +125°C

Storage temperature............................................................................................................................. –65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................–0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V

Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power dissipation (Note 1)...........................................................................................................................700 mW

Maximum current out of VSS pin...........................................................................................................................150 mA

Maximum current into VDD pin..............................................................................................................................125 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by GPIO pins combined...................................................................................................100 mA

Maximum current sourced by GPIO pins combined..............................................................................................100 mA

Note 1: Power dissipation is calculated as f ollo ws: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional oper ation of the de vice at those or an y other conditions abo v e those

indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC12CE67X

DS40181B-page 82 Preliminary  1998 Microchip Technology Inc.

TABLE 12-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC PIC12CE673-04

PIC12CE674-04 PIC12CE673-10

PIC12CE674-10 PIC12LCE673-04

PIC12LCE674-04 PIC12CE673/JW

PIC12CE674/JW

INTRC

VDD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 2.7 mA typ. at 5.5V

IPD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

VDD: 2.5V to 5.5V

IDD: 2.0 mA typ. at 2.5V

IPD: 0.9 µA typ. at 2.5V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

EXTRC

VDD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 2.7 mA typ. at 5.5V

IPD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

VDD: 2.5V to 5.5V

IDD: 2.0 mA typ. at 2.5V

IPD: 0.9 µA typ. at 2.5V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 2.7 mA typ. at 5.5V

IPD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

VDD: 2.5V to 5.5V

IDD: 2.0 mA typ. at 2.5V

IPD: 0.9 µA typ. at 2.5V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V

N/A

VDD: 3.0V to 5.5V

IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V

IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ . at 4.5V IPD: 1.5 µA typ. at 4.5V

Freq: 4 MHz max. Freq: 10 MHz max. Freq: 10 MHz max.

VDD: 3.0V to 5.5V

IDD: 52.5 µA typ. at 32 kHz, 4.0V

IPD: 0.9 µA typ. at 4.0V

Freq: 200 kHz max.

N/A

VDD: 2.5V to 5.5V

IDD: 48 µA max. at 32 kHz, 2.5V

IPD: 5.0 µA max. at 2.5V

Freq: 200 kHz max.

VDD: 3.0V to 5.5V

IDD: 48 µA max. at 32 kHz, 2.5V

IPD: 5.0 µA max. at 2.5V

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not f or MIN/MAX speciﬁcations . It is recommended that the user

select the device type that ensures the speciﬁcations required.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 83

PIC12CE67X

12.1 DC Characteristics: PIC12CE673-04 (Commercial, Industrial, Extended(5))

PIC12CE673-10 (Commercial, Industrial, Extended(5))

PIC12CE674-04 (Commercial, Industrial, Extended(5))

PIC12CE674-10 (Commercial, Industrial, Extended(5))

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For EXTRC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: Extended operating range is Advance Information for this device.

6: INTRC calibration value is for 4 MHz nominal at 5V, 35°C.

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

–40°C ≤ TA ≤ +125˚C (extended)

Parm

No. Characteristic Sym Min Typ† Max Units Conditions

D001

D001A

Supply Voltage VDD 3.0

4.5

-5.5

5.5

XT, INTRC, EXTRC and LP osc conﬁgura-

tion

HS osc conﬁguration

D002 RAM Data Retention

Voltage (Note 1) VDR - 1.5 - V Device in SLEEP mode

D003 VDD start voltage to

ensure internal Power-on

Reset signal

VPO

RVSS - VSS V See section on Power-on Reset for details

D004 VDD rise rate to ensure inter-

nal Power-on Reset signal SVD

D0.05 - - V/ms See section on Power-on Reset for details

D010

D010A

D013

Supply Current (Note 2)

No read/write to EEPROM

peripheral

IDD -

2.7

TBD

3.3

XT, EXTRC osc conﬁguration

(PIC12CE67X-04)

FOSC = 4 MHz, VDD = 5.5V (Note 4)

INTRC osc conﬁguration

FOSC = 4 MHz, VDD = 5.5V (Note 6)

HS osc conﬁguration (PIC12CE67X-10)

FOSC = 10 MHz, VDD = 5.5V

D028 ∆IEE 0.1 0.2 VDD = 5.5V

SCL = 400 kHz

D020

D021

D021A

D021B

Power-down Current (Note 3) IPD -

5.5

1.5

TBD

µA

VDD = 4.0V, WDT enabled, –40°C to +85°C

VDD = 4.0V, WDT disabled, 0°C to +70°C

VDD = 4.0V, WDT disabled, –40°C to

+85°C

VDD = 4.0V, WDT disabled, –40°C to

+125°C

PIC12CE67X

DS40181B-page 84 Preliminary  1998 Microchip Technology Inc.

12.2 DC Characteristics: PIC12LCE673-04 (Commercial, Industrial)

PIC12LCE674-04 (Commercial, Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

Param

No. Characteristic Sym Min Typ† Max Units Conditions

D001 Supply Voltage VDD 2.5 - 5.5 V XT, INTRC, EXTRC and LP osc conﬁguration

(DC - 4 MHz)

D002* RAM Data Retention

Voltage (Note 1) VDR - TBD - V Device in SLEEP mode

D003 VDD start voltage to

ensure internal

Power-on Reset

signal

VPOR - VSS - V See section on Power-on Reset for details

D004* VDD rise rate to

ensure internal

Power-on Reset

signal

SVDD TBD - - V/ms See section on Power-on Reset for details

D010

D010B

D010A

Supply Current

(Note 2) IDD -

TBD

µA

XT, EXTRC osc conﬁguration

FOSC = 4 MHz, VDD = 3.0V (Note 4)

INTRC osc conﬁguration

FOSC = 4 MHz, VDD = 3.0V (Note 5)

LP osc conﬁguration

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D020

D021

D021A

Power-down Current

(Note 3) IPD -

TBD

µA

VDD = 3.0V, WDT enabled, –40°C to +85°C

VDD = 3.0V, WDT disabled, 0°C to +70°C

VDD = 3.0V, WDT disabled, –40°C to +85°C

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For EXTRC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: INTRC calibration value is for 4 MHz nominal at 5V, 25°C.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 85

PIC12CE67X

12.3 DC Characteristics: PIC12CE673-04 (Commercial, Industrial, Extended(4))

PIC12CE673-10 (Commercial, Industrial, Extended(4))

PIC12CE674-04 (Commercial, Industrial, Extended(4))

PIC12CE674-10 (Commercial, Industrial, Extended(4))

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

–40°C ≤ TA ≤ +125˚C (extended)

Operating voltage VDD range as described in DC spec Section 12.1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ

†Max Units Conditions

Input Low Voltage

I/O ports VIL

D030 with TTL buffer VSS - 0.5V V

D031 with Schmitt Trigger buffer VSS - 0.2VDD V

D032 MCLR, GP2/T0CKI/AN2/INT

(in EXTRC mode) VSS - 0.2VDD V

D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1

Input High Voltage

I/O ports VIH -

D040 with TTL buffer 2.0 - VDD V 4.5 ≤ VDD ≤ 5.5V

D040A 0.8VDD - VDD V For VDD > 5.5V or VDD < 4.5V

D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range

D042 MCLR, GP2/T0CKI/AN2/INT 0.8VDD - VDD V

D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1

D043 OSC1 (in EXTRC mode) 0.9VDD - VDD V

D070 GPIO weak pull-up current IPUR 50 250 400 µA VDD = 5V, VPIN = VSS

Input Leakage Current (Notes 2, 3)

D060 I/O ports IIL - - +1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

D061 MCLR, GP2/T0CKI - - +5(5) µA Vss ≤ VPIN ≤ VDD

D063 OSC1 - - +5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc conﬁguration

Output Low Voltage

D080 I/O ports/CLKOUT VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

–40°C to +85°C

D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V,

–40°C to +125°C

D083 OSC2 - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,

–40°C to +85°C

D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V,

–40°C to +125°C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C67X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied v oltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

4: Extended operating range is Advance Information for this device.

5: When conﬁgured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum.

This pull-up is weaker than the standard I/O pull-up.

PIC12CE67X

DS40181B-page 86 Preliminary  1998 Microchip Technology Inc.

Output High Voltage

D090 I/O ports/CLKOUT (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

–40°C to +85°C

D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

–40°C to +125°C

D092 OSC2 VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

–40°C to +85°C

D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

–40°C to +125°C

Capacitive Loading Specs on

Output Pins

D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

D101 All I/O pins and OSC2 CIO - - 50 pF

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

–40°C ≤ TA ≤ +125˚C (extended)

Operating voltage VDD range as described in DC spec Section 12.1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ

†Max Units Conditions

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C67X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied v oltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

4: Extended operating range is Advance Information for this device.

5: When conﬁgured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum.

This pull-up is weaker than the standard I/O pull-up.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 87

PIC12CE67X

12.4 DC Characteristics: PIC12LCE671-04 (Commercial, Industrial)

PIC12LCE672-04 (Commercial, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

Operating voltage VDD range as described in DC spec Section 12.1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ

†Max Units Conditions

Input Low Voltage

I/O ports VIL

D030 with TTL buffer VSS - TBD V

D031 with Schmitt Trigger buffer VSS - TBD V

D032 MCLR, GP2/T0CKI/AN2/INT

(in EXTRC mode) VSS - TBD V

D033 OSC1 (in XT, HS and LP) VSS - TBD V Note1

Input High Voltage

I/O ports VIH -

D040 with TTL buffer TBD - VDD V 4.5 ≤ VDD ≤ 5.5V

D040A TBD - VDD V For VDD > 5.5V or VDD < 4.5V

D041 with Schmitt Trigger buffer TBD - VDD V For entire VDD range

D042 MCLR, GP2/T0CKI/AN2/INT TBD - VDD V

D042A OSC1 (XT, HS and LP) TBD - VDD V Note1

D043 OSC1 (in EXTRC mode) TBD - VDD V

D070 GPIO weak pull-up current IPUR TBD TBD TBD µA VDD = 5V, VPIN = VSS

Input Leakage Current (Notes 2, 3)

D060 I/O ports IIL - TBD TBD µA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

D061 MCLR, GP3 - TBD TBD µA Vss ≤ VPIN ≤ VDD

D063 OSC1 - TBD TBD µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc conﬁguration

Output Low Voltage

D080 I/O ports/CLKOUT VOL - TBD 0.6 V IOL = TBD, VDD = 4.5V,

–40°C to +85°C

D080A - TBD 0.6 V IOL = TBD, VDD = 4.5V,

–40°C to +125°C

D083 OSC2 - TBD 0.6 V IOL = TBD, VDD = 4.5V,

–40°C to +85°C

D083A - TBD 0.6 V IOL = TBD, VDD = 4.5V,

–40°C to +125°C

Output High Voltage

D090 I/O ports/CLKOUT (Note 3) VOH VDD - 0.7 - - V IOH = TBD, VDD = 4.5V,

–40°C to +85°C

D090A VDD - 0.7 - - V IOH = TBD, VDD = 4.5V,

–40°C to +125°C

D092 OSC2 VDD - 0.7 - - V IOH = TBD, VDD = 4.5V,

–40°C to +85°C

D092A VDD - 0.7 - - V IOH = TBD, VDD = 4.5V,

–40°C to +125°C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C67X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied v oltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

4: Extended operating range is Advance Information for this device.

PIC12CE67X

DS40181B-page 88 Preliminary  1998 Microchip Technology Inc.

Capacitive Loading Specs on

Output Pins

D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

D101 All I/O pins and OSC2 CIO - - 50 pF

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

Operating voltage VDD range as described in DC spec Section 12.1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ

†Max Units Conditions

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C67X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied v oltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

4: Extended operating range is Advance Information for this device.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 89

PIC12CE67X

12.5 Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

FIGURE 12-1: LOAD CONDITIONS

1. TppS2ppS 3. TCC:ST (I2C speciﬁcations only)

2. TppS 4. Ts (I2C speciﬁcations only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase letters and their meanings:

SF Fall P Period

H High R Rise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

I2C only

AA output access High High

BUF Bus free Low Low

TCC:ST (I2C speciﬁcations only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition

STA START condition

VDD/2

Pin Pin

VSS VSS

RL= 464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1 Load condition 2

PIC12CE67X

DS40181B-page 90 Preliminary  1998 Microchip Technology Inc.

12.6 Timing Diagrams and Speciﬁcations

FIGURE 12-2: EXTERNAL CLOCK TIMING

TABLE 12-2: CLOCK TIMING REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

Fosc External CLKIN Frequency

(Note 1) DC — 4 MHz XT and EXTRC osc mode

DC — 4 MHz HS osc mode (PIC12CE67X-04)

DC — 10 MHz HS osc mode (PIC12CE67X-10)

DC — 200 kHz LP osc mode

Oscillator Frequency

(Note 1) DC — 4 MHz EXTRC osc mode

.455 — 4 MHz XT osc mode

4 — 4 MHz HS osc mode (PIC12CE67X-04)

4 — 10 MHz HS osc mode (PIC12CE67X-10)

5 — 200 kHz LP osc mode

1 Tosc External CLKIN Period

(Note 1) 250 — — ns XT and EXTRC osc mode

250 — — ns HS osc mode (PIC12CE67X-04)

100 — — ns HS osc mode (PIC12CE67X-10)

5 — — µs LP osc mode

Oscillator Period

(Note 1) 250 — — ns EXTRC osc mode

250 — 10,000 ns XT osc mode

250 — 250 ns HS osc mode (PIC12CE67X-04)

100 — 250 ns HS osc mode (PIC12CE67X-10)

5 — — µs LP osc mode

2 TCY Instruction Cycle Time (Note 1) 400 — DC ns TCY = 4/FOSC

3 TosL,

TosH External Clock in (OSC1) High

or Low Time 50 — — ns XT oscillator

2.5 — — µs LP oscillator

10 — — ns HS oscillator

4 TosR,

TosF External Clock in (OSC1) Rise

or Fall Time — — 25 ns XT oscillator

— — 50 ns LP oscillator

— — 15 ns HS oscillator

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are based on

characterization data for that particular oscillator type under standard operating conditions with the device e x ecuting code.

Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected

(has no loading) for the PIC12CE67X.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

23344

 1998 Microchip Technology Inc. Preliminary DS40181B-page 91

PIC12CE67X

TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1

Parameter

No. Sym Characteristic Min* Typ(1) Max* Units Conditions

Internal Calibrated RC Frequency TBD 4.00 TBD MHz VDD = 5.0V

Internal Calibrated RC Frequency TBD 4.00 TBD MHz VDD = 2.5V

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

PIC12CE67X

DS40181B-page 92 Preliminary  1998 Microchip Technology Inc.

FIGURE 12-3: CLKOUT AND I/O TIMING

TABLE 12-4: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 15 30 ns Note 1

11* TosH2ckH OSC1↑ to CLKOUT↑ — 15 30 ns Note 1

12* TckR CLKOUT rise time — 5 15 ns Note 1

13* TckF CLKOUT fall time — 5 15 ns Note 1

14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1

15* TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns Note 1

16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1

17* TosH2ioV OSC1↑ (Q1 cycle) to

Port out valid — — 80 - 100 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to

Port input invalid (I/O in hold time) TBD — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) TBD — — ns

20* TioR Port output rise time PIC12CE67X — 10 25 ns

21* TioF Port output fall time PIC12CE67X — 10 25 ns

22††* Tinp INT pin high or low time 20 — — ns

23††* Trbp GPIO change INT high or low time 20 — — ns

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.

Note: Refer to Figure 12-1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

12 16

old value new value

 1998 Microchip Technology Inc. Preliminary DS40181B-page 93

PIC12CE67X

FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER TIMING

TABLE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, –40˚C to +125˚C

31* Twdt Watchdog Timer Time-out Period

(No Prescaler) 7 18 33 ms VDD = 5V, –40˚C to +125˚C

32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period

33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, –40˚C to +125˚C

34 TIOZ I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset — — 2.1 µs

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

PIC12CE67X

DS40181B-page 94 Preliminary  1998 Microchip Technology Inc.

FIGURE 12-5: TIMER0 CLOCK TIMINGS

TABLE 12-6: TIMER0 CLOCK REQUIREMENTS

TABLE 12-7: GPIO PULL-UP RESISTOR RANGES

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period Greater of:

20µs or TCY + 40*

— — ns N = prescale value

(1, 2, 4,..., 256)

48 Tcke2tmrI Delay from external clock edge to timer increment 2Tosc — 7Tosc —

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD (Volts) Temperature (°C) Min Typ Max Units

GP0/GP1

2.5 –40 38K 42K 63K Ω

25 42K 48K 63K Ω

85 42K 49K 63K Ω

125 50K 55K 63K Ω

5.5 –40 15K 17K 20K Ω

25 18K 20K 23K Ω

85 19K 22K 25K Ω

125 22K 24K 28K Ω

GP3

2.5 –40 285K 346K 417K Ω

25 343K 414K 532K Ω

85 368K 457K 532K Ω

125 431K 504K 593K Ω

5.5 –40 247K 292K 360K Ω

25 288K 341K 437K Ω

85 306K 371K 448K Ω

125 351K 407K 500K Ω

* These parameters are characterized but not tested.

Note: Refer to Figure 12-1 for load conditions.

GP2/T0CKI

TMR0

 1998 Microchip Technology Inc. Preliminary DS40181B-page 95

PIC12CE67X

TABLE 12-8: A/D CONVERTER CHARACTERISTICS:

PIC12CE673-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))

PIC12CE673-10 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))

PIC12CE674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))

PIC12CE674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

NRResolution — — 8-bits — VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

(Notes 4,5)

NINT Integral error — — less than

±1 LSb — VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

(Notes 4,5)

NDIF Differential error — — less than

±1 LSb — VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

(Notes 4,5)

NFS Full scale error — — less than

±1 LSb — VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

(Notes 4,5)

NOFF Offset error — — less than

±1 LSb — VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

(Notes 4,5)

— Monotonicity — Typ — — VSS ≤ AIN ≤ VREF

VREF Reference voltage 3.0V — VDD + 0.3 V

VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V

ZAIN Recommended

impedance of analog

voltage source

— — 10.0 kΩ

IAD A/D conversion cur-

rent (VDD)— 180 — µA Average current consumption when

A/D is on. (Note 1)

IREF VREF input current

(Note 2) — — 1

10 mA

µADuring sampling

All other times

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes

any such leakage from the A/D module.

2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.

3: Extended operating range is Advance Information for this device.

4: These speciﬁcations apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF

5: When using e xternal VREF, VDD must be greater than 3V f or +1 LSB accuracy. If VDD is less than 3V, you must

use internal VREF for +1 LSB.

PIC12CE67X

DS40181B-page 96 Preliminary  1998 Microchip Technology Inc.

TABLE 12-9: A/D CONVERTER CHARACTERISTICS:

PIC12LCE673-04 (COMMERCIAL, INDUSTRIAL)

PIC12LCE674-04 (COMMERCIAL, INDUSTRIAL)

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

NRResolution — — 8-bits — VREF = VDD = 3.0V (Notes 1,4)

NINT Integral error — — less than

±1 LSb — VREF = VDD = 3.0V (Notes 1,4)

NDIF Differential error — — less than

±1 LSb — VREF = VDD = 3.0V (Notes 1,4)

NFS Full scale error — — less than

±1 LSb — VREF = VDD = 3.0V (Notes 1,4)

NOFF Offset error — — less than

±1 LSb — VREF = VDD = 3.0V (Notes 1,4)

— Monotonicity — Typ — — VSS ≤ AIN ≤ VREF

VREF Reference voltage TBD — VDD + 0.3 V

VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V

ZAIN Recommended

impedance of ana-

log voltage source

— — 10.0 kΩ

IAD A/D conversion cur-

rent (VDD)— TBD — µA Average current consumption when

A/D is on. (Note 2)

IREF VREF input current

(Note 3) — — TBD

TBD mA

µADuring sampling

All other times

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: These speciﬁcations apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF

2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes

any such leakage from the A/D module.

3: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.

4: When using external VREF, VDD must be greater than 3V for +1 LSB accuracy. If VDD is less than 3V, you

must use internal VREF for +1 LSB.

 1998 Microchip Technology Inc. Preliminary DS40181B-page 97

PIC12CE67X

FIGURE 12-6: A/D CONVERSION TIMING

TABLE 12-10: A/D CONVERSION REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period 1.6

2.0 —

—µs

µsVREF ≥ 3.0V

VREF full range

130 TAD A/D Internal RC

Oscillator source 3.0 6.0 9.0 µs

ADCS1:ADCS0 = 11

(RC oscillator source)

PIC12LCE67X, VDD = 3.0V

2.0 4.0 6.0 µs PIC12CE67X

131 TCNV Conversion time

(not including S/H

time). Note 1

— 9.5TAD — —

132 TACQ Acquisition time Note 2 20 — µs

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: ADRES register may be read on the following TCY cycle.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2) (1)

7 6 5 4 3 2 1 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 Tcy

PIC12CE67X

DS40181B-page 98 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 99

PIC12CE67X

13.0 DC AND AC CHARACTERISTICS - PIC12CE67X

The graphs and tab les pro vided in this section are f or design guidance and are not tested. In some graphs or tables the

data presented are outside speciﬁed operating range (e.g., outside speciﬁed VDD range). This is for information only

and devices will operate properly only within the speciﬁed range.

The data presented in this section is a statistical summary of data collected on units from diff erent lots ov er a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 13-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V)

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

FIGURE 13-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 3.0V)

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

TO BE DETERMINED

PIC12CE67X

DS40181B-page 100 Preliminary  1998 Microchip Technology Inc.

TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

FIGURE 13-3: WDT TIMER TIME-OUT PERIOD vs. VDD

Oscillator Frequency VDD = 2.5V VDD = 5.5V

External RC 4 MHz TBD µA* 620 µA*

Internal RC 4 MHz TBD µA 1.1 mA

XT 4 MHz TBD µA 775 µA

LP 32 KHz TBD µA 37 µA

*Does not include current through external R&C.

5234567

VDD (Volts)

WDT period (µs)

Max +125°C

Max +85°C

Typ +25°C

MIn –40°C

 1998 Microchip Technology Inc. Preliminary DS40181B-page 101

PIC12CE67X

FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V

FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V

500m 1.0 1.5

VOH (Volts)

IOH (mA)

2.0 2.5

-1

-2

-3

-4

-5

-6

-7

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

3.01.5

VOH (Volts)

IOH (mA)

2.0 2.5

-5

-10

-15

-20 .50

-18

-13

-8

-3

Min +125°C

Min +85°C

Typ +25°C

Max –40°C

FIGURE 13-6: IOL vs. VOL, VDD = 2.5 V

FIGURE 13-7: IOL vs. VOL, VDD = 3.5 V

0250.0m 500.0m 1.0

VOL (Volts)

IOL (mA)

Min +85°C

Max –40°C

Typ +25°C

Min +125°C

0.50 .75 1.0

VOL (Volts)

IOL (mA)

Max –40°C

Typ +25°C

Min +85°C

Min +125°C

PIC12CE67X

DS40181B-page 102 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-8: IOH vs. VOH, VDD = 5.5 V

3.5 4.0 4.5

VOH (Volts)

IOH (mA)

5.0 5.5

-5

-10

-15

-20

-25

-30

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V

0.50 .75 1.0

VOL (Volts)

IOL (mA)

.25

Min +85°C

Max –40°C

Typ +25°C

Min +125°C

 1998 Microchip Technology Inc. Preliminary DS40181B-page 103

PIC12CE67X

14.0 PACKAGING INFORMATION

14.1 Package Marking Information

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information*

AA Year code (last 2 digits of calendar year)

BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

O = Outside Vendor

C = 5” Line

S = 6” Line

H = 8” Line

D Mask revision number

E Assembly code of the plant or country of origin in which

part was assembled

Note:In the e v ent the full Microchip part number cannot be marked on one line ,

it will be carried over to the next line thus limiting the number of available

characters for customer speciﬁc information.

*Standard OTP marking consists of Microchip par t number, year code, week

code, facility code, mask rev#, and assembly code. For OTP marking

beyond this, certain price adders apply. Please check with your Microchip

Sales Ofﬁce. For QTP devices, any special marking adders are included in

QTP price.

MMMMMMMM

XXXXXCDE

AABB

8-Lead PDIP (300 mil) Example

8-Lead Windowed Ceramic Side Brazed (300 mil) Example

12CE674

04/PSAZ

9725

CE674

MMMMMM

PIC12CE67X

DS40181B-page 104 Preliminary  1998 Microchip Technology Inc.

Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil

* Controlling Parameter.

†Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

0.310

0.267

0.245

0.355

0.120

0.005

0.060

0.140

0.006

0.000

0.055

0.014

Mold Draft Angle Bottom

Mold Draft Angle Top

Overall Row Spacing

Radius to Radius Width

Molded Package Width

Tip to Seating Plane

Base to Seating Plane

Top of Lead to Seating Plane

Top to Seating Plane

Upper Lead Width

Lower Lead Width

PCB Row Spacing

Package Length

Lead Thickness

Shoulder Radius

Number of Pins

Pitch

E‡

D‡

B1†

Dimension Limits

Units MIN

0.3800.342

510

10 15

0.130

0.280

0.250

0.370

0.020

0.080

0.150

0.018

0.012

0.005

0.060

0.100

0.300

0.292

0.260

0.385

0.140

0.035

0.100

0.160

0.015

0.010

0.065

0.022

9.658.677.87

510

10 15

7.10

6.35

9.40

3.30

0.51

2.03

3.81

0.29

0.13

1.52

0.46

2.54

7.62

3.05

6.78

6.22

9.02

0.13

1.52

3.56

0.36

0.20

0.00

1.40

3.56

7.42

6.60

9.78

0.89

2.54

4.06

0.56

0.38

0.25

1.65

MINNOM

INCHES* MAX MILLIMETERS

NOM MAX

 1998 Microchip Technology Inc. Preliminary DS40181B-page 105

PIC12CE67X

Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil

0.260

0.440

0.161

0.310

0.280

0.510

0.130

0.025

0.103

0.145

0.008

0.050

0.016

0.098

MIN

Window Diameter

Overall Row Spacing

Package Length

Tip to Seating Plane

Base to Seating Plane

Top of Body to Seating Plane

Top to Seating Plane

Upper Lead Width

Lower Lead Width

PCB Row Spacing

Dimension Limits

Lid Length

Lid Width

Package Width

Lead Thickness

Number of Pins

Pitch

Units

0.450

0.270

0.520

0.166

0.338

0.290

0.140

0.035

0.123

0.460

0.280

0.171

0.365

0.300

0.530

0.150

0.045

0.143

NOM

0.018

0.165

0.010

0.055

0.100

0.300 MAX

0.185

0.012

0.060

0.020

0.102

6.86

11.43

4.22

8.57

7.37

13.21

3.56

0.89

3.12

11.18

6.60

12.95

4.09

7.87

7.11

3.30

0.64

2.62

11.68

7.11

13.46

4.34

9.27

7.62

3.81

1.14

3.63

4.19

0.25

1.40

0.46

2.54

7.62

NOM

MILLIMETERS

MIN

0.41

3.68

0.20

1.27

2.49

MAX

0.51

4.70

0.30

1.52

2.59

INCHES*

* Controlling Parameter.

PIC12CE67X

DS40181B-page 106 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 107

PIC12CE67X

INDEX

A/D Accuracy/Error............................................................43

ADCON0 Register.......................................................37

ADIF bit.......................................................................39

Analog Input Model Block Diagram.............................40

Analog-to-Digital Converter.........................................37

Configuring Analog Port Pins......................................41

Configuring the Interrupt.............................................39

Configuring the Module...............................................39

Connection Considerations.........................................43

Conversion Clock........................................................41

Conversions................................................................42

Converter Characteristics ...........................................95

Delays.........................................................................40

Effects of a Reset........................................................43

Equations....................................................................40

Flowchart of A/D Operation.........................................44

GO/DONE bit..............................................................39

Internal Sampling Switch (Rss) Impedence................40

Operation During Sleep ..............................................43

Sampling Requirements..............................................40

Sampling Time............................................................40

Source Impedence......................................................40

Time Delays................................................................40

Transfer Function........................................................43

Absolute Maximum Ratings................................................81

ADDLW Instruction .............................................................64

ADDWF Instruction.............................................................64

ADIE bit...............................................................................18

ADIF bit...............................................................................19

ADRES Register.....................................................13, 37, 39

ALU.......................................................................................7

ANDLW Instruction .............................................................64

ANDWF Instruction.............................................................64

Application Notes

AN546.........................................................................37

AN556.........................................................................22

Architecture

Harvard.........................................................................7

Overview.......................................................................7

von Neumann................................................................7

Assembler

MPASM Assembler.....................................................77

BCF Instruction...................................................................65

Bit Manipulation ..................................................................62

Block Diagrams

Analog Input Model.....................................................40

On-Chip Reset Circuit.................................................49

Timer0.........................................................................31

Timer0/WDT Prescaler ...............................................34

Watchdog Timer..........................................................57

BSF Instruction ...................................................................65

BTFSC Instruction...............................................................65

BTFSS Instruction...............................................................66

C bit.....................................................................................15

CAL0 bit..............................................................................21

CAL1 bit..............................................................................21

CAL2 bit..............................................................................21

CAL3 bit..............................................................................21

CALFST bit .........................................................................21

CALL Instruction .................................................................66

CALSLW bit........................................................................ 21

Carry bit.................................................................................7

Clocking Scheme................................................................ 10

CLRF Instruction................................................................. 66

CLRW Instruction ............................................................... 66

CLRWDT Instruction........................................................... 67

Code Examples

Changing Prescaler (Timer0 to WDT)........................ 35

Changing Prescaler (WDT to Timer0)........................ 35

Indirect Addressing..................................................... 23

Code Protection............................................................ 45, 59

COMF Instruction ............................................................... 67

Computed GOTO ............................................................... 22

Configuration Bits ............................................................... 45

DC bit.................................................................................. 15

DC Characteristics

PIC12CE673............................................................... 83

PIC12CE674............................................................... 83

DECF Instruction ................................................................ 67

DECFSZ Instruction............................................................ 67

Development Support..................................................... 3, 75

Development Tools............................................................. 75

Diagrams - See Block Diagrams

Digit Carry bit.........................................................................7

Direct Addressing ............................................................... 23

EEPROM Peripheral Operation.......................................... 27

Electrical Characteristics

PIC12CE67X.............................................................. 81

Errata.....................................................................................2

External Brown-out Protection Circuit................................. 53

External Power-on Reset Circuit ........................................ 53

Family of Devices ..................................................................4

Features ................................................................................1

FSR Register.......................................................... 13, 14, 23

Fuzzy Logic Dev. System (

fuzzy

TECH-MP).................... 77

General Description...............................................................3

GIE bit................................................................................. 54

GOTO Instruction ............................................................... 68

GPIF bit .............................................................................. 56

GPIO............................................................................. 25, 51

GPIO Register .................................................................... 13

GPPU bit............................................................................. 16

I/O Interfacing..................................................................... 25

I/O Ports ............................................................................. 25

I/O Programming Considerations ....................................... 26

ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator............ 75

ID Locations........................................................................ 45

INCF Instruction.................................................................. 68

INCFSZ Instruction............................................................. 68

In-Circuit Serial Programming ...................................... 45, 59

INDF Register............................................................... 14, 23

Indirect Addressing............................................................. 23

Initialization Conditions for All Registers ............................ 51

Instruction Cycle................................................................. 10

Instruction Flow/Pipelining.................................................. 10

Instruction Format............................................................... 61

Instruction Set

ADDLW....................................................................... 64

ADDWF ...................................................................... 64

PIC12CE67X

DS40181B-page 108 Preliminary  1998 Microchip Technology Inc.

ANDLW.......................................................................64

ANDWF.......................................................................64

BCF.............................................................................65

BSF.............................................................................65

BTFSC........................................................................65

BTFSS ........................................................................66

CALL...........................................................................66

CLRF...........................................................................66

CLRW .........................................................................66

CLRWDT.....................................................................67

COMF .........................................................................67

DECF..........................................................................67

DECFSZ......................................................................67

GOTO .........................................................................68

INCF............................................................................68

INCFSZ.......................................................................68

IORLW........................................................................68

IORWF........................................................................69

MOVF..........................................................................69

MOVLW ......................................................................69

MOVWF ......................................................................69

NOP............................................................................70

OPTION......................................................................70

RETFIE.......................................................................70

RETLW .......................................................................70

RETURN.....................................................................71

RLF.............................................................................71

RRF.............................................................................71

SLEEP ........................................................................71

SUBLW.......................................................................72

SUBWF.......................................................................72

SWAPF.......................................................................73

TRIS............................................................................73

XORLW.......................................................................73

XORWF.......................................................................73

Section........................................................................61

INTCON Register................................................................17

INTEDG bit..........................................................................16

Internal Sampling Switch (Rss) Impedence........................40

Interrupts.............................................................................45

A/D..............................................................................54

GP2/INT......................................................................54

GPIO Port ...................................................................54

Section........................................................................54

TMR0..........................................................................56

TMR0 Overflow...........................................................54

IORLW Instruction...............................................................68

IORWF Instruction...............................................................69

IRP bit .................................................................................15

KeeLoq Evaluation and Programming Tools....................78

Loading of PC .....................................................................22

MCLR............................................................................48, 51

Memory

Data Memory ..............................................................11

Program Memory........................................................11

Program Memory Map

PIC12CE67X.......................................................11

PIC12CE67X.......................................................12

MOVF Instruction................................................................69

MOVLW Instruction.............................................................69

MOVWF Instruction.............................................................69

MPLAB Integrated Development Environment Software.... 77

NOP Instruction .................................................................. 70

Opcode............................................................................... 61

OPTION Instruction ............................................................ 70

OPTION Register................................................................ 16

Orthogonal............................................................................ 7

OSC selection..................................................................... 45

OSCCAL Register............................................................... 21

Oscillator

EXTRC ....................................................................... 50

HS............................................................................... 50

INTRC......................................................................... 50

LP ............................................................................... 50

XT............................................................................... 50

Oscillator Configurations..................................................... 46

Oscillator Types

EXTRC ....................................................................... 46

HS............................................................................... 46

INTRC......................................................................... 46

LP ............................................................................... 46

XT............................................................................... 46

Package Marking Information........................................... 103

Packaging Information...................................................... 103

Paging, Program Memory................................................... 22

PCL..................................................................................... 62

PCL Register .......................................................... 13, 14, 22

PCLATH.............................................................................. 51

PCLATH Register................................................... 13, 14, 22

PCON Register............................................................. 20, 50

PD bit............................................................................ 15, 48

PIC12CE67X DC and AC Characteristics .......................... 99

PICDEM-1 Low-Cost PICmicro Demo Board ..................... 76

PICDEM-2 Low-Cost PIC16CXX Demo Board................... 76

PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 76

PICSTART Plus Entry Level Development System......... 75

PIE1 Register...................................................................... 18

Pinout Description

PIC12CE67X ................................................................ 9

PIR1 Register ..................................................................... 19

POP.................................................................................... 22

POR.................................................................................... 50

Oscillator Start-up Timer (OST)............................ 45, 50

Power Control Register (PCON)................................. 50

Power-on Reset (POR)................................... 45, 50, 51

Power-up Timer (PWRT)...................................... 45, 50

Power-Up-Timer (PWRT) ........................................... 50

Time-out Sequence .................................................... 50

Time-out Sequence on Power-up............................... 52

TO............................................................................... 48

Power.................................................................................. 48

Power-down Mode (SLEEP)............................................... 58

Prescaler, Switching Between Timer0 and WDT................ 35

PRO MATE II Universal Programmer.............................. 75

Product Identification System - PIC12CE67X................... 113

Program Branches................................................................ 7

Program Memory

Paging ........................................................................ 22

Program Memory Map

PIC12CE67X .............................................................. 11

Program Verification........................................................... 59

PS0 bit................................................................................ 16

PS1 bit................................................................................ 16

 1998 Microchip Technology Inc. Preliminary DS40181B-page 109

PIC12CE67X

PS2 bit ................................................................................16

PSA bit................................................................................16

PUSH..................................................................................22

RC Oscillator.......................................................................47

Read Modify Write ..............................................................26

Read-Modify-Write..............................................................26

Registers

Map PIC12CE67X ......................................................12

Reset Conditions.........................................................51

Reset.............................................................................45, 48

Reset Conditions for Special Registers ..............................51

RETFIE Instruction..............................................................70

RETLW Instruction..............................................................70

RETURN Instruction ...........................................................71

RLF Instruction....................................................................71

RP0 bit..........................................................................11, 15

RP1 bit................................................................................15

RRF Instruction...................................................................71

SEEVAL Evaluation and Programming System...............77

Services

One-Time-Programmable (OTP) ..................................5

Quick-Turnaround-Production (QTP)............................5

Serialized Quick-Turnaround Production (SQTP).........5

SFR.....................................................................................62

SFR As Source/Destination................................................62

SLEEP ..........................................................................45, 48

SLEEP Instruction...............................................................71

Software Simulator (MPLAB-SIM) ......................................77

Special Features of the CPU ..............................................45

Special Function Register

PIC12CE67X...............................................................13

Special Function Registers.................................................62

Special Function Registers, Section...................................12

Stack...................................................................................22

Overflows....................................................................22

Underflow....................................................................22

STATUS Register ...............................................................15

SUBLW Instruction..............................................................72

SUBWF Instruction .............................................................72

SWAPF Instruction..............................................................73

T0CS bit..............................................................................16

TAD......................................................................................41

Timer0

RTCC..........................................................................51

Timers

Timer0

Block Diagram.................................................... 31

External Clock .................................................... 33

External Clock Timing ........................................ 33

Increment Delay ................................................. 33

Interrupt.............................................................. 31

Interrupt Timing .................................................. 32

Prescaler ............................................................ 34

Prescaler Block Diagram.................................... 34

Section ............................................................... 31

Switching Prescaler Assignment........................ 35

Synchronization.................................................. 33

T0CKI ................................................................. 33

T0IF.................................................................... 56

Timing................................................................. 31

TMR0 Interrupt ................................................... 56

Timing Diagrams

A/D Conversion .......................................................... 97

CLKOUT and I/O........................................................ 92

External Clock Timing................................................. 90

Time-out Sequence.................................................... 52

Timer0 .................................................................. 31, 94

Timer0 Interrupt Timing.............................................. 32

Timer0 with External Clock......................................... 33

Wake-up from Sleep via Interrupt............................... 59

TO bit.................................................................................. 15

TOSE bit............................................................................. 16

TRIS Instruction.................................................................. 73

TRIS Register......................................................... 14, 25, 26

Two’s Complement................................................................7

UV Erasable Devices.............................................................5

W Register

ALU................................................................................7

Wake-up from SLEEP ........................................................ 58

Watchdog Timer (WDT).................................... 45, 48, 51, 57

WDT ................................................................................... 51

Block Diagram............................................................ 57

Period......................................................................... 57

Programming Considerations..................................... 57

Timeout....................................................................... 51

WWW, On-Line Support........................................................2

XORLW Instruction............................................................. 73

XORWF Instruction............................................................. 73

Z bit..................................................................................... 15

Zero bit ..................................................................................7

PIC12CE67X

DS40181B-page 110 Preliminary  1998 Microchip Technology Inc.

 1998 Microchip Technology Inc. DS40181B-page10-111

PIC12CE67X

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-602-786-7302 for the rest of the world.

Trademarks: The Microchip name, logo, PIC, PICSTART,

PICMASTER and PRO MATE are registered trademarks

of Microchip Technology Incorporated in the U.S.A. and

other countries. PICmicro,

Flex

ROM, MPLAB and

fuzzy-

LAB are trademarks and SQTP is a service mark of Micro-

chip in the U.S.A.

fuzzy

TECH is a registered trademark of Inform Software

Corporation. IBM, IBM PC-AT are registered trademarks

of International Business Machines Corp. Pentium is a

trademark of Intel Corporation. Windows is a trademark

and MS-DOS, Microsoft Windows are registered trade-

marks of Microsoft Corporation. CompuServe is a regis-

tered trademark of CompuServe Incorporated.

All other trademarks mentioned herein are the property of

their respective companies.

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The web site is used b y Microchip as a means to mak e

ﬁles and information easily available to customers. To

view the site , the user must ha ve access to the Internet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your

favorite Internet browser to attach to:

www.microchip.com

The ﬁle transfer site is available by using an FTP ser-

vice to connect to:

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The web site and ﬁle transf er site pro vide a v ariety of

services. Users may download ﬁles for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip speciﬁc business information is also

available, including listings of Microchip sales ofﬁces,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products , De velopment Systems ,

technical information and more

• Listing of seminars and events

980106

PIC12CE67X

DS40181B-page10-112  1998 Microchip Technology Inc.

READER RESPONSE

It is our intention to provide y ou with the best documentation possible to ensure successful use of your Microchip prod-

uct. If y ou wish to provide y our comments on organization, clarity, subject matter , and wa ys in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS40181B

PIC12CE67X

 1998 Microchip Technology Inc. Preliminary DS40181B-page 113

PIC12CE67X

PIC12CE67X PRODUCT IDENTIFICATION SYSTEM

Please contact your local sales ofﬁce for exact ordering procedures.

SALES AND SUPPORT

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce.

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

Pattern: Special Requirements

Package: P = 300 mil PDIP

JW = 300 mil Windowed Ceramic Side Brazed

Temperature

Range: - = 0°C to +70°C

I = -40°C to +85°C

E = -40°C to +125°C

Frequency

Range: 04 = 4 MHz/200 kHz

10 = 10 MHz

Device PIC12CE673

PIC12CE674

PIC12LCE673

PIC12LCE674

PART NO. -XX X /XX XXX Examples

a) PIC12CE673-04/P

Commercial Temp.,

PDIP Package, 4 MHz,

normal VDD limits

b) PIC12CE673-04I/P

Industrial Temp., PDIP

package, 4 MHz, normal

VDD limits

c) PIC12CE673-10I/P

Industrial Temp.,

PDIP package , 10 MHz,

normal VDD limits

PIC12CE67X

DS40181B-page 114 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40181B-page 115

PIC12CE67X

NOTES:

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed

by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products

as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property r ights. The Microchip

logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS40181B-page 116  1998 Microchip Technology Inc.

AMERICAS

Corporate Ofﬁce

Microchip Technology Inc.

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Chandler, AZ 85224-6199

Tel: 602-786-7200 Fax: 602-786-7277

Technical Support:

602 786-7627

Web:

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Atlanta

Microchip Technology Inc.

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Tel: 770-640-0034 Fax: 770-640-0307

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Chicago

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Microchip Technology Inc.

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Tel: 972-991-7177 Fax: 972-991-8588

Dayton

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Detroit

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San Jose

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AMERICAS (continued)

Toronto

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Tel: 905-405-6279 Fax: 905-405-6253

ASIA/PACIFIC

Hong Kong

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India Liaison Ofﬁce

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Tel: 91-80-229-0061 Fax: 91-80-229-0062

Japan

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Korea

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Shanghai

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ASIA/PACIFIC (continued)

Singapore

Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre

Singapore 188980

Tel: 65-334-8870 Fax: 65-334-8850

Taiwan, R.O.C

Microchip Technology Taiwan

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EUROPE

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

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Tel: 44-1189-21-5858 Fax: 44-1189-21-5835

France

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Germany

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Italy

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Tel: 39-39-6899939 Fax: 39-39-6899883

7/7/98

WORLDWIDE SALES AND SERVICE

Microchip received ISO 9001 Quality

System certiﬁcation for its w orldwide

headquarters, design, and wafer

fabrication facilities in J anuary , 1997.

Our ﬁeld-programmable PICmicro™

8-bit MCUs, Serial EEPROMs,

related specialty memory products

and development systems conform

to the stringent quality standards of

the International Standard

Organization (ISO).