Am79761 - Advanced Micro Devices

Publication# 22206 Rev: DAmendment/0

Issue Date: November 1999

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Am79C978

PCnet™- Home

Single-Chip 1/10 Mbps PCI Home Networking Controller

DISTINCTIVE CHARACTERISTICS

nFully integrated 1 Mbps HomePNA Physical

Layer (PHY) as defined by Home Phoneline

Networking Alliance (HomePNA) specification

1.1

— Optimized for home networking applications

over ordinary telephone wire

— In-band control features:

Adjustable power and speed levels

32 bits of reserved in-band messaging piggy-

backed on Ethernet packet

— Register programmable features:

Power control

Performance registers

Speed control

Major frame timing parameters programma-

ble: ISBI, AID ISBI, pulse width, inter-symbol

time

nFully integrated 10 Mbps PHY interface

— Comprehensive Auto-Negotiation

implementation

— Full-duplex capability

— Optimized for 10BASE-T applications

nIntegrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus

— 32-bit glueless PCI host interface

— Supports PCI clock frequency from DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

— PC I draft specifi cation revis ion 2.2 complia nt

— Supports PCI Subsystem/Subvendor ID/

V endor ID programming through the

EEPROM interface

— Supports both PCI 5.0-V and 3.3-V signaling

environments

— Plug and Play compatible

— Supports an unlimited PCI burst length

— Big endian and little endian byte alignments

supported

— Implements optional PCI power management

event (PME) pin

nDual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 Ethernet standard

nMedia Independent Interface (MII) for

connecting external 10/100 Mbps transceivers

— IEEE 802.3u compliant MII

— Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Supports both auto-negotiable and non-

auto-negotiable external PHYs

— Supports 10BASE-T, 100BASETX/FX,

100BASET4, and 100BASET2 IEEE 802.3

compliant MII PHYs at full-duplex or half-

duplex

nFull-duplex operation supported on the MII port

with independent Transmit (TX) and Receive

(RX) channels

nSupports PC98 and Net PC specifications

— Implements full OnNow features including

pattern matching and link status wake-up

events

— Implements Magic Packet™ mode

— Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock

— Supports PCI Bus Power Management

Interface specification revision 1.1

— Supports Advanced Configuration and

Power Interface (ACPI) specification version

1.0

— Supports Network Device Class Power

Management specification version 1.0a

2 Am79C978

nIndependent internal TX and RX FIFOs

—Programmable FIFO wa termarks for b oth TX

and RX operations

—RX frame queuing for high latency PCI bus

host operation

—Programmable allocation of buffer space

between RX and TX queues

nExtensive programmable internal/external

loopback capabilities

nEEPROM interface supports jumperless design

and provides through-chip programming

—Supports full programmability of half-/full-

duplex operation thr ough EEPROM mapping

—Programmable PHY reset output pin capable

of resetting external PHY without the need

for buffering

nExtensive programmable LED status support

nLook-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead

by allowing protocol analysis to begin before

the end of a receive frame

nIncludes Programmable Inter Packet Gap (IPG)

to address less network aggressive MAC

controllers

nOffers the Modified Back-Off algorithm to

address the Eth ernet Capture Effect

nIEEE 1149.1-compliant JTAG Boundary Scan

test access port interface and NAND tree test

mode for board-level production c onnectivity

test

nSoftware compatible with AMD’s PCnet™

Family and LANCE/C-LANCE register and

descriptor architecture

nVery low power consumption

n+3.3 V power supply along wit h 5 V tolerant I/Os

enable broad system compatibility

nAvailable in 144-pin TQFP and 160-pin PQFP

packages

GENERAL DESCRIPTION

The Am79C978 controller is the first in a series of home

networking products from AMD. The Am79C978 con-

troller is fabricated in an advanced low power 3.3 V

CMOS process to provide low operating current for

power sensitive applications.

The Am79C978 controller contains an Ethernet Con-

troller b ased on th e Am79C971 Fast E thernet cont rol-

ler, a physical layer device for supporting the 802.3

standard for 10BASE-T, and a physical layer device for

data netwo rking at speeds up to 1 Mbps ove r ordinary

residential telephone wiring.

The inte grate d PCI E thernet c ontr oller i s a highl y in te-

grated 32-bit full-duplex, 10/100 Mbps Ethernet con-

troller solution designed to address high-performance

system application requirements. It is a flexible bus-

mastering device that can be used in any application,

including network ready PCs. The bus master architec-

ture provides high data throughput and low CPU and

system bus utilization.

The integ rated Ethernet tr ansc eive r is a phy sical l ayer

device supporting the IEEE 802.3 standards for

10BASE-T. It provides all of the PHY layer functions re-

quired to support 10 Mbps data transfer speeds.

The integrated HomePNA transceiver is a physical

layer device that enables data networking at speeds up

to 1 Mbps over common residential phone wiring re-

gardless of topology and without disrupting telep hone

(POTS) se rvice.

The 32-bit multiplexed bus interface unit provides a di-

rect interface to the PCI local bus, simplifying the de-

sign of an Ethernet or home network node in a PC

system. The device has built-in support for both little

and big endian byte alignment. The integrated home

networking controller’s advanced CMOS design allows

the bus in ter face to be con nec ted to e ith er a + 5.0 V or

a +3.3 V signaling environment. A compliant IEEE

1149.1 JTAG test interface for board level testing is

also provided, as well as a NAND tree test structure for

those systems that do not support the JTAG interface.

The integrated Am79C978 home networking controller

is also co mplian t with the PC9 8 and Net PC speci fica-

tions. It includes the full implementation of the Mi-

crosoft OnNow and ACPI specifications, which are

backwar d compati ble with Ma gic Pa cket technol ogy. It

is also compliant with the PCI Bus Power Management

Interface specification by supporting the four power

management states (D0, D1, D2, and D3), the optional

PME pin, and the necessary configuration and data

registers.

The integrated Am79C978 home networking controller

is a complete Ethernet or home network node inte-

grated into a single VLSI device. It contains a bus inter-

face unit, a Direct Memory Access (DMA) Buffer

Management Unit, an ISO/IEC 88023 (IEEE 802.3)

complia nt Media Ac cess Con troller (M AC), a Transmit

FIFO and a large Receive FIFO, and an IEEE 802.3u

compliant MII. Both IEEE 802.3 compliant full-duplex

and half-duplex operations are supported on the MII in-

terface. 10/100 Mbps operation is supported through

the MII interface.

The integrated Am79C978 home networking controller

is register compatible with the LANCE (Am7990) and

C-LANCE (Am79C90) Ethernet controllers and all

Am79C978 3

Ethernet controllers in the PCnet Family (except

ILACC™ (Am79C900)), including PCnet-ISA

(Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA II

(Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI

(Am79C970), PCnet-PCI II (Am79C970A), PCnet-

FAST (Am79C971), and PCnet-FAST+ (Am79C972).

The Buffer Management Unit supports the LANCE and

PCnet descriptor software models.

While consuming minimal network resources, AMD’s

innovative any1Home™ Link Detection Packet for

HomePNA networks provides a means to indicate to

the MAC a nd thus the up per lay ers of the sy stem pro-

tocol that a valid network (as defined by Home Net-

working Alliance) has been detected. The Link

Detection Packet is also capable of detecting a network

failure and allows the upp er la yer pro tocol to take cor -

rective a cti on . Thus , t he L in k D etec tion P ac k et e nsur e

strict compliance to the Microsoft PC97, PC98, and

Home PNA requirements.

The integrated Am79C978 controller supports auto-

configuration in the PCI configuration space. Additional

integrated controller configuration parameters, includ-

ing the unique IEEE physical address, can be read

from an external non-volatile memory (EEPROM) im-

media tel y foll owi ng sy st em reset.

In addition, the Am79C978 controller provides pro-

grammable on-chip LED drivers for transmit, receive,

collision, link integrity, Magic Packet status, speed, ac-

tivity, pow er ou tpu t, a ddr ess ma tch , full-dupl ex , or 10 0

Mbps status.

4 Am79C978

BLOCK DIAGRAM

CLK

RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT

PERR

SERR

INTA

PCI Bus

Interface

Unit

Buffer

Management

Unit

Bus

Rcv

FIFO

Bus

Xmt

FIFO

Control Network

Port

Manager

MAC

Rcv

FIFO

12K

SRAM

MAC

Xmt

FIFO

JTAG

Port

Control

OnNow

Power

Management

Unit

802.3

MAC

Core

93C46

EEPROM

Interface

LED

Control

PME PG

TCK

TMS

TDI

TDO

Transmit

State

Machine

MII

Interface

MII

Management

MDIO

Receive

State

Machine

PHY Control

Link

Monitor Auto

Negotiation

10 Mbps PHY

Transmit

State

Machine

MII

Interface

Receive

State

Machine

Drive

Control

Analog

Front

End

10 BASE-T

TX±

RX±

LED0

LED1

LED2

LED3

LED4

EECS

EESK

EEDI

EEDO

MII

Management

MDIO

RXD(3:0)/TXD(3:0)

PHY

Control Link

Monitor

HRTXRXP/N

MDC

1Mbps HomePNA PHY

MDC

Clock

Reference XTAL2

XTAL1

22206B-1

Am79C978 5
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5
CONNECTION DIAGRAM (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CONNECTION DIAGRAM (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESIGNATIONS (PQL144). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PIN DESIGNATIONS (PQR160)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PIN DESIGNATIONS (PQL144). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PIN DESIGNATIONS (PQR160)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Magic Packet Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Board Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
EEPROM Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Ethernet Network Interfaces  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
HomePNA PHY Network Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BASIC FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MII Receive Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Management Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Auto-Poll External PHY Status Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Network Port Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PCI and JTAG Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave Bus Interface Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave I/O Tr ansfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Slave Cycle Termination  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Disconnect When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Disconnect Of Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Master Bus Interface Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Bus Acquisition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Target Initiated Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Disconnect With Data Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

6 Am79C978
Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Master Initiated Termination  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8
Preemption During Non-Burst Transaction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Preemption During Burst Transaction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Master Abort  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Advanced Parity Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Initialization Block DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Non-Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Re-Initialization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Descriptor Rings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Transmit Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Receive Descriptor Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Software Interrupt Timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
10/100 Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Media Access Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Medium Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Collision Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Transmit Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Late Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
SQE Test Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Receive Function Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Automatic Pad Stripping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receive Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Miscellaneous Loopback Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Full-Duplex Link Status LED Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
1 Mbps HomePNA PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
HomePNA PHY Medium Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
HomePNA Symbol Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Time Interval Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
ACCESS ID Intervals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Symbol 0 (SYNC interval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SYNC Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Am79C978 7
SYNC Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AID Symbols 1 through 6  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AID Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AID Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Collisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
JAM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ACCESS ID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Silence Interval (AID symbol 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Data Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Symbol RLL25 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Management Interfaces  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Header AID Remote Control Word Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PHY Control and Management Block (PCM Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Register Administration for 10BASE-T PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Description of the Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Direct SRAM Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Automatic EEPROM Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EEPROM Auto-Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Direct Access to the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EEPROM-Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EEPROM MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power Management Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
OnNow Wake-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Link Change Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
OnNow Pattern Match Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Pattern Match RAM (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Magic Packet Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Boundary Scan Circuit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Instruction Register and Decoding Logic  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Boundary Scan Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Other Data Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
NAND Tree Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
S_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
STOP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Power on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Address PROM Space  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Double Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10BASE-T Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Twisted Pair Transmit Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Collision Detect Function  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
 

8 Am79C978
Jabber Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Reverse Polarity Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Soft Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
PCI Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PCI Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
PCI Revision ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Programming Interface Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Sub-Class Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Base-Class Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Memory Mapped I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Subsystem ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Interrupt Line Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI MIN_GNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI MAX_LAT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Capability Identifier Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Power Management Capabilities Register (PMC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Power Management Control/Status Register (PMCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
PCI PMCSR Bridge Support Extensions Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
RAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
RAP: Register Address Port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Control and Status Registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR0: Controller Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CSR3: Interrupt Masks and Deferral Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
CSR5: Extended Control and Interrupt 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
CSR7: Extended Control and Interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR12: Physical Address Register 0  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR13: Physical Address Register 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR14: Physical Address Register 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR15: Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR20: Current Transmit Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR21: Current Transmit Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR22: Next Receive Buffer Address Lower  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR23: Next Receive Buffer Address Upper  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Am79C978 9
CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR28: Current Receive Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR29: Current Receive Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR32: Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR33: Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR36: Next Next Receive Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR37: Next Next Receive Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR38: Next Next Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR39: Next Next Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR40: Current Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR41: Current Receive Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR42: Current Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR43: Current Transmit Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR44: Next Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR45: Next Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR46: Transmit Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR48: Receive Poll Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR49: Receive Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR58: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR60: Previous Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR61: Previous Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR62: Previous Transmit Byte Count  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR63: Previous Transmit Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR64: Next Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR65: Next Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR66: Next Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR67: Next Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR72: Receive Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR74: Transmit Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR78: Transmit Ring Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR82: Transmit Descriptor Address Pointer Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR88: Chip ID Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR89: Chip ID Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR92: Ring Length Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR100: Bus Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR114: Receive Collision Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR122: Advanced Feature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR124: Test Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR125: MAC Enhanced Configuration Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Bus Configuration Registers (BCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR1: Master Mode Write Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR2: Miscellaneous Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR4: LED0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
BCR5: LED1 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
BCR6: LED2 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10 Am79C978
BCR7: LED3 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
BCR9: Full-Duplex Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR16: I/O Base Address Lower  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR17: I/O Base Address Upper  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
BCR19: EEPROM Control and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
BCR20: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
BCR22: PCI Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
BCR23: PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR25: SRAM Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR26: SRAM Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR27: SRAM Interface Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
BCR28: Expansion Bus Port Address Lower (Used for Flash/EPROM and SRAM Accesses). . . .166
BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses). . . . . . . . . . . . . . . . .167
BCR30: Expansion Bus Data Port Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
BCR31: Software Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
BCR32: PHY Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
BCR33: PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
BCR34: PHY Management Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . . . . . . . . . . . . . . . . .172
BCR37: PCI DATA Register 0 (DATA0) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
BCR38: PCI DATA Register 1 (DATA1) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
BCR39: PCI DATA Register 2 (DATA2) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
BCR40: PCI DATA Register 3 (DATA3) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR41: PCI DATA Register 4 (DATA4) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR42: PCI DATA Register 5 (DATA5) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR43: PCI DATA Register 6 (DATA6) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR44: PCI DATA Register 7 (DATA7) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR48: LED4 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR49: PHY Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
BCR50-BCR55: Reserved Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
1 Mbps HomePNA PHY Internal Registers 179
HPR0: HomePNA PHY MII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
HPR1: HomePNA PHY MII Status    (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  180
HPR2 and HPR3: HomePNA PHY MII PHY ID (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . .181
HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7). . . . . . . . . . . . . . . . . . . . . . . . . .181
Reserved Registers: HPR8 - HPR15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
HPR16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  182
HPR17: HomePNA Status Control (Register 17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  183
HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19)  . . . . . . . . . . . . . . . . . . . . .183
HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . . . . . . . .  184
HPR22: HomePNA PHY AID (Register 22)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
HPR23: HomePNA PHY Noise Control (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
HPR24: HomePNA PHY Noise Control 2 (Register 24)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
HPR25: HomePNA PHY Noise Statistics (Register 25). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
HPR26: HomePNA PHY Event Status (Register 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  186
HPR27: HomePNA PHY Event Status (Register 27). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
HPR28: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
HPR29: HomePNA PHY TX Control (Register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
HPR30: 1 Mbps HomePNA PHY Drive Level Control Test Register (Register 30) . . . . . . . . . . . . .187
HPR31: 1 Mbps HomePNA PHY Analog Control Register (Register 31) . . . . . . . . . . . . . . . . . . . .187
10BASE-T PHY Management Registers (TBRs) 188
TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
TBR1: 10BASE-T Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  190
TBR2 and TBR3: 10BASE-T PHY Identifier (Registers 2 and 3). . . . . . . . . . . . . . . . . . . . . . . . . .  191

Am79C978 11
TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4)  . . . . . . . . . . . . . . . . . . .192
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . .193
TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6). . . . . . . . . . . . . . . . . . . . . .  194
TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7). . . . . . . . . . . . . . . . . . . . . . .194
Reserved Registers (Registers 8-15, 18, 20-23, and 25-31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . . . . . . . .  195
TBR17: 10BASE-T PHY Control/Status Register (Register 17)  . . . . . . . . . . . . . . . . . . . . . . . . . .  196
TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . . . . . . . .  197
Reserved Register: 10BASE-T Configuration Register (Register 22) . . . . . . . . . . . . . . . . . . . . . . .197
Reserved Register: 10BASE-T Carrier Status Register (Register 23). . . . . . . . . . . . . . . . . . . . . . .197
TBR24: 10BASE-T Summary Status Register (Register 24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Initialization Block  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  198
RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
RDRA and TDRA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
LADRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
PADR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
RMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
RMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
RMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
RMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
TMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
TMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
TMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
TMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
PCI Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Control and Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
10BASE-T PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
1 Mbps HomePNA PHY Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
REGISTER PROGRAMMING SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
Am79C978 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
ABSOLUTE MAXIMUM RATINGS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE                        
SPECIFIED  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
SWITCHING CHARACTERISTICS: BUS INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
10BASE-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
External Clock (XTAL) Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
External Clock (Oscillator) Timing Specification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . .228
SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
PQL144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
PQR160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
APPE NDIX  A:  ALTERNATIV E  ME THOD FO R INITIAL IZATIO N .  . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
APPENDIX B: LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-1

12 Am79C978
LIST OF FIGURES
Figure 1. Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
Figure 2. Frame Format at the MII Interface Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
Figure 3. Slave Configuration Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
Figure 4. Slave Configuration Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
Figure 5. Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
Figure 6. Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39
Figure 7. Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39
Figure 8. Disconnect of Slave Cycle When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40
Figure 9. Disconnect of Slave Burst Transfer - No Host Wait States. . . . . . . . . . . . . . . . . . . . . . . . . .  40
Figure 10. Disconnect of Slave Burst Transfer - Host Inserts Wait States. . . . . . . . . . . . . . . . . . . . . .  41
Figure 11. Address Parity Error Response  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  41
Figure 12. Slave Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
Figure 13. Bus Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  43
Figure 14. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
Figure 16. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
Figure 17. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
Figure 18. Disconnect With Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
Figure 19. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  48
Figure 20. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
Figure 21. Preemption During Non-Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
Figure 22. Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
Figure 23. Master Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
Figure 24. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
Figure 25. Initialization Block Read In Non-Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
Figure 26. Initialization Block Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
Figure 27. Descriptor Ring Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  55
Figure 28. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  55
Figure 29. Descriptor Ring Write In Non-Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
Figure 30. Descriptor Ring Write In Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
Figure 31. FIFO Burst Write at Start of Unaligned Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58
Figure 32. FIFO Burst Write at End of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58
Figure 33. 16-Bit Software Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
Figure 34. 32-Bit Software Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  62
Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  69
Figure 36. IEEE 802.3 Frame and Length Field Transmission Order . . . . . . . . . . . . . . . . . . . . . . . . .  73
Figure 37. HomePNA PHY Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  76
Figure 38. AID Symbol Transmit Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77
Figure 39. AID Symbol Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77
Figure 40. Transmit Data Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  79
Figure 41. Receive Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  79
Figure 42. RLL 25 Coding Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  80
Figure 43. Block Diagram No SRAM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  82
Figure 44. Block Diagram Low Latency Receive Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  83
Figure 45. LED Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  87
Figure 46. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  88
Figure 47. Pattern Match RAM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  90
Figure 48. NAND Tree Circuitry (160 PQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  92
Figure 49. NAND Tree Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  94
Figure 50. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  98
Figure 51. Address Match Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  200
Figure 52. Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  225
Figure 53. PMD Interface Timing (PECL)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Figure 54. 10 Mbps Transmit (TX±) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Figure 55. 10 Mbps Receive (RX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Figure 56. Normal and Tri-State Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  229
Figure 57. CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  230
Figure 58. CLK Waveform for 3.3 V Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  230

Am79C978 13
Figure 59. Input Setup and Hold Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  230
Figure 60. Output Valid Delay Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  231
Figure 61. Output Tri-State Delay Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  231
Figure 62. EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  231
Figure 63. Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  232
Figure 64. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . .  232
Figure 65. JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  233
Figure 66. Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  234
Figure 67. Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  234
Figure 68. MDC Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  234
Figure 69. Management Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  235
Figure 70. Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  235
Figure B-1. LAPP Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-4
Figure B-2. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-5
Figure B-3. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-9
Figure B-4. LAPP 3 Buffer Grouping for Two-inter rupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-10
LIST OF TABLES
Table 1. Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
Table 2. External Clock/Crystal Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
Table 3. PCI Device ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
Table 4. PCI Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
Table 5. Slave Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
Table 6. Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
Table 7. Master Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
Table 8. Descriptor Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
Table 9. Descriptor Write Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
Table 10. Receive Address Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  72
Table 11 . HomePNA PHY Pulse Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  76
Table 12. Access ID Symbol Pulse Positions and Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  78
Table 13. Blanking Interval Speed Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  79
Table 14. Master Station Control Word Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  81
Table 15. MII Control Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  81
Table 16. EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  86
Table 17. LED Default Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  87
Table 18. IEEE 1149.1 Supported Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  91
Table 19. BSR Mode Of Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  91
Table 20. Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  91
Table 21. NAND Tree Pin Sequence (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  93
Table 22. NAND Tree Pin Sequence (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  93
Table 24. PCI Configuration Space Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  95
Table 25. I/O Map in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
Table 26. Legal I/O Accesses in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
Table 27. I/O Map in DWord I/O Mode (DWIO = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  98
Table 28. Legal I/O Accesses in Double Word I/O Mode (DWIO =1). . . . . . . . . . . . . . . . . . . . . . . . . .  98
Table 29. Auto-Negotiation Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  99
Table 30. Loopback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  128
Table 31. Software Styles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  135
Table 32. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  138
Table 33. Transmit Start Point Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  139
Table 34. Transmit Watermark Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  139
Table 35. BCR Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  146
Table 36. ROMTNG Programming Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  156
Table 37. PHY Select Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  158
Table 38. EEDET Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  161
Table 39. Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  161
Table 40. Software Styles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  163
Table 41. SRAM_BND Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
Table 42. EBCS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  166
Table 43. CLK_FAC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  166

14 Am79C978
Table 44. FMDC Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  169
Table 45. APDW Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  169
Table 46. HPR0: HomePNA PHY MII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  179
Table 47. HPR1: HomePNA PHY MII Status (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  180
Table 48. HPR2 and HPR3: HomePNA PHY MII ID (Registers 2 and 3). . . . . . . . . . . . . . . . . . . . . .  181
Table 49. HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7). . . . . . . . . . . . . . . . . . .  181
Table 50. HPR16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  182
Table 51. HPR17: HomePNA Status Control (Register 17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  183
Table 52. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19). . . . . . . . . . . . . . .  183
Table 53. HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21)  . . . . . . . . . . . . . .  184
Table 54. HPR22: HomePNA PHY AID (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  184
Table 55. HPR23: HomePNA PHY Noise Control (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  184
Table 56. HPR24: HomePNA PHY Noise Control 2 (Register 24). . . . . . . . . . . . . . . . . . . . . . . . . . .  185
Table 57. HPR25: HomePNA PHY Noise Statistics (Register 25). . . . . . . . . . . . . . . . . . . . . . . . . . .  185
Table 58. HPR26: HomePNA PHY Event Status (Register 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . .  186
Table 59. HPR27: HomePNA PHY Event Status (Register 27). . . . . . . . . . . . . . . . . . . . . . . . . . . . .  186
Table 60. HPR8: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  186
Table 61. HPR29: HomePNA PHY TX Control (Register 29)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  187
Table 62. HPR30: HomePNA PHY Drive Level Control Test Register (Register 30). . . . . . . . . . . . .  187
Table 63. HPR31: HomePNA PHY Analog Control Register (Register 31) . . . . . . . . . . . . . . . . . . . .  187
Table 64. Am79C978 10BASE-T PHY Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . .  188
Table 65. TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  189
Table 66. TBR1: 10BASE-T PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  190
Table 67. TBR2: 10BASE-T PHY Identifier (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  191
Table 68. TBR3: 10BASE-T PHY Identifier (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  191
Table 69. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4). . . . . . . . . . . . .  192
Table 70. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page                        
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  193
Table 71. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page                                                    
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  193
Table 72. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . .  194
Table 73. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . . . .  194
Table 74. TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . .  195
Table 75. TBR17: 10BASE-T PHY Control/Status Register (Register 17). . . . . . . . . . . . . . . . . . . . .  196
Table 76. TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . .  197
Table 77. TBR24: 10BASE-T Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . .  197
Table 78. Initialization Block (SSIZE32 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  198
Table 79. Initialization Block (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  198
Table 80. R/TLEN Decoding (SSIZE32 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  199
Table 81. R/TLEN Decoding (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  199
Table 82. Receive Descriptor (SWSTYLE = 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  200
Table 83. Receive Descriptor (SWSTYLE = 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  200
Table 84. Receive Descriptor (SWSTYLE = 3)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  200
Table 85. Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
Table 86. Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
Table 87. Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
Table 88. PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  207
Table 89. Control and Status Registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  208
Table 90. Bus Configuration Registers (BCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
Table 91. 10BASE-T PHY Management Registers (TBRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  213
Table 92. 1 Mbps HomePNA PHY Management Registers (HPRs) . . . . . . . . . . . . . . . . . . . . . . . . .  214
Table 93. Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  215
Table 94. Bus Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  217
Table A-1. Registers for Alternative Initialization Method (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . .  A-1
 

Am79C978 15

RELATED AMD PRODUCTS

Part No. Description

Controllers

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

Integrated Controllers

Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller

Am79C940B Media Access Controller for Ethernet (MACE™)

Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus

Am79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses

Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus

Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Am79C972 PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

Manchester Encoder/Decoder

Am7992B Serial Interface Adapter (SIA)

Physical Layer Devices (Single-Port)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver (TAP)

Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)

Am79C98 Twisted Pair Ethernet Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Am79C873 10/100 Mbps Ethernet Physical Layer Transceiver (NetPHY™-1)

Physical Layer Devices (Multi-Port)

Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)

Am79C988B Quad Integrated Ethernet Transceiver (QuIET™)

Am79C989 Quad Ethernet Switching Transceiver (QuEST™)

Integrated Repeater/Hub Devices

Am79C981 Integrated Multiport Repeater Plus (IMR+)

Am79C982 Basic Integrated Multiport Repeater (bIMR)

Am79C983A Integrated Multiport Repeater 2 (IMR2™)

Am79C984A Enhanc ed Inte gra ted Mu ltip ort R epe ater (eIMR ™)

Am79C985 Enhanc ed Inte gra ted Mu ltip ort R epe ater Plus (eIMR+™)

Am79C987 Hardware Implemented Management Information Base (HIMIB™)

16 Am79C978

CONNECTION DIAGRAM (144 TQFP)

100

101

102

103

104

108

107

106

105

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

PCI_CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

PME

VSS

EECS

VSSB

EESK/LED1

LED2

VDDB

EEDI/LED0

EEDO/LED3

RX-

DVDDRX

RX+

DVSSX

TX-

DVDDTX

TX+

DVDDD

IREF

DVSSD

DVSSA

DVDDA

PHY_RST

DVDDA_HR

VSSB

VDDB

HRTRXP

VDDHR

HRTRXN

VSSHR

VDDCO

XTAL1

XTAL2

VSS

VDD

XCLK/XTAL

LED4

MDIO

VSSB

MDC

RXD3

RXD2

VDDB

RXD1

RXD0

VSS

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

VDD

CRS

VSSB

COL

TXD3

TXD2

TXD1

VDD

VDDB

TXD0

TX_EN

TX_CLK

VSSB

RX_ER

RX_CLK

RX_DV

132

131

130

129

128

127

126

125

124

123

122

144

143

142

141

140

139

138

137

136

135

134

133

121

120

119

118

117

116

115

114

113

112

111

110

109

Am79C978

22206B-2

Am79C978 17

CONNECTION DIAGRAM (160 PQFP)

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

DD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

DD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

DD_PCI

AD1

AD0

VSS

VDD

CRS

VSSB

COL

TXD3

TXD2

TXD1

VDD

VDDB

TXD0

TX_EN

TX_CLK

VSSB

RX_ER

RX_CLK

RX_DV

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

PCI_CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

PME

VSS

EECS

VSSB

EESK/LED1

LED2

VDDB

EEDI/LED0

EEDO/LED3

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

RX-

DVDDRX

RX+

DVSSX

TX-

DVDDTX

TX+

DVDDD

IREF

DVSSD

DVSSA

DVDDA

PHY_RST

DVDDA_HR

VSSB

VDDB

HRTRXP

VDDHR

HRTRXN

VSSHR

VDDCO

XTAL1

XTAL2

VSS

VDD

XCLK/XTAL

LED4

MDIO

VSSB

MDC

RXD3

RXD2

VDDB

RXD1

RXD0

VSS

Am79C978

22206B-3

18 Am79C978

PIN DESIGNATIONS (PQL144)

Listed By Pin Number

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name

1IDSEL 37 AD11 73 VSS 109 EEDO/LED3

2AD23 38 VDD_PCI 74 RXD0 110 EEDI/LED0

3VSSB 39 AD10 75 RXD1 111 VDDB

4AD22 40 AD9 76 VDDB 112 LED2

5VDD_PCI 41 AD8 77 RXD2 113 EESK/LED1

6AD21 42 C/BE078 RXD3 114 VSSB

7AD20 43 VSSB 79 MDC 115 EECS

8VDD 44 AD7 80 VSSB 116 VSS

9AD19 45 VDD_PCI 81 MDIO 117 PME

10 AD18 46 AD6 82 LED4 118 TCK

11 VSSB 47 AD5 83 XCLK/XTAL 119 TMS

12 AD17 48 VDD 84 VDD 120 VDDB

13 VDD_PCI 49 AD4 85 VSS 121 TDO

14 AD16 50 AD3 86 XTAL2 122 VSSB

15 C/BE251 VSSB 87 XTAL1 123 TDI

16 VSS 52 AD2 88 VDDCO 124 VDD

17 FRAME 53 VDD_PCI 89 VSSHR 125 PG

18 IRDY 54 AD1 90 HRTRXN 126 INTA

19 VSSB 55 AD0 91 VDDHR 127 RST

20 TRDY 56 VSS 92 HRTRXP 128 PCI_CLK

21 VDD_PCI 57 VDD 93 VDDB 129 GNT

22 DEVSEL 58 CRS 94 VSSB 130 REQ

23 STOP 59 VSSB 95 DVDDA_HR 131 VDD_PCI

24 VDD 60 COL 96 PHY_RST 132 AD31

25 PERR 61 TXD3 97 DVDDA 133 VSSB

26 SERR 62 TXD2 98 DVSSA 134 VSS

27 VSSB 63 TXD1 99 DVSSD 135 AD30

28 PAR 64 VDD 100 IREF 136 AD29

29 VDD_PCI 65 VDDB 101 DVDDD 137 AD28

30 C/BE166 TXD0 102 TX+ 138 AD27

31 AD15 67 TX_EN 103 DVDDTX 139 VDD_PCI

32 VSS 68 TX_CLK 104 TX- 140 AD26

33 AD14 69 VSSB 105 DVSSX 141 VSSB

34 AD13 70 RX_ER 106 RX+ 142 AD25

35 VSSB 71 RX_CLK 107 DVDDRX 143 AD24

36 AD12 72 RX_DV 108 RX- 144 C/BE3

Am79C978 19

PIN DESIGNATIONS (PQR160)

Listed By Pin Number

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name

1NC 41 NC 81 NC 121 NC

2NC 42 NC 82 NC 122 NC

3IDSEL 43 AD11 83 NC 123 EEDO/LED3

4AD23 44 VDD_PCI 84 NC 124 EEDI/LED0

5VSSB 45 AD10 85 VSS 125 VDDB

6AD22 46 AD9 86 RXD0 126 LED2

7VDD_PCI 47 AD8 87 RXD1 127 EESK/LED1

8AD21 48 C/BE088 VDDB 128 VSSB

9AD20 49 VSSB 89 RXD2 129 EECS

10 VDD 50 AD7 90 RXD3 130 VSS

11 AD19 51 VDD_PCI 91 MDC 131 PME

12 AD18 52 AD6 92 VSSB 132 TCK

13 VSSB 53 AD5 93 MDIO 133 TMS

14 AD17 54 VDD 94 LED4 134 VDDB

15 VDD_PCI 55 AD4 95 XCLK/XTAL 135 TDO

16 AD16 56 AD3 96 VDD 136 VSSB

17 C/BE257 VSSB 97 VSS 137 TDI

18 VSS 58 AD2 98 XTAL2 138 VDD

19 FRAME 59 VDD_PCI 99 XTAL1 139 PG

20 IRDY 60 AD1 100 VDDCO 140 INTA

21 VSSB 61 AD0 101 VSSHR 141 RST

22 TRDY 62 VSS 102 HRTRXN 142 PCI_CLK

23 VDD_PCI 63 VDD 103 VDDHR 143 GNT

24 DEVSEL 64 CRS 104 HRTRXP 144 REQ

25 STOP 65 VSSB 105 VDDB 145 VDD_PCI

26 VDD 66 COL 106 VSSB 146 AD31

27 PERR 67 TXD3 107 DVDDA_HR 147 VSSB

28 SERR 68 TXD2 108 PHY_RST 148 VSS

29 VSSB 69 TXD1 109 DVDDA 149 AD30

30 PAR 70 VDD 110 DVSSA 150 AD29

31 VDD_PCI 71 VDDB 111 DVSSD 151 AD28

32 C/BE172 TXD0 112 IREF 152 AD27

33 AD15 73 TX_EN 113 DVDDD 153 VDD_PCI

34 VSS 74 TX_CLK 114 TX+ 154 AD26

35 AD14 75 VSSB 115 DVDDTX 155 VSSB

36 AD13 76 RX_ER 116 TX- 156 AD25

37 VSSB 77 RX_CLK 117 DVSSX 157 AD24

38 AD12 78 RX_DV 118 RX+ 158 C/BE3

39 NC 79 NC 119 DVDDRX 159 NC

40 NC 80 NC 120 RX- 160 NC

20 Am79C978

PIN DESIGNATIONS (PQL144)

Listed By Group

Pin Name Pin Function Type Voltage Driver No. of

Pins

HomePNA PHY Network Ports

HRTXRXP/N Receive/Transmit Data I/O 3.3 NA 2

XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I3.3 - 1

XTAL2 Crystal Output (20 MHz XTAL) O3.3 XTAL 1

XCLK/XTAL Oscillator/Crystal Select I3.3 - 1

10BASE-T Network Ports

TX± Serial Transmit Data O3.3 NA 2

RX± Serial Receive Data I3.3 - 2

IREF Tied to GND via a 12 kΩ 1% resi stor I3.3 - 1

PHY_RST Buffe red PCI RST signal O3.3 OMII1 1

MII

TX_CLK MII Transmit Clock I3.3 - 1

TXD[3:0] MII Transmit Data O3.3 OMII1 4

TX_EN MII Transmit Enable O3.3 OMII1 1

RX_CLK MII Receive Clock I3.3 - 1

RXD[3:0] MII Receive Data I3.3 - 4

RX_ER MII Receive Error I3.3 - 1

RX_DV MII Receive Data Valid I3.3 - 1

MDC MII Management Data Clock O3.3 OMII2 1

MDIO MII Management Data I/O I/O 3.3 TSMII 1

CRS Carrier Sens e I3.3 - 1

COL Collision I3.3 - 1

Magic Packet

PME Power Management Event O3.3 OD6 1

PG Power Good I3.3 - 1

Host CPU Interface

PCI_CLK CPU Clock I3.3/5 - 1

C/BE[3:0] Bus Command Byte Enable I/O 3.3/5 TS3 4

AD[31:0] Address/Data I/O 3.3/5 TS3 32

DEVSEL Device Select I/O 3.3/5 STS6 1

FRAME Cycle Frame I/O 3.3/5 STS6 1

GNT Bus Grant I3.3/5 - 1

IDSEL Initialization Device Select I3.3/5 - 1

INTA Interrupt O3.3/5 OD6 1

IRDY Initiator Ready I/O 3.3/5 STS6 1

PAR Parity I/O 3.3/5 STS6 1

PERR Parity Error I/O 3.3/5 STS6 1

REQ Bus Request O3.3/5 TS3 1

RST Reset I3.3/5 - 1

SERR System Error I/O 3.3/5 OD6 1

Am79C978 21

Pin Name Pin Function Type Voltage Driver No. of

Pins

STOP Stop I/O 3.3/5 STS6 1

TRDY Target Ready I/O 3.3/5 STS6 1

EEPROM/LED Interface

EECS Chip Select O3.3 O6 1

EEDI/LED0 Data In/LED0 I/O 3.3 LED 1

EESK/LED1 Serial Clock/LED1 O3.3 LED 1

LED2 LED2 O3.3 LED 1

EEDO/LED3 Data Out/LED3 O3.3 LED 1

LED4 LED4 O3.3 LED 1

Test Access Port Interface (JTAG)

TCLK Test Clock I3.3 - 1

TMS Test Mode Select I3.3 - 1

TDI Test Data In I3.3 - 1

TDO Test Data Out O3.3 TS6 1

Power/Ground

DVDDTX Transceiver Digital Power P3.3 - 1

DVDDRX Transceiver Digital Power P3.3 - 1

VDD_PCI Digital power for the PCI bus P3.3 - 9

VDDB Digital power for the PCI bus P3.3 - 5

VDD Digital power P3.3 - 7

VDDHR Digital power for HomePNA PHY P3.3 - 1

DVDDA Transceiver Analo g Power P3.3 - 1

DVDDD Transceiver Digital Power P3.3 - 1

VDDCO Crystal Oscillator Power P3.3 - 1

DVDDA_HR Transceiver Analog Power P3.3 - 1

DVSSD Transceiver Digital Ground G 0 - 1

DVSSA Transceiver Analog Ground G 0 - 1

DVSSX Transceiver Ground G 0 - 1

VSSB Digital I/O Ground G 0 - 15

VSS Digital Ground G 0 - 7

VSSHR HomePNA PHY Analog Ground G 0 - 1

22 Am79C978

PIN DESIGNATIONS (PQR160)

Listed By Group

Pin Name Pin Function Type Voltage Driver No. of

Pins

HomePNA PHY Network Ports

HRTXRXP/N Receive/Transmit Data I/O 3.3 NA 2

XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I3.3 - 1

XTAL2 Crystal Output (20 MHz XTAL) O3.3 XTAL 1

XCLK/XTAL Oscillator/Crystal Select I3.3 - 1

10BASE-T Network Ports

TX± Serial Transmit Data O3.3 NA 2

RX± Serial Receive Data I3.3 - 2

IREF Tied to GND via a 12 kΩ 1% resisto r I3.3 - 1

PHY_RST Buffe red PCI RST signal O3.3 OMII1 1

MII

TX_CLK MII Transmit Clock I3.3 - 1

TXD[3:0] MII Transmit Data O3.3 OMII1 4

TX_EN MII Transmit Enable O3.3 OMII1 1

RX_CLK MII Receive Clock I3.3 - 1

RXD[3:0] MII Receive Data I3.3 - 4

RX_ER MII Receive Error I3.3 - 1

RX_DV MII Receive Data Valid I3.3 - 1

MDC MII Management Data Clock O3.3 OMII2 1

MDIO MII Management Data I/O I/O 3.3 TSMII 1

CRS Carrier Sens e I3.3 - 1

COL Collision I3.3 - 1

Magic Packet

PME Power Management Event O3.3 OD6 1

PG Power Good I3.3 - 1

Host CPU Interface

PCI_CLK CPU Clock I3.3/5 - 1

C/BE[3:0] Bus Command Byte Enable I/O 3.3/5 TS3 4

AD[31:0] Address/Data I/O 3.3/5 TS3 32

DEVSEL Device Select I/O 3.3/5 STS6 1

FRAME Cycle Frame I/O 3.3/5 STS6 1

GNT Bus Grant I3.3/5 - 1

IDSEL Initialization Device Select I3.3/5 - 1

INTA Interrupt O3.3/5 OD6 1

IRDY Initiator Ready I/O 3.3/5 STS6 1

PAR Parity I/O 3.3/5 STS6 1

PERR Parity Error I/O 3.3/5 STS6 1

REQ Bus Request O3.3/5 TS3 1

RST Reset I3.3/5 - 1

SERR System Error I/O 3.3/5 OD6 1

Am79C978 23

Pin Name Pin Function Type Voltage Driver No. of

Pins

STOP Stop I/O 3.3/5 STS6 1

TRDY Target Ready I/O 3.3/5 STS6 1

EEPROM/LED Interface

EECS Chip Select O3.3 O6 1

EEDI/LED0 Data In/LED0 I/O 3.3 LED 1

EESK/LED1 Serial Clock/LED1 O3.3 LED 1

LED2 LED2 O3.3 LED 1

EEDO/LED3 Data Out/LED3 O3.3 LED 1

LED4 LED4 O3.3 LED 1

Test Access Port Interface (JTAG)

TCLK Test Clock I3.3 - 1

TMS Test Mode Select I3.3 - 1

TDI Test Data In I3.3 - 1

TDO Test Data Out O3.3 TS6 1

Power/Ground

DVDDTX Transceiver Digital Power P3.3 - 1

DVDDRX Transceiver Digital Power P3.3 - 1

VDD_PCI Digital power for the PCI bus P3.3 - 9

VDDB Digital power for the PCI bus P3.3 - 5

VDD Digital power P3.3 - 7

VDDHR Digital power for HomePNA PHY P3.3 - 1

DVDDA Transceiver Analo g Power P3.3 - 1

DVDDD Transceiver Digital Power P3.3 - 1

VDDCO Crystal Oscillator Power P3.3 - 1

DVDDA_HR Transceiver Analog Power P3.3 - 1

DVSSD Transceiver Digital Ground G 0 - 1

DVSSA Transceiver Analog Ground G 0 - 1

DVSSX Transceiver Ground G 0 - 1

VSSB Digital I/O Ground G 0 - 15

VSS Digital Ground G 0 - 7

VSSHR HomePNA PHY Analog Ground G 0 - 1

24 Am79C978

PIN DESIGNATIONS

Listed By D river Type

The follow ing table des cribe s the vari ous typ es of out-

put drivers used in the Am79C978 controller. All IOL and

IOH values shown in the table apply to 3.3 V signaling.

A sustained tri-state signal is a low active signal that is

driven high for one clock period before it is left floating.

TX is a differential output driver. Its characteristics and

those of XTAL2 output are described in the DC CHAR-

ACTERISTICS section.

For typical 5 V DC characteristics, please refer to DC

Characteristics Over Commercial Operating Ranges

section.

Driver Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 0.4 50

O6 Totem Pole 6 0.4 50

OD6 Open Drain 6 NA 50

TS3 Tri-State 3 2 50

TS6 Tri-State 6 2 50

STS6 Sustained Tri-State 6 2 50

OMII1 Tri-State 4 4 50

OMII2 Tri-State 4 4 390

TSMII Tri-State 4 4 470

Am79C978 25

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed

by a combination of the elements below.

Am79C978

TEMPERATURE RANGE

C = Comme rcial (0° C to +70° C)

SPEED OPTION

PACKAGE TYPE

Valid Combinations list configurations planned to be

supported in volume for this device . Consult the local AMD

sales office to confirm availability of specific valid

combinations and to check on newly released

combinations.

Valid Combinatio ns

DEVICE NUMBER/DESCRIPTION

Not applicable

K = Plastic Quad Flat Pack (PQR160)

V = Thin Quad Flat Pack (PQL144)

Am79C978

PCnet-Home

Single-Chip 1/10 Mbps PCI Home Networking Controller

Valid Combinatio ns

Am79C978 KC\W

VC\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

K\V

26 Am79C978

PIN DESCRIPTIONS

PCI I nterf ace

AD[31:0]

Address and Data Input/Output

Address and data are multiplexed on the same bus in-

terface pins. During the first clock of a transaction,

AD[31:0] contain a physical address (32 bits). During

the subsequent clocks, AD[31:0] contain data. Byte or-

dering is little endian by default. AD[7:0] are defined as

the least s ignificant by te (LSB) and AD[31:2 4] are de-

fined as the most significant byte (MSB). For FIFO data

transfers, the Am79C978 controller can be pro-

grammed for big endian byte ordering. See CSR3, bit 2

(BSWP) for more details.

During the address phase of the transaction, when the

Am79C978 controller is a bus master , AD[31:2] will ad-

dress the active Double Word (DWord). The

Am79C978 controller always drives AD[1:0] to ’00’ dur-

ing the address phase indicating linear burst order.

When the Am79C978 controller is not a bus master , the

AD[31:0] lines are continuously monitored to determine

if an address match exists for slave transfers.

During the dat a phase of the tr ans acti on, AD [31: 0] ar e

driven by the Am79C978 controller when performing

bus master write and slave read operations. Data on

AD[31:0] is latched by the Am7 9C978 cont roller when

performing bus master read and slave write operations.

When RST is active, AD[31:0] are inputs for NAND tree

testing.

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the

same bus interfac e pins. During the a ddress ph ase of

the transaction, C/BE[3:0] define the bus command.

During the data phase, C/BE[3:0 ] ar e us ed as by t e en -

ables. The byte enables define which physical byte

lanes carry meaningful data. C/BE0 applies to byte 0

(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The

function of the byte enables is independent of the byte

ordering mode (BSWP, CSR3, bit 2).

When RST is active, C/BE[3:0] are inputs for NAND

tree testing.

PCI_CLK

Clock Input

This clock is used to drive the system bus interface and

the internal buffer management unit. All bus signals are

sampled on the rising edge of PCI_CLK and all param-

eters are defined with respect to this edge. The

Am79C978 controller normally operates over a fre-

quency range of 10 to 33 MHz on the PCI bus due to

networking demands. The Am79C978 controller will

support a clock frequency of 0 MHz after certain pre-

cautions are taken to ensure data in tegrity. This clock

or a derivation is not used to drive any network func-

tions.

When RST is active, PCI_CLK is an input for NAND

tree testin g.

DEVSEL

Device Select Input/Output

The Am79C978 controller drives DEVSEL LOW whe n

it detects a transaction that selects the device as a tar-

get. Th e device samples DEVSEL t o dete ct if a target

claims a transaction that the Am79C978 controller has

initiated.

When RST is active, DEVSEL is an input for NAND tree

testing.

FRAME

Cycle Frame Input/Output

FRAME is dr iven by the Am79 C978 control ler when it

is the bus master to indicate the beginning and duration

of a transac tion. FRAME is asserted to i ndicate a bus

transaction is beginning. FRAME is asserted while data

transfers continue. FRAME is deasserted before the

final data phase of a transaction. When the Am79C978

controller is in slave mode, it samples FRAME to deter-

mine the address phase of a transaction.

When RST is active, FRAME is an input for NAND tree

testing.

GNT

Bus Grant Input

This signal indicates that the access to the bus has

been granted to the Am79C978 controller.

The Am79C978 controller supports bus parking. When

the PCI bus is idle and the system arbiter asserts GNT

withou t an active REQ from th e Am79C978 controller,

the devic e will dr ive the AD[3 1:0] , C/BE[3: 0], and PAR

lines.

When RST is active, GNT is an input for NAND tree

testing.

IDSEL

Initialization Device Select

Input

This sign al is use d as a ch ip selec t for the A m79C97 8

controller during configuration read and write transa c-

tions.

When RST i s active, IDSEL is an input for NAND tree

testing.

Am79C978 27

INTA

Interrupt Request Output

An attention signal which indicates that one or more of

the following status flags is set: EXDINT, IDON, MERR,

MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,

TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE-

INT, and STINT. Ea ch sta tus flag has either a mask or

an enable bit which allows for suppression of INTA as-

sertion. Table 1 shows the flag descriptions. By default

INTA is an open-drain output. For applications that

need a high-activ e edge-sen sitive in terrupt signal, the

INTA pin can be configured for this mode by setting IN-

TLEVEL (BCR2, bit 7) to Table 1.

When RST is activ e, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready Input/Output

IRDY indicates the ability of the initiator of the transac-

tion to complete the c urrent data phase . IRDY is used

in conjunction with TRDY. Wait states are inserted until

both IRDY and TRDY are asserted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When t he Am79C97 8 controlle r is a bus m aster, it as-

serts IRDY during all write data phases to indicate that

valid data is present on AD[31 :0]. During all read dat a

phases, the device asserts IRDY to indicate that it is

ready to accept the data.

When the Am79C978 controller is the target of a trans-

action, it checks IRDY during all write data phases to

determine if valid data is present on AD[31:0]. During

all read data phases, the device checks IRDY to deter-

mine if the initiator is ready to accept the data.

When RST is active, IRDY is an input for NAND tree

testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C978 controller is a bus master , it gen-

erates parity during the address and write data phases.

It checks parity during read data phases. When the

Am79C978 controller operates in slave mode, it checks

parity during every address phase. When it is the target

of a cycle, it checks parity during write data phases and

it generates parity during read data phases.

When RST is active, PAR is an input for NAND tree

testing.

PERR

Parity Error Input/Output

During any slave write transaction and any master read

transaction, the Am79C978 controller asserts PERR

when it d etects a data parit y error and rep ortin g of the

error is enabled by setting PERREN (PCI Command

the Am79 C978 cont roller mo nitors PE RR to see if the

target reports a data parity error.

When RST is active, PERR is an i nput for NAND tree

testing.

REQ

Bus Request Input/Output

The Am79C978 controller asserts REQ pin as a signal

that it wishes to become a bus master. REQ is driven

high when the Am 79C978 controller does not request

the bus. In Power Management mode, the REQ pin wil l

not be driven.

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT Excessive

Deferral CSR5, bit 6 CSR5, bit 7

IDON Initialization

Done CSR3, bit 8 CSR0, bit 8

MERR Memory Error CSR3, bit 11 CSR0, bit 11

MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO Missed Frame

Count Over-

flow CSR4, bit 8 CSR4, bit 9

MPINT Magic Packet

Interrupt CSR5, bit 3 CSR5, bit 4

RCVCCO Receive

Collision Count

Overflow CSR4, bit 4 CSR4, bit 5

RINT Receive

Interrupt CSR3, bit 10 CSR0, bit 10

SINT System Error CSR5, bit 10 CSR5, bit 11

TINT Transmit

Interrupt CSR3, bit 9 CSR0, bit 9

TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MII

Management

Command

Complete

Interrupt

CSR7, bit 4 CSR7, bit 5

MPDTINT MII PHY Detect

Transition

Interrupt CSR7, bit 0 CSR7, bit 1

MAPINT MII Auto-Poll

Interrupt CSR7, bit 6 CSR7, bit 7

MREINT

MII

Management

Frame Read

Error Interrupt

CSR7, bit 8 CSR7, bit 9

STINT Software Timer

Interrupt CSR7, bit 10 CSR7, bit 11

28 Am79C978

When RST is active, REQ is an input for NAND tree

testing.

RST

Reset Input

When RST is asser ted LOW and the PG pi n is HIGH,

then the Am79C978 controller performs an internal

system reset of the type H_RESET

(HARDWARE_RESET, see section on RESET). RST

must be held for a minimum of 30 clock periods. While

in the H_RESET state, the Am79C978 controller will

disable or deassert all outputs. RST may be asyn ch ro -

nous to clock when asserted or deasserted.

When the P G pin is LO W, RST d isables all of th e PCI

pins except the PME pin.

When RST is LOW and PG is HIGH, NAND tree testing

is enabled.

SERR

System Error Output

During any slave transaction, the Am79C978 controller

asse rts SE RR when it d etects an ad dres s parit y e rror,

and reporting of the error is enabled by setting PER-

REN (PCI Command register , bit 6) and SERREN (PCI

Command register, bit 8) to 1.

By default SERR is an open-drain outp ut. For compo-

nent test, it can be programmed to be an active-high

totem-pole output.

When RST is active, SERR is a n input for NAND tre e

testing.

STOP

Stop Input/Output

In slave mode, the Am79C978 controller drives the

STOP si gnal to i nform the bus maste r to stop th e cur-

rent transaction. In bus master mode, the Am79C978

controller checks STOP to determine if the target wants

to disconnect the current transaction.

When RST is a ctive, STOP is an input for NAND tree

testing.

TRDY

Target Ready Input/Output

TRDY indica tes the abili ty of the target of the tran sac-

tion to complete the current data phase. Wait states are

inserted until both IRDY and TRDY are asserted simul-

taneously. A data phase is completed on any clock

when both IRDY and TRDY are asserted.

When the Am79C978 controller is a bus master, it

checks TRDY during all read data phases to determine

if valid data is present on AD[31:0]. During all write data

phases, the device checks TRDY to determine if the

target is ready to accept the data.

When the Am79C978 controller is the target of a trans-

action, i t asserts TRD Y during all r ead data ph ases to

indicat e that valid da ta is presen t on AD[31:0]. Durin g

all write data phases, the device asserts TRDY to indi-

cate that it is ready to accept the data.

When RST is active, TRDY is an input for NAND tree

testing.

Magic Packet Interface

PME

Power Management Event Output, Open Drain

PME is an output that can be used to indicate that a

power management event (a Magic Packet, an OnNow

pattern ma tch, or a cha nge in link sta te) has been de-

tected. The PME pin is asserted when either

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1.

The PME signal is asynchronous with respect to the

PCI cl oc k. See t he Power Saving Mode section for de-

tailed descripti on.

Power Good Input

The PG pin has two functions: (1) it puts the device into

Magic Pac ket mode, and (2) it bloc ks any rese ts whe n

the PCI b us power is off.

When PG is LOW and either MPPEN or MPMODE is

set to 1, the device enters Magic Packet mode.

When PG is LOW , a LOW assertion of the PCI RST pin

will only cause the PCI interface pins (except for PME)

to be put in the high impedance state. The internal logic

will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin

causes the controller logic to be reset and the configu-

ration information to be loaded from the EEPROM.

Note: PG input should be kept high during NAND tree

testing.

Board Interf ac e

Note: Before programming the LED pins, see the

description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By de-

fault, LED0 indicates an active link connection. This pin

can also be programmed to indicate other network sta-

tus (see BCR4). The LED0 pin polarity is programma-

ble, but by default it is active LOW . When the LED0 pin

polarity is programmed to active LOW, the output is an

open drain driver. When the LED0 pin polarity is pro-

Am79C978 29

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

LED1

LED1 Output

Thi s outp ut is desi gned to dire ctly dr ive a n LED. By de-

fault, LED1 indicates receive activity on the network.

This pin can also be programmed to indicate other net-

work status (see BCR5). The LED1 pin pola rity is pro-

grammab le, bu t b y defa ul t, it is ac ti ve L OW. When th e

LED1 pin polarity is programmed to active LOW, the

output is an op en dr ai n d rive r. When th e L ED1 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Note: The LED1 pin is m u lt i pl ex e d wi t h t h e EES K p i n.

The LED1 pin is also used during EEPROM Auto-

Detection to determin e whether or not an EEPROM is

present at the Am79C978 controller interface. At the

last rising edge of CLK while RST is active LOW , LED1

is sam pled to deter mine the va lue of the EE DET bi t in

BCR19. It is important to maintain adequ ate hold time

around the rising edge of the CLK at this time to ensure

a correctly sampled value. A sampled HIGH value

means that an EEPROM is present, and EEDET will be

set to 1. A sampled LOW value means that an EE-

PROM is not present, and EEDET will be set to 0. See

the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull-

up or pull-down resistor must be attached in order to

select the EEDET setting.

WARNING: The input si gna l l ev el o f LE D1 m us t be in-

sured for correct EEPROM de tection befo re the deas-

sertion of RST.

LED2

LED2 Output

This output is designed to directly drive an LED. This

pin can be programmed to indicate various network

status ( see BC R6). The L ED2 pin polarity i s program-

mable, but by default it is active LOW . When the LED2

pin polarity is programmed to active LOW , the output is

an open drain driver . When the LED2 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

LED3

LED3 Output

Thi s outp ut is desi gned to dire ctly dr ive a n LED. By de-

fault, LED3 indicates transmit activity on the network.

This pin can also be programmed to indicate other net-

work status (see BCR7). The LED3 pin pola rity is pr o-

grammable, but by default it is active LOW. When the

LED3 pin polarity is programmed to active LOW, the

output is an op en dr ai n d rive r. When th e L ED3 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Special attention must be given to the external circuitry

attached to this p in. When th is pin i s us ed to drive an

LED while an EEPROM is used in the system, then

buffering may be required between the LED3 pin and

the LED circuit. If an LED circuit were directly attached

to this pin, it may create an IOL require men t that could

not be met by the serial EEPROM attached to this pin.

If no EEPRO M is inc lu ded in t he s ystem des i gn or lo w

current LEDs are used, then the LED3 signal may be

directly connected to an LED without buffering. For

more details regarding LED connection, see the sec-

tion on LED Support.

Note: The LED3 pin is multiplexed with the EEDO pin.

LED4

LED4 Output

This output is designed to directly drive an LED. This

pin can be programmed to indicate various network

status (see BCR48). The LED4 pin polar ity is program -

mable, but by default it is active LOW . When the LED4

pin polarity is programmed to active LOW , the output is

an open drain driver . When the LED4 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

EEPROM Interface

EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EE-

PROM that uses th e 93C46 EEP ROM i nterface p roto-

col. EECS is connected to the EEPROM’s chip select

pin. It is controlled by either the Am79C978 controller

during command portions of a read of the entire EE-

PROM, or indirectly by the host system by writing to

BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EEDI is conn ected to the EE PROM’s data input

pin. It is controlled by either the Am79C978 controller

during command portions of a read of the entire

EEPROM, or indirectly by the host system by writing to

BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

EEDO

EEPROM Data Out Input

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EE DO is conn ected to the EEPROM ’s data out-

put pin. It is controlled by either the Am79C978

30 Am79C978

controller during command portions of a read of the en-

tire EEPROM, or indirectly by the host system by read-

ing from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3 pin.

EESK

EEPROM Serial Clock Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. E ESK is con nected to the E EPRO M’s clock pin.

It is controlled by either the Am79C978 controller di-

rectly during a read of the entire EEPROM, or indirectly

by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 pin.

The EESK pin is also used during EEPROM Auto-

Detection to determin e whether or not an EEPROM is

present at the Am79C978 controller interface. At the

rising edge of the last CLK edge while RST is asserted,

EESK is sampled to determine the value of the EEDET

bit in BCR19. A sampled HIGH value means that an

EEPROM is present, and EEDET will be set to 1. A

sampled LOW value means that an EEPROM is not

present, and EEDET will be set to 0. See the EEPROM

Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull-

up or pull-down resistor must be attached instead to re-

solve the EEDET setting.

WARNING: The input signal level of EESK must be

valid for correct EEPROM detection before the deas-

sertion of RST.

MII Interface

RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing refer-

ence for the transfer of the RX_DV, RXD[3:0], and

RX_ER signals into the Am79C978 device. RX_CLK

must provide a nibble rate clock (25% of the network

data rate). Hence, when the Am79C978 device is oper-

ating at 10 Mbps , it provides an RX_ CLK freq uency of

2.5 MHz, and at 100 Mbp s i t prov id es an RX _CLK fr e-

quency of 25 MHz.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII-compatible receive

data bus. Data on RXD[3:0] is sampled on every rising

edge of RX_CLK while RX_DV is asserted. RXD[3:0] is

ignored while RX_DV is de-asserted.

RX_DV

Receive Data Valid Input

RX_DV i s an inpu t used t o indic ate that va lid rec eive d

data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. In order

for a frame to be fully received by the Am79C978 de-

vice, RX_DV must be asserted prior to the RX_CLK ris-

ing edge, when the first nibble of the Start of Frame

Delimiter is driven on RXD[3:0], and must remain as-

serted u ntil aft er the r isi ng e dge of RX _CLK , wh en th e

last nibble of the CRC is driven on RXD[3:0]. RX_DV

must then be deasserted prior to the RX_CLK rising

edge which follows this final nibble. RX_DV transitions

are synchronous to RX_CLK rising edges.

CRS

Receive Carrier Sense Input

CRS is an input that indicates that a non-idl e medium,

due either to transmit or recei ve activity, has bee n de-

tected.

COL

Collision Input

COL is an input that indicates that a collision has been

detected on the network medium.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII trans-

ceiver device has detected a coding error in the receive

data frame currently being transferred on the RXD[3:0]

pins. If RX_ER is asserted while RX_DV is asserted, a

CRC error will be indicated in the receive descriptor for

the incoming receive frame. RX_ER is ignored while

RX_DV is deass er te d. Sp ec ial code group s gen er ate d

on RXD while RX _DV is de asse rted a re igno red (e.g .,

bad SSD in T X and idle in T 4). RX_ER tran sitions ar e

synchronous to RX_CLK.

TX_CLK

T ransmit Clock Input

TX_CLK is a clo ck in put t hat p ro vides th e tim in g r efer-

ence for the transfer of the TXD[3:0] and TX_ER sig-

nals into the Am79C978 device. TX_CLK must provide

a nibble rate clock (25% of the network data rate).

Hence, when the Am79C978 device is operating at 10

Mbps, it provides an TX_CLK frequency of 2.5 MHz,

and a t 100 Mb ps it p rovides a n RX_CLK frequen cy of

25 MHz.

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII-compatible transmit

data bus. V alid data is generated on TXD[3:0] on every

rising edge of TX_CLK while TX_EN is asserted. While

TX_EN is deasserted, TXD[3:0] values are driven to 0.

TXD[3:0] transitions are synchronous to rising edges of

TX_CLK.

Am79C978 31

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C978 device is pre-

senting va li d tra ns mit n ibbles on the MII TX D[3:0 ] bus .

While TX _EN is assert ed, the Am79C9 78 device gen-

erates TX D[3:0] and TX_ER on TX _CLK risin g edges .

TX_EN is asserted with the first nibble of preamble and

remains asserted throughout the duration of the packet

until it is deasserted prior to the first TX_CLK following

the final nibble of the frame. TX_EN transitions are syn-

chronous to TX_CLK.

MDC

Management Data Clock Output

MDC is the no n-continuous c lock output that pr ovides

a timing reference for bits on the MDIO pin. During MII

managemen t port operations, MDC runs at a nominal

frequency of 2.5 MHz. When no management opera-

tions are in progress, MDC is driven LOW.

If the MII port is no t s ele cte d, the MDC pi n m ay be le ft

floating.

MDIO

Management Data Input/Output Input/

Output

MDIO is a bidirectional MII management port data pin.

MDIO is an output during the header portion of the

managemen t frame transfer s and during the data por-

tion of write operations. MDIO is an input during the

data portion of read operations.

If a PHY is attached to the MII port via a MII physical

connector then the MDIO pin should be externally

pulled down to Vss with a 10 kΩ ±5% resistor. If a PHY

is directly attached to the MII pins then the MDIO pin

should be externally pulled up to Vcc with a 10 kΩ ±5%

resistor.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

Test Clock Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull-up resistor.

TDI

Test Data In Input

TDI is the test data input pat h to the Am79C978 con-

troller. The pin has an internal pull-up resistor.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C978

controller . The pin is tri-stated when the JT AG port is in-

active.

TMS

Test Mode Select Input

A ser ial i np ut bit str eam o n t he T MS pin is u se d to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull-up resistor.

Ethernet Network Interfaces

TX±

Serial Transmit Data Output

These pins carry the transmit output data and are con-

nected to the transmit side of the magnetics module.

RX±

Serial Receive Data Input

These pins accept the receive input data from the mag-

netics module .

IREF

Internal Current Reference Input

This pin serves as a current reference for the inte-

grated 1/10 PHY. It must be connected to VSS through

a 12100-Ω resistor (1%).

PHY_RST

PHY Reset Output

This output is used to reset the external PHY. This out-

put elim inates the ne ed for a fano ut buffer on the PC I

reset (RST) signal, provided polarity control for the

specific PHY used, and prevents the resetting of the

PHY whe n the PG in put i s LO W. The output polar ity is

determined by the RST_POL (CRS116, bit0).

HomePNA PHY Network Interface

HRTXRXP/HRTXRXN

Serial Receive Data Input/Output

These pins accept the receive input data from the mag-

netics module and carry the transmit output data. A

102-Ω resistor should be placed between these pins.

Clock Interfac e

XCLK/XTAL

External Clock/Crystal Select Input

When HIGH, an external 60-MHz clock source is se-

lected bypassing the crystal circuit and clock trippler.

When LOW, a 20-MHz crystal is used instead. The fol-

lowing table illustrates how this pin works.

32 Am79C978

Table 2. External Clock/Crystal Select

XTAL1

Crystal Oscillator In Input

The internal clock generator utilizes either a 20-MHz

cryst al that is atta ched to pins XTAL 1 and XTAL2 o r a

60-MHz c lock source co nnected to XTAL1. T his pin is

not 5 V tolerant, and the 60 MHz clock source must be

from a 3.3 V source.

XTAL2

Crystal Oscillator Out Output

The internal clock generator utilizesd a 20-MHz crystal

that is attached to pins XTAL1 and XTAL2.

Power Supply

VDDB

I/O Buffer Power (5 Pins) +3.3 V Power

These pins are the power supply pins that are used by

the input/out put buffer drivers. Al l VDDB pins must be

connected to a +3.3 V supply.

VDD_PCI

PCI I/O Buffer Power (9 Pins) +3.3 V Power

These pins are the power supply pins that are used by

the PCI input/output buffer drivers (except PME driver).

All VDD_P CI pi ns m us t be connecte d to a +3.3 V su p-

ply.

VSSB

I/O Buffer Ground (15 Pins) Ground

These pins are the ground pins that are used by the

input/output buffer drivers.

VDD

Digital Power (7 Pins) +3.3 V Power

These pins are the power supply pins that are used by

the inte rnal digital circui try. A ll VDD pins m ust b e co n-

nected to a +3.3 V supply.

VSS

Digital Ground (7 Pins) Ground

There are seven ground pins that are used by the inter-

nal digital circuitry.

DVDDD

10BASE-T PDX B lock Po wer +3.3 V Power

This pin supplies power to the 10 Mbps Transceiver

block. It must be connected to a +3.3 V ±300 mV

source . This pin requ ires c aref ul de coupl ing to e nsure

proper device performance.

DVDDRX, DVDDTX

10BASE-T I/O Buffer Power +3.3 V Power

These pins supply power to the 10BASE-T input/output

buffers. They must be connected to a +3.3 V ±300 mV

source. These pins require careful decoupling to en-

sure proper device performance.

DVDDA

Analog PLL Power +3.3 V Power

This pin suppli es power to the IR EF curren t referenc e

circuit and the 10BASE-T analog PLL. They must be

connected to a +3.3 V ±300 mV source. These pins re-

quire careful decoupling to ensure proper device per-

formance.

DVSSX, DVSSA

10BASE-T PDX Analog Ground Ground

These pins are the ground connection for the analog

section within the Physical Data Transceiver (PDX)

block.

DVSSD

10BASE-T PDX Digital Ground Ground

This pin is the ground connection for the digital logic

within the PDX block.

VDDCO

Crystal +3.3 V Power

This pin supplies power to the crystal circuit.

VDDHR

HomePNA Digital Power +3.3 V Power

These pins are the digital power supply pins that are

used by the internal digital circuitry for the HomePNA

block. They must be connected to a +3.3 V source.

VSSHR

HomePNA Analog Ground Ground

This pin is the ground connection for the analog section

within the HomePNA block.

DVDDA_HR

HomePNA Analog Power +3.3 V Power

This pin supplies power to the analog section of the

HomePNA block. It must be connected to a +3.3 V

±300 mV source. T his pin requ ires care ful decoupl ing

to ensure proper device performance.

Input Pin Output

Pin XCLK/XTAL Clock Source

XTAL1 XTAL2 0 20-MHz Crystal

XTAL1 Don’t Care 1 60-MHz Oscillator/

External CLK

Source

Am79C978 33

BASIC FUNCTIONS

System Bus Interface

The Am 79C978 co ntroller is desi gned to o perate as a

bus maste r during norma l operations. Some slave I/O

accesses to the Am79C978 controller are required in

normal operations as well. Initialization of the

Am79C978 controller is achieved through a combina-

tion of PCI Configuration Space accesses, bus slave

access es, bus mas ter a ccess es, a nd an optio nal rea d

of a serial EEPROM that is performed by the

Am79C978 c ontr ol le r. The EEPROM read operatio n is

performed through the 93C46 EEPROM interface. The

ISO 8802- 3 (IEEE/A NSI 802.3) Ethernet Add ress may

reside within the serial EEPROM. Some controller con-

figuration registers may also be programmed by the

EEPROM read operation.

The Address PROM, on-chip board-configuration reg-

isters, and the Ethernet contr oller register s occup y 32

bytes of address space. I/O and memory mapped I/O

accesses are supported. Base Address registers in the

PCI configuration space allow locating the address

space on a wide variety of starting addresses.

Softw are Interface

The software interface to the Am79C978 controller is

divided int o thr ee par ts . One p ar t is the PCI con f ig ura-

tion registers used to identify the Am79C978 controller

and to setup the configuration of the device. The setup

information includes the I/O or memory mapped I/O

base address, mapping of the Expansion ROM, and

the routi ng of th e A m7 9C97 8 c ont ro ller in ter rupt cha n -

nel. This allows for a jumperless implementation.

The secon d portion of the s oftware interfac e is the di-

rect access to the I/O resources of the Am79C978 con-

troller. The A m79C978 con troll er occ upies 32 by tes o f

address space that must begin on a 32-byte block

boundary. T he addres s spa ce can be ma pped int o I/O

or memory space (memory mapped I/O). The I/O Base

Addres s Regi st er in the PC I Configur ati on S pa ce co n-

trols the start address of the address space if it is

mapped to I /O space. The Me mory Mapped I/O Base

Addres s Register controls the star t address of the a d-

dress spa ce if it i s mapp ed to memo ry space. T he 32-

byte address space is used by the software to program

the Am79C978 controller operating mode, to enable

and disa ble v ar iou s feat ur es, to monitor oper a ting s ta-

tus, and t o requ est pa rticul ar functi ons to be exec uted

by the Am79C978 controller.

The third portion of the software interface is the de-

scriptor and buffer areas that are shared between the

software and the Am79C978 controller during normal

network operations. The descriptor area boundaries

are set by the s oftwar e and do no t change dur ing nor-

mal network operations. There is one descriptor area

for receive activity, and there is a separate area for

transmit activity . The descriptor space contains relocat-

able poin ters to t he network frame da ta, and it is used

to trans fer fr am e s tat us from the Am 79C9 78 c on tr oll er

to the software. The buffer areas are locations that hold

frame data for transmission or that accept frame data

that has been received.

Network Interfaces

The Am79C978 controller provides all of the PHY layer

functions for 10 Mbps (10BASE-T) or 1 Mbps. The

Am79C978 controller supports both half-duplex and

full-duplex operation on the network MII interface.

Media Independent Interface

The Am79C978 controller fully supports the MII ac-

cordin g to the IE EE 80 2.3u sta ndard. This Recon cilia-

tion Sublayer interface allows a variety of PHYs

(100BASE-TX, 100BASE-FX, 100BASE-T4,

100BASE-T2, 10BASE-T, etc.) to be attached to the

Am79C978 device without future upgrade problems.

The MII interface is a 4-bit (nibble) wide data path inter-

face that runs at 25 MHz for 100-Mbps networks or 2.5

MHz for 10-Mbps networks. The interface consists of

two independent data paths, receive (RXD(3:0)) and

transmit ( TXD(3:0 )), con trol sig nals fo r each dat a path

(RX_ER, RX_DV, TX_EN), network status signals

(COL, CRS), clocks (RX_CLK, TX_CLK) for each data

path, and a two-wire management interface (MDC and

MDIO). See Figure 2.

MII Transmit Interface

The MII transmit clock is generated by the external

PHY and is sent to the Am79C978 controller on the

TX_CLK input pin. The clock can run at 25 MHz or 2.5

MHz, dep end ing on th e s pe ed of the ne twor k to which

the external PHY is attached. The data is a nibble-wide

(4 bits) data path, TXD( 3:0), from the Am79C9 78 con-

troller to the external PHY and is synchronous to the

rising edge of TX_CLK. The transmit process starts

when the Am79C978 controller asserts the TX_EN,

which indicates to the external PHY that the data on

TXD(3:0) is valid.

Normally, unrecoverable errors are signaled through

the MII to the external PHY with the TX_ER output pin.

The external PHY will respond to this error by generat-

ing a TX coding error on the current transmitted frame.

The Am79C978 controller does not use this method of

signaling errors on the transmit side. The Am79C978

controller will invert the FCS on the last byte generating

an in val id FC S. The TX_E R pi n sh oul d be tied to GND .

34 Am79C978

Figure 1. Media Independent Interface

MII Receive Interf ace

The MII receive clock is also generated by the external

PHY and is sent to the Am79C978 controller on the

RX_CLK input pin. The clock will be the same fre-

quency as the TX_CLK but will be out of phase and can

run at 25 MHz o r 2.5 MHz , de pen di ng o n th e s pe ed o f

the network to which the external PHY is attached.

The RX_CLK is a continuous clock during the reception

of the frame, but can be stopped for up to two RX_CLK

periods at the beginning and the end of frames, so that

the external PHY can sync up to the network data traffic

necessary to recover the receive clock. During this

time, the external PHY may switch to the TX_CLK to

maintain a stable clock on the receive interface. The

Am79C978 controller will handle this situation with no

loss of data. The data is a nibble-wide (4 bits) data

path, RXD(3:0), from the external PHY to the

Am79C9 78 control ler and is synchron ous to the rising

edge of RX_CLK.

The receive process starts when RX_DV is asserted.

RX_DV will remain asserted until the end of the receive

frame. The Am79C978 controller requires CRS (Car-

rier Sen se) to to ggle in betwe en frame s in order to re-

ceive them properly. Errors in the currently received

frame are signaled across the MII by the RX_ER pin.

RX_ER can be used to signal special conditions out of

band when RX_DV is not asserted. T wo defined out-of-

band conditions for this are the 100BASE-TX signaling

of bad Start of Frame Delimiter and the 100BASE-T4

indicati on of illegal cod e gr oup be fore the r ec eiver has

synched to the incoming data. The Am79C978 control-

ler will not r es po nd to thes e cond iti ons . A ll out o f ban d

conditions are currently treated as NULL events.

MII Network Status Interface

The MII also provides signals that are consistent and

necessar y for IEEE 802.3 and IEE E 802.3u opera tion.

These signals are CRS (Carrier Sense) and COL (Col-

lision Sense). Car rier Sens e is us ed to detect non -idl e

activity on the network. Collision Sense is used to indi-

cate that s imulta neous tra nsmi ssion has oc curre d in a

half-duplex network.

MII Management Interface

The MII prov ides a two-wire manage ment int erface s o

that the Am79C978 controller can control and receive

status from external PHY devices.

The Network Port Manager copies the PHY AD after the

Am79C978 controller rea ds the EEPROM and uses it

to communicate with the external PHY. (Refer also to

the BCR49 description). The PHY address must be

programmed into the EEPROM prior to starting the

Am79C978 controller. This is necessary so that the in-

ternal management controller can work autonomously

from the software driver and can always know where to

access the exter nal PHY. The A m79C978 con troller is

unique by offering direct hardware support of the exter-

nal PHY device without software support. The PHY ad-

dress of 1Fh is reserved and should not be used. To

access the internal or external PHYs, the software

driver mu st hav e knowl edge of th e PHY’s a ddres s be-

fore attempti ng to addres s it.

The MII Management Interface uses the MII Control,

Address, and Data registers (BCR32, 33, 34) to control

and communicate to the external PHYs. The

Am79C978 controller generates MII management

frames to the external PHY through the MDIO pin syn-

chronous to the rising edge of the Management Data

Clock (MDC) based on a combination of writes and

reads to these registers.

4RXD(3:0)

RX_DV

RX_ER

RX_CLK

4TXD(3:0)

TX_EN

Am79C978

MII Interface

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

22206B-4

Am79C978 35

MII Management Frames

MII management frames are automatically generated

by the Am79C978 controller and conform to the MII

clause in the IEE E 802. 3u stan dar d.

The start of the frame may be a preamble of 32 ones

(unless b it 6 of regis ter equals 1) and guar antees tha t

all of the external PHYs are synchronized on the same

interface. See Figure 2. Loss of synchronization is pos-

sible due to t he hot-plugging ca pabil ity of the expo sed

MII.

The IEEE 802.3 specification allows you to drop the

preambl e, if after re ading the MII Status Register from

the external PHY you can d etermine that the external

PHY will support Preamble Suppression (BCR34, bit

6). After having a valid MII Status Register read, the

Am79C 978 cont roller will then dro p the creati on of the

preamble stream until a reset occurs, rece ives a read

error, or the external PHY is disconnected.

Figure 2. Frame Format at the MII Interface Connection

This is followed by a start field (ST) and an operation

field (OP). The operation field (OP) indicates whether

the Am79C978 controller is initiating a read or write op-

eration. This is followed by the external PHY address

(PHYAD) and the register address (REGAD) pro-

grammed in BCR33 . The PHY add ress of 1 D,1E, and

1F are r es erv ed and s hou ld no t b e u se d. Th e exter nal

PHY may hav e a larger address space star ting at 10h

- 1Fh. This is the address range set aside by the IEEE

as vendor usable address space and will vary from

vendor to vendor. This field is followed by a bus turn-

around field. During a read operation, the bus turn-

around field is used to determine if the external PHY is

responding correctly to the read request or not. The

Am79C978 controller will tri-state the MDIO for both

MDC cycles.

During the second cycle, if the external PHY is syn-

chronized to the Am79C978 controller, the external

PHY will drive a 0. If the external PHY does not drive a

0, the Am79C978 controller will signal a MREINT

(CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set

to a 1, indicati ng the Am79C978 contr oller had an MII

management frame read error and that the data in

BCR34 is not va lid. The data field to/from the exter nal

PHY is read or written into the BCR34 register . The last

field is an IDLE field that is necessary to give ample

time for drive rs to t urn o ff before t he next acces s. Th e

Am79C978 controller will drive the MDC to 0 and tri-

state the MDIO anytime the MII Management Port is

not active.

To help to speed up the read ing and o f writing the MII

management frames to the external PHY, the MDC can

be sped up to 5 MHz by setting the FMDC bits in

BCR32. The IEEE 802.3 specification requires use of

the 2.5-MH z c lo ck r ate, b ut 5 M H z is als o av aila bl e for

the user. The 5 -MHz c lock rate ca n be used for a n ex-

posed MII with one external PHY attached. The 2.5-

MHz clock rate is intended to be used when multiple

external PHYs are connect ed to the MII Management

Port or if compliance to the IEEE 802.3u standard is re-

quired.

Auto-Poll External PHY Status Polling

As defined in the IEEE 802.3 standard, the external

PHY attached to the Am79C978 controller’s MII has no

way of communicating important timely status informa-

tion back to Am79C978 controller. The Am79C978

controller has no way of knowing that an external PHY

has undergone a change in status without polling the

MII status register. To prevent problems from occurring

with inadequate host or software polling, the

Am79C978 controller will Auto-Poll when APEP

(BCR32, b it 11) is set to 1 to insure that the mos t cur-

rent information is available. See 10BASE-T PHY Man-

agement Registers for the bit descriptions of the MII

Status Register. The contents of the latest read from

the extern al PHY wil l be store d in a sha dow regist er in

the Auto-Poll block. The first read of the MII Status

be compared to the contents already stored in the

shadow register . If there has been a change in the con-

tents of the MII Status Register, a MAPINT (CSR7, bit

5) interru pt will be genera ted on INTA if the MA PINTE

(CS R7, b it 4 ) is s et t o 1. Th e A ut o -P ol l f e atu r e s ca n be

disabled if software driver polling is required.

Preamble

1111....1111 OP

10 Rd

01 Wr

PHY

Address Register

Address TA

Z0 Rd

10 Wr Data

Bits

Bits 16

Bits 1

Bit

Idle

22206B-5

36 Am79C978

The Auto-Poll’s frequency of generating MII manage-

ment frames can be adjusted by settin g of the APDW

bits (BCR32, bits 10-8). The delay can be adjusted

from 0 MDC periods to 2048 MDC periods. Auto-Poll

by default will only read the MII Status register of the

currently active PHY.

Network Port Manager

If the PHY i s ac tive, the Net w ork Po rt Ma nag er wi ll r e-

quest status from the selecte d PHY by generat ing MII

management frames. These frames will be sent

roughly every 900 ms. These frames are necessary so

that the Network Port Manager can monitor the current

active link and can notify the software if the current link

goes down.

10BASE-T PHY

The 10BASE-T transceiver incorporates the physical

laye r function, i ncluding both clock recovery (ENDEC)

and transceiver function. Data transmission over the

10BASE-T medium requires an integrated 10BASE-T

MAU. The transceiver will meet the electrical require-

ments for 10BASE-T as s pecified in IEE E 802.3i. The

transmit signal is filtered on the transceiver to reduce

harmonic content per IEEE 802.3i. Since filtering is

perform ed in si licon, e xternal fil tering modules a re not

needed. The 10BASE-T PHY transceiver receives 10

Mbps data from the MAC across the internal MII at 2.5

million nibbles per second (parallel), or 10 million bits

per second (serial) for 10BASE-T. It then Manchester

encodes the data before transmission to the network.

The RX+ pins are differential twisted-pair receivers.

When prope rly termi nated, eac h receiver will meet the

electrical requirements for 10BASE-T as specified in

IEEE 802.3i. Each receiver has internal filtering and

does not require external filter modules. The

10BASE-T PHY transceiver receives a Manchester

coded 10BASE-T data stream from the medium. It then

recovers the clock and decodes the data. The data

stream is presented at the internal MII interface in par-

allel format.

PCI and JTAG Configuration Information

The PCI device ID and software configuration informa-

tion is as follows in Table 3 and Table 4.

Table 3. PCI Device ID

Table 4. PCI Software Configuration

Slave Bus Interface Unit

The slave Bus Interface Unit (BIU) controls all ac-

cesses to the PCI configuration space, the Control and

Status Regi sters (CSR) , the B us Configuration Regis-

ters (BCR), and the Address PROM (APROM) loca-

tions. Table 5 shows the response of the Am79C978

controller to each of the PCI commands in slave mode.

Table 5. Slav e Commands

Slave Configuration Transfers

The hos t can ac cess the P CI con figur ation s pace wit h

a configuration read or write command. The

Am79C978 controller will assert DEVSEL during the

address phase when IDSEL is asserted, AD[1:0] are

both 0, and the access is a configuration cycle. AD[7:2]

select the DWord location in the configuration space.

The Am79C978 controller ignores AD[10:8], because it

Vendor ID Device ID Rev ID (offset 0x08)

1022 2001 51

CSR89 CSR88 JTAG

00001262h 00006003h 1262 6003h

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Read of CSR, BCR, APROM,

and Reset registers

0011 I/O Write Write to CSR, BCR, and

APROM

0100 Reserved

0101 Reserved

0110 Memo ry Read

Memory mapped I/O read of

CSR, BCR, APROM, and

Reset registers. Read of the

Expansion Bus

0111 Memory Write Memory m apped I/O writ e o f

CSR, BCR, and APROM

1000 Reserved

1001 Reserved

1010 Configuration

Read Read of the Configuration

Space

1011 Configuration

Write Write to the Configuration

Space

1100 Memory Re ad

Multiple Aliased to Memory Read

1101 Dual Address

Cycle Not used

1110 Memory Read

Line Aliased to Memory Read

1111 Memory Write

Invalidate Alia sed to Memory Writ e

Am79C978 37

is a single function device. AD[31:11] are “don't cares.”

See Table 6.

Table 6. Slave Configuration Transfers

The active bytes within a DWord are determined by the

byte enabl e signals. Eight- bit, 16-bit, and 32-bi t trans-

fers are su pported. DE VSEL is asserte d two clock cy -

cles after the host has asserted FRAME. All

configuration cycles are of fixed length. The

Am79C978 controller will assert TRDY on the third

clock of the data phase.

The Am79C978 controller does not support burst trans-

fers for access to configuration space. When the host

keeps FRAME asserted for a second data phase, the

Am79C978 controller will disconnect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET (see section on RESET) is on-going, the

Am79C978 controller will terminate the access on the

PCI bus with a disconnect/retry response.

The Am79C978 controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register , bit

7), which is hardwired to 1. The Am79C978 controller

is capable of detecting a configuration cycle even when

its addr ess phase immed iately follo ws the data phas e

of a transaction to a different target without any idle

state in-between. There will be no contention on the

DEVSEL, TRDY, and STOP signals, since the

Am79C978 controlle r asserts DEVSEL on the secon d

clock after FRAME is asserted (medium timing).

Slave I/O Transfers

After the A m79C978 con troller is configur ed as an I/O

device by setting IOEN (for regular I/O mode) or

MEMEN (for memory mapped I/O mode) in the PCI

Command re giste r, it star ts monitor ing the PCI bus for

access to its CSR, BCR, or EEPROM locations. If con-

figured for regu la r I /O mo de, the Am7 9C9 78 c on tr oll er

will look for an address that falls within its 32 bytes of I/

O addre ss s pac e ( star ti ng fr om the I/O base add re ss ).

The Am79C978 controller asserts DEVSEL if it detects

an address match and the access is an I/O cycle. If

configured for memory mapped I/O mode, the

Am79C 978 cont roller will look fo r an addres s that falls

within its 32 bytes of memory address space (starting

from the memory mapped I/O base address). The

Am79C978 controller asserts DEVSEL if it detects an

address match and the access is a memory cycle.

DEVSEL is asserted two clock cycles after the host has

asser ted F RA ME. See Figure 3 and Figure 4.

The Am79C978 con troller will not assert DEVSEL if it

detects an address match and the PCI command is not

of the c orrect type. In memory mapped I/O mo de, the

Am79C978 controller aliases all accesses to the I/O re-

source s of t he c om man d t ype s Memor y Read Multipl e

and Memory Read Line to the basic Memory Read com-

mand. All accesses of the type Memo ry Write and In-

validate are aliased to the basic Memory Write

command. Eight-bit, 16-bit, and 32-bit non-burst trans-

actions are supported. The Am79C978 controller de-

codes all 32 address lines to determine which I/O

resource is accessed.

The typical number of wait state s added to a slave I/O

or memory mapped I/O read or write access on the part

of the Am79C978 controller is six to seven clock cycles,

depending upon the relative phases of the internal Buff-

er Management Unit clock and the CLK signal, since

the intern al Buffer M anagement Unit cloc k is a divide-

by-two version of the CLK signal.

The Am79C978 controller does not support burst trans-

fers for access to its I/O resources. When the host keeps

FRAME asserted for a second data phase, the

Am79C978 controller will disconnect the transfer.

The Am79C978 controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register , bit

7), whi ch is hardw ired to 1. T he Am79C97 8 controller

is capabl e of detecting an I/O or a mem ory-mapped I/

O cycle ev en when its address phase immedi ately fol-

lows the data phase of a transaction to a different target,

without any idle state in-between. There will be no con-

tention on the DEVSEL, TRDY , and STOP signals, since

the Am79C978 controller asserts DEVSEL on the sec-

ond clock after FRAME is asserted (medium timing).

See Figure 5 and Figure 6.

AD31

AD11 AD10

AD8 AD7

AD2 AD1 AD0

Don’t care Don’t care DWord

Index 00

38 Am79C978

Figure 3. Slave Configuration Read Figure 4. Slave Configuration Write

Figure 5. Slave Read Using I/O Command

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1010

PAR PAR PAR

DEVSEL is sampled

DATA

ADDR

22206B-6

22206B-7

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1011

PAR PAR PAR

DATA

ADDR

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0010

PAR

1 2345678 109 11

DATA

PAR

22206B-8

Am79C978 39

Figure 6. Slave Write Using Memory Command

Expansion ROM Transfers

Since the Am79C978 device does not have expansion

ROM capab il itie s, PCI config ur ati on offset mu st be se t

to 30H = 0.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1).

Slave Cycle Termination

There are three scenarios besides normal completion

of a transacti on where the Am79C 978 cont roller is the

target of a slave cycle and it will terminate the access.

Figure 7. Expansion ROM Read

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0111

PAR

1 2345678 109 11

DATA

PAR

22206B-9

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

CMD

PAR

1 2345 484950

DATA

PAR

DEVSEL is sampled 22206B-10

40 Am79C978

Disconnect When Busy

The Am79C978 controller cannot service any slave ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not allowed in order to avoid

conflic ts , s ince t he E EP RO M i s used to initi al ize som e

of the PCI configuration space locations and most of

the BCRs a nd CSR116. T he EEPR OM r ead ope ration

will alwa ys h appen a utoma ticall y after the d eass ertio n

of the RST pi n. In add ition, the hos t can star t the rea d

operation by setting the PREAD bit (BCR19, bit 14).

While the EEPROM read is on-going, the Am79C978

controller will disconnect any slave access where it is

the target by asserting STOP together with DEVSEL,

while driving TRDY high. STOP will stay assert ed un til

the end of the cycle.

A seco nd s itu ati on wh er e the Am79 C978 con tro ller wil l

generate a PCI disconnect/retry cycle is when the host

tries to access any of the I/O resources right after hav-

ing read the Reset register. Since the access gener-

ates an inter nal reset pul se of about 1 ms in length, all

further slave accesses will be deferred until the internal

reset operation is completed. See Figure 8.

Disconnect Of Burst Transfer

The Am79C978 controller does not support burst ac-

cess to the configuration space, the I/O resources, or

to the Expansion Bus. The host indicates a burst trans-

action by keeping FRAME asserted during the data

phase. When the Am79C978 controller sees FRAME

and IRDY asserted in the clock cycle before it wants to

assert TRDY, it also asserts STOP at the same time.

The transfer of the first data phase is still successful,

since IRDY and TRDY are both asserted. See Figure 9.

If the host is not yet ready when the Am79C978 control-

ler as serts TRDY, the device will wait for the host to as-

sert IRDY. When the host asserts IRDY and FRAME is

still asserted, the Am79C978 controller will finish the

first data phase by deasserting TRDY one clock later.

At the same time, it will assert STOP to signal a discon-

nect to the host . STOP will sta y asse rt ed unt il th e ho st

removes FRAME. See Figure 10.

Figure 8. Disconnect of Slave Cycle When Busy

Figure 9. Disconnect of Slave Burst Tr ansfer - No

Host Wait States

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

CMD

PAR PAR PAR

DATA

ADDR

22206B-11

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

PAR PAR PAR

DATA

1st DATA

22206B-12

Am79C978 41

Figure 10. Disconnect of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C97 8 controller i s not the current bus

master, it samples the AD[31:0], C/BE[3:0], and the

PAR lines during the address phase of any PCI com-

mand for a parity error . When it detects an address par-

ity error, the Am79C978 controller sets PERR (PCI

Status register , bit 15) to 1. When reporting of that error

is enabled by setting SERREN (PCI Command regis-

ter, bit 8) and PERREN (P CI Comm and regis ter, bit 6)

to 1, the Am79C978 controller also drives the SERR

signal low for one clock cycle and sets SERR (PCI Sta-

tus register , bit 14) to 1. The assertion of SERR follows

the address phase by two clock cycles. The

Am79C978 controller will not assert DEVSEL for a PCI

transaction that has an address parity error when PER-

REN and SERREN are set to 1. See Figure 11.

Figure 11. Address Parity Err or Response

During the data phase of an I/O write, memory-mapped

I/O write, o r configuration write command that selects

the Am79C978 controller as target, the device samples

the AD[31:0] and C/BE[3:0] lines for parity on the clock

edge, and data is transferred as indicated by the asser-

tion of IRDY a nd TRDY. PAR is sampled in the follow-

ing clock cycle. If a parity error is detected and

reporting of that error is enabled by setting PERREN

(PCI Comma nd regi ster, bit 6) to 1, PERR is asserte d

one clock later. The parity error will always set PERR

(PCI Status register, bit 15) to 1 even when PERREN

is cleared to 0. The Am79C978 controller will finish a

transaction that has a data parity error in the normal

way by asserting TRDY. The corrupted data will be writ-

ten to the addressed location.

Figure 12 shows a transaction that suffered a parity

error at the time data was transferred (clock 7, IRDY

and TRDY ar e both asser ted). PERR is driven hi gh at

the beginning of the data phase and then drops low due

to th e pa ri t y error on clock 9, two cl oc k cycl es af te r t he

data was transferred. After PERR is driven low, the

Am79C978 controller drives PERR high for one clock

cycl e, since PERR is a sustained tri-state signal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 23456

PAR

PAR PAR

DATA

1st DATA

22206B-13

FRAME

CLK

SERR

C/BE

DEVSEL

1 2345

PAR PAR

ADDR 1st DATA

CMD

PAR

22206B-14

42 Am79C978

Figure 12. Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acqui-

sition of the PCI bu s and all access es to the initializ a-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 7 shows the usage of

PCI comm ands by the Am 79C9 78 controll er i n m as ter

mode.

Bus Acquisition

The microcode will determine when a DMA transfer

should be initiated. The first step in any bus master

transfer is to acquire ownership of the bus. This task is

handled by synchronous logic within the BIU. Bus own-

ership is requested with the REQ signal and ownership

is granted by the arbiter through the GNT signal.

Figure 13 shows the Am79C978 controller bus acquisi-

tion. REQ is asserted and the arbiter returns GNT while

another bus master is transferring data. The

Am79C978 controller waits until the bus is idle

(FRAME and IRDY deass erted) before it starts drivin g

AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted

at cloc k 5 indi cating a v alid addres s and comm and o n

AD[31:0] and C/BE[3:0]. The Am79C978 controller

does not use address stepping which is reflected by

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

1 2345678 109

DATA

PAR

PERR

22206B-15

Table 7. Master Commands

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Not used

0011 I/O Write Not used

0100 Reserved

0101 Reserved

0110 Memory Read

Read of the initialization

block and desc riptor

rings

Read of the transmit

buffer in non-burst mode

0111 Memory Write Write to the descriptor

rings and to the receive

buffer

1000 Reserved

1001 Reserved

1010 Configuration Read Not used

1011 Configuration Write Not used

1100 Memory Read

Multiple Read of the transmit

buffer in burst mode

1101 Dual Address Cycle Not used

1110 Memo ry Read Line Read of the transmit

buffer in burst mode

1111 Memory Write

Invalidate Not used

Table 7. Master Commands (Continued)

Am79C978 43

ADSTEP (bit 7) in the PCI Command register being

hardwir ed to 0.

Figure 13. Bus Acquisition

In burst mode, the deassertion of REQ depends on the

setting of EXTREQ (BCR18, bit 8). If EXTREQ is

cleared to 0, REQ is deasserted at the same time as

FRAME is asserted. (The Am79C978 controller never

performs more th an o ne burs t tr ans acti on wi thi n a sin-

gle bus mast ershi p period. ) If EXTRE Q is set to 1, the

Am79C978 controller does not deassert REQ until it

starts the last data phase of the transaction.

Once as sert e d, REQ remains active until GNT has be-

come active and independent of subsequent setting of

STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-

tion of H_RESET or S_RESET, however, will cause

REQ to go inactive immediately.

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

Am79C978 controller uses non-burst as well as burst

cycles for read and write access to the main memory.

Basic Non-Burst Read Transfer

By default, the Am79C978 controller uses non-burst

cycle s in all bus mas ter read ope rations. Al l controller

non-burst read accesses are of the PCI command type

Memory Read (type 6). Note that during a non-burst

read operation, all byte lanes will always be active. The

Am79C978 controller will internally discard unneeded

bytes.

The Am79C978 controller typically performs more than

one non-burst read transaction within a single bus

mastership period. FRAME is dropped between con-

secutive non-burst read cycles. REQ stays asserted

until FRAME is asserted for the last transaction. The

Am79C978 controller supports zero wait state read cy-

cles. It asserts IRDY immediately after the address

phase and at the sa me time star ts sam pling DEVS EL .

Figure 14 s hows two non- burs t r ead tran sac ti ons . Th e

first transaction has zero wait states. In the second

transaction, the target extends the cycle by asserting

TRDY one clock later.

Basic Burst Read Tr ansfer

The Am79C978 controller supports burst mode for all

bus master read operations. The burst mode must be

enabled by setting BREADE (BCR18, bit 6). To allow

burst transfers in descriptor read operations, the

Am79C978 controller must also be programmed to use

SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses

to the i nitializ ation bloc k and descriptor ring are of the

PCI co mm and typ e Me mor y Rea d (ty pe 6 ). Bu rst r ea d

accesses to the transmit buffer typically are longer than

two data phases. When MEMCMD (BCR18, bit 9) is

cleared to 0, all burst read accesses to the transmit

buffer are of the PCI command type Memory Read Line

(type 14). When MEMCM D (BCR18, bit 9) is set to 1,

all burst read accesses to the transmit buffer are of the

PCI command type Memory Read Multiple (type 12).

AD[1:0] will both be 0 during the address phase indicat-

ing a linear burst order. Note that during a burst read

operation, all byte lanes will always be active. The

Am79C978 controller will internally discard unneeded

bytes.

The Am79C978 controller will always perform only a

single burst read transaction per bus mastership pe-

riod, where transaction is defined as one address

phase and one or multiple data phases. The

Am79C978 controller supports zero wait state read cy-

cles. It asserts IRDY immediately after the address

phase and at the sa me time star ts sam pling DEVS EL .

FRAME is deasserted when the next to last data phase

is completed.

Figure 15 shows a typical burst read access. The

Am79C 978 controller arbitrates for the bus , is granted

access, reads three 32-bit words (DWord) from the sys-

tem memor y, and then rel eases the b us. In the exam-

ple, the memory system extends the data phase of

each access by one wait state. The example assumes

that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,

REQ is deasserted in the same cycle as FRAME is as-

serted.

FRAME

CLK

IRDY

C/BE

REQ

GNT

1 2345

CMD

ADDR

22206B-16

44 Am79C978

Figure 14. Non-Bur st Rea d Transfer

Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

1 2345678 109 11

DATA

ADDR

DATA

PAR PAR PAR

0000 0110 0000

22206B-17

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

00001110

PAR

1 2345678 109 11

DATA

PAR PAR PAR

22206B-18

Am79C978 45

Basic Non-Burst Write Transfer

By default, the Am79C978 controller uses non-burst

cycle s in all bus ma ster write op erations. A ll contro ller

non-burst write accesses are of the PCI command type

Memory Write (type 7). The byte enable signals indi-

cate the byte lanes that have valid data. The

Am79C978 controller typically performs more than one

non-bur st write transac ti on with in a s in gle bu s mas ter -

ship period. FRAME is dropped between consecutive

non-burst write cycles. REQ stays asserted until

FRAME is asserted for the last transaction. The

Am79C978 controller supports zero wait state write cy-

cles except with descriptor write transfers. (See the

section Descriptor DMA Transfers for the only excep-

tion.) It asserts IRDY immediately after the address

phase.

Figure 16 shows two non-burst write transactions. The

first trans action has two wait sta tes. The tar get ins erts

one wait state by asserting DEVSEL one clock late and

another wait state by also asserting TRDY one clock

late. The second transaction shows a zero wait state

write cycle. The t arget asserts DEVSEL and TRDY in

the same cycle as the Am79C978 controller asserts

IRDY.

Basic Burst Write Transfer

The Am79C978 controller supports burst mode for all

bus mas ter write operations . The bu rst mode m ust be

enabled by setting BWRITE (BCR18, bit 5). To allow

burst transfers in descriptor write operations, the

Am79C978 controller must also be programmed to use

SWSTYLE 3 (BCR20, bits 7-0). All controller burst

write transfers are of the PCI command type Memory

Write (type 7). AD[1:0] will both be 0 during the address

phase indicating a linear burst order. The byte enable

signals indicate the byte lanes that have valid data.

The Am7 9C978 co ntrolle r will al ways per form a si ngle

burst write transaction per bus mastership period,

where transaction is defined as one address phase and

one or multiple data phases. The Am79C978 controller

supports zero wait state write cycles except with the

case of descriptor write transfers. (See the section De-

scriptor DMA Transfers for the only exception.) The de-

vice a sserts IRDY immediately after the address phase

and at the same time starts sampling DEVSEL.

FRAME is deasserted when the next to last data phase

is completed.

Figure 16. Non-Burst Write Transfer

Figure 17 shows a typical burst write access. The

Am79C978 c ontroller arbi trates for the bus, is granted access, and writes four 32-bit words (DWords) to the

system memory and then releases the bus. In this ex-

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 2345678 109

DATA

ADDR

DATA

PAR PAR PAR

BE 0111 BE

22206B-19

46 Am79C978

ample, the memor y system exten ds the data p hase of

the first access b y one wait state. The following three

data phases take one clock cycle each, which is deter-

mined by the timing of TRDY. The example assumes

that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ

is not deasserted until the next to last data phase is fin-

ished.

Target Initiated Termination

When the Am79C978 controller is a bus master , the cy-

cles i t produc es on the PC I bu s may b e te rminated by

the target in one of three different ways: disconnect

with data transfer, disconnect without data transfer, and

target abort.

Disconnect With Data Transfer

Figure 18 shows a disconnection in which one last data

transfer occurs after the target asserte d STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C978

controller terminates the current transfer with the deas-

sertion of FRAME on clock 5 and of IRDY one clock

later. It finally releases the bus on clock 7. If it wants to

transfer more data, the Am79C978 controller will again

request the bus after two clock cycles. The starting ad-

dress of the new transfer will be the address of the next

non-transferred data.

Figure 17. Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

12345678

ADDR DATA DATA DATA

0111

PAR PAR PAR PAR PAR

DATA

PAR

DEVSEL is sampled 22206B-20

Am79C978 47

Figure 18. Disconne ct With Data Transf er

Disconnect Without Data Transfer

Figure 19 shows a target disc onnect s equence dur ing

which no data is transferred. STOP is asserted on clock

4 without TRDY being a sserte d at the s ame tim e. The

Am79C978 controller terminates the access with the

deassertion of FRAME on clock 5 and of IRDY one

clock cycle lat er. I t finally r eleases th e bus on clock 7 .

The Am79C978 controller will again request the bus

after two clock cycles to retry the last transfer. The

starting address of the new transfer will be the address

of the last non-transferred data.

Target Abort

Figure 20 shows a tar get abort sequence. The tar get

asserts DEVSEL for one clock. It then deasserts

DEVSEL and asserts STOP on clock 4. A target can

use the target abort sequence to indicate that it can-

not service the data transfer and that it does not want

the transaction to be retried. Additionally, the

Am79C978 controller cannot make any assumption

about the success of the previous data transfers in the

current transaction. The Am79C978 controller termi-

nates the current transfer with the deassertion of

FRAME on clock 5 and of IRDY one clock cycle later.

It finally releases the bus on cloc k 6.

Since d ata integr ity is not guarantee d, the Am7 9C978

controller cannot recover from a target abort event.

TheAm79C978 controller will reset all CSR locations to

their STOP_RES ET val ues. Th e BCR an d PCI c onfig-

uration regis te rs will not be c le ared. Any o n- goi ng n et-

work transmission is terminated in an orderly

sequenc e. If less than 512 b its have b een transm itted

onto the network, the transmission will be terminated

immediately, generating a runt packet. If 512 bits or

more have been transmitted, the message will have the

current FCS inverted and appended at the next byte

boundary to guarantee an FCS error is detected at the

receiving station.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDRi

00000111

PAR

0111

23456789 11

PAR

DATA

STOP

ADDRi+8

DATA

22206B-21

48 Am79C978

Figure 19. Disconnect Without Data Transfer

RTABORT (PCI Status register, bit 12) will be set to

indicate that the Am79C978 controller has received a

target abort. In addition, SINT (CSR5, bit 11) will be set

to 1. When SINT is set, INTA is assert ed if the ena ble

bit SINTE (CSR5, bit 10) is set to 1. This mechanism

can be used to inform the driver of the system error. The

host can rea d the PCI Status re giste r t o det er min e th e

exact cause of the interrupt.

Ma ster Initiated Termination

There are three scenarios besides normal completion

of a transaction where the Am79C978 controller will

terminate the cycles it produces on the PCI bus.

Preemption During Non-Burst Transaction

When the Am79C978 controller performs multiple non-

burst tran sac ti ons , it keep s RE Q ass er ted u nti l th e as -

sertion of FRAME for the last transaction. When GNT

is removed, the Am79C978 controller will finish the cur-

rent transaction and then release the bus. If it is not the

last transaction, REQ will remain asserted to regain

bus ownership as soon as possible. See Figure 21.

Preemption During Burst Transaction

When the Am79C978 controller operates in burst

mode, it only performs a single transaction per bus

mast ership peri od, whe re transaction is defined as one

address phase and one or multiple data phases. The

central ar bi ter c an rem ov e G NT at an y t ime duri ng th e

transaction. TheAm79C978 controller will ignore the

deassertion of GNT and continue with data transfers,

as long as the PCI Latency Timer is not expired. When

the Latency Timer is 0 and GNT is deasserted, the

Am79C978 controller will finish the current data phase,

deassert FRAME, finish the last data phase, and re-

lease th e bus . If EX TREQ ( BCR18 , bit 8 ) is c leared t o

0, it will i mmedi ately as sert R EQ to regain bus ow ner-

ship as so on as poss ible . I f EXTR EQ i s se t t o 1, REQ

will stay asserted.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

STOP

ADDRi

00000111

PAR

0111

23456789 11

ADDRi

DATA

PAR

22206B-22

Am79C978 49

Figure 20. Target Abort

When the preemption occurs after the counter has

counted down to 0, the Am79C978 controller will finish

the current data phase, deassert FRAME, finish the

last data phase, and release the bus. Note that it is im-

portant for the host to pro gram the PCI Late ncy Timer

according to the bus bandwidth requirement of the

Am79C978 controller. The host can determine this bus

bandwidth requirement by reading the PCI MAX_LAT

and MIN_GNT registers.

Figure 22 assumes that the PCI Latency Timer has

counted down to 0 on clock 7.

Master Abort

TheAm7 9C97 8 con tr oll er wil l termi na te its cy cle wit h a

Master Abort sequence if DEVSEL is not asserted

within 4 clocks after FRAME is asserted. Master Abort

is treated as a fatal error by the Am 79C978 contr oller.

TheAm79C978 controller will reset all CSR locations to

their STOP_RES ET val ues. Th e BCR an d PCI c onfig-

uration regis te rs will not be c le ared. Any o n- goi ng n et-

work transmission is terminated in an orderly

sequenc e. If less than 512 b its have b een transm itted

onto the network, the transmission will be terminated

immediately, generating a runt packet. If 512 bits or

more have been transmitted, the message will have the

current FCS inverted and appended at the next byte

boundary to guarantee an FCS error is detected at the

receiving station.

RMABORT (in the PCI Status register , bit 13) will be set

to indicate that the Am79C978 controller has termi-

nated its transaction with a master abort. In addition,

SINT (CSR5, bit 11) will be set to 1. When SINT is set,

INTA is asserted if the enable bit SINTE (CSR5, bit 10)

is set to 1. Thi s me chani sm c an be used to i nform th e

driver of the system error. The host can read the PCI

Status re gister to deter mine the exact cau se of the in-

terrupt. See Figure 23.

Parity Error Response

During every data phase of a DMA read operation,

when the target indicates that the data is valid by as-

serting TRDY, the Am79C978 controller samples the

AD[31:0], C/BE[3:0], and the P AR lines for a data parity

error. When it detects a data parity error, the

Am79C 978 controll er sets PE RR (PCI Status register,

bit 15) to 1. Whe n report ing of t hat error is enab led by

setting PERREN (PCI Command register, bit 6) to 1,

the Am79C 978 co ntroller a lso drives the PERR s ignal

low and sets DATAPERR (PCI Status register, bit 8) to

1. The assertion of PERR follows the corrupted data/

byte enables by two clock cycles and P AR by one clock

cycle.

Figure 24 shows a transaction that has a parity error in

the data phase. TheAm79C978 controller asserts

PERR on clock 8, two clock cycles after data is valid.

The data on cl ock 5 is not check ed for pa rity, beca use

on a read access, PAR is only required to be valid one

clock after the target has asserted TRDY.

TheAm79C978 controller then drives PERR high for

one clock cycle, since PERR is a sustained tri-state

signal.

During every data phase of a DMA write operation, the

Am79C 978 contro ller chec ks the PER R input to see i f

the target reports a parity error . When it sees the PERR

input asserted, the Am79C978 controller sets PERR

(PCI Status regis ter, bit 15) to 1. When PERRE N (PCI

Command register, bit 6) is set to 1, the Am79C978

controller also sets DAT APERR (PCI Status register, bit

8) to 1.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

234567

ADDR

0000

0111

PAR PAR

DATA

STOP

22206B-23

50 Am79C978

Figure 21. Preemption During Non-Burst Transaction

Figure 22. Preemption During Burst Transaction

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

BE0111

PAR PAR

DEVSEL is sampled

PAR

DATA

ADDR

22206B-24

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

BE0111

PAR

1 23456789

DATA

PAR

REQ

DATA

PAR PAR PAR PAR

GNT

22206B-25

Am79C978 51

Figure 23. Master Abort

Figure 24. Master Cycle Data Parity Error Response

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

REQ

GNT

0000

22206B-26

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

PERR

22206B-27

52 Am79C978

Whene ver the Am 79C 978 con troll er is the curren t bus

master and a data parity error occurs, SINT (CSR5, bit

11) will be set to 1. When SINT is set, INTA is assert ed

if the enable bit SINTE (CSR 5, bit 10) is set to 1. This

mechanism can be used to inform the driver of the sys-

tem error . The host can read the PCI Status register to

determine the exact cause of the interrupt. The setting

of SIN T due t o a da ta parity error is not depen dent o n

the setting of PERREN (PCI Command register, bit 6).

By defa ult, a da ta par it y er ror do es no t a ffect the st at e

of the MAC engine. TheAm79C978 controller treats the

data in all bus master transfers that have a parity error

as if nothing has happened. All network activity contin-

ues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C978 controller provides

a second, more advanced level of parity error handling.

This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits

(RMD1 and TMD1, bit 23) are used to indicate parity

error in data tr ans fe rs to the re ce iv e a nd tr a nsm it buff-

ers. Note that since the advanced parity error handling

uses an additional bit in the descriptor, SWSTYLE

(BCR20, bits 7 -0) m ust be se t to 2 or 3 to p ro gram th e

Am79C978 controller to use 32-bit software structures.

TheAm79C978 controller will react in the following way

when a data parity error occurs:

nInitialization block read: STOP (CSR0, bit 2) is set

to 1 and causes a STOP_RESET of the device.

nDescriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cau se a STOP_RESET

of the device.

nDescriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cau se a STOP_RESET

of the device.

nTransmit buffer read: BPE (TMD1, bit 23) is set in

the current transmit descriptor. Any on-going net-

work transmission is terminated in an orderly se-

quence.

nReceive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Terminating on-going network transmission in an or-

derly sequence means that if less than 512 bits have

been transmitted onto the network, the transmission

will be terminated immediately, generating a runt

packet.

If 512 bits or more have been transmitted, the message

will have the current FCS inverted and appended at the

next byte boundary to guarantee an FCS error is de-

tected at the receiving station.

APERREN does not affect the reporting of address

parity errors or data parity errors that occur when the

Am79C 978 co ntrol ler is the target of the tran sfe r.

Initialization Block DMA Transfers

During execution of the Am79C978 controller bus mas-

ter initialization procedure, the microcode will repeat-

edly reques t DMA transfe rs fro m the B IU. Durin g eac h

of these initialization block DMA transfers, the BIU will

perform two data transfer cycles reading one DWord

per transfer and then it will relinquish the bus. When

SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the initialization

block is organized as 32-bit software structures), there

are seven DWords to transfer during the bus master ini-

tialization procedure, so four bus mastership periods

are needed in order to complete the initialization se-

quence. Note that the last DWord transfer of the last

bus mastership period of the initialization sequence ac-

cesses an unneeded location. Data from this transfer is

discarded internally. When SSIZE32 is cleared to 0

(i.e., th e initia lizatio n block i s organ ized as 1 6-bit s oft-

ware structures), then three bus mastership periods

are needed to complete the initialization sequence.

The Am79C978 device supports two transfer modes

for rea ding the i nitializat ion block: non-burst and burs t

mode, with burst mode being the preferred mode when

the Am79C978 controller is used in a PCI bus applica-

tion. See Figure 25 and Figure 26.

When BREADE is cleared to 0 (BCR18, bit 6), all initial-

ization block read transfers will be executed in non-

burst mode. There is a new address phase for every

data phas e. FRAME will be dr opped between the two

transfers . Th e two pha se s wit hin a bus mas te rs hip pe-

riod will have addresses of ascending contiguous or-

der.

When BR EADE is se t to 1 (BCR18, bit 6) , all i niti al iza-

tion block read transfers will be executed in burst

mode. AD[1:0] will be 0 during the address phase indi-

cating a linear burst order.

Am79C978 53

Figure 25. Initialization Block Read In Non-Burst Mode

Figure 26. Initialization Block Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

IADDi

00000110

PAR PAR

DATA DATA

IADDi+4

0000

0110

PAR PAR

1 2345678 109

22206B-28

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000110

PAR PAR PAR PAR

DEVSEL is sampled

DATA DATA

IADDi

22206B-29

54 Am79C978
Descriptor DMA Transfers
The Am79C978 microcode will determine when a de-
scriptor access is required. A descriptor DMA read will
consist of two data transfers. A descriptor DMA write
will consist of one or two data transfers. The descriptor
DMA transfers within a single bus mastership period
will always be of the same type (either all read or all
write).
During descriptor read accesses, the byte enable sig-
nals wil l indicate that a ll byte lanes a re active. Sho uld
some of the bytes not be needed, then the Am79C978
controller will internally discard the extraneous informa-
tion that was gathered during such a read.
The settings of SWSTYLE (BCR20, bits 7-0) and
BREADE (BCR18, bit 6) affect the way the Am79C978
controller performs descriptor read operations.
When SWSTYLE is set to 0 or 2, all descriptor read op-
erations ar e perfor me d in no n- burs t mode . Th e set tin g
of BREADE has no effect in this configuration. See Fig-
ure 27.
When SWS TYLE is  set to 3, the descripto r entr ies are
ordered to allow burst transfers. TheAm79C978 con-
troller will perform all descriptor read operations in
burst mode, if BREADE is set to 1. See Figure 28. 
Table 8 shows the descriptor read sequence.
During descriptor write accesses, only the byte lanes
which need to be written are enabled.
If buffer chaining is used, accesses to the descriptors
of all intermediate buffers consist of only one data
transfer to return ownership of the buffer to the system.
When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e.,
the desc ripto r entr i es ar e o rgani z ed a s  16-bi t s oftwa re
structures), the descriptor access will write a single
byte. When SW STYLE  (BCR20, bi ts 7-0) is se t to 2 or
3 (i.e., the descriptor entries are organized as 32-bit
software  struc tures), the descr iptor access wi ll write a
single word. On all single buffer transmit or receive de-
scriptors, as well as on the last buffer in chain, writes to
the descriptor consist of two data transfers.
The first data transfer writes a DWord containing status
information. The second data transfer writes a byte
(SWSTYLE cleared to 0), or otherwise a word contain-
ing additional status and the ownership bit (i.e.,
MD1[31]).
The settings of SWSTYLE (BCR20, bits 7-0) and
BWRITE ( BCR 18,  bit  5)  a ffect the  way the Am79 C97 8
controller performs descriptor write operations.
When SWSTYLE is set to 0 or 2, all descriptor write op-
erations ar e perfor me d in no n- burs t mode . Th e set tin g
of BWRITE has no effect in this configuration. See Fig-
ure 29. 
When SWS TYLE  is set to 3, the desc riptor  entries ar e
ordered to allow burst transfers. TheAm79C978 con-
troller will perform all descriptor write operations in
burst m ode, if BWR ITE is set t o 1. See  Figure 30  and
Table 9 for the descriptor write sequence.
A write transaction to the descriptor ring entries is the
only case where the Am79C978 controller inserts a
wait state when being the bus master. Every data
phase in non-burst and burst mode is extended by one
clock cycle, during which IRDY is  deass er te d.
Note that Figure 28 assumes that the Am79C978 con-
troller is programmed to use 32-bit software structures
(SWSTYLE = 2 or 3). The byte enable signals for the
second data transfer would be 0111b, if the device was
programmed to use 16-bit software structures (SW-
STYLE = 0).
Table 8. Descriptor Read Sequence
SWSTYLE
BCR20[7:0] BREADE
BCR18[6] AD Bus Sequence
0X
Address = XXXX XX00h
Turn around cycle
Data =  MD1[31: 24],  MD0[23 :0]
Idle
Address = XXXX XX04h
Turn around cycle
Data = MD2[15:0], MD1[15:0]
2X
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX00h
Turn around cycle
Data = MD0[31:0]
30
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX08h
Turn around cycle
Data = MD0[31:0]
31
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Data = MD0[31:0]

Am79C978 55

Figure 27. Descriptor Ring Read In Non-Burst Mode

Figure 28. Descriptor Ring Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD1

00000110

PAR PAR

DATA DATA

MD0

00000110

PAR PAR

1 2345678 109

22206B-30

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

MD1

00000110

PAR PAR PAR

DATA DATA

PAR

DEVSEL is sampled 22206B-31

56 Am79C978

Figure 29. Descriptor Ring Write In Non-Burst Mode

Figure 30. Descriptor Ring Write In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD2

00000111

PAR

MD1

00110111

PAR

1 2345678 109

DATA

PAR

DATA

22206B-32

GNT

REQ

DEVSEL

TRDY

PAR

C/BE

FRAME

CLK 35

PAR

IRDY

DEVSEL is sampled

DATA

1 2 4 6 7 8

0110 0000 0011

MD2

PAR

DATA

PAR

22206B-33

Am79C978 57

Ta ble 9. Descriptor Write Sequence

FIFO DMA Transfers

The Am79C978 microcode will determine when a FIFO

DMA transfer is required. This transfer mode will be

used for transfers of data to and from the FIFOs. Once

the BIU has been granted bus mastership, it will per-

form a series of consecutive transfer cycles before re-

linquishing the bus. All transfers within the master cycle

will be ei ther read or write cyc les, and a ll tra nsfers wi ll

be to contiguous, ascending addresses. Both non-

burst and burst cycles are used, with burst mode being

the preferred mode when the device is used in a PCI

bus application.

Non-Burst FIFO DMA T ransfers

In the default mode, the Am79C978 controller uses

non-burst transfers to read and write data when ac-

cessing the FIFOs. Each non-burst transfer will be per-

formed sequentially with the issue of an address and

the transfer of the corresponding data with appropriate

output signals to indicate selection of the active data

bytes during the trans fer.

FRAME will b e d eas se rt ed after e ve ry address pha se.

Several factors will affect the length of the bus master-

ship period. The possibilities are as follows:

Bus cycles will continue until the transmit FIFO is filled

to its high threshold (read transfers) or the receive

FIFO is emptied to its low threshold (write transfers).

The exact number of total transfer cycles in the bus

mastership period is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditions o f th e FI FOs , the la tenc y of the s yste m bus

to t he Am79 C978 c ontrol ler’s bus request, the speed of

bus operati on and bus preempti on events. The TRDY

response time of the memory device will also af fect the

number of transfers, since the speed of the accesses

will affect the state of the FIFO. During accesses, the

FIFO may be filling or emptying on the network end.

For example, on a receive operation, a slower TRDY

response will allow additional data to accumulate in-

side of the FIFO. If the accesses are slow enough, a

complete DWord may become available before the end

of the bus mastership period and, thereby , increase the

number o f transfers in that period. Th e general rule is

that the longer the Bus Grant latency, the slower the

bus transfer operations; the slower the clock speed, the

higher the transmit watermark; or the higher the re-

ceive watermark, the longer the bus mastership period

will be.

Note: The PCI Latenc y Timer is not sign ific ant durin g

non-burst transfers.

Burst FIFO DMA Transfers

Bursting is only performed by the Am79C978 controller

if the BR EADE and /or BW RITE bi ts o f BCR18 are se t.

These bits in dividua lly enabl e/disabl e the ability of th e

Am79C978 controller to perform burst accesses during

master read operations and master write operations,

respectively.

A burst transaction will start with an address phase, fol-

lowed by one or more data phases. AD[1:0] will always

be 0 during the address phase indicating a linear burst

order.

During FIFO DMA read operations, all byte lanes will

always be active. TheAm79C978 controller will inter-

nally discard unused bytes. During the first and the last

data phases of a FIFO DMA burst write operation, one

or more of the byte enable signals may be inactive. All

othe r da ta phas es wi ll alwa ys wr ite a co mplet e D W ord.

Figure 31 shows the beginning of a FIFO DMA write

with the beginning of the buffer not aligned to a DWord

boundary . TheAm79C978 controller starts off by writing

only three byte s du ring the first data phas e. This oper-

ation aligns the address for all other data transfers to a

32-bit boundary so that the Am79C978 controller can

continue bursting full DWords.

If a receive buffer does not end on a DWord boundary,

the Am79C978 controller will perform a non-DWord

write on the last transfer to the buffer. Figure 32 shows

the final three FIFO DMA transfe rs to a r eceive bu ffer.

Since there were only nine bytes of space left in the re-

ceive buffer, the Am79C978 controller bursts three

data phases. The first two data phases write a full

DWord, the last one only writes a single byte.

SWSTYLE

BCR20[7:0] BWRITE

BCR18[5] AD Bus Sequence

Address = XXXX XX04h

Data = MD2[15:0],

MD1[15:0]

Idle

Address = XXXX XX00h

Data = MD1[31:24]

Address = XXXX XX08h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Data = MD1[31:16]

58 Am79C978

Note that the Am79C978 controller will always perform

a DWord transfer as long as it owns th e buffer spa ce,

even when there are l ess than fo ur bytes to write. For

example, if there is only one byte left for the current re-

ceive frame, the Am79C978 controller will write a full

DWord, containing the last byte of the receive frame in

the lea st signi ficant byte po sition (BSW P is cleared to

0, CSR3, bit 2). The cont ent of the oth er thre e byte s is

undefined . The mess age byte count in the recei ve de-

scriptor always reflects the exact length of the received

frame.

Figure 31. FIFO Burst Wr ite at S tart of Unaligned

Buffer

TheAm79C978 controller will continue transferring

FIFO data until the transmit FIFO is filled to its high

thresho ld (read transfers) or the re ceive FIFO is emp-

tied to its low threshold (write transfers), or the

Am79C978 controller is preempted and the PCI La-

tency T imer is expired. The host should use the values

in the PCI MIN_GNT and MAX_LAT registers to deter-

mine the value for the PCI Latency Timer.

Figure 32. FIFO Burst Writ e at End of Unaligned

Buffer

The exact number of total transfer cycles in the bus

mastership period is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditions o f th e FI FOs , the la tenc y of the s yste m bus

to the Am79C978 controller’s bus request, and the

speed of bus operation. The TRDY response time of

the memory device will also affect the number of trans-

fers, since the speed of the accesses will affect the

state of the FIFO. During acce sses, the FIFO may be

filling or emptying on the network end. For example, on

a receive operation, a slower TRDY response will allow

additional data to accumulate inside of the FIFO. If the

accesses are slow enough, a complete DWord may be-

come available before the end of the bus mastership

period and, thereby, increase the number of transfers

in that period. The general rule is that the longer the

Bus Grant latency, the slower the bus transfer opera-

tions; the sl owe r the clock spee d, the hi ghe r the tran s-

mit watermark; or the lower the receive watermark, the

longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the

Am79C978 controller will not relinquish bus ownership

until the PCI Latency Timer expires.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 23456

00000111

PAR PAR PAR

DEVSEL is sampled

0001

PAR

DATA DATA

DATA

ADD

22206B-34

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000111

PAR PAR PAR PAR

DEVSEL is sampled

1110

PAR

DATA DATA

DATA

ADD

22206B-35

Am79C978 59

Buffer Management Unit

The Buffer Management Unit (BMU) is a microcoded

state machine which implements the initialization pro-

cedure an d manages th e descripto rs and buffers. The

buffer management unit operates at half the speed of

the CLK input.

Initialization

Initialization includes the reading of the initialization

block in memory to obtain the operating parameters.

The initialization block can be organized in two ways.

When SSIZ E3 2 (BCR20 , bit 8) is at its defau lt value of

0, all initialization block entries are logically 16-bits

wide to be backwards compatible with the Am79C90

C-LANCE and Am79C96x PCnet-ISA family. When

SSIZE32 (BCR20, bit 8) is set to 1, all initialization

block entries are logically 32-bits wide. Note that the

Am79C978 controller always performs 32-bit bus

transfers to read the initialization block entries. The ini-

tialization block is read when the INIT bit in CSR0 is

set. The INIT bit should be set before or concurrent with

the STRT bit to in sure correc t operation . Once the in i-

tialization block has been completely read in and inter-

nal registers have been updated, IDON will be set in

CSR0, generating an interrupt (if IENA is set).

The Am7 9C978 con troller ob tains the start ad dress of

the initialization block from the contents of CSR1 (least

signifi cant 1 6 bits of add ress) and CS R2 (mos t sig nifi-

cant 16 bits of address). The host must write CSR1 and

CSR2 before setting the INIT bit. The initialization block

contains the user defined conditions for operation, to-

gether with the base addresses and length information

of the transmit and receive descriptor rings.

There is an alternate method to initialize the

Am79C978 controller. Instead of initialization via the

initialization block in memory, data can be written di-

rectly into the appropriate registers. Either method or a

combination of the two may be used at the discretion of

the program mer. Please refer to Appendix A, Alterna-

tive Method for Initialization for details on this alternate

method.

Re-Initialization

The transmitter and receiver sections of the

Am79C978 controller can be turned on via the initial-

ization bl ock ( DTX, DRX , CSR1 5, bit s 1- 0). Th e sta tes

of the transmitter and receiver are monitored by the

host through CSR0 (RXON, TXON bits). The

Am79C978 controller should be re-initialized if the

transmitter and/or the receiver were not turned on dur-

ing the original initialization and it was subsequently re-

quired to activate them, or if either section was shut off

due to the detection of an error condition (MERR,

UFLO, TX BUFF error).

Re-initialization may be done via the initialization block

or by setting the STOP bit in CSR0, followed by writing

to CSR15, and then setting the START bit in CSR0.

Note that this f orm o f r es tart wil l not perform th e sam e

in the Am79C978 controller as in the C-LANCE device.

In particular , upon restart, the Am79C978 controller re-

loads th e tr an sm it and rece iv e d es cri ptor p oin ter s wit h

their respective base addresses. This means that the

software must clear the descriptor OWN bits and reset

its descriptor ring pointers before restarting the

Am79C978 controller. The reload of descriptor base

addresses is performed in the C-LANCE device only

after initialization, so that a restart of the C-LANCE

without initialization leaves the C-LANCE pointing at

the same descriptor locations as before the restart.

Suspend

The Am79C978 controller offers two suspend modes

that allow easy updating of the CSR registers without

going through a full re-initialization of the device. The

suspend modes also allow stopping the device with or-

derly termination of all network activity.

The host requests the Am79C978 controller to enter

the suspend mode by setting SPND (CSR5, bit 0) to 1.

The host must poll SPND until it reads back 1 to deter-

mine that the Am79C978 controller has entered the

suspend mode. When the host sets SPND to 1, the pro-

cedure taken by the Am 79C978 co ntroller t o enter the

suspend mod e depen ds on th e setti ng of the fast sus-

pend enable bit (FASTSPND, CSR7, bit 15).

When a fast suspend is requested (FASTSPN D is set

to 1), th e Am79 C978 c ontrolle r perfo rms a qu ick entry

into the suspend mode. At the time the SPND bit is set,

the Am79C978 controller will continue the DMA pro-

cess of any transmit an d/or receive pac kets that hav e

already begun DMA activity until the network activity

has been completed. In addition, any transmit packet

that had started transmission will be fully transmitted

and any receive packet that had begun reception will

be fully received. However, no additional packets will

be transmitted or received and no additional transmit or

receive DMA activity will begin after network activity

has ceased. Hence, the Am79C978 controller may

enter the suspend mode with transmit and/or receive

packets still in the FIFOs or the SRAM. This offers a

worst cas e suspen d time of a m aximu m length packe t

over the possib ility o f co mplete ly emp tying the SRAM .

Care must be ex erc ised in this mode, beca us e the en-

tire m emory s ubsys tem of the Am79C9 78 co ntrol ler is

suspend ed. Any cha nge s t o either the desc ri pto r ri ngs

or the SRAM can cause the Am79C978 controller to

start up in an unknown condition and could cause data

corruption.

When FASTSPNDE is 0 and the SPND bit is set, the

Am79C 978 contro ller may ta ke longer before en tering

the suspend mode. At the time the SPND bit is set, the

Am79C978 controller will complete the DMA process of

a transmit packet if it had already begun, and the

60 Am79C978

Am79C978 controller will completely receive a receive

packet if it had already begun. TheAm79C978 control-

ler will not receive any new packets after the comple-

tion of the current reception. Additionally, all transmit

packets s tored in the transmit FIFOs and the transmi t

buffer area in the SRAM (if one is present) will be trans-

mitted, and all receive packets stored in the receive

FIFOs an d the rece ive buffer are a in the SR AM (if se-

lected) will be transferred into system memory. Since

the FIFO and the SRAM contents are flushed, it may

take much longer befor e the Am 79C978 c ontroll er en-

ters the suspend mode. The amount of time that it

takes depends on many factors including the size of

the SRAM, bus latency, and network traffic level.

Upon completion of the described operations, the

Am79C978 controller sets the read-version of SPND to

1 and enters the suspend mode . In suspend mod e, all

of the CSR and BCR re gis te rs are a cces sibl e. A s lon g

as the Am79C978 controller is not reset while in sus-

pend mode (by H_RESET, S_RESET, or by setting the

STOP bit), n o re-initializ ation of the de vice is req uired

after the device comes out of suspend mode. When

SPND is set to 0, the Am79C978 controller will leave

the suspend mode and will continue at the transmit and

receive descriptor ring locations where it was when it

entered the suspend mode.

See the section on Magic Packet technology for details

on how that affects suspension of the integrated Ether-

net controller.

Buffer Management

Buffer management is accomplished through message

descriptor entries organized as ring structures in mem-

ory . There are two descriptor rings, one for transmit and

one for receive. Each descriptor describes a single

buffer . A frame may occupy one or more buffers. If mul-

tiple buffers are used, this is referred to as buffer chain-

ing.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of

memory. During initialization, the user-defined base

address for the transmit and receive descriptor rings,

as well as the number of entries contained in the de-

scrip tor r ing s a re se t up. Th e programm ing of th e so ft-

ware style (SWSTYLE, BCR20, bits 7-0) affects the

way the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the de-

scriptor rings are backwards compatible with the

Am79C90 C-LANCE and the Am79C96x PCnet-ISA

family. The descriptor ring base addresses must be

aligned to an 8-byt e boundar y and a maxim um of 128

ring entries is allowed when the ring length is set

through th e TLEN and RLE N fields of the i nitializa tion

block. Each ring entry contains a subset of the three

32-bit transmit or receive message descriptors (TMD,

RMD) that are organized as four 16-bit structures

(SSIZE32 (BCR20, bit 8) is set to 0). Note that even

though the Am79C978 controller treats the descriptor

entries as 16-bit structures, it will always perform 32-bit

bus transfers to access the descriptor entries. The

value of CSR2, bits 15-8, is used as the upper 8-bits for

all memory addresses during bus master transfers.

When SWSTYLE is set to 2 or 3, the descriptor ring

base addresses must be aligned to a 16-byte bound-

ary , and a maximum of 512 ring entries is allowed when

the ring length is set through the TLEN and RLEN fields

of the initialization block. Each ring entry is organized

as three 32-bit message descriptors (SSIZE32

(BCR20, bit 8) is set to 1). The fourth DWord is re-

served. When SWSTYLE is set to 3, the order of the

message descriptors is optimized to allow read and

write access in burst mode.

For any so ftware s tyle, the r ing le ngths can b e se t be-

yond this range (up to 65535) by writing the transmit

and receive ring length registers (CSR76, CSR78) di-

rectly.

Each ring entry contains the following information:

nThe address of the actual message data buffer in

user or host memory

nThe length of the message buffer

nStatus information indicating the condition of the

buffer

To permit the queuing and de-queuing of message

buffers, owners hip of each b uffer is alloc ated to eit her

the Am79C978 controller or the host. The OWN bit

within the descr iptor status informati on, either TMD or

RMD, is used for this purpose.

When O WN is set t o 1, it signifi es tha t the A m79C97 8

controlle r currently has owne rship of this r ing descrip-

tor and i ts associate d bu ffer. O nl y the owne r is per m it-

ted to relinquish ownership or to write to any field in the

descripto r entr y. A devic e that is no t the cu rrent owner

of a descriptor entry cannot assume ownership or

change any field in the entry. A device may, however,

read from a descriptor that it does not currently own.

Software should always read descriptor entries in se-

quential order . When software finds that the current de-

scriptor is owned by the Am79C978 controller , then the

software must not read ahead to the next descriptor.

The software should wait at a descriptor it does not own

until the Am79C978 controller sets OWN to 0 to re-

lease ownership to the software. When LAPPEN

(CSR3, bi t 5) is set to 1, this rule i s modi fied. See the

LAPPEN description. At initialization, the Am79C978

controlle r reads the base add ress of both the transmit

and receive descriptor rings into CSRs for use by the

Am79C978 controller during subsequent operations.

Am79C978 61

Figure 33 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

Note that th e value of CSR2, b its 15-8, is us ed as th e

upper 8-bits for all memory addresses during bus mas-

ter transfers.

Figure 34 i llustrates when SSIZE32 is set to 1, the re-

lationship between the initialization base address, the

initialization block, the receive and transmit descriptor

ring base addresses, the receive and transmit descrip-

tors, and the receive and transmit data buffers.

Figure 33. 16-Bit Software Model

22206B-36

Initialization

Block

IADR[15:0]IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLE RES RDRA[23:16]

TLE RES TDRA[23:16]

Rcv

Buffers

RMD RMD RMD RMD

Rcv Descriptor

Ring

NNNN•••

1st desc.

start 2nd

desc.

RMD0

Xmt

Buffers

TMD TMD TMD TMD

Xmt Descriptor

Ring

MMMM•••

1st desc.

start 2nd

desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

62 Am79C978

Figure 34. 32-Bit Software Model

Polling

If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity

being performed by the Am79C978 controller, then the

Am79C978 controller will periodically poll the current

receive and transmit descriptor entries in order to as-

certain their ownership. If the DPOLL bit in CSR4 is set,

then the transmit polling function is disabled.

A typic al pol li ng o per atio n co ns ists of th e followin g s e-

quence. TheAm79C978 controller will use the current

receive descriptor address stored internally to vector to

the appropriate Receive Descriptor Table Entry

(RDTE). It wil l then use the current transm it desc riptor

address (stored intern ally) to vect or to the appropr iate

T ransmit Descriptor Table Entry (TDTE). The accesses

will be made in the following order: RMD1, then RMD0

of the current RDTE during one bus arbitration, and

after that, TMD1, the n TMD0 of the current TDTE dur -

ing a second bus arbitration. All information collected

during polling activity will be stored internally in the ap-

propriate CSRs, if the OWN bit is set (i.e., CSR18,

CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,

CSR52).

A typical receive poll is the product of the following con-

ditions:

1. The co ntroller d oes n ot ow n the curren t RDTE and

the poll time has elapsed and RXON = 1 (CSR0,

bit 5), or

2. The controller does not own the next RDTE and

ther e is m ore th an on e r ec eive de scr ipto r i n t he r ing

and the poll time has elapsed and RXON = 1.

If RXON is clea red to 0, the Am79C978 controller will

never poll RDTE locations.

In order to avoid missing frames, the system should

have at least one RDTE available. To minimize poll ac-

tivity, two RDTEs should be available. In this case, the

poll operation will only consist of the check of the status

of the current TDTE.

A typical transmit poll is the product of the following

conditions:

Initialization

Block

CSR1CSR2

RMD RMD RMD RMD

Rcv Descriptor

Ring

NNNN

•••

1st

desc.

start

2nd

desc.

start

RMD

TMD0 TMD1 TMD2 TMD3

Xmt Descriptor

Ring

MMMM

•••

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16] IADR[15:0]

TLE

RES

RLE

RES

MODE

PADR[47:32]

RES LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

22206B-37

Am79C978 63

1. The contro ller does not own the curr ent TDTE and

TXDPOLL = 0 (CSR4, bit 12) and TXON = 1 (CSR0,

bit 4) and the poll time has elapsed, or

2. The contro ller does not own the curr ent TDTE and

TXDPOLL = 0 and TXON = 1 and a frame has jus t

been received, or

3. The contro ller does not own the curr ent TDTE and

TXDPOLL = 0 and TXON = 1 and a frame has jus t

been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll. If the mi-

crocode is not executing the poll counting code when

the TDMD bit is set, then the demanded poll of the

TDTE will be delayed until the microcode returns to the

poll counti ng cod e.

The user may change the poll time va lue from the de-

fault of 65,536 clock per iods by modi fying the val ue i n

the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) ac-

cess, the Am79C978 c ontroll er finds that the OWN bit

of that TDTE is not set, the Am79C978 controller re-

sumes the poll time count and re-examines the same

TDTE at the next expiration of the poll time count.

If the OWN bit of the TDTE is set, but the Start of

Packet (STP) bit is not set, the Am79C978 controller

will immediately request the bus in order to clear the

OWN bit of this descriptor. (This condition would nor-

mally be found following a late collision (LCOL) or retry

(RTRY) error that occur red in the middl e of a transmit

frame cha in of buffers.) After rese tting the OWN bit of

this des criptor, the Am79 C978 co ntrol ler will aga in im-

mediately request the bus in order to access the next

TDTE location in the ri ng.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. In the C-LANCE device, the buffer

length of 0 is inte rp reted as a 4 096-byte b uffer. A zer o

length buffer is acceptable a s long as it is not th e last

buffer in a chain (STP = 0 and ENP = 1).

If the OWN bit and STP are set, then microcode control

proceeds to a routine that will enable transmit data

transfers to the FIFO. TheAm79C978 controller will

look ahead to the next transmit descriptor after it has

perform ed at lea st one tran smit dat a transf er from th e

first buffer.

If the Am79C978 controller does not own the next

TDTE (i.e., the second TDTE for this frame), it will com-

plete transmission of the current buffer and update the

status of the current (first) TDTE with the BUFF and

UFLO bits being set. If DXSUFLO (CSR3, bit 6) is

cleared to 0, the underflow error will cause the trans-

mitter to be disabled (CSR0, TXON = 0).

TheAm79C978 controller will have to be re-initialized to

restore the transmit function. Setting DXSUFLO to 1

enables the Am79C978 controller to gracefully recover

from an underflow error . The device will scan the trans-

mit descriptor ring until it finds either the start of a new

frame or a TDTE it does not own. To avoid an underflow

situation in a chained buffer transmission, the system

should always set the transmit chain descriptor own

bits in re vers e order.

If the Am79C978 controller does own the second TDTE

in a chain, it will gradually empty the contents of the first

buffer (as th e b ytes are ne eded by the trans mi t o pera-

tion), perform a single-cycle DMA transfer to update

the status of the first descriptor (clear the OWN bit in

TMD1), and then it may perform one data DMA access

on the sec on d bu ffer in the cha in bef or e exec uti ng an-

other lookahead operation. (i.e., a lookahead to the

third descriptor.)

It is imperative that the host system never reads the

TDTE OWN bits out of order . TheAm79C978 controller

normally clears OWN bits in strict FIFO order. How-

ever, the Am79C978 controller can queue up to two

frames in the transmit FIFO. When the second frame

uses buffer chaining, the Am79C978 controller might

return owner ship out of normal FIFO orde r. The OWN

bit for the last (and maybe only) buffer of the first frame

is not cleared until transmission is completed. During

the transmission the Am79C978 controller will read in

buffers for the ne xt frame a nd cle ar their OW N bits for

all but the last one. The first and all intermediate buffers

of the second frame can have the ir OWN bits cleared

before th e Am79 C978 contr oller returns own ership for

the last buffer of the first frame.

If an error occurs in t he transmission before all of the

bytes of the current buffer have been transferred,

transmit status of the current buffer will be immediately

updated. If the buffer does not contain the end of

packet, the Am79C978 controller will skip over the rest

of the fr am e w hic h ex peri enc ed th e e rror. This is don e

by returning to the polling microcode where the

Am79C 978 control ler will cl ear the OW N bit for all de-

scriptors with OWN = 1 and STP = 0 and continue in

like man ner until a de scriptor with OWN = 0 (no more

transmit frames in the ring ) or OWN = 1 and STP = 1

(the first buffer of a new frame) is reached.

At the end of any transmit operation, whether success-

ful or with errors, immediately following the completion

of the descriptor updates, the Am79C978 controller will

always perform another polling operation. As described

earlier, this polli ng operation wil l begin with a check of

the current RDTE, unless the Am79C978 controller al-

ready own s that descrip tor. Then the Am7 9C978 con-

troller will poll the next TDTE. If the transmit descriptor

OWN bit has a 0 value, the Am79C978 controller will

64 Am79C978

resume incrementing the poll time counter. If the trans-

mit descriptor OWN bit has a value of 1, the Am79C978

controller will begin filling the FIFO with transmit data

and initiate a transmission. This end-of-operation poll

coupled with the TDTE lookahead operation allows the

Am79C978 controller to avoid inserting poll time counts

between successive transmit frames.

By default, whenever the Am79C978 controller com-

pletes a transmit frame (either with or without error)

and writes the status information to the current descrip-

tor , then the TINT bit of CSR0 is set to indicate the com-

pletion of a transmission. This causes an interrupt

signal if the IENA bit of CSR0 has been set and the

TINTM bit of C SR3 is c lear ed. TheA m7 9C97 8 c ont ro l-

ler provides two modes to reduce the number of trans-

mit interrupts. The interrupt of a successfully

transmitted frame can be suppressed by setting TIN-

TOKD (CSR5, bit 15) to 1. Another mode, which is en-

abled by setting LTINTEN (CSR5, bit 14) to 1, allows

suppres sion of i nterrupts for successf ul transmiss ions

for all but the last frame in a sequence.

Receive Descriptor Table Entry

If the Am79C978 controller does not own both the cur-

rent and the next Receive Descriptor Table Entry

(RDTE), then the Am79C978 controller will continue to

poll according to the polling sequence described

above. If the receive descriptor ring length is one, then

there is no next descriptor to be polled.

If a poll operation has revealed that the current and the

next RDTE belong to the Am79C978 controller, then

additional poll accesses are not necessary. Future poll

operatio ns will no t include RDTE accesses as long as

the Am79C978 controller retains ownership of the cur-

rent and the next RDTE.

When receive activity is present on the channel, the

Am79C978 controller waits for the complete address of

the message to arrive. It then decides whether to ac-

cept or reject the frame based on all active addressing

schemes. If the frame is accepted, the Am79C978 con-

troller c heck s the cur rent rece ive b uffer status r egis ter

CRST (CSR41) to determine the ownership of the cur-

rent buffer.

If ownership is lacking, the Am79C978 controller will

immediately perform a final poll of the current RDTE. If

ownership is still denied, the Am79C978 controller has

no buffer in which to store the incoming message. The

MISS bit will be set in CSR0 and the Missed Frame

Coun t er (C SR 112) wil l b e in cr em e nte d. An o t her po l l of

the current RDTE will not occur until the frame has fin-

ished.

If the Am79C978 controller sees that the last poll (ei-

ther a normal poll, or the final effort described in the

above paragraph) of the current RDTE shows valid

ownership, it proceeds to a poll of the next RDTE. Fol-

lowing this poll, and regardless of the outcome of this

poll, transfers of receive data from the FIFO may begin.

Regardless of ownership of the second receive de-

scriptor, the Am 79C978 controller will cont inue to per -

form receive data DMA transfers to the first buffer . If the

frame le ngth ex ce eds th e l engt h of the fir st buffer, and

the Am79C978 controller does not own the second

buffer, ownership of the current descriptor will be

passed ba ck to the system b y writing a 0 to the OW N

bit of RMD1. Status will be written indicating buffer

(BUFF = 1) and possibly overflow (OFLO = 1) errors.

If the fra me len gth ex ceeds th e leng th of th e fir st (cur-

rent) buffer, and the Am79C978 controller does own

the second (next) buffer, ownership will be passed

back to the system by writing a 0 to the OWN bit of

RMD1 wh en the first b uffer is ful l. The OWN bit is the

only bi t modifie d in th e desc ript or. Receive data tran s-

fers to the second buffer may occur before the

Am79C978 controller proceeds to look ahead to the

ownership of the third buffer. Such action will depend

upon the state of the FIFO when the OWN bit has been

updated i n the fir st descr iptor. In any cas e, looka head

will be performed to the third buffer and the information

gathered will be stored in the chip, regardless of the

state of the ownership bit.

This activity continues until the Am79C978 controller

recognizes the completion of the frame (the last byte of

this receive message has been removed from the

FIFO). The Am79C978 c ontroller will subsequently up-

date the current RDTE status with the end of frame

(ENP) indication set, write the message byte count

(MCNT) for the en tire fram e into RMD2 , and overwr ite

the “current” entries in the CSRs with the “next” entries.

Receive Fra me Queuing

TheAm79C978 controller supports the lack of RDTEs

when SRAM (SRAM SIZE in BCR 25, bits 7-0) is en-

abled through the Receive Frame Queuing mecha-

nism. When the SRAM SIZE = 0, then the Am79C978

controller reverts back to the PCnet-PCI II mode of op-

eration. This operation is automatic and does not re-

quire any programming by the host. When SRAM is

enabled, the Receive Frame Queuing mechanism al-

lows a slow protocol to manage more frames without

the high frame loss rate normally attributed to FIFO-

based network controllers.

TheAm79C978 controller will store the incoming

frames in the extended FIFOs until polling takes place,

if enabled and it discovers it owns an RDTE. The stored

frames are not altered in any way until written ou t into

system buffers. When the receive FIFO overflows, fur-

ther incoming receive frames will be missed during that

time . As soon as the ne twork re ceive FIFO is empty, in-

coming frames are processed as normal. Status on a

per frame basis is not kept during the overflow process.

Am79C978 65

Statistic counters are maintained and accurate during

that time.

During the time that the Receive Frame Queuing

mechanism is in operation, the Am79C978 controller

relies on the Receive Poll Time Counter (CSR 48) to

control the worst case access to the RDTE. The Re-

ceive Poll Time Counter is programmed through the

Receive Polling Interval (CSR49) register. The Re-

ceived P olling In terv al defau lts to ap proxim ately 2 ms .

TheAm79C978 controller will also try to access the

RDTE during normal descriptor accesses whether they

are transmit or receive accesses. The host can force

the Am79C978 controller to immediately access the

RDTE by setting the RDMD (CSR 7, bit 13) to 1. Its op-

eration is similar to the transmit one. The polling pro-

cess can be disabled by setting the RXDPOLL (CSR7,

bit 12) bit. This will stop the automatic polling process

and the host must set the RDMD bit to initiate the re-

ceive process into host memory. Receive frames are

still stored even when the receive polling process is

disabled.

Software Interrupt Timer

TheAm79C978 controller is equipped with a software

programmable free-running interrupt timer . The timer is

constantly running and will generate an interrupt STINT

(CSR 7, bit 11) when STINI TE (CSR 7, bit 10) is se t to

1. After generating the interrupt, the software timer will

load t he value st ored in STVAL a nd restart. T he timer

value STVAL (BCR31, bits 15-0) is interpreted as an

unsigned number with a resolution of 256 Time Base

Clock periods. For instance, a value of 122 ms would

be programmed with a value of 9531 (253Bh), if the

Time Base Clock is running at 20 MHz. The default

value of STVAL is FFFFh which yields the approximate

maximum 838 ms time r d ur ation. A write to S TVAL r e-

starts the timer with the new contents of STVAL.

10/100 Media Access Controller

The Media Access Controller (MAC) engine incorpo-

rates the ess enti al prot ocol req uirem ents for ope ration

of an Ethernet/IEEE 802.3-compliant node and pro-

vides the interface between the FIFO subsystem and

the internal PHY.

This section describes operation of the MAC engine

when operating in half-duplex mode. When operating

in half-duplex mode, the MAC engine is fully compliant

to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standa rd

1990 Second Edition) and ANSI/IEEE 802.3 (1985).

When operating in full-duplex mode, the MAC engine

behavior changes as described in the section Full-

Duplex Operation.

The MAC engine provides programmable enhanced

features designed to minimize host supervision, bus

utilization, and pre- or post-message processing.

These features include the ability to disable retries after

a collision, dynamic FCS generation on a frame-by-

frame ba si s, automatic pa d fi el d i ns ert io n an d d ele tio n

to enforce minimum frame size attributes, automatic re-

transmission without reloading the FIFO, and auto-

matic deletion of collision fragments.

The two primary attributes of the MAC engine are:

nTransmit and receive message data encapsulation

—Framing (frame boundary delimitation, frame

synchronization)

—Addressing (source and destination address

handling)

—Error detection (physical medium transmission

errors)

nMedia access management

—Medium allocation (collision avoidance, except

in full-duplex operation)

—Contention resolution (collision handling, except

in full-duplex operation)

Transmit and Receive Message Data

Encapsulation

The MAC engine provides minimum frame size en-

forcement for transmit and receive frames. When

APAD_XMT (CSR, bit 11) is set to 1, transmit mes-

sages will be padded with sufficient bytes (containing

00h) to ensure that the receiving station will observe an

information field (destination address, source address,

length/type, data, and FCS) of 64 bytes. When

ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will

automatically strip pad bytes from the received mes-

sage by obs erving the valu e in the length field and by

stripping excess bytes if this value is below the mini-

mum data size (46 bytes). Both features can be inde-

pendently over-ridden to allow illegally short (less than

64 bytes of frame data) messages to be transmitted

and/or received. The use of this feature reduces bus

utilization because the pad bytes are not transferred

into or out of main memory.

Framing

The MAC engine will autonomously handle the con-

str uctio n of the tra nsmit frame . Once th e transm it FIF O

has been fi lled to the prede termined thres hold (set by

XMTSP in CSR80) and access to the channel is cur-

rently permitted, the MAC engine will commence the 7-

byte preamble sequence (10101010b, where first bit

transmitte d is a 1 ). T he M AC en gine will s ubseq uen tly

append the Start Frame Delimiter (SFD) byte

(10101011b) followed by the serialized data from the

transmit FIFO. Once the data has been completed, the

MAC engi ne will appe nd the FCS (most sig nificant bit

first), which was computed on the entire data portion of

the frame. The data portion of the frame consists of

destinat ion addres s, source a ddress, le ngth/type, an d

frame data. The user is responsible for the correct or-

66 Am79C978

dering and content in each of these fields in the frame.

The MAC does not use the content in the length/type

field unless APAD_XMT (CSR4, bit 11) is set and the

data portion of the frame is shorter than 60 bytes.

The MAC engine will detect the incoming preamble se-

quence whe n the RX _DV si gnal is a ctiva ted by the i n-

ternal PHY. The MAC will discard the preamble and

begin searching for the SFD. Once the SFD is de-

tected, all subsequent nibbles are treated as part of the

frame. T he MAC engine will insp ect the length fi eld to

ensure minimum frame size, strip unnecessary pad

characters (if enabled), and pass the remaining bytes

through the receive FIFO to the host. If pad stripping is

performed, the MAC en gin e w ill also s trip the recei ve d

FCS bytes, although normal FCS computation and

checking will occur. Note that apart from pad stripping,

the frame wi ll be passed un modified to the hos t. If the

length field has a value of 46 or greater , all frame bytes

including FCS will be passed unmodified to the receive

buffer, regardless of the actual frame length.

If the frame terminates or suffers a collision before 64

bytes of information (after SFD) have been received,

the MAC engine will automatically delete the frame

from the receive FIFO, without host intervention.

TheAm7 9C978 co ntrolle r has th e abil ity to acc ept run t

packets for diagnostic purposes and proprietary net-

works.

Destination Address Handling

The firs t 6 bytes of i nformation after SFD w ill be inter -

preted as the destination address field. The MAC en-

gine provides facilities for physical (unicast), logical

(multicast), and broadcast address reception.

Error Detect ion

The MAC engine provides several facilities which re-

port and recover from errors on the medium. In addi-

tion, it protects the network from gross errors due to

inabili ty of the ho st to keep pa ce w ith the MA C engin e

activity.

On completion of transmission, the following transmit

status is available in the appropriate Transmit Message

Descriptor (TMD) and Control and Status Register

(CSR) areas:

nThe number of transmission retry attempts (ONE,

MORE, RTRY, and TRC).

nWhether the MAC engine had to Defer (DEF) due to

chann el activ it y.

nExcessive deferral (EXDEF), indicating that the

transmitter experienc ed Excessiv e Deferral on this

transmit frame, where Excessive Deferral is defined

in the ISO 8802-3 (IEEE/ANSI 802.3) standard.

nLoss of Carrier (LCAR), indicating that there was an

interruption in the ability of the MAC engine to mon-

itor its own transmission. Repeated LCAR errors in-

dicate a potentially faulty transceiver or network

connection.

nLate Collision (LCOL) indicates that the transmis-

sion suffered a collision after the slot time. This is in-

dicative of a badly configured network. Late

collisions should not occur in a normal operating

network.

nCollision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the first 4 ms after a transmis sion was com-

pleted. This may be due to a failed transceiver, dis-

connected or faulty transceiver drop cable, or

because the transce iver does not support th is fea-

ture (or it is disabled). SQE Test is only valid for 10-

Mbps networks.

In addition to the reporting of network errors, the MAC

engine w ill also attempt to preve nt the creation of any

network error due to the in ability of the host t o servic e

the MAC engine. During transmission, if the host fails

to keep the t ra ns mit FIFO fi lled s uffici entl y, cau sing a n

underflow , the MAC engine will guarantee the message

is either sent as a runt packet (which will be deleted by

the receiving station) or as an invalid FCS (which will

also cause the receiver to reject the message).

The status of each receive message is available in the

appropriate Receive Message Descriptor (RMD) and

CSR areas. All received frames are passed to the host

regardless of any error. The FRAM error will only be re-

ported if an FCS error is detected and there is a non-

integral number of bytes in the message.

During the reception, the FCS is generated on every

nibble (including the dribbling bits) coming from the ca-

ble, although the internally saved FCS value is only up-

dated on the eighth bit (on each byte boundary). The

MAC engine will ignore up to 7 additional bits at the end

of a message (dribbling bits), which can occur under

normal network operating conditions. The framing error

is reported to the user as follows:

nIf the number of dribbling bits are 1 to 7 and there is

no FCS error, then there is no Framing error

(FRAM = 0).

nIf the number of dribbling bits are 1 to 7 and there is

a FCS error, then there is also a Framing error

(FRAM = 1).

nIf the number of dribb ling bits is 0, t hen there i s no

Framing er ror. There ma y or ma y not be a FCS er -

ror.

nIf the number of dribb ling bits is 8, t hen there i s no

Framing error. FCS error will be reported, and the

receive message count will indicate one extra byte.

Counters are provided to report the Receive Collision

Count and Runt Packet Count for network statistics

and utilization calculations.

Am79C978 67

Media Access Management

The basic requirement for all stations on the network is

to provide fairness of channel allocation. The IEEE

802.3/Ethernet protocols define a media access mech-

anism which permits all stations to access the channel

with equal ity. Any node can attempt to cont end for the

channel by waiting for a predetermined time (Inter

Packet Gap) after the last activity, before transmitting

on the media. The ch annel is a multid rop commun ica-

tions media (with various topological configurations

permitted), which allows a single station to transmit and

all other stations to receive. If two nodes simulta-

neously contend for the channel, their signals will inter-

act causing loss of data, defined as a collision. It is the

responsibility of the MAC to attempt to avoid and

recover from a collision and to guarantee data integrity

for the end-to-end transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)

requires tha t the CSMA /CD MAC mon itor the med ium

for traffic by watching for carrier activity. When carrier

is detected, the media is considered busy, and the

MAC should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also

allows optionally a two-part deferral after a receive

message.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: “It is possible f or the PLS ca rrier sense indica-

tion to fail t o b e as serted durin g a c ollisi on on the m e-

dia. If the deference process simply times the inter-

frame gap based on this i ndication, it is possible for a

short in terframe gap to be ge nerated, lead ing to a po-

tential re ception fail ure of a subsequent frame. To en-

hance system robustness, the following optional

measures (as specified in 4.2.8) are recommended

when InterFrameSpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset th e i nte r-frame gap ti ming if carri er sens e b e-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer sha ll no t b e res et to ens ure fai r acce ss t o

the m e di u m. A n i n itia l pe r i o d s hor t er t han 2 / 3 o f the

interval is permissible including 0.”

The MAC engine implements the optional receive two-

part deferral algorithm, with an InterFrameSpacing-

Part1 time of 6.0 ms. The InterFrameSpacingPart 2 in-

terval is, therefore, 3.4 ms.

TheAm7 9C978 control ler will pe rform the two- part de-

ferral algor ithm as specified in the Process Deferenc e

section. The Inter Packet Gap (IPG) timer will start tim-

ing the 9.6 ms InterFrameSpacing after the receive car-

rier is deasserted. During the first part deferral

(In terFrameSpacingPart1 - IFS1) , the Am79C978 con-

troller will defer any pending transmit frame and re-

spond to the receive message. The IPG counter will be

cleared to 0 continuously until the carrier deasserts, at

which point the IPG counter will resume the 9.6 ms

count once again. Once the IFS1 period of 6.0 ms has

elapsed, the Am79C978 controller will begin timing the

second part deferral (InterFrameSpaci ngPart2 - IFS2)

of 3.4 ms. Once IFS1 has completed and IFS2 has

commenced, the Am79C978 controller will not defer to

a receive frame if a transmit frame is pending. This

means that the Am79C978 controller will not attempt to

receive the receive fram e, since it will start to transmit

and generate a collision at 9.6 ms. TheAm79C978 con-

troller wil l co mpl ete the pream ble (64-bit) and jam (32-

bit) sequence b efore ceasing transmission and invok-

ing the random backoff algorithm.

TheAm79C978 controller allows the user to program

the IPG and the first-part deferral

(InterFrameSpacingPart1 - IFS1) through CSR125. By

changing the IPG default value of 96 bit times (60h),

the user can adjust the fairness or aggressiveness of

the MAC on the network. By programming a lower

number o f bi t tim es tha n th e IS O/IEC 8 802 -3 st and ar d

requires, the MAC engine will become more aggres-

sive on the network. This aggressive nature will give

rise to the Am79C978 controller possibly capturing the

network at times by forcing other less aggressive com-

pliant nodes to defer . By programming a larger number

of bit times, the MAC will become less aggressive on

the network and may defer more often than normal.

The perform anc e of th e Am7 9C97 8 co ntr oller may de-

crease as the IPG value is increased from the de fault

value, but the res ult in g beh av ior may imp ro ve netwo rk

performance by reducing collisions. TheAm79C978

controller uses the same IPG for back-to-back trans-

mits and receive-to-transmit accesses. Changing IFS1

will alter the period for which the MAC engine will defer

to incoming receive frames.

CAUTION: Care must be exercised when altering

these parameters. Adverse network activity could

result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disa bled using the

DXMT2PD bit in CSR3. The IFS1 programming will

have no effect when DXMT2PD is set to 1, but the IPG

programming value is still valid. Two part deferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver should

generate the SQE Test message within 0.6 to 1.6 ms

after the transmission ceases. During the time period in

68 Am79C978

which the SQE Test message is expected, the

Am79C978 controller will not respond to receive carrier

sense.

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the co nclusion o f the output fu nction, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when

the CARRIER_STATUS becomes

CARRIER_OFF. If execution of the output function

does not cause CARRIER_ON to occur, no SQE

test occurs in the DTE. The duration of the window

shall be at least 4.0 µs but no more than 8.0 µs.

During the time window the Carrier Sense Function

is inhibited.”

TheAm79C978 controller implements a carrier sense

“blinding” period of 4.0 µs length starting from the deas-

sertion of carrier sense af ter transmission. This effec-

tively means that when transmit two-part deferral is

enabled (DXMT2PD is cleared), the IF S1 time is from

4 ms to 6 ms after a transmission. However, since IPG

shrinkag e below 4 ms wi ll rarely be encountered on a

correctly configured network, and since the fragment

size will be larger than the 4 ms blinding window, the

IPG counter will be reset by a wo rst case I PG shrink-

age/fragment scenario and the Am79C978 controller

will defer its transmission. If carrier is detected within

the 4.0 to 6.0 ms IFS1 period, the Am79C978 control ler

will not restart the “blinding” period, but only restart

IFS1.

Collision Handling

Collision detection is performed and reported to the

MAC engine via the COL input pin.

If a collision is detected before the complete preamble/

SFD seque nce has been tran sm itt ed, the MAC eng in e

will compl ete the preamble/ SFD before append ing the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits

being transmitted, the MAC engine will abort the trans-

mission and append the jam sequence immediately.

The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be rescheduled to a

time deter mined by the random bac koff algor ithm. If a

single retry was required, the 1 bit will be set in the

transmit frame status. If more than one retry was re-

quired, the MORE bi t will be s et. If all 1 6 attempts ex-

perienced collisions, the RTRY bit will be set (1 and

MORE will be clear), and the transmit message will be

flushed from the FIFO. If retries have been disabled by

setting the DRTY bit in CSR15, the MAC engine will

abandon tr an sm is si on o f the fr ame on d ete cti on of th e

first collision. In this case, only the RTRY bit will be set,

and the transmit message will be flushed from the

FIFO.

If a co llision is d etected after 512 bit times ha ve been

transmi tte d, the co ll is io n is termed a late colli s ion . The

MAC engine will abort the transmission, append the

jam sequ ence, and set the LCOL bi t. No retry at tempt

will be scheduled on detection of a late collision, and

the transmit message will be flushed from the FIFO.

The ISO 8802- 3 (I EEE /ANS I 802 .3) Sta ndar d requ ir es

use of a “truncated binary exponential backoff” algo-

rithm, which provides a controlled pseudo random

mechanism to enforce the collision backoff interval,

before retransmission is attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the

CSMA/CD sublayer delays before attempting to re-

transmit the frame. The delay is an integer multiple

of slot time. The n umb er of s lot t imes to de lay be-

fore the nth retra nsmi ssio n atte mpt is cho se n as a

uniformly distributed random integer r in the range:

0 ≤ r < 2k Where k = Min (N,10).”

TheAm7 9C97 8 co ntr oller prov id es an al ternative al go-

rithm, which suspends the counting of the slot time/IPG

during the time that receive carrier se nse is detected.

This aids in networks where large numbers of nodes

are present, and numerous nodes can be in collision. It

effectively accelerates the increase in the backoff time

in busy networ ks and al lows no des no t invo lved i n the

collision to access the channel, while the colliding

nodes await a reduction in channel activity . Once chan-

nel activity is reduced, the nodes resolving the collision

time-out their slot time counters as normal.

This modified backoff algorithm is enabled when EMBA

(CSR3, bit 3) is set to 1.

Transmit Operation

The trans mi t op erati on a nd featu r es of th e A m7 9C97 8

controller are controlled by programmable options.

TheAm79C978 controller offers a large transmit FIFO

to provide frame buffering for increased system la-

tency, automatic retransmission with no FIFO reload,

and automatic transmit padding.

Transmit Function Programming

Autom atic transmit fe atures suc h as retry on co llision,

FCS generation/transmission, and pad field insertion

can all b e pr ogram med to p ro vide flexi bili ty in the (re- )

transmission of messages.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

Am79C978 69

Automatic pad field insertion is controlled by the

APAD_XMT bit in CSR4.

The disable FCS generation/transmission feature can

be programmed as a static feature or dynamically on a

frame-by-fr ame b asis.

Transmit FIFO Watermark (XMTFW) in CSR80 sets

the point at which the BMU requests more data from

the transmit buffers for the FIFO. A minimum of

XMTFW em pty spac es must be av ailable in th e trans-

mit FIFO before the BMU will request the system bus in

order to transfer transmit frame data into the transmit

FIFO.

Transmit Start Point (XMTSP) in CSR80 sets the point

when the transmitter actually attempts to transmit a

frame onto the media. A minimum of XMTSP bytes

must be written to the transmit FIFO for the current

frame before tr ansmi s sion of the curr ent frame will be-

gin. (When automatically padded packets are being

sent, it is conceivable that the XMTSP is not reached

when all of the data has been trans ferred to the FIFO .

In this case, the transmission will begin when all of the

frame data has been placed into the transmit FIFO.)

The default value of XMTSP is 01b, meaning there has

to be 64 bytes in the transmit FIFO to start a transmis-

sion.

Automatic Pa d Generation

Transmit frames can be automatically padded to ex-

tend the m to 64 d ata by tes (exc l udi ng p reamb le). This

allows the minimum frame size of 64 bytes (512 bits)

for IEEE 802.3/Ethernet to be guaranteed with no soft-

ware intervention from the host/controlling process.

Settin g the APAD_XM T bit in C SR4 enable s the auto-

matic pa dding feature. T he pa d is pla ced betwee n the

LLC data fiel d and FCS fie ld in the IEEE 802 .3 frame.

FCS is always added if the frame is padded, regardless

of the state of DX MTF CS (CSR1 5, bi t 3) or A DD_FCS

(TMD1, bit 29). The transmit frame will be padded by

bytes with the value of 00h. The default value of

APAD_XMT is 0, which will disable automatic pad gen-

eration afte r H_RESE T.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC data

bytes encapsulated in the frame (length field as defined

in the ISO 8802-3 (IEEE/ANSI 802.3) standard). The

length value contained in the message is not used by

the Am79C978 controller to compute the actual num-

ber of pad bytes to be inserted. TheAm79C978 control-

ler will append pad bytes dependent on the actual

number of bi ts transm itted ont o the networ k. Once the

last dat a byte of the frame has c omple ted, pri or to ap-

pending th e FCS, the Am79 C978 controll er will check

to ensure that 544 bits have been transmitted. If not,

pad bytes are added to extend the frame size to this

value, and the FCS is then added. See Figure 35.

The 544 bit count is derived from the following:

Minimu m f ra me si ze ( ex cludi ng pr ea mbl e/S FD,

including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

The 544 bit count is derived from the following:

Minimu m f ra me si ze ( ex cludi ng pr ea mbl e/S FD,

including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble/SFD + (Min Frame Size - FCS)

64 + (512-32) = 544 bits

A minimum length transmit frame from theAm79C978

controller , therefore, will be 576 bits after the FCS is ap-

pended.

Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

Preamble

1010....1010 SFD

10101011 Destination

Address Source

Address Length LLC

Data Pad FCS

Bytes

46 – 1500

Bytes

Bits

22206B-38

70 Am79C978

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(CSR15, b it 3). I f DX MTFCS is clear ed to 0, the trans -

mitter will generate and append the FCS to the trans-

mitted frame. If the automatic padding feature is

invoked (APAD_XMT is set in CSR4), the FCS will be

appended by theAm79C978 controller regardless of

the state of DXMTFCS or ADD_FCS (TMD1, bit 29).

Note that the calculated FCS is transmitted most signif-

icant bit fir st . The de fau lt v al ue of DXM TFCS is 0 af ter

H_RESET.

ADD_FCS ( TMD 1, bit 29) al lows the autom atic ge ner-

ation and transmission of FCS on a frame-by-frame

basis. DXMT FCS s hould b e cleared to 0 in this mode .

To generate FCS for a frame, ADD_FCS must be set in

all descriptors of a frame (STP is set to 1). Note that bit

29 of TMD1 has the function of ADD_FCS if SWSTYLE

(BCR20, bits 7-0) is programmed to 0, 2, or 3.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distin ct cate gories : those cond ition s whic h are the

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal events which may occur and which are handled

autonom ousl y by theAm79C978 co ntr ol le r inc lud e co l-

lisions within the slot time with automatic retry.

TheAm79C978 controller will ensure that collisions

which occur within 512 bit times from the start of trans-

mission (including preamble) will be automatically re-

tried with no host intervention. The transmit FIFO

ensures this by guaranteeing that data contained within

the FIFO will not be over written until a t least 64 by tes

(512 bits) of preamble plus address, length, and data

fields have bee n transmitted onto the network without

encountering a collision. Note that if DRTY (CSR15, bit

5) is se t to 1 or if the network int erface is op erating in

full-duplex mode, no collision handling is required, and

any byte of fram e data in the F IFO can be overwri tten

as soon as it is transmitted.

If 16 total attempts (initial attempt plus 15 retries) fail,

theAm79C978 controller sets the RTRY bit in the cur-

rent transmit TDTE in host memory (TMD2), gives up

ownership (resets the OWN bit to 0) for this frame, and

processes the next frame in the transmit ring for trans-

mission.

Abnormal network conditions include:

nLoss of carrier

nLate collision

nSQE Test Error (does not apply to 100 Mbps net-

works.)

These conditions should not occur on a c orrectly c on-

figured IEEE 802.3 network operating in half-duplex

mode. If they do, they will be reported. None of these

conditions will occur on a network operating in full-

duplex mode. (See the section Full-Duplex Operation

for more detail.)

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the

current descriptor. The OWN bit(s) in the subsequent

descriptor(s) will be cleared until the STP (the next

frame) is found.

Loss of Carrier

LCAR will be reported for every frame transmitted if

theAm79C978 controller detects a loss of carrier.

Late Collision

A late collision will be reported if a collision condition

occurs after one slot time (512 bit times) after the trans-

mit process was initiated (first bit of preamble com-

menced). TheAm79C978 controller will abandon the

transmit process for that frame, set Late Collision

(LCOL) in the as so ci ate d TM D2 , an d proc es s the next

transmit f rame in the rin g. Frames experien cing a late

collision will not be retried. Recovery from this condi-

tion must be performed by upper layer software.

SQE Test Er ror

If the network port is in Link Fail state, CERR will be

asser ted in the 10B ASE- T mode af ter trans mit. CE RR

will neve r cause INTA to be ac tivated. It will , however,

set the ERR bit CSR0.

Receive Opera tio n

The receive operation and features of theAm79C978

controller are controlled by programmable options.

TheAm79C978 controller offers a large receive FIFO to

provide frame buffering for increased system latency,

automatic flushing of collision fragments (runt packets),

automatic receive pad stripping, and a variety of ad-

dress match options.

Receive Function Programming

Autom atic pad field st ripping is ena bled by setti ng the

ASTRP_RCV bit in CSR4. This can provide flexibility in

the reception of messages using the IEEE 802.3 frame

format.

All receive frames can be accepted by setting the

PROM bit in CSR15. Acceptance of unicast and broad-

cast frames can be individually turned off by setting the

DRCVPA or DRCVBC bits in CSR15. The Physical Ad-

dress register (CSR12 to CSR14) stores the address

that theAm79C978 controller compares to the destina-

tion address of the incoming frame for a unicast ad-

dress match. The Logical Address Filter register

(CSR8 to CSR11) serve s as a hash fi lter for mul ticast

address match.

Am79C978 71

The point at which the BMU will start to transfer data

from the receive FIFO to buffer memory is controlled by

the RCVFW bits in CSR80. The default established

during H_RESET is 01b, which sets the watermark flag

at 64 bytes filled.

For test purposes, theAm79C978 controller can be pro-

grammed to accept runt packets by setting RPA in

CSR124.

Address Matching

TheAm79C978 controller supports three types of ad-

dress matching: unicast, multicast, and broadcast. The

normal address matching procedure can be modified

by programming three bits in CSR15, the mode register

(PROM, DRCVPA, and DRCVBC).

If the first bit received after the SFD (the least signifi-

cant bit of the first byte of the destination address field)

is 0, the frame is unicast, which indicates that the frame

is meant to be re ce iv ed by a sing le node. If t he firs t bit

received is 1, the frame is multicast, which indicates

that the frame is meant to be received by a group of

nodes. If the destination address field contains all 1s,

the frame is broadcast, which is a special type of multi-

cast. Frames with the broadcast address in the desti-

nation address field are meant to be received by all

nodes on the local area network.

When a unicast frame arrives at theAm79C978 control-

ler , the Am79C978 controller will accept the frame if the

destination address field of the incoming frame exactly

matches the 6-byte station address stored in the Phys-

ical Addr es s r eg ister s ( PADR, CSR1 2 to CSR1 4). T h e

byte ordering is such that the first byte received from

the network (after the SFD) must match the least signif-

icant byte of CSR12 (P ADR[7:0]), and the sixth byte re-

ceived mu st ma tc h the mos t si gni ficant byte of CSR1 4

(PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1,the

Am79C978 controller will not accept unicast frames.

If the incoming frame is multicast, the Am79C978 con-

troller performs a calculation on the contents of the

destination address field to determine whether or not to

accept the frame. This calculation is explained in the

Logical Address Filter (LADRF) bits description.

When all bits of the LADRF registers are 0, no multicast

frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special

multicast frames, they are treated differently by the

Am79C978 controller hardware. Broadcast frames are

always accepted, except when DRCVBC (CSR15, bit

14) is set and there is no Logical Address match.

None of the address filtering described above applies

when the Am79C978 controller is operating in the pro-

miscuous mode. In the promiscuous mode, all properly

formed packets are received, regardless of the con-

tents of their destination address fields. The promiscu-

ous mode overrides the Disable Receive Broadcast bit

(DRCVBC bit l4 in the MODE register) and the Disable

Receive Physical Address bit (DRCVPA, CSR15, bit

13).

TheAm79C978 controller operates in promiscuous

mode when PROM (CSR15, bit 15) is set.

The re ce ive descrip tor e ntr y RMD1 co nta ins th ree b its

that indicate which method of address matching

caused th e Am79C978 con troller to accept th e frame.

Note that these indicator bits are only available when

the Am79 C978 c ontr oller i s prog ramm ed to use 32- bit

structures for the descriptor entries (BCR20, bit 7-0,

SWSTYLE is set to 2 or 3).

Physical Address Match (P AM) (RMD1, bit 22) is set by

the Am79C978 controller when it accepts the received

frame due to a match of the frame’s destination ad-

dress with the content of the physical address register.

Logical Address Filter Match (LAFM) (RMD1, bit 21) is

set by the Am79C978 controller when it accepts the re-

ceived frame based on the value in the logical address

filter register.

Broadcast Address Match (BAM) (RMD1, bit 20) is set

by the Am79C978 controller when it accepts the re-

ceived frame bec aus e t he fr a me’s destinat ion add re ss

is of the type 'Broadcast.’

If DRCVBC (CSR15 , b it 14) i s c leare d t o 0 , on ly B AM,

but not LAFM will be set when a Broadcast frame is re-

ceived, even if the Logical Address Filter is pro-

grammed i n s uch a way th at a B r oad ca st frame woul d

pass the hash filter . If DRCVBC is set to 1 and the Log-

ical Address Filter is programmed in such a way that a

Broadc ast frame woul d pass the hash filter, LAFM will

be set on the reception of a Broadcast frame.

When the Am 79C978 con troll er op erates i n prom iscu-

ous mode and n one of the thr ee ma tch bi ts is s et, it is

an indication that the Am79C978 controller has only

accepted the frame because it was in promiscuous

mode.

When the A m79C978 contr oller is not pr ogrammed to

be in pro mis cuou s m ode, then when non e of t he three

match bits is set, it is an indication that the Am79C978

controlle r only accepte d the frame becau se it was not

rejected. See Table 10 for receive address matches.

72 Am79C978

Table 10. Receive Address Match

Automatic Pad Stripping

During reception of an IEEE 802.3 frame, the pad field

can be stripped automatically. Setting ASTRP_RCV

(CSR4, bi t 0) to 1 enable s the au tomati c pad str ippin g

feature. The pad field will be stripped before the frame

is pass ed t o the F IFO, thus pr eser v ing F IF O spa ce for

additiona l frames. The FCS f ield will al so be str ipped,

since it is computed at the transmitting station based

on the data and pad field characters, and will be invalid

for a receive frame that has had the pad characters

stripped.

The numb er of bytes to be stripped is c alculated from

the embedded length field (as defined in the ISO 8802-

3 (IEEE/ANSI 802.3) definition) contained in the frame.

The length indicates the actual number of LLC data

bytes contained in the message. Any received frame

which contains a length field less than 46 bytes will have

the pad fi eld s tripped (if ASTRP _RCV i s set) . Receiv e

frames which have a length field of 46 bytes or greater

will be passed to the host unmod ified.

Figure 36 shows the byte/bit ordering of the received

length field for an IEEE 802.3-compatible frame format.

Since any valid Ethernet T ype field value will always be

greater than a normal IEEE 802.3 Length field (≥46),

the Am79 C978 controll er will not attemp t to strip vali d

Ethernet frames. Note that for some network protocols,

the value passed in the Ethernet Type and/or IEEE

802.3 Length field is not compliant with either standard

and may cause problems if pad stripping is enabled.

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the Am79C978 controller.

Note that if the Auto matic Pad Stripping feature is en-

abled, the FCS for padded frames will be verified

against the value computed for the incoming bit stream

including pad characters, but the FCS value for a pad-

ded frame will not be passed to the host. If an FCS

erro r is de tect ed in any f rame, t he er ror w ill be repo rted

in the CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinc t c ate gor ies, i.e., those c on dit ion s w h ich ar e th e

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal events which may occur and which are handled

autonomously by the Am79C978 controller are basi-

cally collisions within the slot time and automatic runt

packet rejection . The Am 79C9 78 c ontr ol le r will ens ure

that collisions that occur within 512 bit times from the

start of reception (excluding preamble) will be automat-

ically deleted from the receive FIFO with no host inter-

vention.

The receive FIFO will delete any frame that is com-

posed of fewer than 64 bytes provided that the Runt

Packet Accept (RPA bit in CSR124) feature has not

been enabled and the network interface is operating in

half-duplex mode, or the full-duplex Runt Packet Ac-

cept Disable bit (FDRPAD, BCR9, bit 2) is set. This cri-

terion will be met regardless of whether the receive

frame was th e fi rst (or o nly) fr am e i n the FIFO or i f th e

receive frame was queued behind a previously re-

ceived message.

Abnormal network conditions include:

nFCS er rors

nLate collision

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

Buffer Management Unit section.

PAM LAFM BAM DRCVBC Comment

000 X

Frame accepted

due to PROM = 1

100 X

Physical address

match

010 0

Logical address

filter match;

frame is not of

type broadc as t

010 1

Logical address

filter match;

frame can be of

type broadc as t

0 0 1 0 Broadcast frame

Am79C978 73

Figure 36. IEEE 802.3 Frame and Le ngth Field Transmission Order

Loopback Operation

Loopback is a mod e of operation intended for system

diagnost ics. In t his mode , the trans mitter and receiv er

are both operating at the same time so that the

Am79C978 controller receives its own transmissions.

The Am79 C978 controller pr ovides two basi c types of

loopback. In internal loopback mode, the transmitted

data is looped back to the receiver inside the

Am79C978 c ontroller withou t actually tra nsmitting any

data to the external network. The receiver will move the

received data to the next receive buffer , where it can be

examined by software. Alternatively, in external loop-

back mode, data can be transmitted to and received

from the PHY.

Refer to Table 30 for various bit settings required for

Loopback modes.

The external loopback requires a two-step operation.

The internal PHY must be placed into a loopback mode

by writing to the PHY Control Register (BCR33,

BCR34). Then, the Am79C978 controller must be

placed into an external loopback mode by setting the

Loop bits.

Miscellaneous Loopback Features

All transmit and receive function programming, such as

automa tic trans mit padd ing and receive pad s tripping,

operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the

C-LANCE (Am79C90) software.

Since the Am79C97 8 controller has two FCS genera-

tors, there ar e no more r es tric tio ns on FCS gene ra tio n

or checking, or on testing multicast address detectio n

as they exist in the half-duplex PCnet family devices

and in the C-LANCE. On re ce iv e, t he A m79 C97 8 c on-

troller now provides true FCS status. The descriptor for

a frame with an FCS error will have the FCS bit (RMD1,

bit 27) set to 1. The FCS generator on the transmit side

can stil l be dis abled by se ttin g DXMTF CS (CSR 15, bi t

3) to 1.

In interna l loo pba ck ope ra tio n, the A m79 C978 con tro l-

ler provides a special mode to test the collision logic.

When FCOLL (CSR15, bit 4) is set to 1, a collision is

forced d uring every tran smission attempt. This wil l re-

sult in a Retry error.

Full-Duplex Operation

TheAm79C978 controller supports full-duplex opera-

tion on the 10BASE-T and MII interfaces. Full-duplex

operation allows simultaneous transmit and receive ac-

tivity. Full-duplex operation is enabled by the FDEN bit

located in BCR9. Full-duplex operation is also enabled

through Auto-Negotiation when DANAS (BCR 32, bit 7)

is not enabled and the ASEL bit is set, and its link partner

is capable of Auto-Negotiation and full-duplex opera-

tion.

Preamble

1010....1010 SFD

10101011 Destination

Address Source

Address Length LLC

Data Pad FCS

Bytes

46 – 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing T ime

Bit

0Bit

7Bit

0Bit

Most

Significant

Byte

Least

Significant

Byte

1 – 1500

Bytes 45 – 0

Bytes

22206B-39

74 Am79C978

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

nThe first 64 bytes of every transmit frame are not

preserved in the Transmit FIFO during transmission

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

plex mode is active and a frame is being transmitted,

the XMTFW bits (CSR80, bits 9-8) always govern

when transmit DMA is requested.

nSuccessful reception of the first 64 bytes of every

receive frame is not a requirement for Receive DMA

to begin as described in the Receive Exception Con-

ditions section. Instead, receive DMA will be re-

quested as soon as either the RCVFW threshold

(CSR80, bi ts 12- 13) is re ached or a comp lete va lid

receive frame is detected, regardless of length. This

Receive FIFO operation is identical to when the RPA

bit (CSR124, bit 3) is set during half-duplex mode

operation.

The MAC engine changes for full-duplex operation are

as follows:

nChanges to the transmit deferral mechanism:

—Transmission is not deferred while receive is

active.

—The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, ins tead of when transmit and car-

rier activity ends.

nThe 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

nThe collision indication in put to the MAC engine is

ignored.

The internal PHY changes for full-duplex operation are

as follows:

nThe collision detect (COL) pin is disabled.

nThe SQE test function is disabled.

nLoss of Carrier (LCAR) reporting is disabled.

nPHY Control Register (TBR0) bit 8 is set to 1 if Auto-

Negotiation is disabled.

Full-Duplex Link Status LED Support

TheAm79C978 controller provides bits in each of the

LED Status registers (BCR4, BCR5, BCR6, BCR7, and

BCR48) to display the Full-Duplex Link Status. If the

FDLSE bi t (bit 8) is set, a val ue of 1 will be s ent to the

associated LEDOUT bit when in Full-Duplex.

PHY/MAC Interface

The internal MII-compatible interface provides the data

path connection between the 10BASE-T PHY, the 1

Mbps HomePNA PHY, and the 10/100 Media Access

Controller (MAC). The interface is compatible with

Clause 22 of the IEEE 802.3 standard specification.

Am79C978 75

DETAILED FUNCTIONS

1 Mbps Home PNA PHY

The integrated HomePNA transceiver is a physical

layer device supporting the HomePNA specification 1.0

for home phone line networking. It provides all of the

PHY layer functions required to support 1 Mbps data

transfer speeds over common residential phone wiring.

All data bits are encoded into the relative time position

of a puls e with re spect to the previou s one, the wave-

form on the wire consists of a 7.5 MHz carrier sinusoid

enclosed within an exponential (bell shaped) envelope.

The waveform is produced by generating four 7.5 MHz

square wave cycles and passing them through a band-

pass filter.

The HomePNA PHY frame consists of a HomePNA

header that replaces the normal Ethernet 64-bit pream-

ble and delimiter and is prepended to a standard Ether-

net packet starting with the destination address and

ending with the CRC.

Only the PHY layer and its parameters are modified

from that of the standard Ethernet implementation. The

HomePNA PHY layer is designed to operate with the

internal Ethernet MAC layer controller implementing all

the CSMA/CD protocol features.

The frame begins with a characteristic SYNC interval

that delineates the beginning of a HomePNA frame fol-

lowed by an Access ID (AID) which e ncodes 8 bits of

Access ID and 4 bits of control word. The Access ID is

used to detect collisions and is dynamically assigned,

while the control word carries speed and power infor-

mation.

The AID is followed by a silence interval, then 32 bits of

data reserved for PHY layer communication. These

bits are acce ssib le via HP R20 and HPR2 1 and are for

future use.

The data encoding consists of two symbol types: an

AID sym bol and a data sym bol. The AI D symbol is al-

ways transm itted at the same sp eed an d encodes two

bits that determine the pulse position (one of four) rel-

ative to the previous pulse. The access symbol interval

is fixed.

The data symbol interval is variable. The arriving bit

stream i s block ed into from 3 to 6 bit bl ocks ac cor ding

to a propri etary (RLL25™) algorithm. Th e bits in each

block are then used to encode a data symbol. Each

symbol consists of a Data Inter Symbol Blanking Inter-

val (DISBI) and then a pulse at one of twenty-five pos-

sible positions. The bits in the data block determine the

pulse position. Immediately after the pulse a new sym-

bol interval begins. During the DISBI the receiver ig-

nores all incoming pulses to allow network reflections

to die out.

Any station may be programmed to assume the role of

a PHY ma ster and rem otely comman d, via the c ontrol

word, the rest of the units on the network to change

their transmit speed or power level.

Many of the fra ming parameter s are programmabl e in

the HomePNA PH Y and will a llow fu ture modif ications

to both transmission speed as well as noise and reflec-

tion rejection algorithms.

Two defaul t sp eeds ar e provided, low at 0.7 Mbps and

high at 1 Mbps. The center frequency is also program-

mable for future use.

HomePNA PHY Medium Interface

Framing

The Home PNA fram e on th e phon e wire ne twork c on-

sists of a header generated in the PHY prepended to

an IEEE 802.3 Ethernet data packet received from the

MAC layer. See Figure 37.

When transmitting on the phone wire pair, the

HomePNA P HY first rec eives an Ethernet MAC frame

from the M AC. The 8 o ctets of preambl e and d elimi ter

are strippe d off and replac ed with the HomePN A PHY

header d escribed below, the n transm itted LSB fi rst on

the phone wire network.

During a rec eive operat ion, the rev erse proces s is ex-

ecuted. When a HomePNA frame is received by the

PHY, the header is stripped off and replaced with the

four octets of preamble and delimiter of the IEEE 802.3

Ethernet MAC frame specification and then passed on

to the MAC layer.

76 Am79C978

Figure 37. HomePNA PHY Framing

HomePNA Symbol Waveform

All HomePNA symbols are composed at the transmitter

of a sile nce interval , and a pulse formed of an integ er

number of cycles (TX_PULSE_CYCLES_P/N in

HPR29) of a square wave of frequency

(CENTER_FREQUENCY TX_PULSE_WIDTH in

HPR29) that has been filtered with a bandpass filter.

Data is encoded in the time interval from the preceding

pulse.

Table 11. HomePNA PHY Pulse Parameters

Time Interval Unit

HomePNA PHY time intervals are expressed in Time

Interval Clock (TIC) units. One TIC is defined as

1/60E6 seconds or approximately 116.7 ns.

ACCESS ID Intervals

A HomePNA fr ame begi ns wi th an Acc es s ID (AID) in-

terval whic h is co mposed of eig ht equally s pac ed su b-

interva ls ter me d A ID s ymbol s 0 thr oug h 7 a s shown in

Figure 37.

An AID symbol is 129 TICs long. Transmit timing is

shown in Figure 38; receive timing in Figure 39. Timing

starts a t the beginn ing of each AID symbol at T IC = 0

and ends at TIC = 129.

These symbols are described in the following sections.

Symbol 0 (SYNC interval)

SYNC Transmit Timing

The SYNC interval (AID symbol 0) delineates the be-

ginning of a HomePNA frame and is composed of a

SYNC_ST ART pulse, followed by a SYNC_END pulse,

after a fixed silence interval as shown in Figure 38.

T iming for this (AID symbol 0) starts (TIC = 0) at the be-

ginning of the SYNC_START pulse. The SYNC_END

pulse starts at TIC = 126.

At TIC = 129, this AID symbol 0 ends and the next AID

symbol begins , with the s ymbo l tim ing ref erence rese t

to TIC = 0. No informati on bits are co ded in the SY NC

(AID symb ol 0 interv al) .

SYNC Receive Timing

As soon as the SYNC_START pulse is detected the re-

ceiver disables (blanks) further detection until time

TIC = 61, after which detection is re-enabled for the

next received pulse. The receiver allows for jitter by es-

tablishing a window around each legal pulse position.

This window is -2 +1 TICS wide on either side of the po-

sition.

A SYNC_END pulse that arrives outside the window of

the legal TIC = 126 is considered a noise event which

is used in setting the adaptive squelch level, aborts the

packet, and sets the receiver in search of a new

SYNC_ST AR T pulse and SYNC interval. If it is a trans-

mitting station, the COLLISION event is asserted as

described in the Collisions section.

SYNC

interval Access ID Silence PCOM

4 bytes Source

Destination Length

2ETHERNET MAC and DATA

max 1500 CRC

32 bits

PCOM Ethernet Packet

Fixed

14.93 µs

AID

blanking

interval

AID

blanking

interval

AID

blanking

interval

AID

blanking

interval

AID

blanking

interval

AID

blanking

interval

01 11 10 00 01 00

60 tics

129 tics 129 tics 129 tics 129 tics 129 tics 129 tics 129 tics

Data

symbols

20 tics 66 tics

Silence

interval

SYNC

Symbol 0 ACCESS

ID Symbol

ACCESS

ID Symbol

ACCESS

ID Symbol

ACCESS

ID Symbol

ACCESS

ID Symbol

ACCESS

ID Symbol

ACCESS

ID Symbol

730.75 µs

@ 1 Mbps

ACCESS ID interval Example Access ID of 01110100 and control word 0100

Fixed 119.44 µsHomePNA PHY Header

150.19 µs @ 1 Mbps 1 Tic = 116.6667 ns

HomePNA Header Ethernet Packet

pulse

129 tics

= receiver blanking interval

potential

pulse position

22206B-41

Parameter Value Tolerance Unit

CENTER_FREQUENCY 7.5 500 PPM MHz

CYCLES_PER_PULSE 4 -- Cycles

Am79C978 77

Figure 38. AID Symbol Transmit Timing

Figure 39. AID Symbol Receive Timing

AID Symbols 1 through 6

AID symbols 1 through 4 are used to identify individual

stations to enable reliable collision detection as de-

scrib ed in the Collisions secti on. Symbols 5 and 6 are

used to transmit remote control management com-

mands across the network. Coding and timing details

are as follows.

The SYNC interval is followed by six AID symbols

(symbols 1 through 6). T ransmit timing is shown in Fig-

ure 38; receive timing in Figure 39. Data is encoded in

the relative position of each pulse with respect to the

previous one. A pulse may occur at one, and only one,

of the four possible positions within an AID symbol

yielding two bits of data coded per AID symbol.

The decoded bits from the AID symbols 1 to 4 produce

eight bits of Access ID which is used to identify individ-

ual HomePNA stations and to detect collisions. The

MSB is encoded in AID Symbol 1 and is the leftmost bit

in Table 12.

AID Symbol 0 AID Symbol 1 AID Symbol 2

pulse 2

shown in position 1

pulse 0 pulse 1

TIC=129

and

TIC=0

TIC=129

and

TIC=0

SYNC_START

TIC=0

SYNC_END

TIC=126

AID_Position_0

TIC=66

AID_Position_1

TIC=86

AID_Position_2

TIC=106

AID_Position_3

TIC=126

Transmitter

22206B-42

AID Symbol 0 AID Symbol 1 AID Symbol 2

pulse 2

shown in position 1

pulse 0 pulse 1

TIC=128

and

TIC=0

TIC=12

8 and

TIC=0

SYNC_START

TIC=0

SYNC_END

TIC=126

AID_Position_0

TIC=66

AID_Position_1

TIC=86

AID_Position_2

TIC=106

AID_Position_3

TIC=126

Receiver

AID slice threshold

END_RCV_BLANK AID_GUARD_INTERVAL

Detected envelope

22206B-43

78 Am79C978

Table 12. Access ID Symbol Pulse Positions and

Encoding

The next two AID symbols (5 and 6) encode four bits of

control word information. The MSB is encode d in AID

Symbol 5. Control word messages are described fur-

ther in the Managem ent Inter fa ce s section.

AID Transmit T iming

The transmitter encodes the Access ID in a pulse posi-

tion in each 128 TIC interval. Each AID symbol interval

must have only one pulse. Pulse transmission must

start in only one of the four possible positions (mea-

sured from the beginning of the Access ID symbol) de-

fined in Table 12.

AID Receive Timing

The receiver allows for jitter by establishing a window

around each legal pulse position. This window is -2 +1

TICS wide on either side of the position. A pulse that ar-

rives outside of the legal AID positions is considered a

COLLISION event.

Collisions

A Collision is detected only during Access ID and silent

interva ls (AID sy mbols 0 thr ough 7) . In general during

a co llis ion , a tr an sm itt ing s tation w i ll read ba ck an A I D

valu e that does not m atch its own a nd recogniz es the

event as a collision and alerts other stations with a JAM

signal. Non-transmitting stations may also detect some

collis ions by inter preting recei ved non -confor ming A ID

pulses as coll is io ns .

With two transmitters colliding, each transmitter nor-

mally blanks its receive input immediately after trans-

mitting (and simultaneously receiving) a pulse.

Therefore, only when a transmitting station receives

pulses in a position earlier than the position it transmit-

ted will it recognize it as a pulse transmitted by another

station and signal a collision.

For this r eason, guarantee d collisio n detection is pos -

sible on ly as long as the spacing between succ essive

possible p ulse pos itions in an AID symb ol (20 TICs or

2.3 µs) is greater than the round trip delay between the

colliding nodes. At approximately 1.5 ns propagation

delay per foot, the maximum distance between two

HomePN A units must not be greate r than 500 feet for

collision detection purposes (1.5 µs round trip delay

plus margin).

The following criteria must be met to guarantee reliable

collision detection:

At least one HomePNA station of a colliding group

must always detect a collision when the delay between

the beginn ing of its transm itted packet and the begin-

ning of the received colliding packet is between -1.5 µs

and +1.5 µs.

In general, any received pulse at a HomePNA station

that does not conform to the pulse position require-

ments of AI D s ym bol s 0 throug h 7 s hal l ind ic ate a co l-

lision on the wire. When a transmitting station senses a

collision, it emits a JAM signal to alert all other stations

to th e co llisi on. T he fo llow in g condi tio ns si gni fy a C OL-

LISION event:

1. A HomePN A statio n receives an AID that doe s not

match the one being sent.

2. A HomePNA station receives a pulse outside the

AID_GUARD INTERVAL in AID intervals 0 to 7.

3. A HomePNA station receives a pulse inside the

SILENT_INTERVAL (AID symbol 7).

As in all cases, pulses received during a blanking inter-

val are ignored.

Passive stations (stations not actively transmitting dur-

ing the collision) cannot reliably detect collisions.

Therefore, once a collision is detected by a transmitting

station, the station must infor m the rest of the stations

of the collision with a JAM pattern described below.

Only a transmitting station emits a JAM signal.

Once a c ollision is detected, th e COLLISION s ignal to

the MAC interface is asserted and is not reset until the

MAC deactivates the TXEN signal.

JAM Signal

A JAM pattern consists of 1 pulse every 32 TICs and

continues until at least the end of the AID intervals.

After the AID interval, the JAM pattern will continue

until TXEN from the MAC is deactivated.

ACCESS ID Values

The acces s ID values for s lave statio ns are picked by

each individual station randomly from the set of AID

slave num bers des cribed in the mana gement sec tion.

During operation, each HomePNA station monitors

HomePNA frames received on the wire. If it detects an-

other Hom ePNA stati on u sing the s am e A ID, it will se-

lect a new random AID.

Silence Interval (AID symbol 7)

The Access ID symbols are followed by a fixed silence

interval of 129 TICs. The receive blanking interval is

the same as that of the AID symbols (1 through 6).

Any pulses detected in the silence interval are consid-

ered a CO LLISION ev ent for tran smitting stations an d

are handled as described in the Collisions sect ion.

Pulse

Position TI Cs from Beginning of AID

Symbol Bit Encoding

166 00

286 01

3 106 10

4 126 11

Am79C978 79

Data Symbols

Data symbols encode data for a much higher transmis-

sion rate, and they do not allow collision detection.

Data Transmit Timing

A data symbol interval begins with the beginning of

transmiss ion of a pul se as show n in Figure 40. Trans-

mit Symbol timing (in TICS) is measured from this point

(TIC = 0).

Depending on the data code, the next pulse may begin

at any PU LSE _PO SIT ION _ N wher e N = 0 t o 24. Eac h

position is separated from the previous one by one TIC.

PULSE_POSITION_0 occurs at a value defined in

Table 13 which determines the transmission speed.

When a pulse begins tr ansmission, th e previous sy m-

bol interval ends and a new one begins immediately.

Table 13. Blan k ing Inte rva l Speed Set tin gs

Figure 40. Transmit Data Symbol Timing

Data Receive Timing

The incoming waveform is formed from the transmitted

pulse. The receiver detects the point at which the enve-

lope of the received waveform crosses a set threshold.

See Figure 41.

Immediately after the threshold crossing, the receiver

disable s any fur ther detec tion for a period IS BI-3 TICs

(HPR28 ISBI_SLOW or ISBI_FAST) starting with the

detection of the pulse peak.

The receiver is then re-enabled for pulse detection.

Upon reception of the next pulse, the receiver mea-

sures the elapsed time from the previous pulse. This

value is then placed in the nearest pulse position bin

(one of 25) where pulse position 0 is at

PULSE_POSITION_0 and each subsequent position is

spaced one TIC from the previous one as defined in the

Data Transmit Timing section. Data symbol intervals

are therefore variable and depend on the encoded

data.

Figure 41. Receive Symbol Timing

Speed Setting Nominal Data

Rate

PULSE_POSITION_0

Value

(in TICs)

LOW_SPEED 0.7 Mbps 44

HIGH_SPEE D 1.0 Mbps 28

Symbol 1 Symbol 2

Pulse 0 Data Blanking interval (DISBI) Pulse 1 Pulse 21 TIC

START_TX_PULSE

TIC=0 END_TX_PULSE

time PULSE_POSITION_0

time Position 1 Position n1 Position 0 Position 1 Position n2

n=0-24

Transmitter

22206B-44

Symbol 1 Symbol 2

Pulse 0

Detected Envelope

Pulse 1 Pulse 2

Begin of receive

Blanking interval

END_DATA_BLANK Position 1 Position n1 Position 0 Position 1 Position n2Position 0

Data slice

threshold

Receiver

22206B-45

80 Am79C978

Data Symbol RLL25 Encoding

The RLL25 code is the version of TM32 that was devel-

oped for the HomePNA PHY. It produces both the high-

est bit rate for a given valu e of ISB I and T IC si ze. In a

manner similar to run length limited disk coding, RLL25

encodes data bits in groups of varying sizes, specifi-

cally: 3, 4, 5, and 6 bits. Pulse p ositions are assigned

to the encoded bit groups in a manner, which causes

more data bi ts to be enco ded in position s that are far-

ther apart. T his keeps bo th the average and minimum

bit rates higher.

Data symbol RLL25 codes data by traversing a tree as

illustrated in Figure 42. Assuming that successive data

bits to be encode d are label ed A, B , C, D,…, etc. The

encoding process begins at the root node and pro-

ceeds as follows:

1. If the fir st bit (b it A) is a one , the ne xt thr ee bit s (B,

C, and D) select which one of the eight positions 1-

8 is transmitted. The encoding process then contin-

ues at the root node.

2. If bit A is a zero and bit B is a one, the next three bits

(C, D, and E) select which one of the eight positions

9-16 is transmitted. The encoding process then

continues at the root node.

3. If bit A is a zero, bit B is a zer o, and bit C is a one,

the next three bits (D, E, and F) select which one of

the eight positions 17-24 is transmitted. The encod-

ing process then continues at the root node.

4. Finally, if bits A, B, and C are all zeros, position 0 is

transmitted. The encoding process then continues

at the root node.

As a result, Symbol 0 encodes the 3-bit data pattern

000, positions 1-8 encode the 4-bit data pattern 1BCD,

positions 9-16 encode the 5-bit data pattern 01CDE,

and positions 17-24 encode the 6-bit data pattern

001DEF. If the data encoded is random, 50% of the po-

sitions used will be for 4-bit patterns, 25% will be for 5-

bit patterns, 12.5% will be for 6-bit patterns, and 12.5%

will be for 3-bit patterns.

Management Interfaces

The HomePNA PHY may be managed from either of

two interfaces (the managed parameters vary depend-

ing on the interface):

1. Remote Control-Word management commands

embedded in the HomePNA AID header on the wire

network.

2. Managemen t messages from a local management

entity.

Figure 42. RLL 25 Coding Tree

These select position 1 - 8

A B E F

Awaiting coding and transmissionEncoded and

Start: Examine the next

bits to be encoded

C D1 B

These select position 9 - 16

C D0 1 E

These select position 17- 24

1 D0 0 E F

00 0

A = ?

B = ?

C = ?

Send symbol 1-8

Send symbol 9-16

Send symbol 17-24

Send symbol 0

Data stream from MAC controller

22206B-46

Am79C978 81

Header AID Remote Control Word Commands

Stations may be configured either as master stations or

as slave stations. Only one master may exist on a given

HomePNA segment.

The master station may send commands embedded in

the HomePNA header control word to remotely set var-

ious par ameters of the re mote sl ave stati ons. St ations

are identified via the AID as follows:

1. The master station is identified on the HomePNA

wire network with an AID of FFh.

2. A slave is identified with an AID of 00h to EFh.

3. AID values of F0h to FEh are reserved for future

use.

Once a command has been transmitted, the master

station will revert to a slave AID, so that subsequent

control words are not interpreted as new commands.

Master mode is entered by writing to the PHY control

registe r (HPR1 6) and is exi ted up on the c ompleti on of

the command sequence.

A valid master remote command consists of three

HomePNA frames with an AID of FFh. Since the

HomePNA header is prepended to packets received

from the M AC as wel l as A ny 1Hom e p acke ts. Pac kets

from the mas ter sta tion may be s epara ted by in tervals

during which other (slave) stations may transmit their

frames.

A remote master Control Word command must be rec-

ognized and executed by a HomePNA PHY when it re-

ceives three consecutive valid HomePN A frames with

an AID of FFh.

If HPR16, bit 15 is not set to 0, valid commands are as

follows:

1. SET_POWER: Commands slave stations to set

their transmit level to a prescribed level.

2. SET_SPEED: Commands slave stations to set their

transmit speed to a prescribed value.

The con tr ol word bi t en co ding and possi ble va lues ar e

described in Table 14.

Table 14. Master Station Control Wor d Functions

All stati ons wil l tr ansmi t the fol lo win g sta tus mes sa ges

in the HomePNA header control word of all outgoing

frames:

1. VERSION_STATUS: The HomePNA PHY version

of the slave station.

2. POWER_STATUS: The transmit power level of the

transmitting slave station for the current frame. All

HomePNA units support LOW_POWER and

HIGH_POWER modes.

3. SPEED_ STATUS : The transm it speed of t he slave

station for the current frame. Receiving stations will

adjust their receiver parameters to correctly inter-

pret this frame.

The slave contro l word bit encod ing and possi ble val-

ues are also described in Table 14.

PHY Control and Management Block (PCM

Block)

The management interface specified in Clause 22 of

the IEEE 802.3u standard provides for a simple two

wire, serial interface to connect a management entity

and a managed PHY f or the p ur pose of contr ol ling th e

PHY and gathering status information. The two lines

are Manag ement Data In put/Output (M DIO) and Man-

agement Data Clock (MDC). A station management

entity which is attached to multiple PHY entities must

have prior knowledge of the appropriate PH Y address

for each PHY entity.

Description of the Methodology

The manag ement inter face physical ly transpor ts man-

agement information across the internal and external

MII. The information is encapsulated in a frame format

as specified in Clause 22 of the IEEE 802.3u draft stan-

dard and is shown in Table 15.

Table 15. MII Control Frame Format

Aid No. LSB MSB

5 Version Set to:

0 = Low Power

1 = High Power

6Set to:

0 = Low Speed

1 = High S peed Reserved

PRE ST OP PHYAD REGAD TA DATA IDLE

READ 1.1 01 10 AAAAA RRRRR Z0 D31………D0 Z

WRITE 1.1 01 01 AAAAA RRRRR 10 D31………D0 Z

82 Am79C978

The start field (ST) is followed by the operation field

(OP). The operation field (OP) indicates whether the

operation is a read or a write operation. This is followed

by the PHY address (PHY AD) and the register address

(REGAD ) that was progra med into BCR3 3 of the Fast

Ethernet controller. This field is followed by a bus turn-

around field (TA). During the read operation, the bus

turnaro und field is us ed to determi ne if the PHY is re-

sponding properly to the read request. The data field

to/from the MAC controller is then written to or read

from BCR34. The final field is the idle field, and it is re-

quired to allow the drivers to turn off.

The PHYADD field, which is five bits wide, allows 32

unique PHY addresses. The managed PHY layer de-

vice t hat is con nected to a station m anagement ent ity

via the MII interface has to respond to transactions ad-

dresse d to the PHY’s address. A station man agemen t

entity attached to multiple PHYs is required to have

prior knowledge of the appropriate PHY address.

SRAM Configuration

If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the

SRAM size register, the controller will assume that

there is no SRAM present and will reconfigure the four

internal FIFOs into two FIFOs, one for transmit and one

for rece ive. The FIFOs wil l operate the same as in th e

PCnet-PCI II controller. When the SRAM_SIZE

(BCR25, bits 7-0) value is 0, the SRAM_BND (BCR26,

bits 7-0) are ignored by the controller. See Figure 43.

Low Latency Receive Configurat ion

If the LOLATRX (BCR27 , bit 4) bit is set to 1, then the

controller will configure itself for a low latency receive

configuration. In this mode, SRAM is required at all

times. If th e S RAM _S IZ E (BC R 25, b its 7- 0) v al ue i s 0,

the contr oller wi ll not conf igure fo r low la tency re ceive

mode. The co ntr oller wi ll pr ov ide a fas t pa th on the re -

ceive side byp as sing th e SRA M. All tra ns mit t raffic will

go to the SRAM, so SRAM_BND (BCR26, bits 7-0) has

no meaning in low latency receive mode. When the

controller has received 16 bytes from the network, it will

start a DMA request to the PCI Bus Interface Unit. The

controller will not wait for the first 64 bytes to pass to

check for collisions in Low Latency Receive mode. The

controller must be in STOP before switching to this

mode. See Figure 44.

CAUTIO N: To provide data integrity when switching

into and out of the low latency mode, DO NOT SET the

FASTSPNDE bit when setting the SPND bit. Receive

frames WILL be overwritten and the controller may give

erratic behavior when it is enabled again.

Direct SRAM Access

The SRAM can be accessed through the Expansion

Bus Data port (BCR30). To access this data port, the

user must load the upper address EPADDRU (BCR29,

bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the

user will load the lower 16 bits of address EPADDRL

(BCR28, bits 15-0). To initiate a read, the user reads

the Expan sion Bus Data P ort (BCR30). T his slave ac-

cess f rom the PCI wil l resu lt in a re try for the v ery firs t

access. Subsequent accesses may give a retry or not,

depending on whether or not the data is present and

valid. The direct SRAM access uses the same FLASH/

EPROM access except for accessing the SRAM in

word format instead of byte format. This access is

meant to be a dia gnostic access on ly. The SR AM ca n

only be accessed while the controller is in STOP or

SPND (FASTSPNDE is set to 0) mode.

Figure 43. Block Diagram SRAM Configuration

PCI Bus

Interface

Unit

802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

and

10BASE-T

and

HomePNA

PHYs

22206B-47

Am79C978 83

Figure 44. Block Diagram Low Latency Receive Configuration

PCI Bus

Interface

Unit 802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

SRAM

and

10BASE-T

and

HomePNA

PHYs

22206B-48

84 Am79C978

EEPROM Interface

The cont roller contai ns a built-in capa bility for read ing

and writing to an external serial 93C46 EEPROM. This

built-in capability consists of an interface for direct con-

nection to a 93C46 compatible EEPROM, an automatic

EEPROM read feature, and a user-programmable reg-

ister that allows direct access to the interface pins.

Automatic EEPROM Read Operation

Shortly after the deassertion of the RST pin, the con-

troller will read the contents of the EEPROM that is at-

tached to the interface. Because of this automatic-read

capability of the controller , an EEPROM can be used to

program many of the features of the controller at

power-up, allowing system-dependent configuration in-

formation to be stored in the hardware instead of inside

the device driver.

If an EEPROM exists on the interface, the controller will

read the EEPROM contents at the end of the

H_RESET operation. The EEPROM contents will be

serial ly shi fted in to a tem porar y regi ster an d th en sen t

to various register locations on board the controller . Ac-

cess to th e Am79C978 c onfigura tion spac e or any I/O

resour ce is not pos sible du ring the EE PROM rea d op-

eration. The controller will terminate any access at-

tempt with the assertion of DEVSEL and STOP while

TRDY is not asserted, signaling to the initiator to dis-

connect and retry the access at a later time.

A checksum verification is performed on the data that

is read from the EEPROM. If the checksum verification

passes, PVALID (BCR19, bit 15) will be set to 1. If the

checksum verification of the EEPROM data fails,

PV ALID will be cleared to 0, and the controller will force

all EEPROM-programmable BCR registers back to

their H_RESET default values. However , the content of

the Addr ess PRO M locati ons (offsets 0h - Fh fr om th e

I/O or memory mapped I/O base address) will not be

cleare d. The 8-bit checksu m for the entire 82 bytes of

the EEPROM should be FFh.

If no EEPROM is present at the time of the automatic

read ope ra tio n, th e c on tro ll er wi ll re cogn iz e th is c ond i-

tion, abort the automatic read operation, and clear both

the PREAD and PVALID bits in BCR19. All EEPROM-

programmable BCR registers will be assigned their de-

fault values after H_RESET. The content of the Ad-

dress PROM l ocations (offsets 0h - Fh fro m the I/O or

memory mapped I/O base address) will be undefined.

EEPROM Auto-Detection

The controller uses the EESK/LED1 pin to determine if

an EEPROM is present in the system. At the rising

edge of CLK durin g the last clock dur ing whic h RST is

asserted, the controller will sample the value of the

EESK/LED1 pin. If the sampled value is a 1, then the

controller assumes that an EEPROM is present, and

the EEPROM read operation begins shortly after the

RST pin is deass erted. If t he sample d value of EESK/

LED1 is a 0, the controller assumes that an external

pull-down device is holding the EESK/LED1 pin low , in-

dicatin g that the re is no E EPROM i n the sys tem. Not e

that if the designer creates a system that contains an

LED circuit on the EESK/LED1 pin, but has no EE-

PROM present, then the EEPROM auto-detection

function will incorrectly conclude that an EEPROM is

present in the system. However, this will not pose a

problem for the controller, since the checksum verifica-

tion will fail.

Direct Access to the Interface

The user may directly access the port through the

EEPROM register, BCR19. This register contains bits

that can be used to control the interface pins. By per-

forming an appropriate sequence of accesses to

BCR19, the user can effectively write to and read from

the EEPR OM. This feature may be used by a syste m

configurat ion util ity to progr am h ardware conf igura tion

information into the EEPROM.

EEPROM-Programmable Registers

The following registers contain configuration informa-

tion that will be programmed automatically during the

EEPROM read operation:

nI/O offsets 0h-Fh Address PROM locations

nBCR2 Miscellaneous Configuration

nBCR4 LED0 Status

nBCR5 LED1 Status

nBCR6 LED2 Status

nBCR7 LED3 Status

nBCR9 Full-Duplex Control

nBCR18 Burst and Bus Control

nBCR22 PCI Latency

nBCR23 PCI Subsystem V endor ID

nBCR24 PCI Subsystem ID

nBCR25 SRAM Size

nBCR26 SRAM Boundary

nBCR27 SRAM Interface Control

nBCR32 PHY Control and Status

nBCR33 PHY Address

nBCR35 PCI Vendor ID

nBCR36 PCI Power Management Capa-

bili ties (PMC) Alias Register

nBCR37 PCI DATA Register 0 (DATA0)

Alias Register

nBCR38 PCI DATA Register 1 (DATA1)

Alias Register

nBCR39 PCI DATA Register 2 (DATA2)

Alias Register

Am79C978 85

nBCR40 PCI DATA Regi ste r 3 (DATA3)

Alia s Register

nBCR41 PCI DATA Regi ste r 4 (DATA4)

Alia s Register

nBCR42 PCI DATA Regi ste r 5 (DATA5)

Alia s Register

nBCR43 PCI DATA Regi ste r 6 (DATA6)

Alia s Register

nBCR44 PCI DATA Regi ste r 7 (DATA7)

Alia s Register

nBCR45 OnNow Pattern Matching

nBCR46 OnNow Pattern Matching

nBCR47 OnNow Pattern Matching

nBCR48 LED4 Status

nBCR49 PHY Select

nCRS12 Physical Address Register 0

nCRS13 Physical Address Register 1

nCRS14 Physical Address Register 2

nCSR116 OnNow Miscellaneous

If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)

are cleared to 0, then the EEPROM read has experi-

enced a fai lure and the conten ts of the EE PROM pro-

grammable BCR register will be set to default

H_RESET values. The conte nt of the Address PROM

locations, however, will not be cleared.

EEPROM MAP

The automatic EEPROM read operation will access 41

words (i.e., 82 bytes) of the EEPROM. The format of

the EEPROM contents is shown in Table 16, beginning

with the byte that resides at the lowest EEPROM ad-

dress.

Note: The first bit ou t of any word locati on in the EE-

PROM is treated as the MSB of the register being pro-

grammed. For example, the first bit out of EEPROM

word locati on 09 h wi ll be wr it ten i nto BCR4 , bit 15; th e

second bit out of EEPROM word location 09h will be

written into BCR4, bit 14, etc.

There are two checksum locations within the EE-

PROM. The first checksum will be used by AMD driver

software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The

value of bytes 0Ch and 0Dh should matc h the sum of

bytes 00 h through 0 Bh and 0 Eh and 0 Fh. The s econd

checks um location (byte 51h) is not a ch ecksum total,

but is, instead, a checksum adjustment. The value of

this byte should be such that the total checksum for the

entire 82 bytes of EEPROM data equals the value FFh.

The che cksum adjust b yte is needed by the contr oller

in order to verify that the EEPROM content has not

been corrupted.

LED Support

The controller can support up to five LEDs. LED out-

puts LED0, LED1 , LED2, LED3, and LED4 allow for di-

rect connection of an LED and its supporting pull-up

device.

In applications that want to use the pin to drive an LED

and also have an EEPROM, it might be necessary to

buffer the LED3 ci rcuit fro m the EE PROM conn ection.

When an LED circuit is directly connected to the

EEDO/LED3 pin, then it is not possible for most EE-

PROM devices to sink enough IOL to maintain a valid

low level on the EEDO input to the controller. Use of

buffering can be avoided if a low power LED is used.

Each LED can be programmed through a BCR register

to indic ate o ne o r mor e of t he fo ll owi ng ne twork st atus

or activities: Collision Status, Full-Duplex Link Status,

Half-Dupl ex Link Sta tus, Rece ive Match, Rec eive Sta-

tus, Magi c Packet, Disa ble Transceiv er, Transmit S ta-

tus, Power, and Speed.

86 Am79C978

Table 16. EEPROM Map

Note: *Lowest EEPROM address.

Word

Address Byte

Addr. Most Significant Byte Byte

Addr. Least Significant Byte

00h* 01h 2nd byte of the ISO 8802-3 (IEEE/ANSI

802.3) station physical address for this node 00h

First byte of the IS0 8802-3 (IEEE/ANSI 802.3)

station physical address for this node, where

“first byte” refers to the fi rst b yte to ap pea r on

the 802.3 medium

01h 03h 4th byte of the node address 02h 3rd byte of the node address

02h 05h 6th byte of the node address 04h 5th byte of the node address

03h 07h CSR116[15:8] (OnNow Misc. Configuration) 06h CSR116[7:0] (OnNow Misc. Configuration)

04h 09h Hardware ID: must be 11h if compatibility to

AMD drivers is desired 08h Reserved location: must be 00h

05h 0Bh User programmable space 0Ah User programmable space

06h 0Dh MSB of two-byte checksum, which is the sum

of bytes 00h-0Bh and bytes 0Eh and 0Fh 0Ch LSB of two-byte checksum, which is the sum

of bytes 00h-0Bh and bytes 0Eh and 0Fh

07h 0Fh Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired 0Eh Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired

08h 11h BCR2[15:8] (Miscellaneous Configuration) 10h BCR2[7:0] (Miscellaneous Configuration)

09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED)

0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status)

0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status)

0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status)

0Dh 1Bh BCR9[15:8] (Full-Duplex control) 1Ah BCR9[7:0] (Full-Duplex Control)

0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)

0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency)

10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (PCI Subsystem Vendor ID)

11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID)

12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size)

13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary)

14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control)

15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status)

16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address)

17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID)

18h 31h BCR36[15:8] (Conf. Space. byte 43h alias) 30h BCR36[7:0] (Conf. Space byte 42h alias)

19h 33h BCR37[15:8] (DATA_SCALE alias 0) 32h BCR37[7:0] (Conf. Space byte 47h0alias)

1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Space byte 47h1alias)

1Bh 37h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Space byte 47h2alias)

1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Space byte 47h3alias)

1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Space byte 47h4alias)

1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 0) 3Ch BCR42[7:0] (Conf. Space byte 47h5alias)

1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 0) 3Eh BCR43[7:0] (Conf. Space byte 47h6alias)

20h 41h BCR44[15:8] (DATA_SCALE alias 0) 40h BCR44[7:0] (Conf. Space byte 47h7alias)

21h 43h BCR48[15:8] (LED4 Status) 42h BCR48[7:0] (LED4 Status)

22h 45h BCR49[15:8] (PHY Select) 44h BCR49[7:0] (PHY Select)

23h 47h BCR50[15:8]Reserved location: must be 00h 46h BCR50[7:0]Reserved location: must be 00h

24h 49h BCR51[15:8]Reserved location: must be 00h 48h BCR51[7:0]Reserved location: must be 00h

25h 4Bh BCR52[15:8]Reserved location: must be 00h 4Ah BCR52[7:0]Reserved location: must be 00h

26h 4Dh BCR53[15:8] Reserved locati on: must be 00h 4Ch BCR53[7:0 ]Reserved location : must be 00h

27h 4Fh BCR54[15:8]Reserved location: must be 00h 4Eh BCR54[7:0]Reserved location: must be 00h

28h 51h Checksum ad just byte f or t he 82 bytes of th e

EEPROM contents, checksum of the 82 bytes

of the EEPROM should total to FFh 50h BCR54[7:0]Reserved location: must be 00h

Empty loc ati on s – Ignored by device

3Eh 7Dh Reserved 7Ch Reserved

3Fh 7Fh Reserved 7Eh Reserved

Am79C978 87

The LED pins can be configured to operate in either

open-drain mode (active low) or in totem-pole mode

(activ e high). Th e out put can be s tretche d to all ow the

human eye to recognize even short events that last

only several microseconds. After H_RESET, the five

LED outputs are configured as shown in Table 17.

Table 17. LED Default Configuration

For each LED register, each of the status signals is

AND’d wi th its enable sign al, and these sign als are all

OR’d toget her to form a combi ned s tatus signa l. E ach

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shi ft register i s normally a t logic 0. T he OR gate

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asserted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 45.

Power Savings Mode

Power Management Support

The controller supports power management as defined

in the PCI Bus Power Management Interface Specifica-

tion V1.1 and Network Device Class Power Manage-

ment Reference Specification V1.0a.These

specifi catio ns def ine the networ k devic e powe r sta tes,

PCI powe r management i nterface in cluding th e Capa-

bilities Data Structure and power management regis-

ters bloc k def ini ti ons , p ower managem ent ev en ts, and

OnNow network wake-up events.

The general scheme for the Am79C978 power man-

agement is that when a PCI wake-up event is detected,

a signal is generated to cause hardware external to the

Am79C978 device to put the computer into the working

(S0) mode.

Figure 45. LED Control Logic

The Am79C978 device supports three types of wake-

up events:

1. Magic Packet Detect

2. OnNow Pattern Match Detect

3. Link State Change

Figure 46 shows the relationship between these wake-

up events and the various outputs used to signal to the

external hardware.

OnNow Wake-Up Sequence

The system software enables the PME pin by setting

the PME_EN bit in the PMCSR register (PCI configura-

tion regist ers, offset 44h, bit 8) to 1. When a wake-up

event is detected, the controller sets the PME_ST A TUS

bit in the PMCSR re gister ( PCI confi gu ratio n reg ister s,

offset 44h, bit 15). Setting this bit causes the PME sig-

nal to be asserted. Assertion of the PME signal causes

external hardware to wake up the CPU. The system

software then reads the PMCS R register o f every PCI

device in the system to determine which device as-

serted the PME signal.

When the software determines that the signal came

from the c ontroller, it writes to the device's PM CSR to

put the dev ice into powe r state D0. The s oftware then

writes a 0 to the P ME_STATUS b it to clear the bit an d

turn off the PME signal, and it calls the device's soft-

ware drive r to tell it that the devi ce is now in state D0.

The system software can clear the PME_STATUS bit

either bef ore, after, or at the same time that it puts the

device back into the D0 state.

LED

Output Indication Driver Mode Pulse Stretch

LED0 Link Status Open Drain -

Active Low Enabled

LED1 Receive

Status Open Drain -

Active Low Enabled

LED2 Power Open Drain -

Active Low Enabled

LED3 Transmit

Status Open Drain -

Active Low Enabled

LED4 Speed Open Drain -

Active Low Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse

Stretcher

MR_SPEED_SEL

100E

MPS

MPSE

POWER

POWERE 22206B-49

88 Am79C978

Figure 46. OnNow Functional Diagram

Link Change Detect

Link change detect is one of wake-up events defined

by the OnNow specification. Link Change Detect mode

is set when th e LCMODE bit (CSR116, bit 8) is set ei-

ther by software or loaded through the EEPROM.

When this bit is set, an y ch ange in t he Link status wi ll

cause t he LCDET bi t (CSR116, bi t 9) to be set. W hen

the LCDET bit is set, the PME_STATUS bit (PMCSR

(PMCSR, bi t 8) or the PM E_ EN_ O VR bi t (CSR11 6, bi t

10) are set, then the PME will also be asserted.

OnNow Pa ttern Match Mode

In the OnNow Pattern Match Mode, the Am79C978 de-

vice compares the incoming packets with up to eight

patterns stored in the Pattern Mat ch RAM (PM R). The

stored pa tterns can be c ompared wi th part or all of in-

coming packets, depending on the pattern length and

the way the PMR is programmed. When a pattern

match has been detected, then PMAT bit (CSR116, bit

7) is set. The setting of the PMAT bit causes the

PME_STATUS bit (PMCSR, b it 15) to be set, wh ich in

turn will assert the PME pin if the PME_EN bit

(PMCSR, bit 8) is set.

Pattern Match RAM (PMR)

PMR is organized as an array of 64 words by 40 bits as

shown in Figure 47. The PMR is programmed indirectly

through BCR s 45, 46 , a nd 47. W hen B CR45 i s wr itte n

and the PMAT_MODE bit (BCR45, bit 7) is set to 1,

Pattern Match logic is enabled. No bus accesses into

the PMR are possible when the PMAT_MODE bit is

set, and BCR46, BCR47, and all other bits in BCR45

are ignored. When PMAT_MODE is set, a read of

BCR45 returns all bits undefined except for

MPDETECT

MPPEN

MPMODE

MPEN

Magic Packet

Link Change

LCMODE

Link Change

MPMAT

LCDET

DET

CLR

BCR47 BCR46 BCR45

SET

CLR

SET

CLR

SET

CLR

PMAT

Pattern Match

Input

Pattern

PME_STATUS

Pattern Match RAM (PMR)

PME Status

PME_EN

MPMAT

PME_EN_OVR

LCEVENT

PME

SET

CLR

POR

H_RESET

POR

22206B-50

Am79C978 89

PMAT_MODE. In order to access the contents of the

PMR, PMAT_MODE bit should be programmed to 0.

When BCR45 i s written to set th e PMAT_MODE bi t to

0, the P atter n Ma tch l ogi c i s dis ab le d and ac ce ss es t o

the PMR are possible. Bits 6:0 of BCR45 specify the

address of the PMR word to be accessed. Writing to

BCR45 does not immediately affect the contents of the

PMR. Following the write to BCR45, the PMR word ad-

dresse d by bit s 6:0 of BC R45 may be read by r eadin g

BCR45, BCR46, and BCR47 in any order. To write to

the PMR word, the write to BCR45 must be followed

by a write to BCR46 and a write to BCR47 in that order

to co mplete the ope ration. The PMR will no t actual ly be

written until the write to BCR47 is complete.

The first two 40-bit words in this RAM serve as pointers

and contain enable bits for the eight possible match

patterns. The remainder of the RAM contains the

match patterns and associated match pattern control

bits. Byte 0 of the first word contains the pattern enable

bits. Any bi t pos it ion se t in th is by te en abl es the c or re-

sponding match pattern in the PMR, as an example if

the bit 3 is se t, then patter n 3 is enabl ed for mat ching.

Bytes 1 to 4 in the fi rst wor d are poin ters to the begin-

ning of the patte rn s 0 to 3, and by tes 1 to 4 in th e sec -

ond word are pointers to the beginning of patterns 4 to

7, respectively. Byte 0 of the second word has no func-

tion associated with it. Byte 0 of the words 2 to 63 is the

control fie ld of the PMR. B it 7 of this fi el d is th e E nd o f

Packet (EOP) bit. When this bit is set, it indicates the

end of a pattern in the PMR. Bits 6-4 of the control field

byte are the SKIP bits. The value of the SKIP field indi-

cates the number of the Dwords to be skipped before

the pattern in this PMR word is compared with data

from the incoming frame. A maximum of seven Dwords

may be skipped. Bits 3-0 of the control field byte are the

MASK bits. These bits correspond to the pattern match

bytes 3-0 of the same PMR word (PMR bytes 4-1). If bit

n of this field is 0, then byte n of the corr espo ndin g pat-

tern word is ignored. If this field is programmed to 3,

then bytes 0 and 1 of the pattern match field (bytes 2

and 1 of the word) ar e u sed, an d by tes 3 and 2 are i g-

nored in the pattern matching operation.

The contents of the PMR are not affected by

H_RESET, S_RESET, or STOP. The content s are un-

defined after a power up reset (POR).

Magic Packet Mode

In Magic Packet mode, the controller remains fully

powered up (all VDD and VDDB pins must remain at

their supply levels). The device will not generate any

bus master transfers. No transmit operations will be ini-

tiated on the network. The device will continue to re-

ceive frames from the network, but all frames will be

automatically flushed from the receive FIFO. Slave ac-

cesses to the controller are still possible. A Magic

Packet is a frame that is addressed to the controller

and contains a data sequence anywhere in its data

field ma de u p o f 16 consec uti ve copi es of the dev ice’s

physical address (PADR[47:0]). The controller will

search incoming frames until it finds a Magic Packet

frame. It starts scanning for the sequence after pro-

cessing the length field of the frame. The data se-

quence can begin anywhere in the data field of the

frame, but must be detected before the controller

reaches t he frame’s FCS field . A ny de vi ati on of t he i n-

coming frame’s data sequence from the required phys-

ical address sequence, even by a single bit, will

prevent the detecti on of that fram e as a Magi c Packet

frame.

The controller supports two different modes of address

detection for a Magic Packet frame. If MPPLBA (CSR5,

bit 5) or E MP P LBA (CS R 116, b it 6) are a t t hei r de faul t

value of 0, the controller will only detect a Magic Packet

frame if the destination address of the packet matches

the conten t of the phy sic al addres s regis ter (PADR) . If

MPPLBA or EMPPLBA are set to 1, the destination ad-

dress of the Magic Packet frame can be unicast, multi-

cast, or broadcast.

Note: The setting of MPPLBA or EMPPLBA only ef-

fects the address detection of the Magic Packet frame.

The Magic Packet’s data sequence must be made up

of 16 consecutive copies of the device’s physical ad-

dress (P ADR[47:0]), regardless of what kind of destina-

tion address it has.

There are two general methods to plac e the controll er

into Magic Packet mode. The first is the software

method. In this method, either the BIOS or othe r soft-

ware sets the MPMODE bit (CSR5, bit 1). Then the

controller must be put into suspend mode (see descrip-

tion of CSR5, bit 0), allowing any current network activ-

ity to finish. Finally, either PG must be deasserted

(hardware control), or MPEN (CSR5, bit 2) must be set

to 1 (software control).

Note: FASTSPNDE (CSR7, bit 15) has no meaning in

Magic Packet mode.

The second method is the hardware method. In this

method, the MPPEN bit (CSR116, bit 4) is set at power

up by the loading of the EEPROM. This bit can also be

set by software. The controller will be placed in the

Magic Pac ket Mod e when eithe r the PG input is deas-

serted or the MPE N bit is se t. Magi c Pa ck et mo de ca n

be disabled at any time by asserting PG or clearing

MPEN bit.

90 Am79C978

Figure 47. Pattern Match RAM

When the controller detects a Magic Packet frame, it

sets the MPMAT bit (CSR116, bit 5), the MPINT bit

(CSR5, bit 4), and the PME_ STATUS bit (PMCSR, bit

15). If the PME_EN or the PME_EN_OVR bits are set,

the PME will be asserted as well. If IENA (CSR0, bit 6)

and MPINTE (CSR5, bit 3) are set to 1, INT A will be as-

serted. Any one of the four LED pins can be pro-

grammed to indicate that a Magic Packet frame has

been received. MPSE (BCR4-7, bit 9) must be set to 1

to enable that function.

Note: The polarity of the LED pin can be programmed

to be active HIGH by setting LEDPOL (BCR4-7, bit 14)

to 1.

Once a Magic Packet frame is detected, the controller

will discard the frame internally , but will not resume nor-

mal transmit and receive operations until PG is as-

serted o r MPE N is c lea red. O nce b oth o f the se events

has oc curred, indic ating that th e system has detected

the Magic Packet and is awake, the controller will con-

tinue polling receive and transmit descriptor rings

where it left off. It is not necessary to re-initialize the de-

vice. If the part is re-initialized, then the descriptor loca-

tions will be reset and the controller will not start where

it left off.

If magic packet mode is disabled by the assertion of

PG, then in order to immediately re-enable Magic

Packet mode, th e PG pin mu st remain deasserted for

at least 200 ns before it is r easse rted. If M agic Pac ket

mode is disabled by clea ring MPEN bi t, then it may be

immediately re-enabled by setting MPEN back to 1.

BCR 47 BCR 46 BCR 45

BCR Bit Number 15 8 7 0 15 8 7 0 15 8

PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0

Pattern Match

RAM Address Patter n Ma tch RAM B it Number

39 32 31 24 23 16 15 8 7 0 Comments

0P3 pointer P2 pointer P1 pointer P0 pointer Pattern Enable

bits First Address

1P7 pointer P6 pointer P5 pointer P4 pointer X Second

Address

2Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Contr ol Start Patte rn

2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End Pattern P1

JData Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start Patte rn

J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern Pk

63 Last Address

7 6 5 4 3 2 1 0

EOP SKIP MASK

22206B-51

Am79C978 91

The PCI bus interface clock (CLK) is not required to be

running while the device is operatin g in Magic Packet

mode. Either of the INT A, the LED pins, or the PME sig-

nal may be used to indicate the receipt of a Magic

Packet frame when the CLK is stoppe d. If the system

wishes to st op the CLK, it will do so after enabling the

Magic Packet mode.

CAUTION: To prevent unwa nted inte rrupts fr om other

active parts of the controller, care must be taken to

mask all likely interruptible events during Magic Packet

mode. An example would be the interrupts from the

Media Inde pendent Inter face, whi ch could occ ur while

the device is in Magic Packet mode.

IEEE 1149.1 (1990) Test Access Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-level continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. The following paragraphs summarize

the IEEE 1149.1-compatible test functions imple-

mented in the control ler.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, T DI, and T DO), def ine d as th e Te st Ac cess Port

(TAP). It includes a finite state machine (FSM), an in-

struction register , a data register array , and a power-on

reset circuit. Internal pull-up resist ors are provided for

the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK), and the Test

Mode Select (TMS) pins. An independent power-on

reset circuit is provided to ensure that the FSM is in the

TEST_LOGIC_RESET state at power-up. Therefore,

the TRST is not provided. The FSM is also reset when

TMS and TDI are high for five TCK periods.

Supported Instructions

In additio n to the minim um IEEE 1149.1 requ irements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP, and SET-

BYP) are provided to further ease board-level testing.

All unused instruction codes are reserved. See Table

18 for a summary of supported instructions.

Instruction Register and Decoding Logic

After the TAP FSM i s reset , the IDCODE instru ction is

always invoked. The decoding logic gives signals to

control th e data flow in the d ata regi ster s acco rdin g to

the current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively .

There are four possible operation modes in the BSR

cell shown in Table 19.

Other Data Registers

Other data registers are the following:

1. Bypass register (1 bit)

2. Device ID register (32 bits) (Table 20).

Note: The content of the Device ID register is the

same as the content of CSR88.

Table 18. IEEE 1149.1 Supported Instruction

Summary

Instruction

Name Instruction

Code Description Mode

Selected

Data

EXTEST 0000 External Test Test BSR

IDCODE 0001 ID Code

Inspection Normal ID REG

SAMPLE 0010 Sample

Boundary Normal BSR

TRIBYP 0011 Force Float Normal Bypass

SETBYP 0100 Control

Bounda ry t o

I/0 Test Bypass

BYPASS 1111 Bypass Scan Normal Bypass

Table 19. BSR Mode Of Operation

1Capture

2Shift

3 Update

4System Function

Table 20. Device ID Register

Bits 31-28 Version

Bits 27-12 Part Number (0010 0110 0010 0110)

Bits 11-1 Manufacturer ID. T he 1 1 bit man ufacturer ID

cod for AMD is 000000000 01 in acc ordance

with JEDEC publication 106-A.

Bit 0 Al ways a l ogic 1

92 Am79C978

NAND Tree Testing

The controller provides a NAND tree test mode to allow

checki ng conn ectivit y to the dev ice on a pri nted circui t

board. The NAND tree is built on all PCI bus pins.

NAND tree testing is enabled by asserting RST. PG

input should be driven HIGH during NAND tree testing.

All PCI bus signals will become inputs on the assertion

of RST. The result of the NAND tree test can be ob-

served on the INTA pin . See F igur e 48.

Pin 141 (RST) is the first input to the NAND tree. Pin

142 (CLK) is the second input to the NAND tree, fol-

lowed by pi n 143 (GNT). Al l other PCI bu s signal s fol-

low , counterclockwise, with pin 61 (AD0) being the last.

Ta ble 21 and Tabl e 22 shows th e comple te list of pi ns

connected to the NAND tree.

RST must be asserted low to start a NAND tree test se-

quence. Initially, all NAND tree inputs except RST

should be driven high. This will result in a high output

at the INT A pin. If the NAND tree inputs are driven from

high to low in the same order as they are connected to

build the NAND tree, INT A will toggle every time an ad-

ditional input is driven low. INTA will change to low,

when CLK is driven low and all other NAND tree inputs

stay h igh. INTA will toggle back to high, when GNT is

addition ally driv en low. The sq uare wave wil l continue

until all NAND tree inputs are driven low. INTA will be

high, when all NAND tree inputs are driven low. See

Figure 49.

Some of the pins connected to the NAND tree are out-

puts in normal mode of operation. They must not be

driven from an external source until the controller is

configured for NAND tree testing.

Figure 48. NAND Tree Circuitry (160 PQFP)

Am79C972

Core

RST (pin141)

CLK (pin 142)

VDD

GNT (pin 143)

AD0 (pin 61)

INTA (pin 140)

MUX

.... INTA

Am79C978

Core

22206B-52

Am79C978 93

Table 21. NAND Tree Pin Sequence (160 PQFP)

Table 22. NAND Tree Pin Sequence (144 TQFP)

NAND

T ree Input

No. Pin No. Name NAND Tree

Input No. Pin No. Name NAND Tree

Input No. Pin No. Name

1 141 RST 18 9 AD20 35 36 AD13

2 142 PCI_CLK 19 11 AD19 36 38 AD12

3 143 GNT 20 12 AD18 37 43 AD11

4 144 REQ 21 14 AD17 38 45 AD10

5 146 AD31 22 16 AD16 39 46 AD9

6 149 AD30 23 17 C/BE24047 AD8

7 150 AD29 24 19 FRAME 41 48 C/BE0

8 151 AD28 25 20 IRDY 42 50 AD7

9 152 AD27 26 22 TRDY 43 52 AD6

10 154 AD26 27 24 DEVSEL 44 53 AD5

11 156 AD25 28 25 STOP 45 55 AD4

12 157 AD24 29 27 PERR 46 56 AD3

13 158 C/BE3 30 28 SERR 47 58 AD2

14 3 IDSEL 31 30 PAR 48 60 AD1

15 4 AD23 32 32 C/BE14961 AD0

16 6 AD22 33 33 AD15 50

17 8 AD21 34 35 AD14 51

NAND

T ree Input

No. Pin N o. N am e NAND Tree

Input No. Pin No. Name NAND Tree

Input No. Pin No. Name

1 127 RST 18 7 AD20 35 34 AD13

2 128 PCI_CLK 19 9 AD19 36 36 AD12

3 129 GNT 20 10 AD18 37 37 AD11

4 130 REQ 21 12 AD17 38 39 AD10

5 132 AD31 22 14 AD16 39 40 AD9

6 135 AD30 23 15 C/BE24041 AD8

7 136 AD29 24 17 FRAME 41 42 C/BE0

8 137 AD28 25 18 IRDY 42 44 AD7

9 138 AD27 26 20 TRDY 43 46 AD6

10 140 AD26 27 22 DEVSEL 44 47 AD5

11 142 AD25 28 23 STOP 45 49 AD4

12 143 AD24 29 25 PERR 46 50 AD3

13 144 C/BE3 30 26 SERR 47 52 AD2

14 1 IDSEL 31 28 PAR 48 54 AD1

15 2 AD23 32 30 C/BE14955 AD0

16 4 AD22 33 31 AD15

17 6 AD21 34 33 AD14

94 Am79C978

Figure 49. NAND Tree Waveform

Reset

There are four different types of RESET operations that

may be performed on the Am79C978 device,

H_RESET, S_RESET, S TOP, and POR. The follo wing

is a description of each type of RESET operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C978 reset

operation that has been created by the proper asser-

tion of the RST pin o f the A m79C978 devi ce wh ile th e

PG pin is HIGH. When the minimum pulse width timing

as specified in the RST pin description has been satis-

fied, an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR reg-

isters to their default value. Note that there are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for details.

H_RESET will clear most of the registers in the PCI

configuration space. H_RESET will cause the micro-

code program to jump to its reset sta te. Following the

end of the H_RESET operation, the controller will at-

tempt to read the EEPROM device through the EE-

PROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the con-

troller will be in 16-bit I/O mode after the reset opera-

tion. A DWord write operation to the RDP (I/O offset

10h) must be performed to set the device into 32-bit

I/O mode.

S_RESET

Software Reset (S_RESET) is an Am79C978 reset op-

eration that has been created by a read ac cess to th e

Reset register, which is located at offset 14h in Word

I/O mode or offset 18h in DWord I/O mode from the

Am79C978 I/O or memory mapped I/O base address.

S_RE SET wil l reset al l of or some porti ons of CS R0, 3,

4, 15, 80, 100, and 124 to default values. For the iden-

tity of individual CSRs and bit locations that are af-

fected by S_RESET, see the individual CSR register

descriptions. S_RESET will not affect any PCI configu-

ration space location. S_RESET will not affect any of

the BCR re gister values. S _RESET will cau se the mi-

crocode program to jump to its reset state. Following

the end of the S_RESET operation, the controller will

not attempt to read the EEPROM device. After

S_RESET, the host must perform a full re-initialization

of the controller before starting network activity.

S_RESET will cause REQ to deassert immediately.

STOP (CSR0, bit 2) or SPND (CSR5, bit 0) can be

used to terminate any pending bus mastership request

in an orderly sequence.

S_RESE T te rminates al l n etwork ac tiv i ty a bruptl y. Th e

host can use the suspend mode (SPND, CSR5 , bit 0)

to terminate all network activity in an orderly sequence

before issuing an S_RESET.

RST

CLK

GNT

REQ

AD[31:0]

C/BE[3:0]

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

INTA

FFFFFFFF

0000FFFF

... ... ...

22206B-53

Am79C978 95

STOP

A STOP reset is generated by the assertion of the

STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,

when the stop bit currently has a value of 0, will initiate

a STOP reset. If the STOP bit is already a 1, then writ-

ing a 1 to the STOP bit will not generate a STOP reset.

STOP will reset all or some portions of CSR0, 3, and 4

to default values. For the identity of individual CSRs

and bit locations that are affected by STOP, see the in-

dividual CSR register descriptions. STOP will not affect

any of the BCR and PCI configuration space locations.

STOP will cause the microc ode prog ram to jump to its

reset state. Following the end of the STOP operation,

the controller will not attempt to read the EEPROM de-

vice.

Note: STOP will n ot cause a dea ssertion of th e REQ

signal, if it happens to be active at the time of the write

to CSR0. The controller will wait until it gains bus own-

ership, and it will first finish all scheduled bus master

accesses before the STOP reset is executed.

STOP terminates all network activity abruptly . The host

can use the suspend mode (SPND, CSR5, bit 0) to ter-

minate all network activity in an orderly sequence be-

fore setting the STOP bit.

Power on Reset

Power on Res et (POR ) is gen erate d when the con tro l-

ler is powered up. POR generates a hardware reset

(H_RESET). In addition, it clears some bits that

H_RESET does not affect.

Software Access

PCI Configuration Registers

The controller implements the 256-byte configuration

space as defined by the PCI draft specification revision

2.2. The 64- byte header incl udes all regis ter s req ui re d

to identify the controller and its function. Additionally,

PCI Power Man age men t In ter fac e regi ste rs are impl e-

mented at location 40h - 47h. The layout of the PCI

configuration space is shown in Table 24.

The PCI co nfi gur ation regi ste rs a re ac ces si ble on ly by

configuration cycles. All multi-byte numeric fields follow

little endian byte ordering. All write accesses to Re-

served locations have no effect; reads from these loca-

tions will return a data value of 0.

Table 24. PCI Configuration Space Layout

I/O Resources

The Am79C978 controller requires 32 bytes of address

space for access to all the various internal registers as

well as to some setup information stored in an external

serial EEPROM. A software reset port is available, too.

The Am79C978 controller supports mapping the ad-

dress space to both I/O and memory space. The value

in the PCI I/O Base Address register determines the

start addres s of the I/O ad dress sp ace. Th e registe r is

typically programmed by the PCI configuration utility

after system power-up.

31 24 23 16 15 8 7 0 Offset

Device ID Vendor ID 00h

Status Command 04h

Base-Class Sub-Class Programming IF Revision ID 08h

Rese rve d Header Type Latenc y Timer Reserv ed 0Ch

I/O Base Address 10h

Memory Mapped I/O Base Address 14h

Reserved 18h

Reserved 1Ch

Reserved 20h

Reserved 24h

Reserved 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CAP-PTR 34h

Reserved 38h

MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch

PMC NXT_ITM_PTR CAP_ID 40h

DATA_REG PMCSR_BSE PMCSR 44H

Reserved .

Reserved FCh

96 Am79C978

The PCI configuration utility must also set the IOEN bit

in the PCI Command register to enable I/O accesses to

the Am79C978 controller . For memory mapped I/O ac-

cess, th e P CI Me mor y Ma ppe d I/O Bas e A ddr ess re g-

ister controls the start address of the memory space.

The MEMEN bit in the PCI Command register must also

be set to enable the mode. Both base address registers

can be active at the same time.

The Am7 9C978 con troller supp orts two modes for ac -

cessing the I/O resources. For backwards compatibility

with AMD’s 16-bit E ther ne t co ntr ol lers , Word I/O is the

default mode after power up. The device can be config-

ured to DWord I/O mode by software.

I/O Registers

The Am79C978 controller registers are divided into two

groups. The Control and Status Registers (CSR) are

used to confi gure the Etherne t MAC eng ine and to ob-

tain status information. The Bus Control Registers

(BCR) are used to configure the bus interface unit and

the LEDs. Both sets of registers are accessed using in-

direct addre ss in g.

The CSR and BCR share a common Register Address

Port (RAP). There are, however, separate data ports.

The Register Data Port (RDP) is used to access a

CSR. The BCR Data Port (BDP) is used to access a

BCR.

In order to a ccess a part icular CSR locati on, the RAP

should first be written with the appropriate CSR ad-

dress. The RDP wi ll the n p oi nt t o th e s el ected CS R. A

read of the RDP will yield the selected CSR data. A

write to the RDP will write to the selected CSR. In order

to access a particular BCR location, the RAP should

first b e written with the appr opriate BCR add ress . The

BDP will th en p oi nt to the sele ct ed B CR. A r ea d o f th e

BDP will yield the selected BCR data. A write to the

BDP will write to the selected BCR.

Once th e RA P ha s been written wit h a v alu e, the RAP

valu e remains un changed unt il another RAP write oc -

curs, or until an H_RESET or S_RESET occurs. RAP

is cleared to all 0s when an H_RESET or S_RESET oc-

curs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C978 controller allows for connection of a

serial EEPROM. The first 16 bytes of the EEPROM will

be automatically loaded into the Address PROM

(APROM) space after H_RESET. Add itionall y, the first

six bytes of the EEPROM will be loaded into CSR12 to

CSR14. The Address PROM space is a convenient

place to store the value of the 48-bit IEEE station ad-

dress. It can be ov erwritte n by the host com puter, and

its content has no effect on the operation of the

Am79C978 controller. The software must copy the sta-

tion addres s from the Add re ss PRO M s pace to the in i-

tialization block in order for the receiver to accept

unicast frames directed to this station.

The six bytes of the IEEE station address occupy the

first six locations of the Address PROM space. The

next six bytes are reserved. Bytes 12 and 13 should

matc h th e val ue of t he ch ecks um o f byte s 1 th roug h 11

and 14 and 15. Bytes 14 and 15 should each be ASCII

“W” (57h). The above requirements must be met in

order to be compatible with AMD driver software.

APROMWE bit (BCR2, bit 8) must be set to 1 to enable

write access to the Addre ss PROM space.

Reset Register

A read of the Reset register creates an internal soft-

ware reset (S_RESET) pulse in the Am79C978 control-

ler. The internal S_RESET pulse that is generated by

this access is different from both the assertion of the

hardware RS T pin (H_RES ET) an d from th e asser tion

of the software STOP bit. Specifically , S_RESET is the

equival ent of th e as s ertio n of the RST pin (H _ RES ET )

except that S_RESET has no effect on the BCR or PCI

Configuration space locations.

The NE2100 LANCE-based family of Ethernet cards

requires that a write access to the Reset register fol-

lows each read access to the Reset register. The

Am79C 978 controll er does not ha ve a similar r equire-

ment. The write access is not required and does not

have any effect.

Note: The Am79C978 controller cannot service any

slave accesses for a very short time after a read access

of the Reset register, because the internal S_RESET

operation takes about 1 ms to finish. The Am79C978

controlle r wi ll term ina te al l sl av e acces s es with the as-

sertion of DEVSEL and STOP while TRDY is not as-

serted, signaling to the initiator to disconnect and retry

the access at a later time.

Word I/O Mode

After H_RESET, the Am79C978 controller is pro-

grammed to operate in Word I/O mode. DWIO (BCR18,

bit 7) will be cleared t o 0. Tabl e 25 shows how th e 32

bytes of address space are used in Word I/O mode.

All I/O resour ces must be acces sed in word quantiti es

and on word addresses. The Address PROM locations

can also be read in byte quantities. The only allowed

DWord operation is a write access to the RDP, which

switches the device to DWord I/O mode. A read access

other th an li st ed in the table below wi ll y ield undef ined

data; a write operation may cause unexpected repro-

gramming of the Am79C978 control registers. Table 26

shows legal I/O accesses in Word I/O mode.

Am79C978 97

Double Word I/O Mode

The Am79C978 controller can be configured to operate

in DWord (32-bit) I/O mode. The software can invoke

the DWIO mode by performing a DWord write access

to the I/O location at offset 10h (RDP). The data of the

write access must be such that it does not affect the in-

tended operation of the Am79C978 controller. Setting

the device into 32-bit I/O mode is usually the first oper-

ation after H_RESET or S_RESET. The RAP register

will point to CSR0 at that time. Writing a value of 0 to

CSR0 is a safe operation. DWIO (BCR18, bit 7) will be

set to 1 as an indic ation th at the Am 79C978 c ontr oller

operates in 32-bit I/O mode.

Note: Even though the I/O resource mapping changes

when the I/O mode setti ng ch anges, the RDP loca tion

offset is the s ame fo r both m odes. Once the DW IO bit

has been set to 1, only H_RESET can clear it to 0. The

DWIO mode setti ng is unaf fected by S_RE SET or set-

ting of the STOP bit. Table 27 shows how the 32 bytes

of address space are used in DWord I/O mode.

All I/O resources must be accessed in DWord quanti-

ties and on DWord addresses. A read access other

than listed in Table 27 will yield undefined data, a write

operation may cause unexpected reprogramming of

the Am79C978 control registers.

Table 25. I/O Map in Word I/O Mode (DWIO = 0)

Offset No. of

Bytes Register

00h - 0Fh 16 APROM

10h 2RDP

12h 2RAP (shared by RDP and BDP)

14h 2Reset Register

16h 2BDP

18h - 1Fh 8Reserved

Table 26. Legal I/O Accesses in Word I/O Mode (DWIO = 0)

AD[4:0] BE[3:0] Type Comment

0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h, or Ch

0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h, or Dh

0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah, or Eh

0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh, or Fh

0XX00 1100 RD Word read of APROM locatio ns 1h (M SB) and 0h (L SB), 5h and 4h, 8h an d 9h, or

Ch and Dh

0XX10 0011 RD Word read of APRO M loca tions 3h (M SB) and 2h (L SB), 7h and 6 h, Bh a nd Ah, or

Fh and Eh

10000 1100 RD Word read of RDP

10010 0011 RD Word read of RAP

10100 1100 RD Word read of Reset Register

10110 0011 RD Word read of BDP

0XX00 1100 WR Word write to APRO M locat ions 1 h (MSB) and 0h (LSB), 5 h and 4h , 8h and 9h, or

Ch and Dh

0XX10 0011 WR Word write to APR OM locati ons 3h (MSB ) and 2h (LSB), 7h and 6h, Bh an d Ah, or

Fh and Eh

10000 1100 WR Word write to RDP

10010 0011 WR Word write to RAP

10100 1100 WR Word write to Reset Register

10110 0011 WR Word write to BDP

10000 0000 WR DWord write to RDP,

switches device to DWord I/O mode

98 Am79C978

Table 27. I/O Map in DWord I/O Mode (DWIO = 1)

Table 28. Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

10BASE-T Physical Layer

The 10BASE-T block consists of the following sub-

blocks:

—Transmit Process

—Receive Process

—Interface Status

—Collision Detect Function

—Jabbe r Func tio n

—Reverse Polarity Detect

Refer to Figure 50 for the 10BASE-T block diagram.

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium re-

quires use of the integ rated 10 BA SE - T MAU and us es

the differential driver circuitry on the TX± pins.

TX± is a differential twisted-pair driver. When properly

terminat ed, TX± will meet the transmi tter electrical r e-

quirements for 10BASE-T transmitters as specified in

IEEE 802.3, Section 14.3.1.2. The load is a twisted pair

cable that meets IEEE 802.3, Section 14.4.

The TX± signal is filtered on the chip to reduce har-

monic content per Section 14.3.2.1 (10BASE-T). Since

filteri ng is performe d in silicon, TX± can be conne cted

directly to a standard transformer. External filtering

modules are not needed.

Twisted Pair Receive Function

The RX+ port is a differential twisted-pair receiver.

When properly term inated, the RX+ port will meet the

electrical requirements for 10BASE-T receivers as

specified in IEEE 802.3, Section 14.3.1.3. The receiver

has internal filtering and does not require external filter

modules or common mode chokes.

Signals appearing at the RX± differential input pair are

routed to the internal decoder. The receiver function

meets the propagation delays and jitter requirements

specified by the 10BASE-T standard. The receiver

squelc h le ve l dr op s t o hal f i ts thresh ol d v alu e aft er un-

squelch to allow reception of minimum amplitude sig-

nals and to mitigate carrier fade in the event of worst

case signal attenuation and crosstalk noise conditions.

Figure 50. 10BASE-T Transmit and Receive Data

Paths

Twisted Pair Interface Sta tus

The Am79C978 device will power up in the Link Fail

state. The Auto-Negotiation algorithm will apply to

allow it to enter the Link Pass state.

Offset No. of Bytes Register

00h - 0Fh 16 APROM

10h 4RDP

14h 4RAP (shared by RDP and

BDP)

18h 4Reset Register

1Ch 4BDP

AD[4:0] BE[3:0] Type Comment

0XX00 0000 RD

DWord read of APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8 h, o r Fh to

10000 0000 RD DWord read of RDP

10100 0000 RD DWord read of RAP

11000 0000 RD DWord read of Reset

0XX00 0000 WR

DWord write to APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8 h, o r Fh to

10000 0000 WR DWord write to RDP

10100 0000 WR DWord write to RAP

11000 0000 WR DWord write to Reset

Clock Data

Manchester

Encoder

Clock Data

Manchester

Decoder

Squelch

Circuit

RX Driver

RX±TX±

TX Driver

22206B-54

Am79C978 99

In the Link Pass state, receive activity which passes

the puls e width/ amplitude requ irements of the RX± i n-

puts will cause the PCS Control block to assert Carrier

Sense (CRS) signal at the internal MII interface. A col-

lision would cause the PCS Control block to assert Car-

rier Sense (CRS) and Collision (COL) signals at the

internal MII. In the Link Fail state, this block would

cause the PCS Control block to de-assert Carrier

Sense (CRS) and Colli sion (COL) .

In jabber detect mode, this block would cause the PCS

Control block to assert the COL signal at the internal

MII and allow the PCS Control block to assert or de-as-

sert the CRS pin to indicate the current state of the RX±

pair. If there is no receive activity on RX±, this block

would cause the PCS Control block to assert only the

COL pin at the internal MII. If there is RX± activity, this

block would cause the PCS Control block to assert

both COL and CRS at the internal MII.

Collision Detect Function

Simultaneous activity (presence of valid data signals)

from both the internal encoder transmit function and

the twisted pair RX± pins constitutes a collision,

thereby causing the PCS Control block to assert the

COL pin at the internal MII.

Jabber Function

The Jabber function inhibits the 10BASE-T twisted pair

transmit function of the Am79C978 device if the TX±

circuits are active for an excessive period (20-150 ms).

This prevents one port from disrupting the network due

to a stuck-on or faulty transmitter condition. If the max-

imum transmit time is exceeded, the data path through

the 10BASE-T transmitter circuitry is disabled (al-

though Lin k Test pulses will continue to be sent). Th e

PCS Control block also asserts the COL signal at the

internal MII and sets the Jabber Detect bit in Register 1

of the active PHY. Once the internal transmit data

stream from the Manchester Encoder/Decoder stops,

an unjab time of 250-750 ms will elapse before this

block causes the PCS Control block to de-assert the

COL indication and re-enable the transmit circuitry.

When jabber is detected, this block will cause the PCS

Control block to assert the COL signal and allow the

PCS Control block to assert or de-assert the CRS sig-

nal to indicate the current state of the RX± pair. If there

is no receive activity on RX±, this block causes the

PCS Control block to assert only the COL signal at the

internal MII. If there is RX± activity , this block will cause

the PCS Control block to assert both COL and CRS on

the internal MII.

Reverse Polarit y Detect

The polarity for 10BASE-T signals is set by reception of

Normal Link Pulses (NLP) or packets. Polarity is

locked, however, by incoming packets only. The first

NLP received when trying to bring the link up will be ig-

nored, but it will set the polarity to the correct state. The

reception of two consecutive packets will cause the po-

larity to be locked, based on the polarity of the ETD. In

order to change the polarity once it has been locked,

the link must be brought down and back up again.

Auto-Negotiation

The object of the Au to- Neg oti ati on functi on is to deter -

mine the abilities of the devices sharing a link. After ex-

changing abilities, the Am79C978 device and remote

link pa rt ner de vi ce ac k nowl edg e e ac h ot her an d m ak e

a choice of which advertised abilities to support. The

Auto-Negotiation function facilitates an ordered resolu-

tion between exchanged abilities. This exchange al-

lows both devices at either end of the link to take

maximum advantage of their respective shared abili-

ties.

The Am79C978 device implements the transmit and

receive A uto -Negotia tio n algori thm as define d in IE EE

802.3u, Section 28. The Auto-Negotiation algorithm

uses a burst of link pulses called Fast Link Pulses

(FLPs). The burst of link pulses are spaced between 55

and 140 µs so as to be ignored by the standard

10BASE -T algorit hm. The FLP burst co nveys info rma-

tion about the abilities of the sending device. The re-

ceiver can accept and decode an FLP burst to learn the

abilities of the sending device. The link pulses transmit-

ted conf orm to the standard 1 0BASE-T template . The

device can perform auto-negotiation with reverse po-

larity link pulses.

The Am79C978 device uses the Auto-Negotiation al-

gorithm to select the type connection to be established

according to the following priority: 10BASE-T full du-

plex, then 10BASE-T half-duplex. See Table 29.

The Auto-Negotiation algorithm is initiated by the fol-

lowing events: Auto-Negotiation enable bit is set, hard-

ware res et, so ft res et , tr an siti on to li nk fa il s tate ( whe n

Auto-Negotiation enable bit is set), or Auto-Negotiation

restart bit is set. The result of the Auto-Negotiation pro-

cess can be read from the status register (Summary

Status Register, TBR24).

By default, the link partner must be at least 10BASE-T

half-duplex capable. The Am79C978 controller can au-

tomatically negotiate with the network and yield the

highest performance possible without software sup-

port. See the Network Port Manager section for more

details.

Table 29. Auto-Negotiation Capabilities

Network Speed Physical Network Type

20 Mbps 10BASE-T, Full Duplex

10 Mbps 10BASE-T, Half Duplex

100 Am79C978

Auto-Negotiation goes further by providing a message-

based communication scheme called Next Pages be-

fore co nnecti ng to the L ink Partn er. This featur e is no t

supported in the Am79C978 device unless the DANAS

(BCR32, bit 10) is selected.

Soft Reset Function

The PHY Control Register (TBR0) incorporates the soft

reset functi on (bit 15). It is a read/wr ite register and is

self-c le ar ing . Writin g a 1 to thi s bi t cau ses a so ft re se t.

When read, the register returns a 1 if the soft reset is

still being performed; otherwise, it is cleared to 0. Note

that the register can be polled to verify that the soft

reset has terminated. Under normal operating condi-

tions, soft reset will be finished in 150 clock cycles.

Soft reset only resets the 10BASE-T PHY unit registers

to default values (some register bits retain their previ-

ous values). Refer to the individual registers for values

after a soft reset. Soft reset does not reset the manage-

ment interface.

Am79C978 101

USER ACCESSIBLE REGISTERS

The Am79C978 controller has four types of user regis-

ters: the PCI configuration registers, the Control and

Status registers (CSRs), the Bus Control registers

(BCRs), 10BASE-T PHY Management registers

(TBRs), and 1 Mbps HomePNA PHY Management reg-

isters (HPRs).

The Am79C978 controller implements all PCnet-ISA

(Am79C960) registers, all C-LANCE (Am79C90) regis-

ters, plus a number of additional registers. The

Am79C978 CS Rs are compatib le upon power u p with

both the PCnet-ISA CSRs and all of the C-LANCE

CSRs.

The PCI configuration registers can be accessed in any

data width. All other registers must be accessed ac-

cording to the I/O mode that is currently selected.

When WIO mode is selected, all other register loca-

tions are defined to be 16 bits in width. When DWIO

mode is selected, all these register locations are de-

fined to be 32 bits in width, with the upper 16 bits of

most register locations marked as reserved locations

with undefi ned v alues. W hen pe rformin g regi ster writ e

operations in DWIO mode, the upper 16 bits should al-

ways be written as zeros. When performing register

read operations in DWIO mode, the upper 16 bits of

I/O resources should always be regarded as having un-

defined values, except for CSR88.

The Am79C978 registers can be divided into four

groups: PCI Configuration, Setup, Running, and Test.

Registers not included in any of these categories can

be assumed to be intended for diagnostic purposes.

nPCI Configuration Registers

These registers are intended to be initialized by the

system initialization procedure (e.g., BIOS device ini-

tialization routine) to program the operation of the con-

troller PCI bus interface.

The following is a list of the registers that would typi-

cally need to be programmed once during the initializa-

tion of the Am79C978 controller within a system:

—PCI I/O Base Address or Memory Mapped I/O

Base Address register

—PCI Expansion ROM Base Address register

—PCI Interrupt Line register

—PCI Latency Timer register

—PCI Status register

—PCI Command register

—OnNow register

nSetup Registers

These registers are intended to be initialized by the de-

vice driver to program the operation of various control-

ler features.

The following is a list of the registers that would typi-

cally need to be programmed once during the setup of

the contr oller wi thin a sy stem. T he contr ol bits in eac h

of these regi sters typica lly do not need to be modi fied

once they have been written. However , there are no re-

strictions as to how many times these registers may ac-

tually be accessed. Note that if the default power up

values of any of these registers is acceptable to the ap-

plicati on, then s uch regi sters n eed ne ver be ac cesse d

at all.

Note: Registers marked with “^” may be programma-

ble through the EEPROM read operation and, there-

fore, do not necessarily need to be written to by the

system initialization procedure or by the driver soft-

ware. Registers marked with “*” will be initialized by the

initialization block read operation.

CSR1 Initialization Block Address[15:0]

CSR2* Initialization Block Address[31:16]

CSR3 Interrupt Masks and Deferral Control

CSR4 Test and Features Control

CSR5 Ex te nded Contr ol and Inte rrup t

CSR7 Ex te nded Contr ol and Inte rrup t2

CSR8* Logical Address Filter[15:0]

CSR9* Logical Address Filter[31:16]

CSR10* Logical Address Filter[47:32]

CSR11* Logical Address Filter[63:48]

CSR12*^ Physical Address[15:0]

CSR13*^ Physical Address[31:16]

CSR14*^ Physical Address[47:32]

CSR15* Mode

CSR24* Base Address of Receive Ring Lower

CSR25* Base Address of Receive Ring Upper

CSR30* Base Address of Transmit Ring Lower

CSR31* Base Address of Transmit Ring Upper

CSR47* Transmit Polling Interval

CSR49* Receive Polling Interval

CSR76* Receive Ring Length

CSR78* Transmit Ring Length

CSR80 DMA Transfer Counter and FIFO Thresh-

old Control

CSR82 Bus Activity Timer

CSR100 Memory Error Timeout

CSR116^ OnNow Miscellaneous

CSR122 Receiver Packet Alignment Control

102 Am79C978

CSR125^ MAC Enhanced Configuration Control

BCR2^ Miscellaneou s Conf iguratio n

BCR4^ LED0 Stat us

BCR5^ LED1 Status

BCR6^ LED2 Status

BCR7^ LED3 Status

BC R9^ Full-Duplex Control

BCR18^ Bus and Burst Control

BCR19 EEPROM Control and Status

BC R20 Software Style

BCR22^ PCI Latency

BCR23^ PCI Subsystem Vendor ID

BCR24^ PCI Subsystem ID

BCR25^ SRAM Size

BCR26^ SRAM Boundary

BCR27^ SRAM Interface Control

BCR32^ Internal PHY Control and Status

BCR33^ Internal PHY Address

BCR35^ PCI Vendor ID

BCR36 PCI Power Management Capabilities

(PMC) Alias Register

BCR37 PCI DATA Register 0 (DATA0) Alias

BCR38 PCI DATA Register 1 (DATA1) Alias

BCR39 PCI DATA Register 2 (DATA2) Alias

BCR40 PCI DATA Register 3 (DATA3) Alias

BCR41 PCI DATA Register 4 (DATA4) Alias

BCR42 PCI DATA Register 5 (DATA5) Alias

BCR43 PCI DATA Register 6 (DATA6) Alias

BCR44 PCI DATA Register 7 (DATA7) Alias

BCR45 OnNow Pattern Matching Register 1

BCR46 OnNow Pattern Matching Register 2

BCR47 OnNow Pattern Matching Register 3

BCR48 LED4 Status

BCR49 PHY Select

nRunning Registers

These regi ste rs ar e i nte nde d t o be use d by the d evi c e

driver software after the Am79C978 controller is run-

ning to access status information and to pass control

information.

The following is a list of the registers that would typi-

cally n eed to be peri odically rea d and perhaps written

during the norma l r un nin g o per ati on of th e A m7 9C97 8

controller within a system. Each of these registers con-

tains control bits, or status bits, or both.

RAP Register Address Po rt

CSR0 Controller Status

CSR3 Interrupt Masks and Deferral Control

CSR4 Test and Features Control

CSR5 Extended Control and Interrupt

CSR7 Extended Control and Interrupt2

CSR112 Missed Frame Count

CSR114 Receive Collision Count

BCR32 Internal PHY Control and Status

BCR33 Internal PHY Address

BCR34 Internal PHY Management Data

nTest Registers

These registers are intended to be used only for testing

and diagnostic purposes. Those registers not included

in any of the above lists can be assumed to be intended

for diagnostic purposes.

PCI Configuration Registers

PCI Vendor ID Register

Offset 00h

The PCI V endor ID register is a 16-bit register that iden-

tifies the manufacturer of the Am79C978 controller.

AMD’s Vendor ID is 10 22h . Note that thi s Vendor I D is

not the same as the Manufacturer ID in CSR88 and

CSR89. The Vendor ID is assigned by the PCI Special

Interest Group.

The PCI Vendor ID register is located at offset 00h in

the PCI Configuration Space. It is read only.

This register is the same as BCR35 and can be written

by the EEPROM.

PCI Device ID Register

Offset 02h

The PCI Device ID register is a 16-bit register that

helps identify the Am79C978 controller within AMD's

product line. The Am79C978 Device ID is 2001h. Note

that this Device ID is not the sa me as the part number

in CSR88 and CSR89. The Device ID is assigned by

Am79C978 103

AMD. The PCI Device ID register is located at offset

02h in the PCI Configuration Space. It is read only.

PCI Command Register

Offset 04h

The PCI Command register is a 16-bit register used to

control the gross functionality of the Am79C978 con-

troller. It controls the Am79C978 controller’s ability to

generate and respond to PCI bus cycles. To logically

disconn ec t the Am 79C 978 devic e f ro m al l PCI b us cy-

cles except configuration cycles, a value of 0 should be

written to this register.

The PCI Command register is located at offset 04h in

the PCI Confi guration Sp ace. It is read and written by

the host.

Bit Name Description

15-10 RES Reserved locati ons. Read as ze-

ros; write operations have no ef-

fect.

9 FBTBEN Fast Back-to-Back Enable. Read

as zero; write operations have no

effect. The Am79C978 controller

will not generate Fast Back-to-

Back cycles.

8 SERREN SERR Enable. Controls the as-

ser tio n of t he S ERR pin. SERR is

disabled when SERREN is

cleared. SERR will be asserted

on detecti on of an addre ss p arity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN is cleared by

H_RESET and is not effecte d by

S_RESET or by setting the STOP

bit.

7 RES Reserved location. Read as ze-

ros; write operations have no ef-

fect.

6 PERREN Parity Error Response Enable.

Enables the parity error response

functions. When PERREN is 0

and the Am79C978 controller de-

tects a parity error, it only sets the

Detected Parity Error bit in the

PCI Status register. When PER-

REN is 1, the Am79C978 control-

ler asserts PERR on the

detection of a data parit y err or. It

also sets the DATAPERR bit (PCI

Status register, bit 8), when the

data parity error occurred during

a master cycle. PERREN also

enables reporting address parity

errors thr oug h th e S ERR pin and

the SERR bit in the PCI Status

PERREN is cleared by

H_RESET and is not affecte d by

S_RESET or by setting the STOP

bit.

5 VGASNOOP VGA Palette Snoop. Read as ze-

ro; write operations have no ef-

fect.

4 MWIE N M emo ry Wr it e and Inv ali da te Cy-

cle Enable. Read as zero; write

operations have no effect. The

Am79C978 controller only gener-

ates Memory Write cycles.

3 SCYCEN Special Cycle Enable. Read as

zero; write operations have no ef-

fect. The Am79C978 controller

ignores all Special Cycle opera-

tions.

2 BMEN Bus Master Enable. Setting

BMEN enables the Am79C978

controller to become a bus mas-

ter on the PCI bus. The host must

set BMEN before setting the INIT

or STRT bit in CSR0 of the

Am79C978 controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

1 MEMEN Memory Space Access Enable.

The Am79 C978 controller wi ll ig-

nore all memory accesses when

MEMEN is cleared. The host

must set MEMEN before the first

memory ac ce ss to the device.

For memory mapped I/O, the

host must program the PCI Mem-

ory Mapped I/O Base Address

dress before setting MEMEN.

For accesses to the Expansion

ROM, the host must pr ogram the

PCI Expansion ROM Base Ad-

dress register at offset 30h with a

valid memory address before set-

ting MEMEN. The Am79C978

104 Am79C978

control ler will onl y respond to ac-

cesses to the Expansion ROM

when both ROMEN (PCI Expan-

sion ROM Base Address register,

bit 0) and MEMEN are set to 1.

Since MEMEN also enables the

memory mapped access to the

Am79C978 I/O resources, the

PCI Memory Mapped I/O Base

Address register must be pro-

grammed with an address so that

the device does not claim cycles

not intended for it.

MEMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

0 IOEN I/O Space Access Enable. The

Am79C978 controller will ignore

all I/O accesses when IOEN is

cleared . The hos t mus t set IOE N

before the first I/O access to the

device. The PCI I/O Base Ad-

dress register must be pro-

grammed with a valid I/O address

before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

PCI Status Register

Offset 06h

The PCI Status register is a 16-bit register that contains

status inf ormation for the PCI bus related events. It is

located at offset 06h in the PCI Configuration Space.

Bit Name Description

15 PERR Parity Error. PERR is set when

the Am79C978 controller detects

a parity error.

The Am79C978 controller sam-

ples the AD[31:0], C/BE[3:0 ], a nd

the PAR li nes fo r a pari ty error a t

the following times :

• In slave mode, during the ad-

dress phase of any PCI bus com-

mand.

• In slave mode , for al l I/O, me m-

ory, and c onfigur ation writ e com-

mands that select the Am79C978

controller when data is trans-

ferred (TRDY and IRDY are as-

serted).

• In master mode, during the data

phase of all memory read com-

mands.

In master mode, during the data

phase of the memory write com-

mand, the Am79C978 controller

sets the PERR bit if the target re-

ports a data parity error by as-

serting the PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the Am79C978

controller and cleared by writing a

1. Writing a 0 has no effect.

PERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

14 SERR Signaled SERR. SERR is set

when the Am79C978 controller

detects an address parity error

and both SERREN and PERREN

(PCI Command register, bits 8

and 6) are set.

SERR is set by the Am79C978

controller and cleared by writing a

1. Writing a 0 has no effect.

SERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

13 RMABORT Received Master Abort. RM-

ABORT is set when the

Am79C978 controller terminates

a master cycle with a master

abort sequence.

RMABORT is set by the

Am79C978 controller and

cleared by writing a 1. Writing a 0

has no effect. RMABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

12 RTABORT Received Target Abort. RT-

ABORT is set when a target ter-

minates an Am79C978 master

cycle with a target abort se-

quence.

Am79C978 105

RTABORT is set by the

Am79C978 controller and

cleared by writing a 1. Writing a 0

has no effect. RTABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

11 STABORT Send Target Abort. Read as ze-

ro; write operations have no ef-

fect. The Am79C978 controller

will never terminate a slave ac-

cess with a target abort se-

quence.

STABORT is read only.

10-9 DEVSEL Device Select Timing. DEVSEL

is set to 01b (medium), which

means that the Am79C978 con-

troller will assert DEVSEL two

clock per io ds aft er F RA ME is as-

serted.

DEVSEL is read only.

8 DATAPERR Data Parity Error Detected.

DATAPERR is set when the

Am79C978 controller is the cur-

rent bus master and it detects a

data parity error and the Parity

Error Response enable bit (PCI

Command register, bit 6) is set.

During the data phase of all

memory read commands, the

Am79C978 controller checks for

parity error by sampling AD[31:0],

C/BE[3:0], and the PAR lines.

During the data phase of all

memory write commands, the

Am79C978 controller che cks the

PERR input to detect whether the

target has reported a parity error.

DATAPERR is set by the

Am79C978 controller and

cleared by writing a 1. Writing a 0

has no effect. DATAPERR is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

7 FBTBC Fast Back-To-Back Capable.

Read as one; write operations

have no effect. The Am79C978

control ler is c apa bl e of acc ep ting

fast back-to-back transactions

with the first transaction address-

ing a different target.

6-5 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

4 NEW_CAP New Capabilities. This bit indi-

cates whether this function imple-

ments a list of extended

capabilities such as PCI power

management. When set, this bit

indicates the presence of New

Capabilities. A value of 0 means

that this fu nction does n ot imple-

ment New Capabilities.

Read as one; write operations

have no effect. The Am79C978

controller supports the Linked

Addit ional Capabilit ies Lis t.

3-0 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

PCI Revision ID Register

Offset 08h

The PCI Revision ID register is an 8-bit register that

specifies the Am79C978 controller revision number.

The value of this register is 5Xh with the lower four bits

being silicon-revision dependent.

The PCI Revision ID register is located at offset 08h in

the PCI Configuration Space. It is read only.

PCI Programming Interface Register

Offset 09h

The PCI Programming Interface register is an 8-bit reg-

ister that identifies the programming interface of

Am79C978 controller . PCI does not define any specific

vices. The value of this register is 00h.

The PCI Programming Interface register is located at

offset 09h in the PCI Configuration Space. It is read only.

PCI Sub-Class Register

Offset 0Ah

The PCI Sub-Class register is an 8-bit register that iden-

tifies specifically the function of the Am79C978 control-

ler . The value of this register is 00h which identifies the

Am79C978 device as an Ethernet controller.

The PCI Su b-Class regis ter is located at offset 0Ah i n

the PCI Configuration Space. It is read only.

106 Am79C978

PCI Base-Class Register

Offset 0Bh

The PCI Base-Class register is an 8-bit register that

broadly classifies the function of the Am79C978 con-

troller . The value of this register is 02h, which classifies

the Am79C978 device as a networking controller.

The PCI Base-Class register is located at offset 0Bh in

the PCI Configuration Space. It is read only.

PCI Latency Timer Register

Offset 0Dh

The PCI Latency Timer register is an 8-bit register that

specifies the minimum guaranteed time the Am79C978

controller will control the bus once it starts its bus mas-

tership period. The time is measured in clock cycles.

Every time the Am79C978 controller asserts FRAME at

the beginning of a bus mastership period, it will copy

the value of the PCI Latency Timer register into a

counter and start counting down. The counter will freeze

at 0. Wh en the s ystem arbiter remove s GNT whil e the

counter is non-zero, the Am79C978 controller will con-

tinue with i ts data tra ns fers. I t will o nly r ele as e the bus

when the counter has reached 0.

The PCI Latency Timer is only significant in burst trans-

actions, where FRAME stays asserted until the last data

phase. In a non-burst transaction, FRAME is only as-

serted during the address phase . The internal latency

counter will be cleared and suspended while FRAME is

deasserted.

All eight bits of the PCI Latency Timer register are pro-

grammab le. The hos t should r ead the Am79C9 78 PCI

MIN_GNT and PCI MAX_LAT registers to determine the

latency requireme nts for the device and then initialize

the Latency Timer register with an appropriate value.

The PCI Latency T imer register is located at offset 0Dh

in the PCI Configuration Space. It is read and written by

the host. The PCI Lat enc y Timer regi st er is c l eared by

H_RESET and is not effected by S_RESET or by setting

the STOP bit.

PCI Header Type Register

Offset 0Eh

The PCI Header Type register is an 8-bit register that

describes the format of the PCI Configuration Space

loca tions 10h to 3Ch and that i dentifi es a device t o b e

single o r mult i-fun ction. The PC I Header Type reg ister

is located at address 0Eh in the PCI Configuration

Space. It is read only.

Bit Name Description

7 FUNCT Single-function/multi-function de-

vice. Read as zero; write opera-

tions have no effect. The

Am79C978 controller is a single

function device.

6-0 LAYOUT PCI configuration space layout.

Read as zeros; write operations

have no effect. The la yout of the

PCI configuration space loca-

tions 10h to 3Ch is as shown in

Table 24.

PCI I/O Base Address Register

Offset 10h

The PCI I/O Base Address register is a 32-bit register

that determines the location of the Am79C978 I/O re-

sources in all of I/O sp ace. It is lo ca ted at offset 10h in

the PCI Configuration Space.

Bit Name Description

31-5 IOBASE I/O base address most significant

27 bits. These bit s are written by

the host to s pe cify the l ocati on o f

the Am79C978 I/O resources in

al l of I/ O sp ace. IOB AS E mus t be

written with a valid address be-

fore the Am79C978 controller

slave I/O mode is turned on by

setting the IOEN bit (PCI Com-

mand register , bit 0).

When the Am79C978 controller

is enable d for I/O mode (IOEN is

set), it monitors the PCI bus for a

valid I/O command. If the value

on AD[31:5] during the address

phase of the cycles matches the

value of IOBASE, the Am79C978

control ler wil l dri ve DEV SEL ind i-

cating it will respond to the ac-

cess.

IOBASE is read and written by

the host. IOBASE is cleared by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

4-2 IOSIZE I/O size requirements. Read as

zeros; write operations have no

effect.

IOSIZE indicates the size of the

I/O space the Am79C978 control-

ler requires. When the host writes

a value of FFF F FFFFh to the I/O

Bas e Addr ess reg ister , it w ill r ead

back a value of 0 in bits 4-2. That

indicates an Am79C978 I/O

space requirement of 32 bytes.

1 RES Reserved location. Read as zero;

write operations have no effect.

Am79C978 107

0 IOSPACE I/O space indicator. Read as one;

write operations have no effect.

Indicating that this base address

address.

PCI Memory Mapped I/O Base Address Register

Offset 14h

The PCI Memory Mapped I/O Base Address register is

a 32-bit register that determines the location of the

Am79C9 78 I/O reso urces i n all of me mory s pace. It is

located at offset 14h in the PCI Configuration Space.

Bit Name Description

31-5 MEMBASE Memory mapped I/O base ad-

dress most significant 27 bits.

These bits are written by the host

to specify the location of the

Am79C978 I/O resources in all of

memory s pace . MEMB ASE m ust

be written with a valid address

before the Am79C978 controller

slave mem ory mapped I/O mode

is turned on by setting the ME-

MEN bit (PCI Command register,

bit 1).

When the Am79C978 controller

is enabled for memory mapped

I/O mode (MEMEN is set), it mon-

itors the PCI bus for a valid mem-

ory command. If the value on

AD[31:5] during the address

phase of the cycles matches the

value of MEMBASE, the

Am79C978 controller will drive

DEVSEL indicating it will respond

to the access.

MEMBASE is read and written by

the host. MEMBASE is cleared

by H_RESE T and is not affec ted

by S_RESET or by setting the

STOP bit.

4 MEMSIZE Memory mapped I/O size re-

quiremen ts . Read as ze r os; writ e

operations have no effect.

MEMSIZE indicates the size of

the memory space the

Am79C978 controller requires.

When the host writes a value of

FFFF FFFFh to the Memory

Mapped I /O B ase Addres s regis-

ter, it will read back a value of 0 in

bit 4. That indicates a Am79C978

memory space requirement of 32

bytes.

3 PREFETCH Prefetchable. Read as zero; write

operations have no effect. Indi-

cates that memory space con-

trolled by this base address

registe r is not prefetch able. Data

in the memory mapped I/O space

cannot be prefetched. Because

one of the I/O resources in this

address space is a Reset regis-

ter, the order of the read access-

es is important.

2-1 TYPE Memory type indicator. Read as

zeros; write operations have no

effect. Indicates that this base ad-

dress reg is ter is 3 2 bi ts wid e an d

mapping can be done anywhere

in the 32-bit memory space.

0 MEMSPACE Memory space indicator. Read

as zero; write operations have no

effect. Indicates that this base ad-

dress register describes a memo-

ry base address.

PCI Subsystem Vendor ID Register

Offset 2Ch

The PCI S ubsy ste m Vendor ID reg ister i s a 16- bi t reg-

ister that together with the PCI Subsystem ID uniquely

identifies the add-in card or subsystem the Am79C978

controller is used in. Subsystem V endor IDs can be ob-

tained from the PCI SIG. A value of 0 (the default) indi-

cates that the Am79C978 controller does not support

subsystem identification. The PCI Subsystem Vendor

ID is an alia s of BCR23, bits 15-0. It is prog ramm able

through the EEPROM.

The PCI Subsystem Vendor ID register is located at off-

set 2Ch in the PCI Configuration Space. It is read only.

PCI Subsystem ID Register

Offset 2Eh

The PCI Subsystem ID register is a 16-bit register that

together with the PCI Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the Am79C978

control ler is used in. Th e value of the Su bsystem ID is

up to the system vendor . A value of 0 (the default) indi-

cates that the Am79C978 controller does not support

subsyste m identifica tion. The P CI Subsyst em ID is a n

alias of BCR24, bits 15-0. It is programmable throug h

the EEPROM.

The PCI Subsystem ID register is located at offset 2Eh

in the PCI Configuration Space. It is read only.

108 Am79C978

PCI Expansion ROM Base Address Register

Offset 30h

The PCI Expansion ROM Base Address register is a

32-bit register that defines the base address, size, and

address align ment of an Ex pans ion ROM . It is locate d

at offset 30h in the PCI Configuration Space.

Bit Name Description

31-20 ROMBASE Expansion ROM base address

most significant 12 bits. These

bits are written by the host to

specify the location of the Expan-

sion ROM in all of memory spac e.

ROMBASE must be written with a

valid address before the

Am79C978 Expansion ROM ac-

cess is enabled by setting

ROMEN (PCI Expansion ROM

Base Ad dr es s reg is ter , b it 0) an d

MEMEN (PCI Command register,

bit 1).

Since the 12 mos t signific ant bits

of the base address are program-

mable, th e host c an map the Ex-

pansion ROM on any 1M

boundary.

When the Am79C978 controller

is enabled for Expansion ROM

access (ROMEN and MEMEN

are set to 1), it monitors the PCI

bus for a valid memory com-

mand. If the value on AD[31:2]

during the address phase of the

cycle falls between ROMBASE

and ROMBASE + 1M - 4, the

Am79C978 controller will drive

DEVSEL indicating it will respond

to the access.

ROMBASE is read and written by

the host. ROMBASE is cleared

by H_RESE T and is not affec ted

by S_RESET or by setting the

STOP bit.

19-1 ROMSIZE ROM size. Read as zeros; write

operation have no effect. ROM-

SIZE indicates the maximum size

of the Expansion ROM the

Am79C978 controller can sup-

port. The ho st can dete rmine th e

Expansion ROM size by writing

FFFF FFFFh to the Expansion

ROM Base Address register. It

will read back a value of 0 in bit

19-1, indicating an Expansion

ROM size of 1M.

Note that ROMSIZE only speci-

fies the maximum size of Expan-

sion ROM the Am79C978

controller supports. A smaller

ROM can also be used. The actu-

al size of the code in the Expan-

sion ROM is always determined

by reading the Expansion ROM

header.

0 ROMEN Expansion ROM En able. Written

by the host to enable access to

the Expansion ROM. The

Am79C978 controller will only re-

spond to a cces ses to th e Exp an-

sion ROM when both ROMEN

and MEMEN (PCI Command reg-

ister, bit 1) are set to 1.

ROMEN is read and written by

the host. ROMEN is cleared by

H_RESET an d is not effected by

S_RESET or by setting the STOP

bit.

PCI Capabilities Point er Register

Offset 34h

Bit Name Description

7-0 CAP_PTR The PCI Capabilities Pointer reg-

ister is an 8-bit register that points

to a linked list of capabilities im-

plemented on this device. This

40h.

The PCI Capabilities Pointer reg-

ister is located at offset 34h in the

PCI Configuration Space. It is

read only.

PCI Interrupt Line Register

Offset 3Ch

The PCI Inter rupt Line register is an 8-bit regi ster that

is used to communicate the routing of the interrupt.

This reg ister is written by the POST softwa re as it ini-

tializes the Am79C978 controller in the system. The

regist er is read by the netwo rk driver to determine the

interrupt channel which the POST software has as-

signed to the Am79 C978 controller. The PCI Interrupt

Line register is not modified by the Am79C978 control-

ler. It has no effect on the operation of the device.

The PCI Interr up t Li ne reg is ter i s located at offset 3C h

in the PCI Configuration Space. It is read and written by

Am79C978 109

the host. It is cl eare d by H_RE S ET an d i s no t affected

by S_RESET or by setting the STOP bit.

PCI Interrupt Pin Register

Offset 3Dh

This PCI Interrupt Pin register is an 8-bit register that

indicates the interrupt pin that the Am79C978 controller

is using. The value for the Am79C978 Interrupt Pin reg-

ister is 01h, which corresponds to INTA.

The PCI Interrupt Pin register is located at offset 3Dh in

the PCI Configuration Space. It is read only.

PCI MIN_GNT Register

Offset 3Eh

The PCI MIN_GNT register is an 8-bit register that

specifies the minimum length of a burst period that the

Am79C978 d evice needs to k eep up with the n etwork

activity. The length of the burst period is calculated as-

suming a clock rate of 33 MHz. The register value

specifies the time in units of 1/4 µs. The PCI MIN_GNT

mended that BCR22 be programmed to a value of

1818h.

The hos t should us e the v alu e i n t his r eg ister t o d e ter-

mine the setting of the PCI Latency Timer register.

The PCI MIN_GNT register is located at offset 3Eh in

the PCI Configuration Space. It is read only.

PCI MAX_LAT Register

Offset 3Fh

The PCI MAX_LA T register is an 8-bit register that spec-

ifies the maximum arbitration latency the Am79C978

control ler can susta in without cau sing problem s to the

netw ork acti vity. The reg ister va lue speci fies th e time in

units of 1/4 µs. The MAX_LAT register is an alias of

BCR22, bits 15-8. It is recommended that BCR22 be

programmed to a value of 1818h.

The hos t should us e the v alu e i n t his r eg ister t o d e ter-

mine the setting of the PCI Latency Timer register.

The PCI MAX_LAT register is located at offset 3Fh in

the PCI Configuration Space. It is read only.

PCI Capability Ide ntifier Register

Offset 40h

Bit Name Description

7-0 CAP_ID This register, when set to 1, iden-

tifies the linked list item as bein g

the PCI Power Management reg-

isters. T his regis ter has a default

value of 1h.

The PCI Capabilities Identifier

the PCI Configuration Space. It is

read only.

PCI Next Item Pointer R egister

Offset 41h

Bit Name Description

7-0 NXT_ITM_PTR

The Next Item Pointer Register

points to the starting address of

the next capability. The pointer at

this offset is a null pointer, indi-

cating that this is the last capabil-

ity in the linked list of the

capabilities. This register has a

default value of 0h.

The P CI Next P ointe r Regist er is

located at offset 41h in the PCI

Configuration Space. It is read

only.

PCI Power Management Capabilities Register

(PMC)

Offset 42h

Note: All bits of this register are loaded from the

EEPROM . Th e regis te r is alias ed to BC R36 for tes tin g

purposes.

Bit Name Description

15-11 PME_SPT PME Support. This 5-bit field indi-

cates the power states in which

the function may assert PME. A

value of 0b for any bit indicates

that the function is not capable of

ass er t ing t h e PM E si gn al w h il e in

that power state.

Bit(11) XXXX1b - PME can be

asserted from D0.

Bit(12) XXX1Xb - PME can be

asserted from D1.

Bit(13) XX1XXb - PME can be

asserted from D2.

Bit(14) X1XXXb - PME can be

asserted from D3hot.

Bit(15) 1XXXXb - PME can be

asserted from D3cold.

PME_SPT is read only.

110 Am79C978

10 D2_SPT D2 Support. If this bit is a 1, this

function supports the D2 Power

Management State.

This bit is read only.

9 D1_SPT D1 Sup port. If this bit is a 1, th is

function supports the D1 Power

Management State.

This bit is read only.

8-6 AUX_CURRENT

Auxiliary Current Requirements.

This 3-bit field reports the

3.3Vaux current req uir em ent s for

the PCI function. If the Data Reg-

ister has been implemented by

this function, then reads of this

field must return a value of 000b

and the Data Register will take

precedence over this field for

3.3Vaux current requirement re-

porting.

If PME generation from D3cold is

not supported by the function

(PMC (15) = 0), this field must re-

turn a value of 00 0b when re ad.

For functions that support PME

from D3cold and do not implement

the Data Register, the following

bit assignments apply:

These bits are read only.

5 DSI Device Specific Initialization.

When this bit is 1, it indicates that

special initialization of the func-

tion is require d (beyo nd the sta n-

dard PCI configuration header)

before the generic class device

driver is able to use it.

This bit is read only.

4 RES Reserved location.

3 PME_ CLK PME Cloc k. When this bit is a 1,

it indicates that the function relies

on the presence of the PCI clock

for PME operation . When this bi t

is a 0 it indicates that no PCI

clock is required for the function

to generate PME.

Functions that do not support

PME generation in any state

must return 0 for this field.

This bit is read only.

2-0 PMIS_VER Power Management Interface

Specification Version. A value of

001b indicates that this function

complies with revision 1.0 of the

PCI Power Management Inter-

face Specification.

PCI Power Management Control/Status Register

(PMCSR)

Offset 44h

Bit Name Description

15 PME_STATUS PME Status. This bit is set when

the function would normally as-

sert the PME s ignal independen t

of the state of the PME_EN bit.

Writing a 1 to this bit will clear it

and cause the function to stop as-

serting a PME (if enabled). Writ-

in g a 0 has no effect.

If the function supports PME from

D3cold, then this bit is sticky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

This bit is always read/write ac-

cessible . Sticky bit. Thi s bit is re-

set by POR. H_RESET,

S_RESET, or setting the STOP

bit has no effect.

Bit

8 7 6 3.3Vaux

Max. Current Required

1 1 1 375 mA

1 1 0 320 mA

1 0 1 270 mA

1 0 0 220 mA

0 1 1 160 mA

0 1 0 100 mA

0 0 1 55 mA

0 0 0 0 (self-powered)

Am79C978 111

14-13 DATA_SCALE

Data Scale. This 2-bit read-only

field indicates the scaling factor

to be used when interpreting the

value of the Data register. The

value and meaning of this field

will vary depending on the

DATA_SCALE field.

These bits are read only.

12-9 DATA_SEL Data Select. This optional 4-bit

field is used to select which data

is repo rted thro ugh the Data reg-

ister and DATA_SCALE field.

These bits are always read/write

accessible. Sticky bit. These bits

are reset by POR. H_RESET,

S_RESET, or setting the STOP

bit has no effect.

8 PME_EN PME Enable. When a 1,

PME_EN en ables the functi on to

assert PM E. When a 0, PME as-

sertion is disabled.

This bit defaults to “0” if the func-

tion does not support PME gener-

ation from D3cold.

If the function supports PME from

D3cold, the n this bi t is stic ky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

This bit is always read/write ac-

cessib le. Stic ky bit. This bit is re-

set by POR. H_RESET,

S_RESET, or setting the STOP

bit has no effect.

7-2 RES Reserved locations. These bits

are read only.

1-0 PWR_STATE Power State. This 2-bit field is

used both to determine the cur-

rent power state of a function and

to set the function into a new

power sta te. The de fin ition of th e

field values is given below.

00b - D0.

01b - D1.

10b - D2.

11b - D3.

These bits can be written and

read, but their contents have no

effect on th e operat ion o f the de-

vice.

These bits are always read/write

accessible.

PCI PMCSR Bridge Support Extensions Register

Offset 46h

Bit Name Description

7-0 PMCSR_BS E The PCI PM CSR Bri dge S upp ort

Extensions Register is an 8-bit

Extensions are not supported.

This register has a default value

of 00h.

The P CI PM CSR B ri dge S upp ort

Extensions register is located at

offset 46h in the PCI Configura-

tion Space. These bits are read

only.

PCI Data Register

Offset 47h

Note: All bits of this register are loaded from the

EEPROM . The re gis ter i s a lias ed to lower bytes of th e

BCR37-B CR44 for testing pur po ses.

Bit Name Description

7-0 DATA_REG The PCI Data Register is an 8-bit

Power Management Interface

Specification” version 1.0 for a

more detailed description of this

The PCI DATA register is located

at offset 47h in the PCI Configu-

ration Space. It is read only.

RAP Register

The RAP (Register Address Pointer) register is used to

gain access to CSR and BCR registers on board the

Am79C978 controller. The RAP contains the address

of a CSR or BCR.

As an exa mpl e of RAP us e, cons id er a read a cc es s to

CSR4. In order to access this register, it is necessary

to first load the value 0004h into the RAP by performing

a write access to the RAP offset of 12h (12h when WIO

mode has been selected, 14h when DWIO mode has

been selected). Then a second access is performed,

this time to the RDP offset of 10h (for either WIO or

DWIO mode). The RDP acces s is a read acc ess, and

112 Am79C978

since RAP has just been loaded with the value of 0004h,

the RDP read will yield the contents of CSR4. A read of

the BDP at this time (offset of 16h when WIO mode has

been selected, 1Ch when DWIO mode has been select-

ed) will yield the contents of BCR4, since the RAP is

used as the pointer into both BDP and RDP space.

RAP: Register Address Port

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 RES Reserved locations. Read and

written as zeros.

7-0 RAP Register Address Port. The value

of these 8 bits determines which

CSR or BCR will be accessed

when an I/O access to the RDP

or BDP po rt, respectiv ely, is per-

formed.

A write acces s to undefi ned CSR

or BCR lo cations may cause un-

expected reprogramming of the

Am79C978 control registers. A

read access will yield undefined

values.

These bits are always read/write

accessible. RAP is cleared by

H_RESET or S_RESET and is

unaffected by setting the STOP

bit.

Control and Status Registers (CSRs)

The CSR spac e is acc essibl e by perfo rming acce sses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will depend

upon the c urrent setti ng of the RAP. RAP serves a s a

pointer into the CSR space.

CSR0: Controller Status and Control Register

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear t he interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 ERR Error. Error is set by the OR of

CERR, MISS, and MERR. ERR

remains set as long as any of the

error flags ar e true .

This bit is always read accessible

only. Write operations are ig-

nored.

14 RES Reserv ed lo cat ion s. Thi s bi t is al -

ways read/write accessible.

Read retu rns zero.

13 CERR Collision Error. Collision Error is

set by the Am79C978 controller

when the device operates in half-

duplex m ode and the c oll is i on in-

puts to the GPSI port fail to acti-

vate within 20 network bit times

after the chip terminates trans-

missio n (SQE Tes t). This feat ure

is a transceiver test feature.

CERR reporting is disabled when

the GPSI port is active and the

Am79C9 78 co ntrol ler operates in

full-duplex mode.

When the MII port is selected,

CERR is only reported when the

external PHY is operating as a

half-duplex 10BASE-T PHY.

CERR assertion will not result in

an interrupt being generated.

CERR as ser tion w ill s et the E RR

bit.

This bit is always read/write ac-

cessible. C E RR is c le ar ed by th e

host by writing a 1. Writing a 0

has no effect. CERR is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

12 MISS Missed Frame. Missed Frame is

set by the Am79C978 controller

when it has lost an incoming re-

ceive frame resulting from a Re-

ceive Descriptor not being

available. This bit is the only im-

mediate indication that receive

data has been lost since there is

no current receive descriptor.

The Missed Frame Counter

(CSR112) also increments each

time a receive frame is missed.

When MISS is set, INTA is as-

serted if IENA is 1 and the mask

bit MISSM (CSR3, bit 12) is 0.

MISS assertion will set the ERR

bit, regardless of the settings of

IENA and MISSM.

Am79C978 113

This bit is always read/write ac-

cessible. MISS is cleared by the

host by writing a 1. Writing a 0

has no effect. MISS is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

11 MERR Memory Error. Memory Error is

set by the Am79C978 controller

when it requests the use of the

system interface bus by asserting

REQ and has not received GNT

assertion after a programmable

length of ti me. Th e l eng th of tim e

in micro seconds before MERR is

asserted will depend upon the

setting of the Bus Timeout Regis-

ter (CSR100). The default setting

of CSR100 will give a MERR after

153.6 ms of bus latency.

When MERR is set, INTA is as-

serted i f IENA is 1 and the ma sk

bit MERRM (CSR3, bit 11) is 0.

MERR assertion wil l set the E RR

bit, regardless of the settings of

IENA and MERRM.

This bit is always read/write ac-

cessible. MERR is cleared by the

host by writing a 1. Writing a 0

has no effect. MERR is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

10 RINT Receive Interrupt is set by the

Am79C978 controller after the

last des criptor o f a rec eive fr ame

has been update by writing a 0 to

the ownership bit (OWN). RINT

may also be set when the first de-

scriptor of a receive frame has

been updated by writing a 0 to the

ownership bit if the LAPPEN bit of

CSR3 has been set to a 1.

When RINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

RINTM (CSR3, bit 10) is 0.

This bit is always read/write ac-

cessible. RINT is cleared by the

host by writing a 1. Writing a 0

has no effec t. RINT is clea red by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

9 TINT Transmit Interrupt is set by the

Am79C978 controller after the

OWN bit in the last descriptor of a

transmit frame has been cleared

to indicate the frame has been

sent or an error occurred in the

transmission.

When TINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

TINTM (CSR3, bit 9) is 0.

TINT will not be set if TINTOKD

(CSR5, bit 15) is set to 1 and the

transmission was successful.

This bit is always read/write ac-

cessible. TINT is cleared by the

host by writing a 1. Writing a 0

has no effect. T INT is c leared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

8 IDON Initialization Done is set by the

Am79C978 controller after the

initialization sequence has com-

pleted. When IDON is set, the

Am79C978 controller has read

the initial ization bl ock from mem-

ory.

When IDON is set, INTA is as-

serted if IENA is 1 and the mask

bit IDONM (CSR3, bit 8) is 0.

This bit is always read/write ac-

cessible. IDON is cleared by the

host by writing a 1. Writing a 0

has no effect. IDON is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

7 INTR Interrupt Flag indicates that one

or more following interrupt caus-

ing conditions has occurred:

EXDINT, IDON, MERR, MISS,

MFCO, RCVCCO, RINT, SINT,

TINT, TXSTRT, UINT, STINT,

MREINT, MCCINT, MIIPDTINT,

MAPINT and the associated

mask or enable bit is pro-

grammed to allow the event to

cause an interrupt. If IE NA is set

to 1 and INTR is set, INTA will be

active. When INTR is set by SINT

or SLPINT, INTA will be active in-

dependent of the state of IENA.

114 Am79C978

This bit is always read accessi-

ble. INTR is read only. INTR is

cleared by clearing all of the ac-

tive individual interrupt bits that

have not been masked out.

6 IENA Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will

be disabled regardless of the

state of INTR.

This bit is always read/write ac-

cess ible. I ENA is s et by writ ing a

1 and cleared by writing a 0. IENA

is cleared by H_RESET or

S_RESET and set ting the STOP

bit.

5 RXON Receive On indicates that the re-

ceive fun ction is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the START bit is set. If

INIT and START are set together,

RXON will not be set until after

the initialization block has been

read in.

This bit is always read accessi-

ble. RXON is read only. RXON is

cleared by H_RESET or

S_RESET and set ting the STOP

bit.

4 TXON Transmit On indicates that the

transmit function is enabled.

TXON is set if DTX (CSR15, bit 1)

is set to 0 after the START bit is

set. If INIT and START are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

This bit will reset if the DXSUFLO

bit (CSR3, bit 6) is reset and there

is an underflow condition encoun-

tered.

Read accessible always. TXON

is read only. TXO N is cleared by

H_RESET or S_RESET and s et-

ting the STOP bit.

3 TDMD Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit De-

scriptor Ring without waiting for

the poll- time cou nter to elapse. If

TXON is not enabled, TDMD bit

will be reset and no Transmit De-

scriptor Ring access will occur.

TDMD is re quired to be set i f the

TXDPOLL bit in CSR4 is set. Set-

ting TDMD while TXDPOLL = 0

merely hastens the controller’s

response to a Transmit Descrip-

tor Ring Entry.

This bit is always read/write ac-

cessible. TDMD is set by writing a

1. Writing a 0 has no effect.

TDMD will be cleared by the Buff-

er Management Unit when it

fetches a Transmit Descriptor.

TDMD is cleared by H_RESET or

S_RESET and setting the STOP

bit.

2 STOP STOP assertion disables the chip

from all DMA activity. The chip re-

mains inactive until either STRT

or INIT are set. If STOP, STRT,

and INIT are all set together,

STOP will override STRT and

INIT.

This bit is always read/write ac-

cessible. STOP is set by writing a

1, by H_RESET or S_RESET.

Writing a 0 has no effect. STOP is

cleared by setting either STRT or

INIT.

1 STRT STRT assertion enables the

Am79C978 controller to send and

receiv e frames and per form buff-

er management operations. Set-

ting STR T clear s the STOP b it. If

STRT and INIT are set together,

the Am79C978 controller initial-

ization will be performed first.

This bit is always read/write ac-

cessible. STRT is set by writing a

1. Writing a 0 has no effect. STRT

is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

0 INIT INIT assertion enables the

Am79C978 controller to begin the

initialization procedure which

reads in the initialization block

from memory. Setting INIT clears

the STOP bit. If STRT and INIT

are set together, the Am79C978

controller initialization will be per-

Am79C978 115

formed first. INIT is not cleared

when the initialization sequence

has completed.

This bit is always read/write ac-

cessible. INIT is set by writing a 1.

Writing a 0 has no effect. INIT is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR1: Initialization Block Address 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADR[15:0] Lower 16 bits of the address of

the Initialization Block. Bit loca-

tions 1 and 0 must both be 0 to

align the initialization block to a

DWord boundary.

This register is aliased with

CSR16.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR2: Initialization Block Address 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 IADR[31 :24] If SSIZE 32 is set (BCR20, b it 8),

then the IADR[31:24] bits will be

used strictly as the upper 8 bits of

the initialization block address.

However, if SSIZE32 is reset

(BCR20, bit 8), then the

IADR[31:24] bits will be used to

generate the upper 8 bits of all

bus mastering addresses, as re-

quired for a 32-bit address bus.

Note that the 16-bit software

structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for the

Am79C978 bus master access-

es, while the 32-bit hardware for

which the Am79C978 controller is

intended will require 32 bits of ad-

dress. Therefore, whenever

SSIZE32 = 0, the IADR[31:24]

bits will be appended to the 24-bit

initiali zati on address , to eac h 24-

bit descriptor base address, and

to each beginning 24-bit buffer

address in order to form complete

32-bit addresses. The upper 8

bits that exist in the descriptor ad-

dress registers and the buffer ad-

dress registers which are stored

on board th e Am79C978 c ontrol-

ler will be overwritten with the

IADR[31:24] value, so that CSR

accesses to these registers will

show the 32-bit address that in-

cludes the appended field.

If SSIZE32 = 1, then software will

provide 32-bit pointer values for

all of the shared software struc-

tures - i.e., descriptor bases and

buffer addresses, and therefore,

IADR[31: 24] will not be written to

the upper 8 bits of any of these

resources, but it will be used as

the upper 8 bits of the initializa-

tion address.

This register is aliased with

CSR17.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

7-0 IADR[23:16] Bits 23 through 16 of the address

of the Initialization Block. When-

ever this register is written,

CSR17 is updated with CSR2’s

contents.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR3: Interrupt Masks and Deferral Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

116 Am79C978

15-13 RES Reserved locations. Read and

written as zero.

12 MISSM Missed Frame Mask. If MISSM is

set, the MISS bit will be masked

and unable to set the INTR bit.

This bit is always read/write ac-

cessible. MISSM is cleared by

H_RESET or S_RESET and is

not affected by STOP.

11 MERRM Memory Error Mask. If MERRM

is set, the MERR bit will be

masked and unable to set the

INTR bit.

This bit is always read/write ac-

cessible. MERRM is cleared by

H_RESET or S_RESET and is

not affected by STOP.

10 RINTM Receive Interrupt Mask. If RINTM

is set, the RINT bit will be masked

and unable to set the INTR bit.

This bit is always read/write ac-

cessible. RINTM is cleared by

H_RESET or S_RESET and is

not affected by STOP.

9 TINTM Transmit Interrupt Mask. If

TINTM is set , th e TINT b it wi ll b e

masked and unable to set the

INTR bit.

This bit is always read/write ac-

cessible. TINTM is cleared by

H_RESET or S_RESET and is

not affected by STOP.

8 IDONM Initialization Done Mask. If

IDONM is set, the IDON bit will be

masked and unable to set the

INTR bit.

This bit is always read/write ac-

cessible. IDONM is cleared by

H_RESET or S_RESET and is

not affected by STOP.

7 RES Reserved location. Read and

written as zero.

6 DXSUFLO Disable Transmit Stop on Under-

flow error.

When DXSUFLO (CSR3, bit 6) is

set to 0, the transmitter is turned

off when an UFLO error occurs

(CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C978 controller gracefully

recovers from an UFLO error. It

scans the transmit descriptor ring

until it finds the start of a new

frame an d sta rts a n ew trans mis-

sion.

This bit is always read/write ac-

cessible. DXSUFLO is cleared by

H_RESET or S_RESET and is

not affected by STOP.

5 LAPPEN Look Ahead Packet Processing

Enable. When set to a 1, the

LAPPEN bit will cause the

Am79C978 controller to generate

an interrupt following the descrip-

tor write operation to the first buff-

er of a receive frame. This

interrupt will be generated in ad-

dition to t he interrupt tha t is gen-

erated following the descriptor

write operation to the last buffer

of a receive packet. The interrupt

will be signaled through the RINT

bit of CSR0.

Setting LAPPEN to a 1 also en-

ables the Am79C978 controller to

read the STP bit of receive de-

scriptors. The Am79C978 con-

troller will use the STP

informat ion to dete rmin e where it

should begin writing a receive

packet’s data. Note that while in

this mode, the Am79C978 con-

troller can write intermediate

packet data to buff ers whose de-

scrip tors do not con tain STP b its

set to 1. Following the write to the

last descriptor used by a packet,

the Am79C978 controller will

scan through the next descriptor

entries t o locate the ne xt STP bit

that is set to a 1. The Am79C978

controller will begin writing the

next packets data to the buffer

pointed to by that descriptor.

Note that because several de-

scrip tors may be alloc at ed by the

host for each packet, and not all

messages may need all of the de-

scriptors that are allocated be-

tween descriptors that contain

Am79C978 117

STP = 1, then some descriptors/

buffers may be skipped in the

ring. While performing the search

for the n ext STP bit that is set t o

1, the Am79C978 controller will

advance through the receive de-

scriptor ring regardless of the

state of ownership bits. If any of

the entries that are examined

during this search indicate

Am79C978 controller ownership

of the descriptor but also indicate

STP = 0, then the Am79C978

controller will reset the OWN bit

to 0 in these entries. If a scanned

entry indicates host ownership

with STP = 0, then the

Am79C978 controller will not al-

ter the entry, but will advance to

the next entry.

When the STP bit is found to be

true, but the descriptor that con-

tains this setting i s not own ed by

the Am79C978 controller, then

the Am79C978 controller will stop

advancing through the ring en-

tries and begin periodic polling of

this entry. When the STP bit is

found to be true, and the descrip-

tor that contains this setting is

owned by the Am79C978 control-

ler, then the controller will stop

advancing through the ring en-

tries, store the descriptor infor-

mation that it has just read, and

wait for the next receive to arrive.

This behavior allows the host

software to pre-assign buffer

space in such a manner that the

header portion of a receive pack-

et will a lways b e wri tten to a par-

ticular memory area, and the data

portion of a receive packet will al-

ways be written to a separate

memory area. The interrupt is

generated when the header bytes

have been written to the header

memory area.

This bit is always read/write ac-

cessib le. The LA PPEN bit wi ll b e

reset to 0 by H_RESET or

S_RESET an d will be una ffected

by STOP.

See Appendix B for more infor-

mation on the Lo ok Ah ead P ack-

et Processing concept.

4 DXMT2PD Disable Transmit Two Part Defer-

ral (see Medium Allocation sec-

tion in the Media Access

Management section for more

details). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

This bit is always read/write ac-

cessible. DXMT2PD is cleared by

H_RESET or S_RESET and is

not affected by STOP.

3 EMBA Enable Modified Back-off Algo-

rithm (see the Contention Reso-

lution section in Media Access

Management section for more

details). If EMBA is set, a modi-

fied back-off algorithm is imple-

mented.

This bit is always read/write ac-

cessible. EMBA is cleared by

H_RESET or S_RESET and is

not affected by STOP.

2 BSWP Byte Swap. This bit is used to

choose between big and little En-

dian modes of operation. When

BSWP is set to a 1, big Endian

mode is sele cted. Wh en BSWP i s

set to 0, lit tle En dian m ode is se-

lected.

When big End ian mode is se lec t-

ed, the Am79C978 controller will

swap the order of bytes on the AD

bus during a data phase on ac-

cesses to the FIFOs only. Specif-

ically, AD[31:24] becomes Byte

0, AD[23:16] becomes Byte 1,

AD[15:8] becomes Byte 2, and

AD[7:0] becomes Byte 3 when

big Endian mode is selected.

When little Endian mode is se-

lected, the order of bytes on the

AD bus during a data phase is:

AD[31:24] i s B yte 3, A D[23: 16] is

Byte 2, AD[15:8] is Byte 1, and

AD[7:0] is Byte 0.

Byte swap only affects data

transfers that involve the FIFOs.

Initialization block transfers are

not affected by the setting of the

118 Am79C978

BSWP bit. Descriptor transfers

are not affected by th e setting of

the BSWP bit. RDP, RAP, BDP

and PCI configuration space ac-

cesses are not affected by the

setting o f the B SWP bi t. Add ress

PROM transfers and Expansion

ROM accesses are not affected

by the setting of the BSWP bit.

Note that the byte ordering of the

PCI bus is de fined to be little En-

dian. BSWP should not be set to

1 when the Am79 C978 con troll er

is used in a PCI bus application.

This bit is always read/write ac-

cessible. BSWP is cleared by

H_RESET or S_RESET and is

not affected by STOP.

1-0 RES Reserved locations. The default

values of these bits are zeros.

Writing a 1 to this bit has no effect

on device function. If a 1 is written

to these bits, then a 1 will be read

back. Existing drivers may write a

1 to these bits for compatibility,

but new drivers should write a 0

to these bits and should tr eat the

read value as undefined.

CSR4: Test and Features Control

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear t he interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 RES Reserved location. It is OK for

legacy software to write a 1 to this

location. This bit must be set

back to 0 before setting INIT or

STRT bits.

This bit is always read/write ac-

cessible. This bit is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

14 DMAPLUS Writing and reading from this bit

has no effect. DMAPLUS is al-

ways set to 1.

13 RES Reserved Location. Written as

zero and read as undefined.

12 TXDPO LL Disabl e Trans mit Poll ing. If TXD-

POLL is set, the Buffer Manage-

ment Unit will disable transmit

polling. Likewise, if TXDPOLL is

cleared, automatic transmit poll-

ing is enabled. If TXDPOLL is set,

TDMD bit in CSR0 must be set in

order to initiate a manual poll of a

transmit descriptor. Transmit de-

scriptor polling will not take place

if TXON is reset. Transmit polling

will take place following Receive

activities.

This bit is always read/write ac-

cessible. TXDPOLL is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

11 APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame, including pad, and ap-

pended after the pad field.

APAD_XMT will override the pro-

gramming of the DXMTFCS bit

(CSR15, bit 3) and of the

ADD_FCS bit (TMD1, bit 29).

This bit is always read/write ac-

cessible. APAD_XMT is cleared

by H_RESET or S_RESET and is

unaffected by the STOP bit.

10 ASTRP_RCV Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

This bit is always read/write ac-

cessible. ASTRP_RCV is cleared

by H_RESET or S_RESET and is

unaffected by the STOP bit.

9 MFCO Missed Frame Counter Overflow

is set by the Am79C978 control-

ler when the Missed Frame

Counter (CSR112 and CSR113)

has wrapped around.

Am79C978 119

When MFCO is set, INTA is as-

serted i f IENA is 1 and the ma sk

bit MFCOM is 0.

This bit is always read/write ac-

cessible. MFCO is cleared by the

host by writing a 1. Writing a 0

has no effect. MFCO is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

8 MFCOM Missed Frame Counter Overflow

Mask. If MFCOM is set, the

MFCO bit will be masked and un-

able to set the INTR bit.

This bit is always read/write ac-

cessible. MFCOM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

7 UINTCMD User Interrupt Command.

UINTCMD can be used by the

host to generate an interrupt un-

related to any network activity.

When UINTCMD is set, INTA is

asserted if IENA is set to 1. Write

a 1 to UINT to clear UINTCMD

and stop interrupts.

This bit is always read/write ac-

cessible. UINTCMD is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

6 UINT User Interrupt. UINT is set by the

Am79C978 controller after the

host has issued a user interrupt

command by setting UINTCMD

(CSR4, bit 7) to 1.

This bit is always read/write ac-

cessible. UINT is cleared by the

host by writing a 1. Writing a 0

has no effec t. UINT is clea red by

H_RESET or S_RESET or by

setting the STOP bit.

5 RCVCCO Receive Collision Counter Over-

flow is set by the Am79C978 con-

troller when the Receive Collision

Counter (CSR114 and CSR115)

has wrapped around.

When RCVCCO is set, INTA is

asserted if IENA is 1 and the

mask bit RCVCCOM is 0.

This bit is always read/write ac-

cessib le. RCVCCO is cleared by

the host by writing a 1. Writing a

0 has no effect. RCVCCO is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

4 RCVCCOM Receive Collision Counter Over-

flow Mask. If RCVCCOM is set,

the RCVCCO bit will be masked

and unable to set the INTR bit.

This bit is always read/write ac-

cessible. RCVCCOM is set to 1

by H_RESET or S_RESET and is

not affected by the STOP bit.

3 TXSTRT Tra nsmit Star t sta tus i s set by t he

Am79C978 controller whenever it

begins transmission of a frame.

When TXSTRT is set, INTA is as-

serted if IENA is 1 and the mask

bit TXSTRTM is 0.

This bit is always read/write ac-

cessible. TXSTRT is cleared by

the host by writing a 1. Writing a

0 has no effect. TXSTRT is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

2 TXSTRTM Transmit Start Mask. If TX-

STRTM is set, the TXSTRT bit

will be mas ked and una ble to set

the INTR bit.

This bit is always read/write ac-

cessible. TXSTRTM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

1-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

120 Am79C978

15 TOKINTD Transmit OK Interrupt Disable. If

TOKINTD is set to 1, the TINT bit

in CSR0 will not be set when a

transmission was successful.

Only a transmit error will set the

TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5 , bit 14) is set to

1. A transmit descriptor with

LTINT set to 1 will always cause

TINT to be set to 1, independent

of the success of the transmis-

sion.

This bit is always read/write ac-

cessib le. TOKINTD i s cleared by

H_RESET or S_RESET and is

unaffected by STOP.

14 LTINTEN Last Transmit Interrupt Enable.

When set to 1, the LTINTEN bit

will cause the Am79C978 control-

ler to read bit 28 of TMD1 as

LTINT. The setting LTINT will de-

termine if TINT will be set at the

end of the transmission.

This bit is always read/write ac-

cessible. LTINTEN is cleared by

H_RESET or S_RESET and is

unaffected by STOP.

13-12 RES Reserved locations. Written as

zeros and read as undefined.

11 SINT System Interrupt is set by the

Am79C978 co ntrol ler when it de-

tects a sys tem err or dur i ng a bus

master transfer on the PCI bus.

System e rrors are d ata parity er-

ror, master abort, or a target

abort. Th e settin g of SINT due to

data parity error is not dependent

on the setting of PERREN (PCI

Command register, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to SINT is not depen-

dent on the state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system er ror.

This bit is always read/write ac-

cessible. SINT is cleared by the

host by writing a 1. Writing a 0

has no effect. The state of SINT is

not affected by clearing any of the

PCI Status register bits that get

set when a data parity error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTABORT, bit 12) occurs.

SINT is cleared by H_RESET or

S_RESET a nd is not affected by

setting the STOP bit.

10 SINTE System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

This bit is always read/write ac-

cessible. SINTE is set to 0 by

H_RESET or S_RESET and is

not affecte d by set ting the S TOP

bit.

9-8 RES Reserved locations. Written as

zeros and read as undefined.

7 EXDINT Excessive Deferral Interrupt is

set by the Am79C978 controller

when the transmitter has experi-

enced Excessive Deferral on a

transmit frame, where Excessive

Deferral is defined in the ISO

8802-3 (IEEE/ANSI 802.3) stan-

dard.

When EXDINT is set, INTA is as-

serted i f the enab le bit E XDINTE

is 1.

This bit is always read/write ac-

cessible. EXDINT is cleared by

the host by writing a 1. Writing a

0 has no effect. EXDINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit .

6 EXDINTE Excessive Deferral Interrupt En-

able. If EXDINTE is set, the

EXDINT bit will be able to set the

INTR bit.

This bit is always read/write ac-

cessib le. E XDINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

5 MPPLBA Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C978 121

Am79C978 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If

MPPLBA is set to 1, the destina-

tion ad dress o f the Ma gic P acke t

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of MPPLBA only affects the

address detection of the Magic

Packet fram e. The Magic P acket

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless of what kind of

destination address it has. This

bit is OR’ed with the EMPPLBA

bit (CSR116, bit 6) .

This bit is always read/write ac-

cessible. MPPLBA is set to 0 by

H_RESET or S_RESET and is

not affected by setti ng the STOP

bit.

4 MPINT Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C978 controller when the

device is in Magic Packet mode

and the Am79C9 78 controlle r re-

ceives a Magic Packet frame.

When MPINT i s set to 1, INTA is

asserted if IENA (CSR0, bit 6)

and the enable bit MPINTE are

set to 1.

This bit is always read/write ac-

cessible. MPINT is cleared by the

host by writing a 1. Writing a 0

has no affect. MPINT is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

3 MPINTE M agic Pack et Interru pt Enable. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

This bit is always read/write ac-

cessible. MPINT is cleared to 0

by H_RESET or S_RESET and is

not affected by setting the STOP

bit.

2 MPEN Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C978 controller will enter

the Magic Packet mode when

both MPEN and MPMODE are

set to 1.

This bit is always read/write ac-

cessible. MPEN is cleared to 0 by

H_RESET or S_RESET and is

not affecte d by set ting the S TOP

bit.

1 MPMODE The Am79C978 controller will en-

ter the M agi c P ack et m ode whe n

MPMODE is set to 1 and either

PG is asserted or MPEN is set to

This bit is always read/write ac-

cessible. MPMODE is cleared to

0 by H_RESET or S_RESET and

is not affected by setting the

STOP bit

0 SPND Suspend. Setting SPND to 1 will

cause the Am79C978 controller

to start requesting entrance into

suspend mode. The host must

poll SPND until it reads back 1 to

determine that the Am79C978

controller has entered the sus-

pend mode. Setting SPND to 0

will get the Am79C978 controller

out of sus pe nd m ode . S PND ca n

only be set to 1 if STOP (CSR0,

bit 2) is set to 0. H_RESET,

S_RESET, or setting the STOP

bit will get the Am79C978 control-

ler out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit des cription of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

In susp end mode, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C978

controller is not reset while in

suspend mode (by H_RESET,

S_RESET, or by setting the

STOP bit), no re-initialization of

the device is required after the

device comes out of suspend

mode. The Am79C978 controller

will continue at the transmit and

receive descriptor ring locations

122 Am79C978

from where it had left, when it en-

tered the suspend mode.

This bit is always read/write ac-

cessible. SPND is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 TLEN Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during the Am79C978 controller

initialization. This field is written

during the Am79C978 initializa-

tion routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

TLEN is only de fined after i nitial-

ization. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

11-8 RLEN Contains a copy of the receive

encoded ring length (RLEN) read

from the initialization block during

Am79C978 controller initializa-

tion. This field is written during

the Am79C978 initialization rou-

tine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

RLEN is only define d a fter ini tial-

ization. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

7-0 RES Reserved locati ons. Read as 0s.

Write operations are ignored.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear t he interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 FASTSPNDE Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C978 controller performs a

fast suspend whenever the

SPND bit is set.

When a fa st suspend is r equest-

ed, the Am79C978 controller per-

forms a quick entry into the

suspend mode. At the time the

SPND bit is set, the Am79C978

controller will complete the DMA

process of any transmit and/or re-

ceive packet that had already be-

gun DMA activity. In addition, any

transmit packet that had started

transmission will be fully transmit-

ted, and any receive packet that

had begun reception will be fully

receiv ed. Howev er, no addi tional

packets wil l be transm itted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence, th e Am79C97 8 controll er

may enter the suspend mode

with transmit and/or receive

packets still in the FIFOs or the

SRAM.

When FASTSPNDE is 0 an d the

SPND bit is set, the Am79C978

control ler may tak e lo nger bef ore

entering the suspend mode. At

the time the SPND bit is set, the

Am79C978 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun,

and the Am79C978 controller will

completely receive a receive

packet if it had already begun.

Additionally, all transmit packets

stored in the transmit FI FOs and

the transmit buffer area in the

SRAM (if one is enabled) will be

transmitted and all receive pack-

ets stored in the receive FIFOs,

and the receive buffer area in the

SRAM (if one is enabled) will be

transferred into system memory.

Since the FIFO and SRAM con-

tents are flushed, it may take

much longer before the

Am79C978 controller enters the

Am79C978 123

suspend mode. The amount of

time that it takes depends on

many factors including the size of

the SRAM, bus latency, a nd net-

work traffic level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach is

used to enter suspend mode.

This bit is always read/write ac-

cessible. FASTSPNDE is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

14 RES Reserved location.

13 RDMD Receive Demand, when set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is requir ed to be set if th e

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C978

controller’s response to a receive

Descriptor Ring Entry.

This bit is always read/write ac-

cessible. RDMD is set by writing

a 1. Writing a 0 has no effect.

RDMD will be cleared by the Buff-

er Management Unit when it

fetches a receive Descriptor.

RDMD is cleared by H_RESET.

RDMD is unaffected by

S_RESET or by setting the STOP

bit.

12 RXDPOLL Receive Disable Polling. If RXD-

POLL is set, the Buffer Manage-

ment Unit will disable receive

polling. Likewise, if RXDPOLL is

cleared, automatic receive poll-

ing is enabled. If RXDPOLL is

set, RDMD bit in CSR7 must be

set in order to initiate a manual

poll of a receive descriptor. Re-

ceive Descriptor Polling will not

take place if RXON is reset.

This bit is always read/write ac-

cessible. RXDPOLL is cleared by

H_RESET. RXDPOLL is unaf-

fected by S_R ES ET or by se ttin g

the STOP bit .

11 STINT Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C978 controller when

the Software Timer counts down

to 0. The So ftware Timer will im-

mediately load the STVAL (BCR

31, bits 5-0) into the Software

Timer and begin co unti ng down .

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

This bit is always read/write ac-

cessible. STINT is cleared by the

host by writing a 1. Writing a 0

has no effect. STINT is cleared

by H_RES ET and is not affe cted

by S_RESET or setting the STOP

bit.

10 STINTE S oftware Timer Interru pt Ena ble.

If STINTE is set, the STINT bit

will be able to set the INTR bit.

This bit is always read/write ac-

cessible. STINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP bit

9 MREINT PHY Management Read Error In-

terrupt. The PHY Read Error in-

terrupt is set by the Am79C978

control ler to indi ca te t hat the cur -

rently read regi ste r from the PHY

is inva lid, the c ontents of B CR34

are incorrect, and the operation

should be performed again. The

indication of an incorrect read

comes from the internal PHY.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

This bit is always read/write ac-

cessible. MREINT is cleared by

the host by writing a 1. Writing a

0 has no effect. MREINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit .

124 Am79C978

8 MREINTE PHY Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

This bit is always read/write ac-

cessible. MR E INT E is s et to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP bit

7 MAPINT PHY Management Auto-Poll In-

terrupt. The PHY Auto-Poll inter-

rupt is set by the Am79C978

control ler to i ndi ca te th at t he c ur -

rently read status does not match

the stored previous status indi-

cating a change in state for the in-

ternal PHY. A change in the Auto-

Poll Access Method (BCR32, Bit

11) will reset the shadow register

and w il l n ot ca us e a n int e rr upt on

the first access from the Auto-Poll

section. Subsequent accesses

will generate an interrupt if the

shadow register and the read

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

This bit is always read/write ac-

cessible. MAPINT is cleared by

the host by writing a 1. Writing a

0 has no effect. MAPINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

6 MAPINTE PHY Auto-Poll Interrupt Enable.

If MAPINTE is set, the MAPINT

bit will be able to set the INTR bit.

This bit is always read/write ac-

cessib le. MAPINT E is s et to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

5 MCCINT PHY Management Command

Complete Interrupt. The PHY

Management Command Com-

plete Interrupt is set by the

Am79C978 controller when a

read or write operation to the in-

ternal PHY Data Port (BCR34) is

complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

This bit is always read/write ac-

cessible. MCCINT is cleared by

the host by writing a 1. Writing a

0 has no effect. MCCINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit .

4 MCCINTE PHY Management Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the MC-

CINT bit will be able to set the

INTR bit when the host reads or

writes to the internal PHY Data

Port (BCR34) only. Internal PHY

Managemen t Com mands wil l not

generate an interrupt. For in-

stance Auto-Poll state machine

generated management frames

will not generate an interrupt

upon completion unless there is a

compare error which gets report-

ed through the MAPINT (CSR7,

bit 6) interrupt or the MCCIINTE

is set to 1.

This bit is always read/write ac-

cessible. MCCINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 MCCIINT PHY Management Command

Complete Internal Interrupt. The

PHY Management Command

Complete Interrupt is set by the

Am79C978 controller when a

read or write op eration on the in-

ternal PHY management port is

complete from an intern al opera-

tion. Examples of internal opera-

tions are Auto-Poll or PHY

Management Port generated

management frames. These are

normally hidden to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

This bit is always read/write ac-

cessible. MCCIINT is cleared by

the host by writing a 1. Writing a

0 has no effect. MCCIINT is

cleared by H_RESET and is not

Am79C978 125

affected by S_RESET or setting

the STOP bit.

2 MCCIINTE PHY Management Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state machines generate man-

agement frames. For instance,

when MCCIINTE is set to 1 and

the Auto-P oll state machi ne gen-

erates a man agement frame, th e

MCCIINT will set the INTR bit

upon completion of the manage-

ment frame regardless of the

comparison outcome.

This bit is always read/write ac-

cessible. MCCIINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 MIIPDTINT PHY Detect Transition Interrupt.

The PHY Dete ct Transit ion Inter-

rupt is set by the Am79C978 con-

troller whenever the MIIPD bit

(BCR32, bit 14) transitions from 0

to 1 or vice versa.

This bit is always read/write ac-

cessible. MIIPDTINT is cleared

by the host by writing a 1. Writing

a 0 has no effect. MIIPDTINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

0 MIIPDTINTE PHY Detect Transition Interrupt

Enable. If MIIPDTINTE is set to 1,

the MIIPDT INT bit will be abl e to

set the INTR bit.

This bit is always read/write ac-

cessible. MIIPDTINTE is set to 0

by H_RESE T and is not affec ted

by S_RESET or setting the STOP

bit.

CSR8: Logical Address Filter 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[15:0] Logical Address Filter, LADRF-

[15:0]. The content of this register

is undefined until loaded from the

initialization block after the INIT

bit in C SR0 has bee n set or a d i-

rect register write has been per-

formed on this register.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR9: Logical Address Filter 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[31:16] Logical Address Filter, LADRF-

[31:16]. The content of this regis-

ter is unde fin ed until l oaded f rom

the initialization block after the

INIT bit in CSR0 has been s et or

a direct register write has been

performed on this register.

These bits are These bits are

read/write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR10: Logical Address Filter 2

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[47:32] Logical Address Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has b een perfo rm ed o n th is

These b it are read/write accessi-

ble only when either the STOP or

the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

126 Am79C978

CSR11: Logical Address Filter 3

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[63:48] Logical Address Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has be en per for m ed o n th is

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR12: Physical Address Register 0

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[15:0] Physical Address Register,

PADR[15:0]. The c onte nts o f th is

EEPROM after H_RESET or by

an EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR13: Physical Address Register 1

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[31:16] Physical Address Register,

PADR[31:16]. The contents of

this register are loaded from the

EEPROM after H_RESET or by

an EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR14: Physical Address Register 2

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[47:32] Physical Address Register,

PADR[47:32]. The contents of

this register are loaded from the

EEPROM after H_RESET or by

an EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

Am79C978 127

CSR15: Mode

This register’s fi elds ar e load ed durin g the A m79C97 8

controller initialization routine with the corresponding

Initialization Block values, or when a direct register write

has been performed on this register.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PROM Promiscuous Mode. When

PROM = 1, all incoming receive

frames are accepted.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

14 DRCVBC Disable Receive Broadcast.

When set, disables the

Am79C978 controller from re-

ceiving broadcast messages.

Used for protocols that do not

support broadcast addressing,

except as a func tion of mu ltic ast.

DRCVBC is cleared by activatio n

of H_RESET or S_RESET

(broadcast messages will be re-

ceived) and is unaffected by

STOP.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

13 DRCVPA Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C978 controller

will be disabled. Frames ad-

dressed to the nodes individual

physical address will not be rec-

ognized.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

12-9 RES Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0] Port Select bits allow for software

controlled selection of the net-

wor k medium. The only legal val-

ues for this field is 11.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set. Cleared by

H_RESET or S_RESET and is

unaffected by STOP.

6 INTL Internal Loopback. See the de-

scr ipti on of LO OP (CSR1 5, bit 2).

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

5 DRTY Disable Retry. When DRTY is set

to 1, the Am79C978 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwr itten, because auto-

matic retransmission will not be

necessar y. When DRTY is set to

0, the Am79C978 controller will

attempt 16 transmissions before

signaling a retry error.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

4 FCOLL Force Collision. This bit allows

the collision logic to be tested.

The Am79C978 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a colli-

sion will be forced during loop-

back transmission attempts,

which will result in a Retry Error.

If FCOLL = 0, the Fo rce Co ll is io n

logic will be disabled. FCOLL is

defined after the initialization

block is read.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

3 DXMTFCS Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. W hen DX MTF CS is s et t o

1, no FCS is generated or sent

with the transmitted frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in TMD1.

When the APAD_XMT bit (CSR4,

bit11) is set to 1, the setting of

DXMTFCS has no effect.

128 Am79C978

If DXMTFCS is set and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in TMD1.

This bit was called DTCR in the

LANCE (Am7990) device.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

2 LOOP Loopback Enable allows the

Am79C978 controller to operate

in full-duplex mode for test pur-

poses. The setting of the full-

duplex c ontrol b its i n BCR9 h ave

no effect when the device oper-

ates in loopback mode. When

LOOP = 1, loopback is enabled.

In combination with INTL and

MIIILP, various loopback modes

are defined as follows in Table

30.

Refer to Loopback Operation

section for more details.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set. LOOP is cleared

by H_RESET or S_RESET and

is unaffected by STOP.

1 DTX Disable Transmit results in

Am79C978 controller not access-

ing the Transmit Descriptor Ring

and, therefore, no transmissions

are attempted. DTX = 0, will set

TXON bit (CSR0 bit 4) if STRT

(CSR0 bit 1) is asserted.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

0 DRX Disable Receiver results in the

Am79C978 controller not access-

ing the Receive Descriptor Ring

and, therefore, all receive frame

data are ignored. DRX = 0 will set

RXON bit (CSR0 bit 5) if STRT

(CSR0 bit 1) is asserted.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

CSR16: Initialization Block Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADRL This register is an alias of CSR1.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set.

CSR17: Initialization Block Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADRH This register is an alias of CSR2.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set.

CSR18: Current Receive Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRBAL C ontains the l ower 16 bits of th e

current receive b uffer address at

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR19: Current Receive Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

Table 30. Loopback Configuration

LOOP INTL MIIILP Function

0 0 0 Normal Operation

0 0 1 Internal Loop

1 0 0 External Loop

Am79C978 129

15-0 CRBAU Contains the upper 16 bits of th e

current receive buffer address at

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR20: Current Transmit Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXBA L Contains the lower 16 bi ts of the

current transmit buffer address

from which the Am79C978 con-

troller is transmitting.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR21: Current Transmit Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXBA U Contains the uppe r 16 bits of th e

current transmit buffer address

from which the Am79C978 con-

troller is transmitting.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR22: Next Receive Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRBAL Contains the lower 16 bits of the

next receive buffer address to

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR23: Next Receive Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRBAU Conta ins the uppe r 16 bits of th e

next receive buffer address to

which the Am79C978 controller

will store incoming frame data.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR24: Base Address of Receive Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADRL C ontains the lower 16 bits of the

base address of the Receive

Ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR25: Base Address of Receive Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADRU Contains the uppe r 16 bits of th e

base address of the Receive

Ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR26: Next Receive Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

130 Am79C978

15-0 NRDAL Conta ins the lo wer 16 bits of the

next receive descriptor address

pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR27: Next Receive Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRDAU Contains the upper 16 bits of the

next receive descriptor address

pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR28: Current Receive Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRDAL Conta ins the lo wer 16 bits of the

current receive descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR29: Current Receive Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRDAU Contains the upper 16 bits of the

current receive descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR30: Base Address of Transmit Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADX L Conta ins the lower 16 bits of the

base address of the Transmit

Ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR31: Base Address of Transmit Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADX U Contains the uppe r 16 bits of th e

base address of the Transmit

Ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR32: Next Transmit Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXDAL Conta ins the lower 16 bits of the

next transmit descriptor address

pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR33: Next Transmit Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXDAU Conta ins the upper 16 bits of the

next transmit descriptor address

pointer.

Am79C978 131

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR34: Current Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXD AL Conta ins the lower 16 bits of the

current transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR35: Current Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXD AU Co ntains the upper 16 bits of the

current transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR36: Next Next Receive Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNRDAL C ontains the lower 16 bi ts of the

next next receive descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR37: Next Next Receive Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNRDAU C ontains the uppe r 16 bits of the

next next receive descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR38: Next Next Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNXDAL Contains th e lower 16 bits of the

next next transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR39: Next Next Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNXDAU C ontains the uppe r 16 bits of th e

next next transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR40: Current Receive Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

132 Am79C978

15-12 RES Reserved locations. Read and

written as zeros.

11-0 CRBC Current Receive Byte Count.

This field is a copy of the BCNT

field of RMD1 of the current re-

ceive descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR41: Current Receive Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRST Current Receive Status. This

field is a copy of bits 31-16 of

RMD1 of the current receive de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR42: Current Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 CXBC Current Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the current trans-

mit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR43: Current Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXST Current Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of th e current transm it de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR44: Next Receive Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 NRBC Next Receive Byte Count. This

field is a copy of the BCNT field of

RMD1 of the next receive de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR45: Next Receive Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRST Nex t R ec eiv e Sta tus . Th is fie ld is

a copy of bits 31-16 of RMD1 of

the next receive descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR46: Transmit Poll Time Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

Am79C978 133

15-0 TXPOL L T ra nsm it P ol l T im e C oun ter . This

counter is incremented by the

Am79C978 controller microcode

and is used to trigger the transmit

descriptor ring polling operation

of the Am79C978 controller.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR47: Transmit Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXPOLLINT Transmit Polling Interval. This

Am79C978 controller will wait be-

tween successive polling opera-

tions. The TXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of TXPOLLINT

represents 1 clock period of time.

TXPOLLINT[3:0] are ignored.

(TXPOLLINT[16] is implied to be

a one, so TXPOLLINT[15] is sig-

nificant and does not represent

the sign of the tw o’s complement

TXPO LLIN T va lue .)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz). The TXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR47 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for POLLINT other than the

default, then the correct proce-

dure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR47 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the st an-

dard initialization procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is im perativ e that the user

also writes all zeros to CSR47 as

part of the alternative initialization

sequence.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR48: Receive Poll Time Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RXPOLL Receive Poll Time Counter. This

counter is incremented by the

Am79C978 controller microcode

and is used to t rigger the re ceiv e

descriptor ring polling operation

of the Am79C978 controller.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR49: Receive Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RXPOLLINT Receive Polling Interval. This reg-

ister contains the time that the

Am79C978 controller will wait be-

tween successive polling opera-

tions. The RXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of RXPOLLINT

represents approximately one

clock time period. RXPOL-

LINT[3:0] are ignored. (RXPOL-

134 Am79C978

LINT[16] is implied to be a 1, so

RXPOLLINT[15] is significant

and does not represent the sign

of the two’s compl ement RXPOL -

LINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz). The RXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR49 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for RX POLLINT other tha n

the default, then the correct pro-

cedure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR49 and set STRT in CSR0.

In this way, the default value of

0000h in CSR 47 will be overwrit-

ten with the desired user value.

If the user does not use the stan-

dard initialization procedure

(standard implies use of an initial-

ization block in me mory and set-

ting the INIT bit of CSR0), but

instead chooses to write directly

to each of the registers that are

involved in the INIT operation, it

is imperative that the user also

writes a ll ze r os to C SR4 9 as p ar t

of the alt ernative in itializati on se-

quence.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR58: Software Style

This register is an alias of the location BCR20. Accesses

to and from this register are equi valent to ac cesses to

BCR20.

Bit Name Description

31-11 RES Reserved locations. Written as

zeros and read as und efi ned.

10 APERREN Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer th at was a ccess ed when a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descriptor, SWSTYLE (bits

7-0 of this register) must be set to

2 or 3 to program the Am79C978

controller to use 32-bit software

structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C978 controller is the

target of the transfer.

Read anytime, write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

9 RES Reserved location. Written as

zero and read as undefined.

8 SSIZE32 Software Size 32 bits. When set,

this bit indicates that the

Am79C978 controller utilizes 32-

bit softwa re struct ures for the in i-

tialization block and the transmit

and receive descriptor entries.

When cleared, this bit indicates

that the Am79C978 controller uti-

lizes 16-bit software structures for

the initialization block and the

transmit and receive descriptor

entries. In this mode, the

Am79C978 controller is back-

wards compatible with the

Am799 0 LANCE and Am79C96 0

PCnet-I S A con tr oll ers .

The value of SSIZE32 is deter-

mined by the A m79 C978 con trol-

ler accor ding to the sett ing of th e

Software Style (SWSTYLE, bits

7-0 of this register).

Read accessible always.

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

Am79C978 135

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-b it add re ss

bus durin g maste r acc esses i niti-

ated by the Am79C978 controller.

This action is required because

the 16-bit software structures

specified by the SSIZE32 = 0 set-

ting will yield only 24 bits of ad-

dress for the Am79C978

cont roller bus master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C978 controller and

the host system will supply a full

32 bits for each address pointer

that is n eed ed by th e A m79 C97 8

controller for performing master

accesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress p ins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE3 2 bit has no effe ct on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in thi s register de termines th e

style of register and memory re-

sources that sha ll be used by the

Am79C978 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width of

the descriptors and initialization

block entries.

All Am79C978 controller CSR

bits and BCR bits and all descrip-

tor, buffer , and ini tiali zation blo ck

entries not cited in Table 31 are

unaffected by the So ftware Style

selection and are, therefore, al-

ways full y functional a s specified

in the CSR and BCR sections .

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. The SW-

STYLE register will contain the

value 00h following H_RESET

and will be unaffected by

S_RESET or STOP.

Table 31. Software Styles

SWSTYLE

[7:0] Style

Name SSIZE32 Initialization Block

Entries Descriptor Ring Entries

00h LANCE/PCnet-ISA

controller 016-bit software structures,

non-burst or burst access 16-bit softw are structure s,

non-bur st acc es s only

01h RES 1RES RES

02h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access 32-bit softw are structure s,

non-bur st acc es s only

03h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access 32-bit softw are structure s,

non-burst or burst access

All Other RES Undefined Undefined Undefined

136 Am79C978

CSR60: Previous Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 PXDAL Contains the lower 16 bits of the

previous transmit descriptor ad-

dress pointer. The Am79C978

controller has the capability to

stack multiple transmit frames.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR61: Previous Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 PXDAU Contains the upper 1 6 bits o f the

previous transmit descriptor ad-

dress pointer. The Am79C978

controller has the capability to

stack multiple transmit frames.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR62: Previous Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-12 RES Reserved locations.

11-0 PXBC Previous Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the previous

transmit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR63: Previous Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PXST Previous Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of the previous transmit

descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR64: Next Transmit Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXBAL Contains the lower 16 bits of the

next trans mit buffer address fro m

which the Am79C978 controller

will transmit an outgoing frame.

These bits are read/write accessi-

ble only when either the STOP or

the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR65: Next Transmit Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXBAU Contains the upper 1 6 bits o f the

next trans mit buffer address fro m

which the Am79C978 controller

will transmit an outgoing frame.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

Am79C978 137

CSR66: Next Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 NXBC Next Transmit Byte Count. This

field is a copy of the BCNT field of

TMD1 of the next transmit de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR67: Next Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 NXST Next Transmit Status. This field is

a copy of bits 31-16 of TMD1 of

the next transmit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

7-0 RES Reserved locations. Read and

written as zeros. Accessible only

when either the STOP or the

SPND bit is set.

CSR72: Receive Ring Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 RCVRC Receive Ring Counter location.

Contains a two’s complement bi-

nary nu mber used to number the

current receive descriptor. This

counter interprets the value in

CSR76 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR74: Transmit Ring Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 XMTRC Transmit Ring Counter location.

Contains a two’s complement bi-

nary nu mber used to number the

current transmit descriptor. This

counter interprets the value in

CSR78 as pointing to the first de-

scriptor. A counter value of zero

corr espo nds to th e la st de scri pto r

in the ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR76: Receive Ring Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RCVRL Receive Ring Length. Contains

the two’s complement of the re-

ceive descriptor ring length. This

Am79C978 controller’s initializa-

tion routine based on the value in

the RLEN field of the initialization

block. H owever, this register can

be manually altered. The actual

receive ring length is defined by

the current value in this register.

The ring length can be defined as

any value from 1 to 65535.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

138 Am79C978

CSR78: Transmit Ring Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 XMTRL Transmit Ring Length. Contains

the two’s complement of the

transmit descriptor ring length.

This register is initialized during

the Am79C978 controller’s initial-

ization routine based on the value

in the TLEN field of th e initializa-

tion block. However, this register

can b e manua lly a ltere d. The ac -

tual transmit ring length is defined

by the c urrent v alue in this regis -

ter. The ring length can be de-

fined as any value from 1 to

65535.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR80: DMA T ransfer Counter and FIFO Threshold

Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-14 RES Reserved locations. Written as

zeros and read as und efi ned.

13-12 RCVFW[1:0] Receive FIFO Watermark.

RCVFW controls the point at

which receive DMA is requested

in relation to the number of re-

ceived bytes in the Receive FIFO.

RCVFW specifies the number of

bytes which must be present

(once the frame has been verified

as a non-runt) before receive

DMA is requested. Note, howev-

er, that if the ne twork inter face is

operatin g in half-duplex mode, in

order for receive DMA to be per-

formed for a new frame at least

64 bytes must have been re-

ceived. This effectively avoids

having to react to re ceive fra mes

which are runts or suffer a colli-

sion during the slot time (512 bit

times). If t he Runt P acket A ccept

feature is enabled or if the net-

work interfac e is operati ng in full-

duplex mode, receive DMA will

be requested as soon as either

the RC VFW th re sh old i s reac he d

or a com pl ete va li d rece iv e f ra me

is detected (regardless of length).

When the FDRPAD (BCR9, bit 2)

is set and the Am79C978 control-

ler is in full-duplex mode, in order

for receive DMA to be performed

for a ne w frame at le ast 64 by tes

must have been received. This

effectively disables the runt pack-

et accept feature in full duplex.

When operating in the NO-SRAM

mode (no SRAM enabled), the

Bus Receive FIFO and the MAC

Receive operate like a single

FIFO and the watermark value

selected by RCVFW[1:0] sets the

number of bytes that must be

present in the FIFO before re-

ceive DMA is requested.

When operating with the SRAM,

the Bus Receive FIFO, and the

MAC Receive FIFO operate inde-

pendently on the bus side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by RCVFW[1:0] sets the

number of bytes that must be

presen t in the Bus Receive F IFO

only. See Table 32.

Table 32. Receive Watermark Programming

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set.

RCVFW[1:0] is set to a value of

01b (64 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

11-10 XMTSP[1:0] Transmit Start Point. XMTSP

controls the point at which pream-

ble transmission attempts to com-

mence in relation to the number

of bytes written to the MAC

Transmit FIFO for the current

RCVFW[1:0] Bytes Received

00 16

01 64

10 112

11 Reserved

Am79C978 139

transmit frame. When the entire

frame is in the MAC Transmit

FIFO, transmission will start re-

gardless of the value in XMTSP.

If the networ k inter face is oper at-

ing in half-duplex mode, regard-

less of XMTSP, the FIFO will not

internally overwrite its data until

at least 64 bytes (or the entire

frame if shorter than 64 bytes)

have been transmitted onto the

network. This ensures that for

collisions within the slot time win-

dow, transmit data need not be

rewritten to the Transmit FIFO,

and retries will be handled auton-

omously by the MAC. If the Dis-

able Retry feature is enabled, or if

the network is oper ating in full-du-

plex mode, the Am79C978 con-

troller can overwrite the

beginning of the frame as soon as

the data is transmitted, because

no collision handling is required in

these modes.

Note that when the SRAM is be-

ing used, if the NOUFLO bit

(BCR18, bit 11) is set to 1, there

is the additional restriction that

the complete transmit frame must

be DMA’d into the Am79C978

controller and reside within a

combination of the Bus Transmit

FIFO, the SRAM, and the MAC

Transmit FIFO.

When the SRAM is used and

SRAM_SIZE > 0, there is a re-

striction that the number of bytes

written is a combination of bytes

written into the Bus Transmit

FIFO and the MAC Transmit

FIFO. The Am79C978 controller

sup por ts a m ode th at w ill wai t un -

til a full packet is available before

commencing with the transmis-

sion of preamble. This mode is

useful in a syst em wher e high la-

tencies cannot be avoided. See

Table 33.

These bits are read/write acces-

sible only when either the STOP

or the SP ND bi t is s et. XM TSP is

set to a value of 01b (64 bytes) af-

ter H_RESET or S_RESET and

is unaffected by STOP.

Table 33. Transmit Start Point Programming

9-8 XMTFW[1:0] Transmit FIFO Watermark. XMT-

FW specifies the point at which

transmit DMA is requested,

based upon the number of bytes

that could be written to the Trans-

mit FIFO without FIFO overflow.

Transmit DMA is requested at

any time when the number of

bytes sp ecified by XM TFW coul d

be written to the FIFO without

causing Transmit FIFO overflow

and the internal microcode en-

gine has reached a point where

the Transmit FIFO is checked to

determi ne if DMA ser vicing is r e-

quired.

When operating in the NO-SRAM

mode (no SRAM enabled) and

SRAM_SIZE is set to 0, the Bus

Transmit FIFO and the MAC

Transmit FIFO operate like a sin-

gle FIFO and the watermark val-

ue selec ted by XMTFW[1: 0] sets

the number of FIFO byte loca-

tions that must be available in the

FIFO before receive DMA is re-

quested.

When operating with the SRAM,

the Bus Transmit FIFO and the

MAC Transmit FIFO operate in-

depend ently on the bu s side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by XMTFW[1:0] sets the

number of FIFO byte locations

that m ust be avai lable i n the Bus

Transmit FIFO. See Table 34

XMTSP[1:0] SRAM_SIZE Bytes Writte n

00 0 20

01 0 64

10 0 128

11 0 220 max

00 >0 36

01 >0 64

10 >0 128

11 >0 Full Packet

XX >0 Full Packet when

NOUFLO bit is set

140 Am79C978

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. XMTFW is

set to a value of 00b (16 bytes) af-

ter H_RESET or S_RESET and

is unaffected by STOP.

7-0 DMATC[7:0] DMA Transfer Counter. Writing

and reading to this field has no ef-

fect. Use MAX_LAT and

MIN_GNT in the PCI configura-

tion space.

CSR82: Transmit Descriptor Address Pointer

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXDAPL Contains the lower 16 bits of the

transmit descriptor address cor-

responding to the last buffer of

the previous transmit frame. If the

previous transmit frame did not

use buffer chaining, then TXDA-

PL contains the lower 16 bits of

the previous frame’s transmit de-

scriptor address.

When both the STOP or SPND

bits are cleared, this register is

updated by the Am79C978 con-

troller immediately before a trans-

mit descriptor write.

Read accessible always. Write

accessible through the PXDAL

bits (CSR60) when the STOP or

SPND bit is set. TXDAPL is set to

0 by H_RESET and are una ffec t-

ed by S_RESE T or STOP.

CSR84: DMA Address Register Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 DMABAL This register contains the lower

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAL register is undefined

until the first Am79C978 control-

ler DM A opera tion.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR85: DMA Address Register Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 DMABAU This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAU register is undefined

until the first Am79C978 control-

ler DM A opera tion.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR86: Buffer Byte Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved. Read and written wit h

ones.

11-0 DMABC DMA Byte Count Register. Con-

tains the two's complement of the

current size of the remaining

transmit or receive buffer in

bytes. This register is increment-

ed by the B us Interface Un it. T h e

Table 34. Transmit Watermark Programming

XMTFW[1:0] Bytes Available

00 16

01 64

10 108

11 Reserved

Am79C978 141

DMABC r egi ster i s un defined u n-

til written.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR88: Chip ID Register Lower

Bit Name Description

31-28 VER Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the S PND bi t is se t.

VER is read only. Write opera-

tions are ignored.

27-12 PA RTID Part num ber. The 16-bit c ode for

the Am79C978 controller is

0010 0110 0010 0110 (2626h).

This register is exactly the same

as the Device ID register in the

JTAG description. However, this

part numb er is differ ent from that

stored in the Device ID register in

the PCI config urati on spa ce .

Read accessible only when either

the STOP or the SPND bit is set.

PARTID is read o nly . Wr i te o per -

ations are ignored.

11-1 MANFID Manufacturer ID. The 11-bit man-

ufacturer code for AMD is

00000000001b. This code is per

the JEDEC Publication 106-A.

Note that this code is not the

same as the Vendor ID in the PCI

configur ati on sp ac e.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. MANFID is

read only. Write operations are

ignored.

0 ONE Always a logic 1.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. ONE is read

only. Write operations are ig-

nored.

CSR89: Chip ID Register Upper

Bit Name Description

31-16 RES Reserv ed locations. Rea d as un-

defined.

15-12 VER Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. Write opera-

tions are ignored.

11-0 PARTIDU Upper 12 bits of the Am79C978

controller part numbe r, i.e., 001 0

0110 0010b (262h).

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. PARTIDU is

read only. Write operations are

ignored.

CSR92: Ring Length Conversion

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RCON Ring Length Conversion Regis-

ter. This register performs a ring

length conversion from an encod-

ed value as found in the initializa-

tion block to a two’s complement

value used for internal counting.

By writing bits 15-12 with an en-

coded ring length, a two’s com-

plemented value is read. The

RCON register is undefined until

written.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RES ET, or STOP .

CSR100: Bus Timeout

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MERRTO This register contains the value of

the longest allowable bus latency

(interval between assertion of

REQ and assertion of GNT) that a

142 Am79C978

system may insert into an

Am79C978 controller master

transfer. If this value of bus laten-

cy is exceeded, then a MERR will

be indic ated in CSR 0, bi t 11 , an d

an interrupt may be generated,

depending upon the setting of the

MERRM bit (CSR3, bit 11) and

the IENA bit (CSR0, bit 6).

The va lue in this registe r is inter -

preted as the unsigned number of

bus clock periods divided by two,

(i.e., the value in this register is

given in 0.1 ms increments). For

example, the value 0600h (1536

decimal) will cause a MERR to be

indicated after 153.6 ms of bus

latency. A value of 0 will allow an

infinitely long bus latency, i.e.,

bus timeout error will never oc-

cur.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. This regis-

ter is set to 0600h by H_RESET

or S_RESET and is unaffected by

STOP.

CSR112: Missed Frame Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 MFC Missed Frame Count. Indicates

the number of missed frames.

MFC will roll over to a count of 0

from the value 65535. The MFCO

bit of CSR4 (bit 8) will be set each

time that this occurs.

Read accessible always. MFC is

read only, write operations are ig-

nored. MFC is cleared by

H_RESET, or S_RESET or by

setting the STOP bit.

CSR114: Receive Collision Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 RCC Receive Collision Count. Indi-

cates the total number of colli-

sions encountered by the

receiver since the last reset of the

counter.

RCC will roll over to a count o f 0

from the value 65535. The

RCVCCO bit of CSR4 (bit 5) will

be set each time that this occurs.

These bits are read accessible al-

ways. RCC is read only, write op-

erations are ignored. RCC is

cleared by H_RESET or

S_RESET, or by setting the

STOP bit.

CSR116: OnNow Power Mode Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

10 PME_EN_OVR PME_EN Overwrite. When this

bit is set and the MPMAT or

LCDET bit is set, the PME pin will

always be as ser ted r ega r dle ss o f

the state of the PME_EN bit.

These bits are read/write accessi-

ble only when either the STOP bit

or the SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

9 LCDET Link Change Detected. This bit is

set when the MII auto-polling log-

ic detec ts a change in link st atus

and the LCMODE bit is set.

LCDET is c leared when power is

initially applied (POR).

This bit is always read/write ac-

cessible.

8 LCMODE Link Change Wake-up Mode.

When this bit is set to 1, the

LCDET bit g ets set when the MII

auto polling logic detects a Link

Change.

Read /Write accessi b le o nly wh en

either t he STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

Am79C978 143

7 PMAT Pattern Matched. This bit is set

when the PMMODE bit is set and

an OnNow pattern match occurs.

PMAT is cleared when power is

initially applied (POR).

This bit is read accessible al-

ways.

6 EMPPLBA Magic Packet Physical Logical

Broadcast Accept. If both EMP-

PLBA and MPPLBA (CSR5, bit 5)

are at their default value of 0, the

Am79C978 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If ei-

ther EMPPLBA or MPPLBA is set

to 1, the destination address of

the Magic Packet frame can be

unicast, multicast, or broadcast.

Note that the setting of EMPPL-

BA and MPPLBA only affects the

address detection of the Magic

Packet fram e. The Magic P acket

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless of what kind of

destination address it has.

This bit is always read/write ac-

cessible. EMPPLBA is set to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

5 MPMAT Magic Packet Match. This bit is

set when the integrated Ethernet

cont ro ll er de t ec t s a M agi c Pa ck et

while it is in Magic Packet mode.

MPMAT is cleared when power is

initially applied (POR).

This bit is always read/write ac-

cessible.

4 MPPEN Magic Packet Pin Enable. When

this bit is set, the device enters

the Magic Packet mode when the

PG i nput g oes LO W or M PEN bi t

(CSR5, bit 2) gets set to 1. This

bit is OR’ed with MPEN bit

(CSR5, bit 2).

Read /Write accessi b le o nly wh en

either t he STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3-1 RES Reserved locations.

0 RST_POL PHY_RST Pin Polarity. If the

PHY_POL is set to 1, the

PHY_RST pin is active LOW; oth-

erwise PHY_RST is active HIGH.

This bit is read/write accessible

only whe n either the STOP bit or

the SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

CSR122: Advanced Feature Control

Bit Name Description

31-1 RES Reserved locations. Written as

zeros and read as undefined.

0 RCVALGN Rec eive Packet Align. When set,

this bit forces the data field of ISO

8802-3 (IEEE/ANSI 802.3) pack-

ets to align to 0 MOD 4 address

boundaries (i.e., DWord aligned

addresses). It is important to note

that this feature will only function

correctly if all receive buffer

boundaries are DWord aligned

and all receive buffers have 0

MOD 4 lengths. In order to ac-

complish the data alignment, the

Am79C978 controller simply in-

sert s t wo by te s of r an d om d a ta at

the beginning of the receive pack-

et (i.e., before the ISO 8802-3

(IEEE/ANSI 802.3) destination

address field). The MCNT field

reported to the receive descriptor

will not include the extra two

bytes.

This bit is always read/write ac-

cessible. RCVALGN is cleared by

H_RESET or S_RESET and is

not affected by STOP.

CSR124: Test Register 1

This register is used to place the Am79C978 controller

into various test modes. The Runt Packet Accept is the

only user accessible test mode. All other test modes are

for AMD internal use only.

144 Am79C978

Bit Name Description

31-4 RES Reserved locations. Written as

zeros and read as und efi ned.

3 RPA Runt Packet Accept. This bit

forces the Am79C978 controller

to accept runt packets (packets

shorter than 64 bytes).

This bit is read accessible al-

ways; write accessible only when

STOP is set to 1. RPA is cleared

by H_RESET or S_RESET and is

not affected by STOP.

2-0 RES Reserved locations. Written as

zeros and read as und efi ned.

CSR125: MAC Enhanced Configuration Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-8 IPG Inter Packet Gap. Changing IPG

allows the user to program the

Am79C978 controller for aggres-

siveness on a network. By chang-

ing the default value of 96 bit

times (60h) the user can adjust

the fairness or aggressiveness of

the Am79C978 integrated MAC

on the network. By programming

a lower num ber of bit times oth er

then the ISO/IEC 8802-3 stan-

dard requires, the Am79C978

controller will become more ag-

gressive on the network. This ag-

gressive nature will give rise to

the Am79C978 controller possi-

bly “capturing the network” at

times by forcing other less ag-

gressive nodes to defer. By pro-

gramming a larger number of bit

times, the Am79C978 home net-

working MAC will become less

aggressive on the network and

may defer more often than nor-

mal. The performance of the

Am79C978 controller may de-

crease as the IPG value is in-

creased from the default value.

Note: Programming of the IPG

should be done in nibble intervals

instea d of absolute bit tim es. The

decimal and hex values do not

match due to delays in the part

used to make up the final IPG.

Changes should be added or sub-

tracted from the provided hex val-

ue on a one-for-one basis.

CAUTION: Use this parameter

with care. By lowering the IPG

below the ISO/ IEC 88 02- 3 stan -

dard 96 bit times, the

Am79C978 controller can inter-

rupt normal network behavior.

These bits are read accessible al-

ways. Write accessible when the

STOP bit is set to 1. IPG is set to

60h (96 Bit times) by H_RESET

or S_RESET and is not affected

by STOP.

7-0 IFS1 InterFrameSpacingPart1. Chang-

ing IFS1 allows the user to pro-

gram the value of the InterFrame-

SpacePart1 timing. The

Am79C978 controller sets the de-

fault value at 60 bit times (3ch).

See the subsection on Medium

Allocation in the section Media

Access Management for more

details. The equation for setting

IFS1 when IPG ≥ 96 bit times is:

IFS1 = IPG - 36 bit times

Note: Programming of the IPG

should be done in nibble intervals

instead of absolute bit times due

to the MII. The decimal and hex

values do not match due to de-

lays in the part used to make up

the final IPG.

Changes should be added or

subtracted from the provided hex

value on a one-for-one basis.

Due to changes in synchroniza-

tion dela ys internally through dif-

ferent network ports, the IFS1

can b e off b y as mu ch as +12 bit

times.

These bits are read accessible al-

ways. Write accessible only when

the SPND bit or the STOP bit is

set to 1. IFS1 is set to 3ch (60 bit

times) by H_RESET or

S_RESET a nd is not affected by

STOP.

Am79C978 145

Bus Configuration Registers (BCRs)

The BCRs are used to program the configuration of the

bus interface and other special features of the

Am79C978 controller that are not related to the IEEE

802.3 MAC f unc ti ons . The BCRs a re acce ss ed by firs t

setting the appropriate RAP value and then by perform-

ing a slave access to the BDP. See Table 35.

All BCR re gist ers are 16 b its in wid th in W or d I /O m ode

(DWIO = 0, BCR18, bit 7) and 32 bits in width in DWord

I/O mode (DWIO = 1). The upper 16 bits of all BCR reg-

isters is undefined when in DWord I/O mode. These

bits should be written as zeros and should be treated

as undefined when read. The default value given for

any BCR is the value in the register after H_RESET.

Some of these values may be changed shortly after

H_RESET when the contents of the external EEPROM

is automa tical ly read in. None of the B CR regist er va l-

ues are affected by the assertion of the STOP bit or

S_RESET.

Note that several registers have no default value.

BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21

are reserved and have undefined values. BCR2 and

BCR34 are not observable without first being pro-

grammed through the EEPROM read operation or a

user register write operation.

BCR0, BCR1, B CR16, BCR17, and BCR21 a re regis-

ters that are used by other devices in the PCnet family.

Writing to these r egist ers have no effect on the op era-

tion of the Am79C978 controller.

Writes to those registers marked as “Reserved” will

have no effect. Reads from these locations will produce

undefined values.

BCR0: Master Mode Read Active

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 MSRDA Reserved locations. After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this registe r has no effec t on any

Am79C978 controller function. It

is only included for software com-

patibility with other PCnet family

devices.

Read always. MSRDA is read

only. Write operations have no ef-

fect.

BCR1: Master Mode Write Active

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MSWRA Reserved locations. After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this regist er has no effect on any

Am79C978 controller function. It

is only included for software com-

patibility with other PCnet family

devices.

Read always. MSWRA is read

only. Write operations have no ef-

fect.

BCR2: Miscellaneous Configuration

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-14 RES Reserved locations. Written and

read as zeros.

13 PHYSELEN This bit enables writes to

BCR18[4:3] for software selec-

tion of va rious o peration and test

modes. When PHYSELEN is set

to 0 (default), the two bits can

only be written from the EE-

PROM. When PHYSELEN is set

to 1, wr it es t o BC R18 [4: 3] are e n-

abled.

This bit is always read/write ac-

cessible. TSTSHDEN is cleared

to 0 by H_RESET and is unaffect-

ed by S_RESET or by setting the

STOP bit.

12 LEDPE LED Program Enable. When

LEDPE is set to 1, programming

of the LED0 (BCR4), LED1

(BCR5), LED2 (BCR6), LED3

(BCR7), and LE D4 (BCR48) reg-

isters is enabled. When LEDPE is

cleared to 0, programming of

LED0 (BCR4), LED1 (BCR5),

LED2 (BCR6), LED3 (BCR7),

and LED4 (BCR48) registers is

disabled. Writes to those regis-

ters will be ignored.

146 Am79C978

Table 35. BCR Registers

RAP Mnemonic Default Name Programmability

User EEPROM

0MSRDA 0005h Reserved No No

1MSWRA 0005h Reserved No No

2MC 0002h Miscellaneous Configuration Yes Yes

3Reserved N/A Reserved No No

4LED0 00C0h LED0 Status Yes Yes

5LED1 0084h LED1 Status Yes Yes

6LED2 0088h LED2 Status Yes Yes

7LED3 0090h LED3 Status Yes Yes

8Reserved N/A Reserved No No

9FDC 0000h Full-Duplex Control Yes Yes

10-15 Reserved N/A Reserved No No

16 IOBASEL N/A Reserved No No

17 IOBASEU N/A Reserved No No

18 BSBC 9001h Burst and Bus Control Yes Yes

19 EECAS 0002h EEPROM Control and Status Yes No

20 SWS 0000h Software Style Yes No

21 INTCON N/A Reserved No No

22 PCILAT FF06h PCI Latency Yes Yes

23 PCISID 0000h PCI Subsystem ID No Yes

24 PCISVID 0000h PCI Subsystem Vendor ID No Yes

25 SRAMSIZ 0000h SRAM Size Yes Yes

26 SRAMB 0000h SRAM Boundary Yes Yes

27 SRAMIC 0000h SRAM Interface Control Yes Yes

28 EBADDRL N/A Expansion Bus Address Lower Yes No

29 EBADDRU N/A Expansion Bus Address Upper Yes No

30 EBD N/A Expansion Bus Data Port Yes No

31 STVAL FFFFh Software Timer Value Yes No

32 MIICAS 0000h PHY Control and Status Yes Yes

33 MIIADDR 0000h PHY Address Yes Yes

34 MIIMDR N/A PHY Management D ata Yes No

35 PCIVID 1022h PCI Vendor ID No Yes

36 PMC_A C811h PCI Power Management Capabilities (PMC)

Alias Register No Yes

37 DATA0 0000h PCI DATA Register 0 Alias Re gister No Yes

38 DATA1 0000h PCI DATA Register 1 Alias Re gister No Yes

39 DATA2 0000h PCI DATA Register 2 Alias Re gister No Yes

40 DATA3 0000h PCI DATA Register 3 Alias Re gister No Yes

41 DATA4 0000h PCI DATA Register 4 Alias Re gister No Yes

42 DATA5 0000h PCI DATA Register 5 Alias Re gister No Yes

43 DATA6 0000h PCI DATA Register 6 Alias Re gister No Yes

44 DATA7 0000h PCI DATA Register 7 Alias Re gister No Yes

45 PMR1 N/A Pattern Matching Register 1 Yes No

46 PMR2 N/A Pattern Matching Register 2 Yes No

47 PMR3 N/A Pattern Matching Register 3 Yes No

48 LED4 0082h LED4 Status Yes Yes

49 PHY Select 8101h PHY Select Yes Yes

Am79C978 147

This bit is always read/write ac-

cessible. LEDPE is cleared to 0

by H_RESET and is unaffected

by S_RESET or by setting the

STOP bit.

11-9 RES Reserved locations. Written and

read as zero s.

8 APROMWE Address PROM Write Enable.

The Am79C978 controller con-

tains a shadow RAM on board for

storage of the fir st 16 bytes load-

ed from the serial EEPROM.

Accesses to Address PROM I/O

Resources will be directed toward

this RAM. When APROMWE is

set to 1, then write acc ess to th e

shadow RAM will be enabled.

This bit is always read/write ac-

cessible. APROMWE is cleared

to 0 by H_RESET and is unaffect-

ed by S_RESET or by setting the

STOP bit.

7 INTLEVEL Interrupt Level. This bit allows the

interr upt outp ut si gna ls to be pro-

grammed for level or edge-

sensitive applications.

When I NTLEVEL is cl eared to 0,

the INTA pin is configured for

level-sensitive applications. In

this mode, an int errupt re quest is

signaled by a low level driv en on

the INTA pin by the Am79C978

controller. When the interrupt is

cleared , th e INTA pi n is tri-st ated

by the Am79C978 controller and

allowed to be pulled to a high lev-

el by an external pullup device.

This mode is intended for sys-

tems which allow the interrupt

signal to be shared by multiple

devices.

When INTLEVEL is set to 1, the

INTA pin is configured for edge-

sensitive applications. In this

mode, an in terru pt re que st is sig-

naled by a high level driven on

the INTA pin by the Am79C978

controller. When the interrupt is

cleared, the INTA p in is driv en to

a low level by the Am79C978

control ler. This mod e is intended

for systems that do not allow in-

terrupt channels to be sha red by

multiple devices.

INTLEVEL sho uld no t be se t to 1

when the Am79C978 controller is

used in a PCI bus application.

This bit is always read/write ac-

cessib le . INTLE VE L is cl eared to

0 by H_RESET and is unaffected

by S_RESET or by setting the

STOP bit.

6-3 RES Reserved locations. Written as

zeros and read as undefined.

2-0 RES Reserved locations. Written and

read as zeros.

BCR4: LED0 Status

BCR4 controls the function(s) that the LED0 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabl ed functions. BCR 4 defaults to

Link Status (LNKST) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED0 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED0 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical val ue of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read accessible al-

ways. This bit is read only; writes

have no effect. LED OUT is unaf-

fected by H_RESET, S_RESET,

or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

148 Am79C978

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s fals e ( i.e., the LED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole outpu t and the ou tput value

will be the same polarity as the

LEDOUT sta tus bit.).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

This bit is always read/write ac-

cessible. LEDPOL is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be g overned by the LE DOUT

and LEDPOL values.

This bit is always read/write ac-

cessible. LEDDIS is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a v alue of 1 is passe d

to the LEDOUT bit in this register

when the Am79C978 controller is

operating at 100 Mbps mode.

This bit is always read/write ac-

cessible. 100E is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passe d to the LEDOUT bit in

this register when Magic Packet

frame mode is enabled and a

Magic Packet frame is detected

on the network.

This bit is always read/write ac-

cessible. MPSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT sig nal w hen the A m7 9C97 8

controller is functioning in a Link

Pass sta te and full-dupl ex opera-

tion is enabled. When the

Am79C 978 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

This bit is always read/write ac-

cessible. FDLSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretche r.

This bit is always read/write ac-

cessible. PSE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 LNKSE Link Status Enable. When this bit

is set, a val ue of 1 w ill be pas sed

to the LEDOUT bit in this register

when in Link Pass state.

This bit is always read/write ac-

cessible. LNKSE is set to 1 by

H_RESET an d is not affected by

Am79C978 149

S_RESET or setting the STOP

bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

This bit is always read/write ac-

cessible. RCVME is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. XMTE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 POWER Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 SPEED Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR5: LED1 Status

BCR5 controls the function(s) that the LED1 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabl ed functions. BCR 5 defaults to

Receive Status (RCV) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED1 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED1 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical val ue of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is always read accessi-

ble. This bit is read only; writes

have no effect. LED OUT is unaf-

fected by H_RESET, S_RESET,

or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s f als e (i .e., t he L ED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

150 Am79C978

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole outpu t and the ou tput value

will be the same polarity as the

LEDOU T status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

This bit is always read/write ac-

cessible. LEDPOL is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be g overned by the LE DOUT

and LEDPOL values.

This bit is always read/write ac-

cessible. LEDDIS is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a v alue of 1 is passe d

to the LEDOUT bit in this register

when the Am79C978 controller is

operating at 100 Mbps mode.

This bit is always read/write ac-

cessible. 100E is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

11-10 RES Reserved locations. Written and

read as zero s.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passed to the LE DOUT bit in

this register when Magic Packet

mode is enabled and a Magic

Packet frame is detected on the

network.

This bit is always read/write ac-

cessible. MPSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT sig nal w hen the A m7 9C97 8

controller is functioning in a Link

Pass sta te and full-dupl ex opera-

tion is enabled. When the

Am79C 978 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

This bit is always read/write ac-

cessible. FDLSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretche r.

This bit is always read/write ac-

cessible. PSE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 LNKSE Link Status Enable. When this bit

is set, a val ue of 1 w ill be pas sed

to the LEDOUT bit in this register

in Link Pass state.

This bit is always read/write ac-

cessible. LNKSE is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

Am79C978 151

physical, logical filtering, broad-

cast, and promiscuous.

This bit is always read/write ac-

cessible. RCVME is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. XMTE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 POWER Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 SPEED Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR6: LED2 Status

BCR6 controls the function(s) that the LED2 pin dis-

plays. Multiple functions can be simultaneously enabled

on this LED pin. The LED display will indicate the logical

OR of the enabled functions.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED2 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED2 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM PREAD operation.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical val ue of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read accessible al-

ways. This bit is read only; writes

have no effect. LED OUT is unaf-

fected by H_RESET, S_RESET,

or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s f als e (i .e., t he L ED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole ou tput and the ou tput value

will be the same polarity as the

LEDOUT status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

152 Am79C978

This bit is always read/write ac-

cessible. LEDPOL is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be g overned by the LE DOUT

and LEDPOL values.

This bit is always read/write ac-

cessible. LEDDIS is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a v alue of 1 is passe d

to the LEDOUT bit in this register

when the Am79C978 controller is

operating at 100 Mbps mode.

This bit is always read/write ac-

cessible. 100E is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

11-10 RES Reserved locations. Written and

read as zero s.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passed to the LE DOUT bit in

this register when Magic Packet

frame mode is enabled and a

Magic Packet frame is detected

on the network.

This bit is always read/write ac-

cessible. MPSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT sig nal when the A m79 C97 8

controller is functioning in a Link

Pass s ta te and fu ll- d upl ex op er a-

tion is enabled. When the

Am79C 978 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

This bit is always read/write ac-

cessible. FDLSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretche r.

This bit is always read/write ac-

cessible. PSE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 LNKSE Link Status Enable. When this bit

is set, a val ue of 1 w ill be pas sed

to the LEDOUT bit in this register

in Link Pass state.

This bit is always read/write ac-

cessible. LNKSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

This bit is always read/write ac-

cessible. RCVME is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

activity on the network.

Am79C978 153

This bit is always read/write ac-

cessible. XMTE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 POWER Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 SPEED Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR7: LED3 Status

BCR7 controls the function(s) that the LED3 pin dis-

plays. Multiple functions can be simultaneously enabled

on this LED pin. The LED display will indicate the logical

OR of the enabled functions. BCR7 defaults to Transmit

Status (XMT) with pulse stretcher enabled (PSE = 1)

and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED3 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED3 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical val ue of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read accessible al-

ways. This bit is read only; writes

have no effect. LED OUT is unaf-

fected by H_RESET, S_RESET,

or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s f als e (i .e., t he L ED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit.).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole ou tput and the ou tput value

will be the same polarity as the

LEDOUT status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

This bit is always read/write ac-

cessible. LEDPOL is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

154 Am79C978

will be g overned by the LE DOUT

and LEDPOL values.

This bit is always read/write ac-

cessible. LEDDIS is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a v alue of 1 is passe d

to the LEDOUT bit in this register

when the Am79C978 controller is

operating at 100 Mbps mode.

This bit is always read/write ac-

cessible. 100E is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

11-10 RES Reserved locations. Written and

read as zero s.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passed to the LE DOUT bit in

this register when magic frame

mode is enabled and a magic

frame is detected on the network.

This bit is always read/write ac-

cessible. MPSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT sig nal when the A m79 C97 8

controller is functioning in a Link

Pass s ta te and fu ll- d upl ex op er a-

tion is enabled. When the

Am79C978 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

This bit is always read/write ac-

cessible. FDLSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretche r.

This bit is always read/write ac-

cessible. PSE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 LNKSE Link Status Enable. When this bit

is set, a val ue of 1 w ill be pas sed

to the LEDOUT bit in this register

in Link Pass state.

This bit is always read/write ac-

cessible. LNKSE is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

This bit is always read/write ac-

cessible. RCVME is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

activity on the network.

This bit is always read/write ac-

cessible. XMTE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 POWER Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

Am79C978 155

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 SPEED Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR9: Full-Duplex Control

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-3 RES Reserved locations. Written as

zeros and read as und efi ned.

2 FDRPAD Full-Duplex Runt Packet Accept

Disable. W hen FDRP AD is set to

1 and full-duplex mode is en-

abled, the Am79C978 controller

will only receive frames that meet

the minimum Ethernet frame

length of 64 b ytes. Rec eive DMA

will not start until at least 64 bytes

or a complete frame have been

received. By de fault, FDRPAD is

cleared to 0. The Am79C978 con-

troller will accept any length

frame and receive DMA will start

according to the programming of

the receive FIFO watermark.

Note that there should not be any

runt packets in a full-duplex net-

work, since the main cause for

runt packets is a network collision

and there are no collisions in a

full-duple x netwo rk.

This bit is always read/write ac-

cessible. FDRPAD is cleared by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

1 RES Reserved locations. Written as

zeros and read as undefined.

0 FDEN Full-Duplex Enable. FDEN con-

trols whether full-duplex opera-

tion is enabled. When FDEN is

cleare d and the Auto- Negotia tion

is disabled, full-duplex operation

is not enabled and the

Am79C978 controller will always

operate in half-duplex mode.

When FDEN is set, the

Am79C978 controller will operate

in full-duplex mode. Do not set

this bit when Auto-Negotiation

is enabled.

This bit is always read/write ac-

cessible. FDEN is reset to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR16: I/O Base Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-5 IOBASEL Reserved locations. After

H_R ESET, t he valu e of thes e bit s

will be u ndefin ed. Th e sett ings o f

these bits will have no effect on

any Am79C978 controller func-

tion.

These bits are always read/write

accessible. IOBASEL is not af-

fected by S_RESET or STOP.

4-0 RES Reserved locations. Written as

zeros, read as undefined.

BCR17: I/O Base Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IOBASEU Reserved locations. After

H_RESET, the value in this regis-

ter will be undefined. The settings

of this regis ter will have no effec t

on any Am79C978 controller

function.

156 Am79C978

This bit is always read/write ac-

cessible. IOBASEU is not affect-

ed by S_RESE T or STOP.

BCR18: Burst and Bus Control Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-12 ROMTMG Expansion ROM Timing. The val-

ue of ROMTMG is used to tune

the timing for all EBDATA

(BCR30) accesses to Flash/

EPROM as well as all Expansion

ROM a ccesses to Flash/EPRO M.

ROMTMG, during read opera-

tions, defines the time from when

the Am79C978 controller drives

the lower 8 or 16 bits of the Ex-

pansion Bus Address bus to

when the Am79C978 controller

latches i n th e dat a on the 8 or 1 6

bits of the Expansion Bus Data

inputs. ROMTMG, during write

operatio ns, defi nes the time from

when the Am79C978 controller

drives the lower 8 or 16 bits of the

Expansi on Bus Data to when the

EBWE and EROMCS deassert.

The register value specifies the

time in number of clock cycles +1

according to Table 36.

Note: Programming ROMTNG

with a value of 0 is not permitted.

The access time for the Expan-

sion ROM or the EBDATA

(BCR30) device (tACC) during

read operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA_EBA[7:0]

outputs (tv_A_D) and by subtract-

ing the input to clock setup time

for the EBD[7:0] inputs (ts_D)

from the time defined by ROMT-

MG:

tACC = ROMTMG * CLK period

*CLK_FAC - (tv_A_D) + (ts_D)

The access time for the Expan-

sion ROM or for the EBDATA

(BCR30) device (tACC) during

write operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA EBA [7:0]

outputs (tv_A_D) and by adding

the input to clock setup time for

Flash/EPRO inputs (ts_D) from

the time defined by ROMTMG.

tACC = ROMTMG * CLK period *

CLK_FAC - (tv_A_D) - (ts_D)

For an adapter card application,

the value used for clock period

should be 30 ns to guarantee cor-

rect interface timing at the maxi-

mum clock frequency of 33 MHz.

These bits are read accessible al-

ways; write accessible only when

the STOP bi t is set. ROMTMG is

set to the value of 1001b by

H_RESET an d is not affected by

S_RESET or STOP. The default

value allows using a n Expansio n

ROM with a n access time of 250

ns in a system with a maximum

clock frequency of 33 MHz.

11 NOUFLO No Underflow on Transmit. When

the NOUFLO bit is set to 1, the

Am79C978 controller will not start

transmitting the preamble for a

packet until the Transmit Start

Point (CSR80, bits 10-11) re-

quirement (except when XMTSP

= 3h, Ful l Packet has no mean ing

when NOUFLO is set to 1) has

been met and the complete pack-

et has been DMA’d into the

Am79C978 controller. The com-

plete packet may reside in any

combination of the Bus Transmit

FIFO, the SRAM, and the MAC

Transmit FIFO as long as enough

of the packet is in the MAC Trans-

mit FIFO to meet the Transmit

Start Point requirement. When

the NOUFLO bit is cleared to 0,

the Transmit Start Point is the

only restriction on when preamble

transmission begins for transmit

packets.

Table 36. ROMTNG Programming Values

ROMTMG (bits 15-12) No. of Expansion Bus Cycles

1h<=n <=Fh n+1

Am79C978 157

Setting the NOUFLO bit guaran-

tees that the Am79C978 control-

ler will never suffer transmit

underflows, because the arbiter

that controls transfers to and from

the SRAM guarantees a worst

case latency on transfers to and

from the MAC and Bus Transmit

FIFOs such that it will never un-

derflow if the complete packet

has been DMA’d into the

Am79C978 controller before

packet transmission begins.

The NOUFLO bit has no effect

when the Am79C978 controller is

operating in the NO-SRAM mode.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. NOUFLO is cleared to 0 af-

ter H_RESET or S_RESET and

is unaffected by STOP.

10 RES Reserved location. Written as

zero and read as undefined.

9 MEMCMD Memory Command used for burst

read accesses to the transmit

buffer. When MEMCMD is set to

0, all burst read accesses to the

transmit buffer are of the PCI

command type Memory Read

Line (type 14). When MEMCMD

is set to 1, all burst read accesses

to the transmit buffer are of the

PCI command type Memory

Read Multiple (type 12).

This bit is read accessible al-

ways; write accessible only when

either the ST OP or the SPND bit

is set. MEMCMD is cleared by

H_RESET an d is not affected by

S_RESET or STOP.

8 EXTREQ Extended Request. This bit con-

trols the deassertion of REQ for a

burst transaction. If EXTREQ is

set to 0, REQ is deasserted at the

beginning of a burst transaction.

(The Am79C978 controller never

performs more than one burst

transaction within a single bus

mastershi p period.) In th is mode,

the Am79C978 controller relies

on the PCI latency timer to get

enough bus bandwidth, in case

the system arbiter also removes

GNT at the beginning of the burst

transaction. If EXTREQ is set to

1, REQ stays asserted until the

last but one data phase of the

burst transaction is done. This

mode is useful for systems that

implement an arbitration scheme

without preemption and require

that REQ stays asse rted th rough-

out the transaction.

EXTREQ should not be set to 1

when the Am79C978 controller is

used in a PCI bus application.

This bit is read accessible al-

ways, write accessible only when

either the STO P or the SPND bit

is set. EXTREQ is cleared by

H_RESET an d is not affected by

S_RESET or STOP.

7 DWIO Double Word I/O. When set, this

bit indicates that the Am79C978

controller is programmed for

DWord I/O (DWIO) mode. When

cleared, th is bi t indica tes th at the

Am79C978 controller is pro-

grammed for Word I/O (WIO)

mode. This bit affects the I/O Re-

source Offset map and it affects

the defined width of the

Am79C978 controller’s I/O re-

sources. See the DWIO and WIO

sections for more details.

The initial value of the DWIO bit is

determined by the programming

of the EEPROM.

The value of DWIO can be al-

tered automatically by the

Am79C9 78 controller. Sp ecifical-

ly, the Am79C978 controller will

set DWIO if it detects a DWord

write access to offset 10h from

the Am79C978 controller’s I/O

base address (corresponding to

the RDP resour ce ).

Once th e DWIO bit has be en se t

to a 1, only a H_RESET or an EE-

PROM read can reset it to a 0.

(Note that the EEPROM read op-

eration will only set DWIO to a 0 if

the appropriate bit inside of the

EEPROM is set to 0.)

158 Am79C978

This bit is read accessible al-

ways. DWIO is read only, write

operatio ns have no effect. DW IO

is cleared by H_RESET and is

not affecte d S_RE SET o r by s et-

ting the STOP bit.

6 BREADE Burst Read Enable. When set,

this bit enables burst mode during

memory read accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during read accesses. The

Am79C978 controller can per-

form burst transfers when reading

the initialization block, the de-

scriptor ring entries (when

SWSTYLE = 3), and the buffer

memory.

BREADE should be set to 1 when

the Am79C978 controller is used

in a PCI bus application to guar-

antee maximum performance.

This bit is read accessible al-

ways; write accessible only when

either the ST OP or the SPND bit

is set. BREADE is cleared by

H_RESET an d is not affected by

S_RESET or STOP.

5 BWRITE Burst Write Enable. When set,

this bit enables burst mode during

memory write accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during write accesses. The

Am79C978 controller can per-

form bur st tra nsfers when writin g

the descriptor ring entries (when

SWSTYLE = 3), and the buffer

memory.

BWRITE should be set to 1 when

the Am79C978 controller is used

in a PCI bus application to guar-

antee maximum performance.

This bit is read accessible al-

ways, write accessible only when

either the ST OP or the SPND bit

is set. BWRITE is cleared by

H_RESET an d is not affected by

S_RESET or STOP.

4-3 PHYSEL[1:0] PHYSEL[1:0] bits allow for soft-

ware controlled selection of differ-

ent operation and test modes.

The normal mode of operatio n is

when both bi ts 0 and 1 are set t o

0 to select the Expansion ROM/

Flash. Setting bit 0 to 1 and bit 1

to 0 allo ws snooping of the inter-

nal MII-compatible bus to allow

External Address Detection Inter-

face (EADI). See Table 37 for de-

tails.

Table 37. PHY Select Programming

These bits are read accessible al-

ways, these bits can only be writ-

ten from the EEPROM unless a

write-enable bit, BCR2[13], is set.

PHYSEL [1:0] is cleared by

H_RESET and is not affected by

S_RES E T or STOP .

2-0 LINBC Reserved locations. These bits

are read accessib le alway s; writ e

accessible only when either the

STOP o r the SPN D bit is set. Af-

ter H_RES ET, the value in th ese

bits will be 001b. The setting of

these bits have no effect on any

Am79C978 controller’s function.

LINBC is not affected by

S_RES E T or STOP .

BCR19: EEPROM Control and Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PVALID EEPROM Valid status bit. This bit

is read accessible only. PVALID

is read only; write operations

have no effect. A value of 1 in this

bit indicates that a PREAD opera-

tion has occurred, and that (1)

there is an EEPROM connected

to the Am79C978 controller inter-

face pins and (2) the contents

read from the EEPROM have

passed the checksum verification

operation.

PHYSEL [1:0] Mode

00 Expansion ROM/Flash

01 EADI/Internal MII Snoop

10 Reserved

11 Reserved

Am79C978 159

A value of 0 in t his bit indicat es a

failure in reading the EEPROM.

The checksum for the entire 82

bytes of EEPROM is i ncorrect or

no EEPROM is connect ed to the

interface pins.

PVALID is set to 0 during

H_RESET and is unaffected by

S_RESET or the STO P bit. How-

ever, following the H_RESET op-

eration, an automatic read o f the

EEPROM will be performed. Just

as it is true for the normal PREAD

command, at the end of this auto-

matic read operation the PVALID

bit may be set to 1. Therefore,

H_RESET will set the PVALID bit

to 0 at first, but the automatic EE-

PROM read operation may later

set PVALID to a 1.

If PVALID becomes 0 following

an EEPROM read operation (ei-

ther automatically generated af-

ter H_RESET, or requested

through PREAD), then all EE-

PROM-pro gramm abl e B CR l oca-

tions will be reset to their

H_R ESET va lue s. Th e con ten t of

the Address PROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI, and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will not be set. This ap-

plies to th e automa tic read of the

EEPROM after H_RESET, as

well as to host-initiated PREAD

commands.

14 PREAD EEPROM Read command bit.

When this bit is set to a 1 by the

host, the P VALID bit (BCR19 , bit

15) will imm ediate ly be res et to a

0, and then the Am79C978 con-

troller will perform a read opera-

tion of 82 bytes from the

EEPROM through the interface.

The EEPROM data that is

fetched during the read will be

stored in the appropriate internal

registers on board the

Am79C978 controller. Upon com-

pletion of the EEPROM read op-

eration, the Am79C978 controller

will assert the PVALID bit. EE-

PROM contents will be indirectly

accessible to the host through

read accesses to the Address

PROM (offsets 0h through Fh)

and through read accesses to

other EEPROM programmable

registers. Note t hat read access-

es from these locations will not

actually access the EEPROM it-

self, but instead will access the

Am79C978 internal copy of the

EEPROM contents. Write ac-

cesses to these locations may

change the Am79C978 register

contents, bu t the EEPROM loca-

tions will not be affected. EE-

PROM locations may be

accessed directly through

BCR19.

At the end of the read operation,

the PREAD bit will automatically

be reset to a 0 by the Am79C978

controller and PVALID will be set,

provide d that an EEP ROM exist-

ed on the in terface pins and tha t

the checksum for the entire 68

bytes of EEPROM was correct.

Note that when PREAD is set to a

1, then the Am79C978 controller

will no longe r respond to any ac-

cesses directed toward it, until

the PREAD operation has com-

pleted successfully. The

Am79C978 controller will termi-

nate thes e acces ses with the a s-

sertion of DEVSEL and STOP

while TRDY is not asserted, sig-

naling to the initiator to discon-

nect and retry the access at a

later time.

If a PREA D c omm and is gi v en t o

the Am79C978 controller but no

EEPROM is attached to the inter-

face pins, the PREAD bit will be

cleared to a 0, and the PVALID bit

will remain reset with a value of 0.

This applies to the automatic

read of the EEPROM after

H_RESET as well as to host initi-

ated PREAD commands. EE-

PROM programmable locations

on board th e Am79C978 c ontrol-

ler will be set to their defau lt val-

ues by such an aborted PREAD

160 Am79C978

operation. For example, if the

aborted PREAD oper a tion imm e-

diately followed the H_RESET

operation, then the final state of

the EEPROM programmable lo-

cations will be equal to the

H_RESET programming for

those locations.

If a PREAD command is gi v en t o

the Am79C978 controller and the

auto-detection pin (EESK/LED1)

indicates that no EEPROM is

present, then the EEPROM rea d

operation will still be attempted.

Note that at the end of the

H_RESET operation, a read of

the EEPROM will be performed

automatically. This H_RESET-

generated EEPROM read func-

tion will not proceed if the auto-

detection pin (EESK/LED1) indi-

cates that no EEPROM is

present.

This bit is read accessible al-

ways; write accessible only when

either the ST OP or the SPND bit

is set. PREAD is set to 0 during

H_RESET and is unaffected by

S_RESET or the STOP bit.

13 EEDET EEPROM Detect. This bit indi-

cates the sampled value of the

EESK/LED1 pin at the end of

H_RESET. This value indicates

whether or not an EEPROM is

present at the EEPROM inter-

face. If this bit is a 1, it indicates

that an EEPROM is present. If

this bit is a 0, it indicates that an

EEPROM is not present.

This bit is read accessible only.

EEDET is read only; write opera-

tion s ha ve no ef f e ct. Th e va lu e of

this bit is determined at the end of

the H_RESE T operation . It is u n-

affected by S_RESET or the

STOP bit.

Table 38 indicates the possible

combinations of EEDET and the

existence of an EEPROM and the

resulti ng op erati ons that ar e pos-

sible on the EEPROM interface.

12-5 RES Reserved locations. Written as

zeros; read as undefined.

4 E EN EEPRO M Port Enabl e. When this

bit is se t to a 1, it cau ses th e va l-

ues of ECS, ESK, and EDI to b e

driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN = 0 and no EEPROM read

function is currently active, then

EECS wil l be driven L OW. Whe n

EEN = 0 and no EEPROM read

function is currently active, EESK

and EEDI pins will be driven by

the LED registers BCR5 and

BCR4, respectively. See Table

39.

This bit is read accessible al-

ways, write accessible only when

either the STO P or the SPND bit

is set. EEN is set to 0 by

H_RESET and is unaffected by

the S_RESET or STOP bit.

3 RES Reserved location. Written as

zero and read as undefined.

2 ECS EEPROM Chip Select. This bit is

used to control the value of the

EECS pin of the interface when

the EEN bit is set to 1 and the

PREAD b it is se t to 0 . If E EN = 1

and PREAD = 0 and ECS is set to

a 1, then the EECS pin will be

forced to a HIGH level at the ris-

ing edg e of the next clock follow-

ing bit programming.

If EEN = 1 and PREAD = 0 and

ECS is set to a 0, then the EECS

pin will be forced to a LOW lev el

at the rising edge of the next

clock following bit programming.

ECS has no effect on the output

value of the EECS pin unless the

PREAD bit is set to 0 and the

EEN bit is set to 1.

This bit is read accessible al-

ways, write accessible only when

either the STO P or the SPND bit

is set. ECS is set to 0 by

H_RESET an d is not affected by

S_RESET or STOP.

Am79C978 161

Table 38. EEDET Setting

1 ESK EEPROM Serial Clock. This bit

and the EDI/EDO bit are used to

control host access to the EE-

PROM. Values programmed to

this bit are pla ced onto the EE SK

pin at t he rising edge of the next

clock following bit programming,

except when the PREAD bit is set

to 1 or the EEN bit is set to 0. If

both the ESK bit and the EDI/

EDO bit value s are c hanged dur-

ing one BCR19 write operation,

while EEN = 1, then setup and

hold times of the EEDI pin value

with respect to the EESK signal

edge are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is set to

0 and the EEN bit is set to 1.

This bit is read accessible al-

ways, write accessible only when

either the ST OP or the SPND bit

is set. ESK is reset to 1 by

H_RESET an d is not affected by

S_RESET or STOP.

0 EDI/EDO EEPROM Data In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the interface, except

when the PREAD bit is set to 1 or

the EEN bit is set to 0. Data that

is read from this bit reflects the

value of the EEDO input of the in-

terface.

EDI/EDO has no effect on the

EEDI pin unl ess th e PREAD bi t is

set to 0 and the E EN bit is set to

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set. EDI/

EDO is reset to 0 by H_RESET

and is not affected by S_RESET

or STOP.

BCR20: Software Style

This register is an alias of the location CSR58. Accesses

to and from this register ar e equival ent to accesses to

CSR58.

Bit Name Description

31-11 RES Reserved locations. Written as

zeros and read as undefined.

EEDET Value

(BCR19[13]) EEPROM

Connected? Result if PREAD is Set to 1 Result of Automatic EEPROM Read

Operation Following H_RESET

0No EEPROM read operation is attempted.

Entire read sequence will occur , checksum

failure will result, PVALID is reset to 0.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

0Yes EEPROM read operation is attempted.

Entire read sequence will occur , checksum

operation will pass, PVALID is set to 1.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

1No EEPROM read operation is attempted.

Entire read sequence will occur , checksum

failure will result, PVALID is reset to 0.

EEPROM read operation is attempted.

Entire rea d sequ ence wi ll occu r, checks um

failure will result, PVALID is reset to 0.

1Yes EEPROM read operation is attempted.

Entire read sequence will occur , checksum

operation will pass, PVALID is set to 1.

EEPROM read operation is attempted.

Entire rea d sequ ence wi ll occu r, checks um

operation will pass, PVALID is set to 1.

Table 39. Interface Pin Assignment

RST Pin PREAD or Auto

Read in Progress EEN EECS EESK EEDI

Low X X 0 Tri-State Tri-State

High 1 X Active Active Active

High 0 1 Fro m ECS

Bit of BCR19 From ESK Bit of

BCR19 From EEDI Bit of

BCR19

High 0 0 0 LED1 LED0

162 Am79C978

10 APERREN Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer tha t was a ccessed wh en a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descr iptor , SWS TYLE (b its

7-0 of this register) must be set to

2 or 3 to p rogr am t he A m79 C97 8

controller to use 32-bit software

structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C978 controller is the

target of the transfer.

Read anytime; write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

9 RES Reserved location. Written as ze-

ro; read as undefined.

8 SSIZE32 Software Size 32 bits . When set,

this bit indicates that the

Am79C978 controller utilizes 32-

bit software structures for the ini-

tialization block and the transmit

and receive descriptor entries.

When cleared, this bit indicates

that the Am79C978 controller uti-

lizes 16-bit software structures for

the initialization block and the

transmit and receive descriptor

entries. In this mode, the

Am79C978 controller is back-

wards compatible with the

Am799 0 LANCE and Am79C96 0

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined by the Am 79C978 cont ro l-

ler accor ding to the setting of the

Software Style (SWSTYLE, bits

7-0 of this register).

This bit is always read accessi-

ble. SSIZE32 is read only; write

operations will be ignored.

SSIZE32 will be cleared after

H_RESET (since SWSTYLE de-

faults to 0) and is no t affec ted by

S_RESET or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-b it add ress

bus duri ng maste r acces ses i niti-

ated by the Am79C978 controller.

This action is required, since th e

16-bit software structures speci-

fied by the SSIZE32 = 0 setting

will yield only 24 bits of address

for Am79C978 controller bus

mast er accesses.

If SSIZE32 is set, then the soft-

ware stru ctu re s that ar e co mmo n

to the Am79C978 controller and

the host system will supply a full

32 bits for each address pointer

that is need ed by th e A m7 9C97 8

controller for performing master

accesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are alway s driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE3 2 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in thi s register de termines th e

style of register and memory re-

sources that sha ll be used by the

Am79C978 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width of

the descriptors and initialization

block entries.

All Am79C978 CSR bits and all

descriptor, buffer, and initializa-

tion block entries not cited in the

Table 40 are unaffected by the

Software St yl e se lec ti on an d are ,

therefore, always fully functional

as specified in the CSR and BCR

sections.

Am79C978 163

Read/Write accessible only when

either the ST OP or the SPND bit

is set. The SWSTYLE register will

contain the value 00h following

H_RESET and wi ll be un affecte d

by S_RESET or STOP.

BCR22: PCI Latency Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-8 MAX_LAT Maximum Latency. Specifies the

maximum arbitration latency the

Am79C978 controller can sustain

without causing problems to the

network ac tivi ty . T he register val-

ue specifies the time in units of 1/

4 microseconds. MAX_LAT is

aliased to the PCI configuration

space register MAX_LAT (offset

3Fh). Th e host will u se the valu e

in the register to determine the

setting of the Am79C978 Latency

Timer register.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

MAX_LAT is set to the value of

FFh by H_RESET which results

in a default maximum latency of

63.75 microseconds. It is re com-

mended to program the value of

18h via EEPROM. MAX_LAT is

not affected by S_RESET or

STOP.

7-0 MIN_GNT Minimum Grant. Specifies the

minimum length of a bu rst p eriod

the Am79C978 controller needs

to keep up with the network activ-

ity. Th e le ngth of the b ur st p er iod

is calculated assuming a clock

rate of 33 M Hz. The register val-

ue specifies the time in units of 1/

4 ms. M IN_GNT is aliase d to the

PCI Con figur ation Spac e reg ister

MIN_GNT (offset 3Eh). The host

will use the value in the register to

determine the setting of the

Am79C978 Latency Timer regis-

ter.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

MIN_GNT is set to the value of

06h by H_RESET which results

in a default minimum grant of

1.5 ms, whi ch is the tim e it takes

to Am79C978 controller to read/

wri t e half o f t h e FI F O . ( 16 D Wo rd

transfers in burst mode with one

extra wait state per data phase

inserted by the target.) Note tha t

the default is only a typical value.

It also does not tak e int o accoun t

any descriptor accesses. It is rec-

ommended t o program th e value

of 18h via EEPROM. MIN_GNT

is not affected by S_RESET or

STOP.

BCR23: PCI Subsystem Vendor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

Table 40. Software Styles

SWSTYLE

[7:0] Style

Name SSIZE32 Initialization Block

Entries Descriptor Ring Entries

00h LANCE/

PCnet-ISA

controller 016-bit software

structures, non-burst or

burst access

16-bit softw are structur es,

non-bur st acc es s onl y

01h RES 1RES RES

02h PCnet-PCI

controller 132-bit software

structures, non-burst or

burst access

32-bit softw are structur es,

non-bur st acc es s onl y

03h PCnet-PCI

controller 132-bit software

structures, non-burst or

burst access

32-bit softw are structur es,

non-burst or burst access

All Other RES Undefined Undefined Undefined

164 Am79C978

31-0 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 SVID Subsystem Vendor ID. SVID is

used together with SID (BCR24,

bits 15-0) to uniq uely identify the

add-in board or subsystem the

Am79C978 controller is used in.

Subsystem Vendor IDs can be

obtained from the PCI SIG. A val-

ue of 0 (the default) indicates that

the Am79C978 controller does

not su pport sub system i denti fica-

tion. SVID is aliased to the PCI

Configuration Space register

Subsystem Vendor ID (offset

2Ch).

This bit is always read accessi-

ble. SVID is read only. Write op-

erations are ignored. SVID is

cleared to 0 by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

BCR24: PCI Subsystem ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 SID Subsystem ID. SID is used to-

gether with SVID (BCR23, bits

15-0) to uniquely identify the add-

in board or subsystem the

Am79C978 controller is used in.

The value of SID is up to the sys-

tem vendor. A value of 0 (the de-

fault) indicates that the

Am79C978 controller does not

support subsystem identification.

SID is aliased to the PCI configu-

ration space register Subsystem

ID (offset 2Eh).

This bit is always read accessi-

ble. SID is r ead only. Write oper-

ations are ignored. SID is cleared

to 0 by H_RESET and is not af-

fected by S_RESET or by setting

the STOP bit.

BCR25: SRAM Size Register

Bit Name Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-8 RES Reserved locations. Written as

zeros and read as undefined.

7-0 SRAM_SIZE SRAM Size. Specifies the upper

8 bits of the 16-bit total size of the

SRAM buffer. Each bit in

SRAM _SIZE account s for a 512-

byte page. The starting address

for the lo wer 8 bi ts is as su med to

be 00h and the ending address

for the lower is assumed to be

FFh. Therefore, the maximum ad-

dress range is the starting ad-

dress of 0000h to ending address

of ((SRAM_SIZE+1) * 256 words)

or 17FFh. An SRAM_SIZE value

of all zeros specifies that no

SRAM will be u sed and the inter -

nal FIFOs will be joined into a

contiguous FIFO similar to the

PCnet-PCI II controller.

Note: The minimum allowed

number of pa ges is eight for nor-

mal network operation. The

Am79C978 c ontroller wi ll not op-

erate correctly with less than the

eight pages of memory. When

the minimum number of pages is

used, these pages must be allo-

cated four each for transmit and

receive.

CAUTION: Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM_SIZE is 0.

This bit is always read accessi-

ble; write accessible only when

the STOP bit is set. SR AM_SIZE

is set to 000000b during

H_RESET and is unaffected by

S_RESET or STOP.

BCR26: SRAM Boundary Register

Bit Name Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-8 RES Reserved locations. Written as

zeros and read as undefined.

7-0 SRAM_BND SRAM Boundary. Specifies the

upper 8 bits of the 16-bit addre ss

Am79C978 165

boundary where the receive buffer

begins in the SRAM. The transmit

buffer in the SRAM begins at ad-

dress 0 and ends at the address

located just before the address

specified by SRAM_BND. There-

fore, the receive buffer always be-

gins on a 512 byte boundary. The

lower bits are assumed to be ze-

ros. SRAM_BND has no effect in

the Low Latency Receive mode.

Note: The minimum allowed

number of pages is four. The

Am79C9 78 controller wi ll not op-

erate correctly with less than four

pages of memory per queue. See

Table 41 for SRAM_BND pro-

gramming details.

CAUTION: Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_BND is set to

00000000b during H_RESET

and is unaffected by S_RESET or

STOP.

BCR27: SRAM Interface Control Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 PTR TST Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

This bit is always read/write ac-

cessib le. PTR_T ST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

14 LOLATRX Low Latency Receive. When the

LOLATRX bit is set to 1, the

Am79C978 controller will switch

to an architecture applicable to

cut-through switches. The

Am79C978 controller will assert a

receive frame DMA after only 16

bytes of the current receive frame

has been received regardless of

where the RCVFW (CSR80, bits

13-12) ar e set. The water mark is

a fixed value and cannot be

changed. The receive FIFOs will

be in NO_SRAM mode while all

transmit traffic is buffered through

the SRAM. This bit is only valid

and the low latency receive only

enabled when the SRAM_SIZE

(BCR25, bits 7-0) bits are non-ze-

ro. SRAM_BND (BCR26, bits 7-

0) has no meaning when the

Am79C978 controller is in the

Low Lat ency mod e. See the se c-

tion on SRAM Configuration for

more details.

When the LOLATRX bit is set to

0, the Am79C978 controller will

return to a normal receive config-

uration. The runt packet accept

bit (RPA, CSR124, bit 3) must be

set when LOLATRX is set.

CAUTION: To provide data in-

tegrity when switching into

and out of the low latency

mode, DO NOT SET the

FASTSPNDE (CSR7, bit 15) bit

when setting the SPND bit. Re-

ceive frames WILL be overwrit-

ten and the Am79C978

controller may give erratic be-

havior w hen it is ena ble again .

The minimum allowed number

of pages is four. The

Am79C978 controller will not

operate correctly in the LOLA-

TRX mode with less than four

pages of memory.

Read/Write accessible only when

the STOP bi t is set. LO LATRX is

cleared to 0 after H_RESET or

S_RESET and is unaffected by

STOP.

13-6 RES Reserved locations. Written as

zeros and read as undefined.

Table 41. SRAM_BND Programming

SRAM Addresses SRAM_BND [7:0]

Minimum SRAM_BND

Address 04h

Maximum SRAM_BND Address 13h

166 Am79C978

5-3 EBCS Expansion Bus Clock Source.

These bit s are u sed to sel ect the

source of the fundamental clock

to drive the SRAM and Expansion

ROM access cycles. Table 42

shows the selected clock source

for the various values of EBCS.

Note that the actual frequency

that the Expansion Bus access

cycle s run at is a func tion of bot h

the EBCS and CLK_FAC

(BCR27, bits 2-0) bit field set-

tings. When EBCS is set to either

the PCI clock or the Time Base

clock , no ex ter na l c l ock s ource is

required as the cl ocks are route d

internally and the EBCLK pin

should b e pulled to VDD t hrough

a resistor.

Read accessible always; write

accessible only when the STOP

bit is set. EBCS is set to 000b

(PCI clock selected) during

H_RESET and is unaffected by

S_RESET or the STOP bit.

Note: The clock frequency driv-

ing the Expansion Bus access cy-

cles that re su lts from the se tti ngs

of the EBCS and CLK FAC bits

must not exceed 33 MHz at any

time. Whe n E BCS is set to eith er

the PCI clock or the Time Base

clock, no exte rn al cloc k sourc e is

required because the clocks are

routed internally and the EBCLK

pin should be pulled to VDD

through a resistor.

CAUTION: Care should be ex-

ercised when choosing the PCI

clock pin because of the nature

of the PCI clock signal. The PCI

specification states that the

PCI clock can be stopped. If

that can occu r wh ile it is being

used for the Expansion Bus

clock data, corruption will re-

sult.

CAUTION: The Time Base

Clock will not support 100

Mbps operation and should

only be selected in 10 Mbps-

only configurations.

CAUTION: The external clock

source used to drive the

EBCLK pin must be a continu-

ous clock source at all times.

2-0 CLK_FAC Clock Factor. These bits are used

to select whether the clock select-

ed by EBCS is used directly or if it

is divided down to give a slower

clock for running the Expansion

Bus access cycles. The possible

factors are given in Table 43.

Read accessible always; write

accessible only when the STOP

bit is set. CLK_FAC is set to 000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

BCR28: Expansion Bus Port Address Lower (Used

for Flash/EPROM and SRAM Accesses)

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 EPADDRL Expansion Port Address Lower.

This address is used to provide

addresses for the Flash and

SRAM port accesses.

SRAM accesses are started

when a read or write is performed

on BCR30 and the FLASH (B CR

29, bit 15) is set to 0. During

SRAM accesses only bits in the

EPADDRL are valid. Since all

SRAM acc esses are wor d orient-

ed only, EPADDRL[0] is the least

significant word address bit. On

Table 42. EBCS Values

EBCS Expansion Bus Clock Source

000 CLK pin (PCI Clock)

001 Time Base Clock

010 EBCLK pin

011 Reserved

1XX Reserved

Table 43. CLK_FAC Values

CLK_FAC Clock Factor

000 1

001 1/2 (divide by 2)

010 Reserved

011 1/4 (divide by 4)

1XX Reserved

Am79C978 167

any byte write accesses to the

SRAM, the user will have to fol-

low the read-modify-write

scheme. On any byte read ac-

cesses to the SRAM, the user will

have to chose which byte is

needed from the complete word

returned in BCR30.

Flash acce ss es are started whe n

a read or write is performed on

BCR30 and the FLASH (BCR 29,

bit 15) is set to 1. During Flash

accesses al l bits in EPA DDR are

valid.

Read accessible always; write

accessible only when the STOP

is set or when SRAM SIZE

(BC R25, b its 7- 0) is 0. EPA DDRL

is undefi ned after H_RES ET and

is unaffected by S_RESET or

STOP.

BCR29: Expansion Port Address Upper (Used for

Flash/EPROM Accesses)

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 FLASH Flash Access. When the FLASH

bit is s et to 1 , the E xpansio n Bus

access will be a Flash cycle.

When FLA SH is set to 0, the Ex-

pansion Bus access will be a

SRAM cycle. For a complete de-

scription, see the section on Ex-

pansion Bus Accesses. This bit is

only app lica ble to reads or wri tes

to EBDATA (BCR3 0). It does no t

affect Expansion ROM accesses

from the PCI system bus.

This bit is always read accessi-

ble; write accessible only when

the STOP bit is set. FLASH is 0

after H_RESET and is unaffected

by S_RESET or the STO P bit.

14 LAAINC Lower Address Auto Increment.

When the LAAINC bit is set to 1,

the Expansion Port Lower Ad-

dress will automatically increment

by one after a read or write ac-

cess to EBDATA (BCR30). When

EBADDRL reaches FFFFh and

LAAINC is set to 1, the Expansion

Port Lower Address (EPADDRL)

will roll over to 0000h. When the

LAAINC bit is set to 0, the Expan-

sion Port Lower Address will not

be affected in any way after an

access to EBDA TA (BCR30) and

must be progr amm ed.

This bit is always read accessi-

ble; write accessible only when

the STOP bit is set. LAINC is 0 af-

ter H_RESET and is unaffected

by S_RESET or the STOP bit .

13-4 RES Reserved locations. Written as

zeros and read as undefined.

3-0 EPADDRU Expansion Port Address Upper.

This upper portion of the Expan-

sion Bus address is used to pro-

vide addresses for Flash/EPROM

port acces ses .

This bit is always read accessi-

ble; write accessible only when

the STOP bit is set or when

SRAM SIZ E (BCR25, bit s 7-0) is

0. EPADDRU is undefined after

H_RESET and is unaffected by

S_RESET or the STO P bit.

BCR30: Expansion Bus Data Port Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 EBDA TA Expansio n Bus Data Po rt. EBD A-

TA is the dat a port for op erations

on the Expansion Port accesses

involving SRAM and Flash ac-

cesses. The type of access is set

by the FLASH bit (BCR 29, bit

15). When the FLASH bit is set to

1, the Ex pansion B us acces s will

follow the Flash access timing.

When the FLASH bit is set to 0,

the Expansion Bus access will

follow the SRAM access timing.

Note: It is important to set the

FLASH bit and load Expansion

Port Address EPADDR (BCR28,

BCR29) with the required ad-

dress before attempting read or

write to the Expansion Bus data

port. The Flash and SRAM ac-

cesses use different address

168 Am79C978

phases. Incorrect configuration

will result in a possible c orruption

of data.

Flash read cycles are performed

when BCR30 is read and the

FLASH bit (BCR2 9, bit 15) is set

to 1. Upon completion of the read

cycle, the 8-bit result for Flash ac-

cess is stored in EBDATA[7:0],

EBDATA[15:8] is undefined.

Flash write c ycles are perfor med

when BCR30 is written and the

FLASH bit (BCR2 9, bit 15) is set

to 1. EBDATA[7:0] only is valid

for write cycles.

SRAM read cycles are performed

when BCR30 is read and the

FLASH bit (BCR2 9, bit 15) is set

to 0. Upon completion of the read

cycle, the 16-bit result for SRAM

access is stored in EBDATA.

Write cy cles to the SRA M are in-

voked when BCR30 is written

and the FLASH bit (BCR29, bit

15) is set to 0. Byte writes to the

SRAM must use a read-modify-

write scheme since the word is al-

ways valid for SRAM write or

read accesses.

This bit is read and write accessi-

ble only when the ST OP i s se t or

when SRAM SIZE (BCR25, bits

7-0) is 0. EBDATA is undefined

after H_RESET and is unaffected

by S_RESET and the STOP bit.

BCR31: Software Timer Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 STVAL Software Timer Value. STVAL

controls the maximum time for

the Software Timer to count be-

fore generating the STINT

(CSR7, bit 11) interrupt. The Soft-

ware Timer is a free-running timer

that is started upon the f irst write

to STVAL. After the first write, the

Software Timer will continually

count and set the STINT interrupt

at the STVAL period.

The STVAL value is interpreted

as an unsigned number with a

resolution of 256 Time Base

Clock periods. For instance, a

value of 122 ms would be pro-

grammed with a value of 9531

(253Bh) if the Time Base Clock is

running at 20 MHz. A value of 0 is

undefined and will result in erratic

behavior.

Read and write accessible al-

ways. STVAL is set to FFFFh af-

ter H_RESET and is unaffected

by S_RESET and the ST OP bit.

BCR32: PHY Control and Status Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 ANTST Reserved for manufacturing

tests. Written as 0 and read as

undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

This bit is always read/write ac-

cessible. ANTST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

14 MIIPD MII PHY Detect (is us ed for man-

ufacturing tests). MIIPD reflects

the quiescent state of the MDIO

pin. MIIPD is continuous ly upd at-

ed whenever there is no manage-

ment operation in progress on the

MII interface. When a manage-

ment operation begins on the in-

terface, the state of MIIPD is

preserved until the operation

ends, when the quiescent state is

again monitored and con tinuous-

ly updates the MIIPD bit. When

the MDIO pin is at a quiescent

LOW state, MIIPD is cleared to 0.

When the MDIO pin is at a quies-

cent HIGH state, MIIPD is set to

1. MIIPD is used by the automatic

port selection logic to select the

Am79C978 169

MII port. When the Auto Select bit

(ASEL, BCR2, bit 1) is a 1 and the

MIIPD bit is a 1, the MII port is se-

lected. Any transition on the MI-

IPD bit will set the MIIPDTI bit in

CSR7, bit 3.

Read accessible always. MIIPD

is read only. Write operations are

ignored and should not be per-

formed.

13-12 FMDC F ast Managem ent Data Clock (is

used for manufacturing tests).

When FMDC i s set to 1h, th e MII

Management Data Clock will run

at 5 MHz max. The Management

Data Clock will no longer be IEEE

802.3u-compliant and setting this

bit should be used with car e. The

accompanying external PHY

must also be able to accept man-

agement frames at the new clock

rate. When FMDC is set to 0h, the

MII Management Data Clock will

run at 2.5 MHz max and will be

fully compliant to IEEE 802.3u

standards. See Table 44.

This bit is always read/write ac-

cessible. FMDC is set to 0 during

H_RESET, and is unaffected by

S_RESET and the STOP bit

11 APEP Auto-Poll PHY. When APEP is

set to 1 t he A m7 9C97 8 c on tr oll er

will poll the status register in the

PHY. This feature allows the soft-

ware driver or upper layers to see

any changes in the status of the

PHY. An interrupt when enabled

is generated when the contents of

the new status is different from

the previous status.

This bit is always read/write ac-

cessible. APEP is set to 0 during

H_RESET and is unaffected by

S_RESET and the STOP bit.

10-8 APDW Auto- Poll Dwell Tim e. APDW de-

termines the dwell time between

PHY Management Frame

accesses when Auto-Poll is

turned on. See Table 45.

This bit is always read/write ac-

cessible. APDW is set to 100h af-

ter H_RESET and is unaffected

by S_RESET and the STOP bit.

7 DANAS Disable Auto-Negotiation Auto

Setup. When DANAS is set, the

Am79C978 controller after a

H_RESET or S_RESET will re-

main dormant and not automati-

cally startup the Auto-Negotiation

section or the enhanced automat-

ic port se lection se ction. Instead ,

the Am79C978 controller will wait

for the software driver to setup

the Auto-Negotiation portions of

the device. The PHY Address

and Data programming in BCR33

and BCR34 is still valid. The

Am79C978 controller will not

generate any management

frames unless Auto-Poll is en-

abled.

This bit is always read/write ac-

cessible. DANAS is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

6 XPHYRST PHY Reset. When XPHYRST is

set, the Am79C978 controller af-

ter an H_RESET or S_RESET

will issue management frames

that will reset the PHY. This bit is

needed when there is no way to

guarantee the state of the exter-

nal PHY. This bit must be repro-

grammed after every H_RESET.

Table 44. FMDC Values

FMDC Fast Management Data Clock

00 2.5 MHz max

01 5 MHz ma x

10 Reserved

11 Reserved

Table 45. APDW Values

APDW Auto-Poll Dwell Time

000 Continuous (26µs @ 2.5 MHz)

001 Every 128 MDC cycles (103µs @ 2.5 MHz)

010 Every 256 MDC cycles (206µs @ 2.5 MHz)

011 Every 512 MDC cycles (410 µs @ 2.5 MHz)

100 Every 1024 MDC cycles (819 µs @ 2.5 MHz)

101 Every 2048 MDC cycles (1640 µs @ 2.5 MHz)

110-111 Reserved

170 Am79C978

This bit is always read/write ac-

cessible. XPHYRST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYRST is onl y v alid when th e

internal Network Port M anager is

scanning for a network port.

5 XPHYANE PHY Auto-Negotiation Enable.

This bit will force the PHY into en-

abling Auto-Negotiation. When

set to 0 t he A m7 9C97 8 c on tr oll er

will send a management frame

disabli ng Aut o -N ego tia tio n.

This bit is always read/write ac-

cessible. XPHYANE is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE is only vali d when the

internal Network Port M anager is

scanning for a network port.

4 XPHYFD PHY Full Duplex. When set, this

bit will force th e PHY into full du-

plex when Auto-Negotiation is not

enabled.

This bit is always read/write ac-

cessible. XPHYFD is set to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

3 XPHYSP PHY Speed. When set, this bit

will force the PHY into 100 Mbps

mode when Auto-Negotiation is

not enabled.

This bit is always read/write ac-

cessible. XPHYSP is set to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

2 RES Reserved location. Written as

zero and read as undefined.

1 MIIILP Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loopback

on itself. The interface is mapped

in the following way. The

TXD[3:0] nibble data path is

looped back onto the RXD[3:0]

nibble data path. TX_CLK is

looped b ack as RX _CLK . TX_E N

is looped back as RX_DV. CRS is

correctly OR’d with TX_EN and

RX_DV and always encompass-

es the transmit frame. TX_ER is

looped back as RX_ER. Howev-

er, TX_ER will not get asserted

by the Am79C978 controller to

signal an err or. The TX_ER fun c-

tion is reserved for future use.

This bit is always read/write ac-

cessible. MIIILP is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

0 RES Reserved location. Written as

zero and read as undefined.

BCR33: PHY Address Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 SHADOW If the user wishes to update the

contents of the BCR33 shadow

value written into BCR33 (bit 15)

will enable the contents to be si-

multaneously written to BCR33

shadow.

14 MII_SEL MII selected. This bit indicates

whether the internal PHY is se-

lected.

13 AUTONEG_COMPLETE

Internal Auto-Negotiation com-

plete. Valid for internal PHY only.

12 LINK STATUS

Link Status. This bit is a valid link

status indication.

11 FULL_DUPLEX

Full Duplex. This bit indicates that

the MAC is configured for Full-

Duplex operation.

10 SPEED_SEL Speed Selected. This bit indi-

cates if High or Low speed has

been selected by MAC.

9-5 PHYAD Management Frame PHY Ad-

dress. PHYAD contains the 5-bit

PHY A ddress f ield tha t is us ed in

the manage ment frame that gets

clocked out via the MII manage-

ment port pins (MDC and MDIO)

Am79C978 171

whenever a read or write transac-

tion occurs to BCR34. The PHY

address 1Fh is not valid.

The Network Port Manager cop-

ies the PHYAD after the

Am79C978 controller reads the

EEPROM and uses i t to comm u-

nicate with the external PHY. The

PHY address must be pro-

grammed into the EEPROM prior

to starting the Am79C978 con-

troller.

These bits are always read/write

accessible. PHYAD is undefined

after H_RESET and is unaffected

by S_RESET and the STOP bit.

4-0 REGAD Management Frame Register Ad-

dress. REGAD contains the 5-bit

used in the management frame

that gets clocked out via the inter-

nal MII management interface

whenever a read or write transac-

tion occurs to BCR34.

These bits are always read/write

accessible. REGAD is undefined

after H_RESET and is unaffected

by S_RESET and the STOP bit.

BCR34: PHY Management Data Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 MIIMD MII Management Data. MIIMD is

the data port for operations on the

MII management interface (MDIO

and MDC). The Am79C978 con-

troller builds management frames

using the PHYAD and REGAD

values from BCR33. The opera-

tion code used in each frame is

based upon whether a read or

write operation has been per-

formed to BCR34. Read cycles

on the MII management interface

are invoked when BCR34 is read.

Upon completion of the read cy-

cle, the 16-bit result of the read

operation is stored in MIIMD.

Write cycles on the MII manage-

ment interface are invoked when

BCR34 is written. The v alue writ-

ten to M IIMD is the val ue us ed i n

the data fi el d of the ma nage men t

write frame.

These bits are always read/write

accessible. MIIMD is undefined

after H_RESET and is unaffected

by S_RESET and the ST OP bit.

BCR35: PCI Vendor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 VID Vendor ID. The PCI Vendor ID

identifi es the manufactu rer of the

Am79C978 controller. AMD’s

Vendor ID is 1022h. Note that this

Vendor ID is not the same as the

Manufacturer ID in CSR88 and

CSR89. The Vendor ID is as-

signed by the PCI Special Inter-

est Group.

The Vendor ID is not normally

programmable, but the

Am79C978 controller allows this

due to legacy operating systems

that do not look at the PCI Sub-

system Vendor ID and the Ven-

dor ID to uniquely identify the

add-in board or subsystem that

the Am79C978 controller is used

in.

Note: If the operating system

or the network operating sys-

tem supports PCI Subsystem

Vendor ID and Subsystem ID,

use those to identify the add-in

board or subsystem and pro-

gram the VID with the default

value of 1022h.

VID is aliased to the PCI configu-

ration space register Vendor ID

(offset 00h).

Read accessible always. VID is

read only. Write operations are

ignored. VID is set to 1022h by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

172 Am79C978

BCR36: PCI Power Management Capabilities (PMC)

Alias Register

Note: This register is an alias of the PMC register

located at offset 42h of the PCI Configuration Space.

Since PMC register is read only, BCR36 provides a

means of programming it through the EEPROM. The

contents of this register are copied into the PMC regis-

ter. For the definition of the bits in this register, refer to

the PMC register definition. Bits 15-0 in this register are

programmable through the EEPROM. Read accessible

always. Read only. Cleared by H_RESET and is not af-

fected by S_RESET or setting the STOP bit.

BCR37: PCI DATA Register 0 (DATA0) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_SCALE fi el d o f the P MCSR r egi ster.

Since these two are read only, BCR37 provides a

means of program ming them indirectly. The contents of

this register are copied into the corresponding fields

pointed wit h the DATA_SE L field set to zero . Bits 15 -0

in this register are programmable through the EE-

PROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D0_SCALE These bits correspond to the

DATA_SCALE field of the

PMCSR (offset Register 44 of the

PCI configuration space, bits 14-

13). Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D0_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA 0 These bits c orr es pon d to the P CI

DAT A re gi st e r (o f fs e t Re gi st e r 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

This bit is always read accessi-

ble. DATA0 is rea d only . Cleare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

BCR38: PCI DATA Register 1 (DATA1) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_SC ALE fi eld o f th e P MCS R r eg ister.

Since these two are read only, BCR38 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

sponding fields pointed with the DATA_SEL field set to

one. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D1_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (off set Reg ister 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

These bits are always read ac-

cessible. D1_SCALE is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7-0 DATA1 These bit s cor res pon d to th e P CI

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

These bits are always read ac-

cessible. DATA1 is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR39: PCI DATA Register 2 (DATA2) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_SC ALE fi eld o f th e P MCS R r eg ister.

Since these two are read only, BCR39 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

sponding fields pointed with the DATA_SEL field set to

two. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

Am79C978 173

9-8 D2_SCALE These bits correspond to the

DATA_SCALE field of the

PMCSR (offset Register 44 of the

PCI configuration space, bits 14-

13). Refer to the description of

DATA_SCALE for the meaning of

this field.

These bits are always read ac-

cessible. D2_SCALE is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7-0 DATA 2 These bits c orr es pon d to the P CI

DAT A re gi st e r (o f fs e t Re gi st e r 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

These bits are always read ac-

cessible. DATA2 is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR40: PCI DATA Register 3 (DATA3) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_S CAL E field of the P C MCR regi st er.

Since these two are read only, BCR40 provides a

means of programming them through the EEPROM.

The co ntents of th is reg ister are c opied i nto th e cor re-

sponding fields pointed with the DATA_SEL field set to

three. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D3_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offse t Regis ter 44 of t he PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

These bits are always read ac-

cessible. D3_SCALE is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7-0 DATA 3 These bits corr espon d to the P CI

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

These bits are always read ac-

cessible. DATA3 is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR41: PCI DATA Register 4 (DATA4) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_S CAL E field of the P CMCR r eg ister.

Since these two are read only, BCR41 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

sponding fields pointed with the DATA_SEL field set to

four. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D4_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D4_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit

7-0 DATA 4 These bits corr espon d to the P CI

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

Read accessible always. DATA4

is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

174 Am79C978

BCR42: PCI DATA Register 5 (DATA5) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_S CAL E field of the P C MCR regi st er.

Since these two are read only, BCR42 provides a

means of programming them through the EEPROM.

The co ntents of th is reg ister are c opied i nto th e cor re-

sponding fields pointed with the DATA_SEL field set to

five. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D5_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offse t Regis ter 44 of t he PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

These bits are always read ac-

cessible. D5_SCALE is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit

7-0 DATA 5 These bits c orr es pon d to the P CI

DAT A re gi st e r (o f fs e t Re gi st e r 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

These bits are always read ac-

cessible. DATA5 is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR43: PCI DATA Register 6 (DATA6) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_S CAL E field of the P C MCR regi st er.

Since these two are read only, BCR43 provides a

means of programming them through the EEPROM.

The co ntents of th is reg ister are c opied i nto th e cor re-

sponding fields pointed with the DATA_SEL field set to

six. Bits 15-0 in this register are programmable through

the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D6_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (off set Reg ister 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

These bits are always read ac-

cessible. D6_SCALE is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit

7-0 DATA 6 These bits corr espon d to the P CI

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

These bits are always read ac-

cessible. DATA6 is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR44: PCI DATA Register 7 (DATA7) Alias

Note: This register is an alias of the DA TA register and

also of the DATA_S CAL E field of the P CMCR r eg ister.

Since these two are read only, BCR44 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

sponding fields pointed with the DATA_SEL field set to

seven. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D7_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (off set Reg ister 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

These bits are always read ac-

cessible. D7_SCALE is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7-0 DATA 7 These bits corr espon d to the P CI

DATA register (offset register 47

Am79C978 175

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

These bits are always read ac-

cessible. DATA7 is read only.

Cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR45: OnNow Pattern Matching Register 1

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 i s writt en and the PMAT_M O DE bi t is 0 ,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accesse d. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 m ust be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written unti l the write to BCR47 is com plete. The writ e

to BCR47 ca uses all 5 bytes (four byt es of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-8 PMR_B0 Pattern Match RAM Byte 0. This

byte is written into or read from

Byte 0 of the Pattern Match RAM.

These bits are r e ad a nd wri te ac -

cessible always. PMR_B0 is un-

defined after H_RESET, and is

unaffected by S_RES ET and th e

STOP bit.

7 PMAT_MODE Pattern Match Mode. Writing a 1

to this bit will enable Pattern

Match Mode and should only be

done after the Pattern Match

RAM has been programmed.

These bits are r e ad a nd wri te ac -

cessible always. PMAT_MODE is

reset to 0 after H_RESE T, and is

unaffected by S_RESET and the

STOP bit.

6-0 PMR_ADDR Pattern Match Ram Address.

These bits are the Pat tern Matc h

Ram address to be written to or

read from.

These bits are re ad a nd wri te a c-

cessible always. PMR_ADDR is

reset to 0 after H_RESET, an d is

unaffected by S_RESET and the

STOP bit.

BCR46: OnNow Pattern Matching Register 2

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). Wh en BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is writ ten and the PMAT_ MOD E bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be access ed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to B CR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written unti l the write to BCR47 is complete. The writ e

to BC R47 causes all 5 by tes (four b ytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 PMR_B2 Pattern Match RAM Byte 2. This

byte is written into or read from

Byte 2 of the Pattern Match RAM.

These bits are re ad a nd wri te a c-

cessible always. PMR_B2 is un-

defined after H_RESET, and is

unaffected by S_RESET and the

STOP bit.

7-0 PMR_B1 Pattern Match RAM Byte 1. This

byte is written into or read from

Byte 1 of Pattern Match RAM.

These bits are re ad a nd wri te a c-

cessible always. PMR_B1 is un-

176 Am79C978

defined after H_RESET, and is

unaffected by S_RES ET and th e

STOP bit.

BCR47: OnNow Pattern Matching Register 3

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 i s writt en and the PMAT_M O DE bi t is 0 ,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accesse d. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 m ust be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written unti l the write to BCR47 is com plete. The writ e

to BCR47 ca uses all 5 bytes (four byt es of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

When PMAT_M O DE i s 0, the contents of the wor d ad-

dresse d by bits 6:0 of B CR45 can be rea d by reading

BCR45-47 in any order.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-8 PMR_B4 Pattern Match RAM Byte 4. This

byte is written into or read from

Byte 4 of Pattern Match RAM.

These bits are r e ad a nd wri te ac -

cessible always. PMR_B4 is un-

defined after H_RESET, and is

unaffected by S_RES ET and th e

STOP bit.

7-0 PMR_B3 Pattern Match RAM Byte 3. This

byte is written into or read from

Byte 3 of Pattern Match RAM.

These bits are r e ad a nd wri te ac -

cessible always. PMR_B3 is un-

defined after H_RESET, and is

unaffected by S_RES ET and th e

STOP bit.

BCR48: LED4 Status

This register defines the functionality of LED4. LED4

will default to indicating the selected SPEED with Pulse

stretching enabled (d efau lt = 0082 h).

BCR48 con trols the function(s) that th e LED4 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED2 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED2 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM PREAD operation.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical val ue of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

Read acce ssible al ways. This bi t

is read only; writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET, or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s f als e (i .e., t he L ED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

Am79C978 177

the LED output will be a Totem

Pole outpu t and the ou tput value

will be the same polarity as the

LEDOU T status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

This bit is always read/write ac-

cessible. LEDPOL is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be g overned by the LE DOUT

and LEDPOL values.

This bit is always read/write ac-

cessible. LEDDIS is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a v alue of 1 is passe d

to the LEDOUT bit in this register

when the Am79C978 controller is

operating in 100 Mbps mode.

This bit is always read/write ac-

cessible. 100E is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

11-10 RES Reserved locations. Written and

read as zero s.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passed to the LE DOUT bit in

this register when Magic Packet

frame mode is enabled and a

Magic Packet frame is detected

on the network.

This bit is always read/write ac-

cessible. MPSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT sig nal w hen the A m7 9C97 8

controller is functioning in a Link

Pass sta te and full-dupl ex opera-

tion is enabled. When the

Am79C 978 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

This bit is always read/write ac-

cessible. FDLSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretche r.

This bit is always read/write ac-

cessible. PSE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 LNKSE Link Status Enable. When this bit

is set, a val ue of 1 w ill be pas sed

to the LEDOUT bit in this register

in Link Pass state.

This bit is always read/write ac-

cessible. LNKSE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

This bit is always read/write ac-

cessible. RCVME is cleared by

H_RESET an d is not affected by

178 Am79C978

S_RESET or setting the STOP

bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. XMTE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 POWER Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is set to 1 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 SPEED Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR49: PHY Select

This register defines which PHY will be able to send

and receive data over the MII interface. Bits 15:8 are

updated whe never the EEPROM is read, and bits 6:0

are updated only if bit 7 is cleared. The bits are defined

as follows:

Bit Name Description

15 PC_NET PCnet mode. This bit must al-

ways be set.

14-10 RES Reserved locations. These bits

must be written as zeros.

9-8 PHY_SEL_Default

PHY Select Default. These bits

store the desired default PHY.

These bits have no effect on the

operation of the device and are

provided only as a storage loca-

tion.

7 PHY_SEL_Lock

PHY Select Lock. Setting this bit

prevents the PHY_SEL bits from

being overwritten by subsequent

soft resets. The user may write

this bit at any time. It is cleared

during Pow er-On Res et.

6-2 RES Reserved. Must be written as

zero.

1-0 PHY_SEL PHY Select. These bits define the

active PHY as follows:

00 10BASE-T PHY

01 HomePNA PHY

10 External PHY

11 Reserved/Undefined

BCR50-BCR55: Reserve d Locations

These registers must be 00h.

Am79C978 179

1 Mbps HomePNA PHY Internal Registers

The registers of the HomePNA PHY are accessible via

the internal MII interface. This interface uses the MII

Control, Address, and Data Registers (BCR32,

BCR33, and BCR34) in the integrated PCnet controller

to control and co mmu ni ca te to the Hom eP N A PHY via

the MDC and MDIO signals.

See Table 46 through Table 63.

HPR0: HomePNA PHY MII Control (Register 0)

Table 46. HPR0: HomePNA PHY MII Control (Register 0)

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

MII_CONTROL

15 RESET 1 = RESET

0 = Normal operation

** Self Clearing R/W 0 0

14 Loopback 1 = MII Loopback enabled

0 = MII Loopback disabled R/W 0 0

13 Speed Selection 0 = 10 Mbps R 0 0

12 Auto-Negotiation Enabled 1 = Enabled

0 = Disabled R/W 0 0

11 Power Down 1 = Power down

0 = Normal operation

(This bit is mirrored in PHY Control bit 4) R/W 0 0

10 Isolate 1 = Electrically isolate PH Y from MII

0 = Normal operation R/W 1 1

9 Restart Auto-Negotiation 1 = Restart Auto-Negotiation

0 = Normal operation

** Self Clearing R/W 0 0

8 Duplex Mode 1 = Full-Duplex (for test purposes only)

0 = Half-Duplex R/W 0 0

7 Collision Test 0 = Disable COL test signal R/W 0 0

6:0 Reserved Write as 0, Ignore Read R/W 0 0

180 Am79C978

HPR1: HomePNA PHY MII Status (Register 1)

Table 47. HPR1: HomePNA PHY MII Status (Register 1)

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

MII_Status

15 100BASE-T4 0 = PHY not able to perform 100BASE-T4 R 0 0

14 100BASE-X Full-Duplex 0 = PHY not able to perform Full-Duplex

100BASE-X R00

13 100BASE-X Half-Duplex 0 = PHY not able to perform Half-Duplex

100BASE-X R00

12 10 Mbps Full-Duplex 0 = PHY not able to perform 10 Mbps in Full-

Duplex R00

11 10 Mbps Half-Duplex 1 = PHY able to per form 10 Mbps in Half-

Duplex R11

10:7 Reserved Reads will produce undefined results R

6 MF Preamble Suppressio n

1 = PHY will accept management frames with

Preamble suppressed

0 = PHY will not accept management frames

with Preamble suppressed

R11

5 Auto-Negotiation Complete 1 = Auto-Negotiation completed

0 = Auto-Negotiation not completed R00

4 Remote Fau lt 1 = Remote fault detected

0 = Normal operation R00

3Auto-Negotiation Ability 1 = PHY is able to perform Auto-Negotiation

0 = PHY is not able to perform Auto-Negotiation R00

2Link Status

1 = Link is up

0 = Link is down

This bit will be RESET (latched low and re-

enabled on Read) on the first occurrence of lost

link and will be SET after completion of valid

LINK process.

R00

1 Jabber Detect 1 = Jabber condition detected

0 = Normal operation R00

0 Extended Capability 1 = Extended Register Capability

0 = Basic Register Set Capability R11

Am79C978 181

HPR2 and HPR3: HomePNA PHY MII PHY ID

(Registers 2 and 3)

Table 48. HPR2 and HPR3: HomePNA PHY MII ID (Registers 2 and 3)

HPR4-HPR7: HomePNA PHY Auto-Negotiation

(Registers 4 - 7)

Table 49. HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7)

Reserved Registers: HPR8 - HPR15

These registers should be ignored when read and

should not be written to at any time.

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

MII_PHY_ID

15:0 PHY_ID MSB (31-16) Most significant bytes of the PHY_ID (Bits 3-18) R 0000 0000

MII_PHY_ID

15:10 PHY_ID LSB (15-10) IEEE Address (Bits 19-24) R 1A 1A

9:4 PHY_ID LSB (9-4) Manufacturer Model Number R 39 39

3:0 PHY_ID LSB (3-0) Revision Number R 0 0

Hex Mnemonic Description Read/

Write Default

Hex Soft

Reset

04 Auto-Negotiation Register 4 Advertisement R 0021 0021

05 Auto-Negotiation Register 5 Link Partner Ability R 0000 0000

06 Auto-Negotiation Register 6 Expansion R 0000 0000

07 Auto-Negotiation Register 7 Next Page R 0000 0000

182 Am79C978

HPR16: HomePNA PHY Control (Register 16)

Table 50. HPR16: HomePNA PHY Control (Register 16)

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

PHY_Control

15 Remote Command 1 = Ignore Remote Commands

0 = Normal operation R/W 0 0

14:12 Reserved Reads will produce undefined results R/W

11 Command Low Power 1 = Comman d low power

0 = Normal operation R/W 0 0

10 Command High Power 1 = Command high power

0 = Normal operation R/W 0 0

9 Command Low Speed 1 = Command low speed

0 = Normal operation R/W 0 0

8 Command High Speed 1 = Command high speed

0 = Normal operation R/W 0 0

7 Disable AID Negotiation 1 = Disable AID negotiation

0 = Normal operation R/W 0 0

6 Clear PHY-Event Counter 1 = Clear PHY event counter

0 = Normal operation R/W 0 0

5 Disable Squelch adaptation 1 = Disable Squelch adaptation

0 = Normal operation R/W 0 0

4 Power Down 1 = Power down

0 = Normal operation

(This bit is controlled by HPR0) R00

3 Reserved Reads will produce undefined results R

2 High S peed 1 = Set node to High speed

0 = Set node to Low speed R11

1High Power 1 = Set node to High power

0 = Set node to Low power R00

0 Reserved Reads will produce undefined results R/W

Am79C978 183

HPR17: HomePNA Status Control (Register 17)

Table 51. HPR17: HomePNA Status Control (Register 17)

HPR18 and HPR19: HomePNA PHY TxCOMM

(Registe rs 18 and 19)

Table 52. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19)

The 32-b it transmitted d ata field i s to be use d for out-

of-band communication between PHY management

entities . No protocol for out-of-b and manageme nt has

been defined. Accessing the low word causes the PHY

to send all -0 PCOMs until th e high word has be en ac-

cessed. Once accessed, the next transmitted packet

will cause this register’s contents to be shifted out in

the PC OM field of the transmi tted pa cket. Upon tr ans-

mission, this register will read back as all 0s. A non-null

transmitted PCOM will set the TxPCOM Ready bit in

the Event Status Register (Register HPR26). An ac-

cess to any of the two TxPCOM words will clear the Tx-

PCOM Ready bit in the ISTAT register.

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

15:13 Reserved Reads will produce undefined results;

Writes = 0 R/W

12 Any1home 1 = Any1Home Link Packet Disable

0 = Any1Home Link Packet Enable R/W 0

11:7 Reserved Reads will produce undefined results;

Writes = 0 R/W

6 Received_Power 1 = Last packet received was sent at high power

0 = Last pa cket rece ived was se nt at low po wer R0

5 Received_Speed 1 = Last packet received was sent at high power

0 = Last pa cket rece ived was se nt at low po wer R0

4 Received_Ver 1 = Last packet received was sent at Version

XX R0

3:0 Reserved Reads will produce undefined results;

Writes = 0 R/W

Hex Mnemonic Description Read/

Write Default

Hex Soft

Reset

12-13 PHY_TX_COMM (4) The 32-bit preamble transm itte d on the

HomePNA PHY. Register 12 cont ains the high

word and Register 13 the low word. R/W All 0s All 0s

184 Am79C978

HPR20 and HPR21: HomePNA PHY RxCOMM

(Registe rs 20 and 21)

Table 53. HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21)

The 32-bit received data field to be used for out-of-

band co mmu nication betwe en P HY manageme nt enti-

ties. No protocol for out-of-band management has

been defined. Accessing the low word of the register is

sufficient to ensure that subsequently received packets

will not ov er-write the re gister contents . A non-null re-

ceived PCOM will set the RxPCOM Valid bit of the

Event Status Register (Register HPR26). Accessing

the high wo rd of the regis ter clears this b it and allows

over-writing of the register by subsequent received

packets.

HPR22: HomePNA PHY AID (Register 22)

Table 54. HPR22: HomePNA PHY AID (Register 22)

The PHY’s AID ad dres s i s used for c ol lisi on dete ct ion .

Unless bit 7 of th e CONTROL registe r is set, the PHY

is assu red to selec t a unique AID ad dress. Addresses

above EFh are reserved. Address FFh is defined to in-

dicate a remote command.

HPR23: HomePNA PHY Noise Control (Register 23)

Table 55. HPR23: HomePNA PHY Noise Control (Register 23)

Hex Mnemonic Description Read/

Write Default

Hex Soft

Reset

14-15 PHY_RX_COMM (4) The 32-bit preamble receiv ed on the

HomePNA PH Y. Register 14 contains the high

word and Register 15 the low word. R All 0s All 0s

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

PHY_AID

15:8 PHY_AID The Address ID of this PHY

If PHY_Control Disable AID Negotiation is not

set then writes to this bit will have no effect. R/W 00 00

7:0 Noise Events

An 8-bit counter that records the number of

noise events detected. Overflows are held as

FFh. Can be cleared by setting bit 6 of the

control register.

R/W 00 00

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

PHY_NOISE_CTRL1

15:8 Noise Floor The minimum value of the NOISE

measurement. R/W 03 03

7:0 Noise Ceiling The maximum value if the NOISE

measurem ent. If it is excee ded, NOISE is res et

to the FLOOR. R/W FF FF

Am79C978 185

HPR24: HomePNA PHY Noise Control 2 (Register

24)

Table 56. HPR24: HomePNA PHY Noise Control 2 (Register 24)

HPR25: HomePNA PHY Noise Statistics (Register

25)

Table 57. HPR25: HomePNA PHY Noise Statistics (Register 25)

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

PHY_NOISE_CTRL2

15:8 Noise Attack

Sets the attack characteristics of the NOISE

algorithm. High nibble sets number of noise

events needed to raise the NOISE level

immedia tely, whi le the low nibbl e is the numbe r

of noise events need ed to ra ise the le vel a t the

end of an 870 ms period.

R/W F4 F4

7:0 Reserved Reads will produce undefined results R

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

PHY_NOISE_STAT

15:8 Noise Level

This is the digital value of the

SLICE_LVL_NOISE output. It is effectively a

measure of the noise level on the wire and

tracks noise by counting the number of false

trigger s of the NOISE compar ator in an 80 0 ms

window . When auto-adaptation is enabled (bit 5

of the PHY_Control Register is false), this

count every 50 ns. When adaptation is

disabled, this register may be written to and is

used to genera te both the SLICE_LVL_NOISE

and SLICE_LVL_DATA signals.

R/W 03 03

7:0 Peak Level This is a me asu r ement of the peak lev el of the

last valid (non -co lli si on) AID receive d. R/W FF FF

186 Am79C978

HPR26: HomePNA PHY Event Status (Register 26)

Table 58. HPR26: HomePNA PHY Event Status (Register 26)

HPR27: HomePNA PHY Event Status (Register 27)

The Event Status register reports the state of each

event source. Any bit may be written and so facilitate

software-stimulated event testing.

Table 59. HPR27: HomePNA PHY Event Status (Register 27)

HPR28: HomePNA PHY ISBI Control (Register 28)

Table 60. HPR8: HomePNA PHY ISBI Control (Register 28)

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

PHY_Event Status

15:10 Reserved R00

9RxPCOM Indicates a valid RxPCOM. An access to the

RxCOM MSB Register 21 will clear this bit. R00

8TxPCOM Indicates a va lid TxPCOM. An y a cc es s to the

TxCOM registers (Registers 18 and 19) will

clear this bit. R00

7:4 Reserved Reads will produce undefined results. R

3 Packet Received Status is cleared by writing a 0. R/W 0 0

2 Packet Transmitted Status is cleared by writing a 0. R/W 0 0

1 Remote Command Received A valid remot e comm and was received.

Status is cleared by writing a 0. R/W 0 0

0 Remote Command Sent A remote command has been sent.

Status is cleared by writing a 0. R/W 0 0

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

AID_CTRL

15:8 AID_INTERVAL Thi s value d efines the number of TCLKs (116.6

ns) separating AID symbols. R/W 14 14

7:0 AID_ISBI This value defi nes the nu mber of TCLKs (1 16.6

ns) separating AID symbol 0. R/W 40 40

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

ISBI_CTRL

15:8 ISBI_SLOW This value defines the nu mber of TCLKs (1 16 .6

ns) separat ing data pulses for Sy mb ol 0 i n low

speed mode. R/W 2C 2C

7:0 ISBI_FAST This value defines the numb er of TCLKs (1 16.6

ns) separa ting data puls es for Symbol 0 in high

speed mode. R/W 1C 1C

Am79C978 187

HPR29: HomePNA PHY TX Control (Register 29)

Table 61. HPR29: HomePNA PHY TX Control (Register 29)

HPR30: 1 Mbps HomePNA PHY Drive Level Control

Test Register (Register 30)

Table 62. HPR30: HomePNA PHY Drive Level Control Test Register (Register 30)

HPR31: 1 Mbps HomePNA PHY Analog Control

Regist er (Register 31)

Table 63. HPR31: HomePNA PHY Analog Control Register (Register 31)

Note: 1. Writes to these bits will cause undefined functionality.

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

TX_CTRL

15:8 TX_PULSE_WIDTH

This value defines the duration of a transmit

pulse in OSC cycles (16.7 ns). This will

ef fect iv el y dete rmi ne the tran sm it spe ctrum of

the PHY.

R/W 04 04

7:4 TX_PULSE_CYCLES_N This value defines the number of pulses that

will be driven onto the HRTXRX_N pin. R/W 4 4

3:0 TX_PULSE_CYCLES_P This value defines the number of pulses that

will be driven onto the HRTXRX_P pin. R/W 4 4

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

15:12 RES Reserved; Write = 0; Read = X R YX

11:6 High Level Control Defines the dri ve level that will be util ized in the

High Power mode. R/W 15

5:0 Low Level Contro l Defines the dri ve level that wi ll be utilize d in the

Low Power mode. R/W 09

Bits Mnemonic Description Read/

Write Default

Hex Soft

Reset

15:11 Level_Adjust

Global output slope adjustment. These bits

control the number of current sources enable

for transmit. Eac h bit represents a single

current source. Thus 10101 enables three

current sources as does 11100.

R/W 18 18

10:8 Reserved Reserved; Write = 0 R/W 0 0

7 Force_Link_Valid 1 = Link Status bit will be held valid

0 = Normal operation R/W 0 0

6:0 Reserved Reserved; Write = 0 R/W 0 0

188 Am79C978

10BASE-T PHY Management Registers

(TBRs)

The Am7 9C978 h ome netw orking device s uppor ts the

MII basic register set and extended register set. Both

sets of registers are accessible through the PHY Man-

agemen t Interfac e. As spec ified in the IEEE standard ,

the basic register set consists of the Control Register

(Regist er 0) and the Sta tus Register (Register 1 ). The

extended register set consists of Registers 2 to 31

(decimal).

Ta ble 64 lis ts all the 10BAS E-T r egister s impl emente d

in the device. All the reserved registers should not be

written to, and reading them will return a zero value.

T able 64. Am79C978 10BASE-T PHY Management

Reg ister Set

Address

(in Decimal) Register Name Basic/

Extended

0 PHY Control B

1PHY StatusB

2-3 PHY Identifier E

4Auto-Negotiation

Advertisement E

5Auto-Negotiation Link

Partner Ability E

6Auto-Negotiation

Expansion E

7Auto-Negotiation Next

Page E

8-15 Reserved E

16 Interrupt Enable and

Status E

17 PHY Control/Status E

18 Reserved E

19 PHY Management

Extension E

20-23 Reserved E

24 Summary Status E

25-31 Reserved E

Am79C978 189

TBR0: 10BASE-T PHY Control Register (Register 0)

Table 65. TBR0: 10BASE-T PHY Control Register (Register 0)

Notes:

1. R/W = Read/Write, SC = Self Clearing, RO = Read only.

2. Soft Reset does not reset the PDX block. Refer to the Soft Reset Section for details.

3. Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1).

4. If the ISOL pin of the chip and the Isolate bit in Register 0 is 1, this bit will be set.

Reg Bits Name Description Read/Write

(Note 1) Default

Value Soft

Reset

0 15 Soft Reset (Note 2)

When write: 1 = PHY software reset,

0 = normal operation.

When read: 1 = reset in process,

0 = reset done.

R/W, SC 0 0

014 Loopback 0 = asserts Loopback mode,

1 = deasserts Loopback mode R/W 0 0

013Speed Selection

(Not e 3) 1 = 100 Mbps,

0 = 10 Mbps R/W 1 1

012Auto-Negotiation

Enable 1 = enable Auto-Negotiation,

0 = disable Auto-Negotiation R/W 1 1

0 11 Power Down 1 = power down,

0 = normal operation R/W 0 0

010 Isolate

(Not e 4) 1 = electrically isolate PHY

0 = normal operation R/W 1 1

09 Restart Auto-

Negotiation 1 = restart Auto-Negotiation,

0 = normal operation R/W, SC 0 0

08 Duplex Mo de

(Not e 3) 1 = Full-Duplex,

0 = Half-Duplex R/W 1 Retains

value

0 7 Collision Test 1 = enable COL signal test,

0 = disable COL signal test R/W 0 0

0 6-0 Reserved Write as 0, ignore on read RO 0 0

190 Am79C978

TBR1: 10BASE-T Status Register (Register 1)

The Status Register identifies the physical and Auto-

negotiation capabilities of the local PHY. This register is

read only; a write will have no ef fect.

Table 66. TBR1: 10BASE-T PHY Status Register (Register 1)

Note:

1. LH = Latching High, LL = Latching Low.

Bits Name Description Read/Write

(Note 1) Default

Value

15 100BASE-T4 1 = 100BASE-T4 able,

0 = not 100BASE-T4 able RO 0

14 100BASE-X Full-Duplex 1 = 100BASE-X full- duplex able,

0 = not 100BASE-X full-duplex able RO 0

13 100BASE-X Half-Duplex 1 = 100BASE-X half-duplex able,

0 = not 100BASE-X half-duplex able RO 0

12 10 Mbps Full-Duplex 1 = 10 Mbps full-duplex able,

0 = not 10 Mbps fu ll-dupl ex able RO 1

11 10 Mbps Half-Duplex 1 = 10 Mbps half-duplex able,

0 = not 10 Mbps half-d uplex able RO 1

10-7 Reserved Ignore when read RO NA

6 MF Preamble Suppression

1 = PHY can accept management (mgmt)

frames with or without preamble, 0 = PHY

can only accept mgmt frames with

preamble

RO 1

5 Auto-Negotiation Complete 1 = Auto-Negotiation completed,

0 = Auto-Negotiation not completed RO 0

4 Remote Fault 1 = remote fault detected,

0 = no remote fault detected RO, LH 0

3 Auto-Negotiation Ability 1 = PHY able to auto-negotiate,

0 = PHY not able to auto-negotiate RO 1

2Link Status 1 = link is up,

0 = link is down RO, LL 0

1 Jabber Detect 1 = jabber condition detected,

0 = no jabber condition detected RO 0

0 Extended Capability 1 = extended register capabilities,

0 = basic register set capa bilities only RO 1

Am79C978 191

TBR2 and TBR3: 10BASE-T PHY Identifier

(Registers 2 and 3)

Registers 2 and 3 contain a unique PHY identifier, con-

sisting of 22 bits of the organizationally unique IEEE

Identif ier, a 6-bit manufacture r’s m odel number, and a

4-bit manufacturer’s revision number . The most signifi-

cant bit of the P HY identifi er is bit 15 of re gister 2; the

least sig nificant bit of the PHY identifie r is bit 0 of reg-

ister 3. Register 2, bit 15 corresponds to bit 3 of the

IEEE Identifier a nd register 2, bit 0 corresponds t o bit

18 of the IEEE Identifier . Register 3, bit 15 corresponds

to bit 19 of the IEEE Identifier and register 3, bit 10 cor-

responds to bit 24 of the IEEE Identifier . Register 3, bits

9-4 cont ain the m anu fac turer ’s model number and bits

3-0 contain the manufacturer’s revision number . These

registers are shown in Table 67 and Table 68.

Table 67. TBR2: 10BASE-T PHY Identifi er (Regist er 2)

Table 68. TBR3 : 10BASE-T PHY Identifi er (Register 3)

Bits Name Description Read/

Write Default Value Soft Reset

15-0 PHY_ID[31-16] IEEE Address (bits 3-18); Register

2, bit 15 is MS bit of PHY Identifier RO 0000000000000000

(0000 Hex) Retains original

Value

Bits Name Description Read/Write Default Value Soft Reset

15-10 PHY_ID[15-10] IEEE Address (bits 19-

24) RO 011010

(1A Hex) Retains original value

9-4 PHY_ID[9-4] Manufacturer’s Model

Number (bit s 5-0) RO 110111

(37 Hex) Retains original value

3-0 PHY_ID[3-0] Revision Number (bits

3-0); Register 3, bit 0 is

LS bit of PHY I dentifi er RO 0000 Retains original value

192 Am79C978

TBR4: 10BASE-T Auto-Negotiation Advertisement

Regist er (Register 4)

This register contains the advertised ability of the

Am79C978 home networking device. The purpose of

this register is to advertise the technology ability to the

link partner device. See Table 69.

When this register is modified, Restart Auto-

Negotiation (Register 0, bit 9) must be enabled to guar-

antee the change is implemented.

Table 69. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4)

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 Next Page When set, the de vice wi shes to en gage in ne xt page ex change. If

clear, the dev ice does not wis h to engage in next page exchange . R/W 0

14 Reserved RO 0

13 Remote Fault

When set, a remote fault bit is inserted into the base link code

word during the Auto Negotiation process. When cleared, the

base link code work will have the bit position for remote fault as

cleared.

R/W 0

12:11 Reserved RO 0

10 P AUSE This bit sh ould be set if t he P AU SE capability is to be adve rtised. R/W 0

9 Reserved RO 0

8Full-Duplex -

100BASE-TX This bit advertises Full-Duplex capability. When set, Full-Duplex

capability is advertised. When cleared, Full-Duplex capability is

not advertised. R/W 0

7Half-Duplex -

100BASE-TX Th is bit adv ertises Half -Duplex capabi lity for the Au to-negotia tion

process. Setting this bit advertises Half-Duplex capability.

Clearing this bit does not advertise Half-Duplex capability. R/W 0

6Full-Duplex -

10BASE-T This bit advertises Full-Duplex capability. When set, Full-Duplex

capability is advertised. When cleared, Full-Duplex capability is

not advertised. R/W 1

5Half-Duplex -

10BASE-T This bit a dvertises Half -Duplex capability fo r the Auto-nego tiation

process. Setting this bit advertises Half-Duplex capability.

Clearing this bit does not advertise Half-Duplex capability. R/W 1

4:0 Selector Field The Am79C978 home networking device is an 802.3 compliant

device RO 0x01

Am79C978 193

TBR5: 10BASE-T Auto-Negotiation Link Partner

Ability Register (Register 5)

The Auto-Negotiation Link Partner Ability Register is

Read Only. T he regi ster con tains the adverti sed ability

of the link partne r. The bit defin itions repr esent the re-

ceived link code word. This register contains either the

base page o r the link partne r’s nex t pages. See Table

70 and Table 71.

Table 70. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page Format

Table 71. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page Format

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 Next Page Link partner next page request RO 0

14 Acknowledge Link partner acknowledgment RO 0

13 Remote Fault Link partner remote fault request RO 0

12:5 Technology Ability Link partner technology ability field RO 0

4:0 Selector Field Link partner selector field RO 0

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 Next Page Link partner next page request RO 0

14 Acknowledge Link partner acknowledgment RO 0

13 Message Page Link partner message page request RO 0

12 Acknowledge 2 1 = Link partner can comply with the request

0 = Link partner cannot comply with the request RO 0

11 Toggle Link partner toggle bit RO 0

10:0 Message Field Link partner’s message code RO 0

194 Am79C978

TBR6: 10BASE-T Auto-Negotiation Expansion

Regist er (Register 6)

The Auto-Negotiation Expansion Register provides ad-

ditional information which aids the Auto-Negotiation

process. The Auto-Negotiation Expansion Register bits

are Read Only. See Table 72.

Table 72. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6)

TBR7: 10BASE-T Auto-Negotiation Next Page

Regist er (Register 7)

The Auto-Negotiation Next Page Register contains the

next page link code word to be transmitted. On power-

up the default value of 2001h represents a message

page with the message code set to null. See Table 73.

Table 73. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7)

Reserved Registers (Registers 8-15, 18, 20-23, and

25-31)

The Am79C978 home networking device contains re-

served registers at addresses 8-15, 18, 20-23, and 25-

31. The se regist ers sh ould be i gnored when read an d

should not be written at any time.

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15:5 Reserved RO 0

4Parallel Detection

Fault 1=Parallel detection fault

0=No parallel detection fault RO, L H 0

3Link Partner Next

Page Able 1 = Link partner is next page able

0 = Link partner is not next page able RO 0

2 Next Page Able

1 = Am79C978 home networking device channel is next page

able

0 = Am79C978 home networking device channel is not next page

able

RO 1

1 Page Received 1 = A new page has been received

0 = A new page has not been received RO, LH 0

0Link Partner ANEG

Able 1 = Link partner is Auto-Negotiation able

0 = Link partner is not Auto-Negotiation able RO 0

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 N ex t Page Am79C978 ho me networking de vi ce cha nnel next p age requ es t R/W 0

14 Reserved RO 0

13 Message Page Am79C978 home networking device channel message page

request R/W 1

12 Acknowledge 2

1 = Am79C978 home networking device channel can comply with

the requ est

0 = Am79C9 78 hom e network ing dev ice chan nel canno t comp ly

with the request

R/W 0

11 Toggle Am79C978 home netw orking device channel toggle bit RO 0

10:0 Message Field Message code field R/W 0x001

Am79C978 195

TBR16: 10BASE-T INTERRUPT Status and Enable

Regist er (Register 16)

The Interrupt bits indicate when there is a change in the

Link Stat us, Duplex Mo de, Auto-Negoti ation status , or

Speed status. Register 16 contains the interrupt status

and interrupt enable bits. The status is always updated

whether or not the inter rupt enable bits are se t. When

an interrupt occurs, the system will need to read the in-

terrupt register to clear the status bits and determine

the course of action needed. See Table 74.

Table 74. TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16)

Note:

1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15:14 Reserved RO 0

13 Interrupt Test Enable

(Not e 1)

1 = When this bit is set, setting bits 12:9 of this register

will cause a condition that will set bits 4:1

accordin gly . Th e eff ect is to t est the regi ster bits w ith

a forced interrupt condition.

0 = Bits 4:1 are only set if the interrupt condition (if any

bits in 12:9 are set) occurs.

R/W 0

12 Link Status Chang e

Enable 1 = Link Status Change enable

0 = This interrupt is masked R/W 0

11 Duplex Mo de Change

Enable 1 = Duplex Mode Change enable

0 = This interrupt is masked R/W 0

10 Auto-Neg Chan ge

Enable 1 = Auto-Negotiation Change enable

0 = This interrupt is masked R/W 0

9Speed Change

Enable 1 = Speed Change enable

0 = This interrupt is masked R/W 0

8Global

Enable 1= Global Interrupt enable

0 = This interrupt is masked R/W 0

7:5 Reserved RO 0

4 Link Status Change 1 = Link Status h as changed on a port

0 = No change in Link Status RO,

LH 0

3 Duplex Mode Change 1 = Duplex Mode has changed on a port

0 = No change in Duplex mode RO,

LH 0

2 Auto-Negotiation Change 1 = Auto-Neg status has changed on a port

0 = No change in Auto-Neg status RO,

LH 0

1 Speed Change 1 = Speed status has changed on a port

0 = No change RO,

LH 0

0Global 1 = Indicates a change in status of any of the above

interrupts

0 = Indicates no change in Interrupt Status

RO,

LH 0

196 Am79C978

TBR17: 10BASE-T PHY Control/Status Register

(Register 17)

This regi ster is used to control the co nfigurati on of th e

10 Mbps PHY unit of the Am79C978 home networking

device. See Table 75.

Table 75. TBR17: 10BASE-T PHY Control/Status Register (Register 17)

Note:

1. For these loopback paths, the data is also transmitted out of the MDI pins (TX±).

Bits Name Description Read/Write H/W

Reset Soft Reset

15 Reserved R/W 0 Retains

Value

14 Reserved R/W 0 Retains

Value

13 Force Link Good

Enable 1 = link status forced to link up state

0 = link status is determined by the device R/W 0 0

12 Disable Link Pulse 1 = Link pulses sent from the

10BASE-T transmitter are suppressed R/W 0 0

11 SQE_TEST Disable

1 = Di sable s the SQE h eartbea t which occu rs

after each 10BASE-T transmission

0 = The heart beat assertion occurs on the

COL pin approximately 1 µs after transmission

and for a duration of 1 µs.

R/W 0 0

10 Reserved R/W 0 0

9 Jabber Detect Disable 1 = disable jabber detect

0 = enable jabber detect R/W 0 0

8:7 Reserved R/W 00 00

6Receive Polarity

Reversed

1 = Receive pol arity of the 10BASE-T receiver

is reversed

0 = Receive polarity is correct RO 0 0

5Auto Receive Pol arity

Correcti on Disa bl e

1 = polarity correction circuit is disabled for

10BASE-T

0 = Self correcting polarity circuit is enabled R/W 0 0

4Extended Distance

Enable

1 = 1 0BASE-T receive squelch thresholds are

reduced to allow reception of frames which are

greater than 100 meters

0 = Squelch thresholds are set for standard

distanc e of 100 met ers

R/W 0 0

3TX_DISABLE 1 = T X± outputs no t active for 10BASE -T. TX±

outputs to logical “0” for PECL.

0 = Transmit valid data R/W 0 0

2 TX_CRS_EN

1 = C RS i s as sert ed w hen t r ans mi t o r re ce iv e

medium is active

0 = CRS is asserted whe n receive mediu m is

active

RO 0 0

1 Reserved RO 0 0

0 PHY Isolated 1 = Internal PHY is isolated

0 = Internal PHY is enabled RO 0/1 0/1

Am79C978 197

TBR19: 10BASE-T PHY Management Extension

Regist er (Register 19)

Table 76 contains the PHY Management Extension

Table 76. TBR19: 10BASE-T PHY Management Extension Register (Register 19)

Reserved Register: 10BASE-T Configuration

Regist er (Register 22)

This register is reserved.

Reserved Register: 10BASE-T Carrier Status

Regist er (Register 23)

This register is reserved.

TBR24: 10BASE-T Summary Status Register

(Register 24)

The Sum mary Status r egister is a gl obal register con-

taining status information. This register is Read/Only

and represents the most important data which a single

ister indicates the following: Link Status, Full-Duplex

Status, Auto-Negotiation Alert, and Speed. See Table

77.

Table 77. TBR24: 10BASE-T Summary Status Register (Register 24)

Bits Name Description Read/Write Default Value Soft Reset

15:6 Reserved Write as 0; ignore on read RO 0 0

5 Mgmt Frame Format 1 = last management frame was

invalid (opcode error, etc.) 0 = last

management frame was valid RO 0 0

4-0 PHY Address PHY Address defaults to 11110 RO 11110 Retains

Previous Value

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15-4 Reserved Write as 0; Ignore on Read 0 0

3Link Status

1 = Link Status is up

0 = Link Status is down R/O 0

2 Full-Duplex Operatin g in Full-D uplex mode

Operating in Half-Duplex mode R/O 0

1AutoNEG

Alert 1 = AutoNEG status has changed

0 = AutoNEG status unchanged R/O 0

0 Speed 1 = Operating at 100 Mbps

0 = Operating at 10 Mbps R/O 0

198 Am79C978

Initialization Block

Note: When SSIZE32 (BCR20, bit 8) is set to 0, the

software structures are defined to be 16 bits wide. The

base address of the initialization block must be aligned

to a DWord boundary, i.e., CSR1, bit 1 a nd 0 must be

cleared to 0. When SSIZE32 is set to 0, the initialization

block looks like Table 78.

Note: The Am79 C978 controller performs DWord ac -

cesses to read the initialization block. This statement is

always true, regardless of the setting of the SSIZE32

bit.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide. The base ad-

dress of the initialization block must be aligned to a

DWord boundary, i.e., CSR1, bits 1 and 0 must be

cleared to 0. When SSIZE32 is set to 1, the initialization

block looks like Table 79.

RLEN and TLEN

When SSIZE32 (BCR20, bit 8) is set to 0, the software

structures are defined to be 16 bits wide, and the RLEN

and TLEN fields in the initialization block are each three

bits wide. The values in these fields determine the num-

ber of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is shown in T able 80. If a value other than those

listed in Table 80 is desired, CSR76 and CSR78 can be

written after initialization is complete.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide, and the RLEN

and TLEN fields in the initialization block are each 4 bits

wide. The values in these fields determine the number

of trans mit and rec eive Desc riptor Rin g Entries (DRE)

which are u sed in the descriptor rings. Their mea ning

is shown in Table 81.

Table 78. Initialization Block (SSIZE32 = 0)

Address Bits 15-13 Bit 12 Bits 11-8 Bits 7-4 Bits 3-0

IADR+00h MODE 15-00

IADR+02h PADR 15-00

IADR+04h PADR 31-16

IADR+06h PADR 47-32

IADR+08h LADRF 15-00

IADR+0Ah LADRF 31-16

IADR+0Ch LADRF 47-3 2

IADR+0Eh LADRF 63-48

IADR+10h RDRA 15-00

IADR+12h RLEN 0RES TDRA 23-16

IADR+14h TDRA 15-00

IADR+16h TLEN 0RES TDRA 23-16

Table 79. Initialization Block (SSIZE32 = 1)

Address Bits Bits Bits Bits Bits Bits Bits Bits

31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

IADR+00h TLEN RES RLEN RES MODE

IADR+04h PADR 31-00

IADR+08h RES PADR 47-32

IADR+0Ch LADRF 31-00

IADR+10h LADRF 63-32

IADR+14h RDRA 31-00

IADR+18h TDRA 31-0 0

Am79C978 199

If a value other than those listed in Table 80 is desired,

CSR76 a nd CS R78 can b e wr it ten a fter i nit ial izati on is

complete.

RDRA and TDRA

RDRA and TDRA indicate where the transmit and re-

ceive descriptor rings begin. Each DRE must be located

at a 16-byte address boundary when SSIZE32 is set to

1 (BCR20, bit 8). Each DRE must be located at an 8-

byte address boundary when SSIZE32 is set to 0

(BCR20, bit 8).

LADRF

The Logical Address Filter (LADRF) is a 64-bit mask

that is used to accept incoming Logical Addresses. If

the first bit in the in coming add ress (as tr ansmitted on

the wire) is a 1, it indicates a logical address. If the first

bit is a 0, it is a physical address and is compared

against the physical address that was loaded throug h

the initialization block.

A logical address is passed through the CRC generator,

producing a 32-bit result. The high order 6 bits of the

CRC is used to select one of the 64 bit positions in the

Logical Address Filter . If the selected filter bit is set, the

address is accepted and the frame is placed into mem-

ory.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message may

be intend ed for the no de. It i s the node’s responsib il ity

to determine if the message is actually intended for the

node by comparing the destination address of the stored

message with a list of acceptable logical addresses.

If the Logical Address Filter is loaded with all zeros and

promiscuous mode is disabled, all incoming logical ad-

dresses except broadcast will be rejected. If the

DRCVBC bit (CSR15, bit 14) is set as well , the broad-

cast packets will be rejected. See Figure 51.

PADR

This 48-bit value repre sents the unique node add ress

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. P A DR[0] is com-

pared with the first bit in the destination address of the

incoming frame. It must be 0 since only the destination

address of a unicast frames is compared to PADR. The

six hex-digit nomenclature used by the ISO 8802-3

(IEEE/ ANS I 80 2.3 ) map s t o th e Am79C978 ho me n et-

working PADR register as follows: the first byte is com-

pared with PADR[7:0] with PADR[0] being the least

significant bit of the byte. The second ISO 8802-3

(IEEE/ANSI 802.3) byte is compared with PADR[15:8],

again from the least significant bit to the most signifi-

cant bit, and so on. The sixth byte is compared with

PADR[47:40], the least significant bit being PADR[40].

Mode

The mode register field of the initialization block is cop-

ied into CSR15 and interpreted according to the de-

scription of CSR15.

Table 80. R/TLEN Decoding (SSIZE32 = 0)

R/TLEN Number of DREs

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

Table 81. R/TLEN Decoding (SSIZE32 = 1)

R/TLEN Number of DREs

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

11XX 512

1X1X 512

200 Am79C978

Figure 51. Address Match Logic

Recei ve De sc ript ors

When SWSTYLE (BCR20, bits 7-0) is set to 0, then the

software structures are defined to be 16 bits wide, and

receive descriptors look like Table 82 (CRDA = Current

Rece ive Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the

software structures are defined to be 32 bits wide, and

receive descriptors look like Table 83 (CRDA = Current

Receive Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the

software structures are defined to be 32 bits wide, and

receive descriptors look like Table 84 (CRDA = Current

Receive Descriptor Address).

Table 82. Receive Descriptor (SWSTYLE = 0)

1CRC

GEN

SEL

31 26

MUX

63 0

Match = 1 Packet Accepted

Match = 0 Packet Rejected

Match

Logical

Address Filter

(LADRF)

32-Bit Resultant CRC

Received Message

Destination Address

22206B-54

Address 15 14 13 12 11 10 9 8 7-0

CRDA+00h RBADR[15:0]

CRDA+02h OWN ERR FRAM OFLO CRC BUFF STP ENP RBADR[23:16]

CRDA+04h 1111 BCNT

CRDA+06h 0000 MCNT

Table 83. Receive Descriptor (SWSTYLE = 2)

Address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0

CRDA+00h RBADR[31:0]

CRDA+04h OWN ERR FRA

MOFL

OCRC BUF

FSTP ENP BPE PAM LAFM BAM RES 1111 BCNT

CRDA+08h RES RFRTAG[14:0] 0000 MCNT

CRDA+0Ch USER SPACE

Table 84. Receive Descriptor (SWSTYLE = 3)

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-0

CRDA+00h RES RES RES 0000 MCNT

CRDA+04h OWN ERR FRAM OFLO CRC BUFF STP ENP BPE RES 1111 BCNT

CRDA+08h RBADR[31:0]

CRDA+0Ch USER SPACE

Am79C978 201

RMD0

Bit Name Description

31-0 RBADR Receive Buffer address. This field

contains the address of the

receive buffer that is associated

with this descriptor.

RMD1

Bit Name Description

31 OWN This bit indicates whether the de-

scriptor entry is owned by the

host (OWN = 0) or by the

Am79C978 controller (OWN = 1).

The Am79C978 controller clears

the OWN bit after filling the buffer

that the descriptor points to. The

host sets the O WN bit afte r emp-

tying the buffer.

Once the Am79C978 controller or

host has relinquished ownership

of a buffer, it must not change any

field in the descriptor entry.

30 ERR ERR is the OR of FRAM, OFLO,

CRC, BUFF, or BPE. ERR is set

by the Am79C978 controller and

cleared by the host.

29 FRAM Framing error indicates that the

incoming frame contains a non-

integer multiple of eight bits and

there was an FCS error. If there

was no FCS error on the incom-

ing frame, then FRAM will not be

set even if there was a non-

integer multiple of eight bits in the

frame. FRAM is not valid in inter-

nal loopback mode. FRAM is val-

id only when ENP is set and

OFLO is not. FRAM i s set by the

Am79C978 controller and

cleared by the host.

28 OFLO Overflow error indicates that the

receiv er h as lo st all or part of the

incoming frame, due to an inabili-

ty to move data from the receive

FIFO into a memory buffer before

the internal FIFO overflowed.

OFLO is set by the Am79C978

controller and cleared by the

host.

27 CRC CRC indicates that the receiver

has detected a CRC (FCS) error

on the incoming frame. CRC is

valid only when ENP is set and

OFLO is not. CRC is set by the

Am79C978 controller and

cleared by the host. CRC will also

be set when Am79C978 home

networking receives an RX_ER

indication from the external PHY

through the MII.

26 BUFF Buffer error is set any time the

Am79C978 controller does not

own the next buffer while data

chaining a received frame. This

can occur in either of two ways:

1. The OWN bit of the next buffer

is 0.

2. FIFO overflow occurred before

the Am79C9 78 control ler was

able to read the OWN bit of

the next descriptor.

If a Buffer Error oc curs, an Over-

flow Error may also occur inter-

nally in the FIFO, but will not be

reported in the descriptor status

entry unless both BUFF and

OFLO errors occur at the same

time. BUFF is set by the

Am79C978 controller and

cleared by the host.

25 STP St art of Packet i ndicates that th is

is the first buffer used by the

Am79C978 controller for this

frame. If STP and ENP are both

set to 1, the frame fits into a single

buffer. Otherwise, the frame is

spread over more than one buff-

er. When LAPPEN (CSR3, bit 5)

is clea red to 0, STP is se t by th e

Am79C978 controller and

cleared by the host. When LAP-

PEN is set to 1, STP mu st be set

by the host.

24 ENP End of Packet indicates that this

is the last buffer used by the

Am79C978 controller for this

frame. It is used for data chaining

buffers . If bo th ST P a nd E NP are

set, the frame fits into one buffer

and there is no data chaining.

ENP is set by the Am79C978

controller and cleared by the

host.

202 Am79C978

23 BPE Bus Parity Error is set by the

Am79C978 controller when a par-

ity error occurred on the bus inter-

face during data transfers to a

receive buffer. BPE is valid only

when ENP, OFLO, or BUFF are

set. The Am79C978 controller will

only set BPE when the advanced

parity error handling is enabled

by setting APERREN (BCR20, bit

10) to 1. BPE is set by the

Am79C978 controller and

cleared by the host.

This bit does not exist when the

Am79C978 controller is pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

22 PAM Physical A ddr ess Ma tch i s se t by

the Am79C978 controller when it

accepts the received frame due

to a match of the frame’s destina-

tion address with the content of

the physical address register.

PAM is valid only when ENP is

set. PAM is set by the Am79C978

controller and cleared by the

host.

This bit does not exist when the

Am79C978 controller is pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

21 LAFM Logical Address Filter Match is

set by the Am79C978 controller

when it accepts the received

frame based on the value in the

logical address filter register.

LAFM is valid only when ENP is

set. LAFM is set by the

Am79C978 controller and

cleared by the host.

Note that if DRCVBC (CSR15, bit

14) is cleared to 0, only BAM, but

not LAFM will be set when a

Broadcast frame is received,

even if the Logic al Address F ilter

is programmed in such a way that

a Broadcast frame would pass

the hash filter. If DRCVBC is set

to 1 an d the Logica l Address F il-

ter is progr ammed in suc h a way

that a Broadcast frame would

pass the hash filter, LAFM will be

set on the reception of a Broad-

cast fra m e.

This bit does not exist when the

Am79C978 controller is pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

20 BAM Broadcast Address Match is set

by the Am79C978 controller

when it accepts the received

frame, because the frame’s desti -

nation address is of the type

’Broadcast.’ BAM is valid only

when ENP is set. BAM is set by

the Am79C978 controller and

cleared by the host.

This bit does not exist when the

Am79C978 controller is pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

19-16 RES Reserved locations. These loca-

tions should be read and written

as zeros.

15-12 ONES These four bits must be written as

ones. They are written by the host

and unchanged by the

Am79C978 controller.

11-0 BCNT Buffer Byte Count is the length of

the buffer pointed to by this de-

scriptor, expressed as the two’s

complement of the length of the

buffer. This field is written by the

host and unchanged by the

Am79C978 controller.

RMD2

Bit Name Description

31 ZERO This field is reserved. The

Am79C978 controller will write a

zero to this location.

30-16 RFRTAG Receive Frame Tag. Indicates

the Receive Frame Tag applied

from the EADI interface. This field

is use r define d and has a default

value of all zeros. When RX-

FRTG (CSR7, bit 14) is set to 0,

Am79C978 203

RFRTAG will be read as all zeros.

See the section on Receive

Frame Taggi ng for details.

15-12 ZEROS This field is reserved. The

Am79C978 controller will write

zeros to these locations.

11-0 MCNT Message Byte Count is the length

in bytes of the received message,

expresse d a s an unsig ned binar y

intege r. MCNT is valid onl y when

ERR is clear and ENP is set.

MCNT is written by the

Am79C978 controller and

cleared by the host.

RMD3

Bit Name Description

31-0 US User Space. Reserved for user

defined space.

Transmit Descriptors

When SWSTYLE (BCR20, bits 7-0) is set to 0, the soft-

ware structures are defined to be 16 bits wide, and

transmit descriptors look like T able 85 (CXDA = Current

Transmit Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 2, the

software structures are defined to be 32 bits wide, and

transmit descriptors look like T able 86 (CXDA = Current

Transmit Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the

software structures are defined to be 32 bits wide, and

transmit descriptors look like T able 87 (CXDA = Current

Transmit Descriptor Address).

Table 85. Transmit Descriptor (SWSTYLE = 0)

Address 15 14 13 12 11 10 9 8 7-0

CXDA+00h TBADR[15:0]

CXDA+02h OWN ERR ADD_

FCS MORE/

LTINT ONE DEF STP ENP TBADR[23:16]

CXDA+04h 1 1 1 1 BCNT

CXDA+06h BUFF UFLO EX

DEF LCOL LCAR RTRY TDR

Table 86. Transmit Descriptor (SWSTYLE = 2)

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0

CXDA+00h TBADR[31:0]

CXDA+04h OWN ERR ADD_

FCS MORE/

LTINT ONE DEF STP ENP BPE RES 1111 BCNT

CXDA+08h BUFF UFLO EX

DEF LCOL LCAR RTRY RES RES RES RES RES RES TRC

CXDA+0Ch USER SPACE

Table 87. Transmit Descriptor (SWSTYLE = 3)

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0

CXDA+00h BUFF UFLO EX

DEF LCOL LCAR RTRY RES RES TRC

CXDA+04h OWN ERR ADD_

FCS MORE/

LTINT ONE DEF STP ENP BPE RES 1111 BCNT

CXDA+08h TBADR[31:0]

CXDA+0Ch USER SPACE

204 Am79C978

TMD0

Bit Name Description

31-0 TBADR Transmit Buffer address. This

field contains the address of the

transmit buffer that is associated

with this descriptor.

TMD1

Bit Name Description

31 OWN This bit indicates whether the de-

scriptor entry is owned by the

host (OWN = 0) or by the

Am79C978 controller (OWN = 1).

The host sets the OWN bit after

filling the buffer p ointed to by the

descriptor entry. The Am79C978

controller clears the OWN bit af-

ter transmitting the contents of

the buffer. Both the Am79C978

controller and the host must not

alter a descriptor entry after it has

relinquished ownership.

30 ERR ERR is the OR of UFLO, LCOL,

LCAR, RTRY or BPE. ERR is set

by the Am79C978 controller and

cleared by the host. This bit is set

in the current descriptor when the

error occurs and, therefore, may

be set in any descriptor of a

chained buff er transmi ss i on.

29 ADD_FCS ADD_FCS dynamically controls

the generation of FCS on a frame

by frame basis. This bit should be

set with the ENP bit. However, for

backward compatibility, it is rec-

ommended th at this bit be se t for

every descriptor of the intended

frame. When ADD_FCS is set,

the state of DXMTFCS is ignored

and transmitter FCS generation is

activated. When ADD_FCS is

cleared to 0, FCS generation is

controlled by DXMTFCS. When

APAD _XM T ( C SR 4, b it 11) i s set

to 1, the setting of ADD_FCS has

no effect. ADD_FCS is set by the

host, and is not changed by the

Am79C978 controller. This is a

reserved bit in the C-LANCE

(Am79C90) controller.

28 MORE/LTINT Bit 28 always functions as

MORE. The value of MORE is

written by the Am79C978 control-

ler and is read by the host. When

LTINTEN is cleared to 0 (CSR5,

bit 14), the Am79C978 controller

will never look at the contents of

bit 28, write operations by the

host have no effect. When LTINT-

EN is set to 1 bit 28 changes its

function to LTINT on host write

operations and on Am79C978

controlle r read operati on s.

MORE MORE indicates that more than

one retry was ne eded to transmit

a frame. The value of MORE is

written by the Am79C978 control-

ler. This bit has meaning only if

the ENP bit is set.

LTINT LTINT is used to suppress inter-

rupts after successful transmis-

sion on selected frames. When

LTINT is cl eared to 0 and EN P is

set to 1, the Am79C978 controller

will not set TINT (CSR0, bit 9) af-

ter a successful transmission.

TINT will only be set when the

last descriptor of a frame has

both LTINT and ENP set to 1.

When LTINT is cleared to 0, it will

only c aus e t he su p pres sion of in-

terrupts for successful transmis-

sion. TINT will always be set if the

transmission has an error. The

LTINTEN overrides the function

of TOKINTD (CSR5, bit 15).

27 ONE ONE indicates that exactly one

retry was needed to transmit a

frame. ONE flag is not valid when

LCOL is set. The value of the

ONE bit is written by the

Am79C978 controller. This bit

has meaning only if the ENP bit is

set.

26 DEF Deferred indicates that the

Am79C978 controller had to de-

fer while trying to transmit a

frame. This condition occurs if the

channel is busy when the

Am79C978 controller is ready to

transmit. DEF is set by the

Am79C978 controller and

cleared by the host.

25 STP St art of Packet i ndicates that th is

is the first buffer to be used by the

Am79C978 controller for this

frame. It is used for data chaining

Am79C978 205

buffers. The STP bit must be se t

in the first buffer of the frame, or

the Am79C978 controller will skip

over the descriptor and poll the

next descriptor(s) until the OWN

and STP bits are set. STP is set

by the host and is not changed by

the Am79C978 controller.

24 ENP End of Packet. End of Packet in-

dicates that this is the last buffer

to be used by the Am79C978

con tr o ll er f or t hi s frame . It is used

for data chaining buffers. If both

STP and ENP are set, the frame

fits into one buffer and there is no

data chaining. ENP is set by the

host and is not changed by the

Am79C9 78 co ntrol ler .

23 BPE Bus Parity Error is set by the

Am79C978 controller when a par-

ity error occurred on the bus inter-

face dur ing a data transf ers from

the transmit buffer associated

with this descriptor. The

Am79C978 controller will only set

BPE when the advanced parity

error handling is enabled by set-

ting APERREN (BCR20, bit 10) to

1. BPE is set by the Am79C978

controller and cleared by the

host.

This bit does not exist, when the

Am79C978 controller is pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

22-16 RES Reserved locations.

15-12 ONES These four bits must be written as

ones. This field is written by the

host and unchanged by the

Am79C9 78 co ntrol ler .

11-00 BCNT Buffer Byte Count is the usable

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length of

the buffer. This is the number of

bytes from this buffer that will be

transmitted by the Am79C978

controller. This field is written by

the host and is not changed by

the Am79C978 controller. There

are no minimum buffer size re-

strictions.

TMD2

Bit Name Description

31 BUFF Buffer error is set by the

Am79C978 controller during

transmission when the

Am79C978 controller does not

find the ENP flag in the current

descriptor and does not own the

next desc ripto r. T his can occ ur in

either of two ways:

1. The OWN bit of the next buffer

is 0.

2. FIFO underflow occurred be-

fore the Am79C978 controller ob-

tained the STATUS byte

(TMD1[31:24]) of the next de-

scriptor. BUFF is set by the

Am79C978 controller and

cleared by the host.

If a Buffer Error occurs, an Un-

derflow Error will also occur.

BUFF is set by the Am79C978

controller and cleared by the

host.

30 UFLO Underflow error indicates that the

transmitter has truncated a mes-

sage because it could not read

data from memory fast enough.

UFLO indicates that the FIFO has

emptied before the end of the

frame was reached.

When DXSUFLO (CSR3, bit 6) is

cleared to 0, the transmitter is

turned off when an UFLO error

occurs (CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C978 controller gracefully

recovers from an UFLO error. It

scans the transmit descriptor ring

until it finds the start of a new

frame an d sta rts a n ew trans mis-

sion.

UFLO is set by the Am79C978

controller and cleared by the

host.

29 EXDEF Excessive Deferral. Indicates that

the transmitter has experienced

206 Am79C978

Excessive Deferral on this trans-

mit frame, where Excessive De-

ferral is defined in the ISO 8802-3

(IEEE/ ANSI 802. 3) stan dard. Ex-

cessive Deferral will also set the

interrupt bit EXDINT (CSR5, bit

7).

28 LCOL Late Collision indicates that a col-

lision has occurred after the first

channel slot time has elapsed.

The Am79C978 home

networkingAm79C978 controller

does not retry on late collisions.

LCOL is set by the Am79C978

controller and cleared by the

host.

27 LCAR Loss of Carrier is set when the

carrier is lost during an

Am79C978 controller initiated

transmission when operating in

half-duplex mode. The

Am79C978 controller does not

retry upon loss of carrier. It will

continue to transmit the whole

frame until done. LCAR will not

be set when the devic e is operat-

ing in full-duplex mode. LCAR is

not valid in Internal Loopback

Mode. LCAR is set by the

Am79C978 controller and

cleared by the host.

LCAR will be set when the PHY is

in Link Fai l st a t e du ri ng tr an sm i s-

sion.

26 RTRY Retry error indicates that the

transmitte r has failed after 16 at-

tempts to successfully transmit a

message, due to repeated colli-

sions on the medium. If DRTY is

set to 1 in the MODE register,

RTRY will set after one failed

transmission attempt. RTRY is

set by the Am79C978 controller

and cleared by the host.

25-4 RES Reserved locations.

3-0 TRC Transmit Retry Count. Indicates

the number of transmit retries of

the associated packet. The maxi-

mum count is 15. However, if a

RETRY error occurs, the count

will roll over to 0.

In this case only, the Transmit

Retry Cou nt val ue of 0 sh oul d b e

interpreted as meaning 16. TRC

is writ ten by the A m79C978 c on-

troller into the last transmit de-

scriptor of a frame, or when an

error terminates a frame. Valid

only when OWN is cleared to 0.

TMD3

Bit Name Description

31-0 US User Space. Reserved for user

defined space.

Am79C978 207

PCI Configuration Registers

Note: RO = read only, RW = read/write

Table 88. PCI Configuration Registers

Offset Name Width

in Bit Access

Mode Default

Value

00h PCI Vendor ID 16 RO 1022h

02h PCI Devi ce ID 16 RO 2001h

04h PCI Command 16 RW 0000h

06h PCI Status 16 RW 0290h

08h PCI Revision ID 8RO 50h

09h PCI Programming IF 8RO 00h

0Ah PCI Sub-Class 8RO 00h

0Bh PCI Base-Class 8RO 02h

0Ch Reserved 8RO 00h

0Dh PCI Latency Timer 8RW 00h

0Eh PCI Header Type 8RO 00h

0Fh Reserved 8RO 00h

10h PCI I/O Base Address 32 RW 0000 0001h

14h PCI Memory Mapped I/O Base Address 32 RW 0000 0000h

18h - 2Bh Reserved 8RO 00h

2Ch PCI Subsystem Vendor ID 16 RO 00h

2Eh PCI Subsystem ID 16 RO 00h

30h PCI Expansion ROM Base Address 32 RW 0000 0000h

34h Capabilities Pointer 8RO 40h

31h - 3Bh Reserved 8RO 00h

3Ch PCI Interrupt Line 8RW 00h

3Dh PCI Interrupt Pin 8RO 01h

3Eh PCI MIN_GNT 8RO 06h

3Fh PCI MAX_LAT 8RO FFh

40h PCI Capability Identifier 8RO 01h

41h PCI Next Item Pointer 8RO 00h

42h PCI Power Management Capabilities 16 RO 00h

44h PCI Power Management Control/Status 16 RO 00h

46h PCI PMCSR Bridge Support Extensions 8RO 00h

47h PCI Data 8RO 00h

48h - FFh Reserved 8RO 00h

208 Am79C978

Control and Status Registers

Note:

u = undefined value, R = Running register, S = Setup register, T = Test register; all default values are in hexadecimal format.

Table 89. Control and Status Registers (CSRs)

RAP

Addr Symbol Default Value Comments Use

00 CSR0 uuuu 0004 Am79C978 Controller Status Register R

01 CSR1 uuuu uuuu Lower IADR: maps to location 16 S

02 CSR2 uuuu uuuu Upper IADR: maps to location 17 S

03 CSR3 uuuu 0000 Interrupt Masks and Deferral Control S

04 CSR4 uuuu 0115 Test and Features Control R

05 CSR5 uuuu 0000 Extended Control and Interrupt 1 R

06 CSR6 uuuu uuuu RXTX: RX/TX Encoded Ring Lengths S

07 CSR7 0uuu 0000 Extended Control and Interrupt 1 R

08 CSR8 uuuu uuuu LADRF0: Logical Address Filter — LADRF[15:0] S

09 CSR9 uuuu uuuu LADRF1: Logical Address Filter — LADRF[31:16] S

10 CSR10 uuuu uuuu LADRF2: Logical Address Filter — LADRF[47:32] S

11 CSR11 uuuu uuu u LADRF3: Logical Address Filter — LADRF[63:48] S

12 CSR12 uuuu uuuu PADR0: Physical Address Register — PADR[15:0][ S

13 CSR13 uuuu uuuu PADR1: Physical Address Register — PADR[31:16] S

14 CSR14 uuuu uuuu PADR2: Physical Address Register — PADR[47:32] S

15 CSR15 see register

description MODE: Mode Register S

16 CSR16 uuuu uuuu IADRL: Base Address of INIT Block Lower (Copy) T

17 CSR17 uuuu uuuu IADRH: Base Address of INIT Block Upper (Copy) T

18 CSR18 uuuu uuuu CRBAL: Current RCV Buffer Address Lower T

19 CSR22 uuuu uuuu CRBAU: Current RCV Buffer Address Upper T

20 CSR20 uuuu uuuu CXBAL: Current XMT Buffer Address Lower T

21 CSR21 uuuu uuuu CXBAU: Current XMT Buffer Address Upper T

22 CSR22 uuuu uuuu NRBAL: Next RCV Buffer Address Lower T

23 CSR23 uuuu uuuu NRBAU: Next RCV Buffer Address Upper T

24 CSR24 uuuu uuuu BADRL: Base Address of RCV Ring Lower S

25 CSR25 uuuu uuuu BADRU: Base Address of RCV Ring Upper S

26 CSR26 uuuu uuuu NRDAL: Next RCV Descriptor Address Lower T

27 CSR27 uuuu uuuu NRDAU: Next RCV Descriptor Address Upper T

28 CSR28 uuuu uuuu CRDAL: Current RCV Descriptor Address Lower T

29 CSR29 uuuu uuuu CRDAU: Current RCV Descriptor Address Upper T

30 CSR30 uuuu uuuu BADXL: Base Address of XMT Ring Lower S

31 CSR31 uuuu uuuu BADXU: Base Address of XMT Ring Upper S

32 CSR32 uuuu uuuu NXDAL: Next XMT Descriptor Address Lower T

33 CSR33 uuuu uuuu NXDAU: Next XMT Descriptor Address Upper T

Am79C978 209

Control and Status Registers (Continued)

RAP

Addr Symbol Default Value

After H_RESET Comments Use

34 CSR34 uuuu uuuu CXDAL: Current XMT Descriptor Address Lower T

35 CSR35 uuuu uuuu CXDAU: Current XMT Descriptor Address Upper T

36 CSR36 uuuu uuuu NNRDAL: Next Next Receive Descriptor Address Lower T

37 CSR37 uuuu uuuu NNRDAU: Next Next Receive Descriptor Address Upper T

38 CSR38 uuuu uuuu NNXDAL: Next Next Transmit Descriptor Address Lower T

39 CSR39 uuuu uuuu NNXDAU: Next Next Transmit Descriptor Address Upper T

40 CSR40 uuuu uuuu CRBC: Current Receive Byte Count T

41 CSR41 uuuu uuuu CRST: Current Receive Status T

42 CSR42 uuuu uuuu CXBC: Current Transmit Byte T

43 CSR43 uuuu uuuu CXST: Current Transmit Status T

44 CSR44 uuuu uuuu NRBC: Next RCV Byte Count T

45 CSR45 uuuu uuuu NRST: Next RCV Status T

46 CSR46 uuuu uuuu POLL: Poll Time Counter T

47 CSR47 uuuu uuuu PI: Polling Interval S

48 CSR48 uuuu uuuu Reserved

49 CSR49 uuuu uuuu Reserved

50 CSR50 uuuu uuuu Reserved

51 CSR51 uuuu uuuu Reserved

52 CSR52 uuuu uuuu Reserved

53 CSR53 uuuu uuuu Reserved

54 CSR54 uuuu uuuu Reserved

55 CSR55 uuuu uuuu Reserved

56 CSR56 uuuu uuuu Reserved

57 CSR57 uuuu uuuu Reserved

58 CSR58 see regist er

description SWS: Software Style S

59 CSR59 uuuu uuuu Reserved T

60 CSR60 uuuu uuuu PXDAL: Previous XMT Descrip tor Address Lower T

61 CSR61 uuuu uuuu PXDAU: Previous XMT Desc rip tor Addre ss Upper T

62 CSR62 uuuu uuuu PXBC: Previous Transmit Byte Count T

63 CSR63 uuuu uuuu PXST: Previous Transmit Status T

64 CSR64 uuuu uuuu NXBAL: Next XMT Buffer Address Lower T

65 CSR65 uuuu uuuu NXBAU: Next XMT Buffer Address Upper T

66 CSR66 uuuu uuuu NXBC: Next Transmit Byte Count T

67 CSR67 uuuu uuuu NXST: Next Transmit Status T

68 CSR68 uuuu uuuu Reserved

69 CSR69 uuuu uuuu Reserved

70 CSR70 uuuu uuuu Reserved

210 Am79C978

Control and Status Registers (Continued)

RAP

Addr Symbol Default Value

After H_RESET Comments Use

71 CSR71 uuuu uuuu Reserved

72 CSR72 uuuu uuuu RCVRC: RCV Ring Counter T

73 CSR73 uuuu uuuu Reserved

74 CSR74 uuuu uuuu XMTRC: XMT Ring Counter T

75 CSR75 uuuu uuuu Reserved

76 CSR76 uuuu uuuu RCVRL: RCV Ring Length S

77 CSR77 uuuu uuuu Reserved

78 CSR78 uuuu uuuu XMTRL: XMT Ring Lengt h S

79 CSR79 uuuu uuuu Reserved

80 CSR80 uuuu 1410 DMATCFW: DMA Transfer Counter and FIFO Threshold S

81 CSR81 uuuu uuuu Reserved

82 CSR82 uuuu uuuu Transmit Descriptor Pointer Address Lower S

83 CSR83 uuuu uuuu Reserved

84 CSR84 uuuu uuuu DMABA: Address Register Lower T

85 CSR85 uuuu uuuu DMABA: Address Register Upper T

86 CSR86 uuuu uuuu DMABC: Buffer Byte Counter T

87 CSR87 uuuu uuuu Reserved

88 CSR88 262 5003 Chip ID Register Lower T

89 CSR89 uuuu 262 Chip ID Register Upper T

90 CSR90 uuuu uuuu Reserved

91 CSR91 uuuu uuuu Reserved T

92 CSR92 uuuu uuuu RCON: Ring Length Conversion T

93 CSR93 uuuu uuuu Reserved

94 CSR94 uuuu uuuu Reserved

95 CSR95 uuuu uuuu Reserved

96 CSR96 uuuu uuuu Reserved

97 CSR97 uuuu uuuu Reserved

98 CSR98 uuuu uuuu Reserved

99 CSR99 uuuu uuuu Reserved

100 CSR100 uuuu 0200 Bus Timeout S

101 CSR101 uuuu uuuu Reserved

102 CSR102 uuuu uuuu Reserved

103 CSR103 uuuu 0105 Reserved

104 CSR104 uuuu uuuu Reserved

105 CSR105 uuuu uuuu Reserved

106 CSR106 uuuu uuuu Reserved

107 CSR107 uuuu uuuu Reserved

Am79C978 211

Control and Status Registers (Concluded)

RAP

Addr Symbol Default Value

After H_RESET Comments Use

108 CSR108 uuuu uuuu Reserved

109 CSR109 uuuu uuuu Reserved

110 CSR110 uuuu uuuu Reserved

111 CSR111 uuuu uuuu Reserved

112 CSR112 uuuu uuuu Missed Frame Count R

113 CSR113 uuuu uuuu Reserved

114 CSR114 uuuu uuuu Received Collision Count R

115 CSR115 uuuu uuuu Reserved

116 CSR116 0000 0000 OnNow Miscellaneous S

117 CSR117 uuuu uuuu Reserved

118 CSR118 uuuu uuuu Reserved

119 CSR119 uuuu 0105 Reserved

120 CSR120 uuuu uuuu Reserved

121 CSR121 uuuu uuuu Reserved

122 CSR226 uuuu 0000 Receive Frame Alignment Control S

123 CSR237 uuuu uuuu Reserved

124 CSR248 uuuu 0000 Te st Regi ster 1 T

125 CSR125 003c 0060 MAC Enhanced Configuration Control T

126 CSR126 uuuu uuuu Reserved

127 CSR127 uuuu uuuu Reserved

212 Am79C978

Bus Configuration Registers

Writes to thos e r eg ister s mark ed as “Reserved” will ha ve no effect. Re ads fr om the se lo ca tio ns wi ll produce un de-

fined values.

Table 90. Bus Configuration Registers (BCRs)

RAP

Mnemonic Default Name Programmability

User EEPROM

0MSRDA 0005h Reserved No No

1MSWRA 0005h Reserved No No

2MC 0002h Miscellaneous Configuration Yes Yes

3Reserved N/A Reserved No No

4LED0 00C0h LED0 Status Yes Yes

5LED1 0084h LED1 Status Yes Yes

6LED2 0088h LED2 Status Yes Yes

7LED3 0090h LED3 Status Yes Yes

8Reserved N/A Reserved No No

9FDC 0000h Full-Duplex Control Yes Yes

10-15 Reserved N/A Reserved No No

16 IOBASEL N/A Reserved No No

17 IOBASEU N/A Reserved No No

18 BSBC 9001h Burst and Bus Control Yes Yes

19 EECAS 0002h EEPROM Control and Status Yes No

20 SWS 0200h Software Style Yes No

22 PCILAT FF06h PCI Latency Yes Yes

23 PCISID 0000h PCI Subsystem ID No Yes

24 PCISVID 0000h PCI Subsystem Vendor ID No Yes

25 SRAMSIZ 0000h SRAM Size Yes Yes

26 SRAMB 0000h SRAM Boundary Yes Yes

27 SRAMIC 0000h SRAM Interface Control Yes Yes

28 EBADDRL N/A Expansion Bus Address Lower Yes No

29 EBADDRU N/A Expansion Bus Address Upper Yes No

30 EBDR N/A Expansion Bus Data Port Yes No

31 STVAL FFFFh Software Timer Va lue Yes No

32 MIICAS 0000h PHY Control and Status Yes Yes

33 MIIADDR N/A PHY Address Yes Yes

34 MIIMDR N/A PHY Management Data Yes No

35 PCIVID 1022h PCI Vendor ID No Yes

36 PMC_A C811h PCI Power Manag ement C apa bil iti es

(PMC) Alias Register No Yes

37 DATA0 0000h PCI DATA Register Zero Alias Register No Yes

38 DATA1 0000h PCI DATA Register One Alias Register No Yes

39 DATA2 0000h PCI DATA Register Two Alias Register No Yes

40 DATA3 0000h PCI DATA Register Three Alias Register No Yes

41 DATA4 0000h PCI DATA Register Four Alias Re gi ste r No Yes

42 DATA5 0000h PC I DATA Regi ster Five Alias Register No Yes

43 DATA6 0000h PCI DATA Register Six Alias Register No Yes

44 DATA7 0000h PCI DATA Register Seven Alias Re gister No Yes

45 PMR1 N/A Pattern Matching Register 1 Yes No

46 PMR2 N/A Pattern Matching Register 2 Yes No

47 PMR3 N/A Pattern Matching Register 3 Yes No

48 LED4 0082h LED4 Status Yes Yes

49 PHY_SEL 8000h PHY Select Yes Yes

Am79C978 213

10BASE-T PHY Management Registers

Writes to register s marked “Reserved” will be written as

zeros. Reads from these locations will produce unde-

fined values.

Table 91. 10BASE-T PHY Management Registers (TBRs)

Address Symbol Name Default Value After

H_RESET

0TBR0 PHY Control Register 2500h

1TBR1 PHY Status Register 7849h

2TBR2 PHY_ID[31:16] 0000h

3TBR3 PHY_ID[15:0] 6BA0h

4TBR4 Auto-Ne goti ation Adv ertis em en t Regis ter 03C1h

5TBR5 Auto-Negotiation Link Partner Ability Register 0000h

6TBR6 Auto-Ne goti ati on Exp ans io n Regis ter 0004h

7TBR7 Auto-Negotiation Next Page Register 2001h

8-15 TBR8-TBR15 Reserved --

16 TBR16 Interrupt Status and Enable Register 0000h

17 TBR17 PHY Control/Status Register 0001h

18 TBR18 Reserved --

19 TBR19 PHY Management Extension Register --

20-23 TBR20-TBR23 Reserved --

24 TBR24 Summary Status Register 0001h

25-31 TBR25-TBR31 Reserved --

214 Am79C978

1 Mbps HomePNA PHY Management Registers

Table 92. 1 Mbps HomePNA PHY Management Registers (HPRs)

Address Symbol Name Default Value After

H_RESET

0HPR0 MII Control Register 0400h

1HPR1 MII Status Register 0841h

2HPR2 MII PHY_ID Register 0000h

3HPR3 MII PHY_ID Register 6B90h

4HPR4 Auto-Ne goti ation Re gi ste r 0021h

5HPR5 Auto-Ne goti ation Re gi ste r 0000h

6HPR6 Auto-Ne goti ation Re gi ste r 0000h

7HPR7 Auto-Ne goti ation Re gi ste r 0000h

8-15 HPR8-HPR15 Reserved --

16 HPR16 PHY Control Register 0005h

17 HPR17 Status and Control --

18 HPR18 PHY TXCOMM Register 0000h

19 HPR19 PHY TXCOMM Register 0000h

20 HPR20 PHY RXCOMM Register 0000h

21 HPR21 PHY RXCOMM Register 0000h

22 HPR22 PHY AID Register 0000h

23 HPR23 PHY Noise Control Register 04FFh

24 HPR24 PHY Noise Control 2 Register F4xxh

25 HPR25 PHY Noise Statistics Register 04D0h

26 HPR26 Event Status Register 0000h

27 HPR27 AID Control Regis ter 1440h

28 HPR28 ISBI Control Register 2C1Ch

29 HPR29 TX Control Register 0444h

30 HPR30 Drive Level Control x549h

31 HPR31 Analog Control C000h

Am79C978 215

Am79C9 78 Progra mmable Registers

Table 93. Control and Status Registers

CSR0 Status and control bits: (DEFAULT = 0004)

8000 ERR

4000 --

2000 CERR

1000 MISS

0800 MERR

0400 RINT

0200 TINT

0100I IDON

0080 INTR

0040 IENA

0020 RXON

0010 TXON

0008 TDMD

0004 STOP

0002 STRT

0001 INIT

CSR1 Lower IADR (Maps to CSR 16)

CSR2 Upper IADR (Maps to CSR 17)

CSR3 Interrupt masks and Deferral Control: (DEFAULT = 0)

8000 --

4000 --

2000 --

1000 MISSM

0800 MERRM

0400 RINTM

0200 TINTM

0100 IDONM

0080 --

0040 DXSUFLO

0020 LAPPEN

0010 DXMT2PD

0008 EMBA

0004 BSWP

0002 --

0001 --

CSR4 Interrupt masks, configuration and status bits: (DEFAULT = 0115)

8000 --

4000 DMAPLUS

2000 --

1000 TXDPOLL

0800 APAD_XMT

0400 ASTRP_RCV

0200 MFCO

0100 MFCOM

0080 UNITCMD

0040 UNIT

0020 RCVCCO

0010 RCVCCOM

0008 TXSTRT

0004 TXSTRTM

0002 --

0001 --

CSR5 Extended Interrupt masks, configuration and status bits: (DEFAULT = 0XXX)

8000 TOKINTD

4000 LTINTEN

2000 --

1000 --

0800 SINT

0400 SINTE

0200 --

0100 --

0080 EXDINT

0040 EXDINTE

0020 MPPLBA

0010 MPINT

0008 MPINTE

0004 MPEN

0002 MPMODE

0001 SPND

CSR7 Extended Interrupt masks, configuration and status bits: (DEFAULT = 0000)

8000 FASTSPND

4000 RXFRMTG

2000 RDMD

1000 RXDPOLL

0800 STINT

0400 STINTE

0200 MREINT

0100 MREINTE

0080 MAPINT

0040 MAPINTE

0020 MCCINT

0010 MCCINTE

0008 MCCIINT

0004 MCCIINTE

0002 MIIPDTINT

0001 MIIPDTNTE

CSR8 - CSR11 Logical Address Filter

CSR12 - CSR14 Physical Address Register

CSR15

MODE: (DEFAULT = 0)

bits [8:7] = PORTSEL, Port Selection

11 PHY Selected

10 Reserved

8000 PROM

4000 DRCVBC

2000 DRCVPA

1000 --

0800 --

0400 --

0200 --

0100 PORTSEL1

0080 PORTSEL0

0040 INTL

0020 DRTY

0010 FCOLL

0008 DXMTFCS

0004 LOOP

0002 DTX

0001 DRX

CSR47 TXPOLLINT: Transmit Polling Interval

CSR49 RXPOLLINT: Receive Polling Interval

CSR58

Software Style (mapped to BCR20)

bits [7:0] = SWSTYLE, Software Style Register.

0000 LANCE/PCnet-ISA

0002 PCnet-32

8000 --

4000 --

2000 --

1000 --

0800 --

0400 APERREN

0200 --

0100 SSIZE32

0080 --

0040 --

0020 --

0010 --

0008 SWSTYLE3

0004 SWSTYLE2

0002 --

0001 SWSTYLE0

216 Am79C978

Am79C978 Programmable Registers (Continued)

CSR76 RCVRL: RCV Descriptor Ring length

CSR78 XMTRL: XMT Descriptor Ring length

CSR80 FIFO threshold and DMA burst control (DEFAULT = 2810)

8000 Reserved

4000 Reserved

bits [13:12] = RCVFW, Receive FIFO Watermark

0000 Request DMA when 16 bytes are pr esent

1000 Request DMA when 64 bytes are pr esent

2000 Request DMA when 112 bytes are present

3000 Reserved

bits [11:10] = XMTSP, Transmit Start Point

0000 Start transmission after 20/36 (No SRAM/SRAM) bytes have been written

0400 Start transmission a fter 64 bytes ha ve been written

0800 Start transmission after 128 bytes have been written

0C00 Start transmission after 220 max/Full Packet (No SRAM/SRAM with UFLO bit set) bytes

have been written

bits [9:8] = XMTFW, Transmit FIFO Watermark

0000 Start DMA when 16 write cycles can be made

0100 Start DMA when 32 write cycles can be made

0200 Start DMA when 64 write cycles can be made

0300 Start DMA when 128 write cycles can be made

bits [7:0] = DMA Burst Register

CSR88~89 Chip ID (Contents = v12626003; v = Version Number)

CSR112 Missed Fram e Count

CSR114 Receive Collision Count

CSR116 OnNow Miscellaneous

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 PME_EN_OVR

0100 LCDET

0080 PMAT

0040 EMPPLBA

0020 MPMAT

0010 MPPEN

0008 RWU_DRIVER

0004 RWU_GATE

0002 RWU_POL

0001 RST_POL

CSR122 Receive Frame Alignment Control

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 --

0004 --

0002 --

0001 RCVALGN

CSR124 BMU Test Register (DEFAULT = 0000)

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 --

0004 RPA

0002 --

0001 --

CSR125 MAC Enhanced Configuration Control (DEFAULT = 603c)

bits [15:8] = IPG, InterPacket Gap (Default = 60xx, 96 bit times)

bits [8:0] = IFS1, InterFrame Space Part 1 (Default = xx3c, 60 bit times)

Am79C978 217

Am79C978 Programmable Registers (Continued)

Table 94. Bus Configuration Registers

RAP Addr Register Contents

0MSRDA Programs width of DMA read signal (DEFAULT = 5)

1MSWRA Programs width of DMA write signal (DEFAULT = 5)

2MC Miscellaneous Configuration bits: (DEFAULT = 2)

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 APROMWE

0080 INITLEVEL

0040 --

0020 --

0010 --

0008 EADISEL

0004 --

0002 ASEL 0001

4LED0 Programs the function and width of the LED0 signal. (DEFAULT = 00C0)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 POWER

0004 RCVE

0002 SPEED

0001 COLE

5LED1 Programs the function and width of the LED1 signal. (DEFAULT = 0084)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 POWER

0004 RCVE

0002 SPEED

0001 COLE

6LED2 Programs the function and width of the LED2 signal. (DEFAULT = 0088)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 POWER

0004 RCVE

0002 SPEED

0001 COLE

7LED3 Programs the function and width of the LED3 signal. (DEFAULT = 0090)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 POWER

0004 RCVE

0002 SPEED

0001 COLE

9FDC Full-Duplex Control. (DEFAULT= 0000)

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 --

0004 FDRPAD

0002 --

0001 FDEN

16 IOBASEL I/O Base Address Lower

17 IOBASEU I/O Base Address Upper

18 BSBC Burst Size and Bus Control (DEFAULT = 2101)

8000 ROMTMG3

4000 ROMTMG2

2000 ROMTMG1

1000 ROMTMG0

0800 NOUFLO

0400 --

0200 MEMCMD

0100 EXTREQ

0080 DWIO

0040 BREADE

0020 BWRITE

0010 --

0008 --

0004 --

0002 --

0001 --

19 EECAS EEPROM Control and Status (DEFAULT = 0002)

8000 PVALID

4000 PREAD

2000 EEDET

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 EEN

0008 --

0004 ECS

0002 ESK

0001 EDI/EDO

20 SWSTYLE Software Style (DEFAULT = 0000, maps to CSR 58)

218 Am79C978

Am79C978 Programmable Registers (Continued)

RAP Addr Register Contents

22 PCILAT PCI Latency (DEFAULT = FF06)

bits [15:8] = MAX_LAT

bits [7:0] = MIN_GNT

25 SRAMSIZE SRAM Size (DEFAULT = 0000)

bits [7:0] = SRAM_SIZE

26 SRAMBND SRAM Boundary (DEFAULT = 0000)

bits [7:0] = SRAM_BND

27 SRAMIC SRAM Interface Control (Default = 0000)

8000PTR TST

4000LOLATRX

bits [5:3] = EBCS, Expansion Bus Clock Source

0000 CLK pin, PCI clock

0008 Time Base Clock

0010 EBCLK pin, Expansion Bus Clock

bits [2:0] = CLK_FAC, Expansion Bus Clock Factor

0000 1/1 clock factor

0001 1/2 clock factor

0002 --

0003 --

28 EPADDRL Expansion Port Address Lower (Default = 0000)

29 EPADDRU Expansion Port Address Upper (Default = 0000)

8000 FLASH

4000 LAINC

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 EPADDRU3

0004 EPADDRU2

0002 EPADDRU1

0001 EPADDRU0

30 EBDATA Expan si on Bus D ata Port

31 STVAL Software Timer Interrupt Value (DEFAULT = FFFF)

32 MIICAS PHY Status and Control (DEFAULT = 0000)

8000 ANTST

4000 MIIPD

2000 FMDC1

1000 FMDC0

0800 APEP

0400 APDW2

0200 APDW1

0100 APDW0

0080 DANAS

0040 XPHYRST

0020 XPHYANE

0010 XPHYFD

0008 XPHYSP

0004 --

0002 MIILP

0001 --

33 MIIADDR PHY Address (DEFAULT = 0000)

bits [9:5] = PHYAD, Physical Layer Device Address

bits [4:0] = REGAD, Auto-Negotiation Register Address

34 MIIMDR PHY Data Port

35 PCI Vendor ID PCI Vendor ID Register (DEFAULT = 1022h)

36 PMC Alias PCI Power Management Capabilities (DEFAULT = 0000)

37 DATA 0 PCI Data Register Zero Alias Register (DEFAULT = 0000)

38 DATA 1 PCI Data Register One Alias Register (DEFAULT = 0000)

39 DATA 2 PCI Data Register Two Alias Register (DEFAULT = 0000)

40 DATA 3 PCI Data Register Three Alias Register (DEFAULT = 0000)

41 DATA 4 PCI Data Register Four Alias Register (DEFAULT = 0000)

42 DATA 5 PCI Data Register Five Alias Register (DEFAULT = 0000)

43 DATA 6 PCI Data Register Six Alias Register (DEFAULT = 0000)

44 DATA 7 PCI Data Register Seven Alias Register (DEFAULT = 0000)

45 PMR 1 OnNow Pattern Matching Regi ste r 1

46 PMR 2 OnNow Pattern Matching Regi ste r 2

47 PMR 3 OnNow Pattern Matching Regi ste r 3

Am79C978 219

Am79C978 Programmable Registers (Concluded)

RAP Addr Register Contents

48 LED4 Programs the function and width of the LED3 signal. (DEFAULT = 0082)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 POWER

0004 RCVE

0002 SPEED

0001 COLE

49 PHY_SEL PHY Select

8000 10BASE_T PHY

8101 HomeRun PHY

8202 External PHY

220 Am79C978

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature. . . . . . . . . . . . . -65°C to +70°C

Supply voltage

with respect to VSSB, VSS . . . . . . . . . –0.3 V to 3.63 V

Stress es ab ove tho se lis ted unde r Ab solute Maxi mum

Ratings may cause permanent device failure. Function-

ality at or above these limits is not implied. Exposure to

Absolut e Maximum Ratin gs for extended per iods may

affect devic e re liabi li ty.

OPERATING RANGES

Commercial (C) Devices

Temperature (TA) . . . . . . . . . . . . . . . . . .0°C to +70°C

Supply Voltages

(VDD, VDDR, VDD_PCI) . . . . . . . . . . . . . . .+3.3 V ±10%

All inputs within the range: . . . . . .VSS - 0.5 V to 5.5 V

Operating ranges define those limits between which

the functionality of the device is guaranteed.

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise

specified

Parameter

Symbol Parameter Description Test Conditions Min Max Units

Digital I/O (Non-PCI Pins)

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

VOL Output LOW Voltage IOL1 = 4 mA

IOL2 = 6 mA

IOL3 = 12 mA (Note 1) 0.4 V

VOH Output HIGH Voltage (Notes 2, 3) IOH1 = -4 mA

IOH2 = -2 mA

(Note 3) 2.4 V

IOZ Output Leakage Current (Note 4) 0 V <VOUT <VDD -10 10 µA

IIX Input Leakage Current (Note 5) 0 V <VIN <VDD -10 10 µA

IIL Input LOW Current (Note 6) VIN = 0 V; VDD = 3.6 V -200 -10 µA

IIH Input HIGH Current (Note 6) VIN = 2.7 V ; VDD = 3.6 V -50 10 µA

PCI Bus Interface - 5 V Signaling

VIH Input HIGH Voltage 2.0 5.5 V

VIL Input LOW Voltage -0.5 0.8 V

IOZ Output Leakage Current (Note 4) 0 V <VIN < VDD_PCI -10 10 µA

IIL Input LOW Current VIN = 0.5 V -- -70 µA

IIH Input HIGH Current VIN = 2.7 V -- 70 µA

IIX_PME Input Leakage Current (Note 7) 0 V = < VIN < 5.5 V -1 1µA

VOH Output HIGH Voltage (Note 2) IOH = -2 mA 2.4 V

VOL Output LOW Voltage IOL4 = 3 mA

IOL2 = 6 mA (Note 1) 0.55 V

PCI Bus Interface - 3.3 V Signaling

VIH Input HIGH Voltage 0.5 VDD_PCI VDD_PCI +

0.5 V

VIL Input LOW Voltage -0.5 0.3 V DD_PCI V

IOZ Output Leakage Current (Note 4) 0 V < VOUT < VDD_PCI -10 10 µA

IIL Input LOW Current VIN = 2.7 V -10 10 µA

IIH Input HIGH Current VIN = 2.7 V -10 10 µA

IIX_PME Input Leakage Current (Note 7) 0 V = < VIN < 3.6 V -1 1µA

VOH Output HIGH Voltage (Note 2) IOH = -500 µA 2.4 V

VOL Output LOW Voltage IOL = 1500 µA 0.1 VDD_PCI V

Am79C978 221

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise

specified (Concluded)

Notes:

1. IOL2 applies to DEVSEL, FRAME, INTA, IRDY, PERR, SERR, STOP, TRDY, EECS, EEDI, EBUA_EBA[7:0], EBDA[15:8],

EBD[7:0], EROMCS, AS_EBOE, EBWE, and PHY_RST.

IOL3 applies to LED0, LED1, LED2, LED3, and LED4.

IOL4 applies to AD[31:0], C/BE[3:0], PAR, and REQ pins in 5 V signalling environment.

2. VOH does not apply to open-drain output pins.

3. IOH2 applies to all other outputs.

4. IOZ applies to all output and bidirectional pins, except the PME pin. Tests are performed at VIN = 0 V and at VDD only.

5. IIX applies to all input pins except PME, TDI, TCLK, and TMS pins.

6. IIL and IIH apply to the TDI, TCLK, and TMS pins.

7. IIX_PME applies to the PME pin only. Tests are performed at VIN = 0 V and 5.5 V only.

8. Parameter not tested. Value determined by characterization.

9. CCLK applies only to the CLK pin.

10. CIDSEL applies only to the IDSEL pin.

11. Power supply current values listed here are preliminary estimates and are not guaranteed.

Parameter

Symbol Parameter Description Test Conditions Min Max Units

Pin Capacitance

CIN Pin Capacitance FC = 1 MHz (Note 8) 10 pF

CCLK CLK Pin Capacitance FC = 1 MHz (Notes 8,9) 512 pF

CIDSEL IDSEL Pin Capacitance Fc = 1 MHz (Notes 8, 10 8pF

LPIN Pin Inductance Fc = 1 MHz (Note 8) 20 nH

Power Supply Current (Note 11)

IDD Dynamic Current PCI CLK at 33 MHz 300 mA

IDD_WU1

Wake-up current when the device is

in the D1, D2, or D3 state and the

PCI bus is in the B0 or B1 state.

PCI CLK at 33 MHz, device in Magic

Packet or OnNow mode, receiv ing

non-matching packets in 10BASE-T

mode

110 mA

IDD_WU2

Wake-up current when the device is

in the D2 or D3 state and the PCI bus

is in the B2 or B3 state.

PCI CLK LOW, PG LOW, device at

Magic Packet or OnNow mode,

receiving non-matching packets in

10BASE-T mode

80 mA

IDD_WU3

Wake-up current when the device is

in the D2 or D3 state and the PCI bus

is in the B2 or B3 state.

PCI CLK at 33 MHz, device in Magic

Packet or OnNow mode, receiv ing

non-matching packets in HomePNA

mode

110 mA

IDD_WU4

Wake-up current when the device is

in the D2 or D3 state and the PCI bus

is in the B2 or B3 state.

PCI CLK LOW, PG LOW, device at

Magic Packet or OnNow mode,

receiving non-matching packets in

HomePNA mode

80 mA

IDD_S Static IDD PCI CLK, RST, and TBC_EN pin

HIGH. 100 mA

222 Am79C978

SWITCHING CHARACTERISTICS: BUS INTERFACE

Parameter

Symbol Parameter Name Test Condition Min Max Unit

Clock Timing

FCLK CLK Frequency 033 MHz

tCYC CLK Period @ 1.5 V for 5 V signaling

@ 0.4 VDD for 3.3 V signaling 30 _ns

tHIGH CLK High Time @ 2.0 V for 5 V signaling

@ 0.4 VDD for 3.3 signaling 12 ns

tLOW CLK Low Time @ 0.8 V for 5 V signaling

@ 0.3 VDD for 3.3 V signaling 12 ns

tFALL CLK Fall Time over 2 V p-p for 5 V signaling

over 0.4 VDD for 3.3 V signaling

(Note 1) 1 4 V/ns

tRISE CLK Rise Time over 2 V p-p for 5 V signaling

over 0.4 VDD for 3.3 V signaling

(Note 1) 1 4 V/ns

Output and Float Delay Timing

tVAL

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY , STOP , DEVSEL, PERR,

SERR

Valid Delay

211 ns

tVAL (REQ)REQ Valid Delay 212 ns

tON

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL Active

Delay 2ns

tOFF

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL Float

Delay 28 ns

Setup and Hold Timing

tSU

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY , STOP, DEVSEL, IDSEL

Setup Time 7ns

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL, IDSEL

Hold Time 0ns

tSU (GNT)GNT Setup Time 10 ns

tH (GNT)GNT Hold Time 0ns

Am79C978 223

SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)

Notes:

1. Not tested; parameter guaranteed by design characterization.

2. Parameter value is given for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access the EE-

PROM, software is responsible for meeting EEPROM timing requirements.

Parameter

Symbol Parameter Name Test Condition Min Max Unit

EEPROM Timing

fEESK EESK Frequency (Note 2) 650 kHz

tHIGH (EESK) EESK High Time 780 ns

tLOW (EESK) EESK Low Time 780 ns

tVAL (EEDI) EEDI Valid Output Delay from EESK (Note 2) -15 15 ns

tVAL (EECS) EECS Valid Output Delay from EESK (Note 2) -15 15 ns

tLOW (EECS) EECS Low Time 1550 ns

tSU (EEDO) EEDO Setup Time to EESK (No te 2) 50 ns

tH (EEDO) EEDO Hold Time from EESK (Note 2) 0ns

JTAG (IEEE 1149.1) Test Signal Timing

tJ1 TCK Frequency 10 MHz

tJ2 TCK Period 100 ns

tJ3 TCK High Time @ 2.0 V 45 ns

tJ4 TCK Low Time @ 0.8 V 45 ns

tJ5 TCK Rise Time 4ns

tJ6 TCK Fall Time 4ns

tJ7 TDI, TMS Setup Time 8ns

tJ8 TDI, TMS Hold Ti me 10 ns

tJ9 TDO Valid Delay 330 ns

tJ10 TDO Float Delay 50 ns

tJ11 All Outputs (Non-Test) Valid Delay 325 ns

tJ12 All Outputs (Non-Test) Float Delay 36 ns

tJ13 All Inputs (Non-Test)) Setup Time 8ns

tJ14 All Inputs (Non-Test) Hold Ti me 7ns

224 Am79C978

SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)

10BASE-T Mode

Note: VOUT reflects output levels prior to 1:√2 transformer stage.

Power Supply Current

Symbol Parameter Description Test Conditions Minimum Maximum Unit

VOUT Output Voltage on TX± (peak) 1.55 1.98 V

VDIFF Input Differential Squelch

Assert on RX± (peak) 300 520 mV

VDIFF Input Differential De-Assert

Voltage on RX± (peak) 150 300 mV

IIX Input Leaka ge Current -300 300 µa

Symbol Parameter Description Test Conditions Maximum Unit

ICC

(1 Mbps) 1Mbps mode on TX± and RX±.

Outputs driving load. VDD= Maximum 480 mA

ICC

(10 Mbps) 10BASE-T mode on TX± and RX±.

Outputs driving load. VDD= Maximum 480 mA

Am79C978 225

SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)

External Clock (XTAL) Timing Specifications

External Clock (Oscillator) Timing Specification

Figure 52. Clock Timing

PMD Interface

PECL

Note:

1. Not included in the production test.

Figure 53. PMD Interface Timing (PECL)

Clock Timing

No. Symbol Parameter Description Min Max Unit

PER Cycle time 49.995 50.005 ns

PWH Cycle high time 0.4* Tcycle 0.6*Tcycle ns

PWL Clock low time 0.4*Tcycle 0.6*Tcycle ns

Clock Timing

No. Symbol Parameter Description Min Max Unit

PER Cycle time 16.665 16.669 ns

PWH Cycle high time 0.4* Tcycle 0.6*Tcycle ns

PWL Clock low time 0.4*Tcycle 0.6*Tcycle ns

XCLK

22206B-55

No. Symbol Parameter Description Test Conditions Min Max Unit

160 tR (Note 1) TX+, TX- Rise Time PECL Load 0.5 3 ns

161 tF (Note 1) TX+, TX- Fall Time PECL Load 0.5 3 ns

162 tSK (Note 1) TX+ to TX- skew PECL Load -- +200 ps

163 tSSDI setup time to XCLK high -- 7 -- ns

164 tHSDI hold time to XCLK high -- 5 -- ns

TX+,TX–

TX+

TX–

162

161

80%

20%

160

22206B-56

226 Am79C978

SWITCHING CHARACTERISTICS: BUS INTERFACE (CONCLUDED)

10BASE-T

Note: RX± pulses n arrower than tPWDRD (min) will mai ntain internal Carri er Sense on. RX± pulses wider than tPWKRD (max) will

turn internal Carrier Sense off.

Figure 54. 10 Mbps Transmit (TX±) Timing Diagram

Figure 55. 10 Mbps Receive (RX±) Timing Diagram

Symbol Parameter Description Test Conditions Min Max Unit

tTETD Transmit End of Transmission 250 375 ns

tPWKRD RX± Pulse Width Maintain/Turn Off Threshold |VIN| > |VTHS| (Note 1) 136 200 ns

TX±

tTETD

22206B-57

RX±

t(PWKRD)

tPWKRD

VTSQ+

VTSQ-

t(PWKRD)

22206B-58

Am79C978 227

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE

Notes:

1. MDIO vali d meas ured at the ex posed mechanic al Medi a Indepen den t Interface.

2. TXCLK a nd RXCLK f requency and tim ing param eters are defined for the e xternal p hysical l ayer trans ceiver a s defined in the

IEEE 802.3u standard. They are not replicated here.

Parameter

Symbol Parameter Name Test Condition Min Max Unit

Transmit Timing

tTVAL TX_EN and TXD valid from

↑ TX_CLK

measu red from Vilmax = 0.8 V or

measu red from Vihmin = 2.0V

(Not e 1) 025 ns

Receive Timing

tRSU RX_DV, RX_ER, RXD setup to

↑ RX_CLK

measu red from Vilmax = 0.8 V or

measu red from Vihmin = 2.0V

(Not e 1) 10 ns

tRH RX_DV, RX_ER, RXD hold to

↑ RX_CLK

measu red from Vilmax = 0.8 V or

measu red from Vihmin = 2.0V

(Not e 1) 10 ns

Management Cycle Timing

tMHIGH MDC Pulse Width HIGH Time CLOAD = 390 pf 160 ns

tMLOW MDC Pulse Width LOW Time CLOAD = 390 pf 160 ns

tMCYC MDC Cycle Period CLOAD = 390 pf 400 ns

tMSU MDIO setup to ↑ MDC

CLOAD = 470 pf,

measu red from Vilmax = 0.8 V or

measu red from Vihmin = 2.0V

(Not e 1)

10 ns

tMH MDIO hold to ↑ MDC

CLOAD = 470 pf,

measu red from Vilmax = 0.8 V or

measu red from Vihmin = 2.0V

(Not e 1)

10 ns

tMVAL MDIO valid from ↑ MDC

CLOAD = 470 pf,

measu red from Vilmax = 0.8 V or

measu red from Vihmin = 2.0V,

(Not e 1)

tMCYC -

tMSU ns

228 Am79C978

SWITCHING WAVEFORMS

Key to Switching Waveforms

SWITCHING TEST CIRCUITS

Figure 56. Normal and Tri-State Outputs

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010-PAL

Sense Point V

THRESHOLD

22206B-59

Am79C978 229

SWITCHING W AVEFO RMS: SYSTEM BUS INTERFACE

Figure 57. CLK Waveform for 5 V Signaling

Figure 58. CLK Waveform for 3.3 V Signaling

Figure 59. Input Setup and Hold Timing

CLK

tHIGH

tCYC

tLOW 2.0 V

1.5 V

0.8 V

0.4 V

2.0 V

1.5 V

0.8 V

2.4 V

22206B-60

CLK

tHIGH

tCYC

tLOW 0.5 VDD_PCI

0.4 VDD_PCI

0.3 VDD_PCI

0.2 VDD_PCI

0.5 VDD_PCI

0.4 VDD_PCI

0.3 VDD_PCI

0.6 VDD_PCI

22206B-61

CLK

AD[31:00], C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP,

DEVSEL, IDSEL

tSU

GNT

tH(GNT)

tSU(GNT)

Tx Tx

22206B-62

230 Am79C978

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONTINUED)

Figure 60. Output Valid Delay Timing

Figure 61. Output Tri-State Delay Timing

Figure 62. EEPROM Read Functional Timing

CLK

tVAL(REQ)

Tx Tx Tx

MIN MAX

Valid n Valid n+1

REQ

MIN MAX

Valid n Valid n+1

tVAL

AD[31:00] C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP, DEVSEL,

PERR, SERR

22206B-63

CLK

Tx Tx Tx

AD[31:00], C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP,

DEVSEL, PERR

AD[31:00], C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP,

DEVSEL, PERR

Valid n

tOFF

tON

Valid n

22206B-64

22206B-65

EECS

EESK

EEDI

EEDO

01 1A6A5 A4 A3 A2 A1 A0

D15 D14 D13 D2 D1 D0

22206B-65

Am79C978 231

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONTINUED)

Figure 63. Automatic PREAD EEPROM Timing

Figure 64. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling

EESK

EEDO

Stable

EEDI

EECS

tHIGH (EESK) tLOW (EESK)

tLOW (EECS)

tSU (EEDO)

tH (EEDO)

tVAL (EEDI,EECS)

22206B-66

TCK

tJ3

tJ6

tJ2

tJ5

tJ4 2.0 V

1.5 V

0.8 V

2.0 V

1.5 V

0.8 V

22206B-67

232 Am79C978

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONCLUDED)

Figure 65. JTAG (IEEE 1149.1) Test Signal Timing

TCK

TDI, TMS

TDO

tJ8

Output

Signals

tJ2

tJ7

tJ9

tJ11

tJ14

Input

Signals

tJ12

tJ13

22206B-68

Am79C978 233

SWITCHING W AVEFO RMS: MEDIA INDEPENDENT INTERFACE

Figure 66. Transmit Timing

Figure 67. Receive Timing

Figure 68. MDC Waveform

TX_CLK

TVAL

TXD[3:0],

TX_EN Vihmin

Vilmax

Vihmin

Vilmax

22206B-69

RX_CLK

tRH

RXD[3:0],

RX_ER,

RX_DV

tRSU

Vihmin

Vilmax

Vihmin

Vilmax

22206B-70

0.8 V

1.5 V

2.0 V

tMHIGH

MCYC

tMLOW

0.8 V

2.4

1.5 V

2.0 V

0.4

22206B-71

234 Am79C978

SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE (CONCLUDED)

Figure 69. Management Data Setup and Hold Timing

Figure 70. Management Data Output Valid Delay Timing

MDC

MDIO

MSU

Vihmin

Vilmax

Vihmin

Vilmax

22206B-72

MDC

tTMVAL

Vihmin

Vilmax

Vihmin

Vilmax

MDIO

22206B-73

Am79C978 235

PHYSICAL DIMENSIONS*

PQL144

Thin Quad Flat Pack (measured in millimeters)

*For reference only. BSC is an ANSI standard for Basic Space Centering.

21.80

22.20

19.80

20.20

21.80

22.20

19.80

20.20

144

1.00 REF.

1.60 MAX

11° – 13°

0.50 BSC

1.35

1.45

11° – 13°

Detail Y

0.20

0.05 MM/MM

See Detail A

Detail Y

Base Metal

With Lead Finish

See Detail A

Seating Plane

0.08 C

0.05 S

SDS0.08 M C A-B

Detail X

0° Min.

Even Lead Sides

Odd Lead Sides

Detail X

0.20 Min.

0.13 R. Min.

Gage Plane

0.13 R. Min.

0.20 R. Max.

0.25

0.05 MM/MM

0.20 M H A-B S

0.20 M SA-BC

A S - B D S

A-B

0.20 M C SA-B D S

0.09

0.16

1.60

MAX

0° – 7°0.17

0.27

0.09

0.20

0.17

0.27

0.17

0.23

0.05

0.15

0.25 BSC

0.17

0.27

0.45

0.75

0.20 C A-B D

16-038-PQT-1_AN

EP 137

8-11-98 lv

236 Am79C978

PQR160

Plastic Quad Flat Pack (measured in millimeters)

*For reference only. BSC is an ANSI standard for Basic Space Centering.

25.35

REF

27.90

28.1031.00

31.40

Pin 120

Pin 80

0.65 BASIC

3.20

3.60

0.25

Min

Pin 40

Pin 1 I.D.

25.35

REF

Pin 160

27.90

28.10

31.00

31.40

3.95

MAX

SEATING PLANE

16-038-PQR-1

PQR160

12-22-95 lv

The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations

or warranties with respect to the accur acy or completeness of the contents of this publicat ion and re serves th e right to make changes to speci-

fications and product desc riptions at any time without notice. No license, whet her express, implied, arising by estoppel or otherwise, to any in-

tellectual property rights is granted by this publicat ion. Except as set forth in AMD’s Standard Terms and Condit ions of Sale, AM D assumes no

liability whatsoever, and disclaims any express or imp lied warranty, relating to its products inc luding, but not limited to, the implied warranty of

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situation where personal injury, death, or sever e propert y or environm ental damage may occur. AM D reser ves t he right to discont inue or make

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AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Auto-Poll, MACE, Magic Packet, PCnet, PCnet-FAST, PCn et -FAST+, PCnet-Home, PCnet-ISA, PCnet-ISA+, PCnet-ISA II, PCnet-32 are trade-

marks of Advanced Micro Devi c es, In c.

RLL25 is a trademark of Tut Systems, Inc.

Other product names used in this publication are for identification purposes only and may be trademark s of their respective companies.

238 Am79C978

APPENDIX A

A-1

Am79C978

Alternative Method for

Initialization

The controller may be initialized by performing I/O

writes only. That is, data can be written directly to the

appropriate control and status registers (CSR instead

of reading from the initialization block in memory). The

registe rs th at must be written are shown in Tabl e A-1.

These register writes are followed by writing the

START bit in CSR0.

Note:

1. The INIT bit must not be set or the initialization block will be accessed instead.

2. Needed only if SSIZE32 =0.

3. Needed only if the physical address is different from the one stored in EEPROM or if there is no EEPROM present.

Table A-1. Registers for Alternative Initialization Method (Note 1)

Control and Status Register Comment

CSR2 IADR[31:16] (Note 2)

CSR8 LADRF[15:0]

CSR9 LADRF[31:16]

CSR10 LADRF[47:32]

CSR11 LADRF[63:48]

CSR12 PADR[15:0] (Note 3)

CSR13 PADR[31:16] (Note 3)

CSR14 PADR[47:32] (Note 3)

CSR15 MODE

CSR24-25 BADR

CSR30-31 BADX

CSR47 TXPOLLINT

CSR49 RXPOLLINT

CSR76 RCVRL

CSR78 XMTRL

A-2 Am79C978

APPENDIX B

B-1Am79C978

Look-Ahead Packet Processing

(LAPP) Concept

INTRODUCTION

A driver for the controller would normally require that

the CPU copy receive frame data from the controllers

buffer space to the a pplications buffer space after the

entire frame has been received by the controller. For

applica tio ns tha t us e a pi ng- po ng w ind owi ng s tyle , th e

traffic on the network will be halted until the current

frame has been completely processed by the entire ap-

plicati on stack. This mean s tha t the time between l ast

byte of a r ec eiv e fr am e ar riv in g a t the cl ie nt’s Ether ne t

control ler and the c lien t’s transmissi on of the first byte

of the next outgoing frame will be separated by:

1. The time that it takes the client’s CPU interrupt pro-

cedure to pass software control from the current

task to the driver,

2. Plus the time that it takes the client driver to pass

the header data to the application and request an

application buffer,

3. Plus t he time that it t akes the appl ication to gener-

ate the buffer pointer and then return the buffer

pointer to the driver,

4. Plus the time that it takes the client driver to transfer

all of the frame data from the controller’s buffer

space into the application’s buffer space and then

call the application again to process the complete

frame,

5. Plus the time that it takes the application to process

the frame and generate the next outgoing frame,

and

6. Plus t he ti me tha t it tak es the c lient driver to set up

the descriptor for the controller and then write a

TDMD bit to CSR0.

The sum of these times can often be about the same

as the time taken to actually transmit the frames on the

wire, ther eby, yieldi ng a netwo rk utiliz ation rate of le ss

than 50 percent.

An important thing to note is that the controller’s data

transfers to its buffer space are such that the system

bus is needed by the controller for approximately 4 per-

cent of the tim e. This le aves 96 percent of the system

bus bandwi dth for the CPU to perfor m some of the in-

terframe operations in advance of the completion of

network re ceiv e acti vity, if p ossibl e. The que st ion the n

becomes : how much of the task s that need to be per-

formed between reception of a frame and transmission

of the next frame can be performed before the recep-

tion of the frame actually ends at the network, and how

can the CP U be ins tr ucted t o per fo rm the se t as ks dur-

ing the network reception time.

The answer depends upon exactly what is ha ppening

in the driver and application code, but the steps that

can be performed at the same time as the receive data

are arriving include as much as the first three steps and

part of the fourth step shown in the sequence above.

By perf ormi ng th es e s tep s b efor e t he e nti re fr ame has

arrived, the frame throughput can be substantially

increased.

A good increase in performance can be expected when

the first three steps are performed before the end of the

network receive operation. A much more significant

performance increase could be realized if the controller

could place the frame data directly into the applica-

tion’s buffer space; (i.e., eliminate the need for step 4.)

In order to mak e this wor k, i t is ne cessar y that the ap-

plication buffer pointer be determined before the frame

has completely arrived, then the buffer pointer in the

next des crip tor for th e rec eiv e fram e wo uld need to b e

modified in order to direct the controller to write directly

to the application buffer. More details on this operation

will be given lat er.

An alternative modification to the existing system can

gain a smaller but still significant improvement in per-

formanc e. This alt er nati ve leav es ste p 4 unchanged in

that the C PU is s til l require d to pe rfor m the co py oper -

ation, but is allows a large portion of the copy operation

to be done before the frame has been completely re-

ceived by the controller, i.e., the CPU can perfo rm the

copy operation of the receive data from the controller’s

buffer space into the application buffer space before

the frame data has completely arrived from the net-

work. This allows the copy operation of step 4 to be

performed concurrently with the arrival of network data,

rather than sequentially, following the end of network

receive acti vity.

OUTLINE OF LAPP FLOW

This sec tion give s a suggeste d ou tli ne fo r a dr iv er tha t

utilizes the LAPP feature of the controller.

B-2 Am79C978

Note: The lab els in th e follo wing te xt ar e used as ref-

erences in the timeline diagram that follows (Figure

B-1).

Setup

The driver should set up descriptors in groups of three,

with the OWN and STP bits of each set of three de-

scriptors to read as follows: 11b, 10b, 00b.

An optio n bit (LA PPEN) exis ts in CSR3, b it pos itio n 5;

the software should set this bit. When set, the LAPPEN

bit directs the controller to generate an INTERRUPT

when STP has been written to a receive d escrip tor by

the controller.

Flow

The controller polls the current receive descriptor at

some point in time before a message arrives. The con-

troller determines that this receive buffer is OWNed by

the controller and it stores the descriptor information to

be used when a message does arrive.

N0 Fr ame pr eambl e app ears on th e wire , fol lowed

by SFD and destination address.

N1 The 64th byte of frame data arrives from the

wire. This causes the controller to begin frame

data DMA operations to the first buffer.

C0 When the 64th byte of the message arrives,

the contro ller performs a loo kahead opera tion

to the next receive descriptor. This descriptor

should be owned by the controller.

C1 The controller intermittently requests the bus

to transfer frame data to the first buffer as it ar-

rives on the wire.

S1 The driver remains idle.

C2 When the controller has completely filled the

first buffer , it writes status to the first descriptor .

C3 When the first descriptor for the frame has

been written, changing ownership from the

controller to the CPU, the controller will gener-

ate an SRP INTERRUPT. (This interrupt ap-

pears as a RINT interrupt in CSR0).

S1 The SRP INTERRUPT causes the CPU to

switch tasks to allow the controller’s driver to

run.

C4 During the CPU interrupt-generated task

switchi ng, th e control ler i s pe rfor min g a l ook a-

head operation to the third descriptor. At this

point in time, the third descriptor is owned by

the CPU.

Note: Even though the third buffer is not owned by the

controller, existing AMD Ethernet controllers will con-

tinue to perform data DMA into the buffer space that the

controller already owns (i.e., buffer number 2). The

control le r does not k now if bu ffer sp ac e i n buff er nu m-

ber 2 will be sufficient or not for this frame, but it has no

way to tell except by trying to move the entire message

into that space. Only when the message does not fit will

it signal a buffer error condition--there is no need to

panic at this point that i t discovers th at it does not yet

own descriptor number 3.

S2 The first task of the drivers interrupt service

routing is to collect the header information

from the controller’s first buffer and pass it to

the application.

S3 The application will return an application buffer

pointer to the driver. The driver will add an off-

set to the application data buffer pointer , since

the controller will be placing the first portion of

the me ssag e i nto the fi rst and se co nd buffers.

(the modified application data buffer pointer

will only be directly used by the controller when

it reaches the third buffer .) The driver will place

the modified data buffer pointer into the final

descriptor of the group (#3) and will grant own-

ership of this descriptor to the controller.

C5 Interleaved with S2, S3, and S4 driver activity,

the controller will write frame data to buffer

number 2.

S4 The driver will next proceed to copy the con-

tents of the controller’s first buffer to the begin-

ning of the application space. This copy will be

to the exact (unmodified) buffer pointer that

was passed by the application.

S5 After copying all of the data from the first buffer

into the beginning of the application data

buffer, the driver will begin to poll the owner-

ship bi t of the seco nd de scriptor. The d riv er is

waiting for the controller to finish filling the sec-

ond buffer.

C6 At this point, knowing that it had not previously

owned the third descriptor and knowing that

the current message has not ended (there is

more data in the FIFO), the controller will make

a last ditch lookahead to the final (third) de-

scriptor . This time the ownership will be TRUE

(i.e., the descriptor belongs tot he controller),

because the driver wrote the application

pointer into this descriptor and then changed

the ownership to give the descriptor to the con-

troller back at S3. Note that if steps S1, S2,

and S3 have not completed at this time, a

BUFF error will result.

C7 After filling the second buffer and performing

the last chance lookahead to the next descrip-

tor, the controller will write the status and

change the ownership bit of descriptor number

Am79C978 B-3

S6 After the ownership of descriptor number 2 has

been changed by the controller , the next driver

poll of the seco nd descriptor wil l show owner-

ship gran ted to the CPU. The driver now co p-

ies the data from buffer number 2 into the

middle s ection of the appl ication b uffer space .

This operation is interleaved with the C7 and

C8 operations.

C8 The controller will perform data DMA to the last

buffer, whos e pointer is poi nting to applica tion

space. Data entering the least buffer will not

need the infamous double copy that is required

by exis ting drivers, s ince it is be ing placed d i-

rectly into the application buffer space.

N2 The message on the wire ends.

S7 When the driver completes the copy of buffer

number 2 d ata to the a ppl ic ati on b uffer sp ace ,

it begins polling descriptor number 3.

C9 Wh en the c ontr ol ler has f inished al l d ata DMA

operations, it w rites status and chan ges own-

ership of descriptor number 3.

S8 The driv er see s that the owner ship of des c rip-

tor number 3 has changed, and it calls the ap-

plication to tell the application that a frame has

arrived.

S9 The appli cation processe s the receiv ed frame

and generates the next TX frame, placing it

into a TX buffer.

S10 The driver sets up the TX descriptor for the

controller.

B-4 Am79C978

Figure B-1. LAPP Timeline

Buffer

Ethernet

Wire

activity:

Ethernet

Controller

activity:

Software

activity:

S10: Driver sets up TX descriptor.

S9: Application processes packet, generates TX packet.

S8: Driver calls application

to tell application that

packethas arrived.

S7: Driver polls descriptor of buffer #3.

S6: Driver copies data from buffer #2 to the application

buffer.

S5: Driver polls descriptor #2.

S4: Driver copies data from buffer #1 to the application

buffer.

S3: Driver writes modified application

pointer to descriptor #3.

S2: Driver call to application to

get application buffer pointer.

S1: Interrupt latency.

S0: Driver is idle.

}

N2:EOM

N0: Packet preamble, SFD

and destination address

are arriving.

{

Packet data arriving

}

C9: Controller writes descriptor #3.

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

C7: Controller writes descriptor #2.

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2

C3: SRP interrupt is

generated.

C2: Controller writes descriptor #1.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

C0: Lookahead to descriptor #2.

N1: 64th byte of packet

data arrives.

C4: Lookahead to descriptor #3 (OWN).

22206B-B1

Am79C978 B-5

LAPP Software Requirements

Software needs to set up a receive ring with descriptors

formed into groups of three. The first descriptor of each

group should have OWN = 1 and STP = 1, the second

descriptor of each group should have OWN = 1 and

STP = 0. The third descriptor of each group should

have OWN = 0 and STP = 0. The size of the first buffer

(as indicated in the first descriptor) should be at least

equal to the largest expected header size; however , for

maximum efficiency of CPU utilization, the first buffer

size should be larger than the header size. It should be

equal to the expected number of message bytes,

minus the ti me neede d for interrup t latenc y and mi nus

the applic ation ca ll latenc y, minus the t ime nee ded for

the driver to write to the third descriptor , minus the time

needed for the drive to copy data from buffer number 2

to the application buffer space. Note that the time

needed for the copies performed by the driver depends

upon the sizes of the second and third buffers, and that

the sizes of the second and third buffers need to be set

accor ding to t he time n eeded fo r the d ata copy o pera-

tions. This means that an iterative self-adjusting mech-

anism needs to be placed into the software to

determine the correct buffer sizing for optimal opera-

tion. Fixed values for buffer sizes may be used; in such

a case, the LAP P me thod wi ll s ti ll pr o vi de a si gni ficant

performance increase, but the performance increase

will not be maximiz ed.

Figure B-2 illustrates this setup for a receive ring size

of 9.

Figure B-2. LAPP 3 Buffer Grouping

LAPP Rules for Parsing Descriptors

When using the LAPP method, software must use a

modified form of descriptor parsing as follows:

nSoftware w ill exam ine O WN and ST P to dete rmine

where an RCV fram e begi ns. RCV fr ames wi ll on ly

begin in buffers that have OWN = 0 and STP = 1.

nSoftware s hall assume th at a frame conti nues until

it finds either ENP = 1 or ERR = 1.

nSoftware must discard all descriptors with OWN = 0

and STP = 0 and move to the next descriptor when

searching for the beginning of a new frame; ENP and

ERR should be ignored by software during this

search.

nSoftware cannot change an STP value in the receive

descriptor ring after the initial setup of the ring is

complete, even if software has ownership of the STP

Descriptor

OWN = 1 STP = 1

SIZE = A-(S1+S2+S3+S4+S6)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = S6

OWN = 1 STP = 1

SIZE = A-(S1+S2+S3+S4+S6)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = S6

OWN = 1 STP = 1

SIZE = A-(S1+S2+S3+S4+S6)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = S6

A = Expected message size in bytes

S1 = Interrupt latency

S2 = Application call latency

S3 = Time needed for driver to write

to third descriptor

S4 = Time needed for driver to copy

data from buffer #1 to

application buffer space

S6 = Time needed for driver to copy

data from buffer #2 to

application buffer space

Note that the times needed for tasks S1,

S2, S3, S4, and S6 should be divided by

0.8 microseconds to yield an equivalent

number of network byte times before

subtracting these quantities from the

expected message size A.

22206B-B2

B-6 Am79C978

descriptor, unless the previous STP descriptor in the

ring is also OWNED by the software.

When LAPP E N = 1, the n har dw are wil l us e a mo di fie d

form of descrip tor parsing as follows:

nThe controller will examine OWN and STP to deter-

mine whe re to be gin p la cing an RCV f rame. A ne w

RCV frame will only begin in a buffer that has

OWN = 1 and STP =1.

nThe con troll er wi ll alwa ys obey the OWN b it fo r d e-

termining whe ther or not it may use the next buffer

for a chain.

nThe controller will always mark the end of a frame

with either ENP = 1 or ERR = 1.

The controller will discard all descriptors with OWN = 1

and STP = 0 and move to the next descriptor when

searching for a place to begin a new frame. It discards

these descriptors by simply changing the ownership bit

from OWN = 1 to OWN = 0. Such a descriptor is un-

used for receive purposes by the controller, and the

driver must recognize this. (The driver will recognize

this if it follows the software rules.)

The contr oller will ignor e all descripto rs with OWN = 0

and STP = 0 and move to the next descriptor when

searching for a place to begin a new frame. In other

words, the controller is allowed to skip entries in the

ring that it does not own, but only when it is looking for

a place to begin a new frame.

Some Examples of LAPP Descriptor

Interaction

Choo se an expect ed fram e size of 1060 bytes. Ch oose

buffer sizes of 800, 200, and 200 bytes.

nExample 1: Assume that a 1060 byte frame arrives

correctly, and that the timing of the early interrupt

and the software is smooth. The descriptors will

have change d from :

nExample 2: Assume that instead of the expected

1060 byte frame, a 900 byte frame arrives, either

because there was an error in the network, or be-

cause this is the last frame in a file transmission se-

quence.

Note: The controller might write a ZERO to ENP loca-

tion in the third descriptor. Here are the two possibili-

ties:

1. If the controller finishes the data transfers into buffer

number 2 after the driver writes the application

modified buffer pointer into the third descriptor , then

the controller will write a ZERO to ENP for this

buffer and will write a ZERO to OWN and STP.

2. If the controller finishes the data transfers into buffer

number 2 before the driver writes the applications

Descriptor

Number Before the Frame Arrives After the Frame Arrives Comments (Afte r

Frame Ar rival)

OWN STP ENPaOWN STP ENPb

1 1 1 x 0 1 0 Bytes 1-800

2 1 0 X 0 0 0 Bytes 801-1000

3 0 0 X 0 0 1 Bytes 1001-1060

4 1 1 X 1 1 X Controller’s current

location

5 1 0 X 1 0 X Not yet used

6 0 0 X 0 0 X Not yet used

etc. 1 1 X 1 1 X Net yet used

a. & b. ENP or ERR.

Descriptor

Number Before the Frame Arrives After the Frame Arrives Comments (Afte r

Frame Ar rival)

OWN STP ENPaOWN STP ENPb

1 1 1 x 0 1 0 Bytes 1-800

2 1 0 X 0 0 0 Bytes 801-1000

3 0 0 X 0 0 ?*Discarded buffer

4 1 1 X 1 1 X Controller’s current

location

5 1 0 X 1 0 X Not yet used

6 0 0 X 0 0 X Not yet used

etc. 1 1 X 1 1 X Net yet used

a. & b. ENP or ERR.

Am79C978 B-7

modified buffer point into the third descriptor, then

the controller will complete the frame in buffer num-

ber 2 and then skip the then unowned third buffer.

In this case , the con tr oll er wil l not hav e had the op-

portunity to RESET the ENP bit in this descriptor,

and it is possible that the software left this bit as

ENP = 1 from the la st ti me through the ring . Ther e-

fore, the s oftw ar e mu st tre at th e lo ca tio n as a don’t

care. The rule is, after finding ENP = 1 (or ERR = 1)

in descriptor number 2, the software must ignore

ENP bits until it finds the next STP = 1.

nExample 3: Assume that instead of the expected

1060 byte frame, a 100 byte frame arrives, because

ther e wa s an e rror in th e netw ork, o r be cause this i s

the last frame in a file transmission sequence, or

perhaps because it is an acknowledge frame.

*Same as n ote in ex am ple 2 above, e xc ept tha t i n th is

case, it is very unlikely that the driver can respond to

the interrupt and get the pointer from the application

before the co ntroller has completed its poll of the next

descriptors. This means that for almost all occurrences

of this case, the controller will not find the OWN bit set

for this descriptor and, therefore, the ENP bit will al-

most a lways c onta in the old va lue, sin ce the controll er

will not have had an opportunity to modify it.

**Note that even though the controller will write a

ZERO to this ENP location, the software should treat

the location as a don’t care, since after finding the ENP

= 1 in descriptor number 2, the software should ignore

ENP bits until it finds the next STP = 1.

Buffer Size Tuning

For maximum performance, buffer sizes should be ad-

justed depending upon the expected frame size and

the values of th e interrupt latency and application call

latency . The best driver code will minimize the CPU uti-

lization while also minimizing the latency from frame

end on the network to the frame sent to application

from driver (frame latency). These objectives are

aimed at increasing throughput on the network while

decreasing CPU utilization.

Note: The buffer sizes in the ring may be altered at

any time that the CPU has ownership of the corre-

sponding descriptor. The best choice for buffer sizes

will maximize the time that the driver is swapped out,

while minimi zing the time from the last by te written by

the controller to the t ime that the data is passed from

the driver to the ap pli ca tio n. In the di agram , this corr e-

sponds to maximizing S0, while minimizing the time be-

tween C9 and S8. (the timeline happens to show a

minimal time from C9 to S8.)

Note: By increasing the size of buffer number 1, we in-

crease the value of S0. However, when we increase

the size of buffer number 1, we also increase the value

of S4. If the size of buffer number 1 is too large, then

the driver will not have enough time to perform tasks

S2, S3, S 4, S 5, a nd S6. T he r esul t i s t hat there will be

delay from the execution of task C9 until the execution

of task S8. A per fectly timed syste m will have the val-

ues for S5 and S7 at a minimum.

An averag e increase in performance can be achieved,

if the general guidelines of buffer sizes in Figure 2 is fol-

lowed. However, as was noted earlier, the co rrect siz-

ing for buffers will depend upon the expected message

size. There are two problems with relating expected

message size with the correct buffer sizing:

1. Message sizes cannot always be accurately pre-

dicted, since a single application may expect differ-

ent message sizes at different times. Therefore, the

buffer sizes chosen will not always maximize

throughput.

2. Within a single application, message sizes might be

somewhat pr ed ic tab le, but when the sa me dr iver is

to be shared with multiple applications, there may

not be a common predictable message size.

Additional problems occur when trying to define the

correct sizing because the correct size also depends

upon the interrupt latency , which may vary from system

to system , depen di ng upo n both the hardwar e and the

software installed in each system.

In order to deal with the unpredictable nature of the

message size, the driver can implement a self-tuning

Descriptor

Number Before the Frame Arrives After the Frame Arrives Comments (Afte r

Frame Ar rival)

OWN STP ENPaOWN STP ENPb

1 1 1 x 0 1 0 Bytes 1-800

2 1 0 X 0 0 0** Discarded buffer

3 0 0 X 0 0 ? Disca rded buffer

4 1 1 X 1 1 X Controller’s current

location

5 1 0 X 1 0 X Not yet used

6 0 0 X 0 0 X Not yet used

etc. 1 1 X 1 1 X Net yet used

a. & b.ENP or ERR.

B-8 Am79C978

mechani sm that exa mines the amo unt of ti me sp ent in

tasks S5 and S7. As such, while the driver is polling for

each descriptor, it could count the number of poll oper-

ations pe rformed and the n adjust the n umber 1 buffer

size to a larger value, by adding “t” by tes to the buffer

count, if the number of poll operations was greater than

”x.” If fewer than “x” poll operations were needed for

each of S5 and S7, then software should adjust the

buffer size to a smaller value by subtracting “y” bytes

from the b uffer coun t. Experiments with s uch a tuning

mechanism must be performed to determine the best

valu es fo r “x” and “y.”

Note: Whenever the size of buffer number 1 is ad-

justed, buffer sizes for buffer number 2 and buffer num-

ber 3 should also be adjusted.

In some systems, the typical mix of receive frames on

a network for a client application consists mostly of

large data frames, with very few small frames. In this

case, for maximum efficiency of buffer sizing, when a

frame arrives under a certain size limit, the driver

should not adjust the buffer sizes in response to the

short frame.

An Alternative LAPP Flow: Two-Interru pt

Method

An alternative to the above suggested flow is to use two

interrupts, one at the start of the receive frame and the

other at the end of the receive frame, instead of just

looking for the SRP in ter rupt as des cri bed ab ov e. Th is

alternat ive attempts to redu ce the amou nt of time that

the software wastes while polling for descriptor own

bits. This time would then be available for other CPU

tasks. It also minimizes the amount of time the CPU

needs for data copying. This savings can be applied to

other CPU tasks.

The time from the end of frame arrival on the wire to de-

livery of the frame to the application is labeled as frame

latency. Fo r the one -i nte rrup t met hod , fra me l aten cy is

minimized, while CPU utilization increases. For the

two-interr upt method, frame latency becomes g reater,

while CPU utilization decreases. See Figure B-3.

Note: Some of the CPU time that can be applied to

non-Ethernet tasks is used for task switching in the

CPU. One task switch is required to swap a non-Ether-

net task into the CPU (after S7A) and a second task

switch is needed to swap the Ethernet driver back in

again (at S8A). If the time needed to perform these task

switches exceeds the time saved by not polling de-

scriptors, then there is a net loss in performance with

this method. Therefore, the LAPP method imple-

mented should be carefully chosen.

Figure B-4 shows the buffer sizing for the two-interrupt

method. N ote that the sec ond buffer size will be about

the same for each method.

There is anot her alte r nati ve wh ic h is a ma r riage of th e

two previous methods. Th is third poss ibility would use

the buffer sizes set by the two-interrupt method, but

would use the polling method of determining frame

end. This will give good fram e latency but at the pri ce

of very high CPU utilization. And still, there are even

more compromise positions that use various fixed

buffer sizes and, effectively, the flow of the one-inter-

rupt metho d. All of these c ompromi ses will re duce the

complexity of the one-interrupt method by removing the

heuristic buffer sizing code, but they all become less ef-

ficient than heuristic code would allow.

Am79C978 B-9

Figure B-3. LAPP Timeline for Two-Interrupt Method

Buffer

Ethernet

Wire

activity:

Ethernet

Controller

activity:

Software

activity:

S10: Driver sets up TX descriptor.

S9: Application processes packet, generates TX packet.

S8: Driver calls application

to tell application that

packethas arrived.

S7: Driver is swapped out, allowing a non-Ethernet

application to run.

S6: Driver copies data from buffer #2 to the application

buffer.

S5: Driver polls descriptor #2.

S4: Driver copies data from buffer #1 to the application

buffer. S3: Driver writes modified application

pointer to descriptor #3.

S2: Driver call to application to

get application buffer pointer.

S1: Interrupt latency.

S0: Driver is idle.

}

N2:EOM

N0: Packet preamble, SFD

and destination address

are arriving.

{

Packet data arriving

}

C9: Controller writes descriptor #3.

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

C7: Controller writes descriptor #2.

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2

C3: SRP interrupt is

generated.

C2: Controller writes descriptor #1.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

C0: Lookahead to descriptor #2.

N1: 64th byte of packet

data arrives.

C10: ERP interrupt

is generated. }S8A: Interrupt latency.

}

S7A: Driver Interrupt Service

Routine executes

RETURN.

C4: Lookahead to descriptor #3 (OWN).

22206B-B3

B-10 Am79C978

Figure B-4. LAPP 3 Buffer Grouping for Two-interrupt Method

Descriptor

OWN = 1 STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

OWN = 1 STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

OWN = 1 STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

A = Expected message size in bytes

S1 = Interrupt latency

S2 = Application call latency

S3 = Time needed for driver to write

to third descriptor

S4 = Time needed for driver to copy

data from buffer #1 to

application buffer space

S6 = Time needed for driver to copy

data from buffer #2 to

application buffer space

Note that the times needed for tasks S1,

S2, S3, S4, and S6 should be divided by

0.8 microseconds to yield an equivalent

number of network byte times before

subtracting these quantities from the

expected message size A.

22206B-B4

Am79C978 1
Numerics
1 Mbps HomePNA PHY Internal Registers 179
1 Mbps HomePNA PHY Management Registers
214
10 Mbps Receive (RX±) Timing Diagram 227
10 Mbps Transmit (TX±) Timing Diagram 227
10/100 Mbps operation 2
10/100 Media Access Control 65
10/100 Media Access Controller 65
10BASE-T 227
10BASE-T Block 98
10BASE-T I/O Buffer Power 32
10BASE-T Mode 224
10BASE-T PDX Analog Ground 32
10BASE-T PDX Block Power 32
10BASE-T PDX Digital Ground 32
10BASE-T PHY Management Registers 213
10BASE-T PHY Management Registers (TBRs)
179
10BASE-T Physical Layer 98
14795
Tabtle
Table 44. R/TLEN Decoding (SSIZE32 =
0) 199
16937
Tabtle
Table 36. Software Styles 163
16-Bit Software Model 61
24958
Tabtle
Table 26. Software Styles 135
24981
Tabtle
Table 35. Interface Pin Assignment 161
C/BE 26
RXD 30
TXD 30
AD 26
31439
Tabtle
Table 25. Loopback Configuration 128
32-Bit Software Model 62
34313
Tabtle
Table 19. Table 18. PCI Configuration
Space Layout 95
38779
Tabtle
Table 49. Transmit Descriptor (SW-
STYLE = 0) 203
40675
TblTitlew
Table 13.  MII Control Frame Format 81
41807
TblTitle
Table 11.  Master Station Control Word
Functions 81
A
Absolute Maximum Ratings 220
ACCESS ID Intervals 76
ACCESS ID Values 78
Address and Data 26
Address Match Logic 200
Address Matching 71
Address Parity Error Response 41
Address PROM Space 96
Advanced Configuration and Power Interface
(ACPI) specification 1
Advanced Parity Error Handling 52
AID Receive Timing 78
AID Transmit Timing 78
Alternative Method for Initialization 1
Am79C978 10BASE-T PHY Management Regis-
ter Set 188
Am79C978 Programmable Register 215
An Alternative LAPP Flow
Two-Interrupt Method 8
Analog PLL Power 32
ANR6
Auto-Negotiation Expansion Register (Regis-
ter 6) 194
APDW Values 169
APP 3 Buffer Grouping for Two-interrupt Method
10
Automatic EEPROM Read Operation 84
Automatic Pad Generation 69
Automatic Pad Stripping 72
Automatic PREAD EEPROM Timing 232
Auto-Negotiation 99
Auto-Negotiation Capabilities 99
Auto-Poll™ 1
B
Basic Burst Read Transfer 43
Basic Burst Write Transfer 45
Basic Non-Burst Read Transfer 43
Basic Non-Burst Write Transfer 45
BCR Registers 146
BCR0

2Am79C978
Master Mode Read Active 145
BCR1
Master Mode Write Active 145
BCR16
I/O Base Address Lower 155
BCR17
I/O Base Address Upper 155
BCR18
Burst and Bus Control Register 156
BCR19
EEPROM Control and Status 158
BCR2
Miscellaneous Configuration 145
BCR20
Software Style 161
BCR22
PCI Latency Register 163
BCR23
PCI Subsystem Vendor ID Register 163
BCR24
PCI Subsystem ID Register 164
BCR25
SRAM Size Register 164
BCR26
SRAM Boundary Register 164
BCR27
SRAM Interface Control Register 165
BCR28
Expansion Bus Port Address Lower (Used for
Flash/EPROM and SRAM Accesses)
166
BCR29
Expansion Port Address Upper (Used for
Flash/EPROM Accesses) 167
BCR30
Expansion Bus Data Port Register 167
BCR31
Software Timer Register 168
BCR32
PHY Control and Status Register 168
BCR32 PHY Control and Status Register 168
BCR33
PHY Address Register 170
BCR34
PHY Management Data Register 171
BCR35
PCI Vendor ID Register 171
BCR36
PCI Power Management Capabilities (PMC)
Alias Register 172
BCR37
PCI DATA Register Zero (DATA0) Alias
Register 172
BCR38
PCI DATA Register 1 (DATA1) Alias Regis-
ter 172
PCI DATA Register One (DATA1) Alias Reg-
ister 172
BCR39
PCI DATA Register 0 (DATA2) Alias Regis-
ter 172
PCI DATA Register Two (DATA2) Alias
Register 172
BCR4
LED 0 Status 147
BCR40
PCI DATA Register 3 (DATA3) Alias Regis-
ter 173
PCI Data Register Three (DATA3) Alias Reg-
ister 173
BCR41
PCI DATA Register 4 (DATA4) Alias Regis-
ter 173
BCR42
PCI DATA Register 5 (DATA5) Alias Regis-
ter 174
PCI DATA Register Five (DATA5) Alias
Register 174
BCR43
PCI DATA Register 6 (DATA6) Alias Regis-
ter 174
BCR44
PCI DATA Register Seven (DATA7) Alias
Register 174
PCI DATA Register7 (DATA7) Alias Regis-
ter 174
BCR45
OnNow Pattern Matching Register 1 175
BCR46
OnNow Pattern Matching Register 2 175
BCR47
OnNow Pattern Matching Register #3 176
OnNow Pattern Matching Register 3 176
BCR48
LED4 Status 176
BCR49
PHY Select 178
BCR5

Am79C978 3
LED1 Status 149
BCR50-BCR55
Reserved Locations 178
BCR6
LED2 Status 151
BCR7
LED3 Status 153
BCR9
Full-Duplex Control 155
Blanking Interval Speed Settings 79
BLOCK DIAGRAM 4
Block Diagram Low Latency Receive Configura-
tion 83
Block Diagram No SRAM Configuration 82
Board Interface 28
Boundary Scan Circuit 91
Boundary Scan Register 91
BSR Mode Of Operation 91
Buffer Management 60
Buffer Management Unit 3, 59
Buffer Size Tuning 7
Burst FIFO DMA Transfers 57
Burst Write Transfer 46
Bus Acquisition 42, 43
Bus Command and Byte Enables 26
Bus Configuration Registers 145, 212, 217
Bus Configuration Registers (BCRs) 145
Bus Grant 26
Bus Master DMA Transfers 43
Bus Request 27
by Driver Type 24
C
CLK 26
CLK Waveform for 3.3 V Signaling 230
CLK Waveform for 5 V Signaling 230
CLK_FAC Values 166
Clock 26
Clock Interface 31
Clock Timing 222, 225
COL 30
Collision 30
Collision Detect Function 99
Collision Handling 68
CONNECTION DIAGRAM (144 TQFP) 16
CONNECTION DIAGRAM (160 PQFP) 17
Contents 5
Control and Status Registers 112, 208, 215
CRS 30
Crystal 32
Crystal Oscillator In 32
Crystal Oscillator Out 32
CSR0
Controller Status and Control Register 112
CSR1
Initialization Block Address 0 115
CSR10
Logical Address Filter 2 125
CSR100
Bus Timeout 141
CSR11
Logical Address Filter 3 126
CSR112
Missed Frame Count 142
CSR114
Receive Collision Count 142
CSR116
OnNow Power Mode Register 142
CSR12
Physical Address Register 0 126
CSR122
Advanced Feature Control 143
CSR124
Test Register 1 143
CSR125
MAC Enhanced Configuration Control 144
CSR13
Physical Address Register 1 126
CSR14
Physical Address Register 2 126
CSR15
Mode 127
CSR16
Initialization Block Address Lower 128
CSR17
Initialization Block Address Upper 128
CSR18
Current Receive Buffer Address Lower 128
CSR19
Current Receive Buffer Address Upper 128
CSR2
Initialization Block Address 1 115
CSR20
Current Transmit Buffer Address Lower 129
CSR21
Current Transmit Buffer Address Upper 129
CSR22
Next Receive Buffer Address Lower 129
CSR23

4Am79C978
Next Receive Buffer Address Upper 129
CSR24
Base Address of Receive Ring Lower 129
CSR25
Base Address of Receive Ring Upper 129
CSR26
Next Receive Descriptor Address Lower 129
CSR27
Next Receive Descriptor Address Upper 130
CSR28
Current Receive Descriptor Address Lower
130
CSR29
Current Receive Descriptor Address Upper
130
CSR3
Interrupt Masks and Deferral Control 115
CSR30
Base Address of Transmit Ring Lower 130
CSR31
Base Address of Transmit Ring Upper 130
CSR32
Next Transmit Descriptor Address Lower 130
CSR33
Next Transmit Descriptor Address Upper 130
CSR34
Current Transmit Descriptor Address Lower
131
CSR35
Current Transmit Descriptor Address Upper
131
CSR36
Next Next Receive Descriptor Address Lower
131
CSR37
Next Next Receive Descriptor Address 131
Next Next Receive Descriptor Address Upper
131
CSR38
Next Next Transmit Desc riptor Address Low -
er 131
CSR39
Next Next Transmit Descriptor Address Upper
131
CSR4
Test and Features Control 118
CSR40
Current Receive Byte Count 131
CSR41
Current Receive Status 132
CSR42
Current Transmit Byte Count 132
CSR43
Current Transmit Status 132
CSR44
Next Receive Byte Count 132
CSR45
Next Receive Status 132
CSR46
Transmit Poll Time Counter 132
CSR47
Transmit Polling Interval 133
CSR48
Receive Poll Time Counter 133
CSR49
Receive Polling Interval 133
CSR5
Extended Control and Interrupt 1 119
CSR58
Software Style 134
CSR6
RX/TX Descriptor Table Length 122
CSR60
Previous Transmit Descriptor Address Lower
136
CSR61
Previous Transmit Descriptor Address Upper
135, 136
CSR62
Previous Transmit Byte Count 136
CSR63
Previous Transmit Status 136
CSR64
Next Transmit Buffer Address Lower 136
CSR65
Next Transmit Buffer Address Upper 136
CSR66
Next Transmit Byte Count 137
CSR67
Next Transmit Status 137
CSR7
Extended Control and Interrupt 2 122
CSR72
Receive Ring Counter 137
CSR74
Transmit Ring Counter 137
CSR76
Receive Ring Length 137

Am79C978 5
CSR78
Transmit Ring Length 137
CSR8
Logical Address Filter 0 125
CSR80
DMA Transfer Counter and FIFO Threshold
Control 138
CSR82
Transmit Descriptor Address Pointer Lower
140
CSR84
DMA Address Register Lower 140
CSR85
DMA Address Register Upper 140
CSR86
Buffer Byte Counter 140
CSR88
Chip ID Register Lower 141
CSR89
Chip ID Register Upper 141
CSR9
Logical Address Filter 1 125
CSR92
Ring Length Conversion 141
Cycle Frame 26
D
Data Receive Timing 79
Data Symbol RLL25 Encoding 80
Data Symbols 79
Data Transmit Timing 79
DC CHARACTERISTICS OVER COMMER-
CIAL OPERATING RANGES 220
DC CHARACTERISTICS OVER COMMER-
CIAL OPERATING RANGES unless otherwise
specified 220
Description of the Methodology 81
Descriptor DMA Transfers 54
Descriptor Ring Read In Burst Mode 55
Descriptor Ring Write In Burst Mode 56
Descriptor Ring Write In Non-Burst Mode 56
Descriptor Rings 60
Destination Address Handling 66
Detailed Functions 75
Device ID Register 91
Device Select 26
DEVSEL 26
Digital Ground (8 Pins) 32
Digital I/O (Non-PCI Pins) 220
Digital Power (6 Pins) 32
Direct Access to the Interface 84
Direct Memory Access (DMA) 2
Direct SRAM Access 82
Disconnect Of Burst Transfer 40
Disconnect Of Slave Burst Transfer - Host Inserts
Wait States 41
Disconnect Of Slave Burst Transfer - No Host
Wait States 40
Disconnect Of Slave Cycle When Busy 40
Disconnect When Busy 40
Disconnect With Data Transfer 46, 47
Disconnect Without Data Transfer 47, 48
DISTINCTIVE CHARACTERISTICS 1
Double Word I/O Mode 97
DVDDA 32
DVDDA_HR 32
DVDDD 32
DVDDRX, DVDDTX 32
DVSSD 32
DVSSX 32
E
EBCS Values 166
EECS 29
EEDET Setting 161
EEDI 29
EEDO 29
EEPROM 86
EEPROM Auto-Detection 84
EEPROM Chip Select 29
EEPROM Data In 29
EEPROM Data Out 29
EEPROM Interface 29, 83, 84
EEPROM MAP 85
EEPROM Map 86
EEPROM Read Functional Timing 231
EEPROM Serial clock 30
EEPROM Timing 223
EEPROM-Programmable Registers 84
EESK 30
Error Detection 66
escriptor Ring Read In Non-Burst Mode 55
Ethernet controllers in the PCnet Family 3
Ethernet Network Interfaces 31
Expansion ROM Read 39
Expansion ROM Transfers 39
External Clock 225
External Clock/Crystal Select 31
F
FIFO Burst Write At End Of Unaligned Buffer 58

6Am79C978
FIFO Burst Write  At Start Of Unaligned  Buffer 58
FIFO DMA Transfers 57
Flow, LAPP 2
FMDC Values 169
FRAME 26
Frame Format at the MII Interface Connection 35
Framing 65, 75
Full-Duplex Link Status LED Support 74
Full-Duplex Operation 73
G
GENERAL DESCRIPTION 2
GNT 26
H
H_RESET 94
Header AID Remote Control W ord Commands 81
Home Networking Controller 1
Home Phoneline Networking Alliance (HomeP-
NA) 1
HomePNA Analog Ground 32
HomePNA Analog Power 32
HomePNA Digital Power 32
HomePNA PHY Framing 76
HomePNA PHY Network Interface 31
HomePNA Physical Layer (PHY) 1
HPR0
HomePNA PHY MII Control (Register 0) 179
HPR1
HomePNA PHY MII Status (Register 1) 180
HPR16
HomePNA PHY Control (Register 16) 182,
183
HPR18 and HPR19
HomePNA PHY TxCOMM (Registers 18 and
19) 183
HPR2 and HPR3
HomePNA PHY MII PHY ID (Registers 2 and
3) 181
HPR20 and HPR21
HomePNA PHY RxCOMM (Registers 20 and
21) 184
HPR22
HomePNA PHY AID (Register 22) 184
HPR23
HomePNA PHY Noise Control (Register 23)
184
HPR24
HomePNA PHY Noise Control 2 (Register 24)
185
HPR25
HomePNA PHY Noise Statis tics (Regis ter 25)
185
HPR26
HomePNA PHY Event Status (Register 26)
186
HPR27
HomePNA PHY Event Status (Register 27)
186
HPR28
HomePNA PHY ISBI Control (Register 28)
186
HPR29
HomePNA PHY TX Control (Register 29) 187
HPR4-HPR7
HomePNA PHY Auto-Negotiation (Registers
4 - 7) 181
HRTXRXP/HRTXRXN 31
I
I/O Buffer Ground (17 Pins) 32
I/O Buffer Power (7 Pins) 32
I/O Map In DWord I/O Mode (DWIO = 1) 98
I/O Map in DWord I/O Mode (DWIO = 1) 98
I/O Map In Word I/O Mode (DWIO = 0) 97
I/O Registers 96
I/O Resources 95
IDSEL 26
IEEE 1149.1 (1990) Test Access Port Interface 31,
91
IEEE 1149.1 Supported Instruction Summary 91
IEEE 802.3 Frame And Length Field Transmis-
sion Order 73
IEEE 802.3u 2
Initialization 59
Initialization Block 198
Initialization Block (SSIZE32 = 0) 198
Initialization Block (SSIZE32 = 1) 198
Initialization Block DMA Transfers 52
Initialization Block Read In Burst Mode 53
Initialization Block Read In Non-Burst Mode 53
Initialization Device Select 26
Initiator Ready 27
Input Setup and Hold Timing 230
Instruction Register and Decoding Logic 91
INTA 27
Integrated Controllers 15
integrated PCI Ethernet controller 2
Integrated Repeater/Hub Devices 15
Inter Packet Gap (IPG) 2
Interface Pin Assignment 161

Am79C978 7
Interrupt Request 27
Introduction 1
IRDY 27
IREF 31
J
Jabber Function 99
JAM Signal 78
JTAG (IEEE 1149.1) TCK Waveform for 5 V Sig-
naling 232
JTAG (IEEE 1149.1) Test Signal Timing 223, 233
K
Key to Switching Waveforms 229
L
LADRF 199
LAPP 3 Buffer Grouping 5
LAPP Software Requirements 5
LAPP Timeline 4
LAPP Timeline for Two-Interrupt Method 9
Late Collision 70
LED Control Logic 87
LED Default Configuration 87
LED Support 85
LED0 28
LED1 29
LED2 29
LED3 29
LED4 29
Legal I/O Accesses in Double Word I/O Mode
(DWIO =1) 98
Legal I/O Accesses in Word I/O Mode (DWIO =
0) 97
Link Change Detect 88
listed by Group 20
Look-Ahead Packet Processing (LAPP) 2
Look-Ahead Packet Processing (LAPP) Concept 1
Loopback Configuration 128
Loopback Operation 73
Loss of Carrier 70
Low Latency Receive Configuration 82
M
MAC 65, 66, 67
Magic Packet Mode 89
Magic Packet™ mode 1
magnetics module. IREF 31
Management Cycle Timing 228
Management Data Clock 31
Management Data Input/Output 31
Management Data Output Valid Delay Timing
235
Management Data Setup and Hold Timing 235
Management Interfaces 80
Manchester Encoder/Decoder 15
Master Abort 49, 51
Master Bus Interface Unit 42
Master Cycle Data Parity Error Response 51
Master Initiated Termination 48
MDC 31
MDC Waveform 234
MDIO 31
Media Access Controller (MAC) 1, 2
Media Access Management 67
Media Independent Interface 33
Medium Allocation 67
Microsoft OnNow 2
MII Interface 30
MII interface 2
MII Management Frames 35
MII Management Interface 34
MII Network Status Interface 34
MII Receive Interface 34
MII Transmit Interface 33
Miscellaneous Loopback Features 73
Mode 199
N
NAND Tree Circuitry 92
NAND Tree Circuitry (160 PQFP 92
NAND Tree Circuitry (160 PQFP) 92
NAND Tree Pin Sequence (144 TQFP) 93
NAND Tree Pin Sequence (160 PQFP) 93
NAND Tree Testing 92
NAND Tree Waveform 94
Network Interfaces 33
Network Port Manager 36
Non-Burst FIFO DMA Transfers 57
Non-Burst Read Transfer 44
Non-Burst Write Transfer 45
Normal and Tri-State Outputs 229
O
Offset 00h 102
Offset 02h 102
Offset 04h 103
Offset 06h 104
Offset 08h 105
Offset 09h 105
Offset 0Ah 105
Offset 0Bh 106
Offset 0Dh 106
Offset 0Eh 106

8Am79C978
Offset 10h 106
Offset 14h 107
Offset 2Ch 107
Offset 2Eh 107
Offset 30h 108
Offset 34h 108
Offset 3Ch 108
Offset 3Dh 109
Offset 3Eh 109
Offset 3Fh 109
Offset 40h 109
Offset 41h 109
Offset 42h 109
Offset 44h 110
Offset 46h 111
Offset 47h 111
OnNow Functional Diagram 88
OnNow Pattern Match Mode 88
OnNow Wake-Up Sequence 87
Operating Ranges 220
ordering information 25
Other Data Registers 91
Outline of LAPP Flow 1
Output and Float Delay Timing 222
Output Tri-State Delay Timing 231
Output Tri-state Delay Timing 231
Output Valid Delay Timing 231
P
PADR 199
PAR 27
Parity 27
Parity Error 27
Parity Error Response 41, 49
Pattern Match RAM 90
Pattern Match RAM (PMR) 88
PCI and JTAG Configuration Information 36
PCI Base-Class Register Offset 0Bh 106
PCI Bus Interface Pins - 3.3 V Signaling 220
PCI Bus Interface Pins - 5 V Signaling 220
PCI Bus Power Management Interface specifica-
tion 2
PCI Capabilities Pointer Register 108
PCI Capability Identifier Register 109
PCI Command Register 103
PCI Command Register Offset 04h 103
PCI Configuration Registers 95, 101, 102, 207
PCI Configuration Space Layout 95
PCI Data Register 111
PCI Data Register Offset 47h 111
PCI Device ID Register 102
PCI Device ID Register Offset 02h 102
PCI Expansion ROM Base Address Register 108
PCI Header Type Register 106
PCI Header Type Register Offset 0Eh 106
PCI I/O Base Address Register 106
PCI I/O Base Address Register Offset 10h 106
PCI I/O Buffer Power (9 Pins) 32
PCI Interface 26
PCI Interrupt Line Register 108
PCI Interrupt Line Register Offset 3Ch 108
PCI Interrupt Pin Register 109
PCI Latency Timer Register 106
PCI MAX_LAT Register 109
PCI Memory Mapped I/O Base Address Register
107
PCI MIN_GNT Register 109
PCI Next Item Pointer Register 109
PCI Next Item Pointer Register Offset 41h 109
PCI PMCSR Bridge Support Extensions Register
111
PCI PMCSR Bridge Support Extensions Register
Offset 46h 111
PCI Power Management Capabilities Register
(PMC) 109
PCI Power Management Control/Status Register
(PMCSR) 110
PCI Programming Interface Register 105
PCI Programming Interface Register Offset 09h
105
PCI Revision ID Register 105
PCI Status Register 104
PCI Status Register Offset 06h 104
PCI Sub-Class Register 105
PCI Sub-Class Register Offset 0Ah 105
PCI Subsystem ID Register 107
PCI Subsystem Vendor ID Register 107
PCI Vendor ID Register 102
PCI Vendor ID Register Offset 00h 102
PECL 225
PERR 27
PG 28
PHY Control and Management Block (PCM
Block) 81
PHY Select Programming 158
PHY/MAC Interface 74
PHY_RST 31
PHYSICAL DIMENSIONS 236
Physical Layer Devices (Multi-Port) 15

Am79C978 9
Physical Layer Devices (Single-Port) 15
Pin Capacitance 221
Pin Descriptions 26
PIN DESIGNATIONS 24
PIN DESIGNATIONS (PQL144 20
PIN DESIGNATIONS (PQL144) 18
PIN DESIGNATIONS (PQR160) 19
listed by Group 22
PMD Interface 225
PMD Interface Timing (PECL) 226
PME 28
Polling 62
Power Good 28, 31
Power Management Event 28
Power Management Support 87
Power on Reset 95
Power Savings Mode 87
Power Supply Current 221, 224
Power Supply Pins 32
PQL144 236
PQR160 237
Preemption During Burst Transaction 48, 50
Preemption During Non-Burst Transaction 48, 50
R
RAP
Register Address Port 112
RAP Register 111
RDRA and TDRA 199
Receive Address Match 72
Receive Carrier Sense 30
Receive Clock 30
Receive Data 30
Receive Data Valid 30
Receive Descriptor (SWSTYLE = 0) 200
Receive Descriptor (SWSTYLE = 2) 200
Receive Descriptor (SWSTYLE = 3) 200
Receive Descriptor Table Entry 64
Receive Descriptors 200
Receive Exception Conditions 72
Receive FCS Checking 72
Receive Frame Queuing 64
Receive Function Programming 70
Receive Operation 70
Receive Symbol Timing 79
Receive Timing 228, 234
Receive Watermark Programming 138
Register Administration for 10BASE-T PHY De-
vice 81
Register Programming Summary 215
Register Summary 207
Re-Initialization 59
RELATED AMD PRODUCTS 15
REQ 27
Reserved Register
10BASE-T Carrier Status Register (Register
23) 197
10BASE-T Configuration Register (Register
22) 197
Reserved Registers
HPR8 - HPR15, HPR17 181
Reserved Registers (Registers 8-15, 18, 20-23, and
25-31) 194
Reset 28, 94
Reset Register 96
Reverse Polarity Detect 99
RLEN and TLEN 198
RLL 25 Coding Tree 80
RMD0 200, 201
RMD1 201
RMD2 202
RMD3 203
ROMTNG Programming Values 156
RST 28
Running Registers 102
RWU 29
RX_CLK 30
RX_DV 30
RX_ER 30
RX± 31
S
S_RESET 94
Serial Receive Data 31
Serial Transmit Data 31
SERR 28
Setup 2
Setup and Hold Timing 222
Setup Registers 101
Silence Interval (AID symbol 7) 78
Slave Bus Interface Unit 36
Slave Configuration Read 38
Slave Configuration Transfers 36
Slave Configuration Write 38
Slave Cycle Data Parity Error Response 42
Slave Cycle Termination 39
Slave I/O Transfers 37
Slave Read Using I/O Command 38
Slave Write Using Memory Command 39
Soft Reset Function 100

10 Am79C978
Software 163
Software Access 95
Software Interface 33
Software Interrupt Timer 65
Some Examples of LAPP Descriptor Interaction 6
SQE Test Error 70
SR2
Initialization Block Address 1 115
SRAM_BND Programming 165
Standard Products 25
STOP 28, 96
Stop 28
Supported Instructions 91
Suspend 59
Switching Characteristics
Bus Interface 222
Media Independent Interface 228
Switching Test Circuits 229
SWITCHING WAVEFORMS 229
Switching Waveforms
Expansion Bus Interface 236
General-Purpose Serial Interface 236
Media Independent Interface 234, 236
System Bus Interface 230
Symbol 0 (SYNC interval) 76
SYNC Receive Timing 76
SYNC Transmit Timing 76
System Bus Interface 33
System Error 28
T
TAP Finite State Machine 91
Target Abort 47, 49
Target Initiated Termination 46
Target Ready 28
TBR0
10BASE-T PHY Control Register (Register 0)
189
TBR16
10BASE-T INTERRUPT Status and Enable
Register (Register 16) 195
TBR17
10BASE-T PHY Control/Status Register
(Register 17) 196
TBR19
10BASE-T PHY Management Extension Reg-
ister (Register 19) 197
TBR2 191
10BASE-T PHY Identifier (Register 2) 191
TBR24
10BASE-T Summary Status Register (Regis-
ter 24) 197
TBR3
10BASE-T PHY Identifier (Register 3) 191
TBR4
10BASE-T Auto-Negotiation Advertisement
Register (Register 4) 192
TBR5
10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5) 193
10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5) - Base
Page Forma 193
10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5) - Next
Page Format 193
TBR6
10BASE-T Auto-Negotiation Expansion Reg-
ister (Register 6) 194
TBR7
10BASE-T Auto-Negotiation Next Page Reg-
ister (Register 7) 194
TCK 31
TDI 31
TDO 31
Test Clock 31
Test Data In 31
Test Data Out 31
Test Mode Select 31
Test Registers 102
Time 76
Time Interval Unit 76
TMD0 204
TMD1 204
TMD2 205
TMD3 206
TMS 31
Transmit and Receive Message Data Encapsula-
tion 65
Transmit Clock 30
Transmit Data 30
Transmit Data Symbol Timing 79
Transmit Descriptor (SWSTYLE = 2) 203
Transmit Descriptor (SWSTYLE = 3) 203
Transmit Descriptor Table Entry 63
Transmit Descriptors 203
Transmit Enable 31
Transmit Exception Conditions 70
Transmit FCS Generation 70

Am79C978 11
Transmit Function Programming 68
Transmit Operation 68
Transmit Start Point Programming 139
Transmit Timin 234
Transmit Timing 228, 234
Transmit Watermark Programming 140
TRDY 28
Twisted Pair Interface Status 98
Twisted Pair Receive Function 98
TX+, TX- 31
TX_CLK 30
TX_EN 31
U
USER ACCESSIBLE REGISTERS 101
V
VDD 32
VDD_PCI 32
VDDB 32
VDDCO 32
VDDHR 32
VSS 32
VSSB 32
VSSHR 32
W
Word I/O Mode 96
X
XCLK/XTAL 31
XTAL1 32
XTAL2 32