TUPP to LXT6251/6051
Adaptation in ADM Mode
Application Note
January 2001
Order Number: 249310-001
As of January 15, 2001, this document replaces the Level One document known as AN9906.
Application Note
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to the m.
The LXT6251/6051 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current char acte rized errata are available on requ est.
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Application Note 3
TUPP to LXT6251/6051 Adaptation in ADM Mode
Contents
1.0 TUPP to lxt6251/6051 Adaptation in ADM Mode............................................5
2.0 Detailed Description..................................................................................................7
3.0 Code Implementation .............................................................................................11
3.1 TOP.vhd..............................................................................................................11
3.2 RCORE.vhd.........................................................................................................12
3.3 INTNM.vhd..........................................................................................................12
3.4 DRETTG.vhd.......................................................................................................13
3.5 INTAZ.vhd...........................................................................................................13
3.6 Output Timings....................................................................................................13
3.7 Board Implem enta tio n ........................... ...... ....... ................... ....... ................... ....14
Figures
1 Block Diagram Master Element.............................................................................6
2 Block Diagram = Non-master................................................................................6
3 FPGA/EPLD1-A (and FPGA/EPLD2-A) ................................................................7
4 Expected Timings at TUPP Input Side..................................................................8
5 Provided Timings from LXT6051...........................................................................9
6 FPGA/EPLD1-B (FPGA/EPLD2-B) .......................................................................9
7 LXT6251 Rx Telecom Bus Timings.....................................................................10
8 TUPP Output Timings .........................................................................................10
9 VHDL Top Level Diagrams..................................................................................11
10 VHDL Block Diagram ..........................................................................................12
11 LXT6051 to TUPP adaptation .............................................................................13
12 TUPP to LXT6251 adaptation showing V1 byte..................................................14
13 TUPP to LXT6251 Adaptation Showing H4=00 ..................................................14
14 Board Implem enta tio n ........................... ...... ....... ................... ....... ................... ....15
TUPP to LXT6251/6051 Adaptation in ADM Mode
Application Note 5
1.0 TUPP to lxt6251/6051 Adaptation in ADM Mode
The current SDH/SONET solution provided by Intel, the LXT6051 and LXT6251, requires
external circuitry in order to implem ent a ring type netwo rk. Several options, such as FPGA or
other circuits, are available for the implementation of this external circuit.
This document will f ocus o n onl y one of these sol ution s: u sing the TUPP chip from PMC-Sierra
with an FPGA. This circuit will provide a complete system solution for customers using Intel SDH/
SONET chip-set in a ring architecture system.
In a ring architecture each element of the ring are ADM (Add and Drop Multiplexer) elements.
The characteristics of such elements are:
•Tributary data can be extracted and inserted via mapper type of devices.
•The entire traffic or the traffic that is not processed by a mapper for access purposes is
supposed to pass through untou c hed in the elem ent in order to main tain traffic continuity. A
key factor here is that the traf fic passes throu gh the element keeping its timing ch aracteristics,
i.e. clock phase and pointer value.
The head-end element, which provides the timings for the whole loop, needs to include a PMC
Sierra chip called the TUPP. This chip provide timing reference for the multiframe alignment via
the H4 byte and also provides pointer initialization for all the TU-12 in the payload envelope.
Because timings are maintained in each of the ADM elementsin a ring architecture, one of the
elements has to act as the master timing gen erator in order to initia lize the ring with a correct mode
of operatio n.
Because of differences between PMC TUPP and Intel’s LXT6051/LXT6251 Telecom Bus format,
some adaptation is required for interconnectivity between the three chips. An FPGA (or EPLD)
device is used to implement this ad apt ation as shown below:
TUPP to LXT6251/6051 Adaptation in ADM Mode
6Application Note
None of the other ADM elements in the ring requir e any tim ing initialization, therefore the
architecture of these nodes is a straight forward connection between the LXT6051 OHT chip and
the LXT6251 Mapper chip as shown in Figure 2.
Figure 1. Block Diagram Master Element
FPGA/EPLD
1-A TUPP FPGA/EPLD
1-B
FPGA/EPLD
2-B TUPP FPGAEPLD
2-A
LXT6051 LXT6051
LXT6251
LXT6251
Rx
Tx
Tx
Rx
STM-1
STM-1
19.44MHz
Ref clock
E1
E1
FPGA/EPLD 1 = FPGA/EPLD 1-A + FPGA/EPLD 1-B
FPGA/EPLD 2 = FPGA/EPLD 2-A + FPGA/EPLD 2-B
FPGA 1 = FPGA 2
Figure 2. Block Diagram = Non-master
LXT6251
LXT6051 LXT6051
LXT6251
Rx
Tx
Tx
Rx
STM-1
STM-1
E1
E1
TUPP to LXT6251/6051 Adaptation in ADM Mode
Application Note 7
2.0 Detailed Description
The implementation of the timing adaptation as described in Figure 2 requires a two-step process:
•Telecom bus adaptation between OHT bus and TUPP bus.
•Telecom bus adaptation between TUPP and Mapper bus.
•The same adaptation is needed for both directions of the bi-directional ring structure.
Note that FPGA/EPLD1 -A and FPGA/EPLD1-B codes will be implemented in the sam e phy sical
chip, FPGA 1. Note also that the implemen tation of FPGA/EPLD2-A and FPGA/EPLD2-B code is
identical as FPGA/EPLD1 - A and FPGA/EPLD1-B and will be implemented in the sam e physical
chip, FPGA 2.
The LXT6051 is configured to implement Rx retiming function in order to synchronize all the
timings to the local Rx reference clock. DRETCLK the 19.44 MHz clock and DRETFRMI 8KHz
clock from the FPGA-A are provided to the OHT to perform the receive retiming.
The telecom bus output format of the LXT6051 should be set for DTBJ0J1EN single pulse.
The TUPP device has two software options (OTMFH4 & ITMFH4) for the expected multiframe
indication signal format:
•Multiframe indication is done by identifying the H4 byte (XTMFH4=1).
•Multiframe indication is don e by identif y ing th e third byte after J1 (equivalent to V1 byte).
All the following circuitry developed such that:
-ITMFH4 = 0
-OTMFH4 = 1
Figure 3. FPGA/EPLD1-A (and FPGA/EPLD2-A)
Rx
LXT6051
FPGA-A
DTBDATA
DTBCK
DTBJ0J1EN
DTBPAYEN
DTBH4EN
19.44MHz
Ref clock
DRETCLK
DRETFRMI
FPGA-A TUPP
ID
SCLK
IC1J1
IPL
ITMF
OTMF
OC1J1
OPL
OTMFH4=1
ITMFH4=0
ITMFEN=1
OTMFEN=1
DTBDATA
DTBCK
DTBJ0J1EN
DTBPAYEN
DTBH4EN
DRETFRMI
DRETCLK
RcvRetimDsbl=0
RcvTbJ0J1Cnfg=0
dtbdata_i
dtbck
dtbj0j1en-i
dtbpayen_i
dtbh4en_i
dretfrmi
dretclk
reset
id
sclk
ic1j1
ipl
itmf
otmf
oc1j1
opl
RESET
TUPP to LXT6251/6051 Adaptation in ADM Mode
8Application Note
Two functions are implemented in th is FPGA/EPLD:
Timing adaptation
The FPGA needs to pro vide th e V1 location timing signal (ITMF) to the TUPP. This is done by
extracting the V1 information from the telecom bus provided by the OHT. This circuit function
consist of 3 DFF for signal detection as well as some glue logic.
Before sending the data and timings out to the TUPP, it is necessary to re-synchronize all data and
timing signals through a DFF in order to realign data VS timings. This function will require 11
DFF.
Time base
The FPGA needs to pro vide the new multiframe (OMF), J0J1 (OC1J1) and pay load ( OTPL)
indication signals. This block will be implemented by using a 2430 bit counter associated with a 4
bit counter.
Figure 4. Expected Timings at TUPP Input Side
A1 A1 A1 A2 A2 A2 C1 C1 C1 J1 H1 H1 H1 H2 H2 H3 J1 H3 V1
ID[7..0]
ITMF
(ITMFH4=0)
IPL
IC1J1
SCLK
STS-1 #1 SPE J1 BYTE Negative stuff byte for STS-1 #2
SPE which happens to carry the
J1 byte
V1 byte for the first tributary in STS-1 #2
TUPP to LXT6251/6051 Adaptation in ADM Mode
Application Note 9
FPGA/EPLD1-B ad apt s TUPP timings into LXT6251 telecom bu s compatible timings. Note that
the input Telecom bus format to the LXT6251 should be set to DTBJ0J1EN single p uls e.
This operation in done in three separate steps:
•TUGEN generation: A separate TUGEN signal need to be generated for each of the 3 TUG-3
contained in the STM-1 stream. This is done by extracting the TUG-3 position from the C1J1
and payload timings from the TUPP.
•DTBH4EN generati on: A sep a r a te signal indicating the multiframe alignment should be
generated. This signal should be high during a whole f rame. It should go high after detection
of H4=00 and go down after detection of H4=01.
•Every signal coming out of the FPGA will be re-timed using the DTBYCK in order to make
sure that signal phase versus clock is compatible with the LXT6251 input b us.
Figure 5. Provided Timings from LXT6051
Figure 6. FPGA/EPLD1-B (FPGA/EPLD2-B)
J1
STM-1 Receive Telecom Bus Timing (Terminal, Add/Drop)
DTBTUGEN1
TUG3 #1 TUG3 #2TUG3 #3TUG3 #1 TUG3 #2
J0 Position NU1_8
Positon
A2
TUG3 #3TUG3 #2 Fixed
Stuff Fixed
Stuff
J1J0
Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01
Output
DTBCK
DTBJ0J1EN
DTBDATA
Output
DTBPAYEN
DTBH4
Output
Output
Output
Output
DTBTUGEN2
Output
DTBTUGEN3
Output
Every POH
byte
NU1_9
Position
LXT6251
ADM Mode
FPGA-A TUPP
19.44MHz
Ref clock
ID
SCLK
IC1J1
IPL
ITMF
OTMF
OC1J1
OPL
OTMFH4=1
ITMFH4=0
FPGA/EPLD
1-B
OTMF
OC1J1
OPL
OD DTBDATA
DTBYCK
DTBJ0J1EN
DTBPAYEN
DTBH4EN
DTBTUGEN
TUPP to LXT6251/6051 Adaptation in ADM Mode
10 Application Note
Figure 7. LXT6251 Rx Telecom Bus Timings
Figure 8. TUPP Output Timings
DTBYCK
Input
DTBJ0J1EN
DTBPAYEN
Input
DTBTUGEN
Input
J1J0
Input DTBTUGEN1 from OHT
Input
DTBDATA
J1
TU 1:1:1
J0 X XA2 V1
Fixed
Stuff Fixed
Stuff Fixed
Stuff TU 2:1:1
V1
TU 3:1:1
V1
Fixed
Stuff
TUG3 1VC-4VC-4 TUG 3:3
TU 2:7:3 TU 3:7:3 V1
TU 1:2:1
DTBH4en Goes High one clock cycle after H4=00, low one clock cycle after H4=01.
Input
A1 A1 A1 A2 A2 A2 C1 C1 C1 J1 H4 Vx H1 H1 H1 H2 H2 H3C2 H2 H4 H3 G1
OD[7..0]
SCLK
OC1J1
(OJ1EN=1)
OPL
OTMF
(OTMFh4=1)
STS-1 #1 SPE J1 byte
Last H4 byte in tributary multiframe
Negative stuff for STS-1 #2
SPE which happens to carry a
non-final H4 byte
TUPP to LXT6251/6051 Adaptation in ADM Mode
Application Note 11
3.0 Code Implementation
Both b locks F P GA/EP LD1-A and FP GA / EPLD 1-B s hou ld b e impl emen t ed i n t he sa me code to be
then implemented using a single FPGA or EPLD.
The code will be written in VHDL and will be designed so that the timings have sufficient margin
to cope with different technologies.
Final code design shows us that the FPGA/EPLD code will consist of 82 flip-flop plus
miscellaneous logic.
The VHDL code has been implemented u sing an hierarchical topolog y . There is one top level block
called TOP.vhd that is used to implement the interconnection between blocks from the sub-levels.
The following discussion will focus on the description of all the VHDL blocks:
3.1 TOP.vhd
This block is represented in the diagram below.
It consist of implementing the top level interconnection between its two sub-blocks: INTCLK.vhd
and RCORE.vhd. No logic is implemented in this block.
INTCLK.vhd
This block has two main functionalities:
•Inverting DTBCLK clock from the LXT6251 for timing adaptation.
•Passing through DTBCLK signal. This function is necessary in order to add a little bit of delay
on the clock which will feed the rest of the circuits on the board. This output clock , SCLK, is
Figure 9. VHDL Top Level Diagrams
rcore
dretfrmi
dtbdata_o
dtbh4en_o
dtbj0j1en_o
dtbpayen_o
dtbtugen1
dtbtugen2
dtbtugen3
ic1 j1
id
ipl
itm f
oc1j1
opl
otm f
dretclk
dtbck
dtbckn
dtbdata_i
dtbh4en_i
dtbj0j1en_i
dtbpayen_i
od
reset
d_co
intc lk
dtbckn
sclkdtbck d_ck
dretfrmi
dtbdata_o (7:0)
dtbh4en_o
dtbj0j1en_o
dtbpayen_o
dtbtugen1
dtbtugen2
dtbtugen3
ic1 j1
id (7 : 0 )
ipl
itm f
oc1j1
opl
otmf
dretclk
dtbdata_i (7:0)
dtbh4en_i
dtbj0j1en_i
dtbpayen_i
od (7:0)
reset
dtbck sclk
dtbckn
TUPP to LXT6251/6051 Adaptation in ADM Mode
12 Application Note
then used as a reference clock in the TUPP and the LXT6251 chips. Adding the delay, allows
correct timing relatio n between signals generated by the FPGA and SC LK (DTBCLK +
delay).
It is important to monitor the results of the VH DL compi lation and the FPGA/EPLD syn thes is to
insure that the clock has been inverted and is fed to the rest of the internal circuit and also that
DTBCLK is goi ng t hrough the devic e and i s output as SCLK.
3.2 RCORE.vhd
•This block is represented in the diagram below.
•RCORE is also a top level VHDL and contain su b-b lo cks as well.
•This block does not contain any logic and is used to interconnect the sub-level blocks:
INTNM.vhd, DRETTG.vhd and INTAZ.vhd.
3.3 INTNM.vhd
This block provides the adaptation between the LXT6051 and the TUPP telecom bus.
The two main features are:
•Decoding of the V1 position and the generation of ITMF and IC1J1 signals.
•This feature uses DTBCLKN (which is the output of INTCLK.vhd).
•Generation of the multi fram e clock (2 kHz) used by the LXT6051 for Rx ret imi ng purp os e.
This feature uses DRETCLK clock.
This block uses 38 Flip-flops.
Figure 10. VHDL Block Diagram
drettg
dtbpayen_o
dtbj0j1en_o
dtbh4en_o
dtbtugen1
dtbtugen2
dtbtugen3
opl
otm f
oc1j1
re se t
dtbck
dtbckn
d_tg
in ta z
dtbdata_o
re se t
od
dtbck
d_az
in tn m
ip l
ic1 j1
itm f
id
dtbckn
re se t
dtbpayen_i
dtbj0j1en_i
dtbh4en_i
dtbdata_i
dretclk dretfrm i
d_nm
re se t
od (7:0)
dtbdata_o (7:0)
id (7 : 0 )
itm f
ip l
ic 1 j1
dtbh4en_o
dtbj0j1en_o
dtbpayen_o
dtbtugen3
dtbtugen2
dtbtugen1
otm f
oc1j1
opl
dtbh4en_i
dtbj0j1en_i
dtbpayen_i
dtbdata_i (7:0)
dtbck
dretclk dretfrm i
dtbckn
TUPP to LXT6251/6051 Adaptation in ADM Mode
Application Note 13
3.4 DRETTG.vhd
This block generates retiming timings reference to the TUPP and also generates all timings needed
by the LXT6251 mapper.
This is done using a timing generator which consist of a 2430 bit counter. Simple decoding is then
used to decode all timing signals (H4en, Tugen, Payen..).
These signals are then clock out using DTBCK clock.
This blo ck also decod es referen ce timings f or the TUPP by using the same 2430 bit coun ter . Simple
decoding is used to generate all three signals required by the TUPP chip (OC1J1, OTMF, OPL).
These signals are then clocked out using DTBCKN (internal inverted clock).
This block uses 36 Flip-flops.
3.5 INTAZ.vhd
This block consist of an array of flip-flo p s to re-sample the data out o f the TUPP (OD) before
sending them to the LXT6251 (DTBDATA).
This block uses 8 Flip-flops.
3.6 Output Timings
Figure 11. LXT6051 to TUPP adaptation
J1
TUG3 #1 TUG3 #2TUG3 #3TUG3 #1 TUG3 #2
J0 Position NU1_8
Positon
A2
TUG3 #3TUG3 #2 Fixed
Stuff Fixed
Stuff
J1J0
Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01
DTBCK
DTBJ0J1EN
DTBDATA
DTBPAYEN
DTBH4
Every POH
byte
NU1_9
Position
SCLK
J1
TUG3 #1 TUG3 #2TUG3 #3TUG3 #1 TUG3 #2
J0 Position NU1_8
Positon
A2
TUG3 #3TUG3 #2 Fixed
Stuff Fixed
Stuff
ID
NU1_9
Position
A2
IC1J1
ITMF
TUPP to LXT6251/6051 Adaptation in ADM Mode
14 Application Note
3.7 B oard Im pl ementation
The VHDL code has been designed so th at both adaptatio ns, LXT6051 to TUPP and TUPP to
LXT6251, should be implemented in the same FPGA/EPLD.
Figure 12. TUPP to LXT6251 adaptation showing V1 byte
Figure 13. TUPP to LXT6251 Adaptation Showing H4=00
DTBJ0J1
DTBPAYEN
DTBTUGEN1
J0
DTBDATA
SCLK
DTBDATA
J1
J0 X XA2 Fixed
Stuff Fixed
Stuff Fixed
Stuff
TUG3 1
VC-4VC-4
TU 2:7:3 TU 3:7:3 Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3
Fixed
Stuff
TUG3 1
Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3
V1
TU 1:1:1
V1
TU 1:1:1
OPL
OC1J1
OTMF
DTBTUGEN2
DTBTUGEN3
TU 1:7:3
J1
J0 X XA2 Fixed
Stuff Fixed
Stuff Fixed
Stuff
TUG3 1
VC-4VC-4
TU 2:7:3 TU 3:7:3 Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3
Fixed
Stuff
TUG3 1
Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3
V1
TU 1:1:1
V1
TU 1:1:1
TU 1:7:3
J1
J0 J1
DTBJ0J1
DTBPAYEN
DTBTUGEN1
J0
DTBDATA
SCLK
DTBDATA
H4=00
J0 X XA2 Fixed
Stuff Fixed
Stuff Fixed
Stuff
TUG3 1
VC-4VC-4
TU 2:2:3 TU 3:2:3 Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3
Fixed
Stuff
TUG3 1
Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3 TU 1:3:1 TU 1:2:1
OPL
OC1J1
OTMF
DTBTUGEN2
DTBTUGEN3
TU 1:2:3
H4
J0 X XA2 Fixed
Stuff Fixed
Stuff Fixed
Stuff
TUG3 1
VC-4VC-4
TU 2:2:3 TU 3:2:3 Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3
Fixed
Stuff
TUG3 1
Fixed
Stuff
TUG3 2
Fixed
Stuff
TUG3 3 TU 1:3:1 TU 1:3:1
TU 1:2:3
J0
DTBH4EN
LOW AFTER ONE FRAME
TUPP to LXT6251/6051 Adaptation in ADM Mode
Application Note 15
When implementing this solution on a board it is very important to make sure that the layout of the
signal SCLK is done as short as possible in order to avoid possible timing issues in the LXT6251.
Figure 14. Board Implementation
Rx
SXT6051
FPGA-A
DTBDATA
DTBCK
DTBJ0J1EN
DTBPAYEN
DTBH4EN
19.44MHz
Ref clock
DRETCLK
DRETFRMI
LXT6251
ADM Mode
FPGA-A TUPP
ID
SCLK
IC1J1
IPL
ITMF
OTMF
OC1J1
OPL
OTMFH4=1
ITMFH4=0
ITMFEN=1
OTMFEN=1
FPGA-B
OD DTBDATA
DTBPAYEN
DTBJ0J1EN
DTBH4EN
DTBTUGEN
DTBDATA
DTBCK
DTBJ0J1EN
DTBPAYEN
DTBH4EN
DRETFRMI
DRETCLK
RcvRetimDsbl=0
RcvTbJ0J1Cnfg=0
dtbdata_i
dtbck
dtbj0j1en-i
dtbpayen_i
dtbh4en_i
dretfrmi
dretclk
reset
id
sclk
ic1j1
ipl
itmf
otmf
oc1j1
opl
od dtbdata_o
dtbj0j1en_o
dtbpayen_o
dtbh4en_o
dtbtugen
DTBYCK
DTBDATA
DTBPAYEN
DTBJ0J1EN
DTBH4EN
DTBTUGEN
RESET E1’s
