TUPP to LXT6251/6051 Adaptation in ADM Mode Application Note January 2001 Order Number: 249310-001 As of January 15, 2001, this document replaces the Level One document known as AN9906. Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT6251/6051 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2000 *Third-party brands and names are the property of their respective owners. Application Note TUPP to LXT6251/6051 Adaptation in ADM Mode Contents 1.0 TUPP to lxt6251/6051 Adaptation in ADM Mode............................................ 5 2.0 Detailed Description.................................................................................................. 7 3.0 Code Implementation .............................................................................................11 3.1 3.2 3.3 3.4 3.5 3.6 3.7 TOP.vhd ..............................................................................................................11 RCORE.vhd.........................................................................................................12 INTNM.vhd ..........................................................................................................12 DRETTG.vhd.......................................................................................................13 INTAZ.vhd ...........................................................................................................13 Output Timings ....................................................................................................13 Board Implementation .........................................................................................14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Block Diagram Master Element............................................................................. 6 Block Diagram = Non-master ................................................................................ 6 FPGA/EPLD1-A (and FPGA/EPLD2-A) ................................................................ 7 Expected Timings at TUPP Input Side .................................................................. 8 Provided Timings from LXT6051........................................................................... 9 FPGA/EPLD1-B (FPGA/EPLD2-B) .......................................................................9 LXT6251 Rx Telecom Bus Timings.....................................................................10 TUPP Output Timings .........................................................................................10 VHDL Top Level Diagrams..................................................................................11 VHDL Block Diagram ..........................................................................................12 LXT6051 to TUPP adaptation .............................................................................13 TUPP to LXT6251 adaptation showing V1 byte ..................................................14 TUPP to LXT6251 Adaptation Showing H4=00 ..................................................14 Board Implementation .........................................................................................15 Figures Application Note 3 TUPP to LXT6251/6051 Adaptation in ADM Mode 1.0 TUPP to lxt6251/6051 Adaptation in ADM Mode The current SDH/SONET solution provided by Intel, the LXT6051 and LXT6251, requires external circuitry in order to implement a ring type network. Several options, such as FPGA or other circuits, are available for the implementation of this external circuit. This document will focus on only one of these solutions: using the TUPP chip from PMC-Sierra with an FPGA. This circuit will provide a complete system solution for customers using Intel SDH/ SONET chip-set in a ring architecture system. In a ring architecture each element of the ring are ADM (Add and Drop Multiplexer) elements. The characteristics of such elements are: * Tributary data can be extracted and inserted via mapper type of devices. * The entire traffic or the traffic that is not processed by a mapper for access purposes is supposed to pass through untouched in the element in order to maintain traffic continuity. A key factor here is that the traffic passes through the element keeping its timing characteristics, i.e. clock phase and pointer value. The head-end element, which provides the timings for the whole loop, needs to include a PMC Sierra chip called the TUPP. This chip provide timing reference for the multiframe alignment via the H4 byte and also provides pointer initialization for all the TU-12 in the payload envelope. Because timings are maintained in each of the ADM elementsin a ring architecture, one of the elements has to act as the master timing generator in order to initialize the ring with a correct mode of operation. Because of differences between PMC TUPP and Intel's LXT6051/LXT6251 Telecom Bus format, some adaptation is required for interconnectivity between the three chips. An FPGA (or EPLD) device is used to implement this adaptation as shown below: Application Note 5 TUPP to LXT6251/6051 Adaptation in ADM Mode Figure 1. Block Diagram Master Element E1 LXT6051 FPGA/EPLD 1-A STM-1 FPGA/EPLD 1-B TUPP Rx LXT6051 LXT6251 Tx 19.44MHz Ref clock LXT6251 Tx FPGA/EPLD 2-B TUPP STM-1 FPGAEPLD 2-A Rx E1 FPGA/EPLD 1 = FPGA/EPLD 1-A + FPGA/EPLD 1-B FPGA/EPLD 2 = FPGA/EPLD 2-A + FPGA/EPLD 2-B FPGA 1 = FPGA 2 None of the other ADM elements in the ring require any timing initialization, therefore the architecture of these nodes is a straight forward connection between the LXT6051 OHT chip and the LXT6251 Mapper chip as shown in Figure 2. Figure 2. Block Diagram = Non-master E1 LXT6051 LXT6051 LXT6251 STM-1 Rx Tx STM-1 LXT6251 Tx Rx E1 6 Application Note TUPP to LXT6251/6051 Adaptation in ADM Mode 2.0 Detailed Description The implementation of the timing adaptation as described in Figure 2 requires a two-step process: * Telecom bus adaptation between OHT bus and TUPP bus. * Telecom bus adaptation between TUPP and Mapper bus. * The same adaptation is needed for both directions of the bi-directional ring structure. Note that FPGA/EPLD1-A and FPGA/EPLD1-B codes will be implemented in the same physical chip, FPGA 1. Note also that the implementation of FPGA/EPLD2-A and FPGA/EPLD2-B code is identical as FPGA/EPLD1-A and FPGA/EPLD1-B and will be implemented in the same physical chip, FPGA 2. Figure 3. FPGA/EPLD1-A (and FPGA/EPLD2-A) DTBDATA DTBCK DTBJ0J1EN DTBPAYEN DTBH4EN DTBDATA DTBCK DTBJ0J1EN dtbdata_i dtbck id sclk dtbpayen_i DTBH4EN dtbh4en_i ic1j1 ipl DRETFRMI DRETFRMI RcvRetimDsbl=0 RcvTbJ0J1Cnfg=0 IC1J1 IPL FPGA-A FPGA-A itmf ITMF otmf OTMF oc1j1 OC1J1 TUPP dretfrmi dretclk DRETCLK SCLK dtbj0j1en-i DTBPAYEN Rx LXT6051 ID opl reset OPL OTMFH4=1 ITMFH4=0 ITMFEN=1 OTMFEN=1 DRETCLK RESET 19.44MHz Ref clock The LXT6051 is configured to implement Rx retiming function in order to synchronize all the timings to the local Rx reference clock. DRETCLK the 19.44 MHz clock and DRETFRMI 8KHz clock from the FPGA-A are provided to the OHT to perform the receive retiming. The telecom bus output format of the LXT6051 should be set for DTBJ0J1EN single pulse. The TUPP device has two software options (OTMFH4 & ITMFH4) for the expected multiframe indication signal format: * Multiframe indication is done by identifying the H4 byte (XTMFH4=1). * Multiframe indication is done by identifying the third byte after J1 (equivalent to V1 byte). All the following circuitry developed such that: -ITMFH4 = 0 -OTMFH4 = 1 Application Note 7 TUPP to LXT6251/6051 Adaptation in ADM Mode Two functions are implemented in this FPGA/EPLD: Timing adaptation The FPGA needs to provide the V1 location timing signal (ITMF) to the TUPP. This is done by extracting the V1 information from the telecom bus provided by the OHT. This circuit function consist of 3 DFF for signal detection as well as some glue logic. Before sending the data and timings out to the TUPP, it is necessary to re-synchronize all data and timing signals through a DFF in order to realign data VS timings. This function will require 11 DFF. Time base The FPGA needs to provide the new multiframe (OMF), J0J1 (OC1J1) and payload (OTPL) indication signals. This block will be implemented by using a 2430 bit counter associated with a 4 bit counter. Figure 4. Expected Timings at TUPP Input Side SCLK IC1J1 IPL ITMF (ITMFH4=0) ID[7..0] A1 A1 A1 A2 A2 A2 C1 STS-1 #1 SPE J1 BYTE C1 C1 J1 H1 H1 H1 H2 H2 H3 J1 H3 V1 Negative stuff byte for STS-1 #2 SPE which happens to carry the J1 byte V1 byte for the first tributary in STS-1 #2 8 Application Note TUPP to LXT6251/6051 Adaptation in ADM Mode Figure 5. Provided Timings from LXT6051 STM-1 Receive Telecom Bus Timing (Terminal, Add/Drop) DTBCK Output DTBJ0J1EN J0 J1 Output DTBPAYEN Every POH byte Output DTBTUGEN1 Output DTBTUGEN2 Output DTBTUGEN3 Output DTBDATA A2 Output DTBH4 J0 Position NU1_8 Positon NU1_9 Position TUG3 #2 TUG3 #3 J1 Fixed Stuff Fixed Stuff TUG3 #1 TUG3 #2 TUG3 #3 TUG3 #1 TUG3 #2 Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01 Output Figure 6. FPGA/EPLD1-B (FPGA/EPLD2-B) ID OD DTBDATA SCLK DTBYCK IC1J1 DTBJ0J1EN IPL FPGA-A ITMF TUPP FPGA/EPLD 1-B DTBPAYEN LXT6251 DTBH4EN OTMF DTBTUGEN OC1J1 OPL OTMFH4=1 ITMFH4=0 ADM Mode OTMF OC1J1 OPL 19.44MHz Ref clock FPGA/EPLD1-B adapts TUPP timings into LXT6251 telecom bus compatible timings. Note that the input Telecom bus format to the LXT6251 should be set to DTBJ0J1EN single pulse. This operation in done in three separate steps: * TUGEN generation: A separate TUGEN signal need to be generated for each of the 3 TUG-3 contained in the STM-1 stream. This is done by extracting the TUG-3 position from the C1J1 and payload timings from the TUPP. * DTBH4EN generation: A separate signal indicating the multiframe alignment should be generated. This signal should be high during a whole frame. It should go high after detection of H4=00 and go down after detection of H4=01. * Every signal coming out of the FPGA will be re-timed using the DTBYCK in order to make sure that signal phase versus clock is compatible with the LXT6251 input bus. Application Note 9 TUPP to LXT6251/6051 Adaptation in ADM Mode Figure 7. LXT6251 Rx Telecom Bus Timings DTBYCK Input DTBJ0J1EN J0 J1 Input DTBPAYEN Input DTBTUGEN Input DTBTUGEN1 from OHT DTBDATA A2 J0 X X TU 2:7:3 TU 3:7:3 J1 Input DTBH4en Fixed Stuff Fixed Stuff Fixed Stuff VC-4 VC-4 TUG3 1 Fixed Stuff V1 V1 V1 V1 TUG 3:3 TU 1:1:1 TU 2:1:1 TU 3:1:1 TU 1:2:1 Goes High one clock cycle after H4=00, low one clock cycle after H4=01. Input Figure 8. TUPP Output Timings OTMF (OTMFh4=1) OPL OC1J1 (OJ1EN=1) SCLK OD[7..0] A1 A1 A1 A2 A2 A2 C1 C1 C1 J1 STS-1 #1 SPE J1 byte C2 H4 Vx H1 H1 H1 H2 H2 H2 H3 H4 H3 G1 Negative stuff for STS-1 #2 SPE which happens to carry a non-final H4 byte Last H4 byte in tributary multiframe 10 Application Note TUPP to LXT6251/6051 Adaptation in ADM Mode 3.0 Code Implementation Both blocks FPGA/EPLD1-A and FPGA/EPLD1-B should be implemented in the same code to be then implemented using a single FPGA or EPLD. The code will be written in VHDL and will be designed so that the timings have sufficient margin to cope with different technologies. Final code design shows us that the FPGA/EPLD code will consist of 82 flip-flop plus miscellaneous logic. The VHDL code has been implemented using an hierarchical topology. There is one top level block called TOP.vhd that is used to implement the interconnection between blocks from the sub-levels. The following discussion will focus on the description of all the VHDL blocks: 3.1 TOP.vhd This block is represented in the diagram below. It consist of implementing the top level interconnection between its two sub-blocks: INTCLK.vhd and RCORE.vhd. No logic is implemented in this block. Figure 9. VHDL Top Level Diagrams d tb c k d _ ck d tb c k s c lk s c lk d tb c k n d tb c k n i n tc l k d _ co re se t d r e tc l k d tb d a t a _ i ( 7 : 0 ) d tb h 4 e n _ i d tb j 0 j1 e n _ i d tb p a y e n _ i d tb c k n re se t d r e tc l k d r e tf r m i d tb d a t a _ i d tb h 4 e n _ i d tb j 0 j1 e n _ i d tb p a y e n _ i id i tm f ic 1 j1 ip l o c 1 j1 d tb c k opl o tm f o d (7 : 0 ) od d tb d a t a _ o d tb h 4 e n _ o d tb j 0 j 1 e n _ o d tb p a y e n _ o d tb t u g e n 1 d tb t u g e n 2 d tb t u g e n 3 d r e tf r m i id ( 7 : 0 ) i tm f ic 1 j1 ip l o c 1 j1 opl o tm f d tb d a t a _ o ( 7 : 0 ) d tb h 4 e n _ o d tb j 0 j 1 e n _ o d tb p a y e n _ o d tb t u g e n 1 d tb t u g e n 2 d tb t u g e n 3 rco re INTCLK.vhd This block has two main functionalities: * Inverting DTBCLK clock from the LXT6251 for timing adaptation. * Passing through DTBCLK signal. This function is necessary in order to add a little bit of delay on the clock which will feed the rest of the circuits on the board. This output clock, SCLK, is Application Note 11 TUPP to LXT6251/6051 Adaptation in ADM Mode then used as a reference clock in the TUPP and the LXT6251 chips. Adding the delay, allows correct timing relation between signals generated by the FPGA and SCLK (DTBCLK + delay). It is important to monitor the results of the VHDL compilation and the FPGA/EPLD synthesis to insure that the clock has been inverted and is fed to the rest of the internal circuit and also that DTBCLK is going through the device and is output as SCLK. 3.2 RCORE.vhd * This block is represented in the diagram below. * RCORE is also a top level VHDL and contain sub-blocks as well. * This block does not contain any logic and is used to interconnect the sub-level blocks: INTNM.vhd, DRETTG.vhd and INTAZ.vhd. Figure 10. VHDL Block Diagram d _ n m d tb c k n d tb c k n d tb p a y e n _ i d tb j 0 j 1 e n _ i d tb h 4 e n _ i d tb d a t a _ i ( 7 : 0 ) d r e tc l k r e s e t d tb p a y e n _ i ip l ip l d tb j0 j1 e n _ i ic 1 j1 ic 1 j1 d tb h 4 e n _ i i tm d tb d a t a _ i itm f id id d r e tc lk f (7 : 0 ) d r e tf r m i d r e tf r m i in tn m d _ tg d r e tt g o p l o tm d tb c k re s e t re s e t d tb t u g e n 1 d tb t u g e n 2 d tb t u g e n 3 d tb p a y e n _ o d tb j0 j1 e n _ o d tb h 4 e n _ o o p l o c 1 j1 o c 1 j1 d tb c k n d tb c k f o tm f d tb t u g e n 1 d tb t u g e n 2 d tb t u g e n 3 d tb p a y e n _ o d tb j 0 j 1 e n _ o d tb h 4 e n _ o d tb d a t a _ o (7 : 0 ) d _ a z d tb c k r e s e t o d ( 7 : 0 ) o d d tb d a t a _ o i n ta z 3.3 INTNM.vhd This block provides the adaptation between the LXT6051 and the TUPP telecom bus. The two main features are: * Decoding of the V1 position and the generation of ITMF and IC1J1 signals. * This feature uses DTBCLKN (which is the output of INTCLK.vhd). * Generation of the multiframe clock (2 kHz) used by the LXT6051 for Rx retiming purpose. This feature uses DRETCLK clock. This block uses 38 Flip-flops. 12 Application Note TUPP to LXT6251/6051 Adaptation in ADM Mode 3.4 DRETTG.vhd This block generates retiming timings reference to the TUPP and also generates all timings needed by the LXT6251 mapper. This is done using a timing generator which consist of a 2430 bit counter. Simple decoding is then used to decode all timing signals (H4en, Tugen, Payen..). These signals are then clock out using DTBCK clock. This block also decodes reference timings for the TUPP by using the same 2430 bit counter. Simple decoding is used to generate all three signals required by the TUPP chip (OC1J1, OTMF, OPL). These signals are then clocked out using DTBCKN (internal inverted clock). This block uses 36 Flip-flops. 3.5 INTAZ.vhd This block consist of an array of flip-flops to re-sample the data out of the TUPP (OD) before sending them to the LXT6251 (DTBDATA). This block uses 8 Flip-flops. 3.6 Output Timings Figure 11. LXT6051 to TUPP adaptation DTBCK DTBJ0J1EN J0 J1 DTBPAYEN Every POH byte NU1_8 Positon NU1_9 Position J1 Fixed Stuff DTBDATA A2 DTBH4 Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01 J0 Position TUG3 #2 TUG3 #3 Fixed Stuff TUG3 #1 TUG3 #2 TUG3 #3 TUG3 #1 TUG3 #2 SCLK ID A2 A2 J0 Position NU1_8 Positon NU1_9 Position TUG3 #2 TUG3 #3 J1 Fixed Stuff Fixed Stuff TUG3 #1 TUG3 #2 TUG3 #3 TUG3 #1 TUG3 #2 IC1J1 ITMF Application Note 13 TUPP to LXT6251/6051 Adaptation in ADM Mode Figure 12. TUPP to LXT6251 adaptation showing V1 byte SCLK DTBDATA A2 J0 X X TU 1:7:3 TU 2:7:3 TU 3:7:3 J1 Fixed Stuff Fixed Stuff VC-4 VC-4 Fixed Fixed Fixed Fixed Fixed Fixed V1 V1 Stuff Stuff Stuff Stuff Stuff Stuff TUG3 1 TUG3 2 TUG3 3 TUG3 1 TUG3 2 TUG3 3 TU 1:1:1 TU 1:1:1 Fixed Stuff Fixed Stuff VC-4 VC-4 OPL OC1J1 J0 J1 OTMF DTBJ0J1 J0 J1 DTBPAYEN DTBTUGEN1 DTBTUGEN2 DTBTUGEN3 DTBDATA A2 J0 X X TU 1:7:3 TU 2:7:3 TU 3:7:3 J1 Fixed Fixed Fixed Fixed Fixed Fixed V1 V1 Stuff Stuff Stuff Stuff Stuff Stuff TUG3 1 TUG3 2 TUG3 3 TUG3 1 TUG3 2 TUG3 3 TU 1:1:1 TU 1:1:1 Figure 13. TUPP to LXT6251 Adaptation Showing H4=00 SCLK DTBDATA A2 J0 X X TU 1:2:3 TU 2:2:3 TU 3:2:3 H4=00 Fixed Stuff Fixed Stuff VC-4 VC-4 Fixed Stuff TUG3 1 Fixed Stuff TUG3 2 Fixed Stuff TUG3 3 Fixed Stuff TUG3 1 Fixed Stuff TUG3 2 Fixed Stuff TUG3 3 TU 1:3:1 TU 1:2:1 Fixed Stuff VC-4 Fixed Stuff VC-4 Fixed Stuff TUG3 1 Fixed Stuff TUG3 2 Fixed Stuff TUG3 3 Fixed Stuff TUG3 1 Fixed Stuff TUG3 2 OPL OC1J1 J0 OTMF DTBJ0J1 J0 DTBPAYEN DTBTUGEN1 DTBTUGEN2 DTBTUGEN3 DTBDATA A2 J0 X X TU 1:2:3 TU 2:2:3 TU 3:2:3 DTBH4EN 3.7 H4 Fixed Stuff TUG3 3 TU 1:3:1 TU 1:3:1 LOW AFTER ONE FRAME Board Implementation The VHDL code has been designed so that both adaptations, LXT6051 to TUPP and TUPP to LXT6251, should be implemented in the same FPGA/EPLD. 14 Application Note TUPP to LXT6251/6051 Adaptation in ADM Mode When implementing this solution on a board it is very important to make sure that the layout of the signal SCLK is done as short as possible in order to avoid possible timing issues in the LXT6251. Figure 14. Board Implementation DTBDATA DTBCK DTBJ0J1EN DTBPAYEN DTBH4EN DTBDATA DTBCK DTBJ0J1EN dtbdata_i dtbck id sclk dtbj0j1en-i DTBPAYEN dtbpayen_i DTBH4EN dtbh4en_i ic1j1 ipl Rx SXT6051 FPGA-A FPGA-A itmf DTBYCK ID OD od dtbdata_o DRETFRMI DTBPAYEN DTBPAYEN dtbj0j1en_o DTBJ0J1EN DTBJ0J1EN IC1J1 IPL ITMF TUPP FPGA-B RcvRetimDsbl=0 RcvTbJ0J1Cnfg=0 dtbtugen oc1j1 opl reset LXT6251 DTBH4EN DTBH4EN OTMF dretfrmi dretclk DRETCLK DTBDATA dtbpayen_o dtbh4en_o otmf DRETFRMI DTBDATA SCLK OC1J1 OPL OTMFH4=1 ITMFH4=0 ITMFEN=1 OTMFEN=1 DTBTUGEN DTBTUGEN ADM Mode DRETCLK E1's RESET 19.44MHz Ref clock Application Note 15