This is information on a product in full production.
June 2012 Doc ID 15453 Rev 11 1/52
1
STM6600, STM6601
Smart push-button on/off controller with Smart Reset™ and
power-on lockout
Datasheet − production data
Features
■Operating voltage 1.6 V to 5.5 V
■Low standby current of 0.6 µA
■Adjustable Smart Reset™ assertion delay time
driven by external CSRD
■Power-up duration determined primarily by
push-button press (STM6600) or by fixed time
period, tON_BLANK (STM6601)
■Debounced PB and SR inputs
■PB and SR ESD inputs withstand voltage up to
±15 kV (air discharge) ±8 kV (contact
discharge)
■Active high or active low enable output option
(EN or EN) provides control of MOSFET,
DC-DC converter, regulator, etc.
■Secure startup, interrupt, Smart Reset™ or
power-down driven by push-button
■Precise 1.5 V voltage reference with 1%
accuracy
■Industrial operating temperature –40 to +85 °C
■Available in TDFN12 2 x 3 mm package
Applications
■Portable devices
■Termin
als
■
A
udio and video players
■Cell phones and smart phones
■PDAs, palmtops, organizers
TDFN12
Table 1. Device summary
Device RST CSRD PB / SR EN or EN INT Startup process
STM6600 open drain(1) ✓✓push-pull open drain(1) PB must be held low until the
PSHOLD(2) confirmation
STM6601 open drain(1) ✓✓push-pull open drain(1) PB can be released before the
PSHOLD(2) confirmation
1. External pull-up resistor needs to be connected to open drain outputs.
2. For a successful startup, the PSHOLD (Power Supply Hold) needs to be pulled high within specific time, tON_BLANK.
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Contents STM6600, STM6601
2/52 Doc ID 15453 Rev 11
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 Product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM6600, STM6601 List of tables
Doc ID 15453 Rev 11 3/52
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6. TDFN12 (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7. Carrier tape dimensions for TDFN12 (2 x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 8. STM6600 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 9. STM6601 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10. STM6600 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. STM6601 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
List of figures STM6600, STM6601
4/52 Doc ID 15453 Rev 11
List of figures
Figure 1. Application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Basic functionality (option with enable deassertion after long push) . . . . . . . . . . . . . . . . . . 6
Figure 3. Basic functionality (option with RST assertion after long push) . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. TDFN12 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Successful power-up on STM6600 (PB released prior to tON_BLANK expiration) . . . . . . . . 14
Figure 8. Successful power-up on STM6600 (tON_BLANK expires prior to PB release) . . . . . . . . . . . 15
Figure 9. Unsuccessful power-up on STM6600 (PB released prior to tON_BLANK) . . . . . . . . . . . . . . 16
Figure 10. Unsuccessful power-up on STM6600 (tON_BLANK expires prior to PB release) . . . . . . . . . 17
Figure 11. Successful power-up on STM6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Unsuccessful power-up on STM6601. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Power-up on STM660x with voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. PB interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Long push, PB pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Long push, SR pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Invalid long push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Long push (option with RST assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Long push (option with enable deassertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Undervoltage detected for <tSRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21. Undervoltage detected for >tSRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. PBOUT output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 23. Supply current vs. temperature, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Supply current vs. temperature, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Supply current vs. supply voltage, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 26. Supply current vs. supply voltage, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 27. Threshold vs. temperature, VTH+ = 3.4 V (typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28. Threshold hysteresis vs. temperature, VHYST = 200 mV (typ.) . . . . . . . . . . . . . . . . . . . . . . 30
Figure 29. Debounce period vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 30. CSRD charging current vs. temperature, VCC = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 31. Output low voltage vs. output low current, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 32. Output high voltage vs. output high current, TA = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 33. Output voltage vs. supply voltage, IOUT = 1 mA, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 34. Input voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 35. Reference output voltage vs. temperature, VCC = 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 36. Reference output voltage vs. load current, VCC = 2.0 V, TA = 25 °C . . . . . . . . . . . . . . . . . 34
Figure 37. Reference output voltage vs. supply voltage, TA = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 38. Reference startup, IREF = 15 µF, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 39. Reference response to steps on supply voltage, IREF = 15 µA, TA = 25 °C . . . . . . . . . . . . 36
Figure 40. Reference response to steps in load current, VCC = 3.6 V, TA = 25 °C . . . . . . . . . . . . . . . 37
Figure 41. TDFN12 (2 x 3 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 42. TDFN12 (2 x 3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 43. Carrier tape for TDFN12 (2 x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM6600, STM6601 Description
Doc ID 15453 Rev 11 5/52
1 Description
The STM6600-01 devices monitor the state of connected push-button(s) as well as sufficient
supply voltage. An enable output controls power for the application through the MOSFET
transistor, DC-DC converter, regulator, etc. If the supply voltage is above a precise voltage
threshold, the enable output can be asserted by a simple press of the button. Factory-
selectable supply voltage thresholds are determined by highly accurate and temperature-
compensated references. An interrupt is asserted by pressing the push-button during
normal operation and can be used to request a system power-down. The interrupt is also
asserted if undervoltage is detected. By a long push of one button (PB) or two buttons (PB
and SR) either a reset is asserted or power for the application is disabled depending on the
option used.
The device also offers additional features such as precise 1.5 V voltage reference with very
tight accuracy of 1%, separate output indicating undervoltage detection and separate output
for distinguishing between interrupt by push-button or undervoltage.
The device consumes very low current of 6 µA during normal operation and only 0.6 µA
current during standby.
The STM6600-01 is available in the TDFN12 package and is offered in several options
among features such as selectable threshold, hysteresis, timeouts, output types, etc.
Figure 1. Application hookup
1. A resistor is required for open drain output type only. A 10 kΩ pull-up is sufficient in most applications.
2. Capacitor CREF is mandatory on VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended.
3. For the STM6601 the processor has to confirm the proper power-on during the fixed time period, tON_BLANK. This failsafe
feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive
microprocessor.
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Description STM6600, STM6601
6/52 Doc ID 15453 Rev 11
Figure 2. Basic functionality (option with enable deassertion after long push)
1. For power-up the battery voltage has to be above VTH+ threshold.
Figure 3. Basic functionality (option with RST assertion after long push)
1. For power-up the battery voltage has to be above VTH+ threshold.
Figure 4. Logic diagram
PB
SR
POWER-UP(1) INTERRUPT
(short push)
POWER-DOWN
(long push)
EN
INT interrupt interrupt
AM00243v1
PB
POWER-UP(1) INTERRUPT
(short push)
POWER-DOWN
(long push)
SR
INT interrupt interrupt
RST
AM00243bv1
AM00236v1
STM6600
STM6601
RST
GND
CSRD
INT
PSHOLD
VCC
PBOUT
VCCLO
VREF
EN (EN)
SR
PB
STM6600, STM6601 Description
Doc ID 15453 Rev 11 7/52
Figure 5. TDFN12 pin connections
Table 2. Pin descriptions
Pin number Symbol Function
1V
CC Power supply input
2SR
Smart Reset™ button input
3V
REF Precise 1.5 V voltage reference
4PS
HOLD PSHOLD input
5C
SRD Adjustable Smart Reset™ delay time input
6PB
Push-button input
7VCC
LO Output for high threshold comparator output (VTH+)
8PB
OUT Status of PB push-button input
9EN or EN
Enable output
10 RST Reset output
11 INT Interrupt output
12 GND Ground
AM00245v1
GND
CSRD
PSHOLD
VCC
EN (EN)
RST
INT
5
1
4
8
67
9
10
11
12
3
2
PBOUT
SR
VREF
PB
VCCLO
Description STM6600, STM6601
8/52 Doc ID 15453 Rev 11
Figure 6. Block diagram
1. Internal pull-up resistor connected to PB input (see Table 5 for precise specifications).
2. Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications and Table 10 for detailed
device options).
3. Internal pull-down resistor is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18).
VTH+
PB
EN (EN)
Smart
logic
Edge detector debounce
SRD logic
GND
CSRD
tREC
generator
INT
RST
PS
HOLD
VCC
VCCLO
VREF
Glitch immunity
PBOUT
AM00237v3
1.5 V
Edge detector debounce
Glitch immunity
+
–
VTH–
+
–
SR
R
PSHOLD
(3)
V
CC
V
CC
R
PB
R
SR
(1) (2)
STM6600, STM6601 Pin descriptions
Doc ID 15453 Rev 11 9/52
2 Pin descriptions
VCC - power supply input
VCC is monitored during startup and normal operation for sufficient voltage level. Decouple
the VCC pin from ground by placing a 0.1 µF capacitor as close to the device as possible.
SR - Smart Reset™ button input
This input is equipped with voltage detector with a factory-trimmed threshold and has ±8 kV
HBM ESD protection.
Both PB and SR buttons have to be pressed and held for tSRD period so the long push is
recognized and the reset is asserted (or the enable output is deasserted depending on the
option) - see Figure 15, 16, and 17.
Active low SR input is usually connected to GND through the momentary push-button (see
Figure 1) and it has an optional 100 kΩ pull-up resistor. It is also possible to drive this input
using an external device with either open drain (recommended) or push-pull output. Open
drain output can be connected in parallel with push-button or other open drain outputs,
which is not possible with push-pull output. SR input is monitored for falling edge after
power-up and must not be grounded permanently.
VREF - external precise 1.5 V voltage reference
This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has
proper output voltage as soon as the reset output is deasserted (i.e. after tREC expires) and
it is disabled when the device enters standby mode. A mandatory capacitor needs to be
connected to VREF output (even if VREF is not used). Capacitor value of 1 µF is
recommended.
PSHOLD input
This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to
confirm correct power-up of the device (if EN or EN is not asserted) or to initiate a shutdown
(if EN or EN is asserted).
Forcing PSHOLD high during power-up confirms the proper start of the application and keeps
enable output asserted. Because most processors have outputs in high-Z state before
initialization, an internal pull-down resistor is connected to PSHOLD input during startup (see
Figure 7, 8, 9, 10, 11, 12, 13, and 18).
Forcing the PSHOLD signal low during normal operation deasserts the enable output (see
Figure 14). Input voltage on this pin is compared to an accurate voltage reference.
CSRD - Smart Reset™ delay time input
A capacitor to ground determines the additional time (tSRD) that PB with SR must be
pressed and held before a long push is recognized. The connected CSRD capacitor is
charged with ISRD current. Additional Smart Reset™ delay time tSRD ends when voltage on
the CSRD capacitor reaches the VSRD voltage threshold. It is recommended to use a low
ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the CSRD pin open. If no
capacitor is connected, there is no tSRD and a long push is recognized right after tINT_Min
expires (see Figure 18 and 19).
Pin descriptions STM6600, STM6601
10/52 Doc ID 15453 Rev 11
PB - power ON switch
This input is equipped with a voltage detector with a factory-trimmed threshold and has
± 8 kV HBM ESD protection.
When the PB button is pressed and held, the battery voltage is detected and EN (or EN) is
asserted if the battery voltage is above the threshold VTH+ during the whole tDEBOUNCE
period (see Figure 13).
A short push of the push-button during normal operation can initiate an interrupt through
debounced INT output (see Figure 14) and a long push of PB and SR simultaneously can
either assert reset output RST (see Figure 18) or deassert the EN or EN output (see
Figure 19) based on the option used.
Note: A switch to GND must be connected to this input (e.g. mechanical push-button, open drain
output of external circuitry, etc.), see Figure 1. This ensures a proper startup signal on PB
(i.e. a transition from full VCC below specified VIL). PB input has an internal 100 kΩ pull-up
resistor connected.
VCCLO - high threshold detection output
During power-up, VCCLO is low when VCC supply voltage is below the VTH+ threshold. After
successful power-up (i.e. during normal operation) VCCLO is low anytime undervoltage is
detected (see Figure 13).
Output type is active low and open drain by default. Open drain output type requires a pull-
up resistor. A 10 kΩ is sufficient in most applications.
VCCLO is floating when STM660x is in standby mode.
PBOUT - PB input state
If the push-button PB is pressed, the pin stays low during the tDEBOUNCE time period.
If PB is asserted for the entire tDEBOUNCE period, PBOUT will then stay low for at least
tINT_Min. If PB is asserted after tINT_Min expires, PBOUT will return high as soon as PB is
deasserted (see Figure 22). PBOUT ignores PB assertion during an undervoltage condition.
At startup on the STM6601 PBOUT will respond only to the first PB assertion and any other
assertion will be ignored until tON_BLANK expires. This output is active low and open drain by
default. Open drain output type requires a pull-up resistor. A 10 kΩ is sufficient in most
applications.
STM6600, STM6601 Pin descriptions
Doc ID 15453 Rev 11 11/52
EN or EN - enable output
This output is intended to enable system power (see Figure 1). EN is asserted high after
a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed
and held for tDEBOUNCE or more and VCC > VTH+ voltage level has been detected - see
Figure 13). EN is released low if any of the conditions below occur:
a) the push-button is released before PSHOLD is driven high (valid for STM6600, see
Figure 9) or tON_BLANK expires before PSHOLD is driven high during startup (valid
for both STM6600 and STM6601, see Figure 10 and 12).
b) PSHOLD is driven low during normal operation (see Figure 14).
c) an undervoltage condition is detected for more than tSRD + tINT_Min + tDEBOUNCE
(see Figure 21).
d) a long push of the buttons is detected (only for the device with option “EN
deasserted by long push” - see Figure 19) or PSHOLD is not driven high during
tON_BLANK after a long push of the buttons (only for the device with option “RST
asserted by long push” - see Figure 18).
Described logic levels are inverted in case of EN output. Output type is push-pull by default.
RST - reset output
This output pulls low for tREC:
a) during startup. PB has been pressed (falling edge on the PB detected) and held
for at least tDEBOUNCE and VCC > VTH+ (see Figure 7, 8, 9, 10, 11, 12 and 13 for
more details).
b) after long push detection (valid only for the device with option “RST asserted by
long push”). PB has been pressed (falling edge on the PB detected) and held for
more than tDEBOUNCE + tSRD (additional Smart Reset™ delay time can be adjusted
by the external capacitor CSRD) - see Figure 18.
Output type is active low and open drain by default. Open drain output type requires a pull-
up resistor. A 10 kΩ is sufficient in most applications.
INT - interrupt output
While the system is under normal operation (PSHOLD is driven high, power for application is
asserted), the INT is driven low if:
a) VCC falls below VTH- threshold (i.e. undervoltage is detected - see Figure 20 and
21).
b) the falling edge on the PB is detected and the push-button is held for tDEBOUNCE or
more. INT is driven low after tDEBOUNCE and stays low as long as PB is held. The
INT signal is held high during power-up.
The state of the PBOUT output can be used to determine if the interrupt was caused by
either the assertion of the PB input, or was due to the detection of an undervoltage condition
on VCC.
INT output is asserted low for at least tINT_Min.
Output type is active low and open drain by default. Open drain output type requires a pull-
up resistor. A 10 kΩ is sufficient in most applications.
GND - ground
Operation STM6600, STM6601
12/52 Doc ID 15453 Rev 11
3 Operation
The STM6600-STM6601 simplified smart push-button on/off controller with Smart Reset™
and power-on lockout enables and disables power for the application depending on push-
button states, signals from the processor, and battery voltage.
Power-on
Because most of the processors have outputs in high-Z state before initialization, an internal
pull-down resistor is connected to PSHOLD input during startup (see Figure 7, 8, 9, 10, 11,
12, 13, and 18).
To power up the device the push-button PB has to be pressed for at least tDEBOUNCE and
VCC has to be above VTH+ for the whole tDEBOUNCE period. If the battery voltage drops
below VTH+ during the tDEBOUNCE, the counter is reset and starts to count again when VCC >
VTH+ (see Figure 13). After tDEBOUNCE the enable signal is asserted (EN goes high, EN
goes low), reset output RST is asserted for tREC and then the startup routine is performed
by the processor. During initialization, the processor sets the PSHOLD signal high.
On the STM6600 the PSHOLD signal has to be set high prior to push-button release and
tON_BLANK expiration, otherwise the enable signal is deasserted (EN goes low, EN goes
high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the
maximum time allowed for the system to power up and initialize the circuits driving the
PSHOLD input. If the PSHOLD signal is low at push-button release, the enable output is
deasserted immediately, thus turning off the system power. If tON_BLANK expires prior to
push-button release, the PSHOLD state is checked at its expiration. This safety feature
disables the power and prevents discharging the battery if the push-button is stuck or it is
held for an unreasonable period of time and the application is not responding (see Figure 8
and 10). PB status, INT status and VCC undervoltage detection are not monitored until
power-up is completed.
On the STM6601 the PSHOLD signal has to be set high before tON_BLANK expires, otherwise
the enable signal is deasserted - see Figure 11 and 12. In this case the tON_BLANK period is
the maximum time allowed for the power switch and processor to perform the proper power-
on. If the PSHOLD signal is low at the end of the blanking period, the enable output is
released immediately, thus turning off the system power. PB status, INT status and VCC
undervoltage detection are not monitored during the entire tON_BLANK period. This failsafe
feature prevents the user from turning on the system when there is a faulty power switch or
an unresponsive microprocessor.
Push-button interrupt
If the device works under normal operation (i.e. PSHOLD is high) and the push-button PB is
pressed for more than tDEBOUNCE, a negative pulse with minimum tINT_Min width is
generated on the INT output. By connecting INT to the processor interrupt input (INT or
NMI) a safeguard routine can be performed and the power can be shut down by setting
PSHOLD low - see Figure 14.
Forced power-down mode
The PSHOLD output can be forced low anytime during normal operation by the processor
and can deassert the enable signal - see Figure 14.
Undervoltage detection
If VCC voltage drops below VTH- voltage threshold during normal operation, the INT output is
driven low (see Figure 20 and Figure 21).
STM6600, STM6601 Operation
Doc ID 15453 Rev 11 13/52
If an undervoltage condition is detected for tDEBOUNCE + tINT_Min + tSRD, the enable output is
deasserted (see Figure 21).
Hardware reset or power-down while system not responding
If the system is not responding and the system hangs, the PB and SR push-buttons can be
pressed simultaneously longer than tDEBOUNCE + tINT_Min + tSRD, and then
a) either the reset output RST is asserted for tREC and the processor is reset (valid
only for the device with option “RST asserted by long push”) – see Figure 18
b) or the power is disabled by EN or EN signal (valid only for the device with option
“EN deasserted by long push”) – see Figure 19
The tSRD is set by the external capacitor connected to the CSRD pin. SR input is monitored
for falling edge after power-up and must not be grounded permanently.
Standby
If the enable output is deasserted (i.e. EN is low or EN is high), the STM660x device enters
standby mode with low current consumption (see Tab l e 5 ). In standby mode PB input is only
monitored for the falling edge. The external 1.5 V voltage reference is also disabled in
standby mode.
Waveforms STM6600, STM6601
14/52 Doc ID 15453 Rev 11
4 Waveforms
Figure 7. Successful power-up on STM6600 (PB released prior to tON_BLANK expiration)
1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. EN signal is high even after PB release, because processor sets PSHOLD signal high before PB is released.
PSHOLD
ignored
internal pull-down resistor
connected to PSHOLD input
VCC undervoltage detection
ignored
PB(1)
PSHOLD
(2)
EN(3)
RST
Push-button pressed and
PB connected to GND
tDEBOUNCE tREC
processor
sets PSHOLD
PB released prior to t ON_BLANK
expiration
PSHOLD state detected as high
EN remains asserted
tON_BLANK
AM00247v3
INT signal is held high during power-up (i.e. until PB release in this case).
VCC is considered VCC > VTH+.
Note:
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 15/52
Figure 8. Successful power-up on STM6600 (tON_BLANK expires prior to PB release)
1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.
PSHOLD
ignored
internal pull-down resistor
connected to PSHOLD input
VCC undervoltage detection
ignored
PB(1)
PSHOLD
(2)
EN(3)
RST
Push-button pressed and
PB connected to GND
tDEBOUNCE tREC
processor
sets PSHOLD
PB released
tON_BLANK
tON_BLANK expired prior to PB
release
PSHOLD state detected as high
EN remains asserted
AM00247bv2
INT signal is held high during power-up (i.e. until t
ON_BLANK
expires in this case).
V
CC
is considered V
CC
> V
TH+.
Note:
Waveforms STM6600, STM6601
16/52 Doc ID 15453 Rev 11
Figure 9. Unsuccessful power-up on STM6600 (PB released prior to tON_BLANK)
1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. EN signal goes low with PB release, because processor did not force PSHOLD signal high.
internal pull-down resistor
connected to PSHOLD input
PSHOLD
ignored
PB status
ignored
VCC undervoltage detection
ignored
PB(1)
PSHOLD
(2)
EN(3)
RST
Push-button pressed and
PB connected to GND
tDEBOUNCE
PB released
PSHOLD state detected as low
EN deasserted
tREC tEN_OFF
tON_BLANK
AM00248v3
INT signal is held high during power-up (i.e. until PB release in this case).
V
CC
is considered V
CC
> V
TH+.
Note:
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 17/52
Figure 10. Unsuccessful power-up on STM6600 (tON_BLANK expires prior to PB release)
1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.
internal pull-down resistor connected to
PSHOLD input
PSHOLD
ignored
PB status
ignored
VCC undervoltage detection ignored
PB(1)
PSHOLD
(2)
EN(3)
RST
Push-button pressed and
PB connected to GND
tDEBOUNCE
PB released
tREC tEN_OFF
tON_BLANK
tON_BLANK expired prior to PB release
PSHOLD state detected as low
EN is deasserted
AM00248bv2
INT signal is held high during power-up (i.e. until t
ON_BLANK
expires in this case).
V
CC
is considered V
CC
> V
TH+.
Note:
Waveforms STM6600, STM6601
18/52 Doc ID 15453 Rev 11
Figure 11. Successful power-up on STM6601
1. PB detection on falling edge.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. PSHOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is high therefore the
EN signal remains asserted.
PB status and
VCC
undervoltage
ignored
PB (1)
EN(3)
RST
Push-button pressed and
PB connected to GND
t
DEBOUNCE
t
REC
processor
sets PSHOLD
detection
tON_BLANK
PS
HOLD
ignored
tON_BLANK expires
PS
HOLD
state detected as high
EN remains asserted
(2)
internal pull-down resistor
connected to PS
HOLD
input
PSHOLD
AM00250v2
INT signal is held high during power-up (i.e. until t
ON_BLANK
expires in the case of the STM6601).
VCC is considered VCC > VTH+.
Note:
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 19/52
Figure 12. Unsuccessful power-up on STM6601
1. PB detection on falling edge.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. PSHOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is not high therefore
the EN signal goes low. Even releasing the PB button after the tON_BLANK will not prevent this.
EN(3)
(2)
t
ON_BLANK
expires
PS
HOLD
state detected as low
EN deasserted
intenal pull-down resistor
connected to PSHOLD input
tDEBOUNCE
Push-button pressed and
PB connected to GND
Push-button pressed and
PB connected to GND
tREC
PB(1)
RST
PS
HOLD
ignored
PS
HOLD
AM00238v2
INT signal is held high during power-up (i.e. until t
ON_BLANK
expires in the case of the STM6601).
VCC is considered VCC > VTH+.
Note:
Waveforms STM6600, STM6601
20/52 Doc ID 15453 Rev 11
Figure 13. Power-up on STM660x with voltage dropout
1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.
3. INT signal is held high during power-up.
VCC goes above VTH+ and
tDEBOUNCE is counted again
V
TH–
VCC
under-
voltage
detected
VCC
drop
V
TH+
VCC
VCC
LO
PB
(1)
EN
tDEBOUNCE tREC
< t ON_BLANK
INT signal is held high during power-up
PS
HOLD
(2)
RST
Push-button pressed and
PB connected to GND
< t DEBOUNCE
INT (3)
internal pull-down resistor
connected to PS
HOLD
input
V
CC–Min
AM00249v2
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 21/52
Figure 14. PB interrupt
1. PB detection on falling edge.
PB(1)
tDEBOUNCE tINT_Min tEN_OFF
Push-button pressed and
PB connected to GND and EN is deasserted
accordingly
PB status
ignored
VCC undervoltage
detection ignored
PB status
ignored
processor sets PS
HOLD
low
PSHOLD
AM00251v2
processor interrupt starts power-down sequence
Note: V
CC
is considered V
CC
> V
TH+
.
Waveforms STM6600, STM6601
22/52 Doc ID 15453 Rev 11
Figure 15. Long push, PB pressed first
Figure 16. Long push, SR pressed first
PB status
ignored
PB
INT
Push-button
PB is pressed
tDEBOUNCE
tINT_Min
SR
tDEBOUNCE
Push-button
SR is pressed
tSRD starts to
be counted
AM00257v1
tSRD
set by CSRD
PB status
ignored
PB
INT
Push-button
PB is pressed
tDEBOUNCE
tINT_Min
SR
Push-button
SR is pressed
tSRD starts to
be counted
tSRD
set by CSRD
AM00258v1
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 23/52
Figure 17. Invalid long push
PB status
ignored
Any rising edge will stop
tSRD
to count regardless
of glitch immunity
AM00259v1
PB
INT
Push-button
PB is pressed
tDEBOUNCE
tINT_Min
SR
Push-button
SR is pressed
tSRD starts to
be counted
set by CSRD
< tSRD
Waveforms STM6600, STM6601
24/52 Doc ID 15453 Rev 11
Figure 18. Long push (option with RST assertion)
1. tSRD period is set by external capacitor CSRD.
2. PB ignored during tINT_Min.
3. PSHOLD signal is ignored during tON_BLANK. Its level is checked after tON_BLANK expires and if it is high the EN signal
remains asserted, otherwise EN goes low.
4. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during startup when device is reset.
internal pull-down resistor
connected to PSHOLD input
PSHOLD ignored
PB status
ignored
tON_BLANK
tSRD(1)
set by CSRD
VCC undervoltage detection status ignored
PB
PSHOLD
(3, 4)
INT(2)
RST
Push-button pressed
and PB connected to
GND
tDEBOUNCE tREC
Push-button held even
after tSRD expires
therefore RST is asserted
INT can go high, if PB goes high,
but system freezes and processor
won’t respond
if system freezes, processor won’t
respond to any INT status change
tINT_Min tDEBOUNCE
After tON_BLANK
PB is monitored
for falling edge
tON_BLANK expires
PSHOLD state detected as high
therefore EN remains high
(valid for STM6600 and STM6601)
SR
AM00252v2
Note: EN is high.
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 25/52
Figure 19. Long push (option with enable deassertion)
1. tSRD period is set by external capacitor CSRD.
2. PB ignored during tINT_Min.
3. After tSRD expires EN is forced low.
PB status
ignored
PB status
ignored
VCC undervoltage detection status ignored
PB
PSHOLD
INT(2)
EN(3)
Push-button
pressed and PB
connected to GND
tDEBOUNCE
Push-button held even
after tSRD expires and
EN is deasserted
tINT_Min tDEBOUNCE
After tEN_OFF expires
PB is monitored for
falling edge
tEN_OFF
INT can go high, if PB goes high,
but system freezes and processor
won’t respond
if system freezes, processor won’t
respond to any INT status change
tSRD(1)
set by CSRD
SR
AM00253v2
Waveforms STM6600, STM6601
26/52 Doc ID 15453 Rev 11
Figure 20. Undervoltage detected for <tSRD
1. VCC goes above VTH+ within tSRD thus power is not disabled after tSRD expires.
2. tSRD period is set by external capacitor CSRD.
Figure 21. Undervoltage detected for >tSRD
1. After tSRD expires VCC is still insufficient (below VTH+) thus power is disabled (EN goes low or EN goes high).
2. tSRD period is set by external capacitor CSRD.
PB status ignored
VCC
under-
voltage
detection
ignored
VCC-Min
VCCLO
VCC(1)
EN
and EN is deasserted
accordingly
PB status
ignored
processor interrupt starts power-down sequence
processor sets PSHOLD low
t
SRD(2)
set by C
SRD
tDEBOUNCE tINT_Min tEN_OFF
INT
VCC undervoltage
detected
VTH+
VTH–
PSHOLD
AM00254v1
EN
VCC
LO
VCC-Min
PB status
ignored
V
CC
is below V
TH+
even after t
SRD
expires
thus power is disabled (EN goes low) and
PB is monitored for regular startup
V
CC
under-
voltage
detection
ignored
INT
PS
HOLD
V
CC
undervoltage
detected
VTH+
VTH–
VCC(1)
PB status ignored
t
DEBOUNCE
t
INT_Min
t
EN_OFF
t
SRD(2)
set by C
SRD
AM00255v1
STM6600, STM6601 Waveforms
Doc ID 15453 Rev 11 27/52
Figure 22. PBOUT output waveform
1. Pulses on PB shorter than glitch immunity are ignored.
2. Pulses on PB shorter than tDEBOUNCE are not recognized by PBOUT.
3. Minimum pulse width on PBOUT is tINT_Min.
4. If push-button is held longer than tDEBOUNCE + tINT_Min, PBOUT goes high when the push-button is released.
PB(1,2,3,4)
<glitch immunity
AM00256v1
t
INT_min
t
DEBOUNCE
PB
OUT
Typical operating characteristics STM6600, STM6601
28/52 Doc ID 15453 Rev 11
5 Typical operating characteristics
Figure 23. Supply current vs. temperature, normal state
Figure 24. Supply current vs. temperature, standby state
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-40 -20 0 20 40 60 80
Temperature, T
A (°C)
Supply current, I
CC
(µA)
VCC = 5.5 V
VCC = 3.6 V
VCC = 2.0 V
AM04701v1
0.0
0.5
1.0
1.5
2.0
-40 -20 0 20 40 60 80
Temperature, T
A (°C)
Supply current, I
CC
(µA)
VCC = 5.5 V
VCC = 3.6 V
VCC = 2.0 V
AM04702v1
STM6600, STM6601 Typical operating characteristics
Doc ID 15453 Rev 11 29/52
Figure 25. Supply current vs. supply voltage, normal state
Figure 26. Supply current vs. supply voltage, standby state
0
1
2
3
4
5
6
7
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply voltage, VCC (V)
Supply current, ICC (µA)
TA = 85 °C
TA = 25 °C
TA = 0 °C
TA = –40 °C
AM04703v1
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.54.04.55.05.5
Supply voltage, VCC (V)
Supply current, ICC (µA)
TA = 85 °C
TA = 25 °C
TA = 0 °C
TA = –40 °C
AM04704v1
Typical operating characteristics STM6600, STM6601
30/52 Doc ID 15453 Rev 11
Figure 27. Threshold vs. temperature, VTH+ = 3.4 V (typ.)
Figure 28. Threshold hysteresis vs. temperature, VHYST = 200 mV (typ.)
3.20
3.25
3.30
3.35
3.40
3.45
3.50
-40 -20 0 20 40 60 80
Temperature, TA (°C)
Threshold, VTH+ (V)
AM04705v1
170
180
190
200
210
220
230
-40 -20 0 20 40 60 80
Temperature, T
A (°C)
Threshold hysteresis, VHTYST (mV)
AM04706v1
STM6600, STM6601 Typical operating characteristics
Doc ID 15453 Rev 11 31/52
Figure 29. Debounce period vs. supply voltage
Figure 30. CSRD charging current vs. temperature, VCC = 3.6 V
15
20
25
30
35
40
45
3.544.555.5
Supply voltage, VCC (V)
Debounce period, tDEBOUNCE (ms)
TA = 85 °C
TA = 25 °C
TA = 0 °C
TA = –40 °C
AM04707v1
100
110
120
130
140
150
160
170
180
190
200
-40 -20 0 20 40 60 80
Temperature, TA (°C)
CSRD charging current, ISRD (nA)
VCC = 5.5 V
VCC = 3.6 V
VCC = 2 V
AM04708v1
Typical operating characteristics STM6600, STM6601
32/52 Doc ID 15453 Rev 11
Figure 31. Output low voltage vs. output low current, TA = 25 °C
Note: Characteristics valid for all the outputs (EN, EN, RST, INT, PBOUT and VCCLO).
Figure 32. Output high voltage vs. output high current, TA = 25 °C
Note: Characteristics valid for EN and EN outputs.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
012345
Output low current, IOL (mA)
Output low voltage, VOL (V)
VCC=1.6V
VCC=3.6V
VCC=5.5V
AM04709v1
0
0.2
0.4
0.6
0.8
00.511.52
Output high current, IOH (mA)
Output high voltage, V
CC
- V
OH
(V)
VCC=1.6V
VCC=3.6V
VCC=5.5V
AM04710v1
STM6600, STM6601 Typical operating characteristics
Doc ID 15453 Rev 11 33/52
Figure 33. Output voltage vs. supply voltage, IOUT = 1 mA, TA = 25 °C
Note: Characteristics valid for all the outputs (EN, EN, RST, INT, PBOUT and VCCLO).
Figure 34. Input voltage vs. temperature
Note: Characteristics valid for PB, SR and PSHOLD inputs.
0
0.2
0.4
0.6
0.8
1
012345
Supply voltage, VCC (V)
Output voltage, VOUT (V)
AM04711v1
0.99
1.00
1.01
1.02
1.03
1.04
1.05
-40 -20 0 20 40 60 80
Temperature, TA (°C)
Input voltage, V
IN
(V)
VCC = 3.6 V
VCC = 5.5 V
AM04712v1
Typical operating characteristics STM6600, STM6601
34/52 Doc ID 15453 Rev 11
Figure 35. Reference output voltage vs. temperature, VCC = 2.0 V
Note: 1 µF capacitor is connected to the VREF pin.
Figure 36. Reference output voltage vs. load current, VCC = 2.0 V, TA = 25 °C
Note: 1 µF capacitor is connected to the VREF pin.
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
-40 -20 0 20 40 60 80
Temperature, T
A (°C)
Reference output voltage, V
REF
(V)
IREF = 0 mA
IREF = 15 µA
AM04713v1
1
1.1
1.2
1.3
1.4
1.5
1.6
050100150200250300
Load current, IREF (µA)
Reference output voltage, V
REF
(V)
AM04714v1
STM6600, STM6601 Typical operating characteristics
Doc ID 15453 Rev 11 35/52
Figure 37. Reference output voltage vs. supply voltage, TA = 25 °C
Note: 1 µF capacitor is connected to the VREF pin.
Figure 38. Reference startup, IREF = 15 µF, TA = 25 °C
Note: 1 µF capacitor is connected to the VREF pin.
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
22.533.5 4 4.5 5 5.5
Supply voltage, V
CC
(V)
Reference output voltage, V
REF
(V)
IREF = 0 µA
I
REF
= 15 µA
AM04715v1
Typical operating characteristics STM6600, STM6601
36/52 Doc ID 15453 Rev 11
Figure 39. Reference response to steps on supply voltage, IREF = 15 µA, TA = 25 °C
Note: 1 Supply voltage goes from 3.6 V to 5.5 V and back to 3.6 V, ramp 1 V / 100 ns.
2 1 µF capacitor is connected to the VREF pin.
STM6600, STM6601 Typical operating characteristics
Doc ID 15453 Rev 11 37/52
Figure 40. Reference response to steps in load current, VCC = 3.6 V, TA = 25 °C
Note: 1 Supply voltage goes from 0 µA to 15 µA and back to 0 µA, ramp 1 µA / 100 ns.
2 1 µF capacitor is connected to the VREF pin.
Maximum ratings STM6600, STM6601
38/52 Doc ID 15453 Rev 11
6 Maximum ratings
Stressing the device above the rating listed inTa ble 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in Table 4 of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol Parameter Min. Max. Unit Remarks
VCC Input supply voltage –0.3 +7.0 V
Input voltages on PB, SR, PSHOLD and
CSRD
–0.3 VCC + 0.3 V
Output voltages on EN (EN), RST and
INT –0.3 VCC + 0.3 V
VESD Electrostatic protection –2 +2 kV Human body model (all pins)
–8 +8 kV Human body model (PB and SR)
VESD Electrostatic protection –1000 +1000 V Charged device model
VESD Electrostatic protection –200 +200 V Machine model
VESD Point discharge on PB and SR inputs –8 +8 kV IEC61000-4-2
VESD Air discharge on PB and SR inputs –15 +15 kV IEC61000-4-2
TAOperating ambient temperature –40 +85 °C
TSTG Storage temperature –45 +150 °C
TSLD(1) Lead solder temperature for 10 seconds +260 °C
θJA Thermal resistance (junction to ambient) +132.4 °C/W
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
STM6600, STM6601 DC and AC characteristics
Doc ID 15453 Rev 11 39/52
7 DC and AC characteristics
This section summarizes the operating measurement conditions and the DC and AC
characteristics of the device. The parameters inTable 5 that follow are derived from tests
performed under the measurement conditions summarized in Table 4. Designers should
check that the operating conditions in their circuit match the operating conditions when
relying on the quoted parameters.
Table 4. Operating and AC measurement conditions
Parameter Condition Unit
VCC supply voltage 1.6 to 5.5 V
Ambient operating temperature (TA) –40 to 85 °C
Input rise and fall times ≤
_
5ns
Table 5. DC and AC characteristics
Symbol Parameter Test condition(1) Min. Typ.(2) Max. Unit
VCC Supply voltage 1.6 5.5 V
ICC Supply current
VCC = 3.6 V, no load 6.0 8.0 µA
Standby mode, enable
deasserted, VCC = 3.6 V 0.6 1.0 µA
VTH+
Power-on lockout voltage
(see Ta b l e 1 0 for detailed
listing)
2.40 2.50 2.60
V
3.00 3.10 3.20
3.20 3.30 3.40
3.29 3.40 3.51
3.39 3.50 3.61
VHYST
Threshold hysteresis (see
Table 10 for detailed listing)
200
mV
500
VTH–
Forced power-off voltage
(see Ta b l e 1 0 for detailed
listing)
VTH+ – VHYST V
tTH–
Undervoltage detection to
INT delay VCC ≥ 2.0 V203244ms
tON_BLANK
Blanking period (see
Table 10 for detailed
listing)(3)
1.4 2.2 3.0
s5.6 8.8 12.0
11.2 17.6 24.0
RST assertion to EN (EN)
assertion delay during
power-up
VCC = 3.6 V 100 ns
DC and AC characteristics STM6600, STM6601
40/52 Doc ID 15453 Rev 11
PB
VIL Input low voltage VCC ≥ 2.0 V, enable asserted 0.99 V
VIH Input high voltage VCC ≥ 2.0 V, enable asserted 1.05 V
tDEBOUNCE Debounce period VCC ≥ 2.0 V203244ms
RPB Internal pull-up resistor VCC = 5.5 V, input asserted 65 100 135 kΩ
SR
VIL Input low voltage 0.99 V
VIH Input high voltage 1.05 V
tDEBOUNCE Debounce period 20 32 44 ms
RSR(4) Internal pull-up resistor VCC = 5.5 V, input asserted 65 100 135 kΩ
PBOUT
VOL Output low voltage VCC = 2 V, ISINK = 1 mA,
PBOUT asserted 0.3 V
PBOUT leakage current VPBOUT = 3 V, PBOUT open
drain –0.1 +0.1 µA
VCCLO
VOL Output low voltage VCC = 2 V, ISINK = 1 mA,
VCCLO asserted 0.3 V
VCCLO leakage current VVCCLO = 3 V, VCCLO open
drain –0.1 +0.1 µA
PSHOLD
VIL Input low voltage VCC ≥ 2.0 V0.99V
VIH Input high voltage VCC ≥ 2.0 V1.05 V
Glitch immunity 1 80 µs
PSHOLD leakage current VPSHOLD = 0.6 V –0.1 0.1 µA
PSHOLD to enable
propagation delay 30 µs
RPSHOLD
Pull-down resistor
connected internally during
power-up
VPSHOLD = 5.5 V 195 300 405 kΩ
Table 5. DC and AC characteristics (continued)
Symbol Parameter Test condition(1) Min. Typ.(2) Max. Unit
STM6600, STM6601 DC and AC characteristics
Doc ID 15453 Rev 11 41/52
CSRD
ISRD CSRD charging current 100 150 200 nA
VSRD CSRD voltage threshold
VCC = 3.6 V, load on VREF pin
100 kΩ and mandatory 1 µF
capacitor, TA = 25 °C
1.5 V
tSRD
Additional Smart Reset™
delay time External CSRD connected 10 s/µF
EN, EN
VOL Output low voltage VCC = 2 V, ISINK = 1 mA,
enable asserted 0.3 V
VOH(5) Output high voltage VCC = 2 V, ISOURCE = 1 mA,
enable asserted VCC – 0.3 V
tEN_OFF(6) enable off to enable on VCC ≥ 2.0 V406488ms
EN, EN leakage current VEN = 2 V, enable open drain –0.1 +0.1 µA
RST
VOL Output low voltage VCC = 2 V, ISINK = 1 mA,
RST asserted 0.3 V
tREC RST pulse width VCC ≥ 2.0 V 240 360 480 ms
RST leakage current VRST = 3V –0.1 +0.1 µA
INT
VOL Output low voltage VCC = 2 V, ISINK = 1 mA,
INT asserted 0.3 V
tINT_Min Minimum INT pulse width VCC ≥ 2.0 V203244ms
INT leakage current VINT = 3 V –0.1 +0.1 µA
VREF
VREF 1.5 V voltage reference
VCC = 3.6 V, load on VREF pin
100 kΩ and mandatory 1 µF
capacitor, TA = 25 °C
1.485
–1% 1.5 1.515
+1% V
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.6 V to 5.5 V (except where noted).
2. Typical values are at TA = +25 °C.
3. This blanking time allows the processor to start up correctly (see Figure 7, 8, 9, 10, 11, 12).
4. The internal pull-up resistor connected to the SR input is optional (see Table 10 for detailed device options).
5. Valid for push-pull only.
6. Minimum delay time between enable deassertion and enable reassertion, allowing the application to complete the power-down
properly. PB is ignored during this period.
Table 5. DC and AC characteristics (continued)
Symbol Parameter Test condition(1) Min. Typ.(2) Max. Unit
Package mechanical data STM6600, STM6601
42/52 Doc ID 15453 Rev 11
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
STM6600, STM6601 Package mechanical data
Doc ID 15453 Rev 11 43/52
Figure 41. TDFN12 (2 x 3 mm) package outline
Table 6. TDFN12 (2 x 3 mm) package mechanical data
Symbol
mm inches
Min. Typ. Max. Min. Typ. Max.
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.15 0.20 0.25 0.006 0.008 0.010
D 3.00 BSC 0.118
E 2.00 BSC 0.079
e 0.50 0.020
L 0.45 0.55 0.65 0.018 0.022 0.026
e
12
(D/2xE/2)
INDEX AREA
L
BOTTOM VIEW
7
PIN#1 ID
1
b
6
E
SEATING
TOP VI EW
A
A1
SIDE VIEW
PLANE
2x
D
(D/2xE/2)
INDEX AREA
0.10 C
0.10 C
0.10 C
0.10 C A B
C
B
A
0.08 C
8070542_A
Package mechanical data STM6600, STM6601
44/52 Doc ID 15453 Rev 11
Figure 42. TDFN12 (2 x 3 mm) recommended footprint
Note: Drawing not to scale.
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$IMENSIONS MM
INCHES
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


STM6600, STM6601 Package mechanical data
Doc ID 15453 Rev 11 45/52
Figure 43. Carrier tape for TDFN12 (2 x 3 mm) package
T
K0
P1
A0
B0
P2
P0
CENTER LINES
OF CAVITY
W
E
F
D
TOP COVER
TAPE
USER DIRECTION OF FEED
AM03073v1
Table 7. Carrier tape dimensions for TDFN12 (2 x 3 mm) package
Package W D E P0P2FA
0B0K0P1TUnit
Bulk
qty.
TDFN12 12.00
±0.30
1.50
+0.10/
–0.00
1.75
±0.10
4.00
±0.10
2.00
±0.10
5.50
±0.05
2.30
±0.10
3.20
±0.10
1.10
±0.01
4.00
±0.10
0.30
±0.05 mm 3000
Part numbering STM6600, STM6601
46/52 Doc ID 15453 Rev 11
9 Part numbering
Table 8. STM6600 ordering information scheme
Example: STM660 0 F Q 2 4 DM 6 F
Device type
STM660
Startup process
0: PB must be held low until the PSHOLD confirmation
Input and output types(1)
A: active high EN output, long push asserts RST, pull-up on SR
B: active low EN output, long push asserts RST, pull-up on SR
C: active high EN output, long push deasserts EN, pull-up on SR
D: active low EN output, long push deasserts EN, pull-up on SR
E: active high EN output, long push asserts RST, no resistor on SR
F: active low EN output, long push asserts RST, no resistor on SR
G: active high EN output, long push deasserts EN, no resistor on SR
H: active low EN output, long push deasserts EN, no resistor on SR
VTH+ threshold voltage(1)
A: 2.50 V
Q: 3.30 V
S: 3.40 V
U: 3.50 V
VHYST voltage hysteresis(1)
2: 200 mV
5: 500 mV
tON_BLANK blanking period(1)
2: 1.4 s (min.)
4: 5.6 s (min.)
5: 11.2 s (min.)
STM6600, STM6601 Part numbering
Doc ID 15453 Rev 11 47/52
Package
DM: TDFN12
Temperature range
6: –40 °C to +85 °C
Shipping method
F: ECOPACK® package, tape and reel
1. Other options are offered. Minimum order quantities may apply. Please contact local ST sales office for availability.
Table 8. STM6600 ordering information scheme (continued)
Example: STM660 0 F Q 2 4 DM 6 F
Part numbering STM6600, STM6601
48/52 Doc ID 15453 Rev 11
Table 9. STM6601 ordering information scheme
Example: STM660 1 G U 2 B DM 6 F
Device type
STM660
Startup process
1: PB can be released before the PSHOLD confirmation
Input and output types(1)
A: active high EN output, long push asserts RST, pull-up on SR
B: active low EN output, long push asserts RST, pull-up on SR
C: active high EN output, long push deasserts EN, pull-up on SR
D: active low EN output, long push deasserts EN, pull-up on SR
G: active high EN output, long push deasserts EN, no resistor on SR
VTH+ threshold voltage(1)
M: 3.10 V
Q: 3.30 V
S: 3.40 V
U: 3.50 V
VHYST voltage hysteresis(1)
2: 200 mV
tON_BLANK blanking period(1)
B: 1.4 s (min.)
D: 5.6 s (min.)
Package
DM: TDFN12
Temperature range
6: –40 °C to +85 °C
Shipping method
F: ECOPACK® package, tape and reel
1. Other options are offered. Minimum order quantities may apply. Please contact local ST sales office for availability.
STM6600, STM6601 Product selector
Doc ID 15453 Rev 11 49/52
10 Product selector
Table 10. STM6600 product selector
Full part number EN or
EN(1)
1. EN (or EN) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain.
After
long
push(2)
2. After tSRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN) pin
will be deasserted. The additional Smart Reset™ delay time, tSRD, can be adjusted by the user at 10 s/µF (typ.) by
connecting the external capacitor to the CSRD pin.
Internal
resistor
on SR
input
Power-on
lockout
voltage
VTH+ (V)
Forced
power-off
voltage
VTH- (V)
tON_BLANK
(s)
at startup
(min.)
tON_BLANK
(s)
at reset
(min.)
Top
marking(3)
3. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52).
STM6600AS24DM6F EN RST pull-up 3.40 3.20 5.6 5.6 pyww
AS24
STM6600BQ24DM6F EN RST pull-up 3.30 3.10 5.6 5.6 pyww
BQ24
STM6600CS25DM6F EN EN pull-up 3.40 3.20 11.2 — pyww
CS25
STM6600DA55DM6F EN EN pull-up 2.50 2.00 11.2 — pyww
DA55
STM6600DQ25DM6F EN EN pull-up 3.30 3.10 11.2 — pyww
DQ25
STM6600DU25DM6F EN EN pull-up 3.50 3.30 11.2 — pyww
DU25
STM6600ES24DM6F(4)
4. Please contact local ST sales office for availability.
EN RST — 3.40 3.20 5.6 5.6 pyww
ES24
STM6600FQ24DM6F(4) EN RST — 3.30 3.10 5.6 5.6 pyww
FQ24
STM6600GS22DM6F(4) EN EN — 3.40 3.20 1.4 — pyww
GS22
STM6600GS25DM6F(4) EN EN — 3.40 3.20 11.2 — pyww
GS25
STM6600GU22DM6F(4) EN EN — 3.50 3.30 1.4 — pyww
GU22
STM6600HA55DM6F(4) EN EN — 2.50 2.00 11.2 — pyww
HA55
STM6600HQ25DM6F(4) EN EN — 3.30 3.10 11.2 — pyww
HQ25
STM6600HU25DM6F(4) EN EN — 3.50 3.30 11.2 — pyww
HU25
Product selector STM6600, STM6601
50/52 Doc ID 15453 Rev 11
Table 11. STM6601 product selector
Full part number EN or
EN(1)
1. EN (or EN) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain.
After
long
push(2)
2. After tSRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN) pin
will be deasserted. The additional Smart Reset™ delay time, tSRD, can be adjusted by the user at 10 s/µF (typ.) by
connecting the external capacitor to the CSRD pin.
Internal
resistor
on SR
input
Power-on
lockout
voltage
VTH+ (V)
Forced
power-off
voltage
VTH- (V)
tON_BLANK
(s)
at startup
(min.)
tON_BLANK
(s)
at reset
(min.)
Top
marking(3)
3. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52).
STM6601AQ2BDM6F EN RST pull-up 3.30 3.10 1.4 1.4 pyww
AQ2B
STM6601AU2DDM6F EN RST pull-up 3.50 3.30 5.6 5.6 pyww
AU2D
STM6601BM2DDM6F EN RST pull-up 3.10 2.90 5.6 5.6 pyww
BM2D
STM6601BS2BDM6F EN RST pull-up 3.40 3.20 1.4 1.4 pyww
BS2B
STM6601CM2DDM6F EN EN pull-up 3.10 2.90 5.6 — pyww
CM2D
STM6601CQ2BDM6F EN EN pull-up 3.30 3.10 1.4 — pyww
CQ2B
STM6601CU2BDM6F EN EN pull-up 3.50 3.30 1.4 — pyww
CU2B
STM6601DS2BDM6F EN EN pull-up 3.40 3.20 1.4 — pyww
DS2B
STM6601GU2BDM6F(4)
4. Please contact local ST sales office for availability.
EN EN — 3.50 3.30 1.4 — pyww
GU2B
STM6600, STM6601 Revision history
Doc ID 15453 Rev 11 51/52
11 Revision history
Table 12. Document revision history
Date Revision Changes
04-Mar-2009 1 Initial release.
05-Jun-2009 2
Updated text in Section 2, Section 3, Figure 11, 12; updated Figure 1, 7,
9, 14, 18, 19, 43, Ta b l e 3 , 5, 8, 9, 10; added Figure 8, 10, Ta b le 7 ;
reformatted document.
23-Jul-2009 3 Updated text in Features, Table 1, 8, 9, and 10; reformatted document.
22-Oct-2009 4
Updated Section 2, Table 5, Ta b le 1 0 , Figure 1, 7, 8, 9, 10, 11, 12, 14, 18,
title of Section 10; added Section 5: Typical operating characteristics
(Figure 23 through 40); document status upgraded to full datasheet.
25-Jan-2010 5 Updated Figure 6, Section 2, Table 5; textual update to “Smart Reset™”.
13-Apr-2010 6 Updated Figure 1, 6, 7, 8, 9, 10, 11, 12, 13, Section 2, Section 3, Ta b le 3 ,
5, 8, 9, 10.
07-Jun-2010 7
Reformatted Figure 1 and Figure 42, corrected typo in Section 3, added
option A to Ta bl e 8 , updated Table 10 and separated Ta bl e 1 0 to Table 10
and Ta bl e 1 1 .
10-Sep-2010 8 Updated standby current to 0.6 µA throughout datasheet; removed
footnote 2 of Figure 14; updated Table 8, 9, 11; minor textual updates.
24-Feb-2011 9 Updated Ta bl e 1 1 - removed footnote 4.
12-May-2011 10 Updated Ta b l e 8 , Ta b l e 1 0 and Table 11, minor text and typo
modifications throughout document.
26-Jun-2012 11
Updated Section 1: Description, “SR - Smart Reset™ button input” in
Section 2: Pin descriptions and “Hardware reset or power-down while
system not responding” in Section 3: Operation, added cross-references
in Section 6: Maximum ratings and Section 7: DC and AC characteristics.
STM6600, STM6601
52/52 Doc ID 15453 Rev 11
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