SC628 System Clock Generator Supporting Synchronous/Asynchronous PCI System Board Designs Preliminary FREQUENCY TABLE PRODUCT FEATURES Supports Synchronous / Asynchronous PCI system board designs with P54, P55, and P6, Cyrix and AMD CPU's. 12 CPU clocks for SDRAM support. 90 mA buffer switching current @ 3.3V Current controlled buffers for lower EMI. Selectable Offset Delay between CPU and PCI clocks. Selectors S2 S1 S0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Outputs(MHz) CPU PCI F.A.S.T. 83.33 33.33 3.25% 75.17 37.59 4.76% 55.07 27.54 4.76% TEST TEST TEST 50.11 25.06 4.76% 66.66 33.33 4.76% 60.14 30.07 4.76% 75.17 30.07 4.76% F.A.S.T. (Frequency Augmentation System Test) function for increased host/PCI speed. Optional common or mixed supply mode: VDD=VDDq=3.3V, VDD=3.3V, VDDq=2.5V. CONNECTION DIAGRAM 34 Pin SSOP. BLOCK DIAGRAM XIN REF0 / F.A.S.T. REF REF1 / DLY XOUT PLL1 S0 12 CPU(0:7), (10:12) B S1 S2 VDDQ F.A.S.T. DLY PCI DELAY CONTROL UNIT B B CPU(8:9)/S(0:1) 6 PCI(0:5) 48MHz PLL2 24MHz VDD Xin Xout VSS CPU1 / S2 CPU2 CPU3 VDDQ CPU4 CPU5 VSS CPU6 CPU7 VDDQ CPU8 / S1 CPU9 / S0 CPU10 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Rev.1.2 REF0 / F.A.S.T. REF1 / DLY VDD 24 MHZ 48 MHZ VSS PCI1 PCI2 VDD PCI3 PCI4 VSS PCI5 PCI6 VSS CPU12 CPU11 6/16/97 Page 1 of 6 SC628 System Clock Generator Supporting Synchronous/Asynchronous PCI System Board Designs Preliminary PIN DESCRIPTION Xin, Xout - On-chip reference oscillator buffer. These pins are connected to the terminals of a parallel (or anti-) resonant crystal. Xin may also be used as input for an externally generated signal; in this case Xout must be left unconnected (floating.) CPU(1:12) - Low skew host clocks outputs. CPU1 / S2, CPU8 / S1, and CPU9 / S0 are bidirectionals pins. During power-up these pins are in input mode and are considered frequency select lines; they have internal pull-ups (see table, page 1 for frequency selection, and fig.2 page 4, for selection application note). When the power reaches the VDD rail, the select data is latched internally to the IC and these pins become CPU clock outputs. (See Fig.1) These pins are powered by VDDQ at either 2.5 or 3.3 volts. PCI(1:6) - Low skew PCI clock outputs. These outputs are synchronous to CPU clocks except when selectors are set to (000) or (111) in the frequency table where the PCI clocks are Pseudo-synchronous. REF0 / F.A.S.T., REF1 / DLY - These are bidirectional pins. During power-up, These pins are in input mode and are used for enabling the F.A.S.T. mode and for selecting the offset delay between CPU and PCI clocks (See table below); they have internal pull-ups. When F.A.S.T. is low (see fig.2 page 4, for selection application note), CPU and PCI frequencies are increased by a certain percentage as listed in the table on page 1. When the power reaches the VDD rail (See Fig.1), the select data is latched internally to the IC and these pins become buffered outputs of the crystal. DLY select 1 0 MIN 1 0 Toff (nS) TYP MAX 4 2 48MHz - USB clock output. 24MHz - SIO clock output VSS - Circuit ground. VDD - 3.3 volt power supply. A 0.1F capacitor must be placed as close as possible to each VDD pin. Otherwise the filtering intent of the cap will be neutralized by the trace lead inductance. VDDQ - 3.3 or 2.5 volt power supply for CPU clocks. VDD Power Supply CPU1 / S2 CPU8 / S1 CPU9 / S0 REF0 / F.A.S.T. REF1 / DLY toggle , outputs Hi-Z (tristate), inputs Fig.1 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 6/16/97 Page 2 of 6 SC628 System Clock Generator Supporting Synchronous/Asynchronous PCI System Board Designs Preliminary MAXIMUM RATINGS Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Ambient Temperature: Maximum Operating Supply: -0.3V 0.3V -65C to 150C -55C to +125C 7V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to its circuit. For proper operation, Vin and Vout should be constrained to the range: VSS <(Vin,Vout)< VDD Unused inputs must always be tied to an appropriate logic voltage level (either Vss or VDD). ELECTRICAL CHARACTERISTICS Characteristic Input Low Voltage Input High Voltage Current on Pull (up/down) Output Low Voltage IOL = 12mA Output High Voltage IOH=12mA Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol VIL VIH IIL, IIH VOL Min Typ Max Units - - 0.8 Vdc 2.0 - - Vdc -66, 5 A 0.4 Vdc - - Conditions S2, S1, S0, F.A.S.T., DLY All outputs VOH 2.4 - - Vdc IOZ IDD IDD IOS - - 10 A - - TBD mA CPU* = 66.6 MHz - - TBD A Xin = 1 25 - - mA 1 output at a time - max 30 sec. VDD = 3.3V + 10%. TA = 0C to 70C INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 6/16/97 Page 3 of 6 SC628 System Clock Generator Supporting Synchronous/Asynchronous PCI System Board Designs Preliminary SWITCHING CHARACTERISTICS Characteristic Symbol Typ Max Units Output Rise (0.8V - 2.0V) tTLH, Min - - 1.5 nS 40 pF load. ALL OUTPUTS* Conditions and Fall (2.0V-0.8V) time Output duty cycle CPU*-Skew PCI*-Skew tTHL t1SKW t2SKW 45 - 50 - 1.5 55 250 500 nS % pS pS 40 pF load. ALL OUTPUTS* Measured at 1.5V Measured at 1.5V Measured at 1.5V CPU* - PCI* OFFSET CPU* - PCI* OFFSET tOFF1 tOFF0 1 0 - 4 2 Cycle to cycle Period P - - + 250 nS nS pS Measured at 1.5V, DLY = 1 Measured at 1.5V, DLY = 0 Measured at 1.5V on CPU* Jitter Absolute Switching current (AC) tjab Iol, Ioh - 90 500 - pS mA Measured at 1.5V on CPU* CPU* and PCI* outputs VDD = 3.3V + 10%. TA = 0C to 70C PCB LAYOUT RECOMMENDATION FB1 Via to VCC plane Via to VDD island VCC IMISC628 Via to GND plane C8 This is only a layout recommendation for best performance and lower EMI. The designer may choose a differnent approach such as using VDD traces instead of islands (dashed areas). Also, the designer may choose to use more than one bead. Regardless of which way the layout is implemented, Bypass caps : C3, C4, C5, C6, and C7 (all 0.1F) should always be used and placed as close to their VDD pins as possible. C8 (22F) is for EMI reduction. Caps should be multilayer low impedance at high frequencies such as Z5U material. C3 C4 C5 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 1 34 2 33 3 32 4 31 5 30 6 29 7 28 8 27 9 26 10 25 11 24 12 23 13 22 14 21 15 20 16 19 17 18 Rev.1.2 C7 C6 6/16/97 Page 4 of 6 SC628 System Clock Generator Supporting Synchronous/Asynchronous PCI System Board Designs Preliminary SELECTOR APPLICATION Pins 5, 15, 16, 33 and 34 are bidirectional pins and are used for selecting the output frequency of the CPU clocks, enabling the F.A.S.T. mode, and/or selecting delay time (Toff) between CPU and PCI clocks. During power-up of the SC628, these pins are in input mode (see Fig1, page 2), therefore, they are considered input select pins S2, S1, S0, F.A.S.T, and DLY. (see Fig.1, page2). Internal to the IC, these pins have large value pull-ups, therefore, if a selection "1" is the default. If a selection "0" is required, then an external 10K pull-down is required as in Fig.2. Note : the Selection resistor 10 K must be placed close the pin and before the dedamping resistor (Rd). Applicable to pins : 5, 15, 16, 33, 34 IMISC628 Rd To load 10K Jumper Fig. 2 PACKAGE DRAWINGS AND DIMENSIONS 34 PIN SSOP OUTLINE DIMENSIONS INCHES SYMBOL C A L H E D a A2 A A1 B e INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 MILLIMETERS MIN NOM MAX MIN NOM MAX 0.097 0.101 0.104 2.46 2.56 2.64 A1 0.0050 0.009 0.0115 0.127 0.22 0.29 A2 0.090 0.092 0.094 2.29 2.34 2.39 B 0.014 0.016 0.019 0.35 0.41 0.48 C 0.0091 0.010 0.0125 0.23 0.25 0.32 D 0.701 0.706 0.711 17.81 17.93 18.06 E 0.292 0.296 0.299 7.42 7.52 7.59 e 0.040 BSC 1.016 BSC H 0.400 0.406 0.410 10.16 10.31 10.41 a 0.10 0.013 0.016 0.25 0.33 0.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0 4 8 0 4 8 X 0.085 0.093 0.100 2.16 2.36 2.54 Rev.1.2 6/16/97 Page 5 of 6 SC628 System Clock Generator Supporting Synchronous/Asynchronous PCI System Board Designs Preliminary ORDERING INFORMATION Part Number Package Type Production Flow IMISC628BYB 34 Pin SSOP Commercial, 0 C to + 70 C Marking: Example: IMI SC628BYB Date Code, Lot # IMISC628BYB Flow B = Commerical, 0 C to + 70 C Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 6/16/97 Page 6 of 6