Integrated Silicon Solution, Inc.
1
Rev. E
01/08/2010
IS61(64)LF12832A IS64VF12832A
IS61(64)LF12836A IS61(64)VF12836A
IS61(64)LF25618A IS61(64)VF25618A
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
•
Three chip enable option for simple depth expan-
sion
and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VF: VDD 2.5V -5% +10%, VDDQ 2.5V -5% +10%
• JEDEC 100-Pin TQFP, 119-pin PBGA, and
165-pin PBGA packages
• Automotive temperature available
• Lead-free available
JANUARY 2010
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
DESCRIPTION
The ISSI IS61(64)LF12832A, IS64VF12832A,
IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are
high-speed, low-power synchronous static
RAMs
designed
to provide burstable,
high-performance
memory for commu-
nication and networking applications. The
IS61(64)LF12832A is organized as 131,072 words by 32
bits. The IS61(64)LF/VF12836A is organized as 131,072
words by 36 bits. The IS61(64)LF/VF25618A is organized
as 262,144 words by 18 bits. Fabricated with ISSI's
advanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All syn-
chronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol Parameter -6.5 -7.5 Units
tKQ Clock Access Time 6.5 7.5 ns
tKC Cycle Time 7.5 8.5 ns
Frequency 133 117 MHz
2
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
BLOCK DIAGRAM
17/18
BINARY
COUNTER
GW
CLR
CE
CLK Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
15/16 17/18
ADDRESS
REGISTER
CE
D
CLK
Q
DQ(a-d)
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
BWE
BW(a-d)
x18: a,b
x32/x36: a-d
CE
CE2
CE2
128Kx32;
128Kx36;
256Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OE
2/4/8
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
A
POWER
DOWN
ZZ
Integrated Silicon Solution, Inc.
3
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
BOTTOM VIEW
BOTTOM VIEW
165-PIN BGA
165-Ball, 13x15 mm BGA
119-PIN BGA
119-Ball, 14x22 mm BGA
4
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
119 BGA PACKAGE PIN CONFIGURATION
128K X 36 (TOP VIEW)
PIN DESCRIPTIONS
123456 7
AVDDQ AAADSP AAVDDQ
BNC CE2 A ADSC ACE2 NC
CNC A A VDD A A NC
DDQc DQPc Vss NC Vss DQPb DQb
EDQc DQc Vss CE Vss DQb DQb
FVDDQ DQc Vss OE Vss DQb VDDQ
GDQc DQc BWc ADV BWb DQb DQb
HDQc DQc Vss GW Vss DQb DQb
JVDDQ VDD NC VDD NC VDD VDDQ
KDQd DQd Vss CLK Vss DQa DQa
LDQd DQd BWd NC BWa DQa DQa
MVDDQ DQd Vss BWE Vss DQa VDDQ
NDQd DQd Vss A1* Vss DQa DQa
PDQd DQPd Vss A0* Vss DQPa DQa
RNC A MODE VDD NC A NC
TNC NC A A A NC ZZ
UVDDQ NC NC NC NC NC VDDQ
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW Global Write Enable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Controls
BWE Byte Write Enable
Symbol Pin Name
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
NC No Connect
DQa-DQd Data Inputs/Outputs
DQPa-Pd Output Power Supply
VDD Power Supply
VDDQ Output Power Supply
Vss Ground
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Integrated Silicon Solution, Inc.
5
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
119 BGA PACKAGE PIN CONFIGURATION
256KX18 (TOP VIEW)
PIN DESCRIPTIONS
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
123456 7
AVDDQ AAADSP AA VDDQ
BNC CE2 A ADSC ACE2 NC
CNC A A VDD A A NC
DDQb NC Vss NC Vss DQPa NC
ENC DQb Vss CE Vss NC DQa
FVDDQ NC Vss OE Vss DQa VDDQ
GNC DQb BWb ADV Vss NC DQa
HDQb NC Vss GW Vss DQa NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQb Vss CLK Vss NC DQa
LDQb NC Vss NC BWa DQa NC
MVDDQ DQb Vss BWE Vss NC VDDQ
NDQb NC Vss A1* Vss DQa NC
PNC DQPb Vss A0* Vss NC DQa
RNC A MODE VDD NC A NC
TNC A A NC A A ZZ
UVDDQ NC NC NC NC NC VDDQ
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW Global Write Enable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Controls
BWE Byte Write Enable
Symbol Pin Name
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
NC No Connect
DQa-DQb Data Inputs/Outputs
DQPa-Pb Output Power Supply
VDD Power Supply
VDDQ Output Power Supply
Vss Ground
6
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
PIN DESCRIPTIONS
165 PBGA PACKAGE PIN CONFIGURATION
128K X 36 (TOP VIEW)
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
1234567891011
ANC A CE BWc BWb CE2 BWE ADSC ADV ANC
BNC A CE2 BWd BWa CLK GW OE ADSP ANC
CDQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NC DQPb
DDQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb
EDQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb
FDQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb
GDQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb
HNC NC NC VDD Vss Vss Vss VDD NC NC ZZ
JDQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa
KDQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa
LDQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa
MDQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa
NDQPd NC VDDQ Vss NC NC NC Vss VDDQ NC DQPa
PNC NC A A NC A1*NCAAANC
RMODE NC A A NC A0*NCAAAA
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW Global Write Enable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
Symbol Pin Name
BWE Byte Write Enable
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
NC No Connect
DQx Data Inputs/Outputs
DQPx Data Inputs/Outputs
VDD 3.3V/2.5V Power Supply
VDDQ Isolated Output Power Supply
3.3V/2.5V
Vss Ground
Integrated Silicon Solution, Inc.
7
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
165 PBGA PACKAGE PIN CONFIGURATION
256K X 18 (TOP VIEW)
PIN DESCRIPTIONS
1234567891011
ANC A CE BWb NC CE2 BWE ADSC ADV AA
BNC A CE2 NC BWa CLK GW OE ADSP ANC
CNC NC VDDQ Vss Vss Vss Vss Vss VDDQ NC DQPa
DNC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa
ENC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa
FNC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa
GNC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa
HNC NC NC VDD Vss Vss Vss VDD NC NC ZZ
JDQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC
KDQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC
LDQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC
MDQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC
NDQPb NC VDDQ Vss NC NC NC Vss VDDQ NC NC
PNC NC A A NC A1*NCAAANC
RMODE NC A A NC A0*NCAAAA
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW Global Write Enable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write
Controls
Symbol Pin Name
BWE Byte Write Enable
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
NC No Connect
DQx Data Inputs/Outputs
DQPx Data Inputs/Outputs
VDD 3.3V/2.5V Power Supply
VDDQ Isolated Output Power Supply
3.3V/2.5V
Vss Ground
8
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock
DQa-DQd Synchronous Data Input/Output
DQPa-DQPd Parity Data Input/Output
GW Synchronous Global Write Enable
MODE Burst Sequence Mode Selection
OE Output Enable
VDD 3.3V/2.5V Power Supply
VDDQ Isolated Output Buffer Supply:
3.3V/2.5V
Vss Ground
ZZ Snooze Enable
PIN CONFIGURATION
(3 Chip-Enable option)
100-PIN TQFP (128K x 36)
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
100-PIN TQFP (128K x 32)
(3 Chip-Enable option)
Integrated Silicon Solution, Inc.
9
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
PIN CONFIGURATION
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWb Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock
DQa-DQb Synchronous Data Input/Output
DQPa-DQPb Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GW Synchronous Global Write Enable
MODE Burst Sequence Mode Selection
OE Output Enable
VDD 3.3V/2.5V Power Supply
VDDQ Isolated Output Buffer Supply:
3.3V/2.5V
Vss Ground
ZZ Snooze Enable
100-PIN TQFP (256K x 18)
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
10
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
PARTIAL TRUTH TABLE
Function GWGW
GWGW
GW BWEBWE
BWEBWE
BWE BWaBWa
BWaBWa
BWa BWbBWb
BWbBWb
BWb BWcBWc
BWcBWc
BWc BWdBWd
BWdBWd
BWd
Read H H X X X X
Read H L H H H H
Write Byte 1 H L L H H H
Write All Bytes H L L L L L
Write All Bytes L X X X X X
TRUTH TABLE(1-8)
OPERATION ADDRESS
CECE
CECE
CE CE2CE2
CE2CE2
CE2 CE2 ZZ ADSPADSP
ADSPADSP
ADSP ADSCADSC
ADSCADSC
ADSC ADVADV
ADVADV
ADV WRITEWRITE
WRITEWRITE
WRITE OEOE
OEOE
OE CLK DQ
Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z
Deselect Cycle, Power-Down None L X L L L XXXXL-HHigh-Z
Deselect Cycle, Power-Down None L H X L L XXXXL-HHigh-Z
Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z
Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z
Snooze Mode, Power-Down None X X X H X XXXXXHigh-Z
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycle, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H HHHHL-HHigh-Z
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X HHHHL-HHigh-Z
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are
available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc.
11
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
1,0
0,1A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
TSTG Storage Temperature –55 to +150 °C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to Vss for I/O Pins –0.5 to VDDQ + 0.5 V
VIN Voltage Relative to Vss for –0.5 to VDD + 0.5 V
for Address and Control Inputs
VDD Voltage on VDD Supply Relative to Vss –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
12
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V 2.5V
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA (3.3V) 2.4 — 2.0 — V
IOH = –1.0 mA (2.5V)
VOL Output LOW Voltage IOL = 8.0 mA (3.3V) — 0.4 — 0.4 V
IOL = 1.0 mA (2.5V)
VIH Input HIGH Voltage 2.0 VDD + 0.3 1.7 VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.8 –0.3 0.7 V
ILI Input Leakage Current VSS ≤ VIN ≤ VDD
(1)
–5 5 –5 5 µA
ILO Output Leakage Current VSS ≤ VOUT ≤ VDDQ, OE = VIH –5 5 –5 5 µA
OPERATING RANGE (IS61/64LFxxxxx)
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 3.3V ± 5% 3.3V/2.5V ± 5%
Industrial -40°C to +85°C 3.3V ± 5% 3.3V/2.5V ± 5%
Automotive -40°C to +125°C 3.3V ± 5% 3.3V/2.5V ± 5%
OPERATING RANGE (IS61/64VFxxxxx)
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 2.5V -5% +10% 2.5V -5% +10%
Industrial -40°C to +85°C 2.5V -5% +10% 2.5V -5% +10%
Automotive -40°C to +125°C 2.5V -5% +10% 2.5V -5% +10%
Integrated Silicon Solution, Inc.
13
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
6.5
7.5
MAX MAX
Symbol Parameter Test Conditions
Temp. range x18 x32/x36 x18 x32/x36 Uni
t
ICC AC Operating Device Selected, Com. 175 175 155 155 mA
Supply Current OE = VIH, ZZ ≤ VIL, Ind. 180 180 160 160
All Inputs ≤ 0.2V or ≥ VDD – 0.2V, AUTO. 190 190 175 175
Cycle Time ≥ tKC min. typ.
(2)
120 110
ISB Standby Current Device Deselected, Com. 90 90 90 90 mA
TTL Input VDD = Max., Ind. 100 100 100 100
All Inputs ≤ VIL or ≥ VIH, Auto. 120 120 120 120
ZZ ≤ VIL, f = Max.
ISBI Standby Current Device Deselected, Com. 70 70 70 70 mA
CMOS Input VDD = Max., Ind. 75 75 75 75
VIN
≤
VSS + 0.2V or ≥VDD – 0.2V Auto. 90 90 90 90
f = 0 typ. 40 40
ISB2Sleep Mode ZZ>VIH Com. 30 30 30 30 mA
Ind. 35 35 35 35
Auto. 45 45 45 45
typ. 25 25
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100 µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
14
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
3.3V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1
OUTPUT
ZO
= 50Ω
1.5V
50Ω
Integrated Silicon Solution, Inc.
15
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 3 and 4
ZO = 50Ω
1.25V
50Ω
OUTPUT
1,667 Ω
5 pF
Including
jig and
scope
1,538 Ω
OUTPUT
+2.5V
Figure 3 Figure 4
2.5V I/O OUTPUT LOAD EQUIVALENT
16
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
6.5 7.5
Symbol Parameter Min. Max. Min. Max. Unit
fmax Clock Frequency — 133 — 117 MHz
tKC Cycle Time 7.5 — 8.5 — ns
tKH Clock High Time 2.2 — 2.5 — ns
tKL Clock Low Time 2.2 — 2.5 — ns
tKQ Clock Access Time — 6.5 — 7.5 ns
tKQX(2) Clock High to Output Invalid 2.5 — 2.5 — ns
tKQLZ(2,3) Clock High to Output Low-Z 2.5 — 2.5 — ns
tKQHZ(2,3) Clock High to Output High-Z — 3.8 — 4.0 ns
tOEQ Output Enable to Output Valid — 3.2 — 3.4 ns
tOEQX(2) Output Enable to Output Invalid 2.5 — 2.5 — ns
tOELZ(2,3) Output Enable to Output Low-Z 0 — 0 — ns
tOEHZ(2,3) Output Disable to Output High-Z — 3.5 — 3.5 ns
tAS Address Setup Time 1.5 — 1.5 — ns
tSS Address Status Setup Time 1.5 — 1.5 — ns
tWS Read/Write Setup Time 1.5 — 1.5 — ns
tCES Chip Enable Setup Time 1.5 — 1.5 — ns
tAVS Address Advance Setup Time 1.5 — 1.5 — ns
tDS Data Setup Time 1.5 — 1.5 — ns
tAH Address Hold Time 0.5 — 0.5 — ns
twHWrite Hold Time 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — ns
tDH Data Hold Time 0.5 — 0.5 — ns
tPDS ZZ High to Power Down — 2 — 2 cyc
tPUS ZZ Low to Power Down — 2 — 2 cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
17
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
READ/WRITE CYCLE TIMING
Single Read
Flow-through
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWd-BWa
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQX
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
t
KQLZ
t
KQ
t
KQ
t
KQX
18
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWd-BWa
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE1 inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z 1a 3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
Integrated Silicon Solution, Inc.
19
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
SNOOZE MODE TIMING
Don't Care
Deselect or Read Only Deselect or Read Only
tRZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
ISB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
tPDS tPUS
tZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
ISB2Current during SNOOZE MODE ZZ ≥ Vih — 60 mA
tPDS ZZ active to input ignored — 2 cycle
tPUS ZZ inactive to input sampled 2 — cycle
tZZI ZZ active to SNOOZE current — 2 cycle
tRZZI ZZ inactive to exit SNOOZE current 0 — ns
20
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Configuration Access Time Order Part Number Package
128Kx32 6.5 IS61LF12832A-6.5TQ 100 TQFP
IS61LF12832A-6.5B2 119 PBGA
IS61LF12832A-6.5B3 165 PBGA
128Kx32 7.5 IS61LF12832A-7.5TQ 100 TQFP
IS61LF12832A-7.5B2 119 PBGA
IS61LF12832A-7.5B3 165 PBGA
128Kx36 6.5 IS61LF12836A-6.5TQ 100 TQFP
IS61LF12836A-6.5B2 119 PBGA
IS61LF12836A-6.5B3 165 PBGA
128Kx36 7.5 IS61LF12836A-7.5TQ 100 TQFP
IS61LF12836A-7.5B2 119 PBGA
IS61LF12836A-7.5B3 165 PBGA
256Kx18 6.5 IS61LF25618A-6.5TQ 100 TQFP
IS61LF25618A-6.5TQL 100 TQFP, Lead-free
IS61LF25618A-6.5B2 119 PBGA
IS61LF25618A-6.5B3 165 PBGA
256Kx18 7.5 IS61LF25618A-7.5TQ 100 TQFP
IS61LF25618A-7.5B2 119 PBGA
IS61LF25618A-7.5B3 165 PBGA
Integrated Silicon Solution, Inc.
21
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)
Industrial Range: -40°C to +85°C
Configuration Access Time Order Part Number Package
128Kx32 6.5 IS61LF12832A-6.5TQI 100 TQFP
IS61LF12832A-6.5B2I 119 PBGA
IS61LF12832A-6.5B3I 165 PBGA
128Kx32 7.5 IS61LF12832A-7.5TQI 100 TQFP
IS61LF12832A-7.5TQLI 100 TQFP, Lead-free
IS61LF12832A-7.5B2I 119 PBGA
IS61LF12832A-7.5B3I 165 PBGA
128Kx36 6.5 IS61LF12836A-6.5TQI 100 TQFP
IS61LF12836A-6.5TQLI 100 TQFP, Lead-free
IS61LF12836A-6.5B2I 119 PBGA
IS61LF12836A-6.5B3I 165 PBGA
128Kx36 7.5 IS61LF12836A-7.5TQI 100 TQFP
IS61LF12836A-7.5TQLI 100 TQFP, Lead-free
IS61LF12836A-7.5B2I 119 PBGA
IS61LF12836A-7.5B3I 165 PBGA
256Kx18 6.5 IS61LF25618A-6.5TQI 100 TQFP
IS61LF25618A-6.5B2I 119 PBGA
IS61LF25618A-6.5B3I 165 PBGA
256Kx18 7.5 IS61LF25618A-7.5TQI 100 TQFP
IS61LF25618A-7.5TQLI 100 TQFP, Lead-free
IS61LF25618A-7.5B2I 119 PBGA
IS61LF25618A-7.5B3I 165 PBGA
Automotive Range: -40°C to +125°C
Configuration Access Time Order Part Number Package
128Kx32 7.5 IS64LF12832A-7.5TQA3 100 TQFP
IS64LF12832A-7.5TQLA3 100 TQFP, Lead-free
128Kx36 7.5 IS64LF12836A-7.5TQA3 100 TQFP
256Kx18 7.5 IS64LF25618A-7.5TQA3 100 TQFP
22
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
ORDERING INFORMATION (VDD = 2.5V /VDDQ = 2.5V)
Commercial Range: 0°C to +70°C
Configuration Access Time Order Part Number Package
128Kx36 6.5 IS61VF12836A-6.5TQ 100 TQFP
IS61VF12836A-6.5B2 119 PBGA
IS61VF12836A-6.5B3 165 PBGA
128Kx36 7.5 IS61VF12836A-7.5TQ 100 TQFP
IS61VF12836A-7.5B2 119 PBGA
IS61VF12836A-7.5B3 165 PBGA
256Kx18 6.5 IS61VF25618A-6.5TQ 100 TQFP
IS61VF25618A-6.5B2 119 PBGA
IS61VF25618A-6.5B3 165 PBGA
256Kx18 7.5 IS61VF25618A-7.5TQ 100 TQFP
IS61VF25618A-7.5B2 119 PBGA
IS61VF25618A-7.5B3 165 PBGA
Industrial Range: -40°C to +85°C
Configuration Access Time Order Part Number Package
128Kx36 6.5 IS61VF12836A-6.5TQI 100 TQFP
IS61VF12836A-6.5B2I 119 PBGA
IS61VF12836A-6.5B3I 165 PBGA
128Kx36 7.5 IS61VF12836A-7.5TQI 100 TQFP
IS61VF12836A-7.5B2I 119 PBGA
IS61VF12836A-7.5B3I 165 PBGA
256Kx18 6.5 IS61VF25618A-6.5TQI 100 TQFP
IS61VF25618A-6.5B2I 119 PBGA
IS61VF25618A-6.5B3I 165 PBGA
256Kx18 7.5 IS61VF25618A-7.5TQI 100 TQFP
IS61VF25618A-7.5B2I 119 PBGA
IS61VF25618A-7.5B3I 165 PBGA
Automotive Range: -40°C to +125°C
Configuration Access Time Order Part Number Package
128Kx32 7.5 IS64VF12832A-7.5TQLA3 100 TQFP, Lead-free
128Kx36 7.5 IS64VF12836A-7.5TQA3 100 TQFP
256Kx18 7.5 IS64VF25618A-7.5TQA3 100 TQFP
Integrated Silicon Solution, Inc.
23
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
24
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
1. CONTROLLING DIMENSION : MM .
NOTE :
2. Reference document : JEDEC MS-028
10/02/2008
Package Outline
Integrated Silicon Solution, Inc.
25
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
1. CONTROLLING DIMENSION : MM .
NOTE :
Package Outline 08/28/2008
