Fully Accurate 16-Bit VOUT nanoDAC
SPI Interface 2.7 V to 5.5 V in an MSOP
AD5063
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
FEATURES
Single 16-bit DAC, 1 LSB INL
Power-on reset to midscale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
10-lead MSOP, low power
Fast settling time of 1 μs maximum (AD5063-1 model)
2.7 V to 5.5 V power supply
Low glitch on power-up
Unbuffered voltage capable of driving 60 kΩ load
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
AD5063
V
DD
V
OUT
V
REF
POWER-ON
RESET
DAC
REGISTER DAC
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC RESISTOR
NETWORK
REF(+)
SCLK DIN
04766-001
SYNC DACGND
BUF
A
GND
R
FB
INV
Figure 1.
Table 1. Related Devices
Part No. Description
AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A,
4 LSBs INL, SOT-23.
AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, SOT-23.
AD5040/AD5060 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A,
1 LSB INL, SOT-23.
GENERAL DESCRIPTION
The AD5063, a member of ADI’s nanoDAC™ family, is a low
power, single 16-bit, unbuffered voltage-output DAC that operates
from a single 2.7 V to 5 V supply. The part offers a relative
accuracy specification of ±1 LSB, and operation is guaranteed
monotonic with a ±1 LSB DNL specification. The AD5063
comes with on-board resistors in a 10-lead MSOP, allowing
bipolar signals to be generated with an output amplifier. The
part uses a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and that is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
reference for the AD5063 is supplied from an external VREF pin.
A reference buffer is also provided on-chip. The part incor-
porates a power-on reset circuit that ensures the DAC output
powers up to midscale and remains there until a valid write to
the device takes place. The part contains a power-down feature
that reduces the current consumption of the device to typically
300 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode via the serial interface. Total unadjusted error for the part
is <1 mV.
This part exhibits very low glitch on power-up.
PRODUCT HIGHLIGHTS
Available in 10-lead MSOP.
16-bit accurate, 1 LSB INL.
Low glitch on power-up.
High speed serial interface with clock speeds up to 30 MHz.
Three power-down modes available to the user.
AD5063
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
DAC Architecture ....................................................................... 13
Reference Buffer ......................................................................... 13
Serial Interface ............................................................................ 13
Input Shift Register .................................................................... 13
SYNC Interrupt .......................................................................... 13
Power-On to Midscale ............................................................... 14
Software Reset ............................................................................. 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing ....................................................... 14
Applications ..................................................................................... 16
Choosing a Reference for the AD5063 .................................... 16
Bipolar Operation Using the AD5063 ..................................... 16
Using the AD5063
with a Galvanically Isolated Interface Chip ............................ 17
Power Supply Bypassing and Grounding ................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
8/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Output Voltage Settling Time Parameter, Table 2 ... 3
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
3/06—Rev. A to Rev. B
Updated Format .................................................................. Universal
Change to Features ........................................................................... 1
Change to Figure 1 ........................................................................... 1
Changes to Specifications ................................................................ 3
Change to Absolute Maximum Ratings ......................................... 6
Change to Reference Buffer Section ............................................ 13
Change to Serial Interface Section ............................................... 13
Change to Table 6 ........................................................................... 14
Change to Bipolar Operation Using the AD5063 Section ........ 16
7/05—Rev. 0 to Rev. A
Changes to Galvanically Isolated Chip Section .......................... 17
Changes to Figure 38 ...................................................................... 17
4/05—Revision 0: Initial Version
AD5063
Rev. C | Page 3 of 20
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VREF = 4.096 V @ VDD = 5.0 V, RL = unloaded, CL = unloaded to GND; TMIN to TMAX, unless otherwise noted.
Table 2.
B Version1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1 LSB −40°C to + 85°C, B grade over all codes
Total Unadjusted Error (TUE) ±500 ±800 μV
Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic
Gain Error ±0.01 ±0.02 % FSR TA = −40°C to +85°C
Gain Error Temperature Coefficient 1 ppm FSR/°C
Zero-Code Error ±0.05 ±0.1 mV All 0s loaded to DAC register,
TA = −40°C to +85°C
Zero-Code Error Temperature Coefficient 0.05 μV/°C
Offset Error ±0.05 ±0.1 mV TA = −40°C to +85°C
Offset Error Temperature Coefficient 0.5 μV/°C
Full-Scale Error ±500 ±800 μV All 1s loaded to DAC register,
TA = −40°C to +85°C
Bipolar Resistor Matching 1 Ω/Ω RFB/RINV, RFB = RINV = 30 kΩ typically
Bipolar Zero Offset Error ±8 ±16 LSB
Bipolar Zero Temperature Coefficient ±0.5 ppm FSR/°C
Bipolar Gain Error ±16 ±32 LSB
OUTPUT CHARACTERISTICS2
Output Voltage Range 0 VREF V Unipolar operation
−VREF V
REF V Bipolar operation
Output Voltage Settling Time3 ¼ scale to ¾ scale code transition to ±1 LSB
AD5063BRMZ 4 μs
AD5063BRMZ-1 1 μs VDD = 4.5 V to 5.5 V
4 μs VDD = 2.7 V to 5.5 V
Output Noise Spectral Density 64 nV/√Hz DAC code = midscale, 1 kHz
Output Voltage Noise 6 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry
Digital Feedthrough 0.002 nV-s
DC Output Impedance (Normal) 8 kΩ Output impedance tolerance ±10%
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network) 1 kΩ Output impedance tolerance ±400 Ω
(Output Connected to 10 kΩ Network) 100 kΩ Output impedance tolerance ±20 kΩ
REFERENCE INPUT/OUPUT
VREF Input Range 2 VDD − 50 mV
Input Current (Power-Down) ±1 μA Zero-scale loaded
Input Current (Normal) ±1 μA
DC Input Impedance 1 MΩ Bipolar/unipolar operation
LOGIC INPUTS
Input Current4 ±1 ±2 μA
Input Low Voltage, VIL 0.8 V VDD = 4.5 V to 5.5 V
0.8 VDD = 2.7 V to 3.6 V
Input High Voltage, VIH 2.0 V VDD = 2.7 V to 5.5 V
1.8 VDD = 2.7 V to 3.6 V
Pin Capacitance 4 pF
AD5063
Rev. C | Page 4 of 20
B Version1
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.7 5.5 V All digital inputs at 0 V or VDD
IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 0.65 0.7 mA VIN = VDD and VIL = GND, VDD = 5 V,
VREF = 4.096 V, code = midscale
VDD = 2.7 V to 3.6 V 0.5 mA VIH = VDD and VIL = GND, VDD = 3 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V 1 μA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 1 μA VIH = VDD and VIL = GND
Power Supply Rejection Ratio (PSRR) 0.5 LSB ∆VDD ± 10%, VDD = 5 V, unloaded
1 Temperature ranges for the B version: −40°C to +85°C, typical at +25°C, functional to +125°C.
2 Guaranteed by design and characterization, not production tested.
3 See the Ordering Guide.
4 Total current flowing into all pins.
AD5063
Rev. C | Page 5 of 20
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Limit1 Unit Test Conditions/Comments
t12 33 ns min SCLK cycle time
t2 5 ns min SCLK high time
t3 3 ns min SCLK low time
t4 10 ns min
SYNC to SCLK falling edge setup time
t5 3 ns min Data setup time
t6 2 ns min Data hold time
t7 0 ns min
SCLK falling edge to SYNC rising edge
t8 12 ns min
Minimum SYNC high time
t9 9 ns min
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0D1D2D22D23
SYNC
SCLK
04766-002
t
9
t
1
t
8
D23 D22
DIN
Figure 2. Timing Diagram
AD5063
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
VOUT to GND −0.3 V to VDD + 0.3 V
VREF to GND −0.3 V to VDD + 0.3 V
INV to GND −0.3 V to VDD + 0.3 V
RFB to GND +7 V to −7 V
Operating Temperature Range
Industrial (B Version) −40°C to + 85°C1
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
MSOP Package
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 206°C/W
θJc Thermal Impedance 44°C/W
Reflow Soldering (Pb-Free)
Peak Temperature 260(0/−5)°C
Time at Peak Temperature 10 sec to 40 sec
ESD 1.5 kV
1 Temperature range for this device is −40°C to +85°C; however, the device is
still operational at 125°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5063
Rev. C | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5063
TOP VIEW
(Not to Scale)
V
OUT
SYNC
110
AGND
SCLK
29
DIN
DACGND
38
04766-003
V
REF
47
V
DD
INV R
FB
56
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.
3 VREF Reference Voltage Input.
4 VOUT Analog Output Voltage from DAC.
5 INV Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amp’s inverting
input in bipolar mode.
6 RFB Feedback Resistor. In bipolar mode, connect this pin to the external op amp circuit.
7 AGND Ground Reference Point for Analog Circuitry.
8 DACGND Ground Input to the DAC.
9 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in
which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
10 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 30 MHz.
AD5063
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
04766-047
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 10000 20000 30000 40000 50000 60000 70000
DAC CODE
INL ERROR (LSB)
1.2
1.4 T
A
= 25°C
V
DD
= 5V V
REF
= 4.096V
04766-046
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 10000 20000 30000 40000 50000 60000 70000
DAC CODE
DNL ERROR (LSB)
T
A
= 25°C
V
DD
= 5V V
REF
= 4.096V
Figure 4. INL Error vs. DAC Code Figure 7. DNL Error vs. DAC Code
04766-048
0 10000 20000 30000 40000 50000 60000 70000
DAC CODE
TUE ERROR (mV)
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10 T
A
= 25°C
V
DD
= 5V V
REF
= 4.096V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
DNL ERROR (LSB)
V
DD
= 5.5V V
REF
= 4.096V
V
DD
= 2.7V V
REF
= 2.0V
MAX DNL @ V
DD
= 5.5V
MAX DNL @ V
DD
= 2.7V
MIN DNL @ V
DD
= 2.7V
MIN DNL @ V
DD
= 5.5V
04766-013
Figure 5. TUE Error vs. DAC Code Figure 8. DNL Error vs. Temperature
V
DD
= 5.5V V
REF
= 4.096V
V
DD
= 2.7V V
REF
= 2.0V
–1.0
–0.8
–0.6
–0.4
–0.2
0.2
0.4
0.6
0.8
1.0
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
TUE ERROR (LSB)
04766-009
MAX TUE @ 2.7V MAX TUE @ 5.5V
MIN TUE @ 5.5V
MIN TUE @ 2.7V
0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
INL ERROR (LSB)
04766-012
V
DD
= 5.5V V
REF
= 4.096V
V
DD
= 2.7V V
REF
= 2.0V MAX INL @ V
DD
= 2.7V
MAX INL @ V
DD
= 5.5V
MIN INL @ V
DD
= 2.7V
MIN INL @ V
DD
= 5.5V
Figure 6. INL Error vs. Temperature Figure 9. TUE Error vs. Temperature
AD5063
Rev. C | Page 9 of 20
–3
–2
–1
0
1
2
3
1
REFERENCE VOLTAGE (V)
INL ERROR (LSB)
T
A
= 25°C
MAX INL @ V
DD
= 5.5V
MIN INL @ V
DD
= 5.5V
62345
04766-004
Figure 10. INL Error vs. Reference Input Voltage
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1
REFERENCE VOLTAGE (V)
DNL ERROR (LSB)
T
A
= 25°C
62345
MIN DNL V
DD
= 5.5V
MAX DNL V
DD
= 5.5V
04766-044
Figure 11. DNL Error vs. Reference Input Voltage
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
1
REFERENCE VOLTAGE (V)
TUE ERROR (mV)
T
A
= 25°C
62345
MIN TUE @ V
DD
= 5.5V
MAX TUE @ V
DD
= 5.5V
04766-005
Figure 12. TUE Error vs. Reference Input Voltage
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
OFFSET (mV)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
V
DD
= 5.5V V
REF
= 4.096V
V
DD
= 2.7V V
REF
= 2.0V
MAX OFFSET @ V
DD
= 5.5V
MAX OFFSET @ V
DD
= 2.7V
04766-007
Figure 13. Offset vs. Temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
04766-041
V
DD
= 3V V
REF
= 2.7V
V
DD
= 5.5V V
REF
= 4.096V
Figure 14. Supply Current vs. Temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 10000 20000 30000 40000 50000 60000 70000
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
04766-042
T
A
= 25°C
V
DD
= 5.5V V
REF
= 4.096V
V
DD
= 3V V
REF
= 2.5V
Figure 15. Supply Current vs. Digital Input Code
AD5063
Rev. C | Page 10 of 20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.7 3.2 3.7 4.2 4.7 5.2 5.7
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
04766-043
TA = 25°C
VREF = 2.7V
Figure 16. Supply Current vs. Supply Voltage
04766-015
CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/DIV
24TH CLOCK FALLING
CH1 = SCLK
CH2 = VOUT
Figure 17. Digital-to-Analog Glitch Impulse (See Figure 21)
0
50
100
150
200
250
300
1000 10000 100000 1000000
FREQUENCY (Hz)
NOISE SPECTRAL DENSITY (nV/ Hz)
V
DD
= 5V
T
A
= 25°C
V
REF
= 4.096V
FULL SCALE
MIDSCALE
ZERO SCALE
100
04766-011
Figure 18. Output Noise Spectral Density
04766-026
CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs
CH2 = V
OUT
CH1 = TRIGGER
CH3 = SCLK
Figure 19. Exiting Power-Down Time to Midscale
04766-018
VDD = 3V
DAC = FULL SCALE
VREF = 2.7V
TA = 25°C
Y-AXIS = 2µV/DIV
X-AXIS = 4sec/DIV
Figure 20. 0.1 Hz to 10 Hz Noise Plot
04766-017
50 100 150 200 250 300 350 400 450 5000
SAMPLES
AMPLITUDE (200µV/DIV)
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25°C
10ns/SAMPLE
Figure 21. Glitch Energy
AD5063
Rev. C | Page 11 of 20
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
04766-010
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
0.010
GAIN ERROR (%fsr)
GAIN ERROR @ V
DD
= 5.5V
GAIN ERROR @ V
DD
= 2.7V
V
DD
= 5.5V V
REF
= 4.096V
V
DD
= 2.7V V
REF
= 2.0V
04766-022
CH1 2V/DIV CH2 1V/DIV TIME BASE = 100µs
V
DD
= 5V V
REF
= 4.096V
RAMP RATE = 200µs
T
A
= 25
°
C
CH1 = V
DD
CH2 = V
OUT
Figure 22. Gain Error vs. Temperature Figure 25. Hardware Power-Down Glitch
0
2
4
6
8
10
12
14
16
18
20
0.550
0.565
0.580
0.595
0.610
0.625
0.640
0.655
0.680
MORE
BIN
FREQUENCY
04766-049
04766-020
CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV
TIME BASE 1µs/DIV
CH3 = V
OUT
CH4 = TRIGGER
CH2 = SYNC
CH1 = SCLK
V
DD
= 5V V
REF
= 4.096V
T
A
= 25°C
Figure 26. Exiting Software Power-Down Glitch
Figure 23. IDD Histogram @ VDD = 5 V
0
5
10
15
20
25
30
35
BIN
FREQUENCY
0.465
0.475
0.485
0.495
0.505
0.515
0.525
0.535
0.545
04766-050
Figure 24. IDD Histogram @ VDD = 3 V
AD5063
Rev. C | Page 12 of 20
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL error vs. code plot is shown in Figure 4.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL error vs. code plot is shown in Figure 7.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5063 because the output of the DAC cannot go below 0 V.
This is due to a combination of the offset errors in the DAC
and output amplifier. Zero-code error is expressed in mV.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed as a percentage
of the full-scale range.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percentage of the full-scale range.
Tota l Un a dju ste d Error ( T UE)
Total unadjusted error is a measure of the output error, taking
all the various errors into account. A typical TUE vs. code plot
is shown in Figure 5.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with a
change in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition. See Figure 17 and Figure 21.
Figure 17 shows the glitch generated following completion of
the calibration routine; Figure 21 zooms in on this glitch.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
AD5063
Rev. C | Page 13 of 20
THEORY OF OPERATION
The AD5063 is a single 16-bit, serial input, voltage-output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is
written to the AD5063 in a 24-bit word format via a 3-wire serial
interface.
The AD5063 incorporates a power-on reset circuit that ensures
the DAC output powers up to midscale. The device also has a
software power-down mode pin that reduces the typical current
consumption to less than 1 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5063 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 27. The four MSBs of the 16-bit data-word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either the DACGND or VREF
buffer output. The remaining 12 bits of the data-word drive
Switches S0 to S11 of a 12-bit voltage mode R-2R ladder
network.
2R
04766-027
S0
VREF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
VOUT
12-BIT R-2R LADDER FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 27. DAC Ladder Structure
REFERENCE BUFFER
The AD5063 operates with an external reference. The reference
input (VREF) has an input range of 2 V to AVDD − 50 mV. This
input voltage is used to provide a buffered reference for the
DAC core.
SERIAL INTERFACE
The AD5063 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. (See for a
timing diagram of a typical write sequence.)
Figure 2
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
At this stage, the SYNC line can be kept low or be brought
high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence, so that a falling edge of
SYNC can initiate the next write sequence. Because the SYNC
buffer draws more current when VIH = 1.8 V than it does when
VIH = 0.8 V, SYNC should be idled low between write sequences
for even lower power operation of the part. As previously indi-
cated, however, it must be brought high again just before the
next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 28). PD1
and PD0 are bits that control the operating mode of the part
(normal mode or any one of the three power-down modes).
There is a more complete description of the various modes in
the Power-Down Modes section. The next 16 bits are the data
bits. These are transferred to the DAC register on the 24th falling
edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, it acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see ). Figure 31
DATA BITS
DB15 (MSB) DB0 (LSB)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NORMAL OPERATION
1kΩTO GND
100kΩTO GND
THREE-STATE
POWER-DOWN MODES
0
0
1
1
0
1
0
1
04766-028
000000PD1PD0
Figure 28. Input Register Contents
AD5063
Rev. C | Page 14 of 20
POWER-ON TO MIDSCALE
The AD5063 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the midscale code, and the output voltage is midscale until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the DAC
output while it is in the process of powering up.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bits D23 to
D16, which is not the normal mode of operation. Note that the
SYNC interrupt command cannot be performed if a software
reset command is started.
POWER-DOWN MODES
The AD5063 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
Table 6. Modes of Operation for the AD5063
DB17 DB16 Operating Mode
0 0 Normal operation
Power-down mode:
0 1 Three-state
1 0 100 kΩ to GND
1 1 1 kΩ to GND
When both bits are set to 0, the part has normal power con-
sumption. However, for the three power-down modes, the
supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three options: The output
can be connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or it can be left open-circuited
(three-stated). The output stage is illustrated in Figure 29.
POWER-DOWN
CIRCUITRY RESISTOR
NETWORK
V
OUT
AD5063
DAC
04766-029
Figure 29. Output Stage During Power-Down
The bias generator, DAC core, and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V (see Figure 19).
MICROPROCESSOR INTERFACING
AD5063 to ADSP-2101/ADSP-2103 Interface
Figure 30 shows a serial interface between the AD5063 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
AD5063
1ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
DIN
SCLK
04766-030
ADSP-2101/
ADSP-2103
1
Figure 30. AD5063 to ADSP-2101/ADSP-2103 Interface
04766-031
DB23 DB23 DB0DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24
TH
FALLING EDGE
VALID WRITE SEQUENCE:
OUTPUT UPDATES ON THE 24
TH
FALLING EDGE
SYNC
SCLK
DIN
Figure 31. SYNC Interrupt Facility
AD5063
Rev. C | Page 15 of 20
AD5063 to 68HC11/68L11 Interface
Figure 32 shows a serial interface between the AD5063 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5063, and the MOSI output
drives the serial data line of the DAC. The SYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of this interface require that the 68HC11/68L11 be
configured so that its CPOL bit is 0 and its CPHA bit is 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 are configured with their
CPOL bit set to 0 and their CPHA bit set to 1, data appearing
on the MOSI output is valid on the falling edge of SCK. Serial
data from the 68HC11/68L11 is transmitted in 8-bit bytes with
only eight falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. To load data to the AD5063, PC7
is left low after the first eight bits are transferred, and then a
second serial write operation is performed to the DAC, with
PC7 taken high at the end of this procedure.
AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
04766-032
68HC11/
68L11
1
Figure 32. AD5063 to 68HC11/68L11 Interface
AD5063 to Blackfin® ADSP-BF53x Interface
Figure 33 shows a serial interface between the AD5063 and
the Blackfin® ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5063, the
setup for the interface is as follows: DT0PRI drives the DIN pin
of the AD5063, TSCLK0 drives the SCLK of the part, and TFS0
drives SYNC.
ADSP-BF53x
1AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
04766-033
Figure 33. AD5063 to Blackfin ADSP-BF53x Interface
AD5063 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5063 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5063,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5063, P3.3 is taken low. The 80C51/80L51 transmits
data only in 8-bit bytes; therefore, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data in a format that has the LSB first. The
AD5063 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into
account.
80C51/80L51
1AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04766-034
Figure 34. AD5063 to 80C51/80L51 Interface
AD5063 to MICROWIRE Interface
Figure 35 shows an interface between the AD5063 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and clocked into the AD5063
on the rising edge of the SK.
MICROWIRE
1AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
04766-035
Figure 35. AD5063 to MICROWIRE Interface
AD5063
Rev. C | Page 16 of 20
APPLICATIONS
Table 7. Recommended Precision References for the AD5063
Part No.
Initial
Accuracy
(mV max)
Temperature Drift
(ppm/°C max)
CHOOSING A REFERENCE FOR THE AD5063
To achieve optimum performance of the AD5063, thought
should be given to the choice of a precision voltage reference.
The AD5063 has one reference input, VREF. The voltage on the
reference input is used to supply the positive input to the DAC;
therefore, any error in the reference is reflected in the DAC.
0.1 Hz to 10 Hz
Noise (μV p-p typ)
ADR435 ±2 3 (R-8) 8
ADR425 ±2 3 (R-8) 3.4
ADR02 ±3 3 (R-8) 10
ADR02 ±3 3 (SC-70) 10
There are four possible sources of error when choosing a voltage
reference for high accuracy applications: initial accuracy, ppm
drift, long-term drift, and output voltage noise. Initial accuracy
on the output voltage of the DAC leads to a full-scale error in the
DAC. To minimize these errors, a reference with high initial
accuracy is preferred. Also, choosing a reference with an output
trim adjustment, such as the ADR423, allows a system designer to
trim out system errors by setting a reference voltage to a voltage
other than the nominal. The trim adjustment can also be used at
any point within the operating temperature range to trim out error.
ADR395 ±5 9 (TSOT-23) 8
BIPOLAR OPERATION USING THE AD5063
The AD5063 has been designed for single-supply operation, but
a bipolar output range is also possible by using the circuit shown
in Figure 37. This circuit yields an output voltage range of ±4.096 V.
Rail-to-rail operation at the amplifier output is achievable using
AD8675/AD8031/AD8032 or an OP196.
The output voltage for any input code can be calculated as
Because the supply current required by the AD5063 is extremely
low, the parts are ideal for low supply applications. The ADR395
voltage reference is recommended; it requires less than 100 μA of
quiescent current and can, therefore, drive multiple DACs in one
system, if required. It also provides very good noise performance
at 8 μV p-p in the 0.1 Hz to 10 Hz range.
⎥
⎦
⎤
⎢
⎣
⎡⎟
⎠
⎞
⎜
⎝
⎛
×−
⎟
⎠
⎞
⎜
⎝
⎛+
×
⎟
⎠
⎞
⎜
⎝
⎛
×= R1
R2
V
R1
R2R1D
VV DDDD
O536,65
where D represents the input code in decimal (0 to 65,536).
With VREF = 5 V, R1 = R2 = 30 kΩ
AD5063
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
7V
5V
V
OUT
= 0V TO 5V
ADR395
04766-036
V5
65536
10 −
⎟
⎠
⎞
⎜
⎝
⎛×
=D
VO
This is an output voltage range of ±5 V, with 0x0000 corresponding
to a −5 V output and 0xFFFF corresponding to a +5 V output.
04766-037
AD5063
DACGND
VV
REF
DD
OUT
SCLK
DIN
SYNC
+5V
+4.096V
EXTERNAL
OP AMP
BIPOLAR
OUTPUT
10
µ
F
SERIAL
INTERFACE
0.1
µ
F
0.1
µ
F
INV
RINV
+5V
–5V
RFB
R
FB
AGND
+
Figure 36. ADR395 as a Reference to AD5063
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains relatively stable during
its entire lifetime. The temperature coefficient of a reference’s
output voltage affects INL, DNL, and TUE. A reference with a
tight temperature coefficient specification should be chosen to
reduce the temperature dependence of the DAC output voltage
on ambient conditions.
Figure 37. Bipolar Operation
In high accuracy applications, which have a relatively low
tolerance for noise, reference output voltage noise needs to be
considered. It is important to choose a reference with as low an
output noise voltage as practical for the system noise resolution
required. Precision voltage references, such as the ADR435,
produce low output noise in the 0.1 Hz to 10 Hz region. Exam-
ples of some recommended precision references for use as the
supply to the AD5063 are shown in Table 7.
AD5063
Rev. C | Page 17 of 20
USING THE AD5063 WITH A GALVANICALLY
ISOLATED INTERFACE CHIP
In process-control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from hazardous common-
mode voltages that may occur in the area where the DAC is
functioning. iCoupler® provides isolation in excess of 2.5 kV.
Because the AD5063 uses a 3-wire serial logic interface, the
ADuM130x family provides an ideal digital solution for the
DAC interface.
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range of 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.
Figure 38 shows a typical galvanically isolated configuration
using the AD5063. The power supply to the part also needs to
be isolated; this is accomplished by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5063.
VDD
AD5063ADMu1300
POWER 10µF 0.1µF
GND
5V
REGULATOR
SCLKV0A
VOUTV0B SYNC
V0C
V1A
V1B
V1C
SCLK
SDI
DATA DIN
04766-039
Figure 38. AD5063 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to consider
carefully the power supply and ground return layout on the
board. The printed circuit board containing the AD5063 should
have separate analog and digital sections, each on its own area
of the board. If the AD5063 is in a system where other devices
require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5063.
The power supply to the AD5063 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), as do common ceramic types of capacitors.
This 0.1 μF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents from internal
logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by a digital ground. Avoid crossover of digital and analog
signals, if possible. When traces cross on opposite sides of the
board, ensure that they run at right angles to each other to
reduce feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
AD5063
Rev. C | Page 18 of 20
COMPLIANT TO JEDEC STANDARDS MO-187-BA
OUTLINE DIMENSIONS
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
3.10
3.00
2.90
PIN 1
5.15
4.90
4.65
3.10
3.00
2.90
COPLANARITY
0.10
Figure 39. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range INL Settling Time Package Description Package Option Branding
AD5063BRMZ1 −40°C to +85°C 1 LSB 4 μs typ 10-Lead MSOP RM-10 D49
AD5063BRMZ-REEL71 −40°C to +85°C 1 LSB 4 μs typ 10-Lead MSOP RM-10 D49
AD5063BRMZ-11 −40°C to +85°C 1 LSB 1 μs max 10-Lead MSOP RM-10 DCG
AD5063BRMZ-1-REEL71 −40°C to +85°C 1 LSB 1 μs max 10-Lead MSOP RM-10 DCG
EVAL-AD5063EB Evaluation Board
1 Z = RoHS Compliant Part.
AD5063
Rev. C | Page 19 of 20
NOTES
AD5063
Rev. C | Page 20 of 20
NOTES
©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04766-0-8/09(C)
