© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1Publication Order Number:
MC74LVXC3245/D
MC74LVXC3245
Configurable Dual Supply
Octal Transceiver
with 3−State Outputs for 3 V Systems
The 74LVXC3245 is a 24−pin dual−supply, octal configurable
voltage interface transceiver especially well suited for PCMCIA and
other real time configurable I/O applications. The VCCA pin accepts a
3.0 V supply level; the A port is a dedicated 3.0 V port. The VCCB pin
accepts a 3.0 V−to−5.0 V supply level. The B port is configured to
track the VCCB supply level. A 5.0 V level on the VCCB pin will
configure the I/O pins at a 5.0 V level and a 3.0 V VCCB will configure
the I/O pins at a 3.0 V level. The A port interfaces with a 3.0 V host
system and the B port to the card slots. This device will allow the
VCCB voltage source pin and I/O pins on the B port to float when OE is
High. This feature is necessary to buffer data to and from a PCMCIA
socket that permits PCMCIA cards to be inserted and removed during
normal operation. The Transmit/Receive (T/R) input determines the
direction of data flow. Transmit (active−High) enables data from the A
port to B port. Receive (active−Low) enables data from the B port to
the A port.
Features
•Bidirectional Interface Between 3.0 V and 3.0 V/5.0 V Buses
•Control Inputs Compatible with TTL Level
•Outputs Source/Sink Up to 24 mA
•Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
•Available in SOIC and TSSOP Packages
•Flexible VCCB Operating Range
•Allows B Port and VCCB to Float Simultaneously When OE is High
•Functionally Compatible With the 74 Series 245
•These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAMS
SOIC−24
DW SUFFIX
CASE 751E
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
24
LVXC
3245G
ALYW
LVXC3245
AWLYYWWG
1
24
1
24
1
24 TSSOP−24
DT SUFFIX
CASE 948H
LVXC3245 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
MC74LVXC3245
http://onsemi.com
2
B0
OE 22
T/R 2
A0
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
3
4
5
6
7
8
9
10
21
20
19
18
17
16
15
14
Figure 1. 24−Lead Pinout (Top View)
2324 22 21 20 19 18
21 34567
VCCB
17
8
16
9
15
10
NC OE B0 B1 B2 B3 B4 B5 B6
VCCA T/R A0 A1 A2 A3 A4 A5 A6 A7
14
11
13
12
B7 GND
GND GND
Figure 2. Logic Diagram
PIN NAMES
Function
Output Enable Input
Transmit/Receive Input
Side A 3−State Inputs or 3−State Outputs
Side B 3−State Inputs or 3−State Outputs
Pins
OE
T/R
A0−A7
B0−B7
INPUTS
OPERATING MODE
Non−Inverting
OE T/R
L L B Data to A Bus
L H A Data to B Bus
H X Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level
and Transitions are Acceptable; for ICC reasons, Do Not Float Inputs
MC74LVXC3245
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Condition Unit
VCCA,
VCCB
DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage OE, T/R −0.5 to VCCA +0.5 V
VI/O DC Input/Output Voltage An −0.5 to VCCA +0.5 V
Bn −0.5 to VCCB +0.5 V
IIK DC Input Diode Current OE, T/R ±20 VI < GND mA
IOK DC Output Diode Current ±50 VO < GND; VO > VCC mA
IODC Output Source/Sink Current ±50 mA
ICC,
IGND
DC Supply Current Per Output Pin
Maximum Current
±50
±200
mA
TSTG Storage Temperature Range −65 to +150 °C
DC Latchup Source/Sink Current ±300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCCA,
VCCB
Supply Voltage (VCCA ≤ VCCB)V
CCA
VCCB
2.3
3.0
3.6
5.5
V
VIInput Voltage OE, T/R 0 VCCA V
VI/O Input/Output Voltage An
Bn
0
0
VCCA
VCCB
V
TAOperating Free−Air Temperature −40 +85 °C
Dt/DVMinimum Input Edge Rate
VIN from 30% to 70% of VCC; VCC at 3.0 V, 4.5 V, 5.5 V 0 8 ns/V
DC ELECTRICAL CHARACTERISTICS
TA = 25°C TA = −40 to +85°C
Symbol Parameter Condition VCCA VCCB Typ Guaranteed Limits Unit
VIHA Minimum HIGH Level
Input Voltage
An
OE
T/R VOUT ≤ 0.1 V
or
≥ VCC − 0.1 V
2.3
3.0
3.6
3.0
3.6
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIHB
Bn
2.3
3.0
3.6
3.0
3.6
5.5
2.00
2.00
3.85
2.00
2.00
3.85
V
VILA Maximum LOW Level
Input Voltage
An
OE
T/R VOUT ≤ 0.1 V
or
≥ VCC − 0.1 V
2.3
3.0
3.6
3.0
3.6
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VILB
Bn
2.3
3.0
3.6
3.0
3.6
5.5
0.80
0.80
1.65
0.80
0.80
1.65
V
VOHA Minimum HIGH Level
Output Voltage
IOUT = −100 mA
IOH = −12 mA
IOH = −24 mA
IOH = −12 mA
IOH = −24 mA
3.0
3.0
3.0
2.3
2.3
3.0
3.0
3.0
3.0
4.5
2.99
2.85
2.65
2.50
2.30
2.90
2.56
2.35
2.30
2.10
2.90
2.46
2.25
2.20
2.00
V
VOHB IOUT = −100 mA
IOH = −12 mA
IOH = −24 mA
IOH = −24 mA
3.0
3.0
3.0
3.0
3.0
3.0
3.0
4.5
2.99
2.85
2.65
4.25
2.90
2.56
2.35
3.86
2.90
2.46
2.25
3.76
V
MC74LVXC3245
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
TA = −40 to +85°CTA = 25°C
Symbol UnitGuaranteed LimitsTypVCCB
VCCA
ConditionParameter
VOLA Maximum LOW Level
Output Voltage
IOUT = 100 mA
IOL = 24 mA
IOL = 12 mA
IOL = 24 mA
3.0
3.0
2.7
2.7
3.0
3.0
3.0
4.5
0.002
0.21
0.11
0.22
0.10
0.36
0.36
0.42
0.10
0.44
0.44
0.50
V
VOLB IOUT = 100 mA
IOL = 24 mA
IOL = 24 mA
3.0
3.0
3.0
3.0
3.0
4.5
0.002
0.21
0.18
0.10
0.36
0.36
0.10
0.44
0.44
V
IIN Max Input Leakage
Current
OE,
T/R VI = VCCA, GND 3.6
3.6
3.6
5.5
±0.1
±0.1
±1.0
±1.0
mA
IOZA Max 3−State Output
Leakage An
VI = VIH, VIL
OE = VCCA
VO = VCCA, GND
3.6
3.6
3.6
5.5
±0.5
±0.5
±5.0
±5.0
mA
IOZB Max 3−State Output
Leakage Bn
VI = VIH, VIL
OE = VCCA
VO = VCCB, GND
3.6
3.6
3.6
5.5
±0.5
±0.5
±5.0
±5.0
mA
DICC Maximum ICC/Input Bn VI = VCCB−2.1 V 3.6 5.5 1.0 1.35 1.5 mA
All In-
puts VI = VCC−0.6 V 3.6 3.6 0.35 0.5 mA
ICCA1 Quiescent VCCA Sup-
ply Current as B Port
Floats
An = VCCA or GND
Bn = Open,
OE = VCCA,
T/R = VCCA,
VCCB = Open
3.6 Open 5 50
mA
ICCA2 Quiescent VCCA Sup-
ply Current
An = VCCA or GND
Bn = VCCB or
GND, OE = GND,
T/R = GND
3.6
3.6
3.6
5.5
5
5
50
50
mA
ICCB Quiescent VCCB Sup-
ply Current
An = VCCA or GND
Bn = VCCB or
GND, OE = GND,
T/R = VCCA
3.6
3.6
3.6
5.5
5
8
50
80
mA
VOLPA Quiet Output Max Dy-
namic VOL
Notes 1, 2 3.3
3.3
3.3
5.0
0.8
0.8
V
VOLPB Notes 1, 2 3.3
3.3
3.3
5.0
0.8
1.5
V
VOLVA Quiet Output Min Dy-
namic VOL
Notes 1, 2 3.3
3.3
3.3
5.0
−0.8
−0.8
V
VOLVB Notes 1, 2 3.3
3.3
3.3
5.0
−0.8
−1.2
V
VIHDA Min HIGH Level Dy-
namic Input Voltage Notes 1, 3 3.3
3.3
3.3
5.0
2.0
2.0
V
VIHDB Notes 1, 3 3.3
3.3
3.3
5.0
2.0
3.5
V
VILDA Max LOW Level Dy-
namic Input Voltage Notes 1, 3 3.3
3.3
3.3
5.0
0.8
0.8
V
VILDB Notes 1, 3 3.3
3.3
3.3
5.0
0.8
1.5
V
1. Worst case package.
2. Max number of outputs defined as (n). Data inputs are driven 0 V to VCC level; one output at GND.
3. Max number of data inputs (n) switching. (n−1) inputs switching 0 V to VCC level. Input under test switching: VCC level to threshold (VIHD),
0 V to threshold (VILD), f = 1 MHz.
MC74LVXC3245
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS
TA = −40 to +85°C; CL = 50 pF
VCCA = 2.7−3.6 V
VCCB = 4.5−5.5 V
VCCA = 2.7−3.6 V
VCCB = 3.0−3.6 V
Symbol Parameter Min
Typ
(Note 4) Max Min
Typ
(Note 5) Max Unit
tPHL
tPLH
Propagation Delay A to B 1.0
1.0
4.8
3.9
8.5
7.0
1.0
1.0
5.5
5.2
9.0
8.5
ns
tPHL
tPLH
Propagation Delay B to A 1.0
1.0
3.8
4.3
7.0
8.0
1.0
1.0
4.4
5.1
7.5
8.0
ns
tPZL
tPZH
Output Enable Time OE to B 1.0
1.0
4.7
4.8
8.5
9.0
1.0
1.0
6.0
6.1
9.5
10.0
ns
tPZL
tPZH
Output Enable Time OE to A 1.0
1.0
5.9
5.4
10.0
9.5
1.0
1.0
6.4
5.8
10.5
9.5
ns
tPHZ
tPLZ
Output Disable Time OE to B 1.0
1.0
4.0
3.8
8.5
8.0
1.0
1.0
6.3
4.5
10.0
8.5
ns
tPHZ
tPLZ
Output Disable Time OE to A 1.0
1.0
4.6
3.1
10.0
7.0
1.0
1.0
5.2
3.4
10.0
7.0
ns
tOSHL
tOSLH
Output to Output Skew, Data to Output
(Note 6) 1.0 1.5 1.0 1.5 ns
4. Typical values at VCCA = 3.3 V, VCCB = 5.0 V at 25°C.
5. Typical values at VCCA = 3.3 V, VCCB = 3.3 V at 25°C.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
CIN Input Capacitance VCCA = 3.3 V; VCCB = 5.0 V 4.5 pF
CI/O Input/Output Capacitance VCCA = 3.3 V; VCCB = 5.0 V 10 pF
CPD Power Dissipation Capacitance A→B
(Measured at 10 MHz) B→A
VCCB = 5.0 V
VCCA = 3.3 V
50
40
pF
ORDERING INFORMATION
Device Package Shipping†
MC74LVXC3245DWR2G SOIC−24
(Pb−Free)
1000 Tape & Reel
MC74LVXC3245DTG TSSOP−24*
(Pb−Free)
62 Units / Rail
MC74LVXC3245DTR2G TSSOP−24*
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74LVXC3245
http://onsemi.com
6
Figure 3. Block Diagram
SLOT 0
LVXC3245
LVXC3245
SLOT 1
LVXC3245
LVXC3245
SLOT 0
SLOT 1
VCCB
VCCA
OPTIONAL
5 V
VCC
3 V
VCC
POWER
SWITCHES
PCMCIA 2.0
JEIDA 4.1
COMPATIBLE
CONTROLLER
SD(0:15)
SD(0:15)
ISA BUS (IEEE P996)
Configurable I/O Application for PCMCIA Cards
The 74LVXC3245 is a dual−supply device well suited for
PCMCIA configurable I/O applications. The LVXC3245
consumes less than 1mW of quiescent power in all modes of
operation, making it ideal for low power notebook designs.
The LVXC3245 meets all PCMCIA I/O voltage requirements
at 5.0 V and 3.3 V operation. By tying the VCCB pin to the
card voltage supply, the PCMCIA card will always have
rail−to−rail output swings, maximizing the reliability of the
interface.
The VCCA pin must always be tied to a 3.3 V power supply.
This voltage connection provides internal references needed
to account for variations in VCCB. When connected as in the
figure above, the LVXC3245 meets all the voltage and current
requirements of the ISA bus standard (IEEE P996).
MC74LVXC3245
http://onsemi.com
7
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
0 V
VOH
VOL
An, Bn
Bn, An
tPHL
tPLH
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
0 V
≈ 0 V
OE, T/R
An, Bn
tPZH
≈ VCC
tPHZ
tPZL tPLZ
An, Bn
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC 50% VCC
Figure 4. AC Waveforms
50% VCC
VCC
VOH - 0.3 V
VOL + 0.3 V
GND
50% VCC
OPEN
PULSE
GENERATOR
RT
DUT
VCC
RL
R1
CL
2xVCC
TEST SWITCH
tPLH, tPHL, tPZH, tPHZ Open
tPZL, tPLZ 2xVCC
CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 5. Test Circuit
MC74LVXC3245
http://onsemi.com
8
PACKAGE DIMENSIONS
SOIC−24
DW SUFFIX
CASE 751E−04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
−A−
−B−P
12X
D24X
12
1324
1
M
0.010 (0.25) B M
S
A
M
0.010 (0.25) B S
T
−T−
G
22X
SEATING
PLANE K
C
RX 45 _
M
F
JDIM MIN MAX MIN MAX
INCHESMILLIMETERS
A15.25 15.54 0.601 0.612
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.41 0.90 0.016 0.035
G1.27 BSC 0.050 BSC
J0.23 0.32 0.009 0.013
K0.13 0.29 0.005 0.011
M0 8 0 8
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
____
MC74LVXC3245
http://onsemi.com
9
PACKAGE DIMENSIONS
TSSOP−24
DT SUFFIX
CASE 948H−01
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A7.70 7.90 0.303 0.311
B4.30 4.50 0.169 0.177
C--- 1.20 --- 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
J
J1
K
K1
ÉÉ
ÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
13
24
12
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
24X REFK
N
N
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
MC74LVXC3245/D
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
