CY8C4247AZI-M485ES - CYPRESS SEMICONDUCTOR

PSoC® 4: PSoC 4200M Family

Datasheet

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-93963 Rev. *G Revised August 19, 2016

General Description

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The

PSoC 4200M product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic,

programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode,

and standard communication and timing peripherals. The PSoC 4200M products will be fully compatible with members of the PSoC 4

platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning

of the design.

Features

32-bit MCU Subs ys te m

■48 MHz ARM Cortex-M0 CPU with single-cycle multiply

■Up to 128 kB of flash with Read Accelerator

■Up to 16 kB of SRAM

■DMA engine

Programmable Analog

■Four opamps that operate in Deep Sleep mode at very low

current levels

■All opamps have reconfigurable high current pin-drive,

high-bandwidth internal drive, ADC input buffering, and

Comparator modes with flexible connectivity allowing input

connections to any pin

■Four current DACs (IDACs) for general-purpose or capacitive

sensing applications on any pin

■Two low-power comparators that operate in Deep Sleep mode

■12-bit SAR ADC with 1-Msps conversion rate

Programmable Digital

■Four programmable logic blocks, each with 8 Macrocells and

an 8-bit data path (called universal digital blocks or UDBs)

■Cypress-provided peripheral component library, user-defined

state machines, and Verilog input

Low Power 1. 71 to 5.5 V Op era tio n

■20-nA Stop Mode with GPIO pin wakeup

■Hibernate and Deep Sleep modes allow wakeup-time versus

power trade-offs

Capacitive Sensing

■Cypress Capacitive Sigma-Delta (CSD) technique provides

best-in-class SNR (>5:1) and water tolerance

■Cypress-supplied software component makes capacitive

sensing design easy

■Automatic hardware tuning (SmartSense™)

Segment LCD Drive

■LCD drive supported on all pins (common or segment)

■Operates in Deep Sleep mode with 4 bits per pin memory

Serial Communication

■Four independent run-time reconfigurable serial communi-

cation blocks (SCBs) with reconfigurable I2C, SPI, or UART

functionality

■Two independent CAN blocks for industrial and automotive

networking

Timing and Pulse-Width Modulation

■Eight 16-bit timer/counter pulse-width modulator (TCPWM)

blocks

■Center-aligned, Edge, and Pseudo-random modes

■Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

Package Options

■68-pin QFN, 64-pin TQFP wide and narrow pitch, and 48-pin

and 44-pin TQFP packages

■Up to 55 programmable GPIOs

■GPIO pins can be CapSense, LCD, analog, or digital

■Drive modes, strengths, and slew rates are programmable

Extended Industrial Temperature Operat ion

■–40 °C to +105 °C operation

PSoC Creator Design Environment

■Integrated Development Environment (IDE) provides

schematic design entry and build (with analog and digital

automatic routing)

■Applications Programming Interface (API component) for all

fixed-function and programmable peripherals

Industry-Standard Tool Compatibility

■After schematic entry, development can be done with

ARM-based industry-standard development tools

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 2 of 42

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you

to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article

KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:

■Overview: PSoC Portfolio, PSoC Roadmap

■Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP

In addition, PSoC Creator includes a device selection tool.

■Application notes: Cypress offers a large number of PSoC

application notes covering a broad range of topics, from basic

to advanced level. Recommended application notes for getting

started with PSoC 4 are:

❐AN79953: Getting Started With PSoC 4

❐AN88619: PSoC 4 Hardware Design Considerations

❐AN86439: Using PSoC 4 GPIO Pins

❐AN57821: Mixed Signal Circuit Board Layout

❐AN81623: Digital Design Best Practices

❐AN73854: Introduction To Bootloaders

❐AN89610: ARM Cortex Code Optimization

■Technical Reference Manual (TRM) is in two documents:

❐Architecture TRM details each PSoC 4 functional block.

❐Registers TRM describes each of the PSoC 4 registers.

■Development Kits:

❐CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and

inexpensive development platform. This kit includes

connectors for Arduino™ compatible shields and Digilent®

Pmod™ daughter cards.

❐CY8CKIT-049 is a very low-cost prototyping platform. It is a

low-cost alternative to sampling PSoC 4 devices.

❐CY8CKIT-001 is a common development platform for any

one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families

of devices.

The MiniProg3 device provides an interface for flash

programming and debug.

PSoC Creator

PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design

of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100

pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:

1. Drag and drop component icons to build your hardware

system design in the main design workspace

2. Codesign your application firmware with the PSoC hardware,

using the PSoC Creator IDE C compiler

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

Figure 1. Multiple-Se ns or Example Project in PSoC Creator

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 3 of 42

Contents

PSoC 4200M Block Diagram............................................ 4

Functional Definitio n............... ................... ... ... ................ 5

CPU and Memory Subsystem ..................................... 5

System Resources ...................................................... 5

Analog Blocks.............................................................. 6

Programmable Digital.................................................. 7

Fixed Function Digital.................................................. 8

GPIO ........................................................................... 9

Special Function Peripherals....................................... 9

Pinouts ............................ ... .................... .. .................... ... 10

Power.............. .................... ... ................... ... .................... 14

Unregulated External Supply..................................... 14

Regulated External Supply........................................ 14

Development Support....... ... .......................................... 15

Documentation .......................................................... 15

Online ........................................................................ 15

Tools.......................................................................... 15

Electrical Specifications ................................................ 16

Absolute Maximum Ratings....................................... 16

Device Level Specifications....................................... 16

Analog Peripherals.................................................... 20

Digital Peripherals ..................................................... 25

Memory ..................................................................... 27

System Resources .................................................... 28

Ordering Information...................................................... 32

Part Numbering Conventions .................................... 33

Packaging........................................................................ 34

Acronyms........................................................................ 38

Document Conventions......................... ........................ 40

Units of Measure ....................................................... 40

Revision History......... ... ................................................. 41

Sales, Solutions, and Legal Information...................... 42

Worldwide Sales and Design Support....................... 42

Products .................................................................... 42

PSoC® Solutions ...................................................... 42

Cypress Developer Community................................. 42

Technical Support ..................................................... 42

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 4 of 42

PSoC 4200M Block Diagram

The PSoC 4200-M devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The ARM Serial_Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator Integrated Development Environment (IDE)

provides fully integrated programming and debug support for

PSoC 4200-M devices. The SWD interface is fully compatible

with industry-standard third-party tools. The PSoC 4200-M

family provides a level of security not possible with multi-chip

application solutions or with microcontrollers. This is due to its

ability to disable debug features, robust flash protection, and

because it allows customer-proprietary functionality to be imple-

mented in on-chip programmable blocks.

The debug circuits are enabled by default and can only be

disabled in firmware. If not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. Because all programming, debug, and test inter-

faces are disabled when maximum device security is enabled,

PSoC 4200-M with device security enabled may not be returned

for failure analysis. This is a trade-off the PSoC 4200-M allows

the customer to make.

PSoC 4200M

32- bit

AHB- Lite

Deep Sleep

Hibernate

Active / Sleep

CPU Subsystem

SRAM

16 KB

SRAM Controller

ROM

8 KB

ROM Controller

FLASH

128 KB

Read Accelerator

SPCIFSWD/ TC

NVIC, IRQMX

Cortex

48 MHz

FAST MUL

System Interconnect ( Multi Layer AHB)

DataWire/

DMA

Initiator/ MMIO

I/O Subsystem

37x GPIO, 14x GPIO OVT

IOSS GPIO (8x ports)

Peripherals

System Resources

Power

Clock

WDT

ILO

Reset

Clock Control

DFT Logic

Test

IMO

DFT Analog

Sleep Control

PWRSYS

REF

POR LVD

NVLatches

BOD

WIC

Reset Control

XRES

Peripheral Interconnect (MMIO)

PCLK

8x TCP WM

LCD

4x S CB-I2C/SPI/UART

2x LP Comparator

2x Caps ens e

Port Interface & Digital System Interconnect (DSI)

Power Modes

SMX

SAR ADC

(12-bit)

Programmable

Analog

CTBm x2

2x Opamp

2x CA N

Programmable

Digital

... UDBUDB

WCO

High Speed I/O Matrix

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 5 of 42

Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0 CPU in the PSoC 4200-M is part of the 32-bit

MCU subsystem, which is optimized for low-power operation

with extensive clock gating. Most instructions are 16 bits in length

and execute a subset of the Thumb-2 instruction set. The

Cypress implementation includes a hardware multiplier that

provides a 32-bit result in one cycle. It includes a nested vectored

interrupt controller (NVIC) block with 32 interrupt inputs and also

includes a Wakeup Interrupt Controller (WIC), which can wake

the processor up from the Deep Sleep mode allowing power to

be switched off to the main processor when the chip is in the

Deep Sleep mode. The Cortex-M0 CPU provides a

Non-Maskable Interrupt (NMI) input, which is made available to

the user when it is not in use for system functions requested by

the user.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a 2-wire form of JTAG; the debug

configuration used for PSoC 4200-M has four break-point

(address) comparators and two watchpoint (data) comparators.

Flash

The PSoC 4200-M has a flash module with a flash accelerator,

tightly coupled to the CPU to improve average access times from

the flash block. The flash accelerator delivers 85% of

single-cycle SRAM access performance on average. Part of the

flash module can be used to emulate EEPROM operation if

required.

SRAM

SRAM memory is retained during Hibernate.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

DMA

A DMA engine, with eight channels, is provided that can do 32-bit

transfers and has chainable ping-pong descriptors.

System Resources

Power System

The power system is described in detail in the section Power on

page 14. It provides assurance that voltage levels are as

required for each respective mode and either delay mode entry

(on power-on reset (POR), for example) until voltage levels are

as required for proper function or generate resets (brown-out

detect (BOD)) or interrupts (low voltage detect (LVD)). The

PSoC 4200M operates with a single external supply over the

range of 1.71 to 5.5 V and has five different power modes, transi-

tions between which are managed by the power system. The

PSoC 4200M provides Sleep, Deep Sleep, Hibernate, and Stop

low-power modes.

Clock System

The PSoC 4200-M clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that no meta-stable conditions occur.

The clock system for the PSoC 4200-M consists of a Watch

Crystal Oscillator (WCO) running at 32 kHz, the IMO (3 to

48 MHz) and the ILO (32-kHz nominal) internal oscillators, and

provision for an external clock.

Figure 2. PSoC 4200M MCU Clocking Architecture

The clk_hf signal can be divided down to generate synchronous

clocks for the UDBs, and the analog and digital peripherals.

There are a total of 16 clock dividers for the PSoC 4200-M, each

with 16-bit divide capability; this allows 12 to be used for the

fixed-function blocks and four for the UDBs. The analog clock

leads the digital clocks to allow analog events to occur before

digital clock-related noise is generated. The 16-bit capability

allows a lot of flexibility in generating fine-grained frequency

values and is fully supported in PSoC Creator.

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4200M. It is trimmed during testing to achieve the

specified accuracy. Trim values are stored in nonvolatile

memory. Trimming can also be done on the fly to allow in-field

calibration. The IMO default frequency is 24 MHz and it can be

adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance

with Cypress-provided calibration settings is ±2%.

ILO Clock Source

The ILO is a very low power oscillator, nominally 32 kHz, which

is primarily used to generate clocks for peripheral operation in

Deep Sleep mode. ILO-driven counters can be calibrated to the

IMO to improve accuracy. Cypress provides a software

component, which does the calibration.

Crystal Oscillator

The PSoC 4200M clock subsystem also includes a

low-frequency crystal oscillator (32-kHz WCO) that is available

during the Deep Sleep mode and can be used for Real-Time

Clock (RTC) and Watchdog Timer applications.

dsi _out[3:0]

IMO

ILO

clk_ext

clk_hf

clk_lf

dsi_in[3]

dsi_in[2]

dsi_in[0]

dsi_in[1]

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 6 of 42

Watchdog Timer

A watchdog timer is implemented in the clock block running from

the low-frequency clock; this allows watchdog operation during

Deep Sleep and generates a watchdog reset or an interrupt if not

serviced before the timeout occurs. The watchdog reset is

recorded in the Reset Cause register.

Reset

The PSoC 4200M can be reset from a variety of sources

including a software reset. Reset events are asynchronous and

guarantee reversion to a known state. The reset cause is

recorded in a register, which is sticky through reset and allows

software to determine the cause of the reset. An XRES pin is

reserved for external reset to avoid complications with configu-

ration and multiple pin functions during power-on or reconfigu-

ration.

V oltage Reference

The PSoC 4200M reference system generates all internally

required references. A 1% voltage reference spec is provided for

the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and

better absolute accuracy, it is possible to add an external bypass

capacitor to the internal reference using a GPIO pin or to use an

external reference for the SAR.

Analog Blocks

12-bit SAR ADC

The 12-bit 1 MSample/second SAR ADC can operate at a

maximum clock rate of 18 MHz and requires a minimum of 18

clocks at that frequency to do a 12-bit conversion.

The block functionality is augmented for the user by adding a

reference buffer to it (trimmable to ±1%) and by providing the

choice of three internal voltage references: VDD, VDD/2, and

VREF (nominally 1.024 V) as well as an external reference

through a GPIO pin. The Sample-and-Hold (S/H) aperture is

programmable allowing the gain bandwidth requirements of the

amplifier driving the SAR inputs, which determine its settling

time, to be relaxed if required. The system performance will be

65 dB for true 12-bit precision if appropriate references are used

and system noise levels permit. To improve performance in noisy

conditions, it is possible to provide an external bypass (through

a fixed pin location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input

sequencer (expandable to 16 inputs). The sequencer cycles

through selected channels autonomously (sequencer scan) and

does so with zero switching overhead (that is, the aggregate

sampling bandwidth is equal to 1 Msps, whether it is for a single

channel or distributed over several channels). The sequencer

switching is effected through a state machine or through

firmware-driven switching. A feature provided by the sequencer

is buffering of each channel to reduce CPU interrupt service

requirements. To accommodate signals with varying source

impedance and frequency, it is possible to have different sample

times programmable for each channel. In addition, the signal

range specification through a pair of range registers (low and

high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

The SAR is able to digitize the output of the on-board temper-

ature sensor for calibration and other temperature-dependent

functions. The SAR is not available in Deep Sleep and Hibernate

modes as it requires a high-speed clock (up to 18 MHz). The

SAR operating range is 1.71 to 5.5 V.

Figure 3. SAR ADC System Diag ram

SARMUX

Port 2 (8 inputs)

vplusvminus

Data and

Status Flags

Reference

Selection

External

Reference

and

Bypass

(optional)

POS

NEG

SARSEQ

SARADC

Inputs from other Ports

VDD/2 VDDD VREF

AHB System Bus and Programmable Logic

Interconnect

Sequencing

and Control

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 7 of 42

Analog Multiplex Bus

The PSoC 4200M has two concentric analog buses (Analog Mux

Bus A and Analog Mux Bus B) that circumnavigate the periphery

of the chip. These buses can transport analog signals from any

pin to various analog blocks (including the opamps) and to the

CapSense blocks allowing, for instance, the ADC to monitor any

pin on the chip. These buses are independent and can also be

split into three independent sections. This allows one section to

be used for CapSense purposes, one for general analog signal

processing, and the third for general-purpose digital peripherals

and GPIO.

Four Opamps

The PSoC 4200M has four opamps with comparator modes,

which allow most common analog functions to be performed

on-chip eliminating external components; PGAs, voltage buffers,

filters, trans-impedance amplifiers, and other functions can be

realized with external passives saving power, cost, and space.

The on-chip opamps are designed with enough bandwidth to

drive the Sample-and-Hold circuit of the ADC without requiring

external buffering. The opamps can operate in the Deep Sleep

mode at very low power levels. The following diagram shows one

of two identical opamp pairs of the opamp subsystem.

Figure 4. Identical Opamp Pairs in Opamp Subsystem

The ovals in Figure 4 represent analog switches, which may be

controlled via user firmware, the SAR sequencer, or user-defined

programmable logic. The opamps (OA0 and OA1) are configu-

rable via these switches to perform all standard opamp functions

with appropriate feedback components.

The opamps (OA0 and OA1) are programmable and reconfigu-

rable to provide standard opamp functionality via switchable

feedback components, unity gain functionality for driving pins

directly, or for internal use (such as buffering SAR ADC inputs as

indicated in the diagram), or as true comparators.

The opamp inputs provide highly flexible connectivity and can

connect directly to dedicated pins or, via the analog mux buses,

to any pin on the chip. Analog switch connectivity is controllable

by user firmware as well as user-defined programmable digital

state machines (implemented via UDBs).

The opamps operate in Deep Sleep mode at very low currents

allowing analog circuits to remain operational during Deep

Sleep.

Temperature Sensor

The PSoC 4200M has one on-chip temperature sensor. This

consists of a diode, which is biased by a current source that can

be disabled to save power. The temperature sensor is connected

to the ADC, which digitizes the reading and produces a temper-

ature value using Cypress-supplied software that includes

calibration and linearization.

Low-power Comparators

The PSoC 4200M has a pair of low-power comparators, which

can also operate in the Deep Sleep and Hibernate modes. This

allows the analog system blocks to be disabled while retaining

the ability to monitor external voltage levels during low-power

modes. The comparator outputs are normally synchronized to

avoid meta-stability unless operating in an asynchronous power

mode (Hibernate) where the system wake-up circuit is activated

by a comparator switch event.

Programmable Digital

Universal Digital Blocks (UDBs) and Port Interfaces

The PSoC 4200M has four UDBs; the UDB array also provides

a switched Digital System Interconnect (DSI) fabric that allows

signals from peripherals and ports to be routed to and through

the UDBs for communication and control. The UDB array is

shown in the following figure.

Figure 5. UDB Array

Analog Mux Bus B

Analog Mux Bus A

Internal

Out0

To SAR ADC

OA0 10x

Internal

Out1

OA1

10x

Programmable Digital Subsystem

UDBIF

UDB UDB

DSI DSI

BUS IF IRQ IF CLK IF Port IF

Port IF

Hi gh -Speed I/O Matrix

CPUSSAHB Bridge Dig CLKS

4 to 8

8 to 32

Scalable array of

UDBs (max=16)

Routing

Channels

Ot h e r Di g i ta l

Signal s in Chip

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 8 of 42

UDBs can be clocked from a clock divider block, from a port

interface (required for peripherals such as SPI), and from the DSI

network directly or after synchronization.

A port interface is defined, which acts as a register that can be

clocked with the same source as the PLDs inside the UDB array.

This allows faster operation because the inputs and outputs can

be registered at the port interface close to the I/O pins and at the

edge of the array. The port interface registers can be clocked by

one of the I/Os from the same port. This allows interfaces such

as SPI to operate at higher clock speeds by eliminating the delay

for the port input to be routed over DSI and used to register other

inputs. The port interface is shown in Figure 6.

The UDBs can generate interrupts (one UDB at a time) to the

interrupt controller. The UDBs can connect to any pin on Ports 0,

1, 2, and 3 (each port interconnect requires one UDB) through

the DSI.

Figure 6. Port Interface

Fixed Function Digital

Timer/Counter/PWM (TCPWM) Block

The TCPWM block uses a16-bit counter with user-program-

mable period length. There is a Capture register to record the

count value at the time of an event (which may be an I/O event),

a period register which is used to either stop or auto-reload the

counter when its count is equal to the period register, and

compare registers to generate compare value signals, which are

used as PWM duty cycle outputs. The block also provides true

and complementary outputs with programmable offset between

them to allow use as deadband programmable complementary

PWM outputs. It also has a Kill input to force outputs to a prede-

termined state; for example, this is used in motor drive systems

when an overcurrent state is indicated and the PWMs driving the

FETs need to be shut off immediately with no time for software

intervention. The PSoC 4200M has eight TCPWM blocks.

Serial Communication Blocks (SCB)

The PSoC 4200M has four SCBs, which can each implement an

I2C, UART, or SPI interface.

I2C Mode: The hardware I2C block implements a full

multi-master and slave interface (it is capable of multimaster

arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

supports EzI2C that creates a mailbox address range in the

memory of the PSoC 4200M and effectively reduces I2C commu-

nication to reading from and writing to an array in memory. In

addition, the block supports an 8-deep FIFO for receive and

transmit which, by increasing the time given for the CPU to read

data, greatly reduces the need for clock stretching caused by the

CPU not having read data on time. The FIFO mode is available

in all channels and is very useful in the absence of DMA.

The I2C peripheral is compatible with the I2C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I2C-bus specification and user manual (UM10204). The I2C bus

I/O is implemented with GPIO in open-drain modes.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP

(essentially adds a start pulse used to synchronize SPI Codecs),

and National Microwire (half-duplex form of SPI). The SPI block

can use the FIFO and also supports an EzSPI mode in which

data interchange is reduced to reading and writing an array in

memory.

CAN Blocks

There are two independent CAN 2.0B blocks, which are certified

CAN conformant.

Clock Selector

Block from

UDB

Digital

GlobalClocks

3 DSI Signals ,

1 I/O Signal

Reset Selector

Block from

UDB

Input Registers Output Registers

To DSI

From DSI

8 8

Enables

From DSI

7 6 . . . 0 7 6 . . . 0 3 2 1 0

High Speed I/O Matrix

To Clock

Tree

[0]

[1]

[1 ]

[1]

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 9 of 42

GPIO

The PSoC 4200M has 55 GPIOs in the 68-pin QFN package.

The GPIO block implements the following:

■Eight drive strength modes including strong push-pull, resistive

pull-up and pull-down, weak (resistive) pull-up and pull-down,

open drain and open source, input only, and disabled

■Input threshold select (CMOS or LVTTL)

■Individual control of input and output disables

■Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode and Hibernate modes)

■Selectable slew rates for dV/dt related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width. During power-on and reset, the blocks are forced

to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a

high-speed I/O matrix is used to multiplex between various

signals that may connect to an I/O pin. Pin locations for

fixed-function peripherals are also fixed to reduce internal multi-

plexing complexity (these signals do not go through the DSI

network). DSI signals are not affected by this and any pin on

Ports 0, 1, 2, and 3 may be routed to any UDB through the DSI

network. Only pins on Ports 0, 1, 2, and 3 may be routed through

DSI signals.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it (8 for PSoC 4200M).

The Pins of Port 6 (up to 6 depending on the package) are

overvoltage tolerant (VIN can exceed VDD). The overvoltage cells

will not sink more than 10 µA when their inputs exceed VDDIO in

compliance with I2C specifications.

Special Function Peripherals

LCD Segment Drive

The PSoC 4200M has an LCD controller, which can drive up to

four commons and up to 51 segments. Any pin can be either a

common or a segment pin. It uses full digital methods to drive the

LCD segments requiring no generation of internal LCD voltages.

The two methods used are referred to as digital correlation and

PWM.

Digital correlation pertains to modulating the frequency and

levels of the common and segment signals to generate the

highest RMS voltage across a segment to light it up or to keep

the RMS signal zero. This method is good for STN displays but

may result in reduced contrast with TN (cheaper) displays.

PWM pertains to driving the panel with PWM signals to effec-

tively use the capacitance of the panel to provide the integration

of the modulated pulse-width to generate the desired LCD

voltage. This method results in higher power consumption but

can result in better results when driving TN displays. LCD

operation is supported during Deep Sleep refreshing a small

display buffer (4 bits; 1 32-bit register per port).

CapSense

CapSense is supported on all pins in the PSoC 4200M through

a CapSense Sigma-Delta (CSD) block that can be connected to

any pin through an analog mux bus that any GPIO pin can be

connected to via an Analog switch. CapSense functionality can

thus be provided on any pin or group of pins in a system under

software control. A component is provided for the CapSense

block, which provides automatic hardware tuning (Cypress

SmartSense™), to make it easy for the user.

Shield voltage can be driven on another Mux Bus to provide

water tolerance capability. Water tolerance is provided by driving

the shield electrode in phase with the sense electrode to keep

the shield capacitance from attenuating the sensed input.

Each CSD block has two IDACs which can be used for general

purposes if CapSense is not being used.(both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available). The PSoC 4200M has two

CSD blocks which can be used independently; one for

CapSense and one providing two IDACs.

The two CapSense blocks are referred to as CSD0 and CSD1.

Capacitance sensing inputs on Ports 0, 1, 2, 3, 4, 6, and 7 are

sensed by CSD0. Capacitance sensing inputs on Port 5 are

sensed by CSD1.

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 10 of 42

Pinouts

The following is the pin list for the PSoC 4200M. This shows the power supply and port pins (for example, P0.0 is Pin 0 of Port 0).

68-QFN 64-TQFP 48-TQFP 44-TQFP

Pin Name Pin Name Pin Name Pin Name

42 P0.0 39 P0.0 28 P0.0 24 P0.0

43 P0.1 40 P0.1 29 P0.1 25 P0.1

44 P0.2 41 P0.2 30 P0.2 26 P0.2

45 P0.3 42 P0.3 31 P0.3 27 P0.3

46 P0.4 43 P0.4 32 P0.4 28 P0.4

47 P0.5 44 P0.5 33 P0.5 29 P0.5

48 P0.6 45 P0.6 34 P0.6 30 P0.6

49 P0.7 46 P0.7 35 P0.7 31 P0.7

50 XRES 47 XRES 36 XRES 32 XRES

51 VCCD 48 VCCD 37 VCCD 33 VCCD

52 VSSD 49 VSSD 38 VSSD DN VSSD

53 VDDD 50 VDDD 39 VDDD 34 VDDD

40 VDDA 35 VDDA

54 P5.0 51 P5.0

55 P5.1 52 P5.1

56 P5.2 53 P5.2

57 P5.3 54 P5.3

58 P5.4

59 P5.5 55 P5.5

60 VDDA 56 VDDA 40 VDDA 35 VDDA

61 VSSA 57 VSSA 41 VSSA 36 VSSA

62 P1.0 58 P1.0 42 P1.0 37 P1.0

63 P1.1 59 P1.1 43 P1.1 38 P1.1

64 P1.2 60 P1.2 44 P1.2 39 P1.2

65 P1.3 61 P1.3 45 P1.3 40 P1.3

66 P1.4 62 P1.4 46 P1.4 41 P1.4

67 P1.5 63 P1.5 47 P1.5 42 P1.5

68 P1.6 64 P1.6 48 P1.6 43 P1.6

1P1.7/VREF 1P1.7/VREF 1P1.7/VREF 44 P1.7/VREF

1VSSD

2P2.0 2P2.0 2P2.0 2P2.0

3P2.1 3P2.1 3P2.1 3P2.1

4P2.2 4P2.2 4P2.2 4P2.2

5P2.3 5P2.3 5P2.3 5P2.3

6P2.4 6P2.4 6P2.4 6P2.4

7P2.5 7P2.5 7P2.5 7P2.5

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 11 of 42

The pins of Port 6 are overvoltage-tolerant. Pins 36, 37, and 38 are No-Connects on the 68-pin QFN. Pins 34, 35, and 36 are

No-Connects on the 64-pin TQFP. Pins 11 and 15 are No-connects in the 48-pin TQFP. All VSS pins must be tied together.

The output drivers of I/O Ports P0 and P7 are connected to VDDD. Output drivers of I/O Ports 1, 2, and 5 are connected to VDDA.

Output drivers of I/O Ports 3, 4, and 6 are connected to VDDIO.

8P2.6 8P2.6 8P2.6 8P2.6

9P2.7 9P2.7 9P2.7 9P2.7

10 VSSA 10 VSSA 10 VSSD 10 VSSD

11 VDDA 11 VDDA

12 P6.0 12 P6.0

13 P6.1 13 P6.1

14 P6.2 14 P6.2

15 P6.3

16 P6.4 15 P6.4

17 P6.5 16 P6.5

18 VSSIO 17 VSSIO 10 VSSD 10 VSSD

19 P3.0 18 P3.0 12 P3.0 11 P3.0

20 P3.1 19 P3.1 13 P3.1 12 P3.1

21 P3.2 20 P3.2 14 P3.2 13 P3.2

22 P3.3 21 P3.3 16 P3.3 14 P3.3

23 P3.4 22 P3.4 17 P3.4 15 P3.4

24 P3.5 23 P3.5 18 P3.5 16 P3.5

25 P3.6 24 P3.6 19 P3.6 17 P3.6

26 P3.7 25 P3.7 20 P3.7 18 P3.7

27 VDDIO 26 VDDIO 21 VDDIO 19 VDDD

28 P4.0 27 P4.0 22 P4.0 20 P4.0

29 P4.1 28 P4.1 23 P4.1 21 P4.1

30 P4.2 29 P4.2 24 P4.2 22 P4.2

31 P4.3 30 P4.3 25 P4.3 23 P4.3

32 P4.4 31 P4.4

33 P4.5 32 P4.5

34 P4.6 33 P4.6

35 P4.7

39 P7.0 37 P7.0 26 P7.0

40 P7.1 38 P7.1 27 P7.1

41 P7.2

68-QFN 64-TQFP 48-TQFP 44-TQFP

Pin Name Pin Name Pin Name Pin Name

Document Number: 001-93963 Rev. *G Page 12 of 42

PSoC® 4: PSoC 4200M Family

Datasheet

Each of the pins shown in the previous table can have multiple programmable functions as shown in the following table. Column headings refer to Analog and Alternate pin

functions.:

Port/Pin Analog Alt. Function 1 Alt. Function 2 Alt. Function 3 Alt. Function 4 Alt. Function 5

P0.0 lpcomp.in_p[0] can[1].can_rx:0 scb[0].spi_select1:0

P0.1 lpcomp.in_n[0] can[1].can_tx:0 scb[0].spi_select2:0

P0.2 lpcomp.in_p[1] scb[0].spi_select3:0

P0.3 lpcomp.in_n[1]

P0.4 wco_in scb[1].uart_rx:0 scb[1].i2c_scl:0 scb[1].spi_mosi:1

P0.5 wco_out scb[1].uart_tx:0 scb[1].i2c_sda:0 scb[1].spi_miso:1

P0.6 ext_clk:0 scb[1].uart_cts:0 scb[1].spi_clk:1

P0.7 scb[1].uart_rts:0 can[1].can_tx_enb_n:0 wakeup scb[1].spi_select0:1

P5.0 ctb1.oa0.inp tcpwm.line[4]:2 scb[2].uart_rx:0 scb[2].i2c_scl:0 scb[2].spi_mosi:0

P5.1 ctb1.oa0.inm tcpwm.line_compl[4]:2 scb[2].uart_tx:0 scb[2].i2c_sda:0 scb[2].spi_miso:0

P5.2 ctb1.oa0.out tcpwm.line[5]:2 scb[2].uart_cts:0 lpcomp.comp[0]:1 scb[2].spi_clk:0

P5.3 ctb1.oa1.out tcpwm.line_compl[5]:2 scb[2].uart_rts:0 lpcomp.comp[1]:1 scb[2].spi_select0:0

P5.4 ctb1.oa1.inm tcpwm.line[6]:2 scb[2].spi_select1:0

P5.5 ctb1.oa1.inp tcpwm.line_compl[6]:2 scb[2].spi_select2:0

P5.6 ctb1.oa0.inp_alt tcpwm.line[7]:0 scb[2].spi_select3:0

P5.7 ctb1.oa1.inp_alt tcpwm.line_compl[7]:0

P1.0 ctb0.oa0.inp tcpwm.line[2]:1 scb[0].uart_rx:1 scb[0].i2c_scl:0 scb[0].spi_mosi:1

P1.1 ctb0.oa0.inm tcpwm.line_compl[2]:1 scb[0].uart_tx:1 scb[0].i2c_sda:0 scb[0].spi_miso:1

P1.2 ctb0.oa0.out tcpwm.line[3]:1 scb[0].uart_cts:1 scb[0].spi_clk:1

P1.3 ctb0.oa1.out tcpwm.line_compl[3]:1 scb[0].uart_rts:1 scb[0].spi_select0:1

P1.4 ctb0.oa1.inm tcpwm.line[6]:1 scb[0].spi_select1:1

P1.5 ctb0.oa1.inp tcpwm.line_compl[6]:1 scb[0].spi_select2:1

P1.6 ctb0.oa0.inp_alt tcpwm.line[7]:1 scb[0].spi_select3:1

P1.7 ctb0.oa1.inp_alt tcpwm.line_compl[7]:1

P2.0 sarmux.0 tcpwm.line[4]:1 scb[1].i2c_scl:1 scb[1].spi_mosi:2

P2.1 sarmux.1 tcpwm.line_compl[4]:1 scb[1].i2c_sda:1 scb[1].spi_miso:2

P2.2 sarmux.2 tcpwm.line[5]:1 scb[1].spi_clk:2

P2.3 sarmux.3 tcpwm.line_compl[5]:1 scb[1].spi_select0:2

P2.4 sarmux.4 tcpwm.line[0]:1 scb[1].spi_select1:1

P2.5 sarmux.5 tcpwm.line_compl[0]:1 scb[1].spi_select2:1

P2.6 sarmux.6 tcpwm.line[1]:1 scb[1].spi_select3:1

Document Number: 001-93963 Rev. *G Page 13 of 42

PSoC® 4: PSoC 4200M Family

Datasheet

Descriptions of the power pin functions are as follows:

VDDD: Power supply for both analog and digital sections (where there is no VDDA

pin).

VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise.

VDDIO: I/O pin power domain.

VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise

VSS: Ground pin.

VCCD: Regulated Digital supply (1.8 V ±5%).

Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense

and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO

pins that can be driven by firmware or DSI signals.

P2.7 sarmux.7 tcpwm.line_compl[1]:1 scb[3].spi_select0:1

P6.0 tcpwm.line[4]:0 scb[3].uart_rx:0 can[0].can_tx_enb_n:0 scb[3].i2c_scl:0 scb[3].spi_mosi:0

P6.1 tcpwm.line_compl[4]:0 scb[3].uart_tx:0 can[0].can_rx:0 scb[3].i2c_sda:0 scb[3].spi_miso:0

P6.2 tcpwm.line[5]:0 scb[3].uart_cts:0 can[0].can_tx:0 scb[3].spi_clk:0

P6.3 tcpwm.line_compl[5]:0 scb[3].uart_rts:0 scb[3].spi_select0:0

P6.4 tcpwm.line[6]:0 scb[3].spi_select1:0

P6.5 tcpwm.line_compl[6]:0 scb[3].spi_select2:0

P3.0 tcpwm.line[0]:0 scb[1].uart_rx:1 scb[1].i2c_scl:2 scb[1].spi_mosi:0

P3.1 tcpwm.line_compl[0]:0 scb[1].uart_tx:1 scb[1].i2c_sda:2 scb[1].spi_miso:0

P3.2 tcpwm.line[1]:0 scb[1].uart_cts:1 swd_data scb[1].spi_clk:0

P3.3 tcpwm.line_compl[1]:0 scb[1].uart_rts:1 swd_clk scb[1].spi_select0:0

P3.4 tcpwm.line[2]:0 scb[1].spi_select1:0

P3.5 tcpwm.line_compl[2]:0 scb[1].spi_select2:0

P3.6 tcpwm.line[3]:0 scb[1].spi_select3:0

P3.7 tcpwm.line_compl[3]:0

P4.0 scb[0].uart_rx:0 can[0].can_rx:1 scb[0].i2c_scl:1 scb[0].spi_mosi:0

P4.1 scb[0].uart_tx:0 can[0].can_tx:1 scb[0].i2c_sda:1 scb[0].spi_miso:0

P4.2 csd[0].c_mod scb[0].uart_cts:0 can[0].can_tx_enb_n:1 lpcomp.comp[0]:0 scb[0].spi_clk:0

P4.3 csd[0].c_sh_tank scb[0].uart_rts:0 lpcomp.comp[1]:0 scb[0].spi_select0:0

P4.4 can[1].can_tx_enb_n:1 scb[0].spi_select1:2

P4.5 can[1].can_rx:1 scb[0].spi_select2:2

P4.6 can[1].can_tx:1 scb[0].spi_select3:2

P4.7

P7.0 tcpwm.line[0]:2 scb[3].uart_rx:1 scb[3].i2c_scl:1 scb[3].spi_mosi:1

P7.1 tcpwm.line_compl[0]:2 scb[3].uart_tx:1 scb[3].i2c_sda:1 scb[3].spi_miso:1

P7.2 tcpwm.line[1]:2 scb[3].uart_cts:1 scb[3].spi_clk:1

Port/Pin Analog Alt. Function 1 Alt. Function 2 Alt. Function 3 Alt. Function 4 Alt. Function 5

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 14 of 42

Power

The supply voltage range is 1.71 to 5.5 V with all functions and

circuits operating over that range.

The PSoC 4200M family allows two distinct modes of power

supply operation: Unregulated External Supply and Regulated

External Supply modes.

Unregulated External Supply

In this mode, the PSoC 4200M is powered by an External Power

Supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation, for

instance, the chip can be powered from a battery system that

starts at 3.5V and works down to 1.8 V. In this mode, the internal

regulator of the PSoC 4200M supplies the internal logic and the

VCCD output of the PSoC 4200M must be bypassed to ground

via an external Capacitor (in the range of 1 to 1.6 µF; X5R

ceramic or better).

The grounds, VSSA and VSS, must be shorted together. Bypass

capacitors must be used from VDDD and VDDA to ground,

typical practice for systems in this frequency range is to use a

capacitor in the 1 µF range in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the Bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

Regulated External Supply

In this mode, the PSoC 4200M is powered by an external power

supply that must be within the range of 1.71 to 1.89 V (1.8 ±5%);

note that this range needs to include power supply ripple. VCCD

and VDDD pins are shorted together and bypassed. The internal

regulator is disabled in firmware.

Power Supply Bypass Capacitors

VDDD–VSS and

VDDIO-VSS

0.1 µF ceramic at each pin plus bulk

capacitor 1 to 10 µF.

VDDA–VSSA 0.1 µF ceramic at pin. Additional 1 µF to

10 µF bulk capacitor

VCCD–VSS 1 µF ceramic capacitor at the VCCD pin

VREF–VSSA

(optional)

The internal bandgap may be bypassed

with a 1 µF to 10 µF capacitor for better

ADC performance.

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 15 of 42

Development Support

The PSoC 4200M family has a rich set of documentation, devel-

opment tools, and online resources to assist you during your

development process. Visit www.cypress.com/go/psoc4 to find

out more.

Documentation

A suite of documentation supports the PSoC 4200M family to

ensure that you can find answers to your questions quickly. This

section contains a list of some of the key documents.

Software User Guide: A step-by-step guide for using

PSoC Creator. The software user guide shows you how the

PSoC Creator build process works in detail, how to use source

control with PSoC Creator, and much more.

Component Datasheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component data sheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Application Notes : PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

Technical Reference Manual: The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC

device, including a complete description of all PSoC registers.

Online

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

Tools

With industry standard cores, programming, and debugging

interfaces, the PSoC 4200M family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 16 of 42

Electrical Specifications

Absolute Maximum Ratings

Device Level Specifications

All specifications are valid for -40 °C  TA  105 °C and TJ  125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Note

1. Usage above the absolute maximum conditions listed in Tab le 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Table 1. Absolute Maximum Ratings[1]

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

SID1 VDD_ABS Analog or digital supply relative to VSS

(VSSD = VSSA)

–0.5 – 6 V Absolute maximum

SID2 VCCD_ABS Direct digital core voltage input relative

to VSSD

–0.5 – 1.95 V Absolute maximum

SID3 VGPIO_ABS GPIO voltage; VDDD or VDDA –0.5 – VDD+0.5 V Absolute maximum

SID4 IGPIO_ABS Current per GPIO –25 – 25 mA Absolute maximum

SID5 IG-PIO_injection GPIO injection current per pin –0.5 – 0.5 mA Absolute maximum

BID44 ESD_HBM Electrostatic discharge human body

model

2200 – – V

BID45 ESD_CDM Electrostatic discharge charged device

model

500 – – V

BID46 LU Pin current for latch-up –140 – 140 mA

Table 2. DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details / Conditio ns

SID53 VDD Power Supply Input Voltage (VDDA =

VDDD = VDD)

1.8 – 5.5 V With regulator

enabled

SID255 VDDD Power Supply Input Voltage unregulated 1.71 1.8 1.89 V Internally unregulated

Supply

SID54 VCCD Output voltage (for core logic) – 1.8 – V

SID55 CEFC External Regulator voltage bypass 1 1.3 1.6 µF X5R ceramic or better

SID56 CEXC Power supply decoupling capacitor – 1 – µF X5R ceramic or better

Active Mode, VDD = 1.71 V to 5.5 V, –40 °C to +105 °C

SID6 IDD1 Execute from Flash; CPU at 6 MHz – 2.2 2.8 mA

SID7 IDD2 Execute from Flash; CPU at 12 MHz – 3.7 4.2 mA

SID8 IDD3 Execute from Flash; CPU at 24 MHz – 6.7 7.2 mA

SID9 IDD4 Execute from Flash; CPU at 48 MHz – 13 13.8 mA

Sleep Mode, –40 °C to +105 °C

SID21 IDD16 I2C wakeup, WDT, and Comparators on.

Regulator Off.

– 1.75 2.1 mA VDD = 1.71 to 1.89,

6MHz

SID22 IDD17 I2C wakeup, WDT, and Comparators on. – 1.7 2.1 mA VDD = 1.8 to 5.5,

6MHz

SID23 IDD18 I2C wakeup, WDT, and Comparators on.

Regulator Off.

– 2.35 2.8 mA VDD = 1.71 to 1.89,

12 MHz

SID24 IDD19 I2C wakeup, WDT, and Comparators on. – 2.25 2.8 mA VDD = 1.8 to 5.5,

12 MHz

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 17 of 42

Deep Sleep Mode, –40 °C to + 60 °C

SID30 IDD25 I2C wakeup and WDT on. Regulator Off. – 1.55 20 µA VDD = 1.71 to 1.89

SID31 IDD26 I2C wakeup and WDT on. – 1.35 15 µA VDD = 1.8 to 3.6

SID32 IDD27 I2C wakeup and WDT on. – 1.5 15 µA VDD = 3.6 to 5.5

Deep Sleep Mode, +85 °C

SID33 IDD28 I2C wakeup and WDT on. Regulator Off. – – 60 µA VDD = 1.71 to 1.89

SID34 IDD29 I2C wakeup and WDT on. – – 45 µA VDD = 1.8 to 3.6

SID35 IDD30 I2C wakeup and WDT on. – – 30 µA VDD = 3.6 to 5.5

Deep Sleep Mode, +105 °C

SID33Q IDD28Q I2C wakeup and WDT on. Regulator Off. – – 135 µA VDD = 1.71 to 1.89

SID34Q IDD29Q I2C wakeup and WDT on. – – 180 µA VDD = 1.8 to 3.6

SID35Q IDD30Q I2C wakeup and WDT on. – – 140 µA VDD = 3.6 to 5.5

Hibernate Mode, –40 °C to + 60 °C

SID39 IDD34 Regulator Off. – 150 3000 nA VDD = 1.71 to 1.89

SID40 IDD35 – 150 1000 nA VDD = 1.8 to 3.6

SID41 IDD36 – 150 1100 nA VDD = 3.6 to 5.5

Hibernate Mode, +85 °C

SID42 IDD37 Regulator Off. – – 4500 nA VDD = 1.71 to 1.89

SID43 IDD38 – – 3500 nA VDD = 1.8 to 3.6

SID44 IDD39 – – 3500 nA VDD = 3.6 to 5.5

Hibernate Mode, +105 °C

SID42Q IDD37Q Regulator Off. – – 19.4 µA VDD = 1.71 to 1.89

SID43Q IDD38Q ––17µAV

DD = 1.8 to 3.6

SID44Q IDD39Q ––16µAV

DD = 3.6 to 5.5

Stop Mode

SID304 IDD43A Stop Mode current; VDD = 3.6 V – 35 85 nA T = –40 °C to +60 °C

SID304A IDD43B Stop Mode current; VDD = 3.6 V – – 1450 nA T = +85 °C

Stop Mode, +105 °C

SID304Q IDD43AQ Stop Mode current; VDD = 3.6 V – – 5645 nA

XRES current

SID307 IDD_XR Supply current while XRES asserted – 2 5 mA

Table 2. DC Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details / Conditio ns

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 18 of 42

GPIO

Table 3. AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID48 FCPU CPU frequency DC – 48 MHz 1.71 VDD 5.5

SID49 TSLEEP Wakeup from sleep mode – 0 – µs Guaranteed by

characterization

SID50 TDEEPSLEEP Wakeup from Deep Sleep mode – – 25 µs 24 MHz IMO.

Guaranteed by

characterization

SID51 THIBERNATE Wakeup from Hibernate mode – – 0.7 ms Guaranteed by

characterization

SID51A TSTOP Wakeup from Stop mode – – 2 ms Guaranteed by

characterization

SID52 TRESETWIDTH External reset pulse width 1 – – µs Guaranteed by

characterization

Note

2. VIH must not exceed VDDD + 0.2 V.

Table 4. GPIO DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

SID57 VIH[2] Input voltage high threshold 0.7 ×

VDDD

– – V CMOS Input

SID57A IIHS Input current when Pad > VDDIO for

OVT inputs

––10µAPer I

2C Spec

SID58 VIL Input voltage low threshold – – 0.3 ×

VDDD

V CMOS Input

SID241 VIH[2] LVTTL input, VDDD < 2.7 V 0.7×

VDDD

––V

SID242 VIL LVTTL input, VDDD < 2.7 V – – 0.3 ×

VDDD

SID243 VIH[2] LVTTL input, VDDD  2.7 V 2.0 – – V

SID244 VIL LVTTL input, VDDD  2.7 V – – 0.8 V

SID59 VOH Output voltage high level VDDD

–0.6

––VI

OH = 4 mA at 3-V

VDDD

SID60 VOH Output voltage high level VDDD

–0.5

––VI

OH = 1 mA at 1.8-V

VDDD

SID61 VOL Output voltage low level – – 0.6 V IOL = 4 mA at 1.8-V

VDDD

SID62 VOL Output voltage low level – – 0.6 V IOL = 8 mA at 3-V

VDDD

SID62A VOL Output voltage low level – – 0.4 V IOL = 3 mA at 3-V

VDDD

SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 k

SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k

SID65 IIL Input leakage current (absolute

value)

–– 2nA25°C, V

DDD = 3.0 V.

Guaranteed by

Characterization

SID65A IIL_CTBM Input leakage current (absolute

value) for CTBM pins

– – 4 nA Guaranteed by

Characterization

SID66 CIN Input capacitance – – 7 pF

SID67 VHYSTTL Input hysteresis LVTTL 25 40 – mV VDDD  2.7 V

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 19 of 42

XRES

SID68 VHYSCMOS Input hysteresis CMOS 0.05 ×

VDDD

––mV

SID69 IDIODE Current through protection diode to

VDD/Vss

––100µA Guaranteed by

characterization

SID69A ITOT_GPIO Maximum Total Source or Sink Chip

Current

– – 200 mA Guaranteed by

characterization

Table 4. GPIO DC Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

Note

3. Simultaneous switching transitions on many fully-loaded GPIO pins may cause ground perturbations depending on several factors including PCB and decoupling

capacitor design. For applications that are very sensitive to ground perturbations, the slower GPIO slew rate setting may be used.

Table 5. GPIO AC Specifications

(Guaranteed by Characterization)[3]

Spec ID # Parameter Description Min Typ Max Units Details/Conditions

SID70 TRISEF Rise time in fast strong mode 2 – 12 ns 3.3 V VDDD,

Cload = 25 pF

SID71 TFALLF Fall time in fast strong mode 2 – 12 ns 3.3 V VDDD,

Cload = 25 pF

SID72 TRISES Rise time in slow strong mode 10 – 60 ns 3.3 V VDDD,

Cload = 25 pF

SID73 TFALLS Fall time in slow strong mode 10 – 60 ns 3.3 V VDDD,

Cload = 25 pF

SID74 FGPIOUT1 GPIO Fout;3.3 V  VDDD 5.5 V. Fast

strong mode.

– – 33 MHz 90/10%, 25-pF load,

60/40 duty cycle

SID75 FGPIOUT2 GPIO Fout;1.7 VVDDD3.3 V. Fast

strong mode.

– – 16.7 MHz 90/10%, 25-pF load,

60/40 duty cycle

SID76 FGPIOUT3 GPIO Fout;3.3 V VDDD 5.5 V.

Slow strong mode.

– – 7 MHz 90/10%, 25-pF load,

60/40 duty cycle

SID245 FGPIOUT4 GPIO Fout;1.7 V VDDD 3.3 V.

Slow strong mode.

– – 3.5 MHz 90/10%, 25-pF load,

60/40 duty cycle

SID246 FGPIOIN GPIO input operating frequency;

1.71 V VDDD 5.5 V

– – 48 MHz 90/10% VIO

Table 6. XRES DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID77 VIH Input voltage high threshold 0.7 ×

VDDD

– – V CMOS Input

SID78 VIL Input voltage low threshold – – 0.3 ×

VDDD

V CMOS Input

SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 k

SID80 CIN Input capacitance – 3 – pF

SID81 VHYSXRES Input voltage hysteresis – 100 – mV Guaranteed by

characterization

SID82 IDIODE Current through protection diode to

VDDD/VSS

– – 100 µA Guaranteed by

characterization

Table 7. XRES AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID83 TRESETWIDTH Reset pulse width 1 – – µs Guaranteed by

characterization

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 20 of 42

Analog Peripherals

Opamp

Table 8. Opamp Specifications

(Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

IDD Opamp block current. No load. – – – –

SID269 IDD_HI Power = high – 1100 1850 µA

SID270 IDD_MED Power = medium – 550 950 µA

SID271 IDD_LOW Power = low – 150 350 µA

GBW Load = 20 pF, 0.1 mA. VDDA = 2.7 V – – – –

SID272 GBW_HI Power = high 6 – – MHz

SID273 GBW_MED Power = medium 4 – – MHz

SID274 GBW_LO Power = low – 1 – MHz

IOUT_MAX VDDA  2.7 V, 500 mV from rail – – – –

SID275 IOUT_MAX_HI Power = high 10 – – mA

SID276 IOUT_MAX_MID Power = medium 10 – – mA

SID277 IOUT_MAX_LO Power = low – 5 – mA

IOUT VDDA = 1.71 V, 500 mV from rail – – – –

SID278 IOUT_MAX_HI Power = high 4 – – mA

SID279 IOUT_MAX_MID Power = medium 4 – – mA

SID280 IOUT_MAX_LO Power = low – 2 – mA

SID281 VIN Input voltage range –0.05 – VDDA

– 0.2

V Charge-pump on,

VDDA 2.7 V

SID282 VCM Input common mode voltage –0.05 – VDDA

– 0.2

V Charge-pump on,

VDDA 2.7 V

VOUT VDDA  2.7 V – – –

SID283 VOUT_1 Power = high, Iload=10 mA 0.5 – VDDA

– 0.5

SID284 VOUT_2 Power = high, Iload=1 mA 0.2 – VDDA

– 0.2

SID285 VOUT_3 Power = medium, Iload=1 mA 0.2 – VDDA

– 0.2

SID286 VOUT_4 Power = low, Iload=0.1mA 0.2 – VDDA

– 0.2

SID288 VOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High mode

SID288A VOS_TR Offset voltage, trimmed – ±1 – mV Medium mode

SID288B VOS_TR Offset voltage, trimmed – ±2 – mV Low mode

SID290 VOS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/°C High mode. TA 

85 °C.

SID290Q VOS_DR_TR Offset voltage drift, trimmed 15 ±3 15 µV/°C High mode. TA 

105 °C

SID290A VOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/°C Medium mode

SID290B VOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/°C Low mode

SID291 CMRR DC Common mode rejection ratio.

High-power mode. Common Model

voltage range from 0.5 V to VDDA - 0.5 V.

60 70 – dB VDDD = 3.6 V

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 21 of 42

SID292 PSRR At 1 kHz, 100-mV ripple 70 85 – dB VDDD = 3.6 V

Noise – – – –

SID293 VN1 Input referred, 1 Hz - 1 GHz, power =

high

–94–µVrms

SID294 VN2 Input referred, 1 kHz, power = high – 72 – nV/rtHz

SID295 VN3 Input referred, 10kHz, power = high – 28 – nV/rtHz

SID296 VN4 Input referred, 100kHz, power = high – 15 – nV/rtHz

SID297 Cload Stable up to maximum load. Perfor-

mance specs at 50 pF.

––125pF

SID298 Slew_rate Cload = 50 pF, Power = High, VDDA 

2.7 V

6––V/µs

SID299 T_op_wake From disable to enable, no external RC

dominating

–25–µs

SID299A OL_GAIN Open Loop Gain – 90 – dB

Comp_mode Comparator mode; 50 mV drive,

Trise = Tfall (approx.)

–––

SID300 TPD1 Response time; power = high – 150 – ns

SID301 TPD2 Response time; power = medium – 400 – ns

SID302 TPD3 Response time; power = low – 2000 – ns

SID303 Vhyst_op Hysteresis – 10 – mV

Deep Sleep Mode Mode 2 is lowest current range. Mode 1

has higher GBW.

Deep Sleep mode.

VDDA  2.7 V.

SID_DS_1 IDD_HI_M1 Mode 1, High current – 1400 – uA 25 °C

SID_DS_2 IDD_MED_M1 Mode 1, Medium current – 700 – uA 25 °C

SID_DS_3 IDD_LOW_M1 Mode 1, Low current – 200 – uA 25 °C

SID_DS_4 IDD_HI_M2 Mode 2, High current – 120 – uA 25 °C

SID_DS_5 IDD_MED_M2 Mode 2, Medium current – 60 – uA 25 °C

SID_DS_6 IDD_LOW_M2 Mode 2, Low current – 15 – uA 25 °C

SID_DS_7 GBW_HI_M1 Mode 1, High current – 4 – MHz 25 °C

SID_DS_8 GBW_MED_M1 Mode 1, Medium current – 2 – MHz 25 °C

SID_DS_9 GBW_LOW_M1 Mode 1, Low current – 0.5 – MHz 25 °C

SID_DS_10 GBW_HI_M2 Mode 2, High current – 0.5 – MHz 20-pF load, no DC

load 0.2 V to

VDDA-1.5 V

SID_DS_11 GBW_MED_M2 Mode 2, Medium current – 0.2 – MHz 20-pF load, no DC

load 0.2 V to

VDDA-1.5 V

SID_DS_12 GBW_LOW_M2 Mode 2, Low current – 0.1 – MHz 20-pF load, no DC

load 0.2 V to

VDDA-1.5 V

SID_DS_13 VOS_HI_M1 Mode 1, High current – 5 – mV With trim 25 °C,

0.2 V to VDDA-1.5 V

SID_DS_14 VOS_MED_M1 Mode 1, Medium current – 5 – mV With trim 25 °C,

0.2 V to VDDA-1.5 V

Table 8. Opamp Specifications

(Guaranteed by Characterization) (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 22 of 42

Comparator

SID_DS_15 VOS_LOW_M1 Mode 1, Low current – 5 – mV With trim 25 °C,

0.2 V to VDDA-1.5 V

SID_DS_16 VOS_HI_M2 Mode 2, High current – 5 – mV With trim 25 °C,

0.2 V to VDDA-1.5 V

SID_DS_17 VOS_MED_M2 Mode 2, Medium current – 5 – mV With trim 25 °C,

0.2 V to VDDA-1.5 V

SID_DS_18 VOS_LOW_M2 Mode 2, Low current – 5 – mV With trim 25 °C,

0.2 V to VDDA-1.5 V

SID_DS_19 IOUT_HI_M1 Mode 1, High current – 10 – mA Output is 0.5 V to

VDDA-0.5 V

SID_DS_20 IOUT_MED_M1 Mode 1, Medium current – 10 – mA Output is 0.5 V to

VDDA-0.5 V

SID_DS_21 IOUT_LOW_M1 Mode 1, Low current – 4 – mA Output is 0.5 V to

VDDA-0.5 V

SID_DS_22 IOUT_HI_M2 Mode 2, High current – 1 – mA Output is 0.5 V to

VDDA-0.5 V

SID_DS_23 IOUT_MED_M2 Mode 2, Medium current – 1 – mA Output is 0.5 V to

VDDA-0.5 V

SID_DS_24 IOUT_LOW_M2 Mode 2, Low current – 0.5 – mA Output is 0.5 V to

VDDA-0.5 V

Table 8. Opamp Specifications

(Guaranteed by Characterization) (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

Table 9. Comparator DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID85 VOFFSET2 Input offset voltage, Common Mode

voltage range from 0 to VDD-1

–– ±4 mV

SID85A VOFFSET3 Input offset voltage. Ultra low-power

mode (VDDD  2.2 V for Temp < 0 °C,

VDDD  1.8 V for Temp > 0 °C)

–±12 – mV

SID86 VHYST Hysteresis when enabled, Common

Mode voltage range from 0 to VDD -1.

– 10 35 mV Guaranteed by

characterization

SID87 VICM1 Input common mode voltage in normal

mode

0–V

DDD – 0.1 V Modes 1 and 2.

SID247 VICM2 Input common mode voltage in low

power mode (VDDD  2.2 V for Temp <

0°C, V

DDD  1.8 V for Temp > 0 °C)

0–V

DDD V

SID247A VICM3 Input common mode voltage in ultra low

power mode

0–V

DDD –

1.15

SID88 CMRR Common mode rejection ratio 50 – – dB VDDD  2.7 V.

Guaranteed by

characterization

SID88A CMRR Common mode rejection ratio 42 – – dB VDDD  2.7 V.

Guaranteed by

characterization

SID89 ICMP1 Block current, normal mode – – 400 µA Guaranteed by

characterization

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 23 of 42

Temperature Sensor

SAR ADC

SID248 ICMP2 Block current, low power mode – – 100 µA Guaranteed by

characterization

SID259 ICMP3 Block current, ultra low power mode

(VDDD  2.2 V for Temp < 0 °C, VDDD 

1.8V for Temp > 0°C)

– 6 28 µA Guaranteed by

characterization

SID90 ZCMP DC input impedance of comparator 35 – – MGuaranteed by

characterization

Table 9. Comparator DC Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

Table 10. Comparator AC Specifications

(Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

SID91 TRESP1 Response time, normal mode – – 110 ns 50-mV overdrive

SID258 TRESP2 Response time, low power mode – – 200 ns 50-mV overdrive

SID92 TRESP3 Response time, ultra low power mode

(VDDD  2.2V for Temp < 0°C, V

DDD 

1.8 V for Temp > 0 °C)

– – 15 µs 200-mV overdrive

Table 11. Temperature Sensor Specifications

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

SID93 TSENSACC Temperature sensor accuracy –5 ±1 +5 °C –40 to +85 °C

Table 12. SAR ADC DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

SID94 A_RES Resolution – – 12 bits

SID95 A_CHNIS_S Number of channels - single ended – – 16 8 full speed

SID96 A-CHNKS_D Number of channels - differential – – 8 Diff inputs use

neighboring I/O

SID97 A-MONO Monotonicity – – – Yes. Based on

characterization

SID98 A_GAINERR Gain error – – ±0.1 % With external

reference.

SID99 A_OFFSET Input offset voltage – – 2 mV Measured with 1-V

VREF.

SID100 A_ISAR Current consumption – – 1 mA

SID101 A_VINS Input voltage range - single ended VSS –V

DDA V Based on device

characterization

SID102 A_VIND Input voltage range - differential VSS – VDDA V Based on device

characterization

SID103 A_INRES Input resistance – – 2.2 KBased on device

characterization

SID104 A_INCAP Input capacitance – – 10 pF Based on device

characterization

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 24 of 42

CSD

Table 13. SAR ADC AC Specifications

(Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

SID106 A_PSRR Power supply rejection ratio 70 – – dB

SID107 A_CMRR Common mode rejection ratio 66 – – dB Measured at 1 V

SID108 A_SAMP_1 Sample rate with external reference bypass

cap

– – 1 Msps

SID108A A_SAMP_2 Sample rate with no bypass cap.

Reference = VDD

– – 1 Msps

SID108B A_SAMP_3 Sample rate with no bypass cap.

Internal reference

– – 100 Ksps

SID109 A_SNDR Signal-to-noise and distortion ratio (SINAD) 66 – – dB FIN = 10 kHz

SID111 A_INL Integral non linearity –1.4 – +1.4 LSB VDD = 1.71 to 5.5,

1 Msps, Vref = 1 to

5.5.

SID111A A_INL Integral non linearity –1.4 – +1.4 LSB VDDD = 1.71 to 3.6,

1 Msps, Vref = 1.71

to VDDD.

SID111B A_INL Integral non linearity –1.4 – +1.4 LSB VDDD = 1.71 to 5.5,

500 ksps, Vref = 1 to

5.5.

SID112 A_DNL Differential non linearity –0.9 – +1.35 LSB VDDD = 1.71 to 5.5,

1 Msps, Vref = 1 to

5.5.

SID112A A_DNL Differential non linearity –0.9 – +1.35 LSB VDDD = 1.71 to 3.6,

1 Msps, Vref = 1.71

to VDDD.

SID112B A_DNL Differential non linearity –0.9 – +1.35 LSB VDDD = 1.71 to 5.5,

500 ksps, Vref = 1 to

5.5.

SID113 A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz.

Table 14. CSD Block Specification

Spec ID# Parameter Description Min Typ Max Units Details/Conditions

CSD Specification

SID308 VCSD Voltage range of operation 1.71 – 5.5 V

SID309 IDAC1 DNL for 8-bit resolution –1 – 1 LSB

SID310 IDAC1 INL for 8-bit resolution –3 – 3 LSB

SID311 IDAC2 DNL for 7-bit resolution –1 – 1 LSB

SID312 IDAC2 INL for 7-bit resolution –3 – 3 LSB

SID313 SNR Ratio of counts of finger to noise.

Guaranteed by characterization

5––Ratio

Capacitance range of

9 to 35 pF, 0.1-pF

sensitivity

SID314 IDAC1_CRT1 Output current of Idac1 (8-bits) in High

range

–612–µA

SID314A IDAC1_CRT2 Output current of Idac1(8-bits) in Low range – 306 – µA

SID315 IDAC2_CRT1 Output current of Idac2 (7-bits) in High

range

–304.8– µA

SID315A IDAC2_CRT2 Output current of Idac2 (7-bits) in Low

range

–152.4– µA

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 25 of 42

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode.

Timer/Counter/PWM

I2C

Table 15. TCPWM Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.TCPWM.1 ITCPWM1 Block current consumption at 3 MHz – – 45 µA All modes

(Timer/Counter/PWM)

SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz – – 155 µA All modes

(Timer/Counter/PWM)

SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz – – 650 µA All modes

(Timer/Counter/PWM)

SID.TCPWM.3 TCPWMFREQ Operating frequency – – Fc MHz Fc max = Fcpu.

Maximum = 24 MHz

SID.TCPWM.4 TPWMENEXT Input Trigger Pulse Width for all

Trigger Events 2/Fc – – ns

Trigger Events can be

Stop, Start, Reload,

Count, Capture, or Kill

depending on which

mode of operation is

selected.

SID.TCPWM.5 TPWMEXT Output Trigger Pulse widths 2/Fc – – ns

Minimum possible

width of Overflow,

Underflow, and CC

(Counter equals

Compare value)

trigger outputs

SID.TCPWM.5A TCRES Resolution of Counter 1/Fc – – ns

Minimum time

between successive

counts

SID.TCPWM.5B PWMRES PWM Resolution 1/Fc – – ns Minimum pulse width

of PWM Output

SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – ns

Minimum pulse width

between Quadrature

phase inputs.

Table 16. Fixed I2C DC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID149 II2C1 Block current consumption at 100 kHz – – 50 µA

SID150 II2C2 Block current consumption at 400 kHz – – 135 µA

SID151 II2C3 Block current consumption at 1 Mbps – – 310 µA

SID152 II2C4 I2C enabled in Deep Sleep mode – – 1.4 µA

Table 17. Fixed I2C AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID153 FI2C1 Bit rate – – 1 Mbps

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 26 of 42

LCD Direct Drive

SPI Specifications

Table 18. LCD Direct Drive DC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID154 ILCDLOW Operating current in low power mode – 5 – µA 16 × 4 small segment

disp. at 50 Hz

SID155 CLCDCAP LCD capacitance per segment/common

driver

– 500 5000 pF Guaranteed by Design

SID156 LCDOFFSET Long-term segment offset – 20 – mV

SID157 ILCDOP1 PWM Mode current. 5-V bias.

24-MHz IMO

– 0.6 – mA 32 × 4 segments.

50 Hz, 25 °C

SID158 ILCDOP2 PWM Mode current. 3.3-V bias.

24-MHz IMO.

– 0.5 – mA 32 × 4 segments.

50 Hz, 25 °C

Table 19. LCD Direct Drive AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID159 FLCD LCD frame rate 10 50 150 Hz

Table 20. Fixed UART DC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID160 IUART1 Block current consumption at

100 Kbps

––55µA

SID161 IUART2 Block current consumption at

1000 Kbps

– – 312 µA

Table 21. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID162 FUART Bit rate – – 1 Mbps

Table 22. Fixed SPI DC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID163 ISPI1 Block current consumption at 1 Mbps – – 360 µA

SID164 ISPI2 Block current consumption at 4 Mbps – – 560 µA

SID165 ISPI3 Block current consumption at 8 Mbps – – 600 µA

Table 23. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID166 FSPI SPI operating frequency (master; 6X

oversampling)

–– 8MHz

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 27 of 42

Memory

Table 24. Fixed SPI Master mode AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID167 TDMO MOSI valid after Sclock driving

edge

– – 15 ns

SID168 TDSI MISO valid before Sclock

capturing edge. Full clock, late

MISO Sampling used

20 – – ns

SID169 THMO Previous MOSI data hold time

with respect to capturing edge at

Slave

0– –ns

Table 25. Fixed SPI Slave mode AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID170 TDMI MOSI valid before Sclock

capturing edge

40 – – ns

SID171 TDSO MISO valid after Sclock driving

edge

– – 42 + 3 ×

(1/FCPU)

SID171A TDSO_ext MISO valid after Sclock driving

edge in Ext. Clock mode

– – 48 ns

SID172 THSO Previous MISO data hold time 0 – – ns

SID172A TSSELSCK SSEL Valid to first SCK Valid

edge

100 – – ns

Table 26. Flash DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID173 VPE Erase and program voltage 1.71 – 5.5 V

Table 27. Flash AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID174 TROWWRITE Row (block) write time (erase and

program)

– – 20 ms Row (block) = 128 bytes

SID175 TROWERASE Row erase time – – 13 ms

SID176 TROWPROGRAM Row program time after erase – – 7 ms

SID178 TBULKERASE Bulk erase time (128 KB) – – 35 ms

SID179 TSECTORERASE Sector erase time (8 KB) – – 15 ms

SID180 TDEVPROG Total device program time – – 15 seconds Guaranteed by charac-

terization

SID181 FEND Flash endurance 100 K – – cycles Guaranteed by charac-

terization

SID182 FRET Flash retention. TA  55 °C, 100 K

P/E cycles

20 – – years Guaranteed by charac-

terization

SID182A Flash retention. TA  85 °C, 10 K

P/E cycles

10 – – years Guaranteed by charac-

terization

SID182B FRETQ Flash retention. TA  105 °C, 10K

P/E cycles,  three years at TA 

85 °C

10 20 – years Guaranteed by charac-

terization.

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 28 of 42

System Resources

Power-on-Reset (POR) with Brown Out

Voltage Monitors

Table 28. Imprecis e Power On Reset (PRES)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID185 VRISEIPOR Rising trip voltage 0.80 – 1.45 V Guaranteed by charac-

terization

SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V Guaranteed by charac-

terization

SID187 VIPORHYST Hysteresis 15 – 200 mV Guaranteed by charac-

terization

Table 29. Precise Power On Reset (POR)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID190 VFALLPPOR BOD trip voltage in active and

sleep modes

1.64 – – V Guaranteed by charac-

terization

SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V Guaranteed by charac-

terization

Table 30. Voltage Monitors DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID195 VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V

SID196 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V

SID197 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V

SID198 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V

SID199 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V

SID200 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V

SID201 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V

SID202 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V

SID203 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V

SID204 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V

SID205 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V

SID206 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V

SID207 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V

SID208 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V

SID209 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V

SID210 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V

SID211 LVI_IDD Block current – – 100 µA Guaranteed by charac-

terization

Table 31. Voltage Monitors AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID212 TMONTRIP Voltage monitor trip time – – 1 µs Guaranteed by charac-

terization

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 29 of 42

SWD Interface

Internal Main Oscillator

Internal Low-Speed Oscillator

Table 32. SWD Interface Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID213 F_SWDCLK1 3.3 V  VDD  5.5 V – – 14 MHz SWDCLK  1/3 CPU

clock frequency

SID214 F_SWDCLK2 1.71 V  VDD  3.3 V – – 7 MHz SWDCLK  1/3 CPU

clock frequency

SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns Guaranteed by

characterization

SID216 T_SWDI_HOLD T = 1/f SWDCLK 0.25*T – – ns Guaranteed by

characterization

SID217 T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T ns Guaranteed by

characterization

SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by

characterization

Table 33. IMO DC Specifications

(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID218 IIMO1 IMO operating current at 48 MHz – – 1000 µA

SID219 IIMO2 IMO operating current at 24 MHz – – 325 µA

SID220 IIMO3 IMO operating current at 12 MHz – – 225 µA

SID221 IIMO4 IMO operating current at 6 MHz – – 180 µA

SID222 IIMO5 IMO operating current at 3 MHz – – 150 µA

Table 34. IMO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID223 FIMOTOL1 Frequency variation from 3 to

48 MHz

– – ±2 % ±3% if TA > 85 °C and

IMO frequency <

24 MHz

SID226 TSTARTIMO IMO startup time – – 12 µs

SID227 TJITRMSIMO1 RMS Jitter at 3 MHz – 156 – ps

SID228 TJITRMSIMO2 RMS Jitter at 24 MHz – 145 – ps

SID229 TJITRMSIMO3 RMS Jitter at 48 MHz – 139 – ps

Table 35. ILO DC Specifications

(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID231 IILO1 ILO operating current at 32 kHz – 0.3 1.05 µA Guaranteed by

Characterization

SID233 IILOLEAK ILO leakage current – 2 15 nA Guaranteed by

Design

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 30 of 42

Table 36. ILO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID234 TSTARTILO1 ILO startup time – – 2 ms Guaranteed by charac-

terization

SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by charac-

terization

SID237 FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Max ILO frequency is

70 kHz if TA > 85 °C

Table 37. External Clock Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID305 ExtClkFreq External Clock input Frequency 0 – 48 MHz Guaranteed by

characterization

SID306 ExtClkDuty Duty cycle; Measured at VDD/2 45 – 55 % Guaranteed by

characterization

Table 38. Watch Crystal Oscillator (WCO) Specifications

Spec Id# Parameter Description Min Typ Max Units Details / Conditions

IMO WCO-PLL calibrated mo de

SID330 IMOWCO1 Frequency variation with IMO set to

3MHz

–0.6 – 0.6 % Does not include WCO

tolerance

SID331 IMOWCO2 Frequency variation with IMO set to

5MHz

–0.4 – 0.4 % Does not include WCO

tolerance

SID332 IMOWCO3 Frequency variation with IMO set to

7MHz or 9MHz

–0.3 – 0.3 % Does not include WCO

tolerance

SID333 IMOWCO4 All other IMO frequency settings –0.2 – 0.2 % Does not include WCO

tolerance

WCO Sp ecifications

SID398 FWCO Crystal frequency – 32.768 – kHz

SID399 FTOL Frequency tolerance – 50 250 ppm With 20-ppm crystal.

SID400 ESR Equivalent series resistance – 50 – k

SID401 PD Drive level – – 1 µW

SID402 TSTART Startup time – – 500 ms

SID403 CLCrystal load capacitance 6 – 12.5 pF

SID404 C0Crystal shunt capacitance – 1.35 – pF

SID405 IWCO1 Operating current (high power

mode)

––8uA

Table 39. UDB AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

Datapa th performance

SID249 FMAX-TIMER Max frequency of 16-bit timer in a

UDB pair

––48MHz

SID250 FMAX-ADDER Max frequency of 16-bit adder in a

UDB pair

––48MHz

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 31 of 42

SID251 FMAX_CRC Max frequency of 16-bit CRC/PRS

in a UDB pair

––48MHz

PLD Performance in UDB

SID252 FMAX_PLD Max frequency of 2-pass PLD

function in a UDB pair

––48MHz

Clock to Output Performance

SID253 TCLK_OUT_UDB1 Prop. delay for clock in to data out

at 25 °C, Typ.

–15 – ns

SID254 TCLK_OUT_UDB2 Prop. delay for clock in to data out,

Worst case.

–25 – ns

Table 39. UDB AC Specifications

(Guaranteed by Characterization) (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

Table 40. Block Specs

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID256* TWS48* Number of wait states at 48 MHz 2 – – CPU execution from

Flash

SID257 TWS24* Number of wait states at 24 MHz 1 – – CPU execution from

Flash

SID260 VREFSAR Trimmed internal reference to SAR –1 – +1 % Percentage of Vbg

(1.024 V).

Guaranteed by

characterization

SID261 FSARINTREF SAR operating speed without

external reference bypass

– – 100 ksps 12-bit resolution.

Guaranteed by

characterization

SID262 TCLKSWITCH Clock switching from clk1 to clk2 in

clk1 periods

3 – 4 Periods . Guaranteed by

design

* Tws48 and Tws24 are guaranteed by Design

Table 41. UDB Port Adaptor Specifications

(Based on LPC Component Specs, Guaranteed by Characterization -10-pF load, 3-V VDDIO and VDDD)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID263 TLCLKDO LCLK to output delay – – 18 ns

SID264 TDINLCLK Input setup time to LCLCK rising

edge

–– 7ns

SID265 TDINLCLKHLD Input hold time from LCLK rising edge 0 – – ns

SID266 TLCLKHIZ LCLK to output tristated – – 28 ns

SID267 TFLCLK LCLK frequency – – 33 MHz

SID268 TLCLKDUTY LCLK duty cycle (percentage high) 40 – 60 %

Table 42. CAN Specifications

SPEC ID# Parameter Description Min Typ Max Units Details /Conditions

SID420 IDD_CAN Block current consumption – – 200 uA

SID421 CAN_bits CAN Bit rate (Min 8-MHZ clock) – – 1 Mbps

PSoC® 4: PSoC 4200M Family

Datasheet

Document Number: 001-93963 Rev. *G Page 32 of 42

Ordering Information

The PSoC 4200M family part numbers and features are listed in the following table.

The nomenclature used in the preceding table is based on the following part numbering convention: