32 SH7146 Group User's Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family SH7146 SH7149 R5F7146 R5M7146 R5F7149 R5M7149 Rev.4.00 Sep 2010 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. Page ii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page iii of xlii Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix * Product Type, Package Dimensions, etc. 10. Main Revisions for This Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Page iv of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Preface The SH7146 and SH7149 Group RISC (Reduced Instruction Set Computer) microcomputers include a Renesas original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the SH7146 and SH7149 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7146 and SH7149 Group to the target users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 23, List of Registers. Examples: Related Manuals: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page v of xlii SH7146 and SH7149 Group Manuals: Document Title Document No. SH7146 Group Hardware Manual This manual SH-1/SH-2/SH-DSP Software Manual REJ09B0171 User's Manuals for Development Tools: Document Title Document No. TM REJ10B0152 SuperH RISC engine High-performance Embedded Workshop 3 User's Manual TM REJ10B0025 SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial REJ10B0023 SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.00 User's Manual Application note: Document Title Document No. SuperH RISC engine C/C++ Compiler Package Application Note REJ05B0463 All trademarks and registered trademarks are the property of their respective owners. Page vi of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Contents Section 1 Overview..................................................................................................1 1.1 1.2 1.3 1.4 Features of SH7146 and SH7149.......................................................................................... 1 Block Diagram...................................................................................................................... 6 Pin Assignments ................................................................................................................... 7 Pin Functions ........................................................................................................................ 9 Section 2 CPU........................................................................................................15 2.1 2.2 2.3 2.4 2.5 2.6 Features............................................................................................................................... 15 Register Configuration........................................................................................................ 16 2.2.1 General Registers (Rn)........................................................................................ 17 2.2.2 Control Registers ................................................................................................ 17 2.2.3 System Registers................................................................................................. 19 2.2.4 Initial Values of Registers................................................................................... 19 Data Formats....................................................................................................................... 20 2.3.1 Register Data Format .......................................................................................... 20 2.3.2 Memory Data Formats ........................................................................................ 20 2.3.3 Immediate Data Formats..................................................................................... 21 Features of Instructions....................................................................................................... 21 2.4.1 RISC Type .......................................................................................................... 21 2.4.2 Addressing Modes .............................................................................................. 24 2.4.3 Instruction Formats ............................................................................................. 27 Instruction Set ..................................................................................................................... 31 2.5.1 Instruction Set by Type....................................................................................... 31 2.5.2 Data Transfer Instructions................................................................................... 35 2.5.3 Arithmetic Operation Instructions ...................................................................... 37 2.5.4 Logic Operation Instructions .............................................................................. 39 2.5.5 Shift Instructions................................................................................................. 40 2.5.6 Branch Instructions ............................................................................................. 41 2.5.7 System Control Instructions................................................................................ 42 Processing States................................................................................................................. 44 Section 3 MCU Operating Modes..........................................................................47 3.1 3.2 3.3 Selection of Operating Modes............................................................................................. 47 Input/Output Pins................................................................................................................ 48 Operating Modes................................................................................................................. 49 3.3.1 Mode 0 (MCU Extension Mode 0) ..................................................................... 49 3.3.2 Mode 1 (MCU Extension Mode 1) ..................................................................... 49 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page vii of xlii 3.4 3.5 3.6 3.3.3 Mode 2 (MCU Extension Mode 2) ..................................................................... 49 3.3.4 Mode 3 (Single Chip Mode) ............................................................................... 49 Address Map....................................................................................................................... 50 Initial State in This LSI....................................................................................................... 52 Note on Changing Operating Mode.................................................................................... 52 Section 4 Clock Pulse Generator (CPG) ...............................................................53 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Features............................................................................................................................... 53 Input/Output Pins................................................................................................................ 57 Clock Operating Mode........................................................................................................ 58 Register Descriptions.......................................................................................................... 63 4.4.1 Frequency Control Register (FRQCR) ............................................................... 63 4.4.2 Oscillation Stop Detection Control Register (OSCCR) ...................................... 66 Changing Frequency ........................................................................................................... 67 Oscillator ............................................................................................................................ 68 4.6.1 Connecting Crystal Resonator ............................................................................ 68 4.6.2 External Clock Input Method.............................................................................. 69 Function for Detecting Oscillator Stop ............................................................................... 70 Usage Notes ........................................................................................................................ 71 4.8.1 Note on Crystal Resonator .................................................................................. 71 4.8.2 Notes on Board Design ....................................................................................... 71 Section 5 Exception Handling ...............................................................................73 5.1 5.2 5.3 5.4 5.5 Overview ............................................................................................................................ 73 5.1.1 Types of Exception Handling and Priority ......................................................... 73 5.1.2 Exception Handling Operations .......................................................................... 74 5.1.3 Exception Handling Vector Table....................................................................... 75 Resets.................................................................................................................................. 77 5.2.1 Types of Resets................................................................................................... 77 5.2.2 Power-On Reset .................................................................................................. 77 5.2.3 Manual Reset ...................................................................................................... 78 Address Errors .................................................................................................................... 79 5.3.1 Address Error Sources ........................................................................................ 79 5.3.2 Address Error Exception Source......................................................................... 80 Interrupts............................................................................................................................. 81 5.4.1 Interrupt Sources................................................................................................. 81 5.4.2 Interrupt Priority ................................................................................................. 82 5.4.3 Interrupt Exception Handling ............................................................................. 82 Exceptions Triggered by Instructions ................................................................................. 83 5.5.1 Types of Exceptions Triggered by Instructions .................................................. 83 Page viii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 5.6 5.7 5.8 5.5.2 Trap Instructions ................................................................................................. 83 5.5.3 Illegal Slot Instructions ....................................................................................... 84 5.5.4 General Illegal Instructions................................................................................. 84 Cases when Exceptions Are Accepted................................................................................ 85 Stack States after Exception Handling Ends....................................................................... 86 Usage Notes ........................................................................................................................ 88 5.8.1 Value of Stack Pointer (SP) ................................................................................ 88 5.8.2 Value of Vector Base Register (VBR) ................................................................ 88 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling ...... 88 5.8.4 Notes on Slot Illegal Instruction Exception Handling......................................... 89 Section 6 Interrupt Controller (INTC) ...................................................................91 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Features............................................................................................................................... 91 Input/Output Pins................................................................................................................ 93 Register Descriptions .......................................................................................................... 94 6.3.1 Interrupt Control Register 0 (ICR0).................................................................... 95 6.3.2 IRQ Control Register (IRQCR) .......................................................................... 96 6.3.3 IRQ Status register (IRQSR)............................................................................... 98 6.3.4 Interrupt Priority Registers A, D to F, and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL) ....................................................... 101 Interrupt Sources............................................................................................................... 104 6.4.1 External Interrupts ............................................................................................ 104 6.4.2 On-Chip Peripheral Module Interrupts ............................................................. 105 6.4.3 User Break Interrupt ......................................................................................... 105 Interrupt Exception Handling Vector Table...................................................................... 106 Interrupt Operation ........................................................................................................... 109 6.6.1 Interrupt Sequence ............................................................................................ 109 6.6.2 Stack after Interrupt Exception Handling ......................................................... 112 Interrupt Response Time................................................................................................... 112 Data Transfer with Interrupt Request Signals ................................................................... 114 6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation and CPU Interrupts .................................................................................................. 115 6.8.2 Handling Interrupt Request Signals as Sources for DTC Activation, but Not CPU Interrupts ..................................................................................... 115 6.8.3 Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not DTC Activation.................................................................................... 116 Usage Note........................................................................................................................ 116 Section 7 User Break Controller (UBC) ..............................................................117 7.1 Features............................................................................................................................. 117 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page ix of xlii 7.2 7.3 7.4 7.5 Input/Output Pins.............................................................................................................. 119 Register Descriptions........................................................................................................ 120 7.3.1 Break Address Register A (BARA) .................................................................. 121 7.3.2 Break Address Mask Register A (BAMRA)..................................................... 121 7.3.3 Break Bus Cycle Register A (BBRA)............................................................... 122 7.3.4 Break Data Register A (BDRA) (F-ZTAT Version Only)................................ 124 7.3.5 Break Data Mask Register A (BDMRA) (F-ZTAT Version Only) .................. 125 7.3.6 Break Address Register B (BARB) .................................................................. 126 7.3.7 Break Address Mask Register B (BAMRB) ..................................................... 127 7.3.8 Break Data Register B (BDRB) (F-ZTAT Version Only) ................................ 128 7.3.9 Break Data Mask Register B (BDMRB) (F-ZTAT Version Only)................... 129 7.3.10 Break Bus Cycle Register B (BBRB) ............................................................... 130 7.3.11 Break Control Register (BRCR) ....................................................................... 132 7.3.12 Execution Times Break Register (BETR) (F-ZTAT Version Only) ................. 137 7.3.13 Branch Source Register (BRSR) (F-ZTAT Version Only)............................... 138 7.3.14 Branch Destination Register (BRDR) (F-ZTAT Version Only) ....................... 139 Operation .......................................................................................................................... 140 7.4.1 Flow of the User Break Operation .................................................................... 140 7.4.2 User Break on Instruction Fetch Cycle ............................................................. 141 7.4.3 User Break on Data Access Cycle .................................................................... 142 7.4.4 Sequential Break ............................................................................................... 143 7.4.5 Value of Saved Program Counter ..................................................................... 143 7.4.6 PC Trace ........................................................................................................... 144 7.4.7 Usage Examples................................................................................................ 145 Usage Notes ...................................................................................................................... 150 Section 8 Data Transfer Controller (DTC)..........................................................153 8.1 8.2 8.3 Features............................................................................................................................. 153 Register Descriptions........................................................................................................ 155 8.2.1 DTC Mode Register A (MRA) ......................................................................... 156 8.2.2 DTC Mode Register B (MRB).......................................................................... 157 8.2.3 DTC Source Address Register (SAR)............................................................... 159 8.2.4 DTC Destination Address Register (DAR)....................................................... 159 8.2.5 DTC Transfer Count Register A (CRA) ........................................................... 160 8.2.6 DTC Transfer Count Register B (CRB)............................................................ 161 8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ................................... 162 8.2.8 DTC Control Register (DTCCR) ...................................................................... 163 8.2.9 DTC Vector Base Register (DTCVBR)............................................................ 165 8.2.10 Bus Function Extending Register (BSCEHR) .................................................. 165 Activation Sources............................................................................................................ 166 Page x of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 8.4 8.5 8.6 8.7 8.8 8.9 Location of Transfer Information and DTC Vector Table ................................................ 166 Operation .......................................................................................................................... 170 8.5.1 Transfer Information Read Skip Function ........................................................ 175 8.5.2 Transfer Information Writeback Skip Function ................................................ 176 8.5.3 Normal Transfer Mode ..................................................................................... 176 8.5.4 Repeat Transfer Mode....................................................................................... 177 8.5.5 Block Transfer Mode ........................................................................................ 179 8.5.6 Chain Transfer .................................................................................................. 180 8.5.7 Operation Timing.............................................................................................. 182 8.5.8 Number of DTC Execution Cycles ................................................................... 185 8.5.9 DTC Bus Release Timing ................................................................................. 187 8.5.10 DTC Activation Priority Order ......................................................................... 190 DTC Activation by Interrupt............................................................................................. 191 Examples of Use of the DTC ............................................................................................ 192 8.7.1 Normal Transfer Mode ..................................................................................... 192 8.7.2 Chain Transfer when Counter = 0..................................................................... 192 Interrupt Sources............................................................................................................... 194 Usage Notes ...................................................................................................................... 194 8.9.1 Module Standby Mode Setting ......................................................................... 194 8.9.2 On-Chip RAM .................................................................................................. 194 8.9.3 DTCE Bit Setting.............................................................................................. 194 8.9.4 Chain Transfer .................................................................................................. 194 8.9.5 Transfer Information Start Address, Source Address, and Destination Address ................................................................................... 194 8.9.6 Access to DTC Registers through DTC ............................................................ 195 8.9.7 Notes on IRQ Interrupt as DTC Activation Source .......................................... 195 8.9.8 Notes on SCI as DTC Activation Sources ........................................................ 195 8.9.9 Clearing Interrupt Source Flag.......................................................................... 195 8.9.10 Conflict between NMI Interrupt and DTC Activation ...................................... 195 8.9.11 Operation When a DTC Activation Request Is Cancelled While in Progress......................................................................................................... 195 Section 9 Bus State Controller (BSC)..................................................................197 9.1 9.2 9.3 9.4 Features............................................................................................................................. 197 Input/Output Pins.............................................................................................................. 199 Area Overview.................................................................................................................. 199 9.3.1 Area Division .................................................................................................... 199 9.3.2 Address Map ..................................................................................................... 199 Register Descriptions ........................................................................................................ 203 9.4.1 Common Control Register (CMNCR) .............................................................. 203 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xi of xlii 9.5 9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 and 1) .............................. 205 9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 and 1)............................ 208 9.4.4 Bus Function Extending Register (BSCEHR) .................................................. 210 Operation .......................................................................................................................... 214 9.5.1 Endian/Access Size and Data Alignment.......................................................... 214 9.5.2 Normal Space Interface..................................................................................... 216 9.5.3 Access Wait Control ......................................................................................... 220 9.5.4 CSn Assert Period Extension ............................................................................ 222 9.5.5 Wait between Access Cycles ............................................................................ 223 9.5.6 Bus Arbitration ................................................................................................. 226 9.5.7 Others................................................................................................................ 230 9.5.8 Access to On-Chip FLASH and On-Chip RAM by CPU ................................. 231 9.5.9 Access to On-Chip Peripheral I/O Registers by CPU ....................................... 231 9.5.10 Access to External Memory by CPU ................................................................ 233 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2).....................................237 10.1 10.2 10.3 Features............................................................................................................................. 237 Input/Output Pins.............................................................................................................. 243 Register Descriptions........................................................................................................ 244 10.3.1 Timer Control Register (TCR).......................................................................... 248 10.3.2 Timer Mode Register (TMDR) ......................................................................... 252 10.3.3 Timer I/O Control Register (TIOR) .................................................................. 255 10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) ................................ 274 10.3.5 Timer Interrupt Enable Register (TIER) ........................................................... 275 10.3.6 Timer Status Register (TSR)............................................................................. 280 10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)............................... 288 10.3.8 Timer Input Capture Control Register (TICCR) ............................................... 289 10.3.9 Timer Synchronous Clear Register (TSYCR)................................................... 291 10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ..................... 293 10.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) .................................................................. 296 10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4)............................................................. 296 10.3.13 Timer Counter (TCNT)..................................................................................... 297 10.3.14 Timer General Register (TGR) ......................................................................... 297 10.3.15 Timer Start Register (TSTR) ............................................................................ 298 10.3.16 Timer Synchronous Register (TSYR)............................................................... 300 10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ................................. 302 10.3.18 Timer Read/Write Enable Register (TRWER) ................................................. 305 10.3.19 Timer Output Master Enable Register (TOER) ................................................ 306 Page xii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 10.4 10.5 10.6 10.7 10.3.20 Timer Output Control Register 1 (TOCR1) ...................................................... 307 10.3.21 Timer Output Control Register 2 (TOCR2) ...................................................... 310 10.3.22 Timer Output Level Buffer Register (TOLBR) ................................................ 313 10.3.23 Timer Gate Control Register (TGCR)............................................................... 314 10.3.24 Timer Subcounter (TCNTS) ............................................................................. 316 10.3.25 Timer Dead Time Data Register (TDDR)......................................................... 317 10.3.26 Timer Cycle Data Register (TCDR) ................................................................. 317 10.3.27 Timer Cycle Buffer Register (TCBR)............................................................... 318 10.3.28 Timer Interrupt Skipping Set Register (TITCR) ............................................... 318 10.3.29 Timer Interrupt Skipping Counter (TITCNT)................................................... 320 10.3.30 Timer Buffer Transfer Set Register (TBTER) .................................................. 321 10.3.31 Timer Dead Time Enable Register (TDER)...................................................... 323 10.3.32 Timer Waveform Control Register (TWCR) .................................................... 324 10.3.33 Bus Master Interface ......................................................................................... 326 Operation .......................................................................................................................... 327 10.4.1 Basic Functions................................................................................................. 327 10.4.2 Synchronous Operation..................................................................................... 333 10.4.3 Buffer Operation ............................................................................................... 335 10.4.4 Cascaded Operation .......................................................................................... 339 10.4.5 PWM Modes ..................................................................................................... 344 10.4.6 Phase Counting Mode ....................................................................................... 349 10.4.7 Reset-Synchronized PWM Mode...................................................................... 356 10.4.8 Complementary PWM Mode ............................................................................ 359 10.4.9 A/D Converter Start Request Delaying Function.............................................. 404 10.4.10 MTU2-MTU2S Synchronous Operation.......................................................... 408 10.4.11 External Pulse Width Measurement.................................................................. 414 10.4.12 Dead Time Compensation................................................................................. 415 10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ... 417 Interrupt Sources............................................................................................................... 418 10.5.1 Interrupt Sources and Priorities......................................................................... 418 10.5.2 DTC Activation................................................................................................. 420 10.5.3 A/D Converter Activation................................................................................. 421 Operation Timing.............................................................................................................. 423 10.6.1 Input/Output Timing ......................................................................................... 423 10.6.2 Interrupt Signal Timing..................................................................................... 430 Usage Notes ...................................................................................................................... 435 10.7.1 Module Standby Mode Setting ......................................................................... 435 10.7.2 Input Clock Restrictions ................................................................................... 435 10.7.3 Caution on Period Setting ................................................................................. 436 10.7.4 Contention between TCNT Write and Clear Operations.................................. 436 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xiii of xlii 10.8 10.7.5 Contention between TCNT Write and Increment Operations........................... 437 10.7.6 Contention between TGR Write and Compare Match ...................................... 438 10.7.7 Contention between Buffer Register Write and Compare Match ..................... 439 10.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 440 10.7.9 Contention between TGR Read and Input Capture........................................... 441 10.7.10 Contention between TGR Write and Input Capture.......................................... 442 10.7.11 Contention between Buffer Register Write and Input Capture ......................... 443 10.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection...................................................................................... 443 10.7.13 Counter Value during Complementary PWM Mode Stop ................................ 445 10.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 445 10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 446 10.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 447 10.7.17 Contention between Overflow/Underflow and Counter Clearing..................... 448 10.7.18 Contention between TCNT Write and Overflow/Underflow............................ 449 10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode...................................................................... 449 10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode...................................................................... 450 10.7.21 Interrupts in Module Standby Mode ................................................................. 450 10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection........ 450 10.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode ......................................................... 451 MTU2 Output Pin Initialization........................................................................................ 453 10.8.1 Operating Modes............................................................................................... 453 10.8.2 Reset Start Operation ........................................................................................ 453 10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc............... 454 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. .............................................................................. 455 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) ................................ 485 11.1 11.2 Input/Output Pins.............................................................................................................. 489 Register Descriptions........................................................................................................ 490 Section 12 Port Output Enable (POE) .................................................................493 12.1 12.2 12.3 Features............................................................................................................................. 493 Input/Output Pins.............................................................................................................. 495 Register Descriptions........................................................................................................ 497 12.3.1 Input Level Control/Status Register 1 (ICSR1) ................................................ 498 12.3.2 Output Level Control/Status Register 1 (OCSR1) ............................................ 502 Page xiv of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 12.4 12.5 12.6 12.3.3 Input Level Control/Status Register 2 (ICSR2) ................................................ 503 12.3.4 Output Level Control/Status Register 2 (OCSR2) ............................................ 507 12.3.5 Input Level Control/Status Register 3 (ICSR3) ................................................ 508 12.3.6 Software Port Output Enable Register (SPOER) .............................................. 510 12.3.7 Port Output Enable Control Register 1 (POECR1) ........................................... 511 12.3.8 Port Output Enable Control Register 2 (POECR2) ........................................... 513 Operation .......................................................................................................................... 516 12.4.1 Input Level Detection Operation....................................................................... 517 12.4.2 Output-Level Compare Operation .................................................................... 518 12.4.3 Release from High-Impedance State................................................................. 519 Interrupts........................................................................................................................... 520 Usage Note........................................................................................................................ 521 12.6.1 Pin State When a Power-On Reset Is Issued from the Watchdog Timer .......... 521 Section 13 Watchdog Timer (WDT)....................................................................523 13.1 13.2 13.3 13.4 13.5 13.6 Features............................................................................................................................. 523 Input/Output Pin for WDT................................................................................................ 525 Register Descriptions ........................................................................................................ 526 13.3.1 Watchdog Timer Counter (WTCNT)................................................................ 526 13.3.2 Watchdog Timer Control/Status Register (WTCSR) ........................................ 527 13.3.3 Notes on Register Access.................................................................................. 529 Operation .......................................................................................................................... 530 13.4.1 Revoking Software Standbys ............................................................................ 530 13.4.2 Using Watchdog Timer Mode........................................................................... 530 13.4.3 Using Interval Timer Mode............................................................................... 531 Interrupt Source ................................................................................................................ 532 Usage Note........................................................................................................................ 532 13.6.1 WTCNT Setting Value ..................................................................................... 532 Section 14 Serial Communication Interface (SCI) ..............................................533 14.1 14.2 14.3 Features............................................................................................................................. 533 Input/Output Pins.............................................................................................................. 535 Register Descriptions ........................................................................................................ 536 14.3.1 Receive Shift Register (SCRSR)....................................................................... 537 14.3.2 Receive Data Register (SCRDR) ...................................................................... 537 14.3.3 Transmit Shift Register (SCTSR) ..................................................................... 537 14.3.4 Transmit Data Register (SCTDR)..................................................................... 538 14.3.5 Serial Mode Register (SCSMR)........................................................................ 538 14.3.6 Serial Control Register (SCSCR)...................................................................... 541 14.3.7 Serial Status Register (SCSSR)......................................................................... 544 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xv of xlii 14.4 14.5 14.6 14.7 14.3.8 Serial Port Register (SCSPTR) ......................................................................... 550 14.3.9 Serial Direction Control Register (SCSDCR)................................................... 552 14.3.10 Bit Rate Register (SCBRR) .............................................................................. 553 Operation .......................................................................................................................... 564 14.4.1 Overview........................................................................................................... 564 14.4.2 Operation in Asynchronous Mode .................................................................... 566 14.4.3 Clock Synchronous Mode................................................................................. 576 14.4.4 Multiprocessor Communication Function ........................................................ 585 14.4.5 Multiprocessor Serial Data Transmission ......................................................... 586 14.4.6 Multiprocessor Serial Data Reception .............................................................. 588 SCI Interrupt Sources and DTC........................................................................................ 591 Serial Port Register (SCSPTR) and SCI Pins ................................................................... 592 Usage Notes ...................................................................................................................... 594 14.7.1 SCTDR Writing and TDRE Flag ...................................................................... 594 14.7.2 Multiple Receive Error Occurrence .................................................................. 594 14.7.3 Break Detection and Processing ....................................................................... 595 14.7.4 Sending a Break Signal..................................................................................... 595 14.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 595 14.7.6 Note on Using DTC .......................................................................................... 597 14.7.7 Note on Using External Clock in Clock Synchronous Mode............................ 597 14.7.8 Module Standby Mode Setting ......................................................................... 597 Section 15 A/D Converter (ADC) .......................................................................599 15.1 15.2 15.3 15.4 15.5 Features............................................................................................................................. 599 Input/Output Pins.............................................................................................................. 601 Register Descriptions........................................................................................................ 602 15.3.1 A/D Data Registers 0, 2, 4, 6, and 8 to 15 (ADDR0, ADDR2, ADDR4, ADDR6, and ADDR8 to ADDR15) .................................................. 603 15.3.2 A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2).................... 604 15.3.3 A/D Control Registers_0 to _2 (ADCR_0 to ADCR_2)................................... 607 15.3.4 A/D Trigger Select Registers_0 and _1 (ADTSR_0 and ADTSR_1) ............... 610 Operation .......................................................................................................................... 616 15.4.1 Single Mode...................................................................................................... 616 15.4.2 Continuous Scan Mode..................................................................................... 616 15.4.3 Single-Cycle Scan Mode................................................................................... 617 15.4.4 Input Sampling and A/D Conversion Time ...................................................... 617 15.4.5 A/D Converter Activation by MTU2 or MTU2S.............................................. 620 15.4.6 External Trigger Input Timing.......................................................................... 620 15.4.7 2-Channel Scanning.......................................................................................... 621 Interrupt Sources and DTC Transfer Request................................................................... 622 Page xvi of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 15.6 15.7 Definitions of A/D Conversion Accuracy......................................................................... 623 Usage Notes ...................................................................................................................... 626 15.7.1 Module Standby Mode Setting ......................................................................... 626 15.7.2 Permissible Signal Source Impedance .............................................................. 626 15.7.3 Influences on Absolute Accuracy ..................................................................... 626 15.7.4 Range of Analog Power Supply and Other Pin Settings ................................... 627 15.7.5 Notes on Board Design ..................................................................................... 627 15.7.6 Notes on Noise Countermeasures ..................................................................... 628 Section 16 Compare Match Timer (CMT)...........................................................629 16.1 16.2 16.3 16.4 16.5 Features............................................................................................................................. 629 Register Descriptions ........................................................................................................ 630 16.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 631 16.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 631 16.2.3 Compare Match Counter (CMCNT) ................................................................. 633 16.2.4 Compare Match Constant Register (CMCOR) ................................................. 633 Operation .......................................................................................................................... 634 16.3.1 Interval Count Operation .................................................................................. 634 16.3.2 CMCNT Count Timing..................................................................................... 634 Interrupts........................................................................................................................... 635 16.4.1 CMT Interrupt Sources and DTC Activation.................................................... 635 16.4.2 Timing of Setting Compare Match Flag ........................................................... 635 16.4.3 Timing of Clearing Compare Match Flag ......................................................... 636 Usage Notes ...................................................................................................................... 637 16.5.1 Module Standby Mode Setting ......................................................................... 637 16.5.2 Conflict between Write and Compare-Match Processes of CMCNT ............... 637 16.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 638 16.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT................. 639 16.5.5 Compare Match between CMCNT and CMCOR ............................................. 639 Section 17 Pin Function Controller (PFC)...........................................................641 17.1 Register Descriptions ........................................................................................................ 658 17.1.1 Port A I/O Register L (PAIORL) ...................................................................... 659 17.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4).............................. 659 17.1.3 Port B I/O Register L, H (PBIORL, PBIORH) ................................................. 673 17.1.4 Port B Control Registers L1, L2, H1 (PBCRL1, PBCRL2, PBCRH1)............. 674 17.1.5 Port D I/O Register L (PDIORL) (SH7149 Only) ............................................ 681 17.1.6 Port D Control Registers L1 to L4 (PDCRL1 to PDCRL4) (SH7149 Only) .... 681 17.1.7 Port E I/O Registers L, H (PEIORL, PEIORH) ................................................ 688 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xvii of xlii 17.1.8 17.2 Port E Control Registers L1 to L4, H1, H2 (PECRL1 to PECRL4, PECRH1, PECRH2).......................................................................................... 689 17.1.9 IRQOUT Function Control Register (IFCR) .................................................... 706 Usage Notes ...................................................................................................................... 707 Section 18 I/O Ports.............................................................................................709 18.1 18.2 18.3 18.4 18.5 Port A................................................................................................................................ 710 18.1.1 Register Descriptions ........................................................................................ 712 18.1.2 Port A Data Register L (PADRL) ..................................................................... 712 18.1.3 Port A Port Register L (PAPRL) ...................................................................... 714 Port B................................................................................................................................ 715 18.2.1 Register Descriptions ........................................................................................ 716 18.2.2 Port B Data Registers H and L (PBDRH and PBDRL) .................................... 716 18.2.3 Port B Port Registers H and L (PBPRH and PBPRL)....................................... 719 Port D (SH7149 Only) ...................................................................................................... 721 18.3.1 Register Descriptions ........................................................................................ 722 18.3.2 Port D Data Register L (PDDRL) ..................................................................... 722 18.3.3 Port D Port Register L (PDPRL) ...................................................................... 724 Port E ................................................................................................................................ 725 18.4.1 Register Descriptions ........................................................................................ 727 18.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ..................................... 727 18.4.3 Port E Port Registers H and L (PEPRH and PEPRL) ....................................... 730 Port F ................................................................................................................................ 732 18.5.1 Register Descriptions ........................................................................................ 733 18.5.2 Port F Data Register L (PFDRL) ...................................................................... 733 Section 19 Flash Memory....................................................................................735 19.1 19.2 19.3 19.4 Features............................................................................................................................. 735 Overview .......................................................................................................................... 737 19.2.1 Block Diagram.................................................................................................. 737 19.2.2 Operating Mode ................................................................................................ 738 19.2.3 Mode Comparison............................................................................................. 740 19.2.4 Flash Memory Configuration............................................................................ 741 19.2.5 Block Division .................................................................................................. 742 19.2.6 Programming/Erasing Interface ........................................................................ 742 Input/Output Pins.............................................................................................................. 745 Register Descriptions........................................................................................................ 745 19.4.1 Registers ........................................................................................................... 745 19.4.2 Programming/Erasing Interface Registers ........................................................ 748 19.4.3 Programming/Erasing Interface Parameters ..................................................... 755 Page xviii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 19.4.4 RAM Emulation Register (RAMER)................................................................ 770 19.5 On-Board Programming Mode ......................................................................................... 772 19.5.1 Boot Mode ........................................................................................................ 772 19.5.2 User Program Mode.......................................................................................... 776 19.5.3 User Boot Mode................................................................................................ 785 19.6 Protection .......................................................................................................................... 790 19.6.1 Hardware Protection ......................................................................................... 790 19.6.2 Software Protection........................................................................................... 791 19.6.3 Error Protection................................................................................................. 791 19.7 Flash Memory Emulation in RAM ................................................................................... 793 19.8 Usage Notes ...................................................................................................................... 796 19.8.1 Switching between User MAT and User Boot MAT........................................ 796 19.8.2 Interrupts during Programming/Erasing ........................................................... 797 19.8.3 Other Notes ....................................................................................................... 800 19.9 Supplementary Information .............................................................................................. 802 19.9.1 Specifications of the Standard Serial Communications Interface in Boot Mode .................................................................................................... 802 19.9.2 Areas for Storage of the Procedural Program and Data for Programming........ 832 19.10 Programmer Mode ............................................................................................................ 840 Section 20 Masked ROM.....................................................................................841 20.1 Usage Note........................................................................................................................ 842 20.1.1 Module Standby Mode Setting ......................................................................... 842 Section 21 RAM ..................................................................................................843 21.1 Usage Notes ...................................................................................................................... 844 21.1.1 Module Standby Mode Setting ......................................................................... 844 21.1.2 Address Error.................................................................................................... 844 21.1.3 Initial Values in RAM....................................................................................... 844 Section 22 Power-Down Modes ..........................................................................845 22.1 22.2 22.3 Features............................................................................................................................. 845 22.1.1 Types of Power-Down Modes .......................................................................... 845 Input/Output Pins.............................................................................................................. 847 Register Descriptions ........................................................................................................ 848 22.3.1 Standby Control Register 1 (STBCR1)............................................................. 848 22.3.2 Standby Control Register 2 (STBCR2)............................................................. 849 22.3.3 Standby Control Register 3 (STBCR3)............................................................. 850 22.3.4 Standby Control Register 4 (STBCR4)............................................................. 851 22.3.5 Standby Control Register 5 (STBCR5)............................................................. 853 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xix of xlii 22.4 22.5 22.6 22.7 22.8 22.3.6 Standby Control Register 6 (STBCR6)............................................................. 854 22.3.7 RAM Control Register (RAMCR) .................................................................... 855 Sleep Mode ....................................................................................................................... 856 22.4.1 Transition to Sleep Mode.................................................................................. 856 22.4.2 Canceling Sleep Mode ...................................................................................... 856 Software Standby Mode.................................................................................................... 857 22.5.1 Transition to Software Standby Mode .............................................................. 857 22.5.2 Canceling Software Standby Mode................................................................... 858 Deep Software Standby Mode .......................................................................................... 859 22.6.1 Transition to Deep Software Standby Mode..................................................... 859 22.6.2 Canceling Deep Software Standby Mode ......................................................... 859 Module Standby Mode...................................................................................................... 860 22.7.1 Transition to Module Standby Mode ................................................................ 860 22.7.2 Canceling Module Standby Function................................................................ 860 Usage Note........................................................................................................................ 861 22.8.1 Current Consumption while Waiting for Oscillation to be Stabilized .............. 861 22.8.2 Executing the SLEEP Instruction ..................................................................... 861 Section 23 List of Registers.................................................................................863 23.1 23.2 23.3 Register Address Table (In the Order from Lower Addresses) ........................................ 864 Register Bit List ................................................................................................................ 876 Register States in Each Operating Mode .......................................................................... 894 Section 24 Electrical Characteristics ...................................................................905 24.1 24.2 24.3 24.4 Absolute Maximum Ratings ............................................................................................. 905 DC Characteristics ............................................................................................................ 906 AC Characteristics ............................................................................................................ 910 24.3.1 Clock Timing .................................................................................................... 911 24.3.2 Control Signal Timing ...................................................................................... 914 24.3.3 AC Bus Timing................................................................................................. 917 24.3.4 Multi Function Timer Pulse Unit 2 (MTU2) Timing........................................ 923 24.3.5 Multi Function Timer Pulse Unit 2S (MTU2S) Timing ................................... 924 24.3.6 I/O Port Timing................................................................................................. 925 24.3.7 Watchdog Timer (WDT) Timing...................................................................... 926 24.3.8 Serial Communication Interface (SCI) Timing................................................. 927 24.3.9 Port Output Enable (POE) Timing.................................................................... 929 24.3.10 UBC Trigger Timing ........................................................................................ 930 24.3.11 A/D Converter Timing...................................................................................... 931 24.3.12 AC Characteristics Measurement Conditions ................................................... 932 A/D Converter Characteristics.......................................................................................... 933 Page xx of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 24.5 24.6 Flash Memory Characteristics .......................................................................................... 934 Usage Note........................................................................................................................ 935 24.6.1 Notes on Connecting VCL Capacitor .................................................................. 935 Appendix..............................................................................................................937 A. B. C. D. E. Pin States .......................................................................................................................... 937 Processing of Unused Pins................................................................................................ 943 Pin States of Bus Related Signals ..................................................................................... 944 Product Code Lineup ........................................................................................................ 946 Package Dimensions ......................................................................................................... 947 Main Revisions for This Edition..........................................................................949 Index ....................................................................................................................959 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxi of xlii Page xxii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Figures Section 1 Overview Figure 1.1 Block Diagram.......................................................................................................... 6 Figure 1.2 Pin Assignments of SH7146 ..................................................................................... 7 Figure 1.3 Pin Assignments of SH7149 (LQFP Version) .......................................................... 8 Section 2 CPU Figure 2.1 CPU Internal Register Configuration...................................................................... 16 Figure 2.2 Register Data Format .............................................................................................. 20 Figure 2.3 Memory Data Format.............................................................................................. 20 Figure 2.4 Transitions between Processing States ................................................................... 44 Section 3 MCU Operating Modes Figure 3.1 Address Map for Each Operating Mode in SH7146 ............................................... 50 Figure 3.2 Address Map for Each Operating Mode in SH7149 ............................................... 51 Figure 3.3 Reset Input Timing when Changing Operating Mode ............................................ 52 Section 4 Clock Pulse Generator (CPG) Figure 4.1 Block Diagram of Clock Pulse Generator............................................................... 54 Figure 4.2 Connection of Crystal Resonator (Example) .......................................................... 68 Figure 4.3 Crystal Resonator Equivalent Circuit ..................................................................... 68 Figure 4.4 Example of External Clock Connection.................................................................. 69 Figure 4.5 Cautions for Oscillator Circuit Board Design ......................................................... 71 Figure 4.6 Recommended External Circuitry around PLL....................................................... 72 Section 6 Interrupt Controller (INTC) Figure 6.1 Block Diagram of INTC ......................................................................................... 92 Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control ............................................ 105 Figure 6.3 Interrupt Sequence Flowchart ............................................................................... 111 Figure 6.4 Stack after Interrupt Exception Handling ............................................................. 112 Figure 6.5 IRQ Interrupt Control Block Diagram .................................................................. 114 Figure 6.6 On-Chip Module Interrupt Control Block Diagram.............................................. 115 Section 7 User Break Controller (UBC) Figure 7.1 Block Diagram of UBC ........................................................................................ 118 Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC......................................................................................... 154 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxiii of xlii Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Figure 8.11 Figure 8.12 Figure 8.13 Figure 8.14 Figure 8.15 Figure 8.16 Page xxiv of xlii Transfer Information on Data Area....................................................................... 167 Correspondence between DTC Vector Address and Transfer Information .......... 167 Flowchart of DTC Operation ................................................................................ 171 Transfer Information Read Skip Timing (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 States) ............................... 175 Memory Map in Normal Transfer Mode .............................................................. 177 Memory Map in Repeat Transfer Mode (When Transfer Source Is Specified as Repeat Area)........................................... 178 Memory Map in Block Transfer Mode (When Transfer Destination Is Specified as Block Area) ..................................... 180 Operation of Chain Transfer ................................................................................. 181 Example of DTC Operation Timing: Normal Transfer Mode or Repeat Transfer Mode (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)........................................................ 182 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2 (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)........................................................ 182 Example of DTC Operation Timing: Chain Transfer (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) ........................................................................................................... 183 Example of DTC Operation Timing: Normal or Repeat Transfer in Short Address Mode (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)........................................................ 183 Example of DTC Operation Timing: Normal or Repeat Transfer with DTPR = 1 (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)........................................................ 184 Example of DTC Operation Timing: Normal or Repeat Transfer (Activated by IRQ; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles).............................................................................................. 184 Example of DTC Operation Timing: Conflict of Two Activation Requests in Normal Transfer Mode (Activated by On-Chip Peripheral Module; I: B: P = 1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)............................. 189 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Figure 8.17 Figure 8.18 Figure 8.19 Example of DTC Activation in Accordance with Priority .................................... 190 Activation of DTC by Interrupt ............................................................................ 191 Chain Transfer when Counter = 0......................................................................... 193 Section 9 Bus State Controller (BSC) Figure 9.1 Block Diagram of BSC ......................................................................................... 198 Figure 9.2 Normal Space Basic Access Timing (Access Wait 0) .......................................... 216 Figure 9.3 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 0 (Access Wait = 0, Cycle Wait = 0) .............................. 217 Figure 9.4 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 1 (Access Wait = 0, Cycle Wait = 0) .............................. 218 Figure 9.5 Example of 16-Bit Data-Width SRAM Connection ............................................. 219 Figure 9.6 Example of 8-Bit Data-Width SRAM Connection ............................................... 219 Figure 9.7 Wait Timing for Normal Space Access (Software Wait Only)............................. 220 Figure 9.8 Wait State Timing for Normal Space Access (Wait State Insertion Using WAIT Signal)........................................................... 221 Figure 9.9 CSn Assert Period Extension ................................................................................ 222 Figure 9.10 Bus Arbitration When DTC Activation Request Occur during External Space Access from CPU.................................................................................................. 227 Figure 9.11 Bus Arbitration Timing......................................................................................... 229 Figure 9.12 Timing of Write Access to On-Chip Peripheral I/O Registers When I:B:P = 4:2:2......................................................................................... 232 Figure 9.13 Timing of Read Access to On-Chip Peripheral I/O Registers When I:B:P = 4:2:1......................................................................................... 232 Figure 9.14 Timing of Write Access to Word Data in External Memory When I:B = 2:1 and External Bus Width is 8 Bits ............................................ 234 Figure 9.15 Timing of Read Access with Condition I:B = 4:1 and External Bus Width Data Width ........................................................................ 235 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.1 Block Diagram of MTU2...................................................................................... 242 Figure 10.2 Complementary PWM Mode Output Level Example........................................... 309 Figure 10.3 PWM Output Level Setting Procedure in Buffer Operation ................................. 314 Figure 10.4 Example of Counter Operation Setting Procedure................................................ 327 Figure 10.5 Free-Running Counter Operation.......................................................................... 328 Figure 10.6 Periodic Counter Operation .................................................................................. 329 Figure 10.7 Example of Setting Procedure for Waveform Output by Compare Match ........... 329 Figure 10.8 Example of 0 Output/1 Output Operation............................................................. 330 Figure 10.9 Example of Toggle Output Operation................................................................... 330 Figure 10.10 Example of Input Capture Operation Setting Procedure....................................... 331 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxv of xlii Figure 10.11 Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Page xxvi of xlii Example of Input Capture Operation .................................................................... 332 Example of Synchronous Operation Setting Procedure........................................ 333 Example of Synchronous Operation ..................................................................... 334 Compare Match Buffer Operation ........................................................................ 335 Input Capture Buffer Operation ............................................................................ 336 Example of Buffer Operation Setting Procedure .................................................. 336 Example of Buffer Operation (1).......................................................................... 337 Example of Buffer Operation (2).......................................................................... 338 Example of Buffer Operation When TCNT_0 Clearing Is Selected for TGRC_0 to TGRA_0 Transfer Timing ........................................................... 339 Cascaded Operation Setting Procedure................................................................. 340 Cascaded Operation Example (a).......................................................................... 341 Cascaded Operation Example (b) ......................................................................... 341 Cascaded Operation Example (c).......................................................................... 342 Cascaded Operation Example (d) ......................................................................... 343 Example of PWM Mode Setting Procedure.......................................................... 346 Example of PWM Mode Operation (1)................................................................. 347 Example of PWM Mode Operation (2)................................................................. 347 Example of PWM Mode Operation (3)................................................................. 348 Example of Phase Counting Mode Setting Procedure .......................................... 349 Example of Phase Counting Mode 1 Operation.................................................... 350 Example of Phase Counting Mode 2 Operation.................................................... 351 Example of Phase Counting Mode 3 Operation.................................................... 352 Example of Phase Counting Mode 4 Operation.................................................... 353 Phase Counting Mode Application Example ........................................................ 355 Procedure for Selecting Reset-Synchronized PWM Mode ................................... 357 Reset-Synchronized PWM Mode Operation Example (When TOCR's OLSN = 1 and OLSP = 1) .......................................................... 358 Block Diagram of Channels 3 and 4 in Complementary PWM Mode.................. 361 Example of Complementary PWM Mode Setting Procedure ............................... 362 Complementary PWM Mode Counter Operation ................................................. 363 Example of Complementary PWM Mode Operation............................................ 365 Example of Operation without Dead Time ........................................................... 368 Example of PWM Cycle Updating ....................................................................... 369 Example of Data Update in Complementary PWM Mode ................................... 371 Example of Initial Output in Complementary PWM Mode (1) ............................ 372 Example of Initial Output in Complementary PWM Mode (2) ............................ 373 Example of Complementary PWM Mode Waveform Output (1)......................... 375 Example of Complementary PWM Mode Waveform Output (2)......................... 375 Example of Complementary PWM Mode Waveform Output (3)......................... 376 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 Figure 10.54 Figure 10.55 Figure 10.56 Figure 10.57 Figure 10.58 Figure 10.59 Figure 10.60 Figure 10.61 Figure 10.62 Figure 10.63 Figure 10.64 Figure 10.65 Figure 10.66 Figure 10.67 Figure 10.68 Figure 10.69 Figure 10.70 Figure 10.71 Figure 10.72 Figure 10.73 Figure 10.74 Example of Complementary PWM Mode 0% and 100% Waveform Output (1).. 376 Example of Complementary PWM Mode 0% and 100% Waveform Output (2).. 377 Example of Complementary PWM Mode 0% and 100% Waveform Output (3).. 377 Example of Complementary PWM Mode 0% and 100% Waveform Output (4).. 378 Example of Complementary PWM Mode 0% and 100% Waveform Output (5).. 378 Example of Toggle Output Waveform Synchronized with PWM Output ............ 379 Counter Clearing Synchronized with Another Channel........................................ 380 Timing for Synchronous Counter Clearing........................................................... 382 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode ............................................... 383 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 10.56; Bit WRE of TWCR in MTU2 Is 1)......................... 384 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56; Bit WRE of TWCR in MTU2 Is 1)......................... 384 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 10.56; Bit WRE of TWCR Is 1)......................................... 385 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56; Bit WRE of TWCR Is 1)....................................... 386 MTU2-MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC Bit in TWCR ........................................................................................... 387 Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing................................................................................................... 388 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) ........................................................................................... 389 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) ........................................................................................... 390 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) ........................................................................................... 391 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) .............. 392 Example of Counter Clearing Operation by TGRA_3 Compare Match ............... 393 Example of Output Phase Switching by External Input (1) .................................. 394 Example of Output Phase Switching by External Input (2) .................................. 395 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) . 395 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) . 396 Example of Interrupt Skipping Operation Setting Procedure ............................... 397 Periods during which Interrupt Skipping Count Can be Changed ........................ 398 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxvii of xlii Figure 10.75 Example of Interrupt Skipping Operation............................................................. 398 Figure 10.76 Example of Operation when Buffer Transfer Is Suppressed (BTE1 = 0 and BTE0 = 1) .................................................................................... 400 Figure 10.77 Example of Operation when Buffer Transfer Is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) .............................................. 401 Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period............................................................................ 402 Figure 10.79 Example of Procedure for Specifying A/D Converter Start Request Delaying Function .......................................................................... 404 Figure 10.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation.... 405 Figure 10.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping............................................................................. 406 Figure 10.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping............................................................................. 407 Figure 10.83 Example of Synchronous Counter Start Setting Procedure .................................. 408 Figure 10.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:1)........................................... 409 Figure 10.84 (2) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:2)........................................... 410 Figure 10.84 (3) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:3)........................................... 410 Figure 10.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:4)........................................... 411 Figure 10.85 Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting Source ........................................................... 412 Figure 10.86 (1) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (1) ............................................................................................. 413 Figure 10.86 (2) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (2).......................................................................................................... 413 Figure 10.87 Example of External Pulse Width Measurement Setting Procedure..................... 414 Figure 10.88 Example of External Pulse Width Measurement (Measuring High Pulse Width)414 Figure 10.89 Delay in Dead Time in Complementary PWM Operation.................................... 415 Figure 10.90 Example of Dead Time Compensation Setting Procedure.................................... 416 Figure 10.91 Example of Motor Control Circuit Configuration ................................................ 416 Figure 10.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation .... 417 Figure 10.93 Count Timing in Internal Clock Operation (Channels 0 to 4)............................... 423 Figure 10.94 Count Timing in Internal Clock Operation (Channel 5) ....................................... 423 Figure 10.95 Count Timing in External Clock Operation (Channels 0 to 4) ............................. 423 Figure 10.96 Count Timing in External Clock Operation (Phase Counting Mode) ................... 424 Figure 10.97 Output Compare Output Timing (Normal Mode/PWM Mode) ............................ 424 Page xxviii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Figure 10.98 Output Compare Output Timing (Complementary PWM Mode/ Reset Synchronous PWM Mode).......................................................................... 425 Figure 10.99 Input Capture Input Signal Timing ....................................................................... 425 Figure 10.100 Counter Clear Timing (Compare Match) (Channels 0 to 4) ................................. 426 Figure 10.101 Counter Clear Timing (Compare Match) (Channel 5) .......................................... 426 Figure 10.102 Counter Clear Timing (Input Capture) (Channels 0 to 5) ..................................... 427 Figure 10.103 Buffer Operation Timing (Compare Match) ......................................................... 427 Figure 10.104 Buffer Operation Timing (Input Capture)............................................................. 427 Figure 10.105 Buffer Transfer Timing (when TCNT Cleared).................................................... 428 Figure 10.106 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) .... 428 Figure 10.107 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) .............................................................................................. 429 Figure 10.108 Transfer Timing from Temporary Register to Compare Register......................... 429 Figure 10.109 TGI Interrupt Timing (Compare Match) (Channels 0 to 4) .................................. 430 Figure 10.110 TGI Interrupt Timing (Compare Match) (Channel 5)........................................... 430 Figure 10.111 TGI Interrupt Timing (Input Capture) (Channels 0 to 4) ...................................... 431 Figure 10.112 TGI Interrupt Timing (Input Capture) (Channel 5)............................................... 431 Figure 10.113 TCIV Interrupt Setting Timing ............................................................................. 432 Figure 10.114 TCIU Interrupt Setting Timing ............................................................................. 432 Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4) ................................. 433 Figure 10.116 Timing for Status Flag Clearing by CPU (Channel 5) .......................................... 433 Figure 10.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4) ............... 434 Figure 10.118 Timing for Status Flag Clearing by DTC Activation (Channel 5) ........................ 434 Figure 10.119 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode................ 435 Figure 10.120 Contention between TCNT Write and Clear Operations ...................................... 436 Figure 10.121 Contention between TCNT Write and Increment Operations............................... 437 Figure 10.122 Contention between TGR Write and Compare Match .......................................... 438 Figure 10.123 Contention between Buffer Register Write and Compare Match ......................... 439 Figure 10.124 Contention between Buffer Register Write and TCNT Clear ............................... 440 Figure 10.125 Contention between TGR Read and Input Capture (Channels 0 to 4) .................. 441 Figure 10.126 Contention between TGR Read and Input Capture (Channel 5)........................... 441 Figure 10.127 Contention between TGR Write and Input Capture (Channels 0 to 4) ................. 442 Figure 10.128 Contention between TGR Write and Input Capture (Channel 5) .......................... 442 Figure 10.129 Contention between Buffer Register Write and Input Capture ............................. 443 Figure 10.130 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection...................................................................................... 444 Figure 10.131 Counter Value during Complementary PWM Mode Stop .................................... 445 Figure 10.132 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode........................................................................................................... 446 Figure 10.133 Reset Synchronous PWM Mode Overflow Flag................................................... 447 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxix of xlii Figure 10.134 Figure 10.135 Figure 10.136 Figure 10.137 Figure 10.138 Figure 10.139 Figure 10.140 Figure 10.141 Figure 10.142 Figure 10.143 Figure 10.144 Figure 10.145 Figure 10.146 Figure 10.147 Figure 10.148 Figure 10.149 Figure 10.150 Figure 10.151 Figure 10.152 Figure 10.153 Figure 10.154 Figure 10.155 Figure 10.156 Figure 10.157 Figure 10.158 Figure 10.159 Figure 10.160 Figure 10.161 Figure 10.162 Page xxx of xlii Contention between Overflow and Counter Clearing ........................................... 448 Contention between TCNT Write and Overflow .................................................. 449 Condition (1) Synchronous Clearing Example ..................................................... 451 Condition (2) Synchronous Clearing Example ..................................................... 452 Error Occurrence in Normal Mode, Recovery in Normal Mode .......................... 456 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 .......................... 457 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 .......................... 458 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode ............. 459 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode .......................................................................................................... 460 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode .......................................................................................................... 461 Error Occurrence in PWM Mode 1, Recovery in Normal Mode .......................... 462 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1.......................... 463 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2.......................... 464 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode ............. 465 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode .......................................................................................................... 466 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode .......................................................................................................... 467 Error Occurrence in PWM Mode 2, Recovery in Normal Mode .......................... 468 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1.......................... 469 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2.......................... 470 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode ............. 471 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode ............. 472 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 ............. 473 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 ............. 474 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode....................................................................................... 475 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode.................................................................................................... 476 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 ................................................................................................... 477 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode............................................................................ 478 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode............................................................................ 479 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode ..................................................................... 480 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Figure 10.163 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode.................................................................................................... 481 Figure 10.164 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 ................................................................................................... 482 Figure 10.165 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode............................................................................ 483 Figure 10.166 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode ..................................................................... 484 Section 12 Port Output Enable (POE) Figure 12.1 Block Diagram of POE ......................................................................................... 494 Figure 12.2 Falling Edge Detection ......................................................................................... 517 Figure 12.3 Low-Level Detection Operation ........................................................................... 518 Figure 12.4 Output-Level Compare Operation ........................................................................ 518 Figure 12.5 Pin State When a Power-On Reset Is Issued from the Watchdog Timer .............. 521 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Watchdog Timer (WDT) Block Diagram of WDT........................................................................................ 524 Writing to WTCNT and WTCSR ......................................................................... 529 Operation in Watchdog Timer Mode (When WTCNT Count Clock Is Specified to P/32 by CKS2 to CKS0) ............. 531 Section 14 Serial Communication Interface (SCI) Figure 14.1 Block Diagram of SCI .......................................................................................... 534 Figure 14.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits).......................................................... 566 Figure 14.3 Sample Flowchart for SCI Initialization ............................................................... 569 Figure 14.4 Sample Flowchart for Transmitting Serial Data ................................................... 570 Figure 14.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)......................................................................... 572 Figure 14.6 Sample Flowchart for Receiving Serial Data (1) .................................................. 573 Figure 14.6 Sample Flowchart for Receiving Serial Data (2) .................................................. 574 Figure 14.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit)................ 576 Figure 14.8 Data Format in Clock Synchronous Communication ........................................... 576 Figure 14.9 Sample Flowchart for SCI Initialization ............................................................... 578 Figure 14.10 Sample Flowchart for Transmitting Serial Data ................................................... 579 Figure 14.11 Example of SCI Transmit Operation..................................................................... 580 Figure 14.12 Sample Flowchart for Receiving Serial Data (1) .................................................. 581 Figure 14.12 Sample Flowchart for Receiving Serial Data (2) .................................................. 582 Figure 14.13 Example of SCI Receive Operation ...................................................................... 583 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxxi of xlii Figure 14.14 Sample Flowchart for Transmitting/Receiving Serial Data .................................. 584 Figure 14.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A).......................................... 586 Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ....................................... 587 Figure 14.17 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 588 Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... 589 Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... 590 Figure 14.19 SCKIO Bit, SCKDT Bit, and SCK Pin ................................................................. 592 Figure 14.20 SPBIO Bit, SPBDT Bit, and TXD Pin.................................................................. 593 Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode...................................... 596 Figure 14.22 Example of Clock Synchronous Transfer Using DTC.......................................... 597 Section 15 A/D Converter (ADC) Figure 15.1 Block Diagram of A/D Converter (for One Module)............................................ 600 Figure 15.2 A/D Conversion Timing ....................................................................................... 618 Figure 15.3 External Trigger Input Timing.............................................................................. 620 Figure 15.4 Example of 2-Channel Scanning .......................................................................... 621 Figure 15.5 Definitions of A/D Conversion Accuracy............................................................. 624 Figure 15.6 Definitions of A/D Conversion Accuracy............................................................. 625 Figure 15.7 Example of Analog Input Circuit.......................................................................... 627 Figure 15.8 Example of Analog Input Protection Circuit ........................................................ 628 Section 16 Compare Match Timer (CMT) Figure 16.1 Block Diagram of CMT........................................................................................ 629 Figure 16.2 Counter Operation ................................................................................................ 634 Figure 16.3 Count Timing........................................................................................................ 634 Figure 16.4 Timing of CMF Setting......................................................................................... 636 Figure 16.5 Conflict between Write and Compare-Match Processes of CMCNT ................... 637 Figure 16.6 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 638 Figure 16.7 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 639 Section 18 I/O Ports Figure 18.1 Port A (SH7146) ................................................................................................... 710 Figure 18.2 Port A (SH7149) ................................................................................................... 711 Figure 18.3 Port B (SH7146) ................................................................................................... 715 Figure 18.4 Port B (SH7149) ................................................................................................... 715 Figure 18.5 Port D.................................................................................................................... 721 Figure 18.6 Port E (SH7146) ................................................................................................... 725 Figure 18.7 Port E (SH7149) ................................................................................................... 726 Page xxxii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Figure 18.8 Port F .................................................................................................................... 732 Section 19 Flash Memory Figure 19.1 Block Diagram of Flash Memory ......................................................................... 737 Figure 19.2 Mode Transition of Flash Memory ....................................................................... 738 Figure 19.3 Flash Memory Configuration................................................................................ 741 Figure 19.4 Block Division of User MAT................................................................................ 742 Figure 19.5 Overview of User Procedure Program .................................................................. 743 Figure 19.6 System Configuration in Boot Mode .................................................................... 772 Figure 19.7 Automatic Adjustment Operation of SCI Bit Rate................................................ 773 Figure 19.8 State Transitions in Boot Mode ............................................................................ 775 Figure 19.9 Programming/Erasing Overview Flow ................................................................. 776 Figure 19.10 RAM Map after Download ................................................................................... 777 Figure 19.11 Programming Procedure ....................................................................................... 778 Figure 19.12 Erasing Procedure ................................................................................................. 783 Figure 19.13 Procedure for Programming User MAT in User Boot Mode................................ 786 Figure 19.14 Procedure for Erasing User MAT in User Boot Mode.......................................... 788 Figure 19.15 Transitions to and from Error Protection State ..................................................... 792 Figure 19.16 Emulation of Flash Memory in RAM ................................................................... 793 Figure 19.17 Example of Overlapped RAM Operation ............................................................. 794 Figure 19.18 Programming of Tuned Data ................................................................................ 795 Figure 19.19 Switching between User MAT and User Boot MAT............................................ 797 Figure 19.20 Timing of Contention between SCO Download Request and Interrupt Request............................................................................................ 798 Figure 19.21 Flow of Processing by the Boot Program ............................................................. 803 Figure 19.22 Sequence of Bit-Rate Matching ............................................................................ 804 Figure 19.23 Formats in the Communications Protocol............................................................. 805 Figure 19.24 Sequence of New Bit Rate Selection .................................................................... 817 Figure 19.25 Sequence of Programming.................................................................................... 821 Figure 19.26 Sequence of Erasure.............................................................................................. 825 Section 20 Masked ROM Figure 20.1 Masked ROM Block Diagram .............................................................................. 841 Section 21 RAM Figure 21.1 On-chip RAM Addresses...................................................................................... 843 Section 24 Electrical Characteristics Figure 24.1 EXTAL Clock Input Timing................................................................................. 911 Figure 24.2 CK Clock Output Timing...................................................................................... 912 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxxiii of xlii Figure 24.3 Figure 24.4 Figure 24.5 Figure 24.16 Figure 24.17 Figure 24.18 Figure 24.19 Figure 24.20 Figure 24.21 Figure 24.22 Figure 24.23 Figure 24.24 Figure 24.25 Figure 24.26 Figure 24.27 Power-On Oscillation Settling Timing ................................................................. 912 Oscillation Settling Timing on Return from Standby (Return by Reset) .............. 912 Oscillation Settling Timing on Return from Standby (Return by NMI or IRQ) ....................................................................................... 913 Reset Input Timing ............................................................................................... 915 Interrupt Signal Input Timing ............................................................................... 915 Interrupt Signal Output Timing ............................................................................ 916 Bus Release Timing .............................................................................................. 916 Pin Driving Timing in Standby Mode .................................................................. 916 Basic Bus Timing for Normal Space (No Wait) ................................................... 918 Basic Bus Timing for Normal Space (One Software Wait Cycle)........................ 919 Basic Bus Timing for Normal Space (One External Wait Cycle)......................... 920 Basic Bus Timing for Normal Space (One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle) ................................... 921 CS Extended Bus Cycle for Normal Space (SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle)............................................................ 922 MTU2 Input/Output Timing ................................................................................. 923 MTU2 Clock Input Timing................................................................................... 923 MTU2S Input/Output Timing ............................................................................... 924 I/O Port Input/Output Timing ............................................................................... 925 WDT Timing ........................................................................................................ 926 Input Clock Timing............................................................................................... 927 SCI Input/Output Timing...................................................................................... 928 POE Input Timing................................................................................................. 929 UBC Trigger Timing ............................................................................................ 930 External Trigger Input Timing.............................................................................. 931 Output Load Circuit .............................................................................................. 932 Connection of VCL Capacitor .............................................................................. 935 Appendix Figure E.1 Figure E.2 FP-80WV.............................................................................................................. 947 FP-100UV............................................................................................................. 948 Figure 24.6 Figure 24.7 Figure 24.8 Figure 24.9 Figure 24.10 Figure 24.11 Figure 24.12 Figure 24.13 Figure 24.14 Figure 24.15 Page xxxiv of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Tables Section 1 Overview Table 1.1 Features ....................................................................................................................... 2 Table 1.2 Pin Functions............................................................................................................... 9 Section 2 CPU Table 2.1 Initial Values of Registers ......................................................................................... 19 Table 2.2 Word Data Sign Extension ........................................................................................ 21 Table 2.3 Delayed Branch Instructions ..................................................................................... 22 Table 2.4 T Bit .......................................................................................................................... 22 Table 2.5 Access to Immediate Data......................................................................................... 23 Table 2.6 Access to Absolute Address ...................................................................................... 23 Table 2.7 Access with Displacement......................................................................................... 24 Table 2.8 Addressing Modes and Effective Addresses ............................................................. 24 Table 2.9 Instruction Formats ................................................................................................... 28 Table 2.10 Instruction Types....................................................................................................... 31 Table 2.11 Data Transfer Instructions ......................................................................................... 35 Table 2.12 Arithmetic Operation Instructions............................................................................. 37 Table 2.13 Logic Operation Instructions..................................................................................... 39 Table 2.14 Shift Instructions ....................................................................................................... 40 Table 2.15 Branch Instructions ................................................................................................... 41 Table 2.16 System Control Instructions ...................................................................................... 42 Section 3 MCU Operating Modes Table 3.1 Selection of Operating Modes................................................................................... 47 Table 3.2 Pin Configuration ...................................................................................................... 48 Section 4 Clock Pulse Generator (CPG) Table 4.1 Operating Clock for Each Module ............................................................................ 56 Table 4.2 Pin Configuration ...................................................................................................... 57 Table 4.3 Clock Operating Mode .............................................................................................. 58 Table 4.4 Frequency Division Ratios Specifiable with FRQCR ............................................... 59 Table 4.5 Register Configuration .............................................................................................. 63 Table 4.6 Damping Resistance Values (Reference Values) ...................................................... 68 Table 4.7 Crystal Resonator Characteristics ............................................................................. 69 Section 5 Exception Handling Table 5.1 Types of Exceptions and Priority .............................................................................. 73 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxxv of xlii Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 5.9 Table 5.10 Table 5.11 Timing for Exception Detection and Start of Exception Handling ........................... 74 Vector Numbers and Vector Table Address Offsets ................................................. 75 Calculating Exception Handling Vector Table Addresses ........................................ 76 Reset Status ............................................................................................................... 77 Bus Cycles and Address Errors ................................................................................. 79 Interrupt Sources ....................................................................................................... 81 Interrupt Priority........................................................................................................ 82 Types of Exceptions Triggered by Instructions......................................................... 83 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions................. 85 Stack Status after Exception Handling Ends ............................................................. 86 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration ...................................................................................................... 93 Table 6.2 Register Configuration .............................................................................................. 94 Table 6.3 Interrupt Exception Handling Vectors and Priorities .............................................. 106 Table 6.4 Interrupt Response Time ......................................................................................... 113 Section 7 User Break Controller (UBC) Table 7.1 Pin Configuration .................................................................................................... 119 Table 7.2 Register Configuration ............................................................................................ 120 Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions ............. 142 Section 8 Data Transfer Controller (DTC) Table 8.1 Register Configuration ............................................................................................ 155 Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................. 168 Table 8.3 DTC Transfer Modes .............................................................................................. 170 Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included)........................... 172 Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers.................................................................................................... 176 Table 8.6 Register Function in Normal Transfer Mode .......................................................... 176 Table 8.7 Register Function in Repeat Transfer Mode ........................................................... 178 Table 8.8 Register Function in Block Transfer Mode............................................................. 179 Table 8.9 DTC Execution Status............................................................................................. 185 Table 8.10 Number of Cycles Required for Each Execution State ........................................... 186 Table 8.11 DTC Bus Release Timing ....................................................................................... 188 Section 9 Bus State Controller (BSC) Table 9.1 Pin Configuration .................................................................................................... 199 Table 9.2 Address Map (Single-Chip Mode) .......................................................................... 200 Table 9.3 Address Map (SH7149 in On-Chip ROM-Enabled Mode) ..................................... 201 Page xxxvi of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Table 9.4 Table 9.5 Table 9.6 Table 9.7 Table 9.8 Table 9.10 Table 9.11 Address Map (SH7149 in On-Chip ROM-Disabled Mode) .................................... 202 Register Configuration ............................................................................................ 203 16-Bit External Device Access and Data Alignment .............................................. 214 8-Bit External Device Access and Data Alignment ................................................ 215 Minimum Number of Idle Cycles between CPU Access Cycles in Normal Space Interface....................................................................................... 224 Minimum Number of Idle Cycles between Access Cycles during DTC Transfer for the Normal Space Interface............................................. 225 Number of Cycles for Access to On-Chip Peripheral I/O Registers ....................... 231 Number of External Access Cycles......................................................................... 233 Section 10 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24 Table 10.25 Table 10.26 Table 10.27 Table 10.28 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2 Functions ..................................................................................................... 238 Pin Configuration .................................................................................................... 243 Register Configuration ............................................................................................ 244 CCLR0 to CCLR2 (Channels 0, 3, and 4)............................................................... 249 CCLR0 to CCLR2 (Channels 1 and 2).................................................................... 249 TPSC0 to TPSC2 (Channel 0)................................................................................. 250 TPSC0 to TPSC2 (Channel 1)................................................................................. 250 TPSC0 to TPSC2 (Channel 2)................................................................................. 251 TPSC0 to TPSC2 (Channels 3 and 4)...................................................................... 251 TPSC1 and TPSC0 (Channel 5) .............................................................................. 252 Setting of Operation Mode by Bits MD0 to MD3................................................... 254 TIORH_0 (Channel 0)............................................................................................. 257 TIORL_0 (Channel 0) ............................................................................................. 258 TIOR_1 (Channel 1)................................................................................................ 259 TIOR_2 (Channel 2)................................................................................................ 260 TIORH_3 (Channel 3)............................................................................................. 261 TIORL_3 (Channel 3) ............................................................................................. 262 TIORH_4 (Channel 4)............................................................................................. 263 TIORL_4 (Channel 4) ............................................................................................. 264 TIORH_0 (Channel 0)............................................................................................. 265 TIORL_0 (Channel 0) ............................................................................................. 266 TIOR_1 (Channel 1)................................................................................................ 267 TIOR_2 (Channel 2)................................................................................................ 268 TIORH_3 (Channel 3)............................................................................................. 269 TIORL_3 (Channel 3) ............................................................................................. 270 TIORH_4 (Channel 4)............................................................................................. 271 TIORL_4 (Channel 4) ............................................................................................. 272 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) ................................................. 273 Table 9.9 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxxvii of xlii Table 10.29 Table 10.30 Table 10.31 Table 10.32 Table 10.33 Table 10.34 Table 10.35 Table 10.36 Table 10.37 Table 10.38 Table 10.39 Table 10.40 Table 10.41 Table 10.42 Table 10.43 Table 10.44 Table 10.45 Table 10.46 Table 10.47 Table 10.48 Table 10.49 Table 10.50 Table 10.51 Table 10.52 Table 10.53 Table 10.54 Table 10.55 Table 10.56 Table 10.57 Table 10.58 Table 10.59 Setting of Transfer Timing by BF1 and BF0 Bits ................................................... 295 Output Level Select Function.................................................................................. 308 Output Level Select Function.................................................................................. 309 Setting of Bits BF1 and BF0 ................................................................................... 311 TIOC4D Output Level Select Function................................................................... 311 TIOC4B Output Level Select Function................................................................... 312 TIOC4C Output Level Select Function................................................................... 312 TIOC4A Output Level Select Function................................................................... 312 TIOC3D Output Level Select Function................................................................... 312 TIOC4B Output Level Select Function................................................................... 313 Output level Select Function ................................................................................... 316 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0........................ 319 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0........................ 319 Setting of Bits BTE1 and BTE0 .............................................................................. 322 Register Combinations in Buffer Operation............................................................ 335 Cascaded Combinations .......................................................................................... 339 TICCR Setting and Input Capture Input Pins.......................................................... 340 PWM Output Registers and Output Pins................................................................. 345 Phase Counting Mode Clock Input Pins.................................................................. 349 Up/Down-Count Conditions in Phase Counting Mode 1 ........................................ 350 Up/Down-Count Conditions in Phase Counting Mode 2 ........................................ 351 Up/Down-Count Conditions in Phase Counting Mode 3 ........................................ 352 Up/Down-Count Conditions in Phase Counting Mode 4 ........................................ 353 Output Pins for Reset-Synchronized PWM Mode .................................................. 356 Register Settings for Reset-Synchronized PWM Mode .......................................... 356 Output Pins for Complementary PWM Mode......................................................... 359 Register Settings for Complementary PWM Mode................................................. 360 Registers and Counters Requiring Initialization...................................................... 366 MTU2 Interrupts ..................................................................................................... 419 Interrupt Sources and A/D Converter Start Request Signals................................... 422 Mode Transition Combinations............................................................................... 454 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Table 11.1 MTU2S Functions................................................................................................... 486 Table 11.2 Pin Configuration .................................................................................................... 489 Table 11.3 Register Configuration ............................................................................................ 490 Section 12 Port Output Enable (POE) Table 12.1 Pin Configuration .................................................................................................... 495 Table 12.2 Pin Combinations .................................................................................................... 496 Page xxxviii of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Table 12.3 Table 12.4 Table 12.5 Register Configuration ............................................................................................ 497 Target Pins and Conditions for High-Impedance Control....................................... 516 Interrupt Sources and Conditions ............................................................................ 520 Section 13 Watchdog Timer (WDT) Table 13.1 WDT Pin Configuration .......................................................................................... 525 Table 13.2 Register Configuration ............................................................................................ 526 Table 13.3 Interrupt Source....................................................................................................... 532 Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Table 14.16 Table 14.17 Table 14.18 Serial Communication Interface (SCI) Pin Configuration .................................................................................................... 535 Register Configuration ............................................................................................ 536 SCSMR Settings...................................................................................................... 554 Bit Rates and SCBRR Settings in Asynchronous Mode (1).................................... 555 Bit Rates and SCBRR Settings in Asynchronous Mode (2).................................... 556 Bit Rates and SCBRR Settings in Asynchronous Mode (3).................................... 557 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1)............................ 558 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2)............................ 559 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3)............................ 560 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................. 561 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ................. 562 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) ......... 563 SCSMR Settings and SCI Communication Formats ............................................... 565 SCSMR and SCSCR Settings and SCI Clock Source Selection ............................. 565 Serial Transfer Formats (Asynchronous Mode) ...................................................... 567 Receive Errors and Error Conditions ...................................................................... 575 SCI Interrupt Sources .............................................................................................. 591 SCSSR Status Flag Values and Transfer of Received Data .................................... 594 Section 15 A/D Converter (ADC) Table 15.1 Pin Configuration .................................................................................................... 601 Table 15.2 Register Configuration ............................................................................................ 602 Table 15.3 Channel Select List.................................................................................................. 608 Table 15.4 A/D Conversion Time (Single Mode) ..................................................................... 619 Table 15.5 A/D Conversion Time (Scan Mode)........................................................................ 619 Table 15.6 A/D Converter Interrupt Source .............................................................................. 622 Table 15.7 Analog Pin Specifications ....................................................................................... 628 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xxxix of xlii Section 16 Compare Match Timer (CMT) Table 16.1 Register Configuration ............................................................................................ 630 Table 16.2 Interrupt Source....................................................................................................... 635 Section 17 Table 17.1 Table 17.2 Table 17.3 Table 17.4 Table 17.5 Table 17.6 Table 17.7 Table 17.8 Table 17.9 Table 17.10 Table 17.11 Table 17.12 Table 17.13 Pin Function Controller (PFC) SH7146 Multiplexed Pins (Port A) ......................................................................... 641 SH7149 Multiplexed Pins (Port A) ......................................................................... 642 SH7146 Multiplexed Pins (Port B) ......................................................................... 642 SH7149 Multiplexed Pins (Port B) ......................................................................... 643 SH7149 Multiplexed Pins (Port D) ......................................................................... 643 SH7146 Multiplexed Pins (Port E).......................................................................... 644 SH7149 Multiplexed Pins (Port E).......................................................................... 645 Multiplexed Pins (Port F)........................................................................................ 646 SH7146 Pin Functions in Each Operating Mode .................................................... 647 SH7149 Pin Functions in Each Operating Mode (1)............................................... 650 SH7149 Pin Functions in Each Operating Mode (2)............................................... 654 Register Configuration ............................................................................................ 658 Transmit Forms of Input Functions Allocated to Multiple Pins.............................. 707 Section 18 Table 18.1 Table 18.2 Table 18.3 Table 18.4 Table 18.5 Table 18.6 Table 18.7 Table 18.8 Table 18.9 Table 18.10 I/O Ports Register Configuration ............................................................................................ 712 Port A Data Register L (PADRL) Read/Write Operations...................................... 713 Register Configuration ............................................................................................ 716 Port B Data Register (PBDR) Read/Write Operations............................................ 718 Register Configuration ............................................................................................ 722 Port D Data Register L (PDDRL) Read/Write Operations...................................... 723 Register Configuration ............................................................................................ 727 Port E Data Register (PEDR) Read/Write Operations ............................................ 730 Register Configuration ............................................................................................ 733 Port F Data Register L (PFDRL) Read/Write Operations....................................... 734 Section 19 Flash Memory Table 19.1 (1) Relationship between FWE and MD Pins and Operating Modes (SH7146)........ 739 Table 19.1 (2) Relationship between FWE and MD Pins and Operating Modes (SH7149)........ 739 Table 19.2 Comparison of Programming Modes ...................................................................... 740 Table 19.3 Pin Configuration .................................................................................................... 745 Table 19.4 (1) Register Configuration ........................................................................................ 746 Table 19.4 (2) Parameter Configuration...................................................................................... 746 Table 19.5 Register/Parameter and Target Mode...................................................................... 747 Page xl of xlii R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Table 19.6 Table 19.7 Table 19.8 Usable Parameters and Target Modes ..................................................................... 756 Overlapping of RAM Area and User MAT Area .................................................... 771 Peripheral Clock (P) Frequency that Can Automatically Adjust Bit Rate of This LSI..................................................................................... 773 Table 19.9 Hardware Protection................................................................................................ 790 Table 19.10 Software Protection ................................................................................................. 791 Table 19.11 Initiation Intervals of User Branch Processing........................................................ 800 Table 19.12 Initial User Branch Processing Time....................................................................... 800 Table 19.13 Inquiry and Selection Commands ........................................................................... 806 Table 19.14 Programming and Erasure Commands.................................................................... 820 Table 19.15 Status Codes ............................................................................................................ 831 Table 19.16 Error Codes ............................................................................................................. 832 Table 19.17 Executable MAT ..................................................................................................... 833 Table 19.18 (1) Usable Area for Programming in User Program Mode ..................................... 834 Table 19.18 (2) Usable Area for Erasure in User Program Mode ............................................... 835 Table 19.18 (3) Usable Area for Programming in User Boot Mode ........................................... 836 Table 19.18 (3) Usable Area for Programming in User Boot Mode (cont) ................................. 837 Table 19.18 (4) Usable Area for Erasure in User Boot Mode ..................................................... 838 Table 19.18 (4) Usable Area for Erasure in User Boot Mode (cont)........................................... 839 Section 22 Power-Down Modes Table 22.1 States of Power-Down Modes................................................................................. 846 Table 22.2 Pin Configuration .................................................................................................... 847 Table 22.3 Register Configuration ............................................................................................ 848 Section 24 Table 24.1 Table 24.2 Table 24.3 Table 24.4 Table 24.5 Table 24.6 Table 24.7 Table 24.8 Table 24.9 Table 24.10 Table 24.11 Table 24.12 Table 24.13 Table 24.14 Electrical Characteristics Absolute Maximum Ratings.................................................................................... 905 DC Characteristics................................................................................................... 906 Permitted Output Current Values ............................................................................ 909 Maximum Operating Frequency ............................................................................. 910 Clock Timing .......................................................................................................... 911 Control Signal Timing............................................................................................. 914 Bus Timing.............................................................................................................. 917 Multi Function Timer Pulse Unit 2 (MTU2) Timing .............................................. 923 Multi Function Timer Pulse Unit 2S (MTU2S) Timing.......................................... 924 I/O Port Timing ....................................................................................................... 925 Watchdog Timer (WDT) Timing ............................................................................ 926 Serial Communication Interface (SCI) Timing ....................................................... 927 Port Output Enable (POE) Timing .......................................................................... 929 UBC Trigger Timing............................................................................................... 930 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page xli of xlii Table 24.15 A/D Converter Timing ............................................................................................ 931 Table 24.16 A/D Converter Characteristics ................................................................................ 933 Table 24.17 Flash Memory Characteristics................................................................................. 934 Appendix Table A.1 Table A.2 Table B.1 TableC.1 Table C.1 Table D.1 Page xlii of xlii Pin States (SH7146) ................................................................................................ 937 Pin States (SH7149) ................................................................................................ 940 Processing of Unused Pins ...................................................................................... 943 Pin States of Bus Related Signals (1)...................................................................... 944 Pin States of Bus Related Signals (2)...................................................................... 945 Product Code Lineup............................................................................................... 946 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 1 Overview Section 1 Overview 1.1 Features of SH7146 and SH7149 This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, a data transfer controller (DTC), timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. TM There are two versions of on-chip ROM: F-ZTAT (Flexible Zero Turn Around Time)* that includes flash memory, and masked ROM. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board. The features of this LSI are listed in table 1.1. Note: * F-ZTAT TM is a trademark of Renesas Electronics Corp. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 1 of 964 SH7146 Group Section 1 Overview Table 1.1 Features Items Specification CPU * Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture * Instruction length: 16-bit fixed length for improved code efficiency * Load-store architecture (basic operations are executed between registers) * Sixteen 32-bit general registers * Five-stage pipeline * On-chip multiplier: Multiplication operations (32 bits x 32 bits 64 bits) executed in two to five cycles * C language-oriented 62 basic instructions Note: Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. For details, see section 5.8.4, Notes on Slot Illegal Instruction Exception Handling. Operating modes * Operating modes Single chip mode Extended ROM enabled mode (only in SH7149) Extended ROM disabled mode (only in SH7149) * Operating states Program execution state Exception handling state Bus release state (only in SH7149) * Power-down modes Sleep mode Software standby mode Deep software standby mode Module standby mode User break controller (UBC) Page 2 of 964 * Addresses, data values, type of access, and data size can all be set as break conditions * Supports a sequential break function * Two break channels * In the masked ROM version, only the L bus instruction fetch address break (two channels) can be set R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 1 Overview Items Specification On-chip ROM * 256 kbytes On-chip RAM * 8 kbytes Bus state controller (BSC) * Address space: A maximum 64 Mbytes for each of two areas (CS0 and CS1) (only in SH7149) * 8-bit external bus (only in SH7149) * 16-bit external bus (only in SH7149) * The following features settable for each area independently Bus size (8 or 16 bits) Number of access wait cycles Idle wait cycle insertion Supports SRAM * Outputs a chip select signal according to the target area * Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer. * Transfer mode selectable for each interrupt source (transfer mode is specified in memory) * Multiple data transfer enabled for one activation source * Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected. * Data transfer size can be specified as byte, word, or longword * The interrupt that activated the DTC can be issued to the CPU. A CPU interrupt can be requested after one data transfer completion. * A CPU interrupt can be requested after all specified data transfer completion. * Five external interrupt pins (NMI and IRQ3 to IRQ0) * On-chip peripheral interrupts: Priority level set for each module * Vector addresses: A vector address for each interrupt source * E10A emulator support Advanced user * debugger (AUD) (only in F-ZTAT version supporting full functions of E10A) E10A emulator support Data transfer controller (DTC) (only in F-ZTAT version) Interrupt controller (INTC) User debugging interface (H-UDI) (only in F-ZTAT version) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 3 of 964 SH7146 Group Section 1 Overview Items Specification Clock pulse generator (CPG) * Clock mode: Input clock can be selected from external input or crystal resonator * Five types of clocks generated: CPU clock: Maximum 80 MHz Bus clock: Maximum 40 MHz Peripheral clock: Maximum 40 MHz MTU2 clock: Maximum 40 MHz MTU2S clock: Maximum 80 MHz Watchdog timer (WDT) * On-chip one-channel watchdog timer * Interrupt generation is supported. Multi-function timer pulse unit 2 (MTU2) * Maximum 16 lines of pulse input/output and three lines of pulse input based on six channels of 16-bit timers * 21 output compare and input capture registers * A total of 21 independent comparators * Selection of eight counter input clocks * Input capture function * Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes * Synchronization of multiple counters * Complementary PWM output mode Non-overlapping waveforms output for 6-phase inverter control Automatic dead time setting 0% to 100% PWM duty cycle specifiable Output suppression A/D conversion delaying function Dead time compensation Interrupt skipping at crest or trough Page 4 of 964 * Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty cycle * Phase counting mode Two-phase encoder pulse counting available R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Items Section 1 Overview Specification Multi-function timer * pulse unit 2S (MTU2S) * Port output enable (POE) * Compare match timer * (CMT) * * Serial communication * interface (SCI) * A/D converter (ADC) I/O ports Packages Power supply voltage R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Subset of MTU2, including channels 3 to 5 Operating at 80 MHz max. High-impedance control of waveform output pins in MTU2 and MTU2S 16-bit counters Compare match interrupts can be generated Two channels Clock synchronous or asynchronous mode Three channels * 10 bits x 12 channels * Conversion request by external triggers, MTU2, or MTU2S * Three sample-and-hold function units (three channels can be sampled simultaneously) * 45 general input/output pins and 12 general input pins (SH7146) * 63 general input/output pins and 12 general input pins (SH7149) * Input or output can be selected for each bit * LQFP1414-80 (0.65 pitch) (SH7146) * LQFP1414-100 (0.5 pitch) (SH7149) * Vcc: 4.0 to 5.5 V * AVcc: 4.0 to 5.5 V Page 5 of 964 SH7146 Group Section 1 Overview 1.2 Block Diagram The block diagram of this LSI is shown in figure 1.1. SH2 CPU UBC AUD *2 L bus (I) ROM RAM Internal bus controller I bus (B) Peripheral bus controller BSC DTC *1 External bus Peripheral bus (P) I/O port (PFC) SCI CMT [Legend] ROM: On-chip ROM RAM: On-chip RAM UBC: User break controller AUD: Advanced user debugger H-UDI: User debugging interface INTC: Interrupt controller CPG: Clock pulse generator WDT: Watchdog timer CPU: Central processing unit BSC: Bus state controller H-UDI *1 INTC Powerdown mode control WDT DTC: PFC: MTU2: MTU2S: POE: SCI: CMT: ADC: CPG MTU2 MTU2S POE ADC Data transfer controller Pin function controller Multi-function timer pulse unit 2 Multi-function timer pulse unit 2 (subset) Port output enable Serial communication interface Compare match timer A/D converter Notes: 1. Only in F-ZTAT version. 2. Only in F-ZTAT version supporting full functions of E10A. Figure 1.1 Block Diagram Page 6 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Pin Assignments PLLVSS MD1 VSS(FWE*1) NMI VCC(ASEMD0*2) EXTAL XTAL WDTOVF RES PB4/IRQ2/POE4/TIC5US VCL PB5/IRQ3/POE5/TIC5U VCC PA0/POE0/RXD0 VSS PA1/POE1/TXD0 PA2/IRQ0/POE2/SCK0 PA3/IRQ1/RXD1 PA4/IRQ2/TXD1 PA5/IRQ3/SCK1 1.3 Section 1 Overview 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PB3/IRQ1/POE1/TIC5V PB2/IRQ0/POE0/TIC5VS AVSS PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 AVCC PF6/AN6 PF4/AN4 AVSS PF2/AN2 PF0/AN0 AVCC PB16/POE3 PB17/POE7 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LQFP-80 (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA6/UBCTRG/TCLKA/POE4 PA7/TCLKB/POE5/SCK2 PA8/TCLKC/POE6/RXD2 PA9/TCLKD/POE8/TXD2 PA10/RXD0 PA11/TXD0/ADTRG PA12/SCK0 VSS PA13/SCK1 VCC PA14/RXD1 PA15/TXD1 PB18/POE8 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 PE3/TIOC0D/SCK0 PE4/TIOC1A/RXD1 PE5/TIOC1B/TXD1 PE6/TIOC2A/SCK1 PE21/TIOC4DS/TRST*3 PE20/TIOC4CS/TMS*3 PE19/TIOC4BS/TDO*3 VCC PE18/TIOC4AS/TDI*3 VSS PE17/TIOC3DS/TCK*3 3 PE16/TIOC3BS/ASEBRKAK* /ASEBRK*3 PE15/TIOC4D/IRQOUT VCL PE14/TIOC4C PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D PE9/TIOC3B PE10/TIOC3C VSS PE8/TIOC3A VCC PE7/TIOC2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Notes: 1. Fixed to VSS in the masked ROM version, and used as the FWE input pin in the F-ZTAT version. 2. A pin for the E10A emulator. Fixed to VCC in the masked ROM version, and used as the ASEMD0 input pin in the F-ZTAT version. 3. This pin function is available only in the F-ZTAT version. (Not available in the masked ROM version.) Figure 1.2 Pin Assignments of SH7146 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 7 of 964 SH7146 Group PLLVSS PB5/A19/IRQ3/POE5/TIC5U VCC MD0 MD1 VSS(FWE*1) NMI VCC(ASEMD0*2) EXTAL XTAL WDTOVF RES PA0/A0/POE0/RXD0 PA1/A1/POE1/TXD0 VCL PA2/A2/IRQ0/POE2/SCK0 VCC PA3/A3/IRQ1/RXD1 VSS PA4/A4/IRQ2/TXD1 PA5/A5/IRQ3/SCK1 PA6/RD/UBCTRG/TCLKA/POE4 PA7/WRH/TCLKB/POE5/SCK2 PA8/WRL/TCLKC/POE6/RXD2 PA9/WAIT/TCLKD/POE8/TXD2 Section 1 Overview 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 LQFP-100 88 38 (Top view) 89 37 90 36 91 35 92 34 93 33 94 32 95 31 96 30 97 29 98 28 27 99 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PA10/A6/RXD0 PA11/A7/TXD0/ADTRG PA12/A8/SCK0 PA13/A9/SCK1 PA14/A10/RXD1 PA15/CK/TXD1 PD0/D0/RXD0 PD1/D1/TXD0 PD2/D2/SCK0 VSS PD3/D3/RXD1 VCC PD4/D4/IRQ0/TXD1 PD5/D5/IRQ1/SCK1 PD6/D6/IRQ2/RXD2 PD7/D7/IRQ3/TXD2 PD8/D8/SCK2/AUDATA0*4 PD9/D9/AUDATA1*4 PD10/D10/AUDATA2*4 PD11/D11/AUDATA3*4 PD12/D12 PD13/D13 PD14/D14/AUDCK*4 PD15/D15/AUDSYNC*4 PB18/POE8 PE19/RD/TIOC4BS/TDO*3 PE18/CS1/TIOC4AS/TDI*3 PE17/CS0/TIOC3DS/TCK*3 PE16/WAIT/TIOC3BS/ASEBRKAK*3/ASEBRK*3 VCC PE15/TIOC4D/IRQOUT VSS PE14/TIOC4C PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D VCL PE9/TIOC3B PE10/CS0/TIOC3C PE8/A15/TIOC3A PE7/A14/TIOC2B PE6/A13/TIOC2A/SCK1 PE5/A12/TIOC1B/TXD1 PE4/A11/TIOC1A/RXD1 PE3/TIOC0D/SCK0 PE2/TIOC0C/TXD0 VSS PE1/TIOC0B/RXD0 VCC PE0/TIOC0A PB4/A18/IRQ2/POE4/TIC5US PB3/A17/IRQ1/POE1/TIC5V PB2/A16/IRQ0/POE0/TIC5VS PB1/BREQ/TIC5W PB0/BACK/TIC5WS AVSS PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 AVCC PF6/AN6 PF4/AN4 AVSS PF2/AN2 PF0/AN0 AVCC PB16/POE3 PB17/POE7 PE21/WRL/TIOC4DS/TRST*3 PE20/WRH/TIOC4CS/TMS*3 Notes: 1. 2. 3. 4. Fixed to VSS in the masked ROM version, and used as the FWE input pin in the F-ZTAT version. A pin for the E10A emulator. Fixed to VCC in the masked ROM version, and used as the ASEMD0 input pin in the F-ZTAT version. This pin function is available only in the F-ZTAT version. (Not available in the masked ROM version.) This pin function is available only in F-ZTAT version supporting full functions of E10A. (Not available in the normal F-ZTAT version and the masked ROM version.) Figure 1.3 Pin Assignments of SH7149 (LQFP Version) Page 8 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 1.4 Section 1 Overview Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Classification Symbol I/O Name Function Power supply Vcc I Power supply Power supply pins. Connect all Vcc pins to the system. There will be no operation if any pins are open. Vss I Ground Ground pin. Connect all Vss pins to the system power supply (0V). There will be no operation if any pins are open. VCL O Power supply for External capacitance pins for internal power-down power supply. Connect internal powerthese pins to Vss via a 0.47 F down capacitor (placed close to the pins). PLLVss I PLL ground Ground pin for the on-chip PLL oscillator EXTAL I External clock Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. XTAL O Crystal Connected to a crystal resonator. CK O System clock Supplies the system clock to external devices. Clock This pin is not available in the SH7146. Operating mode control MD1, MD0 I Mode set Sets the operating mode. Do not change values on these pins during operation. Only MD1 is available in the SH7146. FWE R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 I Flash memory write enable Pin for flash memory. Flash memory can be protected against programming or erasure through this pin. Page 9 of 964 SH7146 Group Section 1 Overview Classification Symbol I/O Name Function System control RES I Power-on reset When low, this LSI enters the poweron reset state. MRES I Manual reset When low, this LSI enters the manual reset state. WDTOVF O Watchdog timer overflow Output signal for the watchdog timer overflow. If this pin needs to be pulled down, use the resistor larger than 1 M to pull this pin down. BREQ I Bus-mastership request Low when an external device requests the release of the bus mastership. This pin is not available in the SH7146. BACK O Bus-mastership request acknowledge Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. This pin is not available in the SH7146. Interrupts Address bus NMI I Non-maskable interrupt Non-maskable interrupt request pin. Fix to high or low level when not in use. IRQ3 to IRQ0 I Interrupt requests Maskable interrupt request pin. 3 to 0 Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. IRQOUT O Interrupt request Shows that an interrupt cause has output occurred. The interrupt cause can be recognized even in the bus release state. A19 to A0 O Address bus Outputs addresses. No address bus pins are available in the SH7146. Data bus D15 to D0 I/O Data bus 16-bit bidirectional bus. No data bus pins are available in the SH7146. Page 10 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 1 Overview Classification Symbol I/O Name Function Bus control CS1, CS0 O Chip select 1 and Chip-select signal for external 0 memory or devices. No chip select pins are available in the SH7146. RD O Read Indicates reading of data from external devices. This pin is not available in the SH7146. WRH O Write to upper byte Indicates a write access to bits 15 to 8 of the external data. This pin is not available in the SH7146. WRL O Write to lower byte Indicates a write access to bits 7 to 0 of the external data. This pin is not available in the SH7146. WAIT I Wait Input signal for inserting a wait cycle into the bus cycles during access to the external space. This pin is not available in the SH7146. Multi function timer- TCLKA, pulse unit 2 (MTU2) TCLKB, TCLKC, TCLKD I MTU2 timer clock External clock input pins for the input timer. TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O MTU2 input capture/output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A, TIOC1B I/O MTU2 input capture/output compare (channel 1) The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins. TIOC2A, TIOC2B I/O MTU2 input capture/output compare (channel 2) The TGRA_2 to TGRB_2 input capture input/output compare output/PWM output pins. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 11 of 964 SH7146 Group Section 1 Overview Classification Symbol I/O Name Function Multi function timer- TIOC3A, pulse unit 2 (MTU2) TIOC3B, TIOC3C, TIOC3D I/O MTU2 input capture/output compare (channel 3) The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O MTU2 input capture/output compare (channel 4) The TGRA_4 to TGRD_4 input capture input/output compare output/PWM output pins. TIC5U, TIC5V, TIC5W I MTU2 input capture (channel 5) The TGRU_5, TGRV_5, and TGRW_5 input capture input pins. Only TIC5U and TIC5V are available in the SH7146. Multi function timer- TIOC3BS, pulse unit 2S TIOC3DS (MTU2S) I/O MTU2S input capture/output compare (channel 3) The TGRB_3S and TGRD_3S input capture input/output compare output/PWM output pins. TIOC4AS, TIOC4BS, TIOC4CS, TIOC4DS I/O MTU2S input capture/output compare (channel 4) The TGRA_4S to TGRD_4S input capture input/output compare output/PWM output pins. TIC5US, TIC5VS, TIC5WS I MTU2S input capture (channel 5) The TGRU_5S, TGRV_5S, and TGRW_5S input capture input pins. POE8 to POE0 I Port output enable Request signal input to place the MTU2 and MTU2S waveform output pins in high impedance state. Port output enable (POE) Only TIC5US and TIC5VS are available in the SH7146. While POE functions are selected in the PFC, pins PB16/POE3, PB17/POE7, and PB18/POE8 are pulled up inside this LSI if no signals are input to them. Serial communication interface (SCI) Page 12 of 964 TXD2 to TXD0 O Transmit data Transmit data output pins RXD2 to RXD0 I Receive data Receive data input pins SCK2 to SCK0 I/O Serial clock Clock input/output pins R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 1 Overview Classification Symbol I/O Name Function A/D converter (ADC) AN15 to AN8, I AN6, AN4, AN2, AN0 Analog input pins Analog input pins. ADTRG I A/D conversion trigger input External trigger input pin for starting A/D conversion. AVcc I Analog power supply Power supply pin for the A/D converter. Connect all AVcc pins to the system power supply (Vcc) when the A/D converter is not used. The A/D converter does not work if any pin is open. AVss I Analog ground Ground pin for the A/D converter. Connect it to the system ground (0 V). Connect all AVss pins to the system ground (0 V) correctly. The A/D converter does not work if any pin is open. I/O ports PA15 to PA0 I/O General port 16-bit general input/output port pins. PB18 to PB16, PB5 to PB0 General port 9-bit general input/output port pins. I/O PB18 to PB16 and PB5 to PB2 are available in the SH7146. PD15 to PD0 I/O General port 16-bit general input/output port pins. These port pins are not available in the SH7146. User break controller (UBC) PE21 to PE0 I/O General port 22-bit general input/output port pins. PF15 to PF8, I PF6, PF4, PF2, PF0 General port 12-bit general input port pins. UBCTRG User break trigger output Trigger output pin for UBC condition match. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 O Page 13 of 964 SH7146 Group Section 1 Overview Classification Symbol I/O Name Function User debugging interface (H-UDI) (only in F-ZTAT version) TCK I Test clock Test-clock input pin. TMS I Test mode select Inputs the test-mode select signal. TDI I Test data input Serial input pin for instructions and data. TDO O Test data output Serial output pin for instructions and data. TRST I Test reset Initialization-signal input pin. AUDATA3 to O AUDATA0 AUD data Branch destination address output pins. AUDCK O AUD clock Sync-clock output pin. AUDSYNC O AUD sync signal Data start-position acknowledgesignal output pin. ASEMD0 I ASE mode Advanced user debugger (AUD) (only in SH7149 F-ZTAT version supporting full functions of E10A) E10A interface (only in F-ZTAT version) Sets the ASE mode. When a low level is input, this LSI enters ASE mode. When a high level is input, this LSI enters the normal mode. The emulator functions are available in ASE mode. When no signal is input, this pin is pulled up inside this LSI. ASEBRK I Break request E10A emulator break input pin. ASEBRKAK O Break mode acknowledge Indicates that the E10A emulator has entered its break mode. Note: The WDTOVF pin should not be pulled down. When absolutely necessary, pull it down through a resistor of 1 M or larger. Page 14 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU Section 2 CPU 2.1 Features * General registers: 32-bit register x 16 * Basic instructions: 62 * Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect (@R0, Rn) GBR indirect with displacement (@disp:8, GBR) Index GBR indirect (@R0, GBR) PC relative with displacement (@disp:8, PC) PC relative (disp:8/disp:12/Rn) Immediate (#imm:8) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 15 of 964 CPUS200C_000020020700 SH7146 Group Section 2 CPU 2.2 Register Configuration There are three types of registers: general registers (32-bit x 16), control registers (32-bit x 3), and system registers (32-bit x 4). General register (Rn) 31 0 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Status register (SR) 31 9 8 7 6 5 4 3 2 1 0 M Q I3 I2 I1 I0 S T Global base register (GBR) 31 0 GBR Vector base register (VBR) 31 0 VBR Multiply and accumulate register (MAC) 31 0 MACH MACL Procedure register (PR) 31 0 PR Program counter (PC) 31 0 PC Notes: 1. R0 can be used as an index register in index register indirect or index GBR indirect addressing mode. For some instructions, only R0 is used as the source or destination register. 2. R15 is used as a hardware stack pointer during exception handling. Figure 2.1 CPU Internal Register Configuration Page 16 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.2.1 Section 2 CPU General Registers (Rn) There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. R0 is also used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the status register (SR) and program counter (PC) values. 2.2.2 Control Registers There are three 32-bit control registers, designated status register (SR), global base register (GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers. VBR is used as a base address of the exception handling (including interrupts) vector table. * Status register (SR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 7 6 5 4 3 2 1 0 - - S T 0 R 0 R R/W R/W Initial value: R/W: Initial value: R/W: 14 13 12 11 10 9 8 - - - - - - M Q 0 R 0 R 0 R 0 R 0 R 0 R R/W R/W I[3:0] 1 R/W Bit Bit name Default Read/ Write Description 31 to 10 All 0 R Reserved 1 R/W 1 R/W 1 R/W 16 These bits are always read as 0. The write value should always be 0. 9 M Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 8 Q Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 7 to 4 I[3:0] 1111 R/W Interrupt Mask 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 17 of 964 SH7146 Group Section 2 CPU Bit Bit name Default Read/ Write Description 1 S Undefined R/W S Bit 0 T Undefined R/W T Bit Used by the multiply and accumulate instruction. Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL * Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations. * Vector-base register (VBR) This register indicates the base address of the exception handling vector table. Page 18 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.2.3 Section 2 CPU System Registers There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC). * Multiply and accumulate registers (MACH and MACL) This register stores the results of multiplication and multiply-and-accumulate operation. * Procedure register (PR) This register stores the return-destination address from subroutine procedures. * Program counter (PC) The PC indicates the point which is four bytes (two instructions) after the current execution instruction. 2.2.4 Initial Values of Registers Table 2.1 lists the initial values of registers after a reset. Table 2.1 Initial Values of Registers Type of register Register Default General register R0 to R14 Undefined R15 (SP) SP value set in the exception handling vector table SR I3 to I0: 1111 (H'F) Control register Reserved bits: 0 Other bits: Undefined System register GBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC PC value set in the exception handling vector table R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 19 of 964 SH7146 Group Section 2 CPU 2.3 Data Formats 2.3.1 Register Data Format The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register. 31 0 Longword Figure 2.2 Register Data Format 2.3.2 Memory Data Formats Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Address m + 1 Address m 31 23 Byte Address 2n Address 4n Address m + 3 Address m + 2 15 Byte 7 Byte Word 0 Byte Word Longword Figure 2.3 Memory Data Format Page 20 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.3.3 Section 2 CPU Immediate Data Formats Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zeroextended to longword and then calculated. Thus, if the immediate data is used for the AND instruction, the upper 24 bits in the destination register are always cleared. The immediate data of word or longword is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed by the MOV immediate data instruction in PC relative addressing mode with displacement. 2.4 Features of Instructions 2.4.1 RISC Type The instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one cycle. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Byte or word data in memory is sign-extended to longword and then calculated. Immediate data is sign-extended to longword for arithmetic operations or zero-extended to longword size for logical operations. Table 2.2 Word Data Sign Extension CPU in this LSI Description Example of Other CPUs MOV.W Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. ADD.W #H'1234,R0 ADD @(disp,PC),R1 R1,R0 ........ .DATA.W H'1234 Note: Immediate data is accessed by @(disp,PC). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 21 of 964 SH7146 Group Section 2 CPU Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions means the delayed branch instructions. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. The conditional branch instructions have two types of instructions: conditional branch instructions and delayed branch instructions. Table 2.3 Delayed Branch Instructions CPU in this LSI Description Example of Other CPUs BRA TRGET ADD is executed before branch to TRGET. ADD.W R1,R0 ADD R1,R0 BRA TRGET Multiply/Multiply-and-Accumulate Operations: A 16 x 16 32 multiply operation is executed in one to two cycles, and a 16 x 16 + 64 64 multiply-and-accumulate operation in two to three cycles. A 32 x 32 64 multiply operation and a 32 x 32 + 64 64 multiply-andaccumulate operation are each executed in two to four cycles. T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Table 2.4 T Bit CPU in this LSI Description Example of Other CPUs CMP/GE R1,R0 When R0 R1, the T bit is set. CMP.W R1,R0 BT TRGET0 When R0 R1, a branch is made to TRGET0. BGE TRGET0 BF TRGET1 When R0 < R1, a branch is made to TRGET1. BLT TRGET1 ADD #-1,R0 The T bit is not changed by ADD. SUB.W #1,R0 CMP/EQ #0,R0 When R0 = 0, the T bit is set. BEQ BT TRGET A branch is made when R0 = 0. TRGET Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword immediate data is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed with the MOV immediate data instruction using PC relative addressing mode with displacement. Page 22 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 2.5 Section 2 CPU Access to Immediate Data Type This LSI's CPU Example of Other CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 MOV.L #H'12345678,R0 ........ .DATA.W H'1234 32-bit immediate MOV.L @(disp,PC),R0 ........ .DATA.L H'12345678 Note: Immediate data is accessed by @(disp,PC). Absolute Addresses: When data is accessed by absolute address, place the absolute address value in a table in memory beforehand. The absolute address value is transferred to a register using the method whereby immediate data is loaded when an instruction is executed, and the data is accessed using the register indirect addressing mode. Table 2.6 Access to Absolute Address Type CPU in this LSI Example of Other CPUs Absolute address MOV.L @(disp,PC),R1 MOV.B @H'12345678,R0 MOV.B @R1,R0 ........ .DATA.L H'12345678 Note: Immediate data is referenced by @(disp,PC). 16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement addressing mode, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is accessed using index register indirect addressing mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 23 of 964 SH7146 Group Section 2 CPU Table 2.7 Access with Displacement Type CPU in this LSI Example of Other CPUs 16-bit displacement MOV.W @(disp,PC),R0 MOV.W MOV.W @(R0,R1),R2 @(H'1234,R1),R2 ........ .DATA.W H'1234 Note: Immediate data is referenced by @(disp,PC). 2.4.2 Addressing Modes Table 2.8 lists addressing modes and effective address calculation methods. Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Register indirect @Rn Register indirect with post-increment @Rn+ Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Rn Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn After instruction execution Byte: Rn + 1 Rn Rn Word: Rn + 2 Rn Rn + 1/2/4 + Longword: Rn + 4 Rn 1/2/4 Register indirect with pre-decrement @-Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 1/2/4 Page 24 of 964 Rn - 1/2/4 Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register indirect with displacement @(disp:4, Rn) Byte: Rn + disp Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Word: Rn + disp x 2 Longword: Rn + disp x 4 Rn disp (zero-extended) + Rn + disp x 1/2/4 x 1/2/4 Index @(R0, Rn) Effective address is sum of register Rn and R0 register indirect contents. Rn + R0 Rn Rn + R0 + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 GBR disp (zero-extended) + GBR + disp x 1/2/4 x 1/2/4 Index GBR indirect @(R0, GBR) Effective address is sum of register GBR and R0 contents. GBR + R0 GBR + GBR + R0 R0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 25 of 964 SH7146 Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Method PC relative with @(disp:8, displacement PC) Calculation Formula Effective address is PC with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. Word: PC + disp x2 Longword: PC&H'FFFFFFFC + disp x 4 *With longword operand PC & H'FFFFFFFC * PC + disp x 2 or + PC& H'FFFFFFFC + disp x 4 disp (zero-extended) x 2/4 PC relative disp:8 Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC + disp x 2 PC disp (sign-extended) + PC + disp x 2 x 2 disp:12 Effective address is PC with 12-bit displacement PC + disp x 2 disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) + PC + disp x 2 x 2 Page 26 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC relative Rn PC + Rn Effective address is sum of PC and Rn. PC + PC + Rn Rn Immediate 2.4.3 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. Instruction Formats This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 27 of 964 SH7146 Group Section 2 CPU Table 2.9 Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type NOP nnnn: register direct MOVT Rn 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx Control register or nnnn: register system register direct STS MACH,Rn Control register or nnnn: preSTC.L SR,@-Rn system register decrement register indirect m type 15 0 xxxx mmmm xxxx xxxx Page 28 of 964 mmmm: register direct Control register or LDC Rm,SR system register mmmm: postControl register or LDC.L @Rm+,SR increment register system register indirect mmmm: register indirect JMP @Rm PC relative using Rm BRAF Rm R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU Instruction Format Source Operand Destination Operand nm type mmmm: register direct nnnn: register direct ADD mmmm: register direct nnnn: register indirect MOV.L Rm,@Rn 15 0 xxxx nnnn mmmm xxxx mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) Sample Instruction Rm,Rn MAC.W @Rm+,@Rn+ nnnn: * postincrement register indirect (multiplyand-accumulate operation) nnnn: register mmmm: postincrement register direct indirect md type 15 0 xxxx xxxx mmmm dddd nd4 type 15 0 xxxx xxxx nnnn dddd nmd type 15 0 xxxx nnnn mmmm dddd R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 MOV.L @Rm+,Rn mmmm: register direct nnnn: preMOV.L Rm,@-Rn decrement register indirect mmmm: register direct nnnn: index register indirect mmmmdddd: register indirect with displacement R0 (register direct) MOV.B @(disp,Rm),R0 MOV.L Rm,@(R0,Rn) R0 (register direct) nnnndddd: register indirect with displacement MOV.B R0,@(disp,Rn) mmmm: register direct nnnndddd: register indirect with displacement MOV.L Rm,@(disp,Rn) mmmmdddd: register indirect with displacement nnnn: register direct MOV.L @(disp,Rm),Rn Page 29 of 964 SH7146 Group Section 2 CPU Instruction Format Source Operand d type dddddddd: GBR indirect with displacement 15 0 xxxx xxxx dddd dddd Destination Operand R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement d12 type 15 0 xxxx nnnn dddd dddd i type 15 0 xxxx xxxx iiii iiii ni type 15 0 xxxx nnnn iiii iiii Note: * MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (register direct) MOVA @(disp,PC),R0 dddddddd: PC relative BF label dddddddddddd: PC relative BRA label dddddddd: PC relative with displacement nnnn: register direct MOV.L @(disp,PC),Rn iiiiiiii: immediate Index GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: immediate R0 (register direct) AND #imm,R0 iiiiiiii: immediate TRAPA #imm iiiiiiii: immediate nnnn: register direct ADD #imm,Rn 15 0 xxxx dddd dddd dddd nd8 type Sample Instruction (label=disp+PC) In multiply and accumulate instructions, nnnn is the source register. Page 30 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU 2.5 Instruction Set 2.5.1 Instruction Set by Type Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Type Data transfer instructions Kinds of Instruction Op Code Function Number of Instructions 5 MOV Data transfer 39 Immediate data transfer Peripheral module data transfer Structure data transfer Arithmetic operation instructions 21 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 MOVA Effective address transfer MOVT T bit transfer SWAP Upper/lower swap XTRCT Extraction of middle of linked registers ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow CMP/cond Comparison DIV1 Division DIV0S Signed division initialization DIV0U Unsigned division initialization DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, doubleprecision multiply-and-accumulate MUL Double-precision multiplication 33 Page 31 of 964 SH7146 Group Section 2 CPU Type Arithmetic operation instructions Logic operation instructions Shift instructions Page 32 of 964 Kinds of Instruction Op Code Function Number of Instructions 21 MULS Signed multiplication 33 MULU Unsigned multiplication NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction with carry SUBV Binary subtraction with underflow AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST T bit setting for logical AND XOR Exclusive logical OR ROTL 1-bit left shift ROTR 1-bit right shift ROTCL 1-bit left shift with T bit ROTCR 1-bit right shift with T bit SHAL Arithmetic 1-bit left shift SHAR Arithmetic 1-bit right shift SHLL Logical 1-bit left shift SHLLn Logical n-bit left shift SHLR Logical 1-bit right shift SHLRn Logical n-bit right shift 6 10 14 14 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Type Branch instructions System control instructions Total: Section 2 CPU Kinds of Instruction Op Code Function 9 BF Conditional branch, delayed conditional 11 branch (T = 0) BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure 11 62 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 RTS Return from subroutine procedure CLRT T bit clear CLRMAC MAC register clear LDC Load into control register LDS Load into system register NOP No operation RTE Return from exception handling SETT T bit setting SLEEP Transition to power-down mode STC Store from control register STS Store from system register TRAPA Trap exception handling Number of Instructions 31 142 Page 33 of 964 SH7146 Group Section 2 CPU The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Instruction Instruction Code Indicated by mnemonic. Indicated in MSB LSB order. Summary of Operation Execution Cycles T Bit Indicates summary of Value when no Value of T bit after operation. wait cycles are instruction is executed 1 inserted* Explanation of Symbols : No change Explanation of Symbols Explanation of Symbols Explanation of Symbols OP.Sz SRC, DEST mmmm: Source register OP: Operation code nnnn: Destination Sz: Size register SRC: Source 0000: R0 DEST: Destination 0001: R1 ......... Rm: Source register 1111: R15 Rn: Destination register iiii: imm: Immediate data disp: Displacement* 2 , : Transfer direction (xx): Memory operand M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: dddd: Displacement Exclusive logical OR of each bit Immediate data -: Logical NOT of each bit <<n: n-bit left shift >>n: n-bit right shift Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: * When there is contention between an instruction fetch and a data access * When the destination register of a load instruction (memory register) is also used by the following instruction 2. Scaled (x1, x2, or x4) according to the instruction operand size, etc. For details, see SH-1/SH-2/SH-DSP Software Manual. Page 34 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.5.2 Section 2 CPU Data Transfer Instructions Table 2.11 Data Transfer Instructions Instruction Operation Code Execution Cycles T Bit MOV imm Sign extension Rn 1110nnnniiiiiiii 1 MOV.W @(disp,PC),Rn (disp x 2 + PC) Sign 1001nnnndddddddd 1 1101nnnndddddddd 1 Rm Rn 0110nnnnmmmm0011 1 MOV.B Rm,@Rn Rm (Rn) 0010nnnnmmmm0000 1 MOV.W Rm,@Rn Rm (Rn) 0010nnnnmmmm0001 1 MOV.L Rm,@Rn Rm (Rn) 0010nnnnmmmm0010 1 MOV.B @Rm,Rn (Rm) Sign extension Rn 0110nnnnmmmm0000 1 MOV.W @Rm,Rn (Rm) Sign extension Rn 0110nnnnmmmm0001 1 MOV.L @Rm,Rn (Rm) Rn 0110nnnnmmmm0010 1 MOV.B Rm,@-Rn Rn-1 Rn, Rm (Rn) 0010nnnnmmmm0100 1 MOV.W Rm,@-Rn Rn-2 Rn, Rm (Rn) 0010nnnnmmmm0101 1 MOV.L Rm,@-Rn Rn-4 Rn, Rm (Rn) 0010nnnnmmmm0110 1 MOV.B @Rm+,Rn (Rm) Sign extension Rn, Rm + 1 Rm 0110nnnnmmmm0100 1 MOV.W @Rm+,Rn (Rm) Sign extension Rn, Rm + 2 Rm 0110nnnnmmmm0101 1 MOV.L @Rm+,Rn (Rm) Rn,Rm + 4 Rm 0110nnnnmmmm0110 1 #imm,Rn extension Rn MOV.L @(disp,PC),Rn (disp x 4 + PC) Rn MOV Rm,Rn MOV.B R0,@(disp,Rn) R0 (disp + Rn) 10000000nnnndddd 1 MOV.W R0,@(disp,Rn) R0 (disp x 2 + Rn) 10000001nnnndddd 1 MOV.L Rm,@(disp,Rn) Rm (disp x 4 + Rn) 0001nnnnmmmmdddd 1 MOV.B @(disp,Rm),R0 (disp + Rm) Sign 10000100mmmmdddd 1 10000101mmmmdddd 1 0101nnnnmmmmdddd 1 extension R0 MOV.W @(disp,Rm),R0 (disp x 2 + Rm) Sign extension R0 MOV.L @(disp,Rm),Rn (disp x 4 + Rm) Rn R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 35 of 964 SH7146 Group Section 2 CPU Instruction Operation Code Execution Cycles T Bit MOV.B Rm,@(R0,Rn) Rm (R0 + Rn) 0000nnnnmmmm0100 1 MOV.W Rm,@(R0,Rn) Rm (R0 + Rn) 0000nnnnmmmm0101 1 MOV.L Rm,@(R0,Rn) Rm (R0 + Rn) 0000nnnnmmmm0110 1 MOV.B @(R0,Rm),Rn (R0 + Rm) Sign extension Rn 0000nnnnmmmm1100 1 MOV.W @(R0,Rm),Rn (R0 + Rm) Sign extension Rn 0000nnnnmmmm1101 1 MOV.L @(R0,Rm),Rn (R0 + Rm) Rn 0000nnnnmmmm1110 1 MOV.B R0,@(disp,GBR) R0 (disp + GBR) 11000000dddddddd 1 MOV.W R0,@(disp,GBR) R0 (disp x 2 + GBR) 11000001dddddddd 1 MOV.L R0,@(disp,GBR) R0 (disp x 4 + GBR) 11000010dddddddd 1 MOV.B @(disp,GBR),R0 (disp + GBR) Sign extension R0 11000100dddddddd 1 MOV.W @(disp,GBR),R0 (disp x 2 + GBR) Sign extension R0 11000101dddddddd 1 MOV.L @(disp,GBR),R0 (disp x 4 + GBR) R0 11000110dddddddd 1 MOVA @(disp,PC),R0 disp x 4 + PC R0 MOVT Rn 11000111dddddddd 1 T Rn 0000nnnn00101001 1 SWAP.B Rm,Rn Rm Swap lowest two bytes Rn 0110nnnnmmmm1000 1 SWAP.W Rm,Rn Rm Swap two consecutive words Rn 0110nnnnmmmm1001 1 XTRCT Rm,Rn Rm: Middle 32 bits of Rn Rn 0010nnnnmmmm1101 1 Page 36 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.5.3 Section 2 CPU Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Instruction Operation Code Execution Cycles T Bit ADD Rm,Rn Rn + Rm Rn 0011nnnnmmmm1100 1 ADD #imm,Rn Rn + imm Rn 0111nnnniiiiiiii 1 ADDC Rm,Rn Rn + Rm + T Rn, Carry T 0011nnnnmmmm1110 1 Carry ADDV Rm,Rn Rn + Rm Rn, Overflow T 0011nnnnmmmm1111 1 Overflow CMP/EQ #imm,R0 If R0 = imm, 1 T 10001000iiiiiiii 1 Comparison result CMP/EQ Rm,Rn If Rn = Rm, 1 T 0011nnnnmmmm0000 1 Comparison result CMP/HS Rm,Rn If Rn Rm with unsigned data, 1 T 0011nnnnmmmm0010 1 Comparison result CMP/GE Rm,Rn If Rn Rm with signed data, 1 T 0011nnnnmmmm0011 1 Comparison result CMP/HI Rm,Rn If Rn > Rm with unsigned data, 1 T 0011nnnnmmmm0110 1 Comparison result CMP/GT Rm,Rn If Rn > Rm with signed data, 1 T 0011nnnnmmmm0111 1 Comparison result CMP/PZ Rn If Rn 0, 1 T 0100nnnn00010001 1 Comparison result CMP/PL Rn If Rn > 0, 1 T 0100nnnn00010101 1 Comparison result CMP/STR Rm,Rn If Rn and Rm have an equivalent byte, 1 T 0010nnnnmmmm1100 1 Comparison result DIV1 Rm,Rn Single-step division (Rn/Rm) 0011nnnnmmmm0100 1 Calculation result DIV0S Rm,Rn MSB of Rn Q, MSB of Rm M, M^ Q T 0010nnnnmmmm0111 1 Calculation result DIV0U 0 M/Q/T 0000000000011001 1 0 DMULS.L Rm,Rn Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits 0011nnnnmmmm1101 2 to 5* R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 37 of 964 SH7146 Group Section 2 CPU Instruction Operation Code Execution Cycles T Bit DMULU.L Rm,Rn Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits 0011nnnnmmmm0101 2 to 5* DT Rn Rn - 1 Rn, if Rn = 0, 1 T, else 0 T 0100nnnn00010000 1 Comparison result EXTS.B Rm,Rn A byte in Rm is signextended Rn 0110nnnnmmmm1110 1 EXTS.W Rm,Rn A word in Rm is signextended Rn 0110nnnnmmmm1111 1 EXTU.B Rm,Rn A byte in Rm is zeroextended Rn 0110nnnnmmmm1100 1 EXTU.W Rm,Rn A word in Rm is zeroextended Rn 0110nnnnmmmm1101 1 MAC.L @Rm+,@Rn+ Signed operation of (Rn) x (Rm) + MAC MAC, 32 x 32 + 64 64 bits 0000nnnnmmmm1111 2 to 5* MAC.W @Rm+,@Rn+ Signed operation of (Rn) x (Rm) + MAC MAC, 16 x 16 + 64 64 bits 0100nnnnmmmm1111 2 to 4* MUL.L Rm,Rn Rn x Rm MACL 32 x 32 32 bits 0000nnnnmmmm0111 2 to 5* MULS.W Rm,Rn Signed operation of Rn x Rm MAC 16 x 16 32 bits 0010nnnnmmmm1111 1 to 3* MULU.W Rm,Rn Unsigned operation of Rn x Rm MAC 16 x 16 32 bits 0010nnnnmmmm1110 1 to 3* NEG Rm,Rn 0-Rm Rn 0110nnnnmmmm1011 1 NEGC Rm,Rn 0-Rm-T Rn, Borrow T 0110nnnnmmmm1010 1 Borrow SUB Rm,Rn Rn-Rm Rn 0011nnnnmmmm1000 1 SUBC Rm,Rn Rn-Rm-T Rn, Borrow T 0011nnnnmmmm1010 1 Borrow SUBV Rm,Rn Rn-Rm Rn, Underflow T 0011nnnnmmmm1011 1 Overflow Note: * Indicates the number of execution cycles for normal operation. Page 38 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.5.4 Section 2 CPU Logic Operation Instructions Table 2.13 Logic Operation Instructions Execution Cycles T Bit Instruction Operation Code AND Rm,Rn Rn & Rm Rn 0010nnnnmmmm1001 1 AND #imm,R0 R0 & imm R0 11001001iiiiiiii 1 11001101iiiiiiii 3 AND.B #imm,@(R0,GBR) (R0 + GBR) & imm (R0 + GBR) NOT Rm,Rn ~Rm Rn 0110nnnnmmmm0111 1 OR Rm,Rn Rn | Rm Rn 0010nnnnmmmm1011 1 OR #imm,R0 R0 | imm R0 11001011iiiiiiii 1 11001111iiiiiiii 3 OR.B #imm,@(R0,GBR) (R0 + GBR) | imm (R0 + GBR) TAS.B @Rn If (Rn) is 0, 1 T; 1 MSB of (Rn) 0100nnnn00011011 4 Test result TST Rm,Rn Rn & Rm; if the result is 0, 1 T 0010nnnnmmmm1000 1 Test result TST #imm,R0 R0 & imm; if the result is 0, 1 T 11001000iiiiiiii 1 Test result 11001100iiiiiiii 3 Test result TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; if the result is 0, 1 T XOR Rm,Rn Rn ^ Rm Rn 0010nnnnmmmm1010 1 XOR #imm,R0 R0 ^ imm R0 11001010iiiiiiii 1 11001110iiiiiiii 3 XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm (R0 + GBR) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 39 of 964 SH7146 Group Section 2 CPU 2.5.5 Shift Instructions Table 2.14 Shift Instructions Code Execution Cycles T Bit T Rn MSB 0100nnnn00000100 1 MSB LSB Rn T 0100nnnn00000101 1 LSB Rn T Rn T 0100nnnn00100100 1 MSB ROTCR Rn T Rn T 0100nnnn00100101 1 LSB SHAL Rn T Rn 0 0100nnnn00100000 1 MSB SHAR Rn MSB Rn T 0100nnnn00100001 1 LSB SHLL Rn T Rn 0 0100nnnn00000000 1 MSB SHLR Rn 0 Rn T 0100nnnn00000001 1 LSB SHLL2 Rn Rn << 2 Rn 0100nnnn00001000 1 SHLR2 Rn Rn >> 2 Rn 0100nnnn00001001 1 SHLL8 Rn Rn << 8 Rn 0100nnnn00011000 1 SHLR8 Rn Rn >> 8 Rn 0100nnnn00011001 1 SHLL16 Rn Rn << 16 Rn 0100nnnn00101000 1 SHLR16 Rn Rn >> 16 Rn 0100nnnn00101001 1 Instruction Operation ROTL Rn ROTR Rn ROTCL Page 40 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 2.5.6 Section 2 CPU Branch Instructions Table 2.15 Branch Instructions Instruction Operation Code Execution Cycles T Bit BF label If T = 0, disp x 2 + PC PC; if T = 1, nop 10001011dddddddd 3/1* BF/S label Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop 10001111dddddddd 2/1* BT label If T = 1, disp x 2 + PC PC; if T = 0, nop 10001001dddddddd 3/1* BT/S label Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop 10001101dddddddd 2/1* BRA Delayed branch, disp x 2 + PC PC 1010dddddddddddd 2 BRAF Rm Delayed branch, Rm + PC PC 0000mmmm00100011 2 BSR Delayed branch, PC PR, disp x 2 + PC PC 1011dddddddddddd 2 BSRF Rm Delayed branch, PC PR, Rm + PC PC 0000mmmm00000011 2 JMP @Rm Delayed branch, Rm PC 0100mmmm00101011 2 JSR @Rm Delayed branch, PC PR, Rm PC 0100mmmm00001011 2 Delayed branch, PR PC 0000000000001011 2 label label RTS Note: * One cycle when the branch is not executed. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 41 of 964 SH7146 Group Section 2 CPU 2.5.7 System Control Instructions Table 2.16 System Control Instructions Instruction Operation Code Execution Cycles T Bit CLRT 0T 0000000000001000 1 0 CLRMAC 0 MACH, MACL 0000000000101000 1 LDC Rm,SR Rm SR 0100mmmm00001110 6 LSB LDC Rm,GBR Rm GBR 0100mmmm00011110 4 LDC Rm,VBR Rm VBR 0100mmmm00101110 4 LDC.L @Rm+,SR (Rm) SR, Rm + 4 Rm 0100mmmm00000111 8 LSB LDC.L @Rm+,GBR (Rm) GBR, Rm + 4 Rm 0100mmmm00010111 4 LDC.L @Rm+,VBR (Rm) VBR, Rm + 4 Rm 0100mmmm00100111 4 LDS Rm,MACH Rm MACH 0100mmmm00001010 1 LDS Rm,MACL Rm MACL 0100mmmm00011010 1 LDS Rm,PR Rm PR 0100mmmm00101010 1 LDS.L @Rm+,MACH (Rm) MACH, Rm + 4 Rm 0100mmmm00000110 1 LDS.L @Rm+,MACL (Rm) MACL, Rm + 4 Rm 0100mmmm00010110 1 LDS.L @Rm+,PR (Rm) PR, Rm + 4 Rm 0100mmmm00100110 1 NOP No operation 0000000000001001 1 RTE Delayed branch, Stack area PC/SR 0000000000101011 5 SETT 1T 0000000000011000 1 1 SLEEP Sleep 0000000000011011 4* STC SR,Rn SR Rn 0000nnnn00000010 1 STC GBR,Rn GBR Rn 0000nnnn00010010 1 STC VBR,Rn VBR Rn 0000nnnn00100010 1 STC.L SR,@-Rn Rn-4 Rn, SR (Rn) 0100nnnn00000011 1 STC.L GBR,@-Rn Rn-4 Rn, GBR (Rn) 0100nnnn00010011 1 STC.L VBR,@-Rn Rn-4 Rn, VBR (Rn) 0100nnnn00100011 1 Page 42 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU Instruction Operation Code Execution Cycles T Bit STS MACH,Rn MACH Rn 0000nnnn00001010 1 STS MACL,Rn MACL Rn 0000nnnn00011010 1 STS PR,Rn PR Rn 0000nnnn00101010 1 STS.L MACH,@-Rn Rn-4 Rn, MACH (Rn) 0100nnnn00000010 1 STS.L MACL,@-Rn Rn-4 Rn, MACL (Rn) 0100nnnn00010010 1 STS.L PR,@-Rn Rn-4 Rn, PR (Rn) 0100nnnn00100010 1 TRAPA #imm PC/SR Stack area, (imm x 4 + VBR) PC 11000011iiiiiiii 8 Note: * Number of execution cycles until this LSI enters sleep mode. About the number of execution cycles: The table lists the minimum number of execution cycles. In practice, the number of execution cycles will be increased depending on the conditions such as: * When there is a conflict between instruction fetch and data access * When the destination register of a load instruction (memory register) is also used by the instruction immediately after the load instruction. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 43 of 964 SH7146 Group Section 2 CPU 2.6 Processing States The CPU has the five processing states: reset, exception handling, bus release, program execution, and power-down. Figure 2.4 shows the CPU state transition. From any state except deep software standby mode when RES = 1 and MRES = 0 From any state when RES = 0 RES = 0 Power-on reset state Manual reset state RES = 0 RES = 1, MRES = 1 RES = 1 When internal power-on reset by WDT or internal manual reset by WDT occurs. Bus request cleared Bus release state Bus request generated Bus request generated Bus request cleared Exception handling state Bus request generated Exception processing source occurs NMI interrupt or IRQ interrupt occurs Exception processing ends Bus request cleared Program execution state SSBY bit = 0 for SLEEP instruction Sleep mode Reset state SSBY bit = 1 and STBYMD bit = 1 for SLEEP instruction SSBY bit = 1 and STBYMD bit = 0 for SLEEP instruction Deep software standby mode Software standby mode Power-down mode Figure 2.4 Transitions between Processing States Page 44 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 2 CPU * Reset state The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state. * Exception handling state This state is a transitional state in which the CPU processing state changes due to a request for exception handling such as a reset or an interrupt. When a reset occurs, the execution start address as the initial value of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table. Then, a branch is made for the start address to execute a program. When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to by SP. The start address of an exception handling routine is fetched from the exception handling vector table and a branch to the address is made to execute a program. Then the processing state enters the program execution state. * Program execution state The CPU executes programs sequentially. * Power-down state The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter sleep mode, software standby mode, or deep software standby mode. * Bus release state In the bus release state, the CPU releases access rights to the bus to the device that has requested them. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 45 of 964 Section 2 CPU Page 46 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows the allowable combinations of these pin settings; do not set these pins in the other way than the shown combinations. When power is applied to the system, be sure to conduct power-on reset. The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip mode. For the on-chip flash memory programming mode, boot mode, user boot mode, and user program mode which are on-chip programming modes are available. Table 3.1 Selection of Operating Modes Pin Setting Bus Width of CS0 Space 1 Mode No. FWE MD1 MD0* Mode Name Mode 0 0 0 0 MCU extension Not active mode 0 8 Mode 1 0 0 1 MCU extension Not active mode 1 16 Mode 2 0 1 0 MCU extension Active mode 2 Set by CS0BCR in BSC Mode 3 0 1 1 Single chip mode Active Mode 4*2 1 0 0 Boot mode Active 1 0 1 User boot mode Active Set by CS0BCR in BSC Mode 6*2 1 1 0 Active Set by CS0BCR in BSC 1 1 User programming mode -- -- Mode 5* Mode 7* 2 2 1 On-Chip ROM SH7146 SH7149 Notes: 1. The SH7146 does not have the MD0 pin and only supports the following operating modes according to the combination of the FWE and MD1 pins. Single chip mode: FWE pin = 0 and MD1 pin = 1 Boot mode: FWE pin = 1 and MD1 pin = 0 User programming mode: FWE pin= 1 and MD1 pin = 1 2. Flash memory programming mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 47 of 964 SH7146 Group Section 3 MCU Operating Modes 3.2 Input/Output Pins Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output Function MD0 Input Designates operating mode through the level applied to this pin MD1 Input Designates operating mode through the level applied to this pin FWE Input Enables, by hardware, programming/erasing of the on-chip flash memory Page 48 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 3.3 Operating Modes 3.3.1 Mode 0 (MCU Extension Mode 0) Section 3 MCU Operating Modes CS0 space becomes external memory spaces with 8-bit bus width in SH7149. 3.3.2 Mode 1 (MCU Extension Mode 1) CS0 space becomes external memory spaces with 16-bit bus width in SH7149. 3.3.3 Mode 2 (MCU Extension Mode 2) The on-chip ROM is active and CS0 space can be used in this mode. 3.3.4 Mode 3 (Single Chip Mode) All ports can be used in this mode, however the external address cannot be used. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 49 of 964 SH7146 Group Section 3 MCU Operating Modes 3.4 Address Map The address maps for the operating modes are shown in figures 3.1 and 3.2. Mode 3 Single chip mode H'00000000 On-chip ROM (256 kbytes) H'0003FFFF H'00040000 Reserved area H'FFFF8FFF H'FFFF9000 On-chip RAM (8 kbytes) H'FFFFAFFF H'FFFFB000 Reserved area H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF Figure 3.1 Address Map for Each Operating Mode in SH7146 Page 50 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 3 MCU Operating Modes Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode H'00000000 H'00000000 Mode 3 Single chip mode H'00000000 CS0 space H'000FFFFF H'00100000 On-chip ROM (256 kbytes) On-chip ROM (256 kbytes) H'0003FFFF H'00040000 H'0003FFFF H'00040000 Reserved area Reserved area H'01FFFFFF H'02000000 CS0 space H'020FFFFF H'02100000 Reserved area H'03FFFFFF H'04000000 H'03FFFFFF H'04000000 CS1 space CS1 space H'040FFFFF H'04100000 H'040FFFFF H'04100000 Reserved area Reserved area Reserved area H'FFFF8FFF H'FFFF9000 H'FFFF8FFF H'FFFF9000 On-chip RAM (8 kbytes) H'FFFFAFFF H'FFFFB000 H'FFFF8FFF H'FFFF9000 On-chip RAM (8 kbytes) H'FFFFAFFF H'FFFFB000 Reserved area H'FFFFBFFF H'FFFFC000 H'FFFFAFFF H'FFFFB000 Reserved area H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF On-chip RAM (8 kbytes) Reserved area H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers On-chip peripheral I/O registers H'FFFFFFFF H'FFFFFFFF Figure 3.2 Address Map for Each Operating Mode in SH7149 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 51 of 964 SH7146 Group Section 3 MCU Operating Modes 3.5 Initial State in This LSI In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section 22, Power-Down Modes. 3.6 Note on Changing Operating Mode When changing operating mode while power is applied to this LSI, make sure to do it in the power-on reset state (that is, the low level is applied to the RES pin). CK MD1, MD0 tMDS* RES Note: * See section 24.3.2, Control Signal Timing. Figure 3.3 Reset Input Timing when Changing Operating Mode Page 52 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 4 Clock Pulse Generator (CPG) Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (I), a bus clock (B), a peripheral clock (P), and clocks (MI and MP) for the MTU2S and MTU2 modules. The CPG also controls power-down modes. 4.1 Features * Five clocks generated independently An internal clock (I) for the CPU; a peripheral clock (P) for the on-chip peripheral modules; a bus clock (B = CK) for the external bus interface; a MTU2S clock (MI) for the on-chip MTU2S module; and a MTU2 clock (MP) for the on-chip MTU2 module. * Frequency change function Frequencies of the internal clock (I), bus clock (B), peripheral clock (P), MTU2S clock (MI), and MTU2 clock (MP) can be changed independently using the divider circuit within the CPG. Frequencies are changed by software using the frequency control register (FRQCR) setting. * Power-down mode control The clock can be stopped in sleep mode and standby mode and specific modules can be stopped using the module standby function. * Oscillation stop detection If the clock supplied through the clock input pin stops for any reason, the timer pins can be automatically placed in the high-impedance state. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 53 of 964 CPGS301C_000020030900 SH7146 Group Section 4 Clock Pulse Generator (CPG) Figure 4.1 shows a block diagram of the clock pulse generator. Oscillator unit MTU2S clock (MI) MTU2 clock (MP) Divider Crystal oscillator XTAL PLL circuit (x8) EXTAL Oscillation stop detection x1 x1/2 x1/3 x1/4 x1/8 Internal clock (I) Peripheral clock (P) Oscillation stop detection circuit Bus clock (B = CK) CK CPG control unit Standby control circuit Clock frequency control circuit OSCCR FRQCR STBCR1 STBCR2 STBCR3 STBCR4 STBCR5 STBCR6 Bus interface [Legend] FRQCR: OSCCR: STBCR1: STBCR2: STBCR3: STBCR4: STBCR5: STBCR6: Internal bus Frequency control register Oscillation stop detection control register Standby control register 1 Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 Figure 4.1 Block Diagram of Clock Pulse Generator Page 54 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 4 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or the EXTAL pin by 8. The multiplication ratio is fixed at x8. Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is connected to the XTAL and EXTAL pins. Divider: The divider generates clocks with the frequencies to be used by the internal clock (I), bus clock (B), peripheral clock (P), MTU2S clock (MI), and MTU2 clock (MP). The frequencies can be selected from 1, 1/2, 1/3, 1/4, and 1/8 times the frequency output from the PLL circuit. The division ratio should be specified in the frequency control register (FRQCR). Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal oscillator. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency according to the setting in the frequency control register (FRQCR). Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator circuit and other modules in sleep or standby mode. Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control bits for the frequency division ratios of the internal clock (I), bus clock (B), peripheral clock (P), MTU2S clock (MI), and MTU2 clock (MP). Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output through an external pin. Standby Control Registers 1 to 6 (STBCR1 to STBCR6): The standby control register (STBCR) has bits for controlling the power-down modes. For details, see section 22, Power-Down Modes. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 55 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating Clock Operating Module Operating Clock Operating Module Internal clock (I) CPU Peripheral clock (P) POE UBC SCI ROM A/D RAM CMT WDT Bus clock (B) Page 56 of 964 BSC MTU2 clock (MP) MTU2 DTC MTU2S clock (MI) MTU2S R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 4.2 Section 4 Clock Pulse Generator (CPG) Input/Output Pins Table 4.2 shows the CPG pin configuration. Table 4.2 Pin Configuration Pin Name Abbr. I/O Description Crystal input/output XTAL pins EXTAL (clock input pins) Output Connects a crystal resonator. Input Connects a crystal resonator or an external clock. Clock output pin Output Outputs an external clock. CK Note: To use the clock output (CK) pin, appropriate settings may be needed for the pin in the pin function controller (PFC) in some cases. For details, refer to section 17, Pin Function Controller (PFC). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 57 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) 4.3 Clock Operating Mode Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Clock Operating Mode 1 Note: * Clock I/O Source Output PLL Circuit Input to Divider EXTAL input or crystal resonator CK* ON (x8) x8 To output the clock through the clock output (CK) pin, appropriate settings should be made in the pin function controller (PFC). For details, refer to section 17, Pin Function Controller (PFC). Mode 1: The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 5 MHz to 12.5 MHz can be used, the internal clock (I) frequency ranges from 10 MHz to 80 MHz. Maximum operating frequencies: I = 80 MHz, B = 40 MHz, P = 40 MHz, MI = 80 MHz, and MP = 40 MHz Table 4.4 shows the frequency division ratios that can be specified with FRQCR. Page 58 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 4.4 PLL Multiplication Ratio I x8 Section 4 Clock Pulse Generator (CPG) Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz)* B P MI MP I B P MI Input MP Clock I B P MI MP 1/8 1/8 1/8 1/8 1/8 1 1 1 1 1 10 10 10 10 10 1/4 1/8 1/8 1/8 1/8 2 1 1 1 1 20 10 10 10 10 1/4 1/8 1/8 1/4 1/8 2 1 1 2 1 20 10 10 20 10 1/4 1/4 1/8 1/8 1/8 2 2 1 1 1 20 20 10 10 10 1/4 1/4 1/8 1/4 1/8 2 2 1 2 1 20 20 10 20 10 1/4 1/4 1/8 1/4 1/4 2 2 1 2 2 20 20 10 20 20 1/4 1/4 1/4 1/4 1/4 2 2 2 2 2 20 20 20 20 20 1/3 1/3 1/3 1/3 1/3 8/3 8/3 8/3 8/3 8/3 26 26 26 26 26 1/2 1/8 1/8 1/8 1/8 4 1 1 1 1 40 10 10 10 10 1/2 1/8 1/8 1/4 1/8 4 1 1 2 1 40 10 10 20 10 1/2 1/8 1/8 1/2 1/8 4 1 1 4 1 40 10 10 40 10 1/2 1/4 1/8 1/8 1/8 4 2 1 1 1 40 20 10 10 10 1/2 1/4 1/8 1/4 1/8 4 2 1 2 1 40 20 10 20 10 1/2 1/4 1/8 1/4 1/4 4 2 1 2 2 40 20 10 20 20 1/2 1/4 1/8 1/2 1/8 4 2 1 4 1 40 20 10 40 10 1/2 1/4 1/8 1/2 1/4 4 2 1 4 2 40 20 10 40 20 1/2 1/4 1/4 1/4 1/4 4 2 2 2 2 40 20 20 20 20 1/2 1/4 1/4 1/2 1/4 4 2 2 4 2 40 20 20 40 20 1/2 1/2 1/8 1/8 1/8 4 4 1 1 1 40 40 10 10 10 1/2 1/2 1/8 1/4 1/8 4 4 1 2 1 40 40 10 20 10 1/2 1/2 1/8 1/4 1/4 4 4 1 2 2 40 40 10 20 20 1/2 1/2 1/8 1/2 1/8 4 4 1 4 1 40 40 10 40 10 1/2 1/2 1/8 1/2 1/4 4 4 1 4 2 40 40 10 40 20 1/2 1/2 1/8 1/2 1/2 4 4 1 4 4 40 40 10 40 40 1/2 1/2 1/4 1/4 1/4 4 4 2 2 2 40 40 20 20 20 1/2 1/2 1/4 1/2 1/4 4 4 2 4 2 40 40 20 40 20 1/2 1/2 1/4 1/2 1/2 4 4 2 4 4 40 40 20 40 40 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 10 Page 59 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) PLL Multiplication Ratio I x8 FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz)* B P MI MP I B P MI Input MP Clock I B P MI MP 1/2 1/2 1/2 1/2 1/2 4 4 4 4 4 40 40 40 40 40 1/1 1/8 1/8 1/8 1/8 8 1 1 1 1 80 10 10 10 10 1/1 1/8 1/8 1/4 1/8 8 1 1 2 1 80 10 10 20 10 1/1 1/8 1/8 1/2 1/8 8 1 1 4 1 80 10 10 40 10 1/1 1/8 1/8 1/1 1/8 8 1 1 8 1 80 10 10 80 10 1/1 1/4 1/8 1/8 1/8 8 2 1 1 1 80 20 10 10 10 1/1 1/4 1/8 1/4 1/8 8 2 1 2 1 80 20 10 20 10 1/1 1/4 1/8 1/4 1/4 8 2 1 2 2 80 20 10 20 20 1/1 1/4 1/8 1/2 1/8 8 2 1 4 1 80 20 10 40 10 1/1 1/4 1/8 1/2 1/4 8 2 1 4 2 80 20 10 40 20 1/1 1/4 1/8 1/1 1/8 8 2 1 8 1 80 20 10 80 10 1/1 1/4 1/8 1/1 1/4 8 2 1 8 2 80 20 10 80 20 1/1 1/4 1/4 1/4 1/4 8 2 2 2 2 80 20 20 20 20 1/1 1/4 1/4 1/2 1/4 8 2 2 4 2 80 20 20 40 20 1/1 1/4 1/4 1/1 1/4 8 2 2 8 2 80 20 20 80 20 1/1 1/3 1/3 1/3 1/3 8 8/3 8/3 8/3 8/3 80 26 26 26 26 1/1 1/3 1/3 1/1 1/3 8 8/3 8/3 8 8/3 80 26 26 80 26 1/1 1/2 1/8 1/8 1/8 8 4 1 1 1 80 40 10 10 10 1/1 1/2 1/8 1/4 1/8 8 4 1 2 1 80 40 10 20 10 1/1 1/2 1/8 1/4 1/4 8 4 1 2 2 80 40 10 20 20 1/1 1/2 1/8 1/2 1/8 8 4 1 4 1 80 40 10 40 10 1/1 1/2 1/8 1/2 1/4 8 4 1 4 2 80 40 10 40 20 1/1 1/2 1/8 1/2 1/2 8 4 1 4 4 80 40 10 40 40 1/1 1/2 1/8 1/1 1/8 8 4 1 8 1 80 40 10 80 10 1/1 1/2 1/8 1/1 1/4 8 4 1 8 2 80 40 10 80 20 1/1 1/2 1/8 1/1 1/2 8 4 1 8 4 80 40 10 80 40 1/1 1/2 1/4 1/4 1/4 8 4 2 2 2 80 40 20 20 20 1/1 1/2 1/4 1/2 1/4 8 4 2 4 2 80 40 20 40 20 Page 60 of 964 10 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group PLL Multiplication Ratio I x8 Section 4 Clock Pulse Generator (CPG) FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz)* B P MI MP I B P MI Input MP Clock I B P MI MP 1/1 1/2 1/4 1/2 1/2 8 4 2 4 4 80 40 20 40 40 1/1 1/2 1/4 1/1 1/4 8 4 2 8 2 80 40 20 80 20 1/1 1/2 1/4 1/1 1/2 8 4 2 8 4 80 40 20 80 40 1/1 1/2 1/2 1/2 1/2 8 4 4 4 4 80 40 40 40 40 1/1 1/2 1/2 1/1 1/2 8 4 4 8 4 80 40 40 80 40 1/1 1/1 1/4 1/4 1/4 8 8 2 2 2 40 40 10 10 10 1/1 1/1 1/4 1/2 1/4 8 8 2 4 2 40 40 10 20 10 1/1 1/1 1/4 1/2 1/2 8 8 2 4 4 40 40 10 20 20 1/1 1/1 1/4 1/1 1/4 8 8 2 8 2 40 40 10 40 10 1/1 1/1 1/4 1/1 1/2 8 8 2 8 4 40 40 10 40 20 1/1 1/1 1/4 1/1 1/1 8 8 2 8 8 40 40 10 40 40 1/1 1/1 1/3 1/3 1/3 8 8 8/3 8/3 8/3 40 40 13 13 13 1/1 1/1 1/3 1/1 1/3 8 8 8/3 8 8/3 40 40 13 40 13 1/1 1/1 1/3 1/1 1/1 8 8 8/3 8 8 40 40 13 40 40 1/1 1/1 1/2 1/2 1/2 8 8 4 4 4 40 40 20 20 20 1/1 1/1 1/2 1/1 1/2 8 8 4 8 4 40 40 20 40 20 1/1 1/1 1/2 1/1 1/1 8 8 4 8 8 40 40 20 40 40 1/1 1/1 1/1 1/1 1/1 8 8 8 8 8 40 40 40 40 40 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 10 5 Page 61 of 964 Section 4 Clock Pulse Generator (CPG) SH7146 Group Notes: * Clock frequencies when the input clock frequency is assumed to be the shown value. 1. The PLL multiplication ratio is fixed at x8. The division ratio can be selected from x1, x1/2, x1/3, x1/4, and x1/8 for each clock by the setting in the frequency control register. 2. The output frequency of the PLL circuit is the product of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio (x8) of the PLL circuit. 3. The input to the divider is always the output from the PLL circuit. 4. The internal clock (I) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (x8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 80 MHz (maximum operating frequency). 5. The bus clock (B) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (x8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and equal to or lower than the internal clock (I) frequency. 6. The peripheral clock (P) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (x8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and equal to or lower than the bus clock (B) frequency. 7. When using the MTU2S and MTU2, the MTU2S clock (MI) frequency must be equal to or lower than the internal clock (I) frequency and equal to or higher than the MTU2 clock (MP) frequency. The MTU2 clock (MP) frequency must be equal to or lower than the MTU2S clock (MI) frequency and the bus clock (B) frequency, and equal to or higher than the peripheral clock frequency (P). The MTU2S clock (MI) frequency and MTU2 clock (MP) frequency are the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (x8) of the PLL circuit, and the division ratio of the divider. 8. The frequency of the CK pin is always be equal to the bus clock (B) frequency. Page 62 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 4.4 Section 4 Clock Pulse Generator (CPG) Register Descriptions The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 23, List of Registers. Table 4.5 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Frequency control register FRQCR R/W H'36DB H'FFFFE800 16 Oscillation stop detection control register OSCCR R/W H'00 H'FFFFE814 8 4.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the internal clock (I), bus clock (B), peripheral clock (P), MTU2S clock (MI), and MTU2 clock (MP). FRQCR can be accessed only in words. FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT overflow). Bit: 15 14 - Initial value: 0 R/W: R 13 0 R/W 1 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 12 11 IFC[2:0] 10 9 8 BFC[2:0] 1 R/W 0 R/W 1 R/W 7 6 5 PFC[2:0] 1 R/W 0 R/W 1 R/W 4 3 2 MIFC[2:0] 1 R/W 0 R/W 1 R/W 1 0 MPFC[2:0] 1 R/W 0 R/W 1 R/W 1 R/W Page 63 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IFC[2:0] 011 R/W Internal Clock (I) Frequency Division Ratio Specify the division ratio of the internal clock (I) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: x1 001: x1/2 010: x1/3 011: x1/4 100: x1/8 Other than above: Setting prohibited 11 to 9 BFC[2:0] 011 R/W Bus Clock (B) Frequency Division Ratio Specify the division ratio of the bus clock (B) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: x1 001: x1/2 010: x1/3 011: x1/4 100: x1/8 Other than above: Setting prohibited Page 64 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 4 Clock Pulse Generator (CPG) Bit Bit Name Initial Value R/W Description 8 to 6 PFC[2:0] 011 R/W Peripheral Clock (P) Frequency Division Ratio Specify the division ratio of the peripheral clock (P) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: x1 001: x1/2 010: x1/3 011: x1/4 100: x1/8 Other than above: Setting prohibited 5 to 3 MIFC[2:0] 011 R/W MTU2S Clock (MI) Frequency Division Ratio Specify the division ratio of the MTU2S clock (MI) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: x1 001: x1/2 010: x1/3 011: x1/4 100: x1/8 Other than above: Setting prohibited 2 to 0 MPFC[2:0] 011 R/W MTU2 Clock (MP) Frequency Division Ratio Specify the division ratio of the MTU2 clock (MP) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: x1 001: x1/2 010: x1/3 011: x1/4 100: x1/8 Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 65 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) 4.4.2 Oscillation Stop Detection Control Register (OSCCR) OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in bytes. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - OSC STOP - OSC ERS 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 OSCSTOP 0 R Oscillation Stop Detection Flag [Setting conditions] * When a stop in the clock input is detected during normal operation * When software standby mode is entered [Clearing conditions] 1 0 R * By a power-on reset input through the RES pin * When software standby mode is canceled Reserved This bit is always read as 0. The write value should always be 0. 0 OSCERS 0 R/W Oscillation Stop Detection Flag Output Select Selects whether to output the oscillation stop detection flag signal through the WDTOVF pin. 0: Outputs only the WDT overflow signal through the WDTOVF pin 1: Outputs the WDT overflow signal and the oscillation stop detection flag signal through the WDTOVF pin Page 66 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 4.5 Section 4 Clock Pulse Generator (CPG) Changing Frequency Selecting division ratios for the frequency divider can change the frequencies of the internal clock (I), bus clock (B), peripheral clock (P), MTU2S clock (MI), and MTU2 clock (MP). This is controlled by software through the frequency control register (FRQCR). The following describes how to specify the frequencies. 1. In the initial state, IFC2 to IFC0 = H'011 (x1/4), BFC2 to BFC0 = H'011 (x1/4), PFC2 to PFC0 = H'011 (x1/4), MIFC2 to MIFC0 = H'011 (x1/4), and MPFC2 to MPFC0 = H'011 (x1/4). 2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM. 3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, MIFC2 to MIFC0, and MPFC2 to MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at x8, the frequencies are determined only be selecting division ratios. When specifying the frequencies, satisfy the following condition: internal clock (I) bus clock (B) peripheral clock (P). When using the MTU2S clock and MTU2 clock, specify the frequencies to satisfy the following condition: internal clock (I) MTU2S clock (MI) MTU2 clock (MP) peripheral clock (P) and bus clock (B) MTU2 clock (MP). Code to rewrite values of FRQCR should be executed in the on-chip ROM or on-chip RAM. 4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will change after (1 to 24n) cyc + 11B + 7P. n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/3, 1/4, or 1/8) cyc: Clock obtained by dividing EXTAL by 8 with the PLL. Note: (1 to 24n) depends on the internal state. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 67 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) 4.6 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.6.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.6. Use a crystal resonator that has a resonance frequency of 5 to 12.5 MHz. It is recommended to consult the crystal resonator manufacturer concerning the compatibility of the crystal resonator and the LSI. CL1 EXTAL XTAL CL2 Rd CL1 = CL2 = 18 to 22 pF (Reference values) Figure 4.2 Connection of Crystal Resonator (Example) Table 4.6 Damping Resistance Values (Reference Values) Frequency (MHz) 5 8 10 12.5 Rd () (Reference values) 500 200 0 0 Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.7. CL L Rs XTAL EXTAL C0 Figure 4.3 Crystal Resonator Equivalent Circuit Page 68 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 4.7 Section 4 Clock Pulse Generator (CPG) Crystal Resonator Characteristics Frequency (MHz) 5 8 10 12.5 Rs Max. () (Reference values) 120 80 60 50 C0 Max. (pF) (Reference values) 7 7 7 7 4.6.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it when in software standby mode. During operation, make the external input clock frequency 5 to 12.5 MHz. When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing software standby mode, in order to ensure the PLL stabilization time. EXTAL XTAL External clock input Open state Figure 4.4 Example of External Clock Connection R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 69 of 964 Section 4 Clock Pulse Generator (CPG) 4.7 SH7146 Group Function for Detecting Oscillator Stop This CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or software standby mode is canceled. If the OSCERS bit is set to 1 at this time, an oscillation stop detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (pins to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2 and the TIOC3BS, TIOC3DS, and TIOC4AS to TIOC4DS signals in the MTU2S are assigned) can be placed in highimpedance state regardless of the PFC setting. For details, refer to appendix A, Pin States. Even in software standby mode, these pins can be placed in high-impedance state. For details, refer to appendix A, Pin States. These pins enter the normal state after software standby mode is canceled. Under an abnormal condition where oscillation stops while the LSI is not in software standby mode, LSI operations other than the oscillation stop detection function become unpredictable. In this case, even after oscillation is restarted, LSI operations including the above high-current pins become unpredictable. Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and operating voltage). Page 70 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 4 Clock Pulse Generator (CPG) 4.8 Usage Notes 4.8.1 Note on Crystal Resonator A sufficient evaluation at the user's site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user's board design. As the oscillator circuit's circuit constant will depend on the resonator and the floating capacitance of the mounting circuit, the value of each external circuit's component should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 4.8.2 Notes on Board Design Measures against radiation noise are taken in this LSI. If further reduction in radiation noise is needed, it is recommended to use a multiple layer board and provide a layer exclusive to the system ground. When using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. Avoid Signal A Signal B CL2 This LSI XTAL EXTAL CL1 Figure 4.5 Cautions for Oscillator Circuit Board Design R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 71 of 964 SH7146 Group Section 4 Clock Pulse Generator (CPG) A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. PLLVSS VCL CPB = 0.47 F* VCC CB = 0.1 F* VSS (Recommended values are shown.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry around PLL Page 72 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 5 Exception Handling Section 5 Exception Handling 5.1 Overview 5.1.1 Types of Exception Handling and Priority Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected at once, they are processed according to the priority. Table 5.1 Types of Exceptions and Priority Exception Exception Source Priority Reset Power-on reset High Manual reset Interrupt User break (break before instruction execution) Address error CPU address error (instruction fetch) Instruction General illegal instructions (undefined code) Illegal slot instruction (undefined code placed immediately after a 1 2 delayed branch instruction* or instruction that changes the PC value* ) Trap instruction (TRAPA instruction) Address error CPU address error (data access) Interrupt User break (break after instruction execution or operand break) Address error DTC address error (data access) Interrupt NMI IRQ On-chip peripheral modules Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 73 of 964 SH7146 Group Section 5 Exception Handling 5.1.2 Exception Handling Operations The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Timing for Exception Detection and Start of Exception Handling Exception Reset Timing of Source Detection and Start of Exception Handling Power-on reset Started when the RES pin changes from low to high or when the WDT overflows. Manual reset Started when the MRES pin changes from low to high or when the WDT overflows. Address error Detected during the instruction decode stage and started after the execution of the current instruction is completed. Interrupt Instruction Trap instruction Started by the execution of the TRAPA instruction. General illegal instructions Started when an undefined code placed at other than a delay slot (immediately after a delayed branch instruction) is decoded. Illegal slot instructions Started when an undefined code placed at a delay slot (immediately after a delayed branch instruction) or an instruction that changes the PC value is detected. When exception handling starts, the CPU operates Exception Handling Triggered by Reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC from the address H'00000000 and SP from the address H'00000004 when a power-on reset. PC from the address H'00000008 and SP from the address H'0000000C when a manual reset.). For details, see section 5.1.3, Exception Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program starts from the PC address fetched from the exception handling vector table. Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception handling, bits I3 to I0 are not affected. The start address is then fetched from the exception handling vector table and the program starts from that address. Page 74 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 5.1.3 Section 5 Exception Handling Exception Handling Vector Table Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception handling, the start addresses of the exception handling routines are fetched from the exception handling vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Vector Numbers and Vector Table Address Offsets Exception Handling Source Power-on reset Vector Number Vector Table Address Offset PC 0 H'00000000 to H'00000003 SP 1 H'00000004 to H'00000007 PC 2 H'00000008 to H'0000000B SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved for system use) 5 H'00000014 to H'00000017 Illegal slot instruction 6 H'00000018 to H'0000001B (Reserved for system use) 7 H'0000001C to H'0000001F Manual reset 8 H'00000020 to H'00000023 CPU address error 9 H'00000024 to H'00000027 DTC address error 10 H'00000028 to H'0000002B NMI 11 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 13 H'00000034 to H'00000037 Interrupt (Reserved for system use) : Trap instruction (user vector) 31 H'0000007C to H'0000007F 32 H'00000080 to H'00000083 : 63 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 : : H'000000FC to H'000000FF Page 75 of 964 SH7146 Group Section 5 Exception Handling Exception Handling Source Vector Number Vector Table Address Offset Interrupt IRQ0 64 H'00000100 to H'00000103 IRQ1 65 H'00000104 to H'00000107 IRQ2 66 H'00000108 to H'0000010B IRQ3 67 H'0000010C to H'0000010F 68 H'00000110 to H'00000113 69 H'00000114 to H'00000117 70 H'00000118 to H'0000011B 71 H'0000011C to H'0000011F 72 H'00000120 to H'00000123 (Reserved for system use) On-chip peripheral module* : : 255 Note: * H'000003FC to H'000003FF For details on the vector numbers and vector table address offsets of on-chip peripheral module interrupts, see table 6.3. Table 5.4 Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number) x 4 Address errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4 Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Page 76 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 5 Exception Handling 5.2 Resets 5.2.1 Types of Resets Resets have priority over any exception source. There are two types of resets: power-on resets and manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset State Internal State CPU, INTC On-Chip Peripheral Module POE, PFC, I/O Port Type RES WDT Overflow Power-on reset Low Initialized Initialized Initialized High Overflow High Initialized Initialized Initialized High Not overflowed Low Initialized Not initialized Not initialized Manual reset 5.2.2 MRES Power-On Reset Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during power-on reset mode. In the power-on reset state, power-on reset exception handling starts when driving the RES pin high after driving the pin low for the given time. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 77 of 964 Section 5 Exception Handling SH7146 Group Be certain to always perform power-on reset exception handling when turning the system power on. Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-on reset state. The frequency control register (FRQCR) in the clock pulse generator (CPG) and the watchdog timer (WDT) registers are not initialized by the reset signal generated by the WDT (these registers are only initialized by a power-on reset from the RES pin). If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in WTCSR is cleared to 0. When the power-on reset exception handling caused by the WDT is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in the PC and SP, then the program starts. 5.2.3 Manual Reset When the RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the oscillation settling time that is set in WDT when in software standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters manual reset status in the middle of a bus cycle, manual reset exception processing does not start until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus cycle ends. (Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets. Page 78 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 5 Exception Handling 5.3 Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Address Errors Instruction fetch CPU Instruction fetched from even address None (normal) Instruction fetched from odd address Address error occurs Instruction fetched from a space other than on-chip peripheral module space None (normal) Instruction fetched from on-chip peripheral module space Address error occurs Instruction fetched from external memory space in single chip mode Address error occurs Word data accessed from even address None (normal) Data read/write CPU or DTC R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs Byte or word data accessed in on-chip peripheral module space None (normal) Longword data accessed in 16-bit on-chip peripheral module space None (normal) Longword data accessed in 8-bit on-chip peripheral module space None (normal) External memory space accessed when in single chip mode Address error occurs Page 79 of 964 Section 5 Exception Handling 5.3.2 SH7146 Group Address Error Exception Source When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address of the instruction which caused an address error exception. When the instruction that caused the exception is placed in the delay slot, the address of the delayed branch instruction which is placed immediately before the delay slot. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the generated address error, and the program starts executing from that address. This branch is not a delayed branch. Page 80 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 5 Exception Handling 5.4 Interrupts 5.4.1 Interrupt Sources Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller (UBC) 1 IRQ IRQ0 to IRQ3 pins (external input) 4 On-chip peripheral module Multi-function timer pulse unit 2 (MTU2) 28 Multi-function timer pulse unit 2S (MTU2S) 13 Data transfer controller (DTC) 1 Watchdog timer (WDT) 1 A/D converter (A/D_0, A/D_1, and A/D_2) 3 Compare match timer (CMT_0 and CMT_1) 2 Serial communication interface (SCI_0, SCI_1, and SCI_2) 12 Port output enable (POE) 3 All interrupt sources are given different vector numbers and vector table address offsets. For details on vector numbers and vector table address offsets, see table 6.3. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 81 of 964 SH7146 Group Section 5 Exception Handling 5.4.2 Interrupt Priority The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the interrupt priority registers A, D to F, and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL) of the INTC as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA, IPRD to IPRF, and IPRH to IPRL, see section 6.3.4, Interrupt Priority Registers A, D to F, and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL). Table 5.8 Interrupt Priority Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. Can be masked. IRQ 0 to 15 Set with interrupt priority registers A, D to F, and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL). On-chip peripheral module 5.4.3 Interrupt Exception Handling When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception handling begins. In interrupt exception handling, the CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched from the exception handling vector table for the accepted interrupt, and program execution branches to that address and the program starts. For details on the interrupt exception handling, see section 6.6, Interrupt Operation. Page 82 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 5 Exception Handling 5.5 Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instruction TRAPA Illegal slot instructions* Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that changes the PC value Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Undefined code anywhere besides in a delay slot General illegal instructions* Note: 5.5.2 Instructions that changes the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR The operation is not guaranteed when undefined instructions other than H'F000 to H'FFFF are decoded. * Trap Instructions When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start address of the exception handling routine from the exception handling vector table that corresponds to the vector number specified in the TRAPA instruction, program execution branches to that address, and then the program starts. This branch is not a delayed branch. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 83 of 964 Section 5 Exception Handling 5.5.3 SH7146 Group Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the undefined code is decoded. Illegal slot exception handling also starts when an instruction that changes the program counter (PC) value is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the exception that occurred. Program execution branches to that address and the program starts. This branch is not a delayed branch. 5.5.4 General Illegal Instructions When an undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. Page 84 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 5.6 Section 5 Exception Handling Cases when Exceptions Are Accepted When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the exception is accepted. Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions Exception Occurrence Timing Address Error General Illegal Instruction Slot Illegal Instruction Trap Instruction Interrupt Instruction in delay slot x* x* x* 3 x* 4 Immediately after interrupt 1 disabled instruction* 2 2 [Legend] : Accepted x: Not accepted : Does not occur Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 2. An exception is accepted before the execution of a delayed branch instruction. However, when an address error or a slot illegal instruction exception occurs in the delay slot of the RTE instruction, correct operation is not guaranteed. 3. An exception is accepted after a delayed branch (between instructions in the delay slot and the branch destination). 4. An exception is accepted after the execution of the next instruction of an interrupt disabled instruction (before the execution two instructions after an interrupt disabled instruction). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 85 of 964 SH7146 Group Section 5 Exception Handling 5.7 Stack States after Exception Handling Ends The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Address error (when the instruction that caused an exception is placed in the delay slot) Stack State SP Address of delayed branch instruction 32 bits SR 32 bits Address of instruction that caused exception 32 bits SR 32 bits Address of instruction after executed instruction 32 bits SR 32 bits Address of instruction after TRAPA instruction 32 bits SR 32 bits Address error (other than above) SP Interrupt SP Trap instruction SP Page 86 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Types Section 5 Exception Handling Stack State Illegal slot instruction SP Address of delayed branch instruction 32 bits SR 32 bits Address of general illegal instruction 32 bits SR 32 bits General illegal instruction SP R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 87 of 964 Section 5 Exception Handling 5.8 Usage Notes 5.8.1 Value of Stack Pointer (SP) SH7146 Group The SP value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.2 Value of Vector Base Register (VBR) The VBR value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling When the SP value is not a multiple of 4, an address error will occur when stacking for exception handling (interrupts, etc.) and address error exception handling will start after the first exception handling is ended. Address errors will also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be passed to the handling routine for address error exception and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. When stacking the SR and PC values, the SP values for both are subtracted by 4, therefore, the SP value is still not a multiple of 4 after the stacking. The address value output during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is undefined. Page 88 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 5.8.4 Section 5 Exception Handling Notes on Slot Illegal Instruction Exception Handling Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. * Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot illegal instructions. * This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal instructions. The supporting status on our software products regarding this note is as follows: Compiler This instruction is not allocated in the delay slot in the compiler V.4 and its subsequent versions. Real-time OS for ITRON specifications 1. HI7000/4, HI-SH7 This instruction does not exist in the delay slot within the OS. 2. HI7000 This instruction is in part allocated to the delay slot within the OS, which may cause the slot illegal instruction exception handling in this LSI. 3. Others The slot illegal instruction exception handling may be generated in this LSI in a case where the instruction is described in assembler or when the middleware of the object is introduced. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 89 of 964 Section 5 Exception Handling Page 90 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features * 16 levels of interrupt priority * NMI noise canceller function * Occurrence of interrupt can be reported externally (IRQOUT pin) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 91 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. Input control IRQ1 IRQ2 IRQ3 CPU/DTC request determination DTC UBC WDT CMT MTU2 A/D SCI MTU2S POE (Interrupt request) (Interrupt request) (Interrupt request) Comparator Priority determination NMI IRQ0 CPU/DTC request determination IRQOUT Interrupt request SR I3 I2 I1 I0 CPU (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) DTCERA to DTCERE ICR0 IPR IRQCR Module bus Bus interface INTC [Legend] UBC: WDT: CMT: SCI: MTU2: MTU2S: A/D: POE: DTC: User break controller Watchdog timer Compare match timer Serial communication interface Multi-function timer pulse unit 2 Multi-function timer pulse unit 2S A/D converter Port output enable Data transfer controller ICR0: IRQCR: IRQSR: IPRA, IPRD to IPRF, IPRH to IPRL: SR: DTCERA to DTCERE: Internal bus IPRA, IPRD to IPRF, IPRH to IPRL IRQSR Interrupt control register 0 IRQ control register IRQ status register Interrupt priority registers A, D to F, and H to L Status register DTC enable registers A to E Figure 6.1 Block Diagram of INTC Page 92 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 6.2 Section 6 Interrupt Controller (INTC) Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Symbol I/O Function Non-maskable interrupt input pin NMI Input Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 Input Input of maskable interrupt request signals Interrupt request output pin IRQOUT Output Output of notification signal when an interrupt has occurred R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 93 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) 6.3 Register Descriptions The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 23, List of Registers. Table 6.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Interrupt control register 0 ICR0 R/W H'x000 H'FFFFE900 8, 16 IRQ control register IRQCR R/W H'0000 H'FFFFE902 8, 16 IRQ status register IRQSR R/W H'Fx00 H'FFFFE904 8, 16 Interrupt priority register A IPRA R/W H'0000 H'FFFFE906 8, 16 Interrupt priority register D IPRD R/W H'0000 H'FFFFE982 16 Interrupt priority register E IPRE R/W H'0000 H'FFFFE984 16 Interrupt priority register F IPRF R/W H'0000 H'FFFFE986 16 Interrupt priority register H IPRH R/W H'0000 H'FFFFE98A 16 Interrupt priority register I IPRI R/W H'0000 H'FFFFE98C 16 Interrupt priority register J IPRJ R/W H'0000 H'FFFFE98E 16 Interrupt priority register K IPRK R/W H'0000 H'FFFFE990 16 Interrupt priority register L IPRL R/W H'0000 H'FFFFE992 16 Page 94 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 6.3.1 Section 6 Interrupt Controller (INTC) Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - NMIE - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R NMIL Initial value: * R/W: R Note: * The initial value is 1 when the level on the NMI pin is high, and 0 when the level on the pin is low. Bit Initial Bit Name Value R/W Description 15 NMIL R NMI Input Level * Indicates the state of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: State of the NMI input is low 1: State of the NMI input is high 14 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select 0: Interrupt request is detected on the falling edge of the NMI input 1: Interrupt request is detected on the rising edge of the NMI input 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 95 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) 6.3.2 IRQ Control Register (IRQCR) IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ3. Bit: 15 14 13 12 11 10 9 8 - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8 All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 IRQ31S 0 R/W IRQ3 Sense Select 6 IRQ30S 0 R/W Set the interrupt request detection mode for pin IRQ3. 00: Interrupt request is detected at the low level of pin IRQ3 01: Interrupt request is detected at the falling edge of pin IRQ3 10: Interrupt request is detected at the rising edge of pin IRQ3 11: Interrupt request is detected at both the falling and rising edges of pin IRQ3 5 IRQ21S 0 R/W IRQ2 Sense Select 4 IRQ20S 0 R/W Set the interrupt request detection mode for pin IRQ2. 00: Interrupt request is detected at the low level of pin IRQ2 01: Interrupt request is detected at the falling edge of pin IRQ2 10: Interrupt request is detected at the rising edge of pin IRQ2 11: Interrupt request is detected at both the falling and rising edges of pin IRQ2 Page 96 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value R/W Description 3 IRQ11S 0 R/W IRQ1 Sense Select 2 IRQ10S 0 R/W Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the low level of pin IRQ1 01: Interrupt request is detected at the falling edge of pin IRQ1 10: Interrupt request is detected at the rising edge of pin IRQ1 11: Interrupt request is detected at both the falling and rising edges of pin IRQ1 1 IRQ01S 0 R/W IRQ0 Sense Select 0 IRQ00S 0 R/W Set the interrupt request detection mode for pin IRQ0. 00: Interrupt request is detected at the low level of pin IRQ0 01: Interrupt request is detected at the falling edge of pin IRQ0 10: Interrupt request is detected at the rising edge of pin IRQ0 11: Interrupt request is detected at both the falling and rising edges of pin IRQ0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 97 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) 6.3.3 IRQ Status register (IRQSR) IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ3 and the status of interrupt request. Bit: 15 14 13 12 - - - - Initial value: 1 R/W: R 1 R 1 R 1 R 11 10 9 8 IRQ3L IRQ2L IRQ1L IRQ0L * R * R * R * R 7 6 5 4 - - - - 0 R 0 R 0 R 0 R 3 2 1 0 IRQ3F IRQ2F IRQ1F IRQ0F 0 R/W 0 R/W 0 R/W 0 R/W Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low. Bit Bit Name Initial Value R/W 15 to 12 All 1 R Description Reserved These bits are always read as 1. The write value should always be 1. 11 IRQ3L * R Indicates the state of pin IRQ3. 0: State of pin IRQ3 is low 1: State of pin IRQ3 is high 10 IRQ2L * R Indicates the state of pin IRQ2. 0: State of pin IRQ2 is low 1: State of pin IRQ2 is high 9 IRQ1L * R Indicates the state of pin IRQ1. 0: State of pin IRQ1 is low 1: State of pin IRQ1 is high 8 IRQ0L * R Indicates the state of pin IRQ0. 0: State of pin IRQ0 is low 1: State of pin IRQ0 is high 7 to 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 98 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value R/W Description 3 IRQ3F 0 R/W Indicates the status of an IRQ3 interrupt request. * When level detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing condition] Driving pin IRQ3 high 1: An IRQ3 interrupt has been detected [Setting condition] Driving pin IRQ3 low * When edge detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing conditions] Writing 0 after reading IRQ3F = 1 Accepting an IRQ3 interrupt 1: An IRQ3 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ3 2 IRQ2F 0 R/W Indicates the status of an IRQ2 interrupt request. * When level detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing condition] Driving pin IRQ2 high 1: An IRQ2 interrupt has been detected [Setting condition] Driving pin IRQ2 low * When edge detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing conditions] Writing 0 after reading IRQ2F = 1 Accepting an IRQ2 interrupt 1: An IRQ2 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ2 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 99 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value R/W Description 1 IRQ1F 0 R/W Indicates the status of an IRQ1 interrupt request. * When level detection mode is selected 0: An IRQ1 interrupt has not been detected [Clearing condition] Driving pin IRQ1 high 1: An IRQ1 interrupt has been detected [Setting condition] Driving pin IRQ1 low * When edge detection mode is selected 0: An IRQ1 interrupt has not been detected [Clearing conditions] Writing 0 after reading IRQ1F = 1 Accepting an IRQ1 interrupt 1: An IRQ1 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ1 0 IRQ0F 0 R/W Indicates the status of an IRQ0 interrupt request. * When level detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing condition] Driving pin IRQ0 high 1: An IRQ0 interrupt has been detected [Setting condition] Driving pin IRQ0 low * When edge detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing conditions] Writing 0 after reading IRQ0F = 1 Accepting an IRQ0 interrupt 1: An IRQ0 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ0 Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low. Page 100 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 6.3.4 Section 6 Interrupt Controller (INTC) Interrupt Priority Registers A, D to F, and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL) Interrupt priority registers are nine 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000). Bit: 15 14 13 12 11 IPR[15:12] Initial value: 0 R/W: R/W 0 R/W 0 R/W 10 9 8 7 IPR[11:8] 0 R/W 0 R/W 0 R/W 6 5 4 3 IPR[7:4] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0 IPR[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 12 IPR[15:12] 0000 R/W Set priority levels for the corresponding interrupt source. 0 R/W 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 101 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value R/W Description 11 to 8 IPR[11:8] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 7 to 4 IPR[7:4] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) Page 102 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value R/W Description 3 to 0 IPR[3:0] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 103 of 964 Section 6 Interrupt Controller (INTC) 6.4 Interrupt Sources 6.4.1 External Interrupts SH7146 Group There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15. IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Use the IRQ sense select bits (IRQ31S, IRQ30S to IRQ01S, and IRQ00S) in the IRQ control register (IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority register A (IPRA). In the case that the low level detection is selected, an interrupt request signal is sent to the INTC while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when the following change on the IRQ pin is detected: from high to low in falling edge detection mode, from low to high in rising edge detection mode, and from low to high or from high to low in both edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been detected by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). An IRQ interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag after reading 1. In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of the IRQ3 to IRQ0 interrupts. Page 104 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) IRQSR.IRQnL Level detection Edge detection RESIRQn (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) S Q R IRQSR.IRQnF Distribution IRQn pins Selection IRQCR.IRQn1S IRQCR.IRQn0S CPU interrupt request DTC activation request n = 3 to 0 Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. Since a different interrupt vector is allocated to each interrupt source, the exception handling routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be allocated to individual on-chip peripheral modules in interrupt priority registers D to F and H to L (IPRD to IPRF and IPRH to IPRL). On-chip peripheral module interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.4.3 User Break Interrupt A user break interrupt has a priority level of 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see section 7, User Break Controller (UBC). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 105 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Handling Vector Table Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated from the vector numbers and vector table address offsets. For interrupt exception handling, the start address of the exception handling routine is fetched from the vector table address in the vector table. For the details on calculation of vector table addresses, see table 5.4. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A, D to F and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL). However, when interrupt sources whose priority levels are allocated with the same IPR are requested, the interrupt of the smaller vector number has priority. This priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order shown in table 6.3. Table 6.3 Interrupt Source Interrupt Exception Handling Vectors and Priorities Vector Table Starting Address IPR 12 H'00000030 NMI 11 H'0000002C IRQ0 64 H'00000100 IPRA15 to IPRA12 IRQ1 65 H'00000104 IPRA11 to IPRA8 IRQ2 66 H'00000108 IPRA7 to IPRA4 IRQ3 67 H'0000010C IPRA3 to IPRA0 TGIA_0 88 H'00000160 IPRD15 to IPRD12 TGIB_0 89 H'00000164 TGIC_0 90 H'00000168 TGID_0 91 H'0000016C TCIV_0 92 H'00000170 TGIE_0 93 H'00000174 TGIF_0 94 H'00000178 User break External pin MTU2_0 Page 106 of 964 Default Priority Vector No. Name High IPRD11 to IPRD8 Low R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority MTU2_1 TGIA_1 96 H'00000180 High TGIB_1 97 H'00000184 TCIV_1 100 H'00000190 TCIU_1 101 H'00000194 TGIA_2 104 H'000001A0 TGIB_2 105 H'000001A4 TCIV_2 108 H'000001B0 TCIU_2 109 H'000001B4 TGIA_3 112 H'000001C0 TGIB_3 113 H'000001C4 TGIC_3 114 H'000001C8 TGID_3 115 H'000001CC MTU2_2 MTU2_3 MTU2_4 MTU2_5 POE (MTU2) MTU2S_3 IPRD3 to IPRD0 IPRE15 to IPRE12 IPRE11 to IPRE8 IPRE7 to IPRE4 TCIV_3 116 H'000001D0 IPRE3 to IPRE0 TGIA_4 120 H'000001E0 IPRF15 to IPRF12 TGIB_4 121 H'000001E4 TGIC_4 122 H'000001E8 TGID_4 123 H'000001EC TCIV_4 124 H'000001F0 IPRF11 to IPRF8 TGIU_5 128 H'00000200 IPRF7 to IPRF4 TGIV_5 129 H'00000204 TGIW_5 130 H'00000208 OEI1 132 H'00000210 OEI3 133 H'00000214 TGIA_3S 160 H'00000280 TGIB_3S 161 H'00000284 TGIC_3S 162 H'00000288 TGID_3S 163 H'0000028C TCIV_3S 164 H'00000290 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 IPRD7 to IPRD4 IPRF3 to IPRF0 IPRH7 to IPRH4 IPRH3 to IPRH0 Low Page 107 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority MTU2S_4 TGIA_4S 168 H'000002A0 High TGIB_4S 169 H'000002A4 TGIC_4S 170 H'000002A8 TGID_4S 171 H'000002AC IPRI15 to IPRI12 TCIV_4S 172 H'000002B0 IPRI11 to IPRI8 TGIU_5S 176 H'000002C0 IPRI7 to IPRI4 TGIV_5S 177 H'000002C4 TGIW_5S 178 H'000002C8 POE (MTU2S) OEI2 180 H'000002D0 IPRI3 to IPRI0 CMT_0 CMI_0 184 H'000002E0 IPRJ15 to IPRJ12 CMT_1 CMI_1 188 H'000002F0 IPRJ11 to IPRJ8 WDT ITI 196 H'00000310 IPRJ3 to IPRJ0 A/D_0 and A/D_1 ADI_0 200 H'00000320 IPRK15 to IPRK12 ADI_1 201 H'00000324 A/D_2 ADI_2 204 H'00000330 IPRK11 to IPRK8 SCI_0 ERI_0 216 H'00000360 IPRL15 to IPRL12 RXI_0 217 H'00000364 TXI_0 218 H'00000368 TEI_0 219 H'0000036C ERI_1 220 H'00000370 RXI_1 221 H'00000374 TXI_1 222 H'00000378 TEI_1 223 H'0000037C ERI_2 224 H'00000380 RXI_2 225 H'00000384 TXI_2 226 H'00000388 TEI_2 227 H'0000038C MTU2S_5 SCI_1 SCI_2 Page 108 of 964 IPRL11 to IPRL8 IPRL7 to IPRL4 Low R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 6.6 Interrupt Operation 6.6.1 Interrupt Sequence Section 6 Interrupt Controller (INTC) The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from interrupt requests sent, according to the priority levels set in interrupt priority registers A, D to F, and H to L (IPRA, IPRD to IPRF, and IPRH to IPRL). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority shown in table 6.3. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling. 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR. 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in 5. above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the IRQOUT pin holds low level. 9. The CPU reads the start address of the exception handling routine from the exception vector table for the accepted interrupt, branches to that address, and starts executing the program. This branch is not a delayed branch. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 109 of 964 Section 6 Interrupt Controller (INTC) Notes: SH7146 Group The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (IRQSR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. Page 110 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Program execution state Interrupt? No Yes User break? No Yes No NMI? Yes No Level 15 interrupt? Yes I3 to I0 level 14? Yes No Yes No No Level 14 interrupt? I3 to I0 level 14? Yes Yes Level 1 interrupt? I3 to I0 level 13? No Yes No Yes I3 to I0 = level 0? No IRQOUT = low *1*3 Save SR to stack Save PC to stack Copy interrupt level to I3 to I0 IRQOUT = high *2*3 Read exception vector table Branch to exception handling routine Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU 1. IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1). Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3-I0 of SR. 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the CPU, the IRQOUT pin holds low level. 3. The IRQOUT pin change timing depends on a frequency dividing ratio between the internal (I) and bus (B) clocks. This flowchart shows that the frequency dividing ratios of the internal (I) and bus (B) clocks are the same. Figure 6.3 Interrupt Sequence Flowchart R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 111 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Handling Figure 6.4 shows the stack after interrupt exception handling. Address 4n - 8 PC*1 32 bits 4n - 4 SR 32 bits SP*2 4n Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Handling 6.7 Interrupt Response Time Table 6.4 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Page 112 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 6.4 Section 6 Interrupt Controller (INTC) Interrupt Response Time Number of Cycles Item NMI IRQ Peripheral Modules DTC active judgment 2 x Bcyc 1 x Pcyc Interrupt priority decision and comparison with mask bits in SR 1 x Icyc + 2 x Pcyc 1 x Icyc + 1 x Pcyc 1 x Icyc + 2 x Pcyc Wait for completion of sequence currently being executed by CPU X ( 0) X ( 0) X ( 0) The longest sequence is for interrupt or addresserror exception handling (X = 7 x Icyc + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Time from start of interrupt exception handling until fetch of first instruction of exception handling routine starts 8 x Icyc + m1 + m2 + m3 8 x Icyc + m1 + m2 + m3 8 x Icyc + m1 + m2 + m3 Performs the saving PC and SR, and vector address fetch. Interrupt response time 9 x Icyc + 3 x 9 x Icyc + 2 x 9 x Icyc + 1 x Pcyc + m1 + m2 Pcyc +2 x Bcyc + Pcyc + m1 + m2 + m3 + X m1 + m2 + m3 + + m3 + X X Notes: * Total: Minimum*: 12 x Icyc + 2 x Pcyc 12 x Icyc + 1 x Pcyc + 2 x Bcyc 12 x Icyc + 3 x Pcyc Maximum: 16 x Icyc + 2 x Pcyc + 2 x (m1 + m2 + m3) + m4 16 x Icyc + 1 x Pcyc + 2 x Bcyc + 2 x (m1 + m2 + m3) + m4 16 x Icyc + 3 x Pcyc + 2 x (m1 + m2 + m3) + m4 SR, PC, and vector table are all in on-chip RAM. In the case that m1 = m2 = m3 = m4 = 1 x Icyc. m1 to m4 are the number of cycles needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Remarks Page 113 of 964 SH7146 Group Section 6 Interrupt Controller (INTC) 6.8 Data Transfer with Interrupt Request Signals The following data transfers can be done using interrupt request signals: * Activate DTC only; CPU interrupts depend on DTC settings The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The conditions for clearing DTCE and interrupt source flag are shown below. DTCE clear condition = DTC transfer end * DTCECLR Interrupt source flag clear condition = DTC transfer end * DTCECLR where DTCECLR = DISEL + counter 0 Figures 6.5 and 6.6 show control block diagrams. Standby control IRQ edge detector (in standby mode) Standby cancel determination Interrupt controller IRQ pin Interrupt priority determination IRQ detection Interrupt request to CPU DTC DTC activation request DTCER DTCE clear DTCECLR Transfer end IRQ flag clear by DTC Figure 6.5 IRQ Interrupt Control Block Diagram Page 114 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 6 Interrupt Controller (INTC) Interrupt controller Interrupt priority determination Interrupt source Interrupt request to CPU DTC DTC activation request DTCER DTCE clear Interrupt source flag clear Interrupt source flag clear by DTC DTCECLR Transfer end Figure 6.6 On-Chip Module Interrupt Control Block Diagram 6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation and CPU Interrupts 1. For DTC, set the corresponding DTCE bits and DISEL bits to 1. 2. When an interrupt occurs, an activation request is sent to the DTC. 3. When completing a data transfer, the DTC clears the DTCE bit to 0 and sends an interrupt request to the CPU. The activation source is not cleared. 4. The CPU clears the interrupt source in the interrupt handling routine then checks the transfer counter value. When the transfer counter value is not 0, the CPU sets the DTCE bit to 1 and allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary end processing in the interrupt processing routine. 6.8.2 Handling Interrupt Request Signals as Sources for DTC Activation, but Not CPU Interrupts 1. For DTC, set the corresponding DTCE bits to 1 and clear the DISEL bits to 0. 2. When an interrupt occurs, an activation request is sent to the DTC. 3. When completing a data transfer, the DTC clears the activation source. No interrupt request is sent to the CPU because the DTCE bit is held at 1. 4. However, when the transfer counter value = 0, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU. 5. The CPU performs the necessary end processing in the interrupt handling routine. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 115 of 964 Section 6 Interrupt Controller (INTC) 6.8.3 SH7146 Group Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not DTC Activation 1. For DTC, clear the corresponding DTCE bits to 0. 2. When an interrupt occurs, an interrupt request is sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt handling routine. 6.9 Usage Note The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction. Page 116 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. In the masked ROM version, only the L bus instruction fetch address break (two channels) can be set. 7.1 Features The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle). * Address Comparison bits are maskable in 1-bit units. One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected. * Data 32-bit maskable. One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected. * Bus cycle Instruction fetch or data access * Read/write * Operand size Byte, word, and longword 2. A user-designed user-break interrupt exception processing routine can be run. 3. In an instruction fetch cycle, it can be selected that a user break is set before or after an instruction is executed. 12 4. Maximum repeat times for the break condition (only for channel B): 2 - 1 times. 5. Eight pairs of branch source/destination buffers. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 117 of 964 SH7146 Group Section 7 User Break Controller (UBC) Figure 7.1 shows a block diagram of the UBC. LDB Access IDB control IAB LAB Internal bus Access comparator BBRA BARA Address comparator BAMRA BDRA * Data * comparator BDMRA * Channel A Access comparator BBRB BARB Address comparator BAMRB BDRB * Data * comparator BDMRB * Channel B BETR * BRSR * PC trace * BRDR * Control User break interrupt request CPU state signals [Legend] BBRA: BARA: BAMRA: BDRA: BDMRA: BBRB: BARB: BAMRB: BRCR Break bus cycle register A Break address register A Break address mask register A Break data register A Break data mask register A Break bus cycle register B Break address register B Break address mask register B BDRB: BDMRB: BETR: BRSR: BRDR: BRCR: Break data register B Break data mask register B Execution times break register Branch source register Branch destination register Break control register Note: * Supported only by the F-ZTAT version. Figure 7.1 Block Diagram of UBC Page 118 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.2 Section 7 User Break Controller (UBC) Input/Output Pins Table 7.1 shows the UBC pin configuration. Table 7.1 Pin Configuration Pin Name Symbol I/O User break trigger output UBCTRG Output UBC condition match trigger output pin. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Function Page 119 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3 Register Descriptions The user break controller has the following registers. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 7.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Break address register A BARA R/W H'00000000 H'FFFFF300 32 Break address mask register A BAMRA R/W H'00000000 H'FFFFF304 32 Break bus cycle register A BBRA R/W H'0000 H'FFFFF308 16 Break data register A BDRA* R/W H'00000000 H'FFFFF310 32 Break data mask register A BDMRA* R/W H'00000000 H'FFFFF314 32 Break address register B BARB R/W H'00000000 H'FFFFF320 32 Break address mask register B BAMRB R/W H'00000000 H'FFFFF324 32 Break bus cycle register B BBRB R/W H'0000 H'FFFFF328 16 Break data register B BDRB* R/W H'00000000 H'FFFFF330 32 Break data mask register B BDMRB* R/W H'00000000 H'FFFFF334 32 Break control register BRCR R/W H'00000000 H'FFFFF3C0 32 Branch source register BRSR* R H'0xxxxxxx H'FFFFF3D0 32 Branch destination register BRDR* R H'0xxxxxxx H'FFFFF3D4 32 R/W H'0000 H'FFFFF3DC 16 Execution times break register BETR* Note: * Supported only in the F-ZTAT version. Page 120 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.3.1 Section 7 User Break Controller (UBC) Break Address Register A (BARA) BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 Initial value: 0 R/W: R/W 0 R/W Bit Bit Name 31 to 0 BAA31 to BAA 0 7.3.2 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Address A Store the address on the LAB or IAB specifying break conditions of channel A. Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 Initial value: 0 R/W: R/W 0 R/W 0 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 BAMA8 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 121 of 964 SH7146 Group Section 7 User Break Controller (UBC) Initial Value Bit Bit Name 31 to 0 BAMA31 to All 0 BAMA 0 R/W Description R/W Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 7.3.3 Break Bus Cycle Register A (BBRA) BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel A. Bit: 15 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 10 9 8 7 6 CPA2* CPA1* CPA0* CDA1* CDA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 5 4 IDA1* IDA0 0 R/W 0 R/W 3 2 1 0 RWA1* RWA0 SZA1* SZA0* 0 R/W 0 R/W 0 R/W 0 R/W Note: * In the masked ROM version, this bit is used as a reserved bit. This bit is always read as 0. The write value should always be 0. Bit Bit Name 15 to 11 Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 10 CPA2* 0 R/W Bus Master Select A for I Bus 9 CPA1* 0 R/W 8 CPA0* 0 R/W Select the bus master when the I bus is selected as the bus cycle of the channel A break condition. However, when the L bus is selected as the bus cycle, the setting of the CPA2 to CPA0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: Setting prohibited 1xx: The DTC cycle is included in the break condition Page 122 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 7 CDA1* 0 R/W L Bus Cycle/I Bus Cycle Select A 6 CDA0 0 R/W Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle 5 IDA1* 0 R/W Instruction Fetch/Data Access Select A 4 IDA0 0 R/W Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 RWA1* 0 R/W Read/Write Select A 2 RWA0 0 R/W Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 SZA1* 0 R/W Operand Size Select A 0 SZA0* 0 R/W Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care. Note: * In the masked ROM version, these bits are reserved bits. They are always read as 0, and the write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 123 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3.4 Break Data Register A (BDRA) (F-ZTAT Version Only) BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select one of two data buses for break condition A. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 Initial value: 0 R/W: R/W 0 R/W Bit Bit Name 31 to 0 BDA31 to BDA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Data Bit A Stores data which specifies a break condition in channel A. If the I bus is selected in BBRA, the break data on IDB is set in BDA31 to BDA0. If the L bus is selected in BBRA, the break data on LDB is set in BDA31 to BDA0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRA as the break data. Page 124 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.3.5 Section 7 User Break Controller (UBC) Break Data Mask Register A (BDMRA) (F-ZTAT Version Only) BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data specified by BDRA. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BDMA31 to All 0 BDMA 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 BDMA8 BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W Break Data Mask A Specifies bits masked in the break data of channel A specified by BDRA (BDA31 to BDA0). 0: Break data BDAn of channel A is included in the break condition 1: Break data BDAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRA as the break mask data in BDRA. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 125 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3.6 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for break condition B. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 Initial value: 0 R/W: R/W 0 R/W Bit Bit Name 31 to 0 BAB31 to BAB 0 Page 126 of 964 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Address B Stores an address which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.3.7 Section 7 User Break Controller (UBC) Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BAMB31 to All 0 BAMB 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 BAMB8 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 127 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3.8 Break Data Register B (BDRB) (F-ZTAT Version Only) BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select one of the two data buses for break condition B. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 Initial value: 0 R/W: R/W 0 R/W Bit Bit Name 31 to 0 BDB31 to BDB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Data Bit B Stores data which specifies a break condition in channel B. If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. Page 128 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.3.9 Section 7 User Break Controller (UBC) Break Data Mask Register B (BDMRB) (F-ZTAT Version Only) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BDMB31 to All 0 BDMB 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 BDMB8 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRB as the break mask data in BDRB. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 129 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3.10 Break Bus Cycle Register B (BBRB) BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit: 15 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 10 9 8 7 6 CPB2* CPB1* CPB0* CDB1* CDB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 5 4 IDB1* IDB0 0 R/W 0 R/W 3 2 1 0 RWB1* RWB0 SZB1* SZB0* 0 R/W 0 R/W 0 R/W 0 R/W Note: * In the masked ROM version, this bit is used as a reserved bit. This bit is always read as 0. The write value should always be 0. Bit Bit Name Initial Value R/W Description 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 CPB2* 0 R/W Bus Master Select B for I Bus 9 CPB1* 0 R/W 8 CPB0* 0 R/W Select the bus master when the I bus is selected as the bus cycle of the channel B break condition. However, when the L bus is selected as the bus cycle, the setting of the CPB2 to CPB0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: Setting prohibited 1xx: The DTC cycle is included in the break condition 7 CDB1* 0 R/W L Bus Cycle/I Bus Cycle Select B 6 CDB0 0 R/W Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle Page 130 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 5 IDB1* 0 R/W Instruction Fetch/Data Access Select B 4 IDB0 0 R/W Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 RWB1* 0 R/W Read/Write Select B 2 RWB0 0 R/W Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 SZB1* 0 R/W Operand Size Select B 0 SZB0* 0 R/W Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care. Note: * In the masked ROM version, these bits are reserved bits. They are always read as 0, and the write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 131 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3.11 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A user break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channels A and B in comparison conditions. 5. Enable PC trace. 6. Select the UBCTRG output pulse width. 7. Specify whether to request the user break interrupt when channels A and B match with comparison conditions. BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Bit: 31 Initial value: R/W: 30 29 28 27 26 25 24 23 22 - - - - - - - - - - UTRGW[1:0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 11 10 9 8 7 6 5 - - 0 R 0 R Bit: 15 14 13 12 SCM FCA SCM FCB SCM FDA* SCM FDB* Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W PCTE* PCBA 0 R/W 0 R/W 21 DBEA* PCBB DBEB* 0 R/W 0 R/W 0 R/W 20 19 18 17 UBIDB - UBIDA 16 - 0 R/W 0 R 0 R/W 0 R 4 3 2 1 0 - SEQ* - - ETBE* 0 R 0 R/W 0 R 0 R 0 R/W Note: * In the masked ROM version, this bit is used as a reserved bit. This bit is always read as 0. The write value should always be 0. Page 132 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 31 to 22 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 UTRGW[1:0] 00 R/W UBCTRG Output Pulse Width Select Select the UBCTRG output pulse width when the break condition matches. 00: Setting prohibited. 01: UBCTRG output pulse width is 3 to 4 tBcyc 10: UBCTRG output pulse width is 7 to 8 tBcyc 11: UBCTRG output pulse width is 15 to 16 tBcyc Note: 19 UBIDB 0 R/W tBcyc indicates the period of one cycle of the external bus clock (B = CK). User Break Disable B Enables or disables the user break interrupt request when the channel B break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17 UBIDA 0 R/W User Break Disable A Enables or disables the user break interrupt request when the channel A break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied 16 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 133 of 964 SH7146 Group Section 7 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches 13 SCMFDA* 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches 12 SCMFDB* 0 R/W I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches 11 PCTE* 0 R/W PC Trace Enable 0: Disables PC trace 1: Enables PC trace Page 134 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 10 PCBA 0 R/W PC Break Select A Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9, 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 DBEA* 0 R/W Data Break Enable A Selects whether or not the data bus condition is included in the break condition of channel A. 0: No data bus condition is included in the condition of channel A 1: The data bus condition is included in the condition of channel A 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution 5 DBEB* 0 R/W Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 4 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 135 of 964 SH7146 Group Section 7 User Break Controller (UBC) Bit Bit Name Initial Value R/W Description 3 SEQ* 0 R/W Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2, 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ETBE* 0 R/W Number of Execution Times Break Enable Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break interrupt is requested when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B Note: * In the masked ROM version, these bits are reserved bits. They are always read as 0, and the write value should always be 0. Page 136 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.3.12 Section 7 User Break Controller (UBC) Execution Times Break Register (BETR) (F-ZTAT Version Only) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The 12 maximum number is 2 - 1 times. When a break condition is satisfied, it decreases BETR. A user break interrupt is requested when the break condition is satisfied after BETR becomes H'0001. Bit: 15 14 13 12 - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W BET[11:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15 to 12 All 0 R 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET[11:0] R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 All 0 R/W Number of Execution Times Page 137 of 964 SH7146 Group Section 7 User Break Controller (UBC) 7.3.13 Branch Source Register (BRSR) (F-ZTAT Version Only) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset or manual reset. Other bits are not initialized by a reset. The eight BRSR registers have a queue structure and a stored register is shifted at every branch. Bit: 31 30 29 28 SVF - - - 0 R 0 R 0 R 0 R R R Bit: 15 14 13 12 11 10 Initial value: R/W: 27 26 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 Initial value: R/W: R Bit Bit Name Initial Value R/W 31 SVF 0 R R R R 25 24 23 22 21 20 19 18 17 16 BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 R R R R R R R R R R R R 9 8 7 6 5 4 3 2 1 0 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 R R R R R R R R R R Description BRSR Valid Flag Indicates whether the branch source address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 Page 138 of 964 Undefined R Branch Source Address Store bits 27 to 0 of the branch source address. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.3.14 Section 7 User Break Controller (UBC) Branch Destination Register (BRDR) (F-ZTAT Version Only) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset or manual reset. Other bits are not initialized by a reset. The eight BRDR registers have a queue structure and a stored register is shifted at every branch. Bit: 31 30 29 28 DVF - - - 0 R 0 R 0 R 0 R R R Bit: 15 14 13 12 11 10 Initial value: R/W: 27 26 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 Initial value: R/W: R Bit Bit Name Initial Value R/W 31 DVF 0 R R R R 25 24 23 22 21 20 19 18 17 16 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 R R R R R R R R R R R R 9 8 7 6 5 4 3 2 1 0 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 R R R R R R R R R R Description BRDR Valid Flag Indicates whether a branch destination address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Undefined R Branch Destination Address Store bits 27 to 0 of the branch destination address. Page 139 of 964 Section 7 User Break Controller (UBC) 7.4 Operation 7.4.1 Flow of the User Break Operation SH7146 Group The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRA or BDRB). The masked data is set in the break data mask register (BDMRA or BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with B'00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. Before using them again, 0 must first be written to them and then reset flags. 4. There is a chance that matches of the break conditions set in channels A and B occur almost at the same time. In this case, there will be only one user break request to the CPU, but these two conditions match flags could be both set. 5. When selecting the I bus as the break condition, note the following: The CPU and DTC are connected to the I bus. The UBC monitors bus cycles generated by all bus masters that are selected by the CPA2 to CPA0 bits in BBRA or the CPB2 to CPB0 bits in BBRB, and compares the conditions for a match. I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles. The DTC only issue data access cycles for I bus cycles. If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the user break is to be accepted cannot be clearly defined. Page 140 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.4.2 Section 7 User Break Controller (UBC) User Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit in the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A user break cannot be generated as long as this bit is set to 1. 2. If the break condition matches when a user break on instruction fetch is specified so that the a break is generated before the execution of the instruction, the user break is generated at the point when it has become deterministic that the instruction will be executed after it is fetched. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break condition is set for the delay slot of a delayed branch instruction, the user break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the break condition is specified so that a user break is generated after execution of the instruction, the instruction that has met the break condition is executed and then the user break is generated before the next instruction is executed. As with pre-execution user breaks, this cannot be used with overrun fetch instructions. When this kind of break condition is set for a delayed branch instruction and its delay slot, a user break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDRA or BDRB) is ignored. Therefore, break data cannot be set for the user break of the instruction fetch cycle. 5. If the I bus is set for a user break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 7.4.1, Flow of the User Break Operation. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 141 of 964 Section 7 User Break Controller (UBC) 7.4.3 SH7146 Group User Break on Data Access Cycle 1. If the L bus is specified as a break condition for data access break, condition comparison is performed for the address (and data) accessed by the executed instructions, and a user break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a user break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 7.4.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 7.3. Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register (BBRA or BBRB). When data values are included in break conditions, a user break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register (BDRA or BDRB) and break data mask register (BDMRA or BDMRB). When word or byte is set, bits 31 to 16 of BDRA or BDRB and BDMRA or BDMRB are ignored. 4. If the L bus is selected, a user break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the user break will occur cannot be determined. When this kind of user Page 142 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) break occurs at a delayed branch instruction or its delay slot, the user break may not actually take place until the first instruction at the branch destination. 7.4.4 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0 and clear the condition match flag to 0 in channel A. 2. In sequential break specification, the L or I bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched. 7.4.5 Value of Saved Program Counter When a user break occurs, the address of the instruction from where execution is to be resumed is saved in the stack, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the user break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the user break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the stack. The instruction that matched the condition is not executed, and the user break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the stack. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the user break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the stack. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 143 of 964 Section 7 User Break Controller (UBC) SH7146 Group 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the user break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the stack. 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the stack. At which instruction the user break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the stack. If the instruction following the instruction that matches the break condition is a branch instruction, the user break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the stack. 7.4.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch. If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR. If a branch occurs due to an interrupt or exception, the value saved in stack due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. 3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. 4. Since eight pairs of queue are shared with the AUD, set the PCTE bit in BRCR to 1 after setting the MSTP25 bit in STBCR5 to 0 and the AUDSRST bit in STBCR6 to 1. Although the AUD is only available in the F-ZTAT version supporting full functions of the E10A, this setting should also be made in the normal F-ZTAT version. Page 144 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 7.4.7 Section 7 User Break Controller (UBC) Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) * Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00000404, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2) * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode <Channel A> Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 145 of 964 SH7146 Group Section 7 User Break Controller (UBC) <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed. (Example 1-3) * Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00027128, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word <Channel B> Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. (Example 1-4) * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode <Channel A> Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Page 146 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs. (Example 1-5) * Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00000500, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) <Channel B> Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword On channel A, a user break occurs after the instruction of address H'00000500 is executed four times and before the fifth time. On channel B, a user break occurs before an instruction of address H'00001000 is executed. (Example 1-6) * Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00008404, Address mask: H'00000FFF Data: H'00000000, Data mask: H'00000000 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 147 of 964 SH7146 Group Section 7 User Break Controller (UBC) Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. Break Condition Specified for L Bus Data Access Cycle: (Example 2-1) * Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00123456, Address mask: H'00000000 Data: H'12345678, Data mask: H'FFFFFFFF Bus cycle: L bus/data access/read (operand size is not included in the condition) <Channel B> Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Page 148 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) * Register specifications BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'01A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00314154, Address mask: H'00000000 Data: H'12345678, Data mask: H'FFFFFFFF Bus cycle: I bus (CPU cycle)/instruction fetch/read (operand size is not included in the condition) <Channel B> Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus (CPU cycle)/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314156 in the external memory space. On channel B, a user break occurs when byte data H'7x is written in address H'00055555 in the external memory space by the CPU. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 149 of 964 Section 7 User Break Controller (UBC) 7.5 SH7146 Group Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired user break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no user break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, Exception Handling. If an exception with higher priority occurs, the user break is not generated. Pre-execution break has the highest priority. When a post-execution break or data access break occurs simultaneously with a reexecution-type exception (including pre-execution break) that has higher priority, the reexecution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The user break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a user break does not occur, the condition match flag is set. 5. Note the following exception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error by data access, the CPU address error is given priority to the user break interrupt. Note that the UBC condition match flag is set in this case. 6. Note the following when a user break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the user break does not occur until the branch destination of the RTE instruction. 7. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. Page 150 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 7 User Break Controller (UBC) 8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a SLEEP instruction or one or two instructions before a SLEEP instruction. 9. When the DTC or DMAC is in operation, the UBC cannot correctly determine access to the external space by the CPU via the I bus. To determine access to the external space via the I bus in the above situation, select all bus masters. This makes it impossible to determine conditions of access with specified bus masters. However, when a bus master can be inferred from data values, the relevant data values can be included as a condition that indicates a particular bus master. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 151 of 964 Section 7 User Break Controller (UBC) Page 152 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request. 8.1 Features * Transfer possible over any number of channels: * Chain transfer Multiple rounds of data transfer is executed in response to a single activation source Chain transfer is only possible after data transfer has been done for the specified number of times (i.e. when the transfer counter is 0) * Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed * The transfer source and destination addresses can be specified by 32 bits to select a 4-Gbyte address space directly * Size of data for data transfer can be specified as byte, word, or longword * A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion * Read skip of the transfer information specifiable * Writeback skip executed for the fixed transfer source and destination addresses * Module stop mode specifiable * Short address mode specifiable * Bus release timing selectable from five types * Priority of the DTC activation selectable from two types Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to the data area*. Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in RAMCR must be set to 1. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 153 of 964 DTCHX10A_000020030600 SH7146 Group Section 8 Data Transfer Controller (DTC) DTC On-chip memory MRB SAR DAR Activation control CRA CRB CPU/DTC request determination DTC internal bus INTC Interrupt request Internal bus (32 bits) On-chip peripheral module Peripheral bus MRA Register control DTCERA to DTCERE CPU interrupt request DTCCR Interrupt control Interrupt source clear request DTCVBR External device (memory mapped) External bus Bus interface External memory Bus state controller [Legend] MRA, MRB: SAR: DAR: CRA, CRB: DTCERA to DTCERE: DTCCR: DTCVBR: DTC mode registers A, B DTC source address register DTC destination address register DTC transfer count registers A, B DTC enable registers A to E DTC control register DTC vector base register Figure 8.1 Block Diagram of DTC Page 154 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.2 Section 8 Data Transfer Controller (DTC) Register Descriptions DTC has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 23, List of Registers. These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer, it writes a set of updated transfer information back to the data area. On the other hand, DTCERA to DTCERE, DTCCR, and DTCVBR can be directly accessed by the CPU. Table 8.1 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size DTC enable register A DTCERA R/W H'0000 H'FFFFCC80 8, 16 DTC enable register B DTCERB R/W H'0000 H'FFFFCC82 8, 16 DTC enable register C DTCERC R/W H'0000 H'FFFFCC84 8, 16 DTC enable register D DTCERD R/W H'0000 H'FFFFCC86 8, 16 DTC enable register E DTCERE R/W H'0000 H'FFFFCC88 8, 16 DTC control register DTCCR R/W H'00 H'FFFFCC90 8 DTC vector base register DTCVBR R/W H'00000000 H'FFFFCC94 8, 16, 32 Bus function extending register BSCEHR R/W H'0000 H'FFFFE89A 8, 16 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 155 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register A (MRA) MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU. Bit: 7 6 5 MD[1:0] Initial value: R/W: - Bit Bit Name Initial Value 7, 6 MD[1:0] Undefined R/W - 4 3 Sz[1:0] - 2 1 0 - - - - SM[1:0] - - - Description DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 5, 4 Sz[1:0] Undefined DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited 3, 2 SM[1:0] Undefined Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0x: SAR is fixed (SAR writeback is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) Page 156 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Bit Bit Name Initial Value 1, 0 Undefined R/W Description Reserved The write value should always be 0. [Legend] x: Don't care 8.2.2 DTC Mode Register B (MRB) MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU. Bit: 7 CHNE Initial value: R/W: - Bit Bit Name Initial Value 7 CHNE Undefined R/W 6 5 CHNS DISEL - - 4 DTS - 3 2 DM[1:0] - - 1 0 - - - - Description DTC Chain Transfer Enable Specifies the chain transfer. For details, see section 8.5.6, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer 6 CHNS Undefined DTC Chain Transfer Select Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 157 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Bit Bit Name Initial Value 5 DISEL Undefined R/W Description DTC Interrupt Select When this bit is set to 1, an interrupt request is generated to the CPU every time a data transfer or a block transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfers end. 4 DTS Undefined DTC Transfer Mode Select Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area 3, 2 DM[1:0] Undefined Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0x: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0 Undefined Reserved The write value should always be 0. [Legend] x: Don't care Page 158 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.2.3 Section 8 Data Transfer Controller (DTC) DTC Source Address Register (SAR) SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. SAR cannot be accessed directly from the CPU. Bit: 31 Initial value: R/W: * - Bit: 15 Initial value: R/W: * - 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * : Undefined 8.2.4 DTC Destination Address Register (DAR) DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. DAR cannot be accessed directly from the CPU. Bit: 31 Initial value: R/W: * - Bit: 15 Initial value: R/W: * - 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * : Undefined R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 159 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU. Bit: 15 Initial value: R/W: * - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * : Undefined Page 160 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.2.6 Section 8 Data Transfer Controller (DTC) DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time a block of data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU. Bit: 15 Initial value: R/W: * - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * : Undefined R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 161 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) DTCER which is comprised of eight registers, DTCERA to DTCERE, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.2. Bit: 15 14 13 12 11 10 DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 DTCE15 0 R/W 14 DTCE14 0 R/W 13 DTCE13 0 R/W 12 DTCE12 0 R/W 11 DTCE11 0 R/W 10 DTCE10 0 R/W 9 DTCE9 0 R/W 8 DTCE8 0 R/W 7 DTCE7 0 R/W 6 DTCE6 0 R/W DTC Activation Enable 15 to 0 If set to 1, the corresponding interrupt source is specified as a DTC activation source. [Clearing conditions] * Writing 0 to the bit after reading 1 from it * When the DISEL bit is 1 and the data transfer has ended * When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended [Setting condition] * Writing 1 to the bit after reading 0 from it 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Page 162 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.2.8 Section 8 Data Transfer Controller (DTC) DTC Control Register (DTCCR) DTCCR specifies transfer information read skip. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - RRS RCHNE - - ERR 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/(W)* Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W 7 to 5 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 4 RRS 0 R/W DTC Transfer Information Read Skip Enable Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. However, when the DTPR bit in the bus function extending register (BSCEHR) is set to 1, transfer information read skip is not performed regardless of the setting of this bit. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match. 3 RCHNE 0 R/W Chain Transfer Enable After DTC Repeat Transfer Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 163 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 2, 1 All 0 R Reserved 0 ERR 0 R/(W)* Transfer Stop Flag These are read-only bits and cannot be modified. Indicates that the DTC address error or NMI interrupt request has occurred. If a DTC address error or NMI interrupt occurs while the DTC is active, address error handling or NMI interrupt handling processing is executed after the DTC has released the bus mastership. The DTC stops in the transfer information writing state after transferring data. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition] * Note: * When writing 0 after reading 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Page 164 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.2.9 Section 8 Data Transfer Controller (DTC) DTC Vector Base Register (DTCVBR) DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bit: 31 Initial value: 0 R/W: R/W Bit: 15 Initial value: 0 R/W: R/W Bit 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Name 31 to 12 0 R/W 0 R/W Initial Value R/W Description All 0 R/W All 0 R Bits 11 to 0 are always read as 0. The write value should always be 0. 11 to 0 8.2.10 Bus Function Extending Register (BSCEHR) BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and other functions. This register can be used to give higher priority to the transfer by the DTC and configure the functions that can reduce the number of cycles over which the DTC is active. For more details, see section 9.4.4, Bus Function Extending Register (BSCEHR). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 165 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.3 Activation Sources The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared. 8.4 Location of Transfer Information and DTC Vector Table Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2. Only in the case where all transfer sources/transfer destinations are in on-chip RAM and on-chip peripheral modules, short address mode can be selected by setting the DTSA bit in the bus function extending register (BSCEHR) to 1 (see section 9.4.4, Bus Function Extending Register (BSCEHR)). Normally, four longwords of transfer information has to be read. But if short address mode is selected, the size of transfer information is reduced to three longwords, which can shorten the period over which the DTC is active. The DTC reads the start address of the transfer information from the vector table for every activation source and reads the transfer information from this start address. Figure 8.3 shows correspondences between the DTC vector table and transfer information. Page 166 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Configuration of transfer information in normal address mode Configuration of transfer information in short address mode Lower addresses Lower addresses Start address 0 1 MRA 2 MRB Transfer information for one round of transfer (4 longwords) SAR DAR Chain transfer CRA MRA Start address 3 Reserved (0 write) CRB Chain transfer Reserved (write 0) MRB Transfer information for the 2nd round of transfer in chain transfer (4 longwords) SAR DAR 0 1 2 3 MRA SAR MRB DAR CRA Transfer information for one round of transfer (3 longwords) CRB MRA SAR MRB DAR CRA Transfer information for the 2nd round of transfer in chain transfer (3 longwords) CRB 4 bytes CRA CRB Note: Since the upper 8 bits of SAR and DAR are regarded as all 1, short address mode can be set only for transfer between on-chip peripheral modules and on-chip RAM. 4 bytes Figure 8.2 Transfer Information on Data Area Upper: DTCVBR Lower: H'400 + vector number x 4 DTC vector address +4 Vector table Transfer information (1) Transfer information (1) start address Transfer information (2) start address +4n Transfer information (2) : : : Transfer information (n) start address : : : 4 bytes Transfer information (n) Figure 8.3 Correspondence between DTC Vector Address and Transfer Information R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 167 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Table 8.2 shows correspondence between the DTC activation source and vector address. Table 8.2 Origin of Activation Source External pin Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source IRQ0 IRQ1 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 MTU2_5 Page 168 of 964 DTC Vector Address Vector Number Offset DTCE*1 64 65 H'500 H'504 DTCERA15 DTCERA14 Transfer Source Transfer Destination Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 IRQ2 66 H'508 DTCERA13 Arbitrary* 2 IRQ3 67 H'50C DTCERA12 Arbitrary* 2 Arbitrary* 2 TGIA_0 88 H'560 DTCERB15 Arbitrary* 2 Arbitrary* 2 TGIB_0 89 H'564 DTCERB14 Arbitrary* 2 Arbitrary* 2 TGIC_0 90 H'568 DTCERB13 Arbitrary* 2 Arbitrary* 2 TGID_0 91 H'56C DTCERB12 Arbitrary* 2 Arbitrary* 2 TGIA_1 96 H'580 DTCERB11 Arbitrary* 2 Arbitrary* 2 TGIB_1 97 H'584 DTCERB10 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 TGIA_2 104 H'5A0 DTCERB9 Arbitrary* 2 TGIB_2 105 H'5A4 DTCERB8 Arbitrary* 2 Arbitrary* 2 TGIA_3 112 H'5C0 DTCERB7 Arbitrary* 2 Arbitrary* 2 TGIB_3 113 H'5C4 DTCERB6 Arbitrary* 2 Arbitrary* 2 TGIC_3 114 H'5C8 DTCERB5 Arbitrary* 2 Arbitrary* 2 TGID_3 115 H'5CC DTCERB4 Arbitrary* 2 Arbitrary* 2 TGIA_4 120 H'5E0 DTCERB3 Arbitrary* 2 Arbitrary* 2 TGIB_4 121 H'5E4 DTCERB2 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 TGIC_4 122 H'5E8 DTCERB1 Arbitrary* 2 TGID_4 123 H'5EC DTCERB0 Arbitrary* 2 Arbitrary* 2 TCIV_4 124 H'5F0 DTCERC15 Arbitrary* 2 Arbitrary* 2 TGIU_5 128 H'600 DTCERC14 Arbitrary* 2 Arbitrary* 2 TGIV_5 129 H'604 DTCERC13 Arbitrary* 2 Arbitrary* 2 TGIW_5 130 H'608 DTCERC12 Arbitrary* 2 Arbitrary* 2 Priority High Low R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Origin of Activation Source MTU2S_3 Section 8 Data Transfer Controller (DTC) Activation Source TGIA_3S TGIB_3S MTU2S_4 MTU2S_5 DTC Vector Address Vector Number Offset DTCE*1 160 161 H'680 H'684 DTCERC3 DTCERC2 Transfer Source Transfer Destination Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 TGIC_3S 162 H'688 DTCERC1 Arbitrary* 2 TGID_3S 163 H'68C DTCERC0 Arbitrary* 2 Arbitrary* 2 TGIA_4S 168 H'6A0 DTCERD15 Arbitrary* 2 Arbitrary* 2 TGIB_4S 169 H'6A4 DTCERD14 Arbitrary* 2 Arbitrary* 2 TGIC_4S 170 H'6A8 DTCERD13 Arbitrary* 2 Arbitrary* 2 TGID_4S 171 H'6AC DTCERD12 Arbitrary* 2 Arbitrary* 2 TCIV_4S 172 H'6B0 DTCERD11 Arbitrary* 2 Arbitrary* 2 TGIU_5S 176 H'6C0 DTCERD10 Arbitrary* 2 Arbitrary* 2 Arbitrary* 2 TGIV_5S 177 H'6C4 DTCERD9 Arbitrary* 2 TGIW_5S 178 H'6C8 DTCERD8 Arbitrary* 2 Arbitrary* 2 CMT_0 CMI_0 184 H'6E0 DTCERD7 Arbitrary* 2 Arbitrary* 2 CMT_1 CMI_1 188 H'6F0 DTCERD6 Arbitrary* 2 Arbitrary* 2 A/D_0, A/D_1 ADI_0 200 H'720 DTCERD5 ADDR0 to ADDR3 Arbitrary* 2 ADI_1 201 H'724 DTCERD4 ADDR4 to ADDR7 Arbitrary* 2 A/D_2 ADI_2 204 H'730 DTCERD3 ADDR8 to ADDR15 Arbitrary* 2 SCI_0 RXI_0 217 H'764 DTCERE15 SCRDR_0 Arbitrary* 2 TXI_0 218 H'768 DTCERE14 Arbitrary* RXI_1 221 H'774 DTCERE13 SCRDR_1 2 SCI_1 SCI_2 2 TXI_1 222 H'778 DTCERE12 Arbitrary* RXI_2 225 H'784 DTCERE11 SCRDR_2 TXI_2 226 H'788 DTCERE10 Arbitrary* 2 Priority High SCTDR_0 Arbitrary* 2 SCTDR_1 Arbitrary* 2 SCTDR_2 Low Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. To leave software standby mode with an interrupt, write 0 to the corresponding DTCE bit. 2. An external memory, a memory-mapped external device, an on-chip memory, or an onchip peripheral module (except DTC, BSC, UBC, and FLASH) can be selected as the source or destination. Note that at least either the source or destination must be an onchip peripheral module; transfer cannot be done among an external memory, a memory-mapped external device, and an on-chip memory. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 169 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.5 Operation There are three transfer modes: normal, repeat, and block transfer modes. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. When activated, the DTC reads transfer information stored in the data are and transfers data according to the transfer information. After the data transfer is complete, it writes updated transfer information back to the data area. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 8.3 shows the DTC transfer modes. Table 8.3 DTC Transfer Modes Transfer Size of Data Transferred at One Memory Address Increment or Mode Transfer Request Decrement Transfer Count Normal Repeat* Block* 2 1 1 byte/word/longword Incremented/decremented by 1, 2, or 4, or fixed 1 to 65536 1 byte/word/longword Incremented/decremented by 1, 2, or 4, or fixed 1 to 256* Block size specified by CRAH (1 to 256 bytes/words/longwords) Incremented/decremented by 1, 2, or 4, or fixed 1 to 65536* 3 4 Notes: 1. Either source or destination is specified to repeat area. 2. Either source or destination is specified to block area. 3. After transfer of the specified transfer count, initial state is recovered to continue the operation. 4. Number of transfers of the specified block size of data. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 8.4 shows a flowchart of DTC operation, and table 8.4 summarizes the conditions for DTC transfers including chain transfer (combinations for performing the second and third transfers are omitted). Page 170 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Start Match & RRS = 1 Vector number comparison Not match | RRS = 0 Read DTC vector Next transfer Read transfer information Transfer data Update transfer information Update the start address of transfer information Write transfer information CHNE = 1 Yes No Transfer counter = 0 or DISEL = 1 Yes No CHNS = 0 Yes No Transfer counter = 0 Yes No DISEL = 1 Yes No Clear activation source flag Clear DTCER/request an interrupt to the CPU End Figure 8.4 Flowchart of DTC Operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 171 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included) 1st Transfer Transfer 2nd Transfer Transfer Mode 1 CHNE CHNS RCHNE DISEL Counter* Normal 0 0 Not 0 Transfer 1 CHNE CHNS RCHNE DISEL Counter* DTC Transfer Ends at 1st transfer 0 0 0 Ends at 1st 0 1 transfer Interrupt request to CPU 1 0 0 0 Not 0 Ends at 2nd transfer 0 0 0 Ends at 2nd 0 1 transfer Interrupt request to CPU 1 1 0 Not 0 Ends at 1st 1 1 1 Not 0 Ends at 1st transfer transfer Interrupt request to CPU 1 1 0 0 0 Not 0 Ends at 2nd transfer 0 0 0 Ends at 2nd 0 1 transfer Interrupt request to CPU Page 172 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) 1st Transfer Transfer 2nd Transfer Transfer Mode 1 CHNE CHNS RCHNE DISEL Counter* Repeat 0 0 Transfer 1 CHNE CHNS RCHNE DISEL Counter* DTC Transfer Ends at 1st transfer 0 1 Ends at 1st transfer Interrupt request to CPU 1 0 0 0 Ends at 2nd 0 1 Ends at 2nd transfer transfer Interrupt request to CPU 1 1 0 Not 0 Ends at 1st transfer 1 1 1 Not 0 Ends at 1st transfer Interrupt request to CPU 1 1 0 0 0* 2 0* 2 Ends at 1st transfer 1 1 0 1 Ends at 1st transfer Interrupt request to CPU 1 1 1 0* 2 0 0 Ends at 2nd transfer 0 1 Ends at 2nd transfer Interrupt request to CPU R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 173 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 1st Transfer Transfer 2nd Transfer Transfer Mode 1 CHNE CHNS RCHNE DISEL Counter* Block 0 0 Not 0 Transfer 1 CHNE CHNS RCHNE DISEL Counter* DTC Transfer Ends at 1st transfer 0 0 0 Ends at 1st 0 1 transfer Interrupt request to CPU 1 0 0 0 Not 0 Ends at 2nd transfer 0 0 0 Ends at 2nd 0 1 transfer Interrupt request to CPU 1 1 0 Ends at 1st transfer 1 1 1 Not 0 Ends at 1st transfer Interrupt request to CPU 1 1 1 0 0 0 Not 0 Ends at 2nd transfer 0 0 0 Ends at 2nd 0 1 transfer Interrupt request to CPU Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is written to the CRAL in repeat transfer mode Page 174 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.5.1 Section 8 Data Transfer Controller (DTC) Transfer Information Read Skip Function By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 8.5 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation. If the DTPR bit in the bus function extending register (BSCEHR) is set to 1, this function is always disabled. Clock (B) DTC activation request DTC request Skip transfer information read Internal address R Vector read Transfer information read Data transfer W Transfer information write R Data transfer W Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.5 Transfer Information Read Skip Timing (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 States) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 175 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.5.2 Transfer Information Writeback Skip Function By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. Table 8.5 shows the transfer information writeback skip condition and writeback skipped registers. Note that the CRA and CRB are always written back. The writeback of the MRA and MRB are always skipped. Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers SM1 DM1 SAR DAR 0 0 Skipped Skipped 0 1 Skipped Written back 1 0 Written back Skipped 1 1 Written back Written back 8.5.3 Normal Transfer Mode In normal transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in normal transfer mode. Table 8.6 Register Function in Normal Transfer Mode Register Function Written Back Value SAR Source address Incremented/decremented/fixed* DAR Destination address Incremented/decremented/fixed* CRA Transfer count A CRA - 1 CRB Transfer count B Not updated Note: * Transfer information writeback is skipped. Page 176 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Transfer source data area Transfer destination data area SAR DAR Transfer Figure 8.6 Memory Map in Normal Transfer Mode 8.5.4 Repeat Transfer Mode In repeat transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 8.7 lists the register function in repeat transfer mode. Figure 8.7 shows the memory map in repeat transfer mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 177 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Table 8.7 Register Function in Repeat Transfer Mode Written Back Value Register Function SAR CRAL is not 1 Source address CRAL is 1 Incremented/decremented/fixed* DTS = 0: Incremented/ decremented/fixed* DTS = 1: SAR initial value DAR Destination address Incremented/decremented/fixed* DTS = 0: DAR initial value DTS = 1: Incremented/ decremented/fixed* CRAH Transfer count storage CRAH CRAH CRAL Transfer count A CRAL - 1 CRAH CRB Transfer count B Not updated Not updated Note: * Transfer information writeback is skipped. Transfer source data area (specified as repeat area) Transfer destination data area SAR DAR Transfer Figure 8.7 Memory Map in Repeat Transfer Mode (When Transfer Source Is Specified as Repeat Area) Page 178 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.5.5 Section 8 Data Transfer Controller (DTC) Block Transfer Mode In block transfer mode, data are transferred in block units in response to a single activation request. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the block data transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in block transfer mode. Table 8.8 Register Function in Block Transfer Mode Register Function SAR Source address Written Back Value DTS = 0: Incremented/decremented/fixed* DTS = 1: SAR initial value DAR Destination address DTS = 0: DAR initial value DTS = 1: Incremented/decremented/fixed* CRAH Block size storage CRAH CRAL Block size counter CRAH CRB Block transfer counter CRB - 1 Note: * Transfer information writeback is skipped. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 179 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Transfer source data area SAR 1st block : : : Transfer destination data area (specified as block area) Transfer Block area DAR Nth block Figure 8.8 Memory Map in Block Transfer Mode (When Transfer Destination Is Specified as Block Area) 8.5.6 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed. Page 180 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Data area Transfer source data (1) Transfer information stored in user area Vector table Transfer destination data (1) DTC vector address Transfer information start address Transfer information CHNE = 1 Transfer information CHNE = 0 Transfer source data (2) Transfer destination data (2) Figure 8.9 Operation of Chain Transfer R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 181 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.5.7 Operation Timing Figures 8.10 to 8.15 show the DTC operation timings. Clock (B) DTC activation request DTC request Internal address R Vector read Transfer information read W Data Transfer information transfer write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.10 Example of DTC Operation Timing: Normal Transfer Mode or Repeat Transfer Mode (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) Clock (B) DTC activation request DTC request Internal address R Vector read Transfer information read W Data transfer R W Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2 (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) Page 182 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Clock (B) DTC activation request DTC request Internal address R Vector read Transfer information read W Data Transfer information transfer write R Transfer information read W Data Transfer information transfer write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.12 Example of DTC Operation Timing: Chain Transfer (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) Clock (B) DTC activation request DTC request Internal address R Vector read Transfer information read W Data Transfer information transfer write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.13 Example of DTC Operation Timing: Normal or Repeat Transfer in Short Address Mode (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 183 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Clock (B) DTC activation request DTC request Internal address R Vector read Transfer information read W Data Transfer information transfer write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.14 Example of DTC Operation Timing: Normal or Repeat Transfer with DTPR = 1 (Activated by On-Chip Peripheral Module; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) Clock (B) DTC activation request by IRQ pin DTC request Internal address R Vector read Transfer information read W Data Transfer information transfer write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Figure 8.15 Example of DTC Operation Timing: Normal or Repeat Transfer (Activated by IRQ; I: B: P =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) Page 184 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.5.8 Section 8 Data Transfer Controller (DTC) Number of DTC Execution Cycles Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the number of cycles required for each execution. Table 8.9 DTC Execution Status Mode Vector Read I Normal 1 0* 1 4 3* 4 0* 1 3 2* 2 1* Repeat 1 0* 1 4 3* 4 0* 1 3 2* 2 Block transfer 1 0* 1 4 3* 4 0* 1 3 2* 2 Transfer Information Read J Transfer Information Write K Data Read L Data Write M Internal Operation N 3 1 1 1 0* 1 1* 3 1 1 1 0* 1 1* 3 1*P 1*P 1 0* 1 [Legend] P: Block size (initial setting of CRAH and CRAL) Notes: 1. When transfer information read is skipped 2. When the SAR or DAR is in fixed mode 3. When the SAR and DAR are in fixed mode 4. When short address mode R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 185 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Table 8.10 Number of Cycles Required for Each Execution State Object to be Accessed On-Chip RAM*1/ROM*2 On-Chip I/O Registers Bus width 32 bits Access cycles status 16 bits 8 bits 16 bits 1 2 2P 2B 2B 1 2 5B 1B to 3B* * 9B Transfer information read SJ 1B to 3B* 1 9B Transfer information write Sk 1B to 3B* 1 Execu- Vector read SI tion External Devices*4 Byte data read SL 1B to 3B* * 1B to 3B*1 1 Word data read SL 1B to 3B* Longword data read SL 1B to 3B*1 1 2B* 5B 5 2B*5 1B + 2P*3 3B 3B 1B + 2P* 5B 3B 3 1B + 4P*3 1B + 2P* 9B 3 2B*5 Byte data write SM 1B to 3B* Word data write SM 1B to 3B*1 1B + 2P*3 2B*5 2B*5 Longword data write SM 1B to 3B*1 1B + 4P*3 2B*5 2B*5 Internal operation SN 2B* 5B 5 1 Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of I:B. Read Write I:B = 1:1 3B 3B I:B = 1:1/2 2B 1B I:B = 1:1/3 2B 1B I:B = 1:1/4 or less 1B 1B 2. Values for on-chip ROM. Number of cycles varies depending on the ratio of I:B.and are the same as on-chip RAM. Only vector read is possible. 3. The values in the table are those for the fastest case. Depending on the state of the internal bus, replace 1B by 1P in a slow case. 4. Values are different depending on the BSC register setting. The values in the table are the sample for the case with no wait cycles and the WM bit in CSnWCR = 1. 5. Values are different depending on the bus state. The number of cycles increases when many external wait cycles are inserted in the case where writing is frequently executed, such as block transfer, and when the external bus is in use because the write buffer cannot be used efficiently in such cases. For details on the write buffer, see section 9.5.7 (2), Access in View of LSI Internal Bus Master. Page 186 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) The number of execution cycles is calculated from the formula below. Note that means the sum of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in transfer information plus 1). Number of execution cycles = I * SI + (J * SJ + K * SK + L * SL + M * SM) + N * SN 8.5.9 DTC Bus Release Timing The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus mastership after a vector read, NOP cycle generation after a vector read, transfer information read, a single data transfer, or transfer information writeback. The DTC does not release the bus mastership during transfer information read, single data transfer, or transfer information writeback. The bus mastership release timing can be specified through the bus function extending register (BSCEHR). For details see section 9.4.4, Bus Function Extending Register (BSCEHR). The difference in bus mastership release timing according to the register setting is summarized in table 8.11. Settings other than settings 1 to 5 are not allowed. The setting must not be changed while the DTC is active. Figure 8.16 is a timing chart showing an example of bus mastership release timing. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 187 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) Table 8.11 DTC Bus Release Timing Bus Function Extending Register (BSCEHR) Bus Release Timing Setting (O: Bus is released; x: Bus is not released) After Setting Setting 1 Setting 2 DTLOCK CSSTP1 1 0 0 0 CSSTP2 3 * 0 3 After After a transfer single After write-back of transfer information vector NOP cycle information data Normal Continuous CSSTP3 DTBST read generation*1 read transfer transfer transfer 1 0 O O O O O O 3 0 x O x x O O 3 * Setting 3 0 1 * * 0 x x x x O O Setting 4*2 0 1 *3 *3 1 x x x x O x Setting 5 1 1 *3 1 0 O x O O O O Notes: 1. The bus mastership is only released for the external space access request from the CPU after a vector read. 2. There are following restrictions in setting 4. * Clock setting by the frequency control register (FRQCR) must be I:B:P:MI:MP = 8:4:4:4:4, 4:2:2:2:2, or 2:1:1:1:1. * Locate vector information in on-chip ROM or on-chip RAM. * Locate transfer information in on-chip RAM. * Transfer is allowed between on-chip RAM and on-chip peripheral module or between external memory and on-chip peripheral module. 3. Don't care. Page 188 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) Clock (B) DTC activation request 1 DTC activation request 2 DTC request Bus release timing [setting 5] Bus release timing [setting 3] Bus release timing [setting 4] Bus release timing [setting 1] Bus release timing [setting 2] R Internal address Vector read Transfer information read R W Data Transfer information Vector transfer write read Transfer information read W Data Transfer information transfer write [Legend] : Indicates bus release timing. : Bus mastership is only released for the external access request from the CPU. Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined. Figure 8.16 Example of DTC Operation Timing: Conflict of Two Activation Requests in Normal Transfer Mode (Activated by On-Chip Peripheral Module; I: B: P = 1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 189 of 964 SH7146 Group Section 8 Data Transfer Controller (DTC) 8.5.10 DTC Activation Priority Order In the case where multiple DTC activation requests are generated while the DTC is inactive, it is selectable whether the DTC starts transfer in the order of activation request generation or in the order of priority for DTC activation. This selection is made by the setting of the DTPR bit in the bus function extending register (BSCEHR). On the other hand, if multiple activation requests are generated while the DTC is active, transfer is performed according to the priority order for DTC activation. Figure 8.17 shows an example of DTC activation according to the priority. (1) DTPR = 0 DTC is inactive DTC is active Transfer is started for the request that is generated first Other than DTC Internal bus DTC (request 3) Transfer is performed according to the priority DTC (request 1) DTC (request 2) Priority determination DTC activation request 1 (High priority) DTC activation request 2 (Medium priority) DTC activation request 3 (Low priority) (2) DTPR =1 DTC is inactive DTC is active Transfer is performed according to the priority Internal bus Other than DTC DTC (request 1) Transfer is performed according to the priority DTC (request 2) DTC (request 3) Priority determination DTC activation request 1 (High priority) Priority determination DTC activation request 2 (Medium priority) DTC activation request 3 (Low priority) Figure 8.17 Example of DTC Activation in Accordance with Priority Page 190 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.6 Section 8 Data Transfer Controller (DTC) DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is shown in figure 8.18. DTC activation by interrupt Clear RRS bit in DTCCR to 0 [1] Set transfer information (MRA, MRB, SAR, DAR, CRA, CRB) [2] Set starts address of transfer information in DTC vector table [3] Set RRS bit in DTCCR to 1 [4] [1] Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information. Read skip is not performed when the DTC is activated after clearing the RRS bit. When updating transfer information, the RRS bit must be cleared. [2] Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer information in the data area. For details on setting transfer information, see section 8.2, Register Descriptions. For details on location of transfer information, see section 8.4, Location of Transfer Information and DTC Vector Table. [3] Set the start address of the transfer information in the DTC vector table. For details on setting DTC vector table, see section 8.4, Location of Transfer Information and DTC Vector Table. Set corresponding bit in DTCER to 1 [5] Set enable bit of interrupt request for activation source to 1 [6] [4] Setting the RRS bit to 1 performs a read skip of second time or later transfer information when the DTC is activated consecutively by the same interrupt source. Setting the RRS bit to 1 is always allowed. However, the value set during transfer will be valid from the next transfer. [5] Set the bit in DTCER corresponding to the DTC activation interrupt source to 1. For the correspondence of interrupts and DTCER, refer to table 8.2. The bit in DTCER may be set to 1 on the second or later transfer. In this case, setting the bit is not needed. Interrupt request generated [6] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. For details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. DTC activated Determine clearing method of activation source Clear corresponding bit in DTCER Clear activation source [7] [7] After the end of one data transfer, the DTC clears the activation source flag or clears the corresponding bit in DTCER and requests an interrupt to the CPU. The operation after transfer depends on the transfer information. For details, see section 8.2, Register Descriptions and figure 8.4. Corresponding bit in DTCER cleared or CPU interrupt requested Transfer end Figure 8.18 Activation of DTC by Interrupt R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 191 of 964 Section 8 Data Transfer Controller (DTC) 8.7 Examples of Use of the DTC 8.7.1 Normal Transfer Mode SH7146 Group An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. 8.7.2 Chain Transfer when Counter = 0 By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.19 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20. Page 192 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 8 Data Transfer Controller (DTC) 3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for resetting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer destination address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer destination address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU. Input circuit Transfer information located on the on-chip memory Input buffer 1st data transfer information Chain transfer (counter = 0) 2nd data transfer information Upper 8 bits of DAR Figure 8.19 Chain Transfer when Counter = 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 193 of 964 Section 8 Data Transfer Controller (DTC) 8.8 SH7146 Group Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or on completion of a single data transfer or a single block data transfer with the DISEL bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller. For details, refer to section 6.8, Data Transfer with Interrupt Request Signals. 8.9 Usage Notes 8.9.1 Module Standby Mode Setting Operation of the DTC can be disabled or enabled using the standby control register. The initial setting is for operation of the DTC to be disabled. DTC operation is disabled in module standby mode but register access is available. Module standby mode cannot be set while the DTC is activated. Before entering software standby mode or module standby mode, all DTCER registers must be cleared. For details, refer to section 22, Power-Down Modes. 8.9.2 On-Chip RAM Transfer information can be located in on-chip RAM. In this case, the RAME bit in RAMCR must not be cleared to 0. 8.9.3 DTCE Bit Setting To set a DTCE bit, disable the corresponding interrupt, read 0 from the bit, and then write 1 to it. While DTC transfer is in progress, do not modify the DTCE bits. 8.9.4 Chain Transfer When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the relevant register. 8.9.5 Transfer Information Start Address, Source Address, and Destination Address The transfer information start address to be specified in the vector table should be address 4n. Transfer information should be placed in on-chip RAM or external memory space. Page 194 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 8.9.6 Section 8 Data Transfer Controller (DTC) Access to DTC Registers through DTC Do not access the DTC registers by using DTC operation. 8.9.7 Notes on IRQ Interrupt as DTC Activation Source * The IRQ interrupt specified as a DTC activation source must not be used to cancel software standby mode. * The IRQ edge input in software standby mode must not be specified as a DTC activation source. * When a low level on the IRQ pin is to be detected, if the end of DTC transfer is used to request an interrupt to the CPU (transfer counter = 0 or DISEL = 1), the IRQ signal must be kept low until the CPU accepts the interrupt. 8.9.8 Notes on SCI as DTC Activation Sources * When the TXI interrupt from the SCI is specified as a DTC activation source, the TEND flag in the SCI must not be used as the transfer end flag. 8.9.9 Clearing Interrupt Source Flag The interrupt source flag set when the DTC transfer is completed should be cleared in the interrupt handler in the same way as for general interrupt source flags. For details, refer to section 6.9, Usage Note. 8.9.10 Conflict between NMI Interrupt and DTC Activation When a conflict occurs between the generation of the NMI interrupt and the DTC activation, the NMI interrupt has priority. Thus the ERR bit is set to 1 and the DTC is not activated. It takes 1 x Bcyc + 3 x Pcyc for determining DTC stop by NMI, 2 x Bcyc for determining DTC activation by IRQ, and 1 x Pcyc for determining DTC activation by peripheral modules. 8.9.11 Operation When a DTC Activation Request Is Cancelled While in Progress Once the DTC has accepted an activation request, the DTC does not accept the next activation request until the sequence of DTC processing that ends with writeback has been completed. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 195 of 964 Section 8 Data Transfer Controller (DTC) Page 196 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) Section 9 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM and other memory storage devices and external devices. 9.1 Features 1. External address space A maximum 1 Mbyte for each of two areas, CS0 and CS1 Can select the data bus width (8 or 16 bits) for each address space Controls the insertion of the wait state for each address space. Controls the insertion of the wait state for each read access and write access Can set the independent idling cycle in the continuous access for five cases: read-write (in same space/different space), read-read (in same space/different space), the first cycle is a write access. 2. Normal space interface Supports the interface that can directly connect to the SRAM R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 197 of 964 SH7146 Group Section 9 Bus State Controller (BSC) BACK BREQ Bus mastership controller Internal bus Figure 9.1 shows a block diagram of the BSC. CMNCR Internal master module Internal slave module CS0WCR CS0, CS1 Wait controller Area controller CS1WCR CS0BCR Module bus WAIT CS1BCR A19 to A0, D15 to D0 RD, WRH, WRL Memory controller BSC [Legend] CMNCR: Common control register CSnWCR: CSn space wait control register (n = 0 and 1) CSnBCR: CSn space bus control register (n = 0 and 1) Figure 9.1 Block Diagram of BSC Page 198 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 9.2 Section 9 Bus State Controller (BSC) Input/Output Pins The pin configuration of the BSC is listed in table 9.1. Table 9.1 Pin Configuration Name I/O A19 to A0 Output Address bus D15 to D0 I/O CS0 and CS1 Output Chip select RD Output Read pulse signal (read data output enable signal) WRH Output Indicates byte write through D15 to D8. WRL Output Indicates byte write through D7 to D0. WAIT Input External wait input BREQ Input Bus request input BACK Output Bus acknowledge output 9.3 Area Overview 9.3.1 Area Division Function Data bus In the architecture, this LSI has 32-bit address spaces. As listed in tables 9.2 to 9.4, this LSI can connect two areas to each type of memory, and it outputs chip select signals (CS0 and CS1) for each of them. CS0 is asserted during area 0 access. 9.3.2 Address Map The external address space has a capacity of 2 Mbytes and is used by dividing into two spaces. The memory to be connected and the data bus width are specified in each space. The address map for the entire address space is listed in tables 9.2 to 9.4. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 199 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Table 9.2 Address Map (Single-Chip Mode) Address Area H'00000000 to H'0003FFFF On-chip ROM H'00040000 to H'FFFF8FFF Reserved H'FFFF9000 to H'FFFFAFFF On-chip RAM H'FFFFB000 to H'FFFFBFFF Reserved H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Memory Type Capacity Bus Width 256 kbytes 32 bits 8 kbytes 32 bits 16 kbytes 8 or 16 bits Note: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. Only the on-chip ROM, on-chip RAM, and on-chip peripheral modules can be accessed; the other areas cannot be accessed. Page 200 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 9.3 Section 9 Bus State Controller (BSC) Address Map (SH7149 in On-Chip ROM-Enabled Mode) Address Area H'00000000 to H'0003FFFF On-chip ROM H'00040000 to H'01FFFFFF Reserved H'02000000 to H'020FFFFF CS0 space H'02100000 to H'03FFFFFF Reserved H'04000000 to H'040FFFFF CS1 space H'04100000 to H'FFFF8FFF Reserved H'FFFF9000 to H'FFFFAFFF On-chip RAM H'FFFFB000 to H'FFFFBFFF Reserved H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Capacity Bus Width 256 kbytes 32 bits Normal space 1 Mbyte 8 or 16 bits* Normal space 1 Mbyte 8 or 16 bits* 8 kbytes 32 bits 16 kbytes 8 or 16 bits Memory Type Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and onchip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 201 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Table 9.4 Address Map (SH7149 in On-Chip ROM-Disabled Mode) Bus Width Address Area Memory Type Capacity H'00000000 to H'000FFFFF CS0 space Normal space 1 Mbyte 8 or 16 1 bits* H'001FFFFF to H'03FFFFFF Reserved H'04000000 to H'040FFFFF CS1 space Normal space 1 Mbyte 8 or 16 2 bits* H'04100000 to H'FFFF8FFF Reserved H'FFFF9000 to H'FFFFAFFF On-chip RAM 8 kbytes 32 bits H'FFFFB000 to H'FFFFBFFF Reserved H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules 16 kbytes 8 or 16 bits Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting. Page 202 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 9.4 Section 9 Bus State Controller (BSC) Register Descriptions The BSC has the following registers. Refer to section 23, List of Registers, for details on the register addresses and register states in each operating mode. Do not access spaces other than CS0 until the termination of the memory interface setting. Table 9.5 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Common control register CMNCR R/W H'00001010 H'FFFFF000 32 CS0 space bus control register CS0BCR R/W H'36DB0600 H'FFFFF004 32 CS1 space bus control register CS1BCR R/W H'36DB0600 H'FFFFF008 32 CS0 space wait control register CS0WCR R/W H'00000500 H'FFFFF028 32 CS1 space wait control register CS1WCR R/W H'00000500 H'FFFFF02C 32 Bus function extending register BSCEHR R/W H'0000 H'FFFFE89A 8, 16 9.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Do not access external memory other than area 0 until the register initialization is complete. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 0 Initial value: R/W: Initial value: R/W: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - - - - - - - - - - - - - HIZMEM - 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R/W 0 R R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 16 Page 203 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 31 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 1 R Reserved This bit is always read as 1. The write value should always be 1. 11 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 1 R Reserved This bit is always read as 1. The write value should always be 1. 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HIZMEM 0 R/W Hi-Z Memory Control Specifies the pin state in software standby mode for A19 to A0, CSn, WRxx, and RD. While the bus is released, these pins are in high-impedance state regardless of this bit setting. 0: High impedance in software standby mode 1: Driven in software standby mode 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 204 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 9.4.2 Section 9 Bus State Controller (BSC) CSn Space Bus Control Register (CSnBCR) (n = 0 and 1) CSnBCR is a 32-bit readable/writable register that specifies the data bus width of the respective space, and the number of wait cycles between access cycles. Do not access external memory other than area 0 until the register initialization is complete. Bit: 31 30 29 28 - - 0 R 0 R 1 R/W Bit name: 15 Initial value: R/W: Initial value: R/W: IWW[1:0] 27 26 25 24 23 22 21 20 19 16 - IWRWS[1:0] - 1 R/W 0 R 1 R/W 1 R/W 0 R 1 R/W 1 R/W 0 R 1 R/W 1 R/W 0 R 1 R/W 1 R/W 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 - - - - 0 R 0 R 0 R 0 R 0 R BSZ[1:0] 1* R/W 1* R/W - 17 IWRWD[1:0] - IWRRD[1:0] 18 - IWRRS[1:0] Note: * When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that specify the bus width when a power-on reset is performed. Bit Bit Name Initial Value R/W 31, 30 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 29, 28 IWW[1:0] 11 R/W Specification for Idle Cycles between Write-Read/WriteWrite Cycles Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are write-read cycles and write-write cycles. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 27 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 205 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Initial Value Bit Bit Name 26, 25 IWRWD[1:0] 11 R/W Description R/W Specification for Idle Cycles between Read-Write Cycles in Different Spaces Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-write cycles in different spaces. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 24 0 R Reserved This bit is always read as 0. The write value should always be 0. 23, 22 IWRWS[1:0] 11 R/W Specification for Idle Cycles between Read-Write Cycles in the Same Space Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-write cycles in the same space. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 21 0 R Reserved This bit is always read as 0. The write value should always be 0. 20, 19 IWRRD[1:0] 11 R/W Specification for Idle Cycles between Read-Read Cycles in Different Spaces Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-read cycles in different spaces. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted Page 206 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 IWRRS[1:0] 11 R/W Specification for Idle Cycles between Read-Read Cycles in the Same Space Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-read cycles in the same space. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10, 9 BSZ[1:0] 11* R/W Data Bus Size Specification Specify the data bus sizes of spaces. 00: Setting prohibited 01: 8-bit size 10: 16-bit size 11: Setting prohibited Note: When the on-chip ROM is disabled, the data bus width in area 0 is specified through external input pins. The BSZ1 and BSZ0 bit setting in CS0BCR is ignored. 8 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that specify the bus width when a power-on reset is performed. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 207 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 and 1) CSnWCR specifies various wait cycles for memory accesses. Specify CSnWCR before accessing the target area. CSnWCR should be modified only after CSnBCR setting is completed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit: 15 12 11 10 9 8 7 0 Initial value: R/W: 14 13 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 19 All 0 R Reserved SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 18 17 16 WW[2:0] 6 5 4 3 2 1 WM - - - - HW[1:0] 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Wait Cycles in Write Access Specify the number of cycles required for write access. 000: The same cycles as WR3 to WR0 settings (read access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 208 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address and CSn Assertion to RD and WRxx Assertion Specify the number of delay cycles from address and CSn assertion to RD and WRxx assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of wait cycles required for read access. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 209 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 Delay Cycles from RD and WRxx Negation to Address and CSn Negation R/W Specify the number of delay cycles from RD and WRxx negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 9.4.4 Bus Function Extending Register (BSCEHR) BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC. It also specifies the application of priority in transfer operations and enables or disables the functions that have the effect of decreasing numbers of cycles over which the DTC is active. The differences in DTC operation made by the combinations of the DTLOCK, CSSTP1, and DTBST bits settings are described in section 8.5.9, DTC Bus Releasing Timing. Setting the CSSTP2 bit can improve the transfer performance of the DTC transfer when the DTLOCK bit is 0. Furthermore, setting the CSSTP3 bit selects whether or not access to the external space by the CPU takes priority over DTC transfer. The DTC short address mode is implemented by setting the DTSA bit. For details of the short address mode, see section 8.4, Location of Transfer Information and DTC Vector Table. A DTC activation priority order can be set up for the DTC activation sources. The DTPR bit selects whether or not this priority order is valid or invalid when multiple sources issue activation requests before DTC activation. Do not modify this register while the DTC is active. Bit: 15 14 DTLOCK CSSTP1 Initial value: 0 R/W: R/W Page 210 of 964 0 R/W 13 12 - CSSTP2 0 R 0 R/W 11 10 9 8 DTBST DTSA CSSTP3 DTPR 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 15 DTLOCK 0 R/W DTC Lock Enable Specifies the timing of bus release by the DTC. 0: The DTC releases the bus on generation of the NOP cycle that follows vector read or write-back of transfer information. 1: The DTC releases the bus after vector read, on generation of the NOP cycle that follows vector read, after transfer information read, after a round of data transfer, or after write-back of transfer information. 14 CSSTP1 0 R/W Select Bus Release on NOP Cycle Generation by DTC Specifies whether or not the bus is released in response to requests from the CPU for external space access on generation of the NOP cycle that follows reading of the vector address. If, however, the CSSTP2 bit is 1, bus mastership is retained until all transfer is complete, regardless of the setting of this bit. 0: The bus is released on generation of the NOP cycle by the DTC. 1: The bus is not released on generation of the NOP cycle by the DTC. 13 0 R Reserved This bit is always read as 0. The write value should always be 0. 12 CSSTP2 0 R/W Select Bus Release during DTC Transfer This setting applies to DTC transfer when the DTLOCK bit is 0. The value specifies whether the bus mastership is or is not to be released after each round of transfer in response to a request from the CPU for access to the external space. 0: When the DTLOCK and CSSTP1 bits are 0, the bus is released on generation of the NOP cycle after reading of the vector address. When the DTLOCK bit is 0 and the CSSTP1 bit is 1, the bus is released after each round of data transfer. 1: Only release the bus mastership after all data transfer is complete. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 211 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 11 DTBST 0 R/W DTC Burst Enable Selects whether or not the DTC retains the bus mastership and remains continuously active until all transfer operations are complete when multiple DTC activation requests have been generated. 0: Release the bus on the completion of transfer for each individual DTC activation source. 1: Keep the DTC continuously active, i.e. only release the bus on completion of processing for all DTC activation sources. Notes: When this bit is set to 1, the following restrictions apply. 1. Clock setting with the frequency control register (FRQCR) must be I: B: P: MI: MP: = 8: 4: 4: 4: 4, 4: 2: 2: 2: 2, or 2: 1: 1: 1: 1 2. The vector information must be in on-chip ROM or on-chip RAM. 3. The transfer information must be in on-chip RAM. 4. Transfer must be between the on-chip RAM and an on-chip peripheral module or between external memory and an on-chip peripheral module. 10 DTSA 0 R/W DTC Short Address Mode In this mode, the information that specifies a DTC transfer takes up only 3 longwords. 0: Transfer information is read out as 4 longwords. The transfer information is arranged as shown in figure 8.2 (normal address mode). 1: Transfer information is read out as 3 longwords. The transfer information is arranged as shown in figure 8.2 (short address mode). Note: Transfer in short address mode is only available between on-chip peripheral modules and on-chip RAM, because the higher-order 8 bits of the SAR and DAR are considered to be all 1. Page 212 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) Bit Bit Name Initial Value R/W Description 9 CSSTP3 0 R/W Select Priority for External Memory Access by CPU Specifies whether or not access to the external space by the CPU takes priority over DTC transfer. 0: DTC transfer has priority. 1: External space access from the CPU has priority. Note: When this bit is 0, and access to internal I/O from the CPU is immediately followed by access to external space from the CPU, a NOP 1B in duration is inserted between the two access cycles. 8 DTPR 0 R/W Application of Priority in DTC Activation When multiple DTC activation requests are generated before the DTC is activated, specify whether transfer starts from the first request to have been generated or is in accord with the priority order for DTC activation requests. However, when multiple DTC activation requests have been issued while the DTC is active, the next transfer to be triggered will be that with the highest DTC activation priority. 0: Start transfer in response to the first request to have been generated. 1: Start transfer in accord with DTC activation request priority. Notes: When this bit is set to 1, the following restrictions apply. 1. The vector information must be in on-chip ROM or on-chip RAM. 2. The transfer information must be in on-chip RAM. 3. Skipping of transfer information reading is always disabled. 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 213 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.5 Operation 9.5.1 Endian/Access Size and Data Alignment This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte data. Two data bus widths (8 bits and 16 bits) are available. Data alignment is performed in accordance with the data bus width of the respective device. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length are performed automatically between the respective interfaces. Tables 9.6 and 9.7 show the relationship between device data width and access unit. Table 9.6 16-Bit External Device Access and Data Alignment Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WRH WRL Byte access at 0 Data 7 to Data 0 Assert Byte access at 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Word access at 2 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Data 23 to Data 16 Assert Assert Data 7 to Data 0 Assert Longword 1st time Data 31 to Data 24 access at 0 at 0 2nd time Data 15 to Data 8 at 2 Page 214 of 964 Assert R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 9.7 Section 9 Bus State Controller (BSC) 8-Bit External Device Access and Data Alignment Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WRH WRL Byte access at 0 Data 7 to Data 0 Assert Byte access at 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 1st time at 0 Data 15 to Data 8 Assert 2nd time at 1 Data 7 to Data 0 Assert Word access at 2 1st time at 2 Data 15 to Data 8 Assert 2nd time at 3 Data 7 to Data 0 Assert Longword 1st time access at 0 at 0 2nd time at 1 Data 31 to Data 24 Assert Data 23 to Data 16 Assert 3rd time at 2 Data 15 to Data 8 Assert 4th time at 3 Data 7 to Data 0 Assert R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 215 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly SRAM without a byte selection will be directly connected. Figure 9.2 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. T1 T2 CK A19 to A0 CSn RD Read D15 to D0 WRxx Write D15 to D0 Figure 9.2 Normal Space Basic Access Timing (Access Wait 0) There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 16 bits are always read in a 16-bit device. When writing, only the WRxx signal for the byte to be written is asserted. It is necessary to control of outputing the data that has been read using RD when a buffer is established in the data bus. Figures 9.3 and 9.4 show the basic timings of continuous accesses to normal space. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 9.4). Page 216 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) T1 T2 Tnop T1 T2 CK A19 to A0 CSn RD Read D15 to D0 WRxx Write D15 to D0 WAIT Figure 9.3 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 0 (Access Wait = 0, Cycle Wait = 0) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 217 of 964 SH7146 Group Section 9 Bus State Controller (BSC) T1 T2 T1 T2 CK A19 to A0 CSn RD Read D15 to D0 WRxx Write D15 to D0 WAIT Figure 9.4 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 1 (Access Wait = 0, Cycle Wait = 0) Page 218 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) 128k x 8-bit SRAM **** A0 CS OE I/O7 **** I/O0 WE **** **** **** D0 WRL A16 **** **** D8 WRH D7 A0 CS OE I/O7 **** **** A1 CSn RD D15 A16 **** **** **** A17 **** This LSI I/O0 WE Figure 9.5 Example of 16-Bit Data-Width SRAM Connection 128 k x 8 bits SRAM This LSI A0 CS RD OE D7 I/O7 ... A0 CSn ... ... A16 ... A16 D0 I/O0 WRL WE Figure 9.6 Example of 8-Bit Data-Width SRAM Connection R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 219 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible to insert wait cycles independently in read access and in write access. The specified number of Tw cycles is inserted as wait cycles in a normal space access shown in figure 9.7. T1 Tw T2 CK A19 to A0 CSn RD Read D15 to D0 WRxx Write D15 to D0 Figure 9.7 Wait Timing for Normal Space Access (Software Wait Only) Page 220 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 9.8. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled at the falling edge of CK at the transition from the T1 or Tw cycle to the T2 cycle. Wait states inserted by WAIT signal T1 Tw Tw Twx T2 CK A19 to A0 CSn RD Read D15 to D0 WRxx Write D15 to D0 WAIT Figure 9.8 Wait State Timing for Normal Space Access (Wait State Insertion Using WAIT Signal) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 221 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.5.4 CSn Assert Period Extension The number of cycles from CSn assertion to RD, WRxx assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WRxx negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 9.9 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WRxx are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CK A19 to A0 CSn RD Read D15 to D0 WRxx Write D15 to D0 Figure 9.9 CSn Assert Period Extension Page 222 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 9.5.5 Section 9 Bus State Controller (BSC) Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data output when the data output from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting wait cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by bits IWW[1:0], IWRWD[1:0], IWRWS[1:0], IWRRD[1:0], and IWRRS[1:0] in CSnBCR. The conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. Continuous accesses are write-read or write-write 2. Continuous accesses are read-write for different spaces 3. Continuous accesses are read-write for the same space 4. Continuous accesses are read-read for different spaces 5. Continuous accesses are read-read for the same space Besides the wait cycles between access cycles (idle cycles) described above, idle cycles must be inserted to reserve the minimum pulse width for a multiplexed pin (WRxx), and an interface with an internal bus. 6. Idle cycle of the external bus for the interface with the internal bus A. Insert one idle cycle immediately before a write access cycle after an external bus idle cycle or a read cycle. B. Insert one idle cycle to transfer the read data to the internal bus when a read cycle of the external bus terminates. Insert two to three idle cycles including the idle cycle in A. for the write cycle immediately after a read cycle. Tables 9.8 and 9.9 list the minimum number of idle cycles to be inserted. The CSnBCR Idle Setting column in the tables describes the number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 223 of 964 SH7146 Group Section 9 Bus State Controller (BSC) Table 9.8 Minimum Number of Idle Cycles between CPU Access Cycles in Normal Space Interface When Access Size is Less than Bus Width BSC Register Setting When Access Size Exceeds Bus Width Contin- Contin- CSnWCR. CSnBCR Read to Write to Read to Write to uous uous 1 Write* Read to Write to Read to Write to 1 Read* 2 Write* 2 Write* 2 WM Setting Idle Setting Read Write Write Read Read* Read* 1 0 1/1/1/1 0/0/0/0 3/3/3/4 0/0/0/0 0/0/0/0 0/0/0/0 1/1/1/1 0/0/0/0 3/3/3/4 0/0/0/0 0 0 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1 1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 0 1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1 2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 0 2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 1 4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 0 4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 2 Notes: The minimum numbers of idle cycles are described sequentially for I:B = 4:1, 3:1, 2:1, and 1:1. 1. Minimum number of idle cycles between the word access to address 0 and the word access to address 2 in the 32-bit access with a 16-bit bus width, minimum number of idle cycles between the byte access to address 0 and the byte access to address 1 in the 16-bit access with an 8-bit bus width, and minimum number of idle cycles between the byte accesses to address 0, to address 1, to address 2, and to address 3 in the 32-bit access with an 8-bit bus width. 2. Other than the above cases Page 224 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table 9.9 Section 9 Bus State Controller (BSC) Minimum Number of Idle Cycles between Access Cycles during DTC Transfer for the Normal Space Interface When Access Size is Less than Bus Width BSC Register Setting When Access Size Exceeds Bus Width CSnWCR. CSnBCR Read to WM Setting Idle Setting Write Write to Read Continuous Read to Read*1 Write*2 Continuous Write to Write*1 Read*2 1 0 2 0 0 2 0 0 0 0 2 1 1 2 1 1 1 1 2 1 1 2 1 1 0 1 2 1 1 2 1 1 1 2 2 2 2 2 2 2 0 2 2 2 2 2 2 2 1 4 4 4 4 4 4 4 0 4 4 4 4 4 4 4 Notes: DTC is operated by B. The minimum number of idle cycles is not affected by changing a clock ratio. 1. Minimum number of idle cycles between the word access to address 0 and the word access to address 2 in the 32-bit access with a 16-bit bus width, minimum number of idle cycles between the byte access to address 0 and the byte access to address 1 in the 16-bit access with an 8-bit bus width, and minimum number of idle cycles between the byte accesses to address 0, to address 1, to address 2, and to address 3 in the 32-bit access with an 8-bit bus width. 2. Other than the above cases. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 225 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.5.6 Bus Arbitration This LSI owns the bus mastership in normal state and releases the bus only when receiving a bus request from an external device. This LSI has two bus masters: CPU and DTC. The bus mastership is given to these bus masters in accordance with the following priority. Request for bus mastership by external device (BREQ) > CPU > DTC > CPU However, when DTC is requesting the bus mastership, the CPU does not obtain the bus mastership continuously. When the CSSTP2 bit is 1 in the bus function extending register (BSCHER), the external space access request from the CPU has lower priority than the DTC transfer request with DTLOCK = 0 in the bus function extending register (BSCHER). In addition, because the write buffer operates as described in section 9.5.7 (2), Access in View of LSI Internal Bus Master, arbitration between the CPU and DTC is different depending on whether the external space access by the CPU is a write or read access. Figure 9.10 shows the bus arbitration when a DTC activation request is generated while an external space is accessed by the CPU. Page 226 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) * When DTC activation request is generated during read access to external space from CPU Internal bus Read access to external space from CPU External bus Read access to external space from CPU DTC DTC activation request DTC activation request is generated in this period. * When DTC activation request is generated during write access to external space from CPU (1) Write to external space from CPU Internal bus DTC Write access to external space from CPU External bus DTC activation request DTC activation request is generated in this period. * When DTC activation request is generated during write access to external space from CPU (2) (When external space read request is generated by CPU during execution of write access to external space from CPU) Internal bus External bus Write to external space from CPU Read access to external space from CPU Write access to external space from CPU DTC Read access to external space from CPU DTC activation request DTC activation request is generated in this period. * When DTC activation request is generated during write access to external space from CPU (3) (When external space write request is generated by CPU during execution of write access to external space from CPU) Internal bus Write to external Write to external space 1 from CPU space 2 from CPU External bus Write access to external space 1 from CPU DTC Write access to external space 2 from CPU DTC activation request DTC activation request is generated in this period. Figure 9.10 Bus Arbitration When DTC Activation Request Occur during External Space Access from CPU R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 227 of 964 Section 9 Bus State Controller (BSC) SH7146 Group The states that do not allow bus arbitration are shown below. 1. Between the read and write cycles of a TAS instruction 2. Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) To prevent device malfunction while the bus mastership is transferred to the external device, the LSI negates all of the bus control signals before bus release. When the bus mastership is received, all of the bus control signals are first negated and then driven appropriately. In addition, to prevent noise while the bus control signal is in the high impedance state, pull-up resistors must be connected to these control signals. Bus mastership is transferred to the external device at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The external bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing the cycles required for master to slave bus mastership transitions streamlines the system design. The LSI has the bus mastership until a bus request is received from the external device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the slave has released the bus, it negates the BACK signal and resumes the bus usage. Processing by this LSI continues even while bus mastership is released to an external device, unless an external device is accessed. When an external device is accessed, the LSI enters the state of waiting for bus mastership to be returned. While the bus is released, sleep mode, software standby mode, and deep software standby mode cannot be entered. The bus release sequence is as follows. The address bus and data bus are placed in a highimpedance state synchronized with the rising edge of CK. The bus mastership acknowledge signal is asserted 0.5 cycles after the above high impedance state, synchronized with the falling edge of Page 228 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) CK. The bus control signals such as CSn are placed in the high-impedance state at subsequent rising edges of CK. These bus control signals go high one cycle before being placed in the highimpedance state. Bus request signals are sampled at the falling edge of CK. The sequence for reclaiming the bus mastership from an external device is described below. At 1.5 cycles after the negation of BREQ is detected at the falling edge of CK, the bus control signals are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CK where address and data signals are driven. Figure 9.11 shows the bus arbitration timing in master mode. After BREQ assertion (low level; bus request), the BREQ signal should be negated (high level; bus release) only after the BACK is asserted (low level; bus acknowledge). If BREQ is negated before BACK is asserted, BACK may be asserted only for one cycle depending on the BREQ negation timing, and a bus conflict may occur between the external device and this LSI. CK BREQ BACK A19 to A0 D15 to D0 CSn Other bus control signals Figure 9.11 Bus Arbitration Timing Acceptance of mastership for the DTC in bus arbitration does not require the insertion of a NOP, so bus access proceeds continuously. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 229 of 964 SH7146 Group Section 9 Bus State Controller (BSC) 9.5.7 (1) Others Reset The bus state controller (BSC) can be initialized completely only at a power-on reset. At a poweron reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At a manual reset, the current bus cycle being executed is completed and then the access wait state is entered. However, a bus arbitration request by the BREQ signal cannot be accepted during manual reset signal assertion. (2) Access in View of LSI Internal Bus Master There are three types of LSI internal buses: L bus, I bus, and peripheral bus. The CPU is connected to the L bus. The DTC and bus state controller are connected to the I bus. Low-speed peripheral modules are connected to the peripheral bus. On-chip memories are connected bidirectionally to the L bus and I bus. For an access of an external space or an on-chip peripheral module, the access is initiated via the I bus. Thus, the DTC can be activated without bus arbitration with the CPU while the CPU is accessing an on-chip memory. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the I bus before the previous external bus cycle is completed in a write cycle. If the onchip peripheral module is read or written after the external low-speed memory is written, the onchip peripheral module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by the DTC. Since access cannot be performed correctly if any BSC register values are modified while the write buffer is operating, do not modify BSC registers immediately after a write access. If the BSC register need to be modified immediately after a write access, execute dummy read to confirm the completion of the write access, then modify the BSC register. Page 230 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 9.5.8 Section 9 Bus State Controller (BSC) Access to On-Chip FLASH and On-Chip RAM by CPU Access to the on-chip FLASH for read is synchronized with I clock and is executed in one clock cycle. For details on programming and erasing, see section 19, Flash Memory. Access to the on-chip RAM for read/write is synchronized with I clock and is executed in one clock cycle. For details, see section 21, RAM. 9.5.9 Access to On-Chip Peripheral I/O Registers by CPU Table 9.10 shows the number of cycles required for access to the on-chip peripheral I/O registers by the CPU. Table 9.10 Number of Cycles for Access to On-Chip Peripheral I/O Registers Number of Access Cycles Write (3 + n) x I + (1 + m) x B + 2 x P Read (3 + n) x I + (1 + m) x B + 2 x P + 2 x I Notes: 1. When I:B = 8:1, n = 0 to 7 When I:B = 4:1, n = 0 to 3 When B:P = 4:1, m = 0 to 3 When I:B = 3:1, n = 0 to 2 When B:P = 3:1, m = 0 to 2 When I:B = 2:1, n = 0 to 1. When B:P = 2:1, m = 0 to 1. When I:B = 1:1, n = 0. When B:P = 1:1, m = 0 n and m depend on the internal execution state. 2. The clock ratio of MI and MP does not affect the number of access cycles. Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus are input and output in synchronization with rising edges of the corresponding clock signal. The L bus, I bus, and peripheral bus are synchronized with the I, B, and P clock, respectively. Figure 9.12 shows an example of the timing of write access to a register in 2P cycle access with the connected peripheral bus width of 16 bits when I:B:P = 4:2:2. In access to the on-chip peripheral I/O registers, the CPU requires three cycles of I for preparation of data transfer to the I bus after the data has been output to the L bus. After these three cycles, data can be transferred to the I bus in synchronization with rising edges of B. However, as there are two I clock cycles in a single B clock cycle when I: B = 4:2, transfer of data from the L bus to the I bus takes (3 + R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 231 of 964 SH7146 Group Section 9 Bus State Controller (BSC) n) x I (n = 0 to 1) (3 x I is indicated in figure 9.52). The relation between the timing of data output to the L bus and the rising edge of B depends on the state of program execution. In the case shown in the figure, where n = 0 and m = 0, the time required for access is 3 x I + 1 x B + 2 x P. I L bus B I bus P Peripheral bus (3 + n) x I (1 + m) x B 2 x P Figure 9.12 Timing of Write Access to On-Chip Peripheral I/O Registers When I:B:P = 4:2:2 Figure 9.13 shows an example of timing of read access to the peripheral bus when I:B:P = 4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for writing. In the case of reading, however, values output onto the peripheral bus need to be transferred to the CPU. Although transfers from the peripheral bus to the I bus and from the I bus to the L bus are performed in synchronization with the rising edge of the respective bus clocks, a period of 2 x I is actually required because I B P. In the case shown in the figure, where n = 0 and m = 1, the time required for access is 3 x I + 2 x B + 2 x P + 2 x I. I L bus B I bus P Peripheral bus (3 + n) x I (1 + m) x B 2 x P 2 x I Figure 9.13 Timing of Read Access to On-Chip Peripheral I/O Registers When I:B:P = 4:2:1 Page 232 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 9.5.10 Section 9 Bus State Controller (BSC) Access to External Memory by CPU Table 9.11 shows the number of cycles required for access to the external memory by the CPU. As the table shows, the number of cycles varies with the clock ratio, the access size, the external bus width of the LSI, and the setting for wait insertion. For details on the wait-insertion setting, see section 9.4, Register Descriptions. Table 9.11 Number of External Access Cycles External Bus Width Access Size Write/Read Number of Access Cycles 8 bits Byte Write (1 + n) x I + (3 + m) x B Read (1 + n) x I + (3 + m) x B + 1 x I Write (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B Read (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B+ 1 x I Word Longword 16 bits Write (1 + n) x I + (3 + m) x B + 3 x (2 + o) x B Read (1 + n) x I + (3 + m) x B + 3 x (2 + o) x B+ 1 x I Byte/Word Write Longword Note: n: m, o: (1 + n) x I + (3 + m) x B Read (1 + n) x I + (3 + m) x B + 1 x I Write (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B Read (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B+ 1 x I When I:B = 8:1, n = 0 to 7 When I:B = 4:1, n = 0 to 3 When I:B = 3:1, n = 0 to 2 When I:B = 2:1, n = 0 to 1 When I:B = 1:1, n = 0 m: Wait setting, o: Wait setting + idle setting For details, see section 9.4, Register Descriptions. Synchronous logic and a layered bus structure have been adopted for this LSI circuit. Data on each bus are input and output in synchronization with rising edges of the corresponding clock signal. The L bus and I bus are synchronized with the I and B clocks, respectively. Figure 9.14 shows an example of the timing of write access to a word of data over the external bus, with a bus-width of 8 bits, when I:B = 2:1. Once the CPU has output the data to the L bus, data are transferred to the I bus in synchronization with rising edges of B. There are two I clock cycles in a single B clock cycle when I: B = 2:1. Thus, when I: B = 2:1, data transfer from the L bus to the I bus takes (1 + n) x I (n = 0 to 1) (2 x I is indicated in figure 9.14). The relation between the timing of data output to the L bus and the rising edge of B depends on the state of program execution. Data output to the I bus are transferred to the external bus after one cycle of B. External access to R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 233 of 964 SH7146 Group Section 9 Bus State Controller (BSC) each data takes at least two cycles, and this can be prolonged by the BSC register settings (m and o in the formulae for number of access cycles). In the case shown in figure 9.14, since n = 1, m = 0, and o = 0, access takes 2 x I + 3 x B + 2 x B. I L bus B (CK) I bus External bus First external access Second external access This access period is This access period is prolonged by a period of m. prolonged by a period of o. (1 + n) x I (3 + m) x B In this example, m = 0 and o = 0. For the numbers of cycles by which m and o prolong the access process, see section 9.4, Register Descriptions. (2 + o) x B Figure 9.14 Timing of Write Access to Word Data in External Memory When I:B = 2:1 and External Bus Width is 8 Bits Figure 9.15 shows an example of the timing of read access when the external bus width is greater than or equal to the data width and I:B = 4:1. Transfer from the L bus to the external bus is performed in the same way as for write access. In the case of reading, however, values output onto the external bus must be transferred to the CPU. Transfers from the external bus to the I bus and from the I bus to the L bus are again performed in synchronization with rising edges of the respective bus clocks. In the actual operation, transfer from the external bus to the L bus takes one period. In the case shown in the figure, where n = 2 and m = 0, access takes 3 x I + 3 x B + 1 x I. Page 234 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 9 Bus State Controller (BSC) I L bus B (CK) I bus External bus External access This access period is prolonged by a period of m. (1 + n) x I (3 + m) x B In this example, m = 0. For the numbers of cycles by which m prolongs the access process, see section 9.4, Register Descriptions. 1 x I Figure 9.15 Timing of Read Access with Condition I:B = 4:1 and External Bus Width Data Width For access by the DTC, the access cycles are obtained by subtracting the cycles of I required for L-bus access from the access cycles required for access by the CPU. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 235 of 964 Section 9 Bus State Controller (BSC) Page 236 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels. 10.1 Features * Maximum 16 pulse input/output lines and three pulse input lines * Selection of eight counter input clocks for each channel (four clocks for channel 5) * The following operations can be set for channels 0 to 4: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 12-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0, 3, and 4 * Phase counting mode settable independently for each of channels 1 and 2 * Cascade connection operation * Fast access via internal 16-bit bus * 28 interrupt sources * Automatic transfer of register data * A/D converter start trigger can be generated * Module standby mode can be settable * A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible. * AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible. * Dead time compensation counter available in channel 5 * In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 237 of 964 TIMMTU1A_020020030800 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.1 MTU2 Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock MP/1 MP/4 MP/16 MP/64 TCLKA TCLKB TCLKC TCLKD MP/1 MP/4 MP/16 MP/64 MP/256 TCLKA TCLKB MP/1 MP/4 MP/16 MP/64 MP/1024 TCLKA TCLKB TCLKC MP/1 MP/4 MP/16 MP/64 MP/256 MP/1024 TCLKA TCLKB MP/1 MP/4 MP/16 MP/64 MP/256 MP/1024 TCLKA TCLKB MP/1 MP/4 MP/16 MP/64 General registers TGRA_0 TGRB_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRU_5 TGRV_5 TGRW_5 General registers/ buffer registers TGRC_0 TGRD_0 TGRF_0 -- -- TGRC_3 TGRD_3 TGRC_4 TGRD_4 -- I/O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Input pins TIC5U TIC5V TIC5W Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture -- Compare 0 output match 1 output output Toggle output -- -- Input capture function Synchronous operation -- PWM mode 1 -- PWM mode 2 -- -- -- Complementary PWM mode -- -- -- -- Reset PWM mode -- -- -- -- AC synchronous motor drive mode -- -- -- Page 238 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Phase counting mode -- -- -- -- Buffer operation -- -- -- Dead time compensation counter function -- -- -- -- -- DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow TGR compare match or input capture A/D converter start TGRA_0 trigger compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture -- TGRE_0 compare match R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 TCNT_4 underflow (trough) in complement ary PWM mode Page 239 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Interrupt sources 7 sources 4 sources 4 sources 5 sources 5 sources 3 sources * * * Compare * Compare Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture capture capture capture capture capture 0A 1A 2A 3A 4A 5U Compare * Compare Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture capture capture capture capture capture 0B 1B 2B 3B 4B 5V Compare * Overflow Compare * Compare * Compare match or match or match or input input input input capture capture capture capture 0C 3C 4C 5W Compare Compare * Compare match or match or match or input input input capture capture capture 0D 3D 4D match or * * * * * Underflow * Overflow * Underflow * * * Compare match 0E or * Compare underflow * Overflow Overflow match 0F * Page 240 of 964 Overflow R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Item Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel 0 A/D converter start -- request delaying function Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 -- -- -- * -- A/D converter start request at a match between TADCOR A_4 and TCNT_4 * A/D converter start request at a match between TADCOR B_4 and TCNT_4 Interrupt skipping function -- -- -- * Skips * Skips TGRA_3 TCIV_4 compare interrupts -- match interrupts [Legend] Possible : --: Not possible R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 241 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel 5: TGIU_5 TGIV_5 TGIW_5 TGRW TGRD TGRD TCNTW TGRB TGRC TGRB TGRC TCBR TDDR TGRV TCNTV TCDR TCNT TGRA TCNT TGRA TCNTS TCNTU BUS I/F TGRF TGRE TGRD TGRB TGRB TGRB A/D conversion start signals Channels 0 to 4: TRGAN Channel 0: TRG0N Channel 4: TRG4AN TRG4BN TGRC TCNT TGRA TCNT TGRA TCNT TGRA TSR TIER TSR TIER TSR TIER Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 Internal data bus TSTR Module data bus TSR TIER TSYR TGRU TSR TIER TIER TGCR TSR TMDR TIORL TIORH TIORL TIORH TIOR TIOR TIOR TIORL TIORH Channel 5 Common Control logic TMDR Channel 2 TCR TMDR Channel 1 TCR Channel 0 Control logic for channels 0 to 2 Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B TMDR Clock input Internal clock: MP/1 MP/4 MP/16 MP/64 MP/256 MP/1024 External clock: TCLKA TCLKB TCLKC TCLKD TCR Input pins Channel 5: TIC5U TIC5V TIC5W TCR TOER TOCR Channel 3 TCR TMDR Channel 4 TCR Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Control logic for channels 3 and 4 Figure 10.1 shows a block diagram of the MTU2. Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2 [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: TGRU: TGRV: TGRW: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer general register U Timer general register V Timer general register W Figure 10.1 Block Diagram of MTU2 Page 242 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.2 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Input/Output Pins Table 10.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input) TIOC0A I/O TGRA_0 input capture input/output compare output/PWM output pin TIOC0B I/O TGRB_0 input capture input/output compare output/PWM output pin TIOC0C I/O TGRC_0 input capture input/output compare output/PWM output pin TIOC0D I/O TGRD_0 input capture input/output compare output/PWM output pin TIOC1A I/O TGRA_1 input capture input/output compare output/PWM output pin TIOC1B I/O TGRB_1 input capture input/output compare output/PWM output pin TIOC2A I/O TGRA_2 input capture input/output compare output/PWM output pin TIOC2B I/O TGRB_2 input capture input/output compare output/PWM output pin TIOC3A I/O TGRA_3 input capture input/output compare output/PWM output pin TIOC3B I/O TGRB_3 input capture input/output compare output/PWM output pin TIOC3C I/O TGRC_3 input capture input/output compare output/PWM output pin TIOC3D I/O TGRD_3 input capture input/output compare output/PWM output pin TIOC4A I/O TGRA_4 input capture input/output compare output/PWM output pin TIOC4B I/O TGRB_4 input capture input/output compare output/PWM output pin TIOC4C I/O TGRC_4 input capture input/output compare output/PWM output pin TIOC4D I/O TGRD_4 input capture input/output compare output/PWM output pin TIC5U Input TGRU_5 input capture input/external pulse input pin TIC5V Input TGRV_5 input capture input/external pulse input pin TIC5W Input TGRW_5 input capture input/external pulse input pin 0 1 2 3 4 5 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 243 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3 Register Descriptions The MTU2 has the following registers. For details on register addresses and register states during each process, refer to section 23, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 10.3 Register Configuration Register Name Abbreviation R/W Initial value Address Access Size Timer control register_3 TCR_3 R/W H'00 H'FFFFC200 8, 16, 32 Timer control register_4 TCR_4 R/W H'00 H'FFFFC201 8 Timer mode register_3 TMDR_3 R/W H'00 H'FFFFC202 8, 16 Timer mode register_4 TMDR_4 R/W H'00 H'FFFFC203 8 Timer I/O control register H_3 TIORH_3 R/W H'00 H'FFFFC204 8, 16, 32 Timer I/O control register L_3 TIORL_3 R/W H'00 H'FFFFC205 8 Timer I/O control register H_4 TIORH_4 R/W H'00 H'FFFFC206 8, 16 Timer I/O control register L_4 TIORL_4 R/W H'00 H'FFFFC207 8 Timer interrupt enable register_3 TIER_3 R/W H'00 H'FFFFC208 8, 16 Timer interrupt enable register_4 TIER_4 R/W H'00 H'FFFFC209 8 Timer output master enable register TOER R/W H'C0 H'FFFFC20A 8 Timer gate control register TGCR R/W H'80 H'FFFFC20D 8 Timer output control register 1 TOCR1 R/W H'00 H'FFFFC20E 8, 16 Timer output control register 2 TOCR2 R/W H'00 H'FFFFC20F 8 Timer counter_3 TCNT_3 R/W H'0000 H'FFFFC210 16, 32 Timer counter_4 TCNT_4 R/W H'0000 H'FFFFC212 16 Timer cycle data register TCDR R/W H'FFFF H'FFFFC214 16, 32 Timer dead time data register TDDR R/W H'FFFF H'FFFFC216 16 Timer general register A_3 TGRA_3 R/W H'FFFF H'FFFFC218 16, 32 Timer general register B_3 TGRB_3 R/W H'FFFF H'FFFFC21A 16 Timer general register A_4 TGRA_4 R/W H'FFFF H'FFFFC21C 16, 32 Timer general register B_4 TGRB_4 R/W H'FFFF H'FFFFC21E 16 Page 244 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Register Name Abbreviation R/W Initial value Address Access Size Timer subcounter TCNTS R H'0000 H'FFFFC220 16, 32 Timer cycle buffer register TCBR R/W H'FFFF H'FFFFC222 16 Timer general register C_3 TGRC_3 R/W H'FFFF H'FFFFC224 16, 32 Timer general register D_3 TGRD_3 R/W H'FFFF H'FFFFC226 16 Timer general register C_4 TGRC_4 R/W H'FFFF H'FFFFC228 16, 32 Timer general register D_4 TGRD_4 R/W H'FFFF H'FFFFC22A 16 Timer status register_3 TSR_3 R/W H'C0 H'FFFFC22C 8, 16 Timer status register_4 TSR_4 R/W H'C0 H'FFFFC22D 8 Timer interrupt skipping set register TITCR R/W H'00 H'FFFFC230 8, 16 Timer interrupt skipping counter TITCNT R H'00 H'FFFFC231 8 Timer buffer transfer set register TBTER R/W H'00 H'FFFFC232 8 Timer dead time enable register TDER R/W H'01 H'FFFFC234 8 Timer output level buffer register TOLBR R/W H'00 H'FFFFC236 8 Timer buffer operation transfer TBTM_3 mode register_3 R/W H'00 H'FFFFC238 8, 16 Timer buffer operation transfer TBTM_4 mode register_4 R/W H'00 H'FFFFC239 8 Timer A/D converter start request control register TADCR R/W H'0000 H'FFFFC240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 R/W H'FFFF H'FFFFC244 16, 32 Timer A/D converter start request cycle set register B_4 TADCORB_4 R/W H'FFFF H'FFFFC246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 R/W H'FFFF H'FFFFC248 16, 32 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 R/W H'FFFF H'FFFFC24A 16 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 245 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Abbreviation R/W Initial value Address Access Size Timer waveform control register TWCR R/W H'00 H'FFFFC260 8 Timer start register TSTR R/W H'00 H'FFFFC280 8, 16 Timer synchronous register TSYR R/W H'00 H'FFFFC281 8 Timer counter synchronous start register TCSYSTR R/W H'00 H'FFFFC282 8 Timer read/write enable register TRWER R/W H'01 H'FFFFC284 8 Timer control register_0 TCR_0 R/W H'00 H'FFFFC300 8, 16, 32 Timer mode register_0 TMDR_0 R/W H'00 H'FFFFC301 8 Timer I/O control register H_0 TIORH_0 R/W H'00 H'FFFFC302 8, 16 Timer I/O control register L_0 TIORL_0 R/W H'00 H'FFFFC303 8 Timer interrupt enable register_0 TIER_0 R/W H'00 H'FFFFC304 8, 16, 32 Timer status register_0 TSR_0 R/W H'C0 H'FFFFC305 8 Timer counter_0 TCNT_0 R/W H'0000 H'FFFFC306 16 Register Name Timer general register A_0 TGRA_0 R/W H'FFFF H'FFFFC308 16, 32 Timer general register B_0 TGRB_0 R/W H'FFFF H'FFFFC30A 16 Timer general register C_0 TGRC_0 R/W H'FFFF H'FFFFC30C 16, 32 Timer general register D_0 TGRD_0 R/W H'FFFF H'FFFFC30E 16 Timer general register E_0 TGRE_0 R/W H'FFFF H'FFFFC320 16, 32 Timer general register F_0 TGRF_0 R/W H'FFFF H'FFFFC322 16 Timer interrupt enable register 2_0 TIER2_0 R/W H'00 H'FFFFC324 8, 16 Timer status register 2_0 TSR2_0 R/W H'C0 H'FFFFC325 8 Timer buffer operation transfer TBTM_0 mode register_0 R/W H'00 H'FFFFC326 8 Timer control register_1 TCR_1 R/W H'00 H'FFFFC380 8, 16 Timer mode register_1 TMDR_1 R/W H'00 H'FFFFC381 8 Timer I/O control register_1 TIOR_1 R/W H'00 H'FFFFC382 8 Timer interrupt enable register_1 TIER_1 R/W H'00 H'FFFFC384 8, 16, 32 Timer status register_1 TSR_1 R/W H'C0 H'FFFFC385 8 Page 246 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Register Name Abbreviation R/W Initial value Address Access Size Timer counter_1 TCNT_1 R/W H'0000 H'FFFFC386 16 Timer general register A_1 TGRA_1 R/W H'FFFF H'FFFFC388 16, 32 Timer general register B_1 TGRB_1 R/W H'FFFF H'FFFFC38A 16 Timer input capture control register TICCR R/W H'00 H'FFFFC390 8 Timer control register_2 TCR_2 R/W H'00 H'FFFFC400 8, 16 Timer mode register_2 TMDR_2 R/W H'00 H'FFFFC401 8 Timer I/O control register_2 TIOR_2 R/W H'00 H'FFFFC402 8 Timer interrupt enable register_2 TIER_2 R/W H'00 H'FFFFC404 8, 16, 32 Timer status register_2 TSR_2 R/W H'C0 H'FFFFC405 8 Timer counter_2 TCNT_2 R/W H'0000 H'FFFFC406 16 Timer general register A_2 TGRA_2 R/W H'FFFF H'FFFFC408 16, 32 Timer general register B_2 TGRB_2 R/W H'FFFF H'FFFFC40A 16 Timer counter U_5 TCNTU_5 R/W H'0000 H'FFFFC480 16, 32 Timer general register U_5 TGRU_5 R/W H'FFFF H'FFFFC482 16 Timer control register U_5 TCRU_5 R/W H'00 H'FFFFC484 8 Timer I/O control register U_5 TIORU_5 R/W H'00 H'FFFFC486 8 Timer counter V_5 TCNTV_5 R/W H'0000 H'FFFFC490 16, 32 Timer general register V_5 TGRV_5 R/W H'FFFF H'FFFFC492 16 Timer control register V_5 TCRV_5 R/W H'00 H'FFFFC494 8 Timer I/O control register V_5 TIORV_5 R/W H'00 H'FFFFC496 8 Timer counter W_5 TCNTW_5 R/W H'0000 H'FFFFC4A0 16, 32 Timer general register W_5 TGRW_5 R/W H'FFFF H'FFFFC4A2 16 Timer control register W_5 TCRW_5 R/W H'00 H'FFFFC4A4 8 Timer I/O control register W_5 TIORW_5 R/W H'00 H'FFFFC4A6 8 Timer status register_5 TSR_5 R/W H'00 H'FFFFC4B0 8 Timer interrupt enable register_5 TIER_5 R/W H'00 H'FFFFC4B2 8 Timer start register_5 TSTR_5 R/W H'00 H'FFFFC4B4 8 Timer compare match clear register TCNTCMPCLR R/W H'00 H'FFFFC4B6 8 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 247 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped. Bit: 7 6 5 CCLR[2:0] Initial value: 0 R/W: R/W 0 R/W 4 3 2 CKEG[1:0] 0 R/W 0 R/W 0 R/W 1 0 TPSC[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 7 to 5 CCLR[2:0] 000 R/W Counter Clear 0 to 2 0 R/W 0 R/W These bits select the TCNT counter clearing source. See tables 10.4 and 10.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. MP/4 both edges = MP/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is MP/4 or slower. When MP/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.6 to 10.10 for details. [Legend] x: Don't care Page 248 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3, 4 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input 2 capture* 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Bit 6 2 Reserved* CCLR1 Bit 5 CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 249 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.6 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on MP/1 1 Internal clock: counts on MP/4 0 Internal clock: counts on MP/16 1 Internal clock: counts on MP/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Table 10.7 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on MP/1 1 Internal clock: counts on MP/4 0 Internal clock: counts on MP/16 1 Internal clock: counts on MP/64 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 0 Internal clock: counts on MP/256 1 Counts on TCNT_2 overflow/underflow 1 1 Note: This setting is ignored when channel 1 is in phase counting mode. Page 250 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.8 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on MP/1 1 Internal clock: counts on MP/4 0 Internal clock: counts on MP/16 1 Internal clock: counts on MP/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on MP/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 10.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3, 4 0 0 0 Internal clock: counts on MP/1 1 Internal clock: counts on MP/4 0 Internal clock: counts on MP/16 1 Internal clock: counts on MP/64 0 Internal clock: counts on MP/256 1 Internal clock: counts on MP/1024 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 251 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.10 TPSC1 and TPSC0 (Channel 5) Channel Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 Internal clock: counts on MP/1 1 Internal clock: counts on MP/4 0 Internal clock: counts on MP/16 1 Internal clock: counts on MP/64 1 Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value should always be 0. 10.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: Initial value: R/W: 7 6 5 4 - BFE BFB BFA 0 - 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 -- 0 -- 3 2 1 0 MD[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 6 BFE 0 R/W Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. Compare match with TGRF occurs even when TGRF is used as a buffer register. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation Page 252 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode. Since the TGFD flag will be set if a compare match occurs during Tb interval in complementary PWM mode, the TGIED bit in timer interrupt enable register 3/4 (TIER_3/4) should be cleared to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRC occurs in complementary PWM mode. Since the TGFC flag will be set if a compare match occurs on channel 4 during Tb interval in complementary PWM mode, the TGIEC bit in timer interrupt enable register 4 (TIER_4) should be cleared to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 10.11 for details. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 253 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Setting prohibited 0 PWM mode 1 1 PWM mode 2* 0 Phase counting mode 1* 2 1 Phase counting mode 2* 2 0 Phase counting mode 3* 2 1 Phase counting mode 4* 2 0 Reset synchronous PWM mode* 1 Setting prohibited 1 x Setting prohibited 0 0 Setting prohibited 1 Complementary PWM mode 1 (transmit at crest)* 0 Complementary PWM mode 2 (transmit at trough)* 1 Complementary PWM mode 2 (transmit at crest and 3 trough)* 1 1 0 1 1 0 1 0 1 1 3 3 3 [Legend] x: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode and complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2. Page 254 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.3.3 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR should be set when TMDR is set to select normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: 7 6 5 4 3 IOB[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 2 1 0 IOA[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4 IOB[3:0] 0000 R/W I/O Control B0 to B3 0 R/W 0 R/W Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: 3 to 0 IOA[3:0] 0000 R/W Table 10.12 Table 10.14 Table 10.15 Table 10.16 Table 10.18 I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Table 10.20 Table 10.22 Table 10.23 Table 10.24 Table 10.26 Page 255 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TIORL_0, TIORL_3, TIORL_4 Bit: 7 6 5 4 3 IOD[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 2 1 0 IOC[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3 0 R/W 0 R/W Specify the function of TGRD. See the following tables. TIORL_0: Table 10.13 TIORL_3: Table 10.17 TIORL_4: Table 10.19 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 10.21 TIORL_3: Table 10.25 TIORL_4: Table 10.27 * TIORU_5, TIORV_5, TIORW_5 Bit: Initial value: R/W: 7 6 5 - - - 0 R 0 R 0 R 4 3 2 1 0 0 R/W 0 R/W IOC[4:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 5 All 0 R Reserved 0 R/W These bits are always read as 0. The write value should always be 0. 4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 10.28. Page 256 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.12 TIORH_0 (Channel 0) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 Output compare register 1 1 0 TIOC0B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 x Input capture at both edges x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 257 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.13 TIORL_0 (Channel 0) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC0D Pin Function 1 Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge 1 x Input capture at both edges x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Page 258 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.14 TIOR_1 (Channel 1) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 Output compare register 1 1 0 TIOC1B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 x Input capture at both edges x x Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 259 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.15 TIOR_2 (Channel 2) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 Output compare register 1 1 0 TIOC2B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 260 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.16 TIORH_3 (Channel 3) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_3 Function 0 0 0 0 Output compare register 1 1 0 TIOC3B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 261 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.17 TIORL_3 (Channel 3) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_3 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC3D Pin Function 1 Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Page 262 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.18 TIORH_4 (Channel 4) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_4 Function 0 0 0 0 Output compare register 1 1 0 TIOC4B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 263 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.19 TIORL_4 (Channel 4) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_4 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC4D Pin Function 1 Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Page 264 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.20 TIORH_0 (Channel 0) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 Output compare register 1 1 0 TIOC0A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 x Input capture at both edges x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 265 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.21 TIORL_0 (Channel 0) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC0C Pin Function 1 Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge 1 x Input capture at both edges x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Page 266 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.22 TIOR_1 (Channel 1) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 Output compare register 1 1 0 TIOC1A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 x Input capture at both edges x x Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 267 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.23 TIOR_2 (Channel 2) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 Output compare register 1 1 0 TIOC2A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 268 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.24 TIORH_3 (Channel 3) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_3 Function 0 0 0 0 Output compare register 1 1 0 TIOC3A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 269 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.25 TIORL_3 (Channel 3) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_3 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC3C Pin Function 1 Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Page 270 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.26 TIORH_4 (Channel 4) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_4 Function 0 0 0 0 Output compare register 1 1 0 TIOC4A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 271 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.27 TIORL_4 (Channel 4) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_4 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC4C Pin Function 1 Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Page 272 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) Description Bit 4 IOC4 Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 0 0 0 0 0 1 TGRU_5, TGRV_5, and TGRW_5 Function TIC5U, TIC5V, and TIC5W Pin Function 1 Compare match Compare match register Setting prohibited 1 x Setting prohibited 1 x x Setting prohibited 1 x x x Setting prohibited 0 0 0 0 1 1 1 Input capture register Setting prohibited Input capture at rising edge 0 Input capture at falling edge 1 Input capture at both edges 1 x x Setting prohibited 0 0 0 Setting prohibited 1 Measurement of low pulse width of external input signal Capture at trough of complementary PWM mode 1 0 Measurement of low pulse width of external input signal Capture at crest of complementary PWM mode 1 Measurement of low pulse width of external input signal Capture at crest and trough of complementary PWM mode 1 0 0 Setting prohibited 1 Measurement of high pulse width of external input signal Capture at trough of complementary PWM mode 1 0 Measurement of high pulse width of external input signal Capture at crest of complementary PWM mode 1 Measurement of high pulse width of external input signal Capture at crest and trough of complementary PWM mode [Legend] x: Don't care R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 273 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: Initial value: R/W: 7 6 5 4 3 - - - - - 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 3 -- All 0 R 2 1 0 CMP CMP CMP CLR5U CLR5V CLR5W 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 2 CMPCLR5U 0 R/W TCNT Compare Clear 5U Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1 CMPCLR5V 0 R/W TCNT Compare Clear 5V Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture Page 274 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Bit Name 0 CMPCLR5W 0 R/W Description R/W TCNT Compare Clear 5W Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 10.3.5 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5. * TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 Bit: 7 6 5 4 3 2 1 0 TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 R/W: R/W 0 R/W Bit Bit Name Initial Value R/W 7 TTGE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description A/D Converter Start Request Enable Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 275 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 6 TTGE2 0 R/W A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Page 276 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 277 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TIER2_0 Bit: 7 6 5 4 3 2 TTGE2 - - - - - 0 R 0 R 0 R 0 R 0 R Initial value: 0 R/W: R/W Bit Bit Name Initial Value R/W 7 TTGE2 0 R/W 1 0 TGIEF TGIEE 0 R/W 0 R/W Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGIEF 0 R/W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled 0 TGIEE 0 R/W TGR Interrupt Enable E Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled Page 278 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TIER_5 Bit: Initial value: R/W: 7 6 5 4 3 - - - - - 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 3 -- All 0 R 2 1 0 TGIE5U TGIE5V TGIE5W 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 2 TGIE5U 0 R/W TGR Interrupt Enable 5U Enables or disables interrupt requests (TGIU_5) by the CMFU5 bit when the CMFU5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled 1 TGIE5V 0 R/W TGR Interrupt Enable 5V Enables or disables interrupt requests (TGIV_5) by the CMFV5 bit when the CMFV5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled 0 TGIE5W 0 R/W TGR Interrupt Enable 5W Enables or disables interrupt requests (TGIW_5) by the CMFW5 bit when the CMFW5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 279 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.6 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5. * TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TCFD - TCFU TCFV TGFD TGFC TGFB TGFA 1 R 1 R 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6 -- 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 1 R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] * Page 280 of 964 When 0 is written to TCFU after reading TCFU = 1* 2 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit 4 Bit Name TCFV Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. [Clearing condition] * 3 TGFD 0 2 When 0 is written to TCFV after reading TCFV = 1* In channel 4, when DTC is activated by TCIV interrupt and the DISEL bit of MRB in DTC is 0, this flag is also cleared. 1 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions] * When TCNT = TGRD and TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing conditions] R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 * When DTC is activated by TGID interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1* 2 Page 281 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 Bit Name TGFC Initial Value 0 R/W Description 1 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions] * When TCNT = TGRC and TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing conditions] 1 TGFB 0 * When DTC is activated by TGIC interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1* 2 1 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * When TCNT = TGRB and TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing conditions] Page 282 of 964 * When DTC is activated by TGIB interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1* 2 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit 0 Bit Name TGFA Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value 0 R/W R/(W)* Description 1 Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * When TCNT = TGRA and TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing conditions] * When DTC is activated by TGIA interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1* 2 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 283 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TSR2_0 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - TGFF TGFE 1 R 1 R 0 R 0 R 0 R 0 R 0 0 R/(W)* R/(W)* Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 7, 6 -- All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGFF 0 R/(W)* 1 Compare Match Flag F Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Setting condition] * When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register [Clearing condition] * 0 TGFE 0 R/(W)* 1 When 0 is written to TGFF after reading TGFF = 1* 2 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Setting condition] * When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register [Clearing condition] * When 0 is written to TGFE after reading TGFE = 1* 2 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it. Page 284 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TSR_5 Bit: Initial value: R/W: 7 6 5 4 3 - - - - - CMFU5 CMFV5 CMFW5 2 1 0 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)* R/(W)* R/(W)* Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 7 to 3 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 CMFU5 0 1 R/(W)* Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. [Setting conditions] * When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register * When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register * When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control 2 register U_5 (TIORU_5)* [Clearing conditions] R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 * When DTC is activated by a TGIU_5 interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to CMFU5 after reading CMFU5 = 1 Page 285 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 1 Bit Name CMFV5 Initial Value 0 R/W Description 1 R/(W)* Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Setting conditions] * When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register * When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register * When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control 2 register V_5 (TIORV_5)* [Clearing conditions] Page 286 of 964 * When DTC is activated by a TGIV_5 interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to CMFV5 after reading CMFV5 = 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit 0 Bit Name CMFW5 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value 0 R/W Description 1 R/(W)* Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Setting conditions] * When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register * When TCNTW_5 value is transferred to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register * When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O 2 control register W_5 (TIORW_5)* [Clearing conditions] * When DTC is activated by a TGIW_5 interrupt and the DISEL bit of MRB in DTC is 0 * When 0 is written to CMFW5 after reading CMFW5 = 1 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. The transfer timing is specified by the IOC bit in timer I/O control registers U_5/V_5/W_5 (TIORU_5, TIORV_5, TIORW_5). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 287 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - TTSE TTSB TTSA 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 3 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 2 TTSE 0 R/W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared 1 TTSB 0 R/W Timing Select B Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. When using a channel in other than PWM mode, do not set this bit to1. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel Page 288 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 0 TTSA 0 R/W Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. When using a channel in other than PWM mode, do not set this bit to 1. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel 10.3.8 Timer Input Capture Control Register (TICCR) TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - I2BE I2AE I1BE I1AE 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 4 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 3 I2BE 0 R/W Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 289 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 2 I2AE 0 R/W Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions 1 I1BE 0 R/W Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions 0 I1AE 0 R/W Input Capture Enable Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions Page 290 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.3.9 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Timer Synchronous Clear Register (TSYCR) TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCR in channel 3 but the MTU2 has no TSYCR. Bit: 7 6 5 4 3 2 1 0 CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 CE0A 0 R/W Clear Enable 0A Enables or disables counter clearing when the TGFA flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_0 1: Enables counter clearing by the TGFA flag in TSR_0 6 CE0B 0 R/W Clear Enable 0B Enables or disables counter clearing when the TGFB flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_0 1: Enables counter clearing by the TGFB flag in TSR_0 5 CE0C 0 R/W Clear Enable 0C Enables or disables counter clearing when the TGFC flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFC flag in TSR_0 1: Enables counter clearing by the TGFC flag in TSR_0 4 CE0D 0 R/W Clear Enable 0D Enables or disables counter clearing when the TGFD flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFD flag in TSR_0 1: Enables counter clearing by the TGFD flag in TSR_0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 291 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 3 CE1A 0 R/W Clear Enable 1A Enables or disables counter clearing when the TGFA flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_1 1: Enables counter clearing by the TGFA flag in TSR_1 2 CE1B 0 R/W Clear Enable 1B Enables or disables counter clearing when the TGFB flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_1 1: Enables counter clearing by the TGFB flag in TSR_1 1 CE2A 0 R/W Clear Enable 2A Enables or disables counter clearing when the TGFA flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_2 1: Enables counter clearing by the TGFA flag in TSR_2 0 CE2B 0 R/W Clear Enable 2B Enables or disables counter clearing when the TGFB flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_2 1: Enables counter clearing by the TGFB flag in TSR_2 Page 292 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.10 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4. Bit: 15 14 BF[1:0] Initial value: 0 R/W: R/W 0 R/W 13 12 11 10 9 8 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE 0 R/W 0* R/W 0 R/W 0* R/W 0* R/W 0* R/W 0* R/W 0* R/W Note: * Do not set to 1 when complementary PWM mode is not selected. Bit Bit Name Initial Value R/W Description 15, 14 BF[1:0] 00 R/W TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 10.29. 13 to 8 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 UT4AE 0 R/W Up-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation 6 DT4AE 0* R/W Down-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 293 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 5 UT4BE 0 R/W Up-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation 4 DT4BE 0* R/W Down-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation 3 ITA3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping 2 ITA4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping 1 ITB3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping Page 294 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 0 ITB4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 10.29 Setting of Transfer Timing by BF1 and BF0 Bits Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set 1 register at the crest of the TCNT_4 count.* 1 0 Transfers data from the cycle set buffer register to the cycle set 2 register at the trough of the TCNT_4 count.* 1 1 Transfers data from the cycle set buffer register to the cycle set 2 register at the crest and trough of the TCNT_4 count.* Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 295 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. 10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. Page 296 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.13 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset. Bit: 15 Initial value: 0 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. 10.3.14 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 297 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.15 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. * TSTR Bit: 7 6 5 4 3 2 1 0 CST4 CST3 - - - CST2 CST1 CST0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 CST4 0 R/W Counter Start 4 and 3 6 CST3 0 R/W These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 298 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 2 CST2 0 R/W Counter Start 2 to 0 1 CST1 0 R/W These bits select operation or stoppage for TCNT. 0 CST0 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation * TSTR_5 Bit : Initial value: R/W: 7 6 5 4 3 - - - - - 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 3 -- All 0 R Reserved 2 1 0 CSTU5 CSTV5 CSTW5 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 2 CSTU5 0 R/W Counter Start U5 Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation 1 CSTV5 0 R/W Counter Start V5 Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation 0 CSTW5 0 R/W Counter Start W5 Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 299 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.16 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: 7 6 SYNC4 SYNC3 Initial value: 0 R/W: R/W 0 R/W 5 4 3 - - - 0 R 0 R 0 R 2 1 0 SYNC2 SYNC1 SYNC0 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 SYNC4 0 R/W Timer Synchronous operation 4 and 3 6 SYNC3 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 300 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 2 SYNC2 0 R/W Timer Synchronous operation 2 to 0 1 SYNC1 0 R/W 0 SYNC0 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 301 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and MTU2S counters. Note that the MTU2S does not have TCSYSTR. Bit: 7 6 5 4 3 2 SCH0 SCH1 SCH2 SCH3 SCH4 - SCH3S SCH4S 0 R 0 0 R/(W)* R/(W)* Initial value: 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 1 0 Note: * Only 1 can be written to set the register. Bit Bit Name Initial Value R/W 7 SCH0 0 R/(W)* Synchronous Start Description Controls synchronous start of TCNT_0 in the MTU2. 0: Does not specify synchronous start for TCNT_0 in the MTU2 1: Specifies synchronous start for TCNT_0 in the MTU2 [Clearing condition] * 6 SCH1 0 When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 = 1 R/(W)* Synchronous Start Controls synchronous start of TCNT_1 in the MTU2. 0: Does not specify synchronous start for TCNT_1 in the MTU2 1: Specifies synchronous start for TCNT_1 in the MTU2 [Clearing condition] * Page 302 of 964 When 1 is set to the CST1 bit of TSTR in MTU2 while SCH1 = 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W 5 SCH2 0 R/(W)* Synchronous Start Description Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition] * 4 SCH3 0 When 1 is set to the CST2 bit of TSTR in MTU2 while SCH2 = 1 R/(W)* Synchronous Start Controls synchronous start of TCNT_3 in the MTU2. 0: Does not specify synchronous start for TCNT_3 in the MTU2 1: Specifies synchronous start for TCNT_3 in the MTU2 [Clearing condition] * 3 SCH4 0 When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 = 1 R/(W)* Synchronous Start Controls synchronous start of TCNT_4 in the MTU2. 0: Does not specify synchronous start for TCNT_4 in the MTU2 1: Specifies synchronous start for TCNT_4 in the MTU2 [Clearing condition] * 2 -- 0 R When 1 is set to the CST4 bit of TSTR in MTU2 while SCH4 = 1 Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 303 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W 1 SCH3S 0 R/(W)* Synchronous Start Description Controls synchronous start of TCNT_3S in the MTU2S. 0: Does not specify synchronous start for TCNT_3S in the MTU2S 1: Specifies synchronous start for TCNT_3S in the MTU2S [Clearing condition] * 0 SCH4S 0 When 1 is set to the CST3 bit of TSTRS in MTU2S while SCH3S = 1 R/(W)* Synchronous Start Controls synchronous start of TCNT_4S in the MTU2S. 0: Does not specify synchronous start for TCNT_4S in the MTU2S 1: Specifies synchronous start for TCNT_4S in the MTU2S [Clearing condition] * Note: * When 1 is set to the CST4 bit of TSTRS in MTU2S while SCH4S = 1 Only 1 can be written to set the register. Page 304 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.18 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - RWE 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W Bit Bit Name Initial Value R/W 7 to 1 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RWE 1 R/W Read/Write Enable Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition] * When 0 is written to the RWE bit after reading RWE = 1 * Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 305 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.19 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - OE4D OE4C OE3D OE4B OE4A OE3B 1 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7, 6 -- All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Page 306 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 0 OE3B 0 R/W Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 10.3.20, Timer Output Control Register 1 (TOCR1), and section 10.3.21, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or resetsynchronized PWM mode. When these bits are set to 0, low level is output. * 10.3.20 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - PSYE - - TOCL TOCS OLSN OLSP 0 R 0 R/W 0 R 0 R 0 0 R/(W)* R/W 0 R/W 0 R/W Note: * This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit. Bit Bit Name Initial value R/W Description 7 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 307 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W 3 TOCL 0 R/(W)* TOC Register Write Protection* Description 1 This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled 2 TOCS 0 R/W TOC Select This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected 1 OLSN 0 R/W Output Level Select N* 2 This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 10.30. 0 OLSP 0 R/W Output Level Select P* 2 This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 10.31. Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 2. Clearing the TOCS0 bit to 0 makes this bit setting valid. Table 10.30 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Page 308 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level 0 High level Low level Low level High level 1 Low level High level High level Low level Up Count Down Count Figure 10.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3 and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Time Positive phase output Initial output Reverse phase output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Figure 10.2 Complementary PWM Mode Output Level Example R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 309 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.21 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 6 BF[1:0] Initial value: 0 R/W: R/W 0 R/W 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7, 6 BF[1:0] 00 R/W TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 10.32. 5 OLS3N 0 R/W Output Level Select 3N* This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode. See table 10.33. 4 OLS3P 0 R/W Output Level Select 3P* This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode. See table 10.34. 3 OLS2N 0 R/W Output Level Select 2N* This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode. See table 10.35. 2 OLS2P 0 R/W Output Level Select 2P* This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode. See table 10.36. 1 OLS1N 0 R/W Output Level Select 1N* This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode. See table 10.37. Page 310 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial value R/W Description 0 OLS1P 0 R/W Output Level Select 1P* This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode. See table 10.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 10.32 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description BF1 BF0 Complementary PWM Mode 0 0 Does not transfer data from the Does not transfer data from the buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2. 0 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared 1 0 Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Setting prohibited 1 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Setting prohibited Reset-Synchronized PWM Mode Table 10.33 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 311 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level 0 High level Low level Low level High level 1 Low level High level High level Low level Up Count Down Count Table 10.35 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 10.36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Table 10.37 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Page 312 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.38 TIOC4B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count 0 High level Low level Low level High level 1 Low level High level High level Low level Down Count 10.3.22 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7 6 - - 0 R 0 R 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7, 6 -- All 0 R Reserved 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 5 OLS3N 0 R/W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2. 4 OLS3P 0 R/W Specifies the buffer value to be transferred to the OLS3P bit in TOCR2. 3 OLS2N 0 R/W Specifies the buffer value to be transferred to the OLS2N bit in TOCR2. 2 OLS2P 0 R/W Specifies the buffer value to be transferred to the OLS2P bit in TOCR2. 1 OLS1N 0 R/W Specifies the buffer value to be transferred to the OLS1N bit in TOCR2. 0 OLS1P 0 R/W Specifies the buffer value to be transferred to the OLS1P bit in TOCR2. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 313 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [1] [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. Set TOCR2 [2] [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Set TOLBR [3] Figure 10.3 PWM Output Level Setting Procedure in Buffer Operation 10.3.23 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - BDC N P FB* WF VF UF 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W 7 -- 1 R Description Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective Page 314 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial value R/W Description 5 N 0 R/W Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB* 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings). 2 WF 0 R/W Output Phase Switch 2 to 0 1 VF 0 R/W 0 UF 0 R/W These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 10.39. Note: * When the MTU2S is used to set the BDC bit to 1, do not set the FB bit to 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 315 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.39 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D WF VF UF U Phase V Phase W Phase U Phase V Phase W Phase 0 0 0 OFF OFF OFF OFF OFF OFF 1 ON OFF OFF OFF OFF ON 0 OFF ON OFF ON OFF OFF 1 OFF ON OFF OFF OFF ON 0 OFF OFF ON OFF ON OFF 1 ON OFF OFF OFF ON OFF 0 OFF OFF ON ON OFF OFF 1 OFF OFF OFF OFF OFF OFF 1 1 0 1 10.3.24 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. Page 316 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.25 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 10.3.26 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 317 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.27 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 10.3.28 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR. Bit: 7 6 T3AEN Initial value: 0 R/W: R/W 5 4 3ACOR[2:0] 0 R/W 0 R/W 3 2 T4VEN 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 T3AEN 0 R/W T3AEN 1 0 4VCOR[2:0] 0 R/W 0 R/W 0 R/W Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 10.40. 3 T4VEN 0 R/W T4VEN Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled Page 318 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Initial value Bit Bit Name 2 to 0 4VCOR[2:0] 000 R/W Description R/W These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 10.41. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TITCNT). Table 10.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description 0 0 0 Does not skip TGIA_3 interrupts. 0 0 1 Sets the TGIA_3 interrupt skipping count to 1. 0 1 0 Sets the TGIA_3 interrupt skipping count to 2. 0 1 1 Sets the TGIA_3 interrupt skipping count to 3. 1 0 0 Sets the TGIA_3 interrupt skipping count to 4. 1 0 1 Sets the TGIA_3 interrupt skipping count to 5. 1 1 0 Sets the TGIA_3 interrupt skipping count to 6. 1 1 1 Sets the TGIA_3 interrupt skipping count to 7. Table 10.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 Bit 1 Bit 0 4VCOR2 4VCOR1 4VCOR0 Description 0 0 0 Does not skip TCIV_4 interrupts. 0 0 1 Sets the TCIV_4 interrupt skipping count to 1. 0 1 0 Sets the TCIV_4 interrupt skipping count to 2. 0 1 1 Sets the TCIV_4 interrupt skipping count to 3. 1 0 0 Sets the TCIV_4 interrupt skipping count to 4. 1 0 1 Sets the TCIV_4 interrupt skipping count to 5. 1 1 0 Sets the TCIV_4 interrupt skipping count to 6. 1 1 1 Sets the TCIV_4 interrupt skipping count to 7. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 319 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.29 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: 7 6 - Initial value: R/W: 5 4 3ACNT[2:0] 0 R Bit Bit Name Initial Value R/W 7 -- 0 R 0 R 0 R 3 2 - 0 R 0 R 1 0 4VCNT[2:0] 0 R 0 R 0 R Description Reserved This bit is always read as 0. 6 to 4 3ACNT[2:0] 000 R TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions] 3 -- 0 R * When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR * When the T3AEN bit in TITCR is cleared to 0 * When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 Reserved This bit is always read as 0. 2 to 0 4VCNT[2:0] 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions] * When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR * When the T4VEN bit in TITCR is cleared to 0 * When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Note: To clear the TITCNT, clear the T3AEN and T4VEN bits in TITCR to 0. Page 320 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.30 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER. Bit: Initial value: R/W: 7 6 5 4 3 2 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 2 -- All 0 R 1 0 BTE[1:0] 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 10.42. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 321 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group Table 10.42 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description 0 0 Enables transfer from the buffer registers to the temporary registers* and does not link the transfer with interrupt skipping operation. 0 1 Disables transfer from the buffer registers to the temporary registers. 1 0 Links transfer from the buffer registers to the temporary registers with 2 interrupt skipping operation.* 1 1 Setting prohibited 1 Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 10.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed. Page 322 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.31 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - TDER 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W) Bit Bit Name Initial Value R/W 7 to 1 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TDER 1 R/(W) Dead Time Enable Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition] * Note: * R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 When 0 is written to TDER after reading TDER = 1 TDDR must be set to 1 or a larger value. Page 323 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.32 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: 7 6 5 4 3 2 1 0 CCE - - - - - SCC WRE 0 R 0 R 0 R 0 R 0 R Initial value: 0* R/W: R/(W) 0 0 R/(W) R/(W) Note: * Do not set to 1 when complementary PWM mode is not selected. Bit Bit Name Initial Value R/W Description 7 CCE 0* R/(W) Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition] * 6 to 2 -- All 0 R When 1 is written to CCE after reading CCE = 0 Reserved These bits are always read as 0. The write value should always be 0. Page 324 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 1 SCC 0 R/(W) Synchronous Clearing Control Specifies whether to clear TCNT_3 and TCNT_4 in the MTU2S when synchronous counter clearing between the MTU2 and MTU2S occurs in complementary PWM mode. When using this control, place the MTU2S in complementary PWM mode. When modifying the SCC bit while the counters are operating, do not modify the CCE or WRE bits. Counter clearing synchronized with the MTU2 is disabled by the SCC bit setting only when synchronous clearing occurs outside the Tb interval at the trough. When synchronous clearing occurs in the Tb interval at the trough including the period immediately after TCNT_3 and TCNT_4 start operation, TCNT_3 and TCNT_4 in the MTU2S are cleared. For the Tb interval at the trough in complementary PWM mode, see figure 10.40. In the MTU2, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: Enables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2-MTU2S synchronous clearing operation 1: Disables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2-MTU2S synchronous clearing operation [Setting condition] * R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 When 1 is written to SCC after reading SCC = 0 Page 325 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit Bit Name Initial Value R/W Description 0 WRE 0 R/(W) Initial Output Suppression Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The initial output is suppressed only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 10.40. 0: Outputs the initial value specified in TOCR 1: Suppresses initial output [Setting condition] * Note: * When 1 is written to WRE after reading WRE = 0 Do not set to 1 when complementary PWM mode is not selected. 10.3.33 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. Page 326 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4 Operation 10.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). Counter Operation: When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of Count Operation Setting Procedure Figure 10.4 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Operation selection Select counter clock [1] Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] <Periodic counter> [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Free-running counter Periodic counter [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation <Free-running counter> [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 10.4 Example of Counter Operation Setting Procedure R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 327 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU2's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU2 requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.5 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.5 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the MTU2 requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Page 328 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.6 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.6 Periodic Counter Operation Waveform Output by Compare Match: The MTU2 can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of Setting Procedure for Waveform Output by Compare Match Figure 10.7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Start count operation [3] [3] Set the CST bit in TSTR to 1 to start the count operation. <Waveform output> Figure 10.7 Example of Setting Procedure for Waveform Output by Compare Match R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 329 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Examples of Waveform Output Operation: Figure 10.8 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB 0 output No change Figure 10.8 Example of 0 Output/1 Output Operation Figure 10.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 10.9 Example of Toggle Output Operation Page 330 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, MP/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if MP/1 is selected. 1. Example of Input Capture Operation Setting Procedure Figure 10.10 shows an example of the input capture operation setting procedure. Input selection Select input capture input [1] [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] <Input capture operation> Figure 10.10 Example of Input Capture Operation Setting Procedure R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 331 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Example of Input Capture Operation: Figure 10.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.11 Example of Input Capture Operation Page 332 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.4.2 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10.12 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes <Synchronous presetting> Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] <Counter clearing> <Synchronous clearing> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10.12 Example of Synchronous Operation Setting Procedure R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 333 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Synchronous Operation: Figure 10.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOC0A TIOC1A TIOC2A Figure 10.13 Example of Synchronous Operation Page 334 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.4.3 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 10.43 shows the register combinations used in buffer operation. Table 10.43 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRE_0 TGRF_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 TGRA_4 TGRC_4 TGRB_4 TGRD_4 3 4 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.14. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.14 Compare Match Buffer Operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 335 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.15. Input capture signal Buffer register Timer general register TCNT Figure 10.15 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation Select TGR function [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Start count [3] <Buffer operation> Figure 10.16 Example of Buffer Operation Setting Procedure Page 336 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 10.17 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. In this example, the TTSA bit in TBTM is cleared to 0. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes. TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 TGRC_0 H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 10.17 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 10.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 337 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 10.18 Example of Buffer Operation (2) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation: The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer timing is one of the following cases. * When TCNT overflows (H'FFFF to H'0000) * When H'0000 is written to TCNT during counting * When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note: TBTM must be modified only while TCNT stops. Figure 10.19 shows an operation example in which PWM mode 1 is designated for channel 0 and buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. The TTSA bit in TBTM_0 is set to 1. Page 338 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 H'0000 TGRC_0 Time H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 H'0520 TIOCA Figure 10.19 Example of Buffer Operation When TCNT_0 Clearing Is Selected for TGRC_0 to TGRA_0 Transfer Timing 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 10.44 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 10.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 339 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.45 shows the TICCR setting and input capture input pins. Table 10.45 TICCR Setting and Input Capture Input Pins Target Input Capture TICCR Setting Input Capture Input Pins Input capture from TCNT_1 to TGRA_1 I2AE bit = 0 (initial value) TIOC1A I2AE bit = 1 TIOC1A, TIOC2A Input capture from TCNT_1 to TGRB_1 I2BE bit = 0 (initial value) TIOC1B I2BE bit = 1 TIOC1B, TIOC2B Input capture from TCNT_2 to TGRA_2 I1AE bit = 0 (initial value) TIOC2A I1AE bit = 1 TIOC2A, TIOC1A Input capture from TCNT_2 to TGRB_2 I1BE bit = 0 (initial value) TIOC2B I1BE bit = 1 TIOC2B, TIOC1B Example of Cascaded Operation Setting Procedure: Figure 10.20 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. Cascaded operation Set cascading [1] Start count [2] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. <Cascaded operation> Figure 10.20 Cascaded Operation Setting Procedure Cascaded Operation Example (a): Figure 10.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. Page 340 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCLKC TCLKD TCNT_2 FFFD TCNT_1 FFFE FFFF 0000 0000 0001 0002 0001 0001 0000 FFFF 0000 Figure 10.21 Cascaded Operation Example (a) Cascaded Operation Example (b): Figure 10.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used. TCNT_2 value H'FFFF H'C256 H'6128 H'0000 TCNT_1 Time H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 TGRA_2 H'0512 H'0513 H'C256 As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing. Figure 10.22 Cascaded Operation Example (b) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 341 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Cascaded Operation Example (c): Figure 10.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'FFFF H'C256 H'9192 H'6128 H'2064 H'0000 TCNT_1 Time H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 H'0512 TGRA_2 H'6128 H'0513 H'2064 H'0514 H'C256 H'9192 Figure 10.23 Cascaded Operation Example (c) Cascaded Operation Example (d): Figure 10.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1. Page 342 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value Compare match between TCNT_0 and TGRA_0 TGRA_0 Time H'0000 TCNT_2 value H'FFFF H'D000 H'0000 TCNT_1 Time H'0512 H'0513 TIOC1A TIOC2A TGRA_1 TGRA_2 H'0513 H'D000 Figure 10.24 Cascaded Operation Example (d) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 343 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.46. Page 344 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.46 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 0 TGRA_0 TIOC0A TIOC0A TGRB_0 TGRC_0 TIOC0B TIOC0C TGRD_0 1 TGRA_1 TIOC0D TIOC1A TGRB_1 2 TGRA_2 TGRA_3 TIOC2A TIOC3A TGRA_4 TIOC3C TGRD_4 Cannot be set Cannot be set TIOC4A TGRB_4 TGRC_4 Cannot be set Cannot be set TGRD_3 4 TIOC2A TIOC2B TGRB_3 TGRC_3 TIOC1A TIOC1B TGRB_2 3 TIOC0C Cannot be set Cannot be set TIOC4C Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 345 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Example of PWM Mode Setting Procedure: Figure 10.25 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] Start count [6] <PWM mode> Figure 10.25 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10.26 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. Page 346 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10.26 Example of PWM Mode Operation (1) Figure 10.27 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 10.27 Example of PWM Mode Operation (2) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 347 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 TIOCA 100% duty 0% duty Figure 10.28 Example of PWM Mode Operation (3) Page 348 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.4.6 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 10.47 shows the correspondence between external clock pins and channels. Table 10.47 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10.29 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. Phase counting mode Select phase counting mode [1] Start count [2] [2] Set the CST bit in TSTR to 1 to start the count operation. <Phase counting mode> Figure 10.29 Example of Phase Counting Mode Setting Procedure R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 349 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.30 shows an example of phase counting mode 1 operation, and table 10.48 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.30 Example of Phase Counting Mode 1 Operation Table 10.48 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Page 350 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Phase counting mode 2 Figure 10.31 shows an example of phase counting mode 2 operation, and table 10.49 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.31 Example of Phase Counting Mode 2 Operation Table 10.49 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care High level Don't care Low level Down-count [Legend] : Rising edge : Falling edge R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 351 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Phase counting mode 3 Figure 10.32 shows an example of phase counting mode 3 operation, and table 10.50 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.32 Example of Phase Counting Mode 3 Operation Table 10.50 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Page 352 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 4. Phase counting mode 4 Figure 10.33 shows an example of phase counting mode 4 operation, and table 10.51 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.33 Example of Phase Counting Mode 4 Operation Table 10.51 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level Don't care High level High level Down-count Low level High level Don't care Low level [Legend] : Rising edge : Falling edge R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 353 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group Phase Counting Mode Application Example: Figure 10.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Page 354 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 TGRA_0 (speed control period) + - TGRC_0 (position control period) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 10.34 Phase Counting Mode Application Example R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 355 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.7 SH7146 Group Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 10.52 shows the PWM output pins used. Table 10.53 shows the settings of the registers. Table 10.52 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description 3 TIOC3B PWM output pin 1 TIOC3D PWM output pin 1' (negative-phase waveform of PWM output 1) 4 TIOC4A PWM output pin 2 TIOC4C PWM output pin 2' (negative-phase waveform of PWM output 2) TIOC4B PWM output pin 3 TIOC4D PWM output pin 3' (negative-phase waveform of PWM output 3) Table 10.53 Register Settings for Reset-Synchronized PWM Mode Register Description of Setting TCNT_3 Initial setting of H'0000 TCNT_4 Initial setting of H'0000 TGRA_3 Set count cycle for TCNT_3 TGRB_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins TGRA_4 Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins TGRB_4 Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Page 356 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 10.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. Reset-synchronized PWM mode Stop counting [1] [2] Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. Select counter clock and counter clear source [2] Brushless DC motor control setting [3] Set TCNT [4] Set TGR [5] PWM cycle output enabling, PWM output level setting [6] Set reset-synchronized PWM mode [7] Enable waveform output [8] PFC setting [9] [7] Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. Start count operation [10] [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. Reset-synchronized PWM mode [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR2, see figure 10.3. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Figure 10.35 Procedure for Selecting Reset-Synchronized PWM Mode R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 357 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Reset-Synchronized PWM Mode Operation: Figure 10.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT_3 and TCNT_4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 10.36 Reset-Synchronized PWM Mode Operation Example (When TOCR's OLSN = 1 and OLSP = 1) Page 358 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.4.8 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval is also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 10.54 shows the PWM output pins used. Table 10.55 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 10.54 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOC3A Toggle output synchronized with PWM period (or I/O port) TIOC3B PWM output pin 1 TIOC3C I/O port* TIOC3D PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) TIOC4A PWM output pin 2 TIOC4B PWM output pin 3 TIOC4C PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) TIOC4D PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) 4 Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 359 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.55 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU 3 TCNT_3 Start of up-count from value set in dead time register Maskable by TRWER setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting* TGRB_3 PWM output 1 compare register Maskable by TRWER setting* TGRC_3 TGRA_3 buffer register Always readable/writable TGRD_3 PWM output 1/TGRB_3 buffer register Always readable/writable TCNT_4 Up-count start, initialized to H'0000 Maskable by TRWER setting* TGRA_4 PWM output 2 compare register Maskable by TRWER setting* TGRB_4 PWM output 3 compare register Maskable by TRWER setting* TGRC_4 PWM output 2/TGRA_4 buffer register Always readable/writable TGRD_4 PWM output 3/TGRB_4 buffer register Always readable/writable Timer dead time data register (TDDR) Set TCNT_4 and TCNT_3 offset value (dead time value) Maskable by TRWER setting* Timer cycle data register (TCDR) Set TCNT_4 upper limit value (1/2 carrier cycle) Maskable by TRWER setting* Timer cycle buffer register (TCBR) TCDR buffer register Always readable/writable Subcounter (TCNTS) Subcounter for dead time generation Read-only Temporary register 1 (TEMP1) PWM output 1/TGRB_3 temporary register Not readable/writable Temporary register 2 (TEMP2) PWM output 2/TGRA_4 temporary register Not readable/writable Temporary register 3 (TEMP3) PWM output 3/TGRB_4 temporary register Not readable/writable 4 Note: * Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register). Page 360 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group TCBR TGRA_3 TCDR Comparator TCNT_3 Match signal TCNTS TCNT_4 TGRD_3 TGRC_4 TGRB_4 Temp 3 Match signal TGRA_4 Temp 2 TGRB_3 Temp 1 Comparator PWM cycle output Output protection circuit TDDR TGRC_3 Output controller TCNT_4 underflow interrupt TGRA_3 comparematch interrupt Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3 TGRD_4 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 10.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 361 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 10.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. Complementary PWM mode Stop count operation [1] Counter clock, counter clear source selection [2] Brushless DC motor control setting [3] TCNT setting [4] [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. Inter-channel synchronization setting [5] TGR setting [6] Enable/disable dead time generation [7] Dead time, carrier cycle setting [8] PWM cycle output enabling, PWM output level setting [9] Complementary PWM mode setting [10] Enable waveform output [11] setting StartPFC count operation [12] [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 10.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. Start count operation [13] [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). <Complementary PWM mode> [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Figure 10.38 Example of Complementary PWM Mode Setting Procedure Page 362 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 10.39 illustrates counter operation in complementary PWM mode, and figure 10.40 shows an example of complementary PWM mode operation. 1. Counter Operation In complementary PWM mode, three counters--TCNT_3, TCNT_4, and TCNTS--perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, downcounting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. TCNT_3 TCNT_4 TCNTS Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TCNTS TDDR H'0000 Time Figure 10.39 Complementary PWM Mode Counter Operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 363 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group 2. Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 10.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 10.40 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 10.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters--TCNT_3, TCNT_4, and TCNTS--and two registers--compare register and temporary register--are compared, and PWM output controlled accordingly. Page 364 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 Ta Tb1 Ta Tb2 Ta TGRA_3 TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 H'6400 H'0080 Temporary register TEMP2 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 10.40 Example of Complementary PWM Mode Operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 365 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 10.56 Registers and Counters Requiring Initialization Register/Counter Set Value TGRC_3 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER) TCBR 1/2 PWM carrier cycle TGRD_3, TGRC_4, TGRD_4 Initial PWM duty value for each phase TCNT_4 H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1. Page 366 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 4. PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. 5. Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. 6. Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 10.41 shows an example of operation without dead time. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 367 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register to compare register Ta Tb1 Ta Tb2 Ta TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Temporary register TEMP2 Data1 Data2 Compare register TGRA_4 Data1 Output waveform Initial output Output waveform Initial output Data2 Output waveform is active-low. Figure 10.41 Example of Operation without Dead Time Page 368 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 7. PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers--TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 10.42 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 10.42 Example of PWM Cycle Updating R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 369 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group 8. Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 10.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Page 370 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Sep 24, 2010 R01UH0049EJ0400 Rev. 4.00 data1 Temp_R GR data1 BR H'0000 TGRC_4 TGRA_4 TGRA_3 Counter value data1 Transfer from temporary register to compare register data2 data2 data2 Transfer from temporary register to compare register Data update timing: counter crest and trough data3 data3 Transfer from temporary register to compare register data3 data4 data4 Transfer from temporary register to compare register data4 data5 data5 Transfer from temporary register to compare register data6 data6 data6 Transfer from temporary register to compare register : Compare register : Buffer register Time SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.43 Example of Data Update in Complementary PWM Mode Page 371 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 9. Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 10.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 10.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TCNT_3 TCNT_4 TGRA_4 TDDR Time Dead time Initial output Positive phase output Negative phase output Active level Active level Complementary PWM mode (TMDR setting) TCNT_3 and TCNT_4 count start (TSTR setting) Figure 10.44 Example of Initial Output in Complementary PWM Mode (1) Page 372 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TCNT_3 TCNT_4 TDDR TGRA_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3 and TCNT_4 count start (TSTR setting) Figure 10.45 Example of Initial Output in Complementary PWM Mode (2) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 373 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group 10. Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off comparematch occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 10.46 to 10.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solidline counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a b c d (or c d a' b'), as shown in figure 10.46. If compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 10.47, compare-match b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 10.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. Page 374 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T2 period T1 period T1 period TGRA_3 c d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 10.46 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGRA_3 c d TCDR a b a b TDDR H'0000 Positive phase Negative phase Figure 10.47 Example of Complementary PWM Mode Waveform Output (2) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 375 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR c a' d b' H'0000 Positive phase Negative phase Figure 10.48 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period c TGRA_3 T1 period d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 10.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) Page 376 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR a b a b TDDR H'0000 c d Positive phase Negative phase Figure 10.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period c TGRA_3 T1 period d TCDR a b TDDR H'0000 Positive phase Negative phase Figure 10.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 377 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 c b' Positive phase d a' Negative phase Figure 10.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 T2 period c ad T1 period b TCDR TDDR H'0000 Positive phase Negative phase Figure 10.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Page 378 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 11. Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 10.49 to 10.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turnoff compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. 12. Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 10.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a comparematch between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 10.54 Example of Toggle Output Waveform Synchronized with PWM Output R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 379 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 13. Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 10.55 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TCNTS TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 10.55 Counter Clearing Synchronized with Another Channel Page 380 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 10.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 10.56) immediately after the counters start operation, initial value output is not suppressed. When using the initial output suppression function, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. If synchronous clearing occurs with the compare registers set to a value less than twice the setting of TDDR, the PWM output dead time may be too short (or nonexistent) or illegal active-level PWM negative-phase output may occur during the initial output suppression interval. For details, see 10.7.23, Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode. This function can be used in both the MTU2 and MTU2S. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing in complementary PWM mode; in the MTU2S, compare match or input capture flag setting in channels 0 to 2 in the MTU2 can cause counter clearing. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 381 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Counter start Tb interval Tb interval Tb interval TGRA_3 TCNT_3 TCDR TGRB_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Figure 10.56 Timing for Synchronous Counter Clearing Page 382 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 10.57. Output waveform control at synchronous counter clearing Stop count operation Set TWCR and complementary PWM mode [1] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [2] [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Start count operation [3] Output waveform control at synchronous counter clearing Figure 10.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 10.58 to 10.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 10.58 to 10.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 10.56, respectively. In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in complementary PWM mode and synchronous counter clearing is generated while the SCC bit is cleared to 0 and the WRE bit is set to 1 in TWCR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 383 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 10.56; Bit WRE of TWCR in MTU2 Is 1) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56; Bit WRE of TWCR in MTU2 Is 1) Page 384 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 10.56; Bit WRE of TWCR Is 1) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 385 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit WRE = 1 Synchronous clearing TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 10.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56; Bit WRE of TWCR Is 1) Page 386 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 15. Suppressing MTU2-MTU2S Synchronous Counter Clearing In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused by the MTU2. Synchronous counter clearing is suppressed only within the interval shown in figure 10.62. When using this function, the MTU2S should be set to complementary PWM mode. For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter clearing) in section 10.4.10, MTU2-MTU2S Synchronous Operation. Tb interval immediately after counter operation starts Tb interval at the crest Tb interval at the trough Tb interval at the crest Tb interval at the trough TGRA_3 TCDR TGRB_3 TDDR H'0000 MTU2-MTU2S synchronous counter clearing is suppressed. MTU2-MTU2S synchronous counter clearing is suppressed. Figure 10.62 MTU2-MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC Bit in TWCR R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 387 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing An example of the procedure for suppressing MTU2-MTU2S synchronous counter clearing is shown in figure 10.63. [1] Clear bits CST of the timer start register (TSTR) in the MTU2S to 0, and halt count operation. Clear bits CST of TSTR in the MTU2 to 0, and halt count operation. MTU2-MTU2S synchronous counter clearing suppress Stop count operation (MTU2 and MTU2S) [1] * Set the following. * Complementary PWM mode (MTU2S) * Compare match/input capture operation (MTU2) * Bit WRE in TWCR (MTU2S) [2] Start count operation (MTU2 and MTU2S) [3] Set bit SCC in TWCR (MTU2S) Output waveform control at synchronous counter clearing and synchronous counter clearing suppress [4] [2] Set the complementary PWM mode in the MTU2S and compare match/input capture operation in the MTU2. When bit WRE in TWCR should be set, make appropriate setting here. [3] Set bits CST3 and CST4 of TSTR in the MTU2S to 1 to start count operation. For MTU2-MTU2S synchronous counter clearing, set bits CST of TSTR in the MTU2 to 1 to start count operation in any one of TCNT_0 to TCNT_2. [4] Read TWCR and then set bit SCC in TWCR to 1 to suppress MTU2-MTU2S synchronous counter clearing*. Here, do not modify the CCE and WRE bit values in TWCR of the MTU2S. MTU2-MTU2S synchronous counter clearing is suppressed in the intervals shown in figure 10.62. Note: * The SCC bit value can be modified during counter operation. However, if a synchronous clearing occurs when bit SCC is modified from 0 to 1, the synchronous clearing may not be suppressed. If a synchronous clearing occurs when bit SCC is modified from 1 to 0, the synchronous clearing may be suppressed. Figure 10.63 Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing Examples of Suppression of MTU2-MTU2S Synchronous Counter Clearing Figures 10.64 to 10.67 show examples of operation in which the MTU2S operates in complementary PWM mode and MTU2-MTU2S synchronous counter clearing is suppressed by setting the SCC bit in TWCR in the MTU2S to 1. In the examples shown in figures 10.64 to 10.67, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 10.56, respectively. In these examples, the WRE bit in TWCR of the MTU2S is set to 1. Page 388 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Counters are not cleared TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.64 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 389 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2S) Counters are not cleared TCNT_4 (MTU2S) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.65 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) Page 390 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR TGRB_3 Counters are not cleared TCNT_3 (MTU2S) TCNT_4 (MTU2S) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.66 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 391 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit WRE = 1 Bit SCC = 1 MTU2-MTU2S synchronous clearing TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Counters are cleared TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Initial value output is suppressed. Figure 10.67 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S) Page 392 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 16. Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 10.68 illustrates an operation example. Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest) 2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to SYNC4 bits in the timer synchronous register (TSYR) to 1 or the CE0A, CE0B, CE0C, CE0D, CE1A, CE1B, CE1C, and CE1D bits in the timer synchronous clear register (TSYCR) to 1). 3. Do not set the PWM duty value to H'0000. 4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1. Counter cleared by TGRA_3 compare match TGRA_3 TCDR TGRB_3 TDDR H'0000 Output waveform Output waveform Output waveform is active-high. Figure 10.68 Example of Counter Clearing Operation by TGRA_3 Compare Match R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 393 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 17. Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 10.69 to 10.72 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 10.69 Example of Output Phase Switching by External Input (1) Page 394 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 10.70 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 10.71 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 395 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 10.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) 18. A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1. Page 396 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Interrupt Skipping in Complementary PWM Mode: Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER). For the linkage with buffer registers, refer to description 3, Buffer Transfer Control Linked with Interrupt Skipping, below. A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in coordination with interrupt skipping by making settings in the timer A/D converter request control register (TADCR). For the linkage with the A/D converter start request delaying function, refer to section 10.4.9, A/D Converter Start Request Delaying Function. The setting of the timer interrupt skipping setting register (TITCR) must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of registers TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. 1. Example of Interrupt Skipping Operation Setting Procedure Figure 10.73 shows an example of the interrupt skipping operation setting procedure. Figure 10.74 shows the periods during which interrupt skipping count can be changed. [1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register (TITCR) to 0 to clear the skipping counter. Interrupt skipping Clear interrupt skipping counter [1] Set skipping count and enable interrupt skipping [2] <Interrupt skipping> [2] Specify the interrupt skipping count within the range from 0 to 7 times in bits 3ACOR2 to 3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and enable interrupt skipping through bits T3AEN and T4VEN. Note: The setting of TITCR must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. Figure 10.73 Example of Interrupt Skipping Operation Setting Procedure R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 397 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Figure 10.74 Periods during which Interrupt Skipping Count Can be Changed 2. Example of Interrupt Skipping Operation Figure 10.75 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR). Interrupt skipping period Interrupt skipping period TGIA_3 interrupt flag set signal Skipping counter 00 01 02 03 00 01 02 03 TGFA_3 flag Figure 10.75 Example of Interrupt Skipping Operation Page 398 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER). Figure 10.76 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the temporary register. Figure 10.77 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer register outside the buffer transfer-enabled period. Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register (TITCR). Figure 10.78 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period. Note: This function must always be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never performed. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 399 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Buffer register Data1 Data2 (1) Temporary register (3) Data* Data2 (2) General register Data* Data2 Buffer transfer is suppressed [Legend] (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. Note: * When buffer transfer at the crest is selected. Figure 10.76 Example of Operation when Buffer Transfer Is Suppressed (BTE1 = 0 and BTE0 = 1) Page 400 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) When buffer register is rewritten within one carrier cycle after the TGIA_3 interrupt TGIA_3 interrupt generated TGIA_3 interrupt generated TCNT_3 TCNT_4 Buffer register rewrite timing Buffer register rewrite timing Buffer transfer-enabled period Bits 6 to 4 in TITCR 2 Bits 6 to 4 in TITCNT 0 1 2 0 1 Buffer register Data Data1 Data2 Temporary register Data Data1 Data2 General register Data Data1 Data2 (2) When buffer register is rewritten after one carrier cycle has elapsed after the TGIA_3 interrupt TGIA_3 interrupt generated TGIA_3 interrupt generated TCNT_3 TCNT_4 Buffer register rewrite timing Buffer transfer-enabled period Bits 6 to 4 in TITCR Bits 6 to 4 in TITCNT Buffer register Temporary register General register 2 0 1 Data 2 0 1 Data1 Data Data Data1 Data1 Note: Bits MD3 to MD0 in TMDR_3 are set to 1101, selecting buffer transfer at the crest. The skipping count is set to two. T3AEN is set to 1, and T4VEN is cleared to 0. Figure 10.77 Example of Operation when Buffer Transfer Is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 401 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Skipping counter 3ACNT Skipping counter 4VCNT 0 1 0 2 1 3 2 0 3 1 0 2 1 3 0 2 3 Buffer transfer-enabled period (T3AEN set to 1) Buffer transfer-enabled period (T4VEN set to 1) Buffer transfer-enabled period (T3AEN and T4VEN set to 1) Note: Bits MD3 to MD0 in TMDR_3 are set to 1111, selecting buffer transfer at the crest and trough. The skipping count is set to three. T3AEN and T4VEN are set to 1. Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period Page 402 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. 1. Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following: TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. 2. Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 12, Port Output Enable (POE), for details. 3. Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. See section 4.7, Function for Detecting Oscillator Stop. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 403 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR. 1. Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 10.79 shows an example of procedure for specifying the A/D converter start request delaying function. [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) A/D converter start request delaying function Set A/D converter start request cycle [1] * Set the timing of transfer from cycle set buffer register * Set linkage with interrupt skipping * Enable A/D converter start request delaying function A/D converter start request delaying function [2] [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register. * Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE. * Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. Figure 10.79 Example of Procedure for Specifying A/D Converter Start Request Delaying Function Page 404 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Basic Operation Example of A/D Converter Start Request Delaying Function Figure 10.80 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting. Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register TADCORA_4 TCNT_4 TADCOBRA_4 A/D converter start request (TRG4AN) (Complementary PWM mode) Figure 10.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation 3. Buffer Transfer The data in the timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D converter start request control register (TADCR_4). 4. A/D Converter Start Request Delaying Function Linked with Interrupt Skipping A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR). Figure 10.81 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D converter start requests are linked with interrupt skipping. Figure 10.82 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter start requests are linked with interrupt skipping. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 405 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 01 00 02 01 00 02 01 00 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping (UT4AE/DT4AE = 1) Note: When the interrupt skipping count is set to two. Figure 10.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Page 406 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter 00 TCIV_4 interrupt skipping counter 01 00 02 01 00 02 01 00 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: UT4AE = 1 DT4AE = 0 When the interrupt skipping count is set to two. Figure 10.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 407 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.10 MTU2-MTU2S Synchronous Operation MTU2-MTU2S Synchronous Counter Start: The counters in the MTU2 and MTU2S which operate at different clock systems can be started synchronously by making the TCSYSTR settings in the MTU2. 1. Example of MTU2-MTU2S Synchronous Counter Start Setting Procedure Figure 10.83 shows an example of synchronous counter start setting procedure. [1] Use TSTR registers in the MTU2 and MTU2S and halt the counters used for synchronous start operation. MTU2-MTU2S synchronous counter start [2] Specify necessary operation with appropriate registers such as TCR and TMDR. Stop count operation [1] Set the necessary operation [2] Set TCSYSTR <Counter operation starts> [3] [3] In TCSYSTR in the MTU2, set the bits corresponding to the counters to be started synchronously to 1. The TSTRs are automatically set appropriately and the counters start synchronously. Notes: 1. Even if a bit in TCSYSTR corresponding to an operating counter is cleared to 0, the counter will not stop. To stop the counter, clear the corresponding bit in TSTR to 0 directly. 2. To start channels 3 and 4 in reset-synchronized PWM mode or complementary PWM mode, make appropriate settings in TCYSTR according to the TSTR setting for the respective mode. For details, refer to section 10.4.7, Reset-Synchronized PWM Mode, and section 10.4.8, Complementary PWM Mode. Figure 10.83 Example of Synchronous Counter Start Setting Procedure Page 408 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Examples of Synchronous Counter Start Operation Figures 10.84 (1), 10.84 (2), 10.84 (3), and 10.84 (4) show examples of synchronous counter start operation when the clock frequency ratio between the MTU2 and MTU2S is 1:1, 1:2, 1:3, and 1:4, respectively. In these examples, the counter clock of the MTU2 is MP/1. MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 H'0001 H'0002 MTU2S/TCNT_4 H'0000 H'0001 H'0002 Figure 10.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:1) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 409 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 MTU2S/TCNT_4 H'0000 H'0002 H'0001 H'0002 H'0004 H'0003 H'0001 Figure 10.84 (2) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:2) MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 MTU2S/TCNT_4 H'0000 H'0002 H'0001 H'0002 H'0001 H'0004 H'0003 Figure 10.84 (3) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:3) Page 410 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 MTU2S/TCNT_4 H'0000 H'0001 H'0002 H'0002 H'0004 H'0001 H'0003 Figure 10.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:4) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 411 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (MTU2-MTU2S Synchronous Counter Clearing): The MTU2S counters can be cleared by sources for setting the flags in TSR_0 to TSR_2 in the MTU2 through the TSYCR_3 settings in the MTU2S. 1. Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting Source Figure 10.85 shows an example of procedure for specifying MTU2S counter clearing by MTU2 flag setting source. [1] Use TSTR registers in the MTU2 and MTU2S and halt the counters used for this function. MTU2S counter clearing by MTU2S flag setting source Stop count operation [1] [2] Use TSYCR_3 in the MTU2S to specify the flag setting source to be used for the TCNT_3 and TCNT_4 clearing source. [3] Start TCNT_3 or TCNT_4 in the MTU2S. Set TSYCR_3 [2] [4] Start TCNT_0, TCNT_1, or TCNT_2 in the MTU2. Start channel 3 or 4 in MTU2S [3] Note: The TSYCR_3 setting is ignored while the counter is stopped. The setting becomes valid after TCNT_3 or TCNT4 is started. Start one of channels 0 to 2 in MTU2 [4] <Counter clearing by flag setting> Figure 10.85 Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting Source Page 412 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Examples of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source Figures 10.86 (1) and 10.86 (2) show examples of MTS2S counter clearing caused by MTU2 flag setting source. TSYCR_3 H'00 H'80 Compare match between TCNT_0 and TGRA_0 TCNT_0 value in MTU2 TGRA_0 TCNT_0 in MTU2 H'0000 Time TCNT_4 value in MTU2S TCNT_4 in MTU2S H'0000 Time Figure 10.86 (1) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (1) TSYCR_3 H'00 H'F0 TCNT_0 value in MTU2 TGRD_0 TGRB_0 Compare match between TCNT_0 and TGR TCNT_0 in MTU2 TGRC_0 TGRA_0 H'0000 Time TCNT_4 value in MTU2S TCNT_4 in MTU2S H'0000 Time Figure 10.86 (2) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (2) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 413 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.11 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in channel 5. Example of External Pulse Width Measurement Setting Procedure: [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. External pulse width measurement Select counter clock [1] [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Select pulse width measuring conditions [2] Start count operation [3] Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR. <External pulse width measurement> Figure 10.87 Example of External Pulse Width Measurement Setting Procedure Example of External Pulse Width Measurement: MP TIC5U TCNTU_5 0000 0001 0002 0003 0004 0005 0006 0007 0007 0008 0009 000A 000B Figure 10.88 Example of External Pulse Width Measurement (Measuring High Pulse Width) Page 414 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.12 Dead Time Compensation By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation. Tdead Upper arm signal Lower arm signal Inverter output detection signal Tdelay Dead time delay signal Figure 10.89 Delay in Dead Time in Complementary PWM Operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 415 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Dead Time Compensation Setting Procedure: Figure 10.90 shows an example of dead time compensation setting procedure by using three counters in channel 5. [1] Place channels 3 and 4 in complementary PWM mode. For details, refer to section 10.4.8, Complementary PWM Mode. Complementary PWM mode [1] [2] Specify the external pulse width measurement function for the target TIOR in channel 5. For details, refer to section 10.4.11, External Pulse Width Measurement. External pulse width measurement [2] [3] Set bits CST3 and CST4 in TSTR and bits CST5U, CST5V, and CST5W in TSTR2 to 1 to start count operation. Start count operation in channels 3 to 5 [3] TCNT_5 input capture occurs [4] * [5] Interrupt processing [4] When the capture condition specified in TIOR is satisfied, the TCNT_5 value is captured in TGR_5. [5] For U-phase dead time compensation, when an interrupt is generated at the crest (TGIA_3) or trough (TCIV_4) in complementary PWM mode, read the TGRU_5 value, calculate the difference in time in TGRB_3, and write the corrected value to TGRD_3 in the interrupt processing. For the V phase and W phase, read the TGRV_5 and TGRW_5 values and write the corrected values to TGRC_4 and TGRD_4, respectively, in the same way as for U-phase compensation. The TCNT_5 value should be cleared through the TCNTCMPCLR setting or by software. Notes: The PFC settings must be completed in advance. * As an interrupt flag is set under the capture condition specified in TIOR, do not enable interrupt requests in TIER_5. Figure 10.90 Example of Dead Time Compensation Setting Procedure MTU Complementary PWM output ch5 Dead time delay input Level conversion ch3/4 DC + W Inverter output monitor signals V U W Motor V U W U V Figure 10.91 Example of Motor Control Circuit Configuration Page 416 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 10.92 is an operating example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). TGRA_4 Tdead Upper arm signal Lower arm signal Inverter output monitor signal Tdelay Dead time delay signal Up-count/down-count signal (udflg) TCNT[15:0] TGR[15:0] 3DE7 3E5B 3DE7 3ED3 3E5B 3ED3 3F37 3FAF 3F37 3FAF Figure 10.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 417 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.5 Interrupt Sources 10.5.1 Interrupt Sources and Priorities SH7146 Group There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 10.57 lists the MTU2 interrupt sources. Page 418 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.57 MTU2 Interrupts Interrupt Flag DTC Activation Priority TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible High TGIB_0 TGRB_0 input capture/compare match TGFB_0 Possible TGIC_0 TGRC_0 input capture/compare match TGFC_0 Possible TGID_0 TGRD_0 input capture/compare match TGFD_0 Possible TCIV_0 TCFV_0 Not possible TGIE_0 TGRE_0 compare match TGFE_0 Not possible TGIF_0 Channel Name 0 1 2 3 4 5 Interrupt Source TCNT_0 overflow TGFF_0 Not possible TGIA_1 TGRA_1 input capture/compare match TGRF_0 compare match TGFA_1 Possible TGIB_1 TGRB_1 input capture/compare match TGFB_1 Possible TCIV_1 TCFV_1 Not possible TCIU_1 TCNT_1 underflow TCFU_1 Not possible TGIA_2 TGRA_2 input capture/compare match TGFA_2 Possible TGIB_2 TGRB_2 input capture/compare match TGFB_2 Possible TCIV_2 TCFV_2 Not possible TCNT_1 overflow TCNT_2 overflow TCIU_2 TCNT_2 underflow TCFU_2 Not possible TGIA_3 TGRA_3 input capture/compare match TGFA_3 Possible TGIB_3 TGRB_3 input capture/compare match TGFB_3 Possible TGIC_3 TGRC_3 input capture/compare match TGFC_3 Possible TGID_3 TGRD_3 input capture/compare match TGFD_3 Possible TCIV_3 TCFV_3 Not possible TGIA_4 TGRA_4 input capture/compare match TGFA_4 Possible TGIB_4 TGRB_4 input capture/compare match TGFB_4 Possible TGIC_4 TGRC_4 input capture/compare match TGFC_4 Possible TGID_4 TGRD_4 input capture/compare match TGFD_4 Possible TCIV_4 TCNT_4 overflow/underflow TCFV_4 Possible TGIU_5 TGRU_5 input capture/compare match TGFU_5 Possible TGIV_5 TGRV_5 input capture/compare match TGFV_5 Possible TGIW_5 TGRW_5 input capture/compare match TGFW_5 Possible TCNT_3 overflow Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 419 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2. 10.5.2 DTC Activation DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt in each channel or the overflow interrupt in channel 4. For details, see section 8, Data Transfer Controller (DTC). A total of 20 MTU2 input capture/compare match interrupts and overflow interrupts can be used as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, five for channel 4, and three for channel 5. Page 420 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.5.3 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) A/D Converter Activation The A/D converter can be activated by one of the following three methods in the MTU2. Table 10.58 shows the relationship between interrupt sources and A/D converter start request signals. A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode: The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions. * When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1 * When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0: The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by A/D Converter Start Request Delaying Function: The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the TAD4AE or TAD4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 10.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 421 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.58 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal TGRA_0 and TCNT_0 Input capture/compare match TRGAN TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4 TCNT_4 Trough in complementary PWM mode TGRE_0 and TCNT_0 Compare match TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 TRG4BN Page 422 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.6 Operation Timing 10.6.1 Input/Output Timing TCNT Count Timing: Figures 10.93 and 10.94 show TCNT count timing in internal clock operation, and figure 10.95 shows TCNT count timing in external clock operation (normal mode), and figure 10.96 shows TCNT count timing in external clock operation (phase counting mode). MP Falling edge Internal clock Rising edge TCNT input clock TCNT N-1 N N+1 Figure 10.93 Count Timing in Internal Clock Operation (Channels 0 to 4) MP Rising edge Internal clock TCNT input clock TCNT N-1 N Figure 10.94 Count Timing in Internal Clock Operation (Channel 5) MP External clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 Figure 10.95 Count Timing in External Clock Operation (Channels 0 to 4) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 423 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MP External clock Falling edge Rising edge TCNT input clock N-1 TCNT N N-1 Figure 10.96 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.97 shows output compare output timing (normal mode and PWM mode) and figure 10.98 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). MP TCNT input clock TCNT TGR N N+1 N Compare match signal TIOC pin Figure 10.97 Output Compare Output Timing (Normal Mode/PWM Mode) Page 424 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MP TCNT input clock TCNT N TGR N N+1 Compare match signal TIOC pin Figure 10.98 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 10.99 shows input capture signal timing. MP Input capture input Input capture signal N TCNT N+1 N+2 N TGR N+2 Figure 10.99 Input Capture Input Signal Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 425 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Timing for Counter Clearing by Compare Match/Input Capture: Figures 10.100 and 10.101 show the timing when counter clearing on compare match is specified, and figure 10.102 shows the timing when counter clearing on input capture is specified. MP Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10.100 Counter Clear Timing (Compare Match) (Channels 0 to 4) MP Compare match signal Counter clear signal TCNT N-1 TGR N H'0000 Figure 10.101 Counter Clear Timing (Compare Match) (Channel 5) Page 426 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MP Input capture signal Counter clear signal H'0000 N TCNT N TGR Figure 10.102 Counter Clear Timing (Input Capture) (Channels 0 to 5) Buffer Operation Timing: Figures 10.103 to 10.105 show the timing in buffer operation. MP TCNT n n+1 TGRA, TGRB n N TGRC, TGRD N Compare match buffer signal Figure 10.103 Buffer Operation Timing (Compare Match) MP Input capture signal TCNT N N+1 TGRA, TGRB n N N+1 n N TGRC, TGRD Figure 10.104 Buffer Operation Timing (Input Capture) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 427 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MP n H'0000 TGRA, TGRB, TGRE n N TGRC, TGRD, TGRF N TCNT TCNT clear signal Buffer transfer signal Figure 10.105 Buffer Transfer Timing (when TCNT Cleared) Buffer Transfer Timing (Complementary PWM Mode): Figures 10.106 to 10.108 show the buffer transfer timing in complementary PWM mode. MP H'0000 TCNTS TGRD_4 write signal Temporary register transfer signal Buffer register n Temporary register n N N Figure 10.106 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) Page 428 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MP TCNTS P-x P H'0000 TGRD_4 write signal Buffer register n N Temporary register n N Figure 10.107 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) MP TCNTS P-1 P H'0000 Buffer transfer signal Temporary register N Compare register n N Figure 10.108 Transfer Timing from Temporary Register to Compare Register R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 429 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figures 10.109 and 10.110 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. MP TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 10.109 TGI Interrupt Timing (Compare Match) (Channels 0 to 4) MP TCNT input clock TCNT TGR N-1 N N Compare match signal TGF flag TGI interrupt Figure 10.110 TGI Interrupt Timing (Compare Match) (Channel 5) Page 430 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TGF Flag Setting Timing in Case of Input Capture: Figures 10.111 and 10.112 show the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. MP, P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.111 TGI Interrupt Timing (Input Capture) (Channels 0 to 4) MP, P Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 10.112 TGI Interrupt Timing (Input Capture) (Channel 5) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 431 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCFV Flag/TCFU Flag Setting Timing: Figure 10.113 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.114 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. MP, P TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 10.113 TCIV Interrupt Setting Timing MP, P TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 10.114 TCIU Interrupt Setting Timing Page 432 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figures 10.115 and 10.116 show the timing for status flag clearing by the CPU, and figures 10.117 and 10.118 show the timing for status flag clearing by the DTC. TSR write cycle T1 T2 MP, P Address TSR address Write signal Status flag Interrupt request signal Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4) TSR write cycle T1 T2 MP, P Address TSR address Write signal Status flag Interrupt request signal Figure 10.116 Timing for Status Flag Clearing by CPU (Channel 5) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 433 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) DTC read cycle DTC write cycle Source address Destination address MP, P, B Address Status flag Interrupt request signal Flag clear signal Figure 10.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4) DTC read cycle DTC write cycle Source address Destination address MP, P, B Address Status flag Interrupt request signal Flag clear signal Figure 10.118 Timing for Status Flag Clearing by DTC Activation (Channel 5) Page 434 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7 Usage Notes 10.7.1 Module Standby Mode Setting MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 22, Power-Down Modes. 10.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.119 shows the input clock conditions in phase counting mode. Overlap Phase Phase differdifference Overlap ence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.119 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 435 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: * Channels 0 to 4 MP f= (N + 1) * Channel 5 MP f= N Where 10.7.4 f: MP: N: Counter frequency MTU2 peripheral clock operating frequency TGR set value Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.120 shows the timing in this case. TCNT write cycle T2 T1 MP Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10.120 Contention between TCNT Write and Clear Operations Page 436 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.7.5 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.121 shows the timing in this case. TCNT write cycle T2 T1 MP Address TCNT address Write signal TCNT input clock TCNT N M TCNT write data Figure 10.121 Contention between TCNT Write and Increment Operations R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 437 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 10.122 shows the timing in this case. TGR write cycle T2 T1 MP TGR address Address Write signal Compare match signal TCNT N N+1 TGR N M TGR write data Figure 10.122 Contention between TGR Write and Compare Match Page 438 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.7.7 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 10.123 shows the timing in this case. TGR write cycle T1 T2 MP Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register TGR N M N Figure 10.123 Contention between Buffer Register Write and Compare Match R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 439 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.8 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 10.124 shows the timing in this case. TGR write cycle T1 T2 MP Buffer register address Address Write signal TCNT clear signal Buffer transfer signal Buffer register TGR Buffer register write data N M N Figure 10.124 Contention between Buffer Register Write and TCNT Clear Page 440 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.7.9 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 10.125 and 10.126 show the timing in this case. TGR read cycle T2 T1 MP Address TGR address Read signal Input capture signal TGR N M Internal data bus N Figure 10.125 Contention between TGR Read and Input Capture (Channels 0 to 4) TGR read cycle T2 T1 MP Address TGR address Read signal Input capture signal TGR Internal data bus N M M Figure 10.126 Contention between TGR Read and Input Capture (Channel 5) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 441 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 10.127 and 10.128 show the timing in this case. TGR write cycle T2 T1 MP Address TGR address Write signal Input capture signal TCNT M M TGR Figure 10.127 Contention between TGR Write and Input Capture (Channels 0 to 4) TGR write cycle T2 T1 MP Address TGR address Write signal Input capture signal TCNT M TGR write data TGR N Figure 10.128 Contention between TGR Write and Input Capture (Channel 5) Page 442 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.129 shows the timing in this case. Buffer register write cycle T2 T1 MP Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 10.129 Contention between Buffer Register Write and Input Capture 10.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to TGRD_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 10.130. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 443 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT write cycle T1 T2 MP Address TCNT_2 address Write signal TCNT_2 H'FFFE H'FFFF N N+1 TCNT_2 write data TGRA_2 to TGRB_2 H'FFFF Ch2 comparematch signal A/B Disabled TCNT_1 input clock TCNT_1 M TGRA_1 M Ch1 comparematch signal A TGRB_1 N M Ch1 input capture signal B TCNT_0 P TGRA_0 to TGRD_0 Q P Ch0 input capture signal A to D Figure 10.130 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection Page 444 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 10.131. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 10.131 Counter Value during Complementary PWM Mode Stop 10.7.14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 445 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 10.132 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT3 Point a TGRC_3 Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, TGRD_4 Point b TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 10.132 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode Page 446 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 10.133 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 10.133 Reset Synchronous PWM Mode Overflow Flag R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 447 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.134 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. MP TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF TCFV Disabled Figure 10.134 Contention between Overflow and Counter Clearing Page 448 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.135 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 MP TCNT address Address Write signal TCNT write data TCNT TCFV flag H'FFFF M Disabled Figure 10.135 Contention between TCNT Write and Overflow 10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 449 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00. 10.7.21 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module standby mode. 10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. The MTU2 has a function that allows simultaneous capture of TCNT_1 and TCNT_2 with a single input-capture input as the trigger. This function allows reading of the 32-bit counter such that TCNT_1 and TCNT_2 are captured at the same time. For details, see section, 10.3.8, Timer Input Capture Control Register (TICCR). Page 450 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode In complementary PWM mode, when output waveform control during synchronous counter clearing is enabled (WRE in the TWCR register set to 1), the following problems may occur when condition (1) or condition (2), below, is satisfied. * Dead time for the PWM output pins may be too short (or nonexistent). * Active-level output from the PWM negative-phase pins may occur outside the correct activelevel output interval Condition (1): When synchronous clearing occurs in the PWM output dead time interval within initial output suppression interval (10) (figure 10.136). Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or (11) and TGRB_3 TDDR, TGRA_4 TDDR, or TGRB_4 TDDR is true (figure 10.137). Synchronous clearing TGRA_3 (10) (11) (10) TCNT3 (11) Tb interval Tb interval TCNT4 TGR TDDR 0 PWM output (positive phase) PWM output (negative phase) TDDR Shortened dead time Initial output suppression Dead time Note: PWM output is low-active. Figure 10.136 Condition (1) Synchronous Clearing Example R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 451 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing (10) TGRA_3 (11) (10) (11) TCNT3 Tb interval Tb interval TCNT4 TDDR TGR 0 PWM output (positive phase) PWM output (negative phase) Active-level output occurs at synchronous clearing even though no active-level output interval has been set. Nonexistent dead time Initial output suppression Dead time Note: PWM output is low-active. Figure 10.137 Condition (2) Synchronous Clearing Example The following workaround can be used to avoid these problems. When using synchronous clearing, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. Page 452 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.8 MTU2 Output Pin Initialization 10.8.1 Operating Modes Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) The MTU2 has the following six operating modes. Waveform output is possible in all of these modes. * Normal mode (channels 0 to 4) * PWM mode 1 (channels 0 to 4) * PWM mode 2 (channels 0 to 2) * Phase counting modes 1 to 4 (channels 1 and 2) * Complementary PWM mode (channels 3 and 4) * Reset-synchronized PWM mode (channels 3 and 4) The MTU2 output pin initialization method for each of these modes is described in this section. 10.8.2 Reset Start Operation The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 453 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 10.59. Table 10.59 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (2) (3) (4) (5) (6) PWM1 (7) (8) (9) (10) (11) (12) PWM2 (13) (14) (15) (16) None None PCM (17) (18) (19) (20) None None CPWM (21) (22) None None (23) (24) (25) RPWM (26) (27) None None (28) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode Page 454 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 10.8.4 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. * When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. * When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 455 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Pin initialization procedures are described below for the numbered combinations in table 10.59. The active level is assumed to be low. Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.138 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.138 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low and ports are in the high-impedance state. 2. After a reset, the TMDR setting is for normal mode. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Page 456 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.139 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.139 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.138. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 457 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 10.140 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.140 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 10.138. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Page 458 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.141 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 13 14 12 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.141 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 10.138. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 459 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.142 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after resetting. 12 11 10 9 7 8 6 4 5 14 3 13 1 2 15 16 17 18 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) occurs (PORT) (0) (1 init (MTU2) (1) (normal) (1) (CPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.142 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.138. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR. Page 460 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 10.143 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. 6 4 5 3 1 2 PFC TSTR RESET TMDR TOER TIOR (1 init (MTU2) (1) (normal) (1) 0 out) 7 Match 10 9 8 PFC TSTR Error occurs (PORT) (0) 12 11 14 13 15 16 17 18 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.143 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 10.138. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 461 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 10.144 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.144 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. After a reset, MTU2 output is low and ports are in the high-impedance state. 2. Set PWM mode 1. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Page 462 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 10.145 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Not initialized (TIOC*B) Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.145 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.144. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 463 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 10.146 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.146 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 10.144. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Page 464 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.147 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 13 14 12 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.147 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 10.144. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 465 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.148 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after resetting. 1 2 15 16 17 18 19 14 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.148 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.144. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR. Page 466 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 10.149 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. 13 6 7 8 9 10 11 12 1 2 3 4 5 15 16 17 18 19 14 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (PWM1) (1) (1 init (MTU2) (1) (RPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.149 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 10.148. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 467 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 10.150 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (normal) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.150 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. After a reset, MTU2 output is low and ports are in the high-impedance state. 2. Set PWM mode 2. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) 4. Set MTU2 output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. Page 468 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 10.151 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Not initialized (TIOC*B) Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.151 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.150. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 469 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 10.152 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A Not initialized (cycle register) TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.152 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.150. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. Page 470 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.153 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PCM) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.153 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.150. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 471 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.154 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (normal) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.154 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low and ports are in the high-impedance state. 2. Set phase counting mode. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 4. Set MTU2 output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. Page 472 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.155 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Not initialized (TIOC*B) Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.155 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.154. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 473 of 964 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) SH7146 Group Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 10.156 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.156 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.154. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. Page 474 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.157 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PCM) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn Hi-Z PEn Hi-Z n = 0 to 15 Figure 10.157 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.154. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 475 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.158 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.158 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low and ports are in the high-impedance state. 2. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 3. Set complementary PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. The complementary PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM output initial value.) 11. Set normal mode. (MTU2 output goes low.) 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Page 476 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.159 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.159 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.158. 11. Set PWM mode 1. (MTU2 output goes low.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 477 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.160 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.160 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.158. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. Page 478 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.161 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). 1 2 3 15 16 17 5 4 6 7 8 9 10 11 12 13 14 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.161 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.158. 11. Set normal mode and make new settings. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 479 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 10.162 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. 13 14 12 11 10 9 7 8 6 4 5 1 2 3 15 16 17 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.162 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 10.158. 11. Set normal mode. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR. Page 480 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.163 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.163 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low and ports are in the high-impedance state. 2. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 3. Set reset-synchronized PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. The reset-synchronized PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized PWM output initial value.) 11. Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 481 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.164 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.164 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.163. 11. Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Page 482 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.165 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 15 16 8 9 10 11 12 13 14 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.165 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.163. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU2 cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU2 output with the PFC. 16. Operation is restarted by TSTR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 483 of 964 SH7146 Group Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 10.166 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 Hi-Z PE9 Hi-Z PE11 Hi-Z Figure 10.166 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 10.163. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence. Page 484 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) This LSI has an on-chip multi-function timer pulse unit 2S (MTU2S) that comprises three 16-bit timer channels. The MTU2S includes channels 3 to 5 of the MTU2. For details, refer to section 10, Multi-Function Timer Pulse Unit 2 (MTU2). To distinguish from the MTU2, "S" is added to the end of the MTU2S input/output pin and register names. For example, TIOC3A is called TIOC3AS and TGRA_3 is called TGRA_3S in this section. The MTU2S can operate at 80 MHz max. for complementary PWM output functions or at 40 MHz max. for the other functions. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 485 of 964 TIMMTU1A_020020030800 SH7146 Group Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Table 11.1 MTU2S Functions Item Channel 3 Channel 4 Channel 5 Count clock MI/1 MI/4 MI/16 MI/64 MI/256 MI/1024 MI/1 MI/4 MI/16 MI/64 MI/256 MI/1024 MI/1 MI/4 MI/16 MI/64 General registers TGRA_3S TGRB_3S TGRA_4S TGRB_4S TGRU_5S TGRV_5S TGRW_5S General registers/ buffer registers TGRC_3S TGRD_3S TGRC_4S TGRD_4S -- I/O pins TIOC3BS TIOC3DS TIOC4AS TIOC4BS TIOC4CS TIOC4DS Input pins TIC5US TIC5VS TIC5WS Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output -- 1 output -- -- Input capture function Synchronous operation -- PWM mode 1 -- -- -- PWM mode 2 -- -- -- Complementary PWM mode -- Reset PWM mode -- AC synchronous motor drive mode -- -- -- Phase counting mode -- -- -- Buffer operation -- Compare match output Toggle output Page 486 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Item Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Channel 3 Channel 4 Channel 5 Counter function of -- compensation for dead time -- DTC activation TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow TGR compare match or input capture A/D converter start trigger TGRA_3S compare match or input capture TGRA_4S compare match or input capture -- TCNT_4S underflow (trough) in complementary PWM mode Interrupt sources A/D converter start request delaying function 5 sources 5 sources 3 sources * Compare match or input capture 3AS * Compare match or input capture 4AS * Compare match or input capture 5US * Compare match or input capture 3BS * Compare match or input capture 4BS * Compare match or input capture 5VS * Compare match or input capture 3CS * Compare match or input capture 4CS * Compare match or input capture 5WS * Compare match or input capture 3DS * Compare match or input capture 4DS * Overflow * Overflow or underflow * A/D converter start request at a match between TADCORA_4S and TCNT_4S * A/D converter start request at a match between TADCORB_4S and TCNT_4S -- R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 -- Page 487 of 964 SH7146 Group Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Item Channel 3 Channel 4 Channel 5 Interrupt skipping function * * -- Skips TGRA_3S compare match interrupts Skips TCIV_4S interrupts [Legend] Possible : --: Not possible Page 488 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 11.1 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Input/Output Pins Table 11.2 Pin Configuration Channel Symbol 3 4 5 I/O TIOC3BS I/O TGRB_3S input capture input/output compare output/PWM output pin TIOC3DS I/O TGRD_3S input capture input/output compare output/PWM output pin TIOC4AS I/O TGRA_4S input capture input/output compare output/PWM output pin TIOC4BS I/O TGRB_4S input capture input/output compare output/PWM output pin TIOC4CS I/O TGRC_4S input capture input/output compare output/PWM output pin TIOC4DS I/O TGRD_4S input capture input/output compare output/PWM output pin TIC5US Input TGRU_5S input capture input/external pulse input pin TIC5VS Input TGRV_5S input capture input/external pulse input pin TIC5WS Input TGRW_5S input capture input/external pulse input pin R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Function Page 489 of 964 SH7146 Group Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) 11.2 Register Descriptions The MTU2S has the following registers. For details on register addresses and register states during each process, refer to section 23, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 3 is expressed as TCR_3S. Table 11.3 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Timer control register_3S TCR_3S R/W H'00 H'FFFFC600 8, 16, 32 Timer control register_4S TCR_4S R/W H'00 H'FFFFC601 8 Timer mode register_3S TMDR_3S R/W H'00 H'FFFFC602 8, 16 Timer mode register_4S TMDR_4S R/W H'00 H'FFFFC603 8 Timer I/O control register H_3S TIORH_3S R/W H'00 H'FFFFC604 8, 16, 32 Timer I/O control register L_3S TIORL_3S R/W H'00 H'FFFFC605 8 Timer I/O control register H_4S TIORH_4S R/W H'00 H'FFFFC606 8, 16 Timer I/O control register L_4S TIORL_4S R/W H'00 H'FFFFC607 8 Timer interrupt enable register_3S TIER_3S R/W H'00 H'FFFFC608 8, 16 Timer interrupt enable register_4S TIER_4S R/W H'00 H'FFFFC609 8 Timer output master enable register S TOERS R/W H'C0 H'FFFFC60A 8 Timer gate control register S TGCRS R/W H'80 H'FFFFC60D 8 Timer output control register 1S TOCR1S R/W H'00 H'FFFFC60E 8, 16 Timer output control register 2S TOCR2S R/W H'00 H'FFFFC60F 8 Timer counter_3S TCNT_3S R/W H'0000 H'FFFFC610 16, 32 Timer counter_4S TCNT_4S R/W H'0000 H'FFFFC612 16 Timer cycle data register S TCDRS R/W H'FFFF H'FFFFC614 16, 32 Timer dead time data register S TDDRS R/W H'FFFF H'FFFFC616 16 Timer general register A_3S TGRA_3S R/W H'FFFF H'FFFFC618 16, 32 Timer general register B_3S TGRB_3S R/W H'FFFF H'FFFFC61A 16 Timer general register A_4S TGRA_4S R/W H'FFFF H'FFFFC61C 16, 32 Timer general register B_4S TGRB_4S R/W H'FFFF H'FFFFC61E 16 Page 490 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Register Name Abbreviation R/W Initial Value Address Access Size Timer subcounter S TCNTSS R H'0000 H'FFFFC620 16, 32 Timer cycle buffer register S TCBRS R/W H'FFFF H'FFFFC622 16 Timer general register C_3S TGRC_3S R/W H'FFFF H'FFFFC624 16, 32 Timer general register D_3S TGRD_3S R/W H'FFFF H'FFFFC626 16 Timer general register C_4S TGRC_4S R/W H'FFFF H'FFFFC628 16, 32 Timer general register D_4S TGRD_4S R/W H'FFFF H'FFFFC62A 16 Timer status register_3S TSR_3S R/W H'C0 H'FFFFC62C 8, 16 Timer status register_4S TSR_4S R/W H'C0 H'FFFFC62D 8 Timer interrupt skipping set register S TITCRS R/W H'00 H'FFFFC630 8, 16 Timer interrupt skipping counter S TITCNTS R H'00 H'FFFFC631 8 Timer buffer transfer set register S TBTERS R/W H'00 H'FFFFC632 8 Timer dead time enable register S TDERS R/W H'01 H'FFFFC634 8 Timer output level buffer register S TOLBRS R/W H'00 H'FFFFC636 8 Timer buffer operation transfer mode register_3S TBTM_3S R/W H'00 H'FFFFC638 8, 16 Timer buffer operation transfer mode register_4S TBTM_4S R/W H'00 H'FFFFC639 8 Timer A/D converter start request control register S TADCRS R/W H'0000 H'FFFFC640 16 Timer A/D converter start request cycle set register A_4S TADCORA_4S R/W H'FFFF H'FFFFC644 16, 32 Timer A/D converter start request cycle set register B_4S TADCORB_4S R/W H'FFFF H'FFFFC646 16 Timer A/D converter start request cycle set buffer register A_4S TADCOBRA_4S R/W H'FFFF H'FFFFC648 16, 32 Timer A/D converter start request cycle set buffer register B_4S TADCOBRB_4S R/W H'FFFF H'FFFFC64A 16 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 491 of 964 SH7146 Group Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Abbreviation R/W Initial Value Address Access Size Timer synchronous clear register S TSYCRS R/W H'00 H'FFFFC650 8 Timer waveform control register S TWCRS R/W H'00 H'FFFFC660 8 Timer start register S TSTRS R/W H'00 H'FFFFC680 8, 16 Timer synchronous register S TSYRS R/W H'00 H'FFFFC681 8 Timer read/write enable register S TRWERS R/W H'01 H'FFFFC684 8 Timer counter U_5S TCNTU_5S R/W H'0000 H'FFFFC880 16, 32 Timer general register U_5S TGRU_5S R/W H'FFFF H'FFFFC882 16 Timer control register U_5S TCRU_5S R/W H'00 H'FFFFC884 8 R/W H'00 H'FFFFC886 8 Register Name Timer I/O control register U_5S TIORU_5S Timer counter V_5S TCNTV_5S R/W H'0000 H'FFFFC890 16, 32 Timer general register V_5S TGRV_5S R/W H'FFFF H'FFFFC892 16 Timer control register V_5S TCRV_5S R/W H'00 H'FFFFC894 8 R/W H'00 H'FFFFC896 8 Timer I/O control register V_5S TIORV_5S Timer counter W_5S TCNTW_5S R/W H'0000 H'FFFFC8A0 16, 32 Timer general register W_5S TGRW_5S R/W H'FFFF H'FFFFC8A2 16 Timer control register W_5S TCRW_5S R/W H'00 H'FFFFC8A4 8 Timer I/O control register W_5S TIORW_5S R/W H'00 H'FFFFC8A6 8 Timer status register_5S TSR_5S R/W H'00 H'FFFFC8B0 8 Timer interrupt enable register_5S TIER_5S R/W H'00 H'FFFFC8B2 8 Timer start register_5S TSTR_5S R/W H'00 H'FFFFC8B4 8 Timer compare match clear register S TCNTCMPCLRS R/W H'00 H'FFFFC8B6 8 Page 492 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 12 Port Output Enable (POE) Section 12 Port Output Enable (POE) The port output enable (POE) can be used to place the high-current pins (pins multiplexed with TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2 and TIOC3BS, TIOC3DS, TIOC4AS, TIOC4BS, TIOC4CS, and TIOC4DS in the MTU2S) and the pins for channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in high-impedance state, depending on the change on POE0 to POE8 input pins and the output status of the high-current pins, or by modifying register settings. It can also simultaneously generate interrupt requests. 12.1 Features * Each of the POE0 to POE8 input pins can be set for falling edge, P/8 x 16, P/16 x 16, or P/128 x 16 low-level sampling. * High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by POE0 to POE8 pin falling-edge or low-level sampling. * High-current pins can be placed in high-impedance state when the high-current pin output levels are compared and simultaneous active-level output continues for one cycle or more. * High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by modifying the POE register settings. * Interrupts can be generated by input-level sampling or output-level comparison results. The POE has input level detection circuits, output level comparison circuits, and a high-impedance request/interrupt request generating circuit as shown in figure 12.1. In addition to control by the POE, high-current pins can be placed in high-impedance state when the oscillator stops or in software standby state. For details, refer to appendix A, Pin States. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 493 of 964 SH7146 Group Section 12 Port Output Enable (POE) Figure 12.1 shows a block diagram of the POE. POECR1, POECR2 OCSR1 Output level comparison circuit Output level comparison circuit Output level comparison circuit Output level comparison circuit Input level detection circuit POE3 POE2 POE1 POE0 ICSR1 Falling edge detection circuit Low level sampling circuit Input level detection circuit POE7 POE6 POE5 POE4 High-impedance request signal for MTU2 high-current pins Output level comparison circuit ICSR2 Falling edge detection circuit Low level sampling circuit High-impedance request/interrupt request generating circuit TIOC3BS TIOC3DS TIOC4AS TIOC4CS TIOC4BS TIOC4DS Output level comparison circuit OCSR2 TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D High-impedance request signal for MTU2 channel 0 pins High-impedance request signal for MTU2S high-current pins Interrupt request signal Input level detection circuit POE8 ICSR3 Falling edge detection circuit Low level sampling circuit P/8 P/16 P/128 SPOER Frequency divider [Legend] ICSR1: ICSR2: ICSR3: OCSR1: OCSR2: P Input level control/status register 1 Input level control/status register 2 Input level control/status register 3 Output level control/status register 1 Output level control/status register 2 SPOER: Software port output enable register POECR1: Port output enable control register 1 POECR2: Port output enable control register 2 Figure 12.1 Block Diagram of POE Page 494 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 12.2 Section 12 Port Output Enable (POE) Input/Output Pins Table 12.1 Pin Configuration Name I/O Description Port output enable input pins POE0 to POE3 0 to 3 Input Input request signals to place highcurrent pins for MTU2 in highimpedance state* Port output enable input pins POE4 to POE7 4 to 7 Input Input request signals to place highcurrent pins for MTU2S in highimpedance state* Port output enable input pin 8 POE8 Input Inputs a request signal to place pins for channel 0 in MTU2 in highimpedance state* Note: Symbol * When the selected functions of pins PB16/POE3, PB17/POE7, and PB18/POE8 are for the POE in the PFC, the pins are pulled up inside the LSI if nothing is input to them. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 495 of 964 SH7146 Group Section 12 Port Output Enable (POE) Table 12.2 shows output-level comparisons with pin combinations. Table 12.2 Pin Combinations Pin Combination I/O PE9/TIOC3B and PE11/TIOC3D Output The high-current pins for the MTU2 are placed in high-impedance state when the pins simultaneously output an active level (low level when the output level select P (OLSP) bit of the timer output control register (TOCR) in the MTU2 is 0 or high level when the bit is 1) for one or more cycles of the peripheral clock (P). PE12/TIOC4A and PE14/TIOC4C PE13/TIOC4B and PE15/TIOC4D Description This active level comparison is done when the MTU2 output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and highimpedance control can be selected by POE registers. PE16/TIOC3BS and PE17/TIOC3DS Output The high-current pins for the MTU2S are placed in high-impedance state when the pins PE18/TIOC4AS and PE20/TIOC4CS simultaneously output an active level (low level PE19/TIOC4BS and PE21/TIOC4DS when the output level select P (OLSP) bit of the timer output control register (TOCR) in the MTU2S is 0 or high level when the bit is 1) for one or more cycles of the peripheral clock (P). This active level comparison is done when the MTU2S output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and highimpedance control can be selected by POE registers. Page 496 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 12.3 Section 12 Port Output Enable (POE) Register Descriptions The POE has the following registers. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 12.3 Register Configuration Abbreviation R/W Initial Value Address Access Size Input level control/status register 1 ICSR1 R/W H'0000 H'FFFFD000 8, 16, 32 Output level control/status register 1 OCSR1 R/W H'0000 H'FFFFD002 8, 16 Input level control/status register 2 ICSR2 R/W H'0000 H'FFFFD004 8, 16, 32 Output level control/status register 2 OCSR2 R/W H'0000 H'FFFFD006 8, 16 Input level control/status register 3 ICSR3 R/W H'0000 H'FFFFD008 8, 16 Software port output enable register SPOER R/W H'00 H'FFFFD00A 8 Port output enable control register 1 POECR1 R/W H'00 H'FFFFD00B 8 Port output enable control register 2 POECR2 R/W H'7700 H'FFFFD00C 8, 16 Register Name R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 497 of 964 SH7146 Group Section 12 Port Output Enable (POE) 12.3.1 Input Level Control/Status Register 1 (ICSR1) ICSR1 is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: 15 14 13 12 POE3F POE2F POE1F POE0F Initial value: 0 0 0 0 R/W:R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 11 10 9 8 - - - PIE1 0 R 0 R 0 R 0 R/W 7 6 POE3M[1:0] 5 4 POE2M[1:0] 3 2 POE1M[1:0] 1 0 POE0M[1:0] 0 0 0 0 0 0 0 0 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name POE3F Initial value 0 R/W Description 1 R/(W)* POE3 Flag This flag indicates that a high impedance request has been input to the POE3 pin. [Clearing conditions] * By writing 0 to POE3F after reading POE3F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR1) * By writing 0 to POE3F after reading POE3F = 1 after a high level input to POE3 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR1) [Setting condition] * Page 498 of 964 When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit 14 Bit Name POE2F Section 12 Port Output Enable (POE) Initial value 0 R/W Description 1 R/(W)* POE2 Flag This flag indicates that a high impedance request has been input to the POE2 pin. [Clearing conditions] * By writing 0 to POE2F after reading POE2F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR1) * By writing 0 to POE2F after reading POE2F = 1 after a high level input to POE2 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR1) [Setting condition] * 13 POE1F 0 When the input set by ICSR1 bits 5 and 4 occurs at the POE2 pin 1 R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions] * By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1) * By writing 0 to POE1F after reading POE1F = 1 after a high level input to POE1 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR1) [Setting condition] * R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin Page 499 of 964 SH7146 Group Section 12 Port Output Enable (POE) Bit 12 Bit Name POE0F Initial value 0 R/W Description 1 R/(W)* POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin. [Clearing conditions] * By writing 0 to POE0F after reading POE0F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR1) * By writing 0 to POE0F after reading POE0F = 1 after a high level input to POE0 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR1) [Setting condition] * 11 to 9 All 0 R When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin Reserved These bits are always read as 0. The write value should always be 0. 8 PIE1 0 R/W Port Interrupt Enable 1 This bit enables/disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0] 00 R/W* 2 POE3 mode 1, 0 These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE3 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE3 input has been sampled for 16 P/128 clock pulses and all are low level. Page 500 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit 5, 4 Bit Name Section 12 Port Output Enable (POE) Initial value POE2M[1:0] 00 R/W R/W* Description 2 POE2 mode 1, 0 These bits select the input mode of the POE2 pin. 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE2 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE2 input has been sampled for 16 P/128 clock pulses and all are low level. 3, 2 POE1M[1:0] 00 R/W* 2 POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE1 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE1 input has been sampled for 16 P/128 clock pulses and all are low level. 1, 0 POE0M[1:0] 00 R/W* 2 POE0 mode 1, 0 These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE0 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE0 input has been sampled for 16 P/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 501 of 964 SH7146 Group Section 12 Port Output Enable (POE) 12.3.2 Output Level Control/Status Register 1 (OCSR1) OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - OCE1 OIE1 - - - - - - - - Initial value: 0 0 R/W:R/(W)*1 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R OSF1 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name OSF1 Initial value 0 R/W Description 1 R/(W)* Output Short Flag 1 This flag indicates that any one of the three pairs of MTU2 2-phase outputs to be compared has simultaneously become an active level. [Clearing condition] * By writing 0 to OSF1 after reading OSF1 = 1 [Setting condition] * 14 to 10 9 OCE1 All 0 R When any one of the three pairs of 2-phase outputs has simultaneously become an active level Reserved These bits are always read as 0. The write value should always be 0. 0 R/W* 2 Output Short High-Impedance Enable 1 This bit specifies whether to place the pins in highimpedance state when the OSF1 bit in OCSR1 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 OIE1 0 R/W Output Short Interrupt Enable 1 This bit enables or disables interrupt requests when the OSF1 bit in OCSR is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled Page 502 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 12 Port Output Enable (POE) Bit Bit Name Initial value R/W Description 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. 12.3.3 Input Level Control/Status Register 2 (ICSR2) ICSR2 is a 16-bit readable/writable register that selects the POE4 to POE7 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: 15 14 13 12 POE7F POE6F POE5F POE4F Initial value: 0 0 0 0 R/W:R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 11 10 9 8 - - - PIE2 0 R 0 R 0 R 0 R/W 7 6 POE7M[1:0] 5 4 POE6M[1:0] 3 2 POE5M[1:0] 1 0 POE4M[1:0] 0 0 0 0 0 0 0 0 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name POE7F Initial value 0 R/W Description 1 R/(W)* POE7 Flag This flag indicates that a high impedance request has been input to the POE7 pin. [Clearing conditions] * By writing 0 to POE7F after reading POE7F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR2) * By writing 0 to POE7F after reading POE7F = 1 after a high level input to POE7 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR2) [Setting condition] * R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 When the input condition set by bits 7 and 6 in ICSR2 occurs at the POE7 pin Page 503 of 964 SH7146 Group Section 12 Port Output Enable (POE) Bit 14 Bit Name POE6F Initial value 0 R/W Description 1 R/(W)* POE6 Flag This flag indicates that a high impedance request has been input to the POE6 pin. [Clearing conditions] * By writing 0 to POE6F after reading POE6F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR2) * By writing 0 to POE6F after reading POE6F = 1 after a high level input to POE6 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR2) [Setting condition] * 13 POE5F 0 When the input condition set by bits 5 and 4 in ICSR2 occurs at the POE6 pin 1 R/(W)* POE5 Flag This flag indicates that a high impedance request has been input to the POE5 pin. [Clearing conditions] * By writing 0 to POE5F after reading POE5F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR2) * By writing 0 to POE5F after reading POE5F = 1 after a high level input to POE5 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR2) [Setting condition] * Page 504 of 964 When the input condition set by bits 3 and 2 in ICSR2 occurs at the POE5 pin R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit 12 Bit Name POE4F Section 12 Port Output Enable (POE) Initial value 0 R/W Description 1 R/(W)* POE4 Flag This flag indicates that a high impedance request has been input to the POE4 pin. [Clearing conditions] * By writing 0 to POE4F after reading POE4F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR2) * By writing 0 to POE4F after reading POE4F = 1 after a high level input to POE4 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR2) [Setting condition] * 11 to 9 -- All 0 R When the input condition set by bits 1 and 0 in ICSR2 occurs at the POE4 pin Reserved These bits are always read as 0. The write value should always be 0. 8 PIE2 0 R/W Port Interrupt Enable 2 This bit enables/disables interrupt requests when any one of the POE4F to POE7F bits of the ICSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE7M[1:0] 00 R/W* 2 POE7 mode 1 and 0 These bits select the input mode of the POE7 pin. 00: Accept request on falling edge of POE7 input 01: Accept request when POE7 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE7 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE7 input has been sampled for 16 P/128 clock pulses and all are at a low level. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 505 of 964 SH7146 Group Section 12 Port Output Enable (POE) Bit 5, 4 Bit Name Initial value POE6M[1:0] 00 R/W R/W* Description 2 POE6 mode 1 and 0 These bits select the input mode of the POE6 pin. 00: Accept request on falling edge of POE6 input 01: Accept request when POE6 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE6 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE6 input has been sampled for 16 P/128 clock pulses and all are at a low level. 3, 2 POE5M[1:0] 00 R/W* 2 POE5 mode 1 and 0 These bits select the input mode of the POE5 pin. 00: Accept request on falling edge of POE5 input 01: Accept request when POE5 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE5 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE5 input has been sampled for 16 P/128 clock pulses and all are at a low level. 1, 0 POE4M[1:0] 00 R/W* 2 POE4 mode 1 and 0 These bits select the input mode of the POE4 pin. 00: Accept request on falling edge of POE4 input 01: Accept request when POE4 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE4 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE4 input has been sampled for 16 P/128 clock pulses and all are at a low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Page 506 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 12.3.4 Section 12 Port Output Enable (POE) Output Level Control/Status Register 2 (OCSR2) OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - - - - OCE2 OIE2 - - - - - - - - Initial value: 0 0 R/W:R/(W)*1 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R OSF2 0 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name OSF2 Initial value 0 R/W Description 1 R/(W)* Output Short Flag 2 This flag indicates that any one of the three pairs of MTU2S 2-phase outputs to be compared has simultaneously become an active level. [Clearing condition] * By writing 0 to OSF2 after reading OSF2 = 1 [Setting condition] * 14 to 10 9 OCE2 All 0 R When any one of the three pairs of 2-phase outputs has simultaneously become an active level Reserved These bits are always read as 0. The write value should always be 0. 0 R/W* 2 Output Short High-Impedance Enable 2 This bit specifies whether to place the pins in highimpedance state when the OSF2 bit in OCSR2 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 OIE2 0 R/W Output Short Interrupt Enable 2 This bit enables or disables interrupt requests when the OSF2 bit in OCSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 507 of 964 SH7146 Group Section 12 Port Output Enable (POE) Bit Bit Name Initial value R/W Description 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. 12.3.5 Input Level Control/Status Register 3 (ICSR3) ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the enable/disable of interrupts, and indicates status. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - POE8F - - POE8E PIE3 - - - - - - POE8M[1:0] 1 Initial value: 0 R/W: R 0 R 0 R 0 R/(W)*1 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W*2 0 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit Bit Name Initial value R/W Description 15 to 13 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 POE8F 0 R/(W)* 1 POE8 Flag This flag indicates that a high impedance request has been input to the POE8 pin. [Clearing conditions] * By writing 0 to POE8F after reading POE8F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR3) * By writing 0 to POE8F after reading POE8F = 1 after a high level input to POE8 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR3) [Setting condition] * Page 508 of 964 When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 12 Port Output Enable (POE) Bit Bit Name Initial value R/W 11, 10 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 9 POE8E 0 R/W* 2 POE8 High-Impedance Enable This bit specifies whether to place the pins in highimpedance state when the POE8F bit in ICSR3 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 PIE3 0 R/W Port Interrupt Enable 3 This bit enables or disables interrupt requests when the POE8 bit in ICSR3 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 POE8M[1:0] 00 R/W* 2 POE8 mode 1 and 0 These bits select the input mode of the POE8 pin. 00: Accept request on falling edge of POE8 input 01: Accept request when POE8 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE8 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE8 input has been sampled for 16 P/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 509 of 964 SH7146 Group Section 12 Port Output Enable (POE) 12.3.6 Software Port Output Enable Register (SPOER) SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: Bit Bit Name 7 to 3 -- 7 6 5 4 3 2 - - - - - MTU2S HIZ 0 R 0 R 0 R 0 R 0 R 0 R/W Initial value R/W Description All 0 R Reserved 1 0 MTU2 MTU2 CH0HIZ CH34HIZ 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 2 MTU2SHIZ 0 R/W MTU2S Output High-Impedance This bit specifies whether to place the high-current pins for the MTU2S in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] * Power-on reset * By writing 0 to MTU2SHIZ after reading MTU2SHIZ = 1 1: Places the pins in high-impedance state [Setting condition] * 1 MTU2CH0HIZ 0 R/W By writing 1 to MTU2SHIZ MTU2 Channel 0 Output High-Impedance This bit specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] * Power-on reset * By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ = 1 1: Places the pins in high-impedance state [Setting condition] * Page 510 of 964 By writing 1 to MTU2CH0HIZ R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 12 Port Output Enable (POE) Initial value Bit Bit Name 0 MTU2CH34HIZ 0 R/W Description R/W MTU2 Channel 3 and 4 Output High-Impedance This bit specifies whether to place the high-current pins for the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] * Power-on reset * By writing 0 to MTU2CH34HIZ after reading MTU2CH34HIZ = 1 1: Places the pins in high-impedance state [Setting condition] * 12.3.7 By writing 1 to MTU2CH34HIZ Port Output Enable Control Register 1 (POECR1) POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - MTU2 PE3ZE MTU2 PE2ZE MTU2 PE1ZE MTU2 PE0ZE 0 R 0 R 0 R 0 R 0 0 0 0 R/W* R/W* R/W* R/W* Note: * Can be modified only once after a power-on reset. Bit Bit Name Initial value R/W 7 to 4 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 3 MTU2PE3ZE 0 R/W* MTU2 PE3 High-Impedance Enable This bit specifies whether to place the PE3/TIOC0D pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 511 of 964 SH7146 Group Section 12 Port Output Enable (POE) Bit Bit Name Initial value R/W Description 2 MTU2PE2ZE 0 R/W* MTU2 PE2 High-Impedance Enable This bit specifies whether to place the PE2/TIOC0C pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 1 MTU2PE1ZE 0 R/W* MTU2 PE1 High-Impedance Enable This bit specifies whether to place the PE1/TIOC0B pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 0 MTU2PE0ZE 0 R/W* MTU2 PE0 High-Impedance Enable This bit specifies whether to place the PE0/TIOC0A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state Note: * Can be modified only once after a power-on reset. Page 512 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 12.3.8 Section 12 Port Output Enable (POE) Port Output Enable Control Register 2 (POECR2) POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins. Bit: 15 - Initial value: 0 R/W: R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MTU2 P1CZE MTU2 P2CZE MTU2 P3CZE - MTU2S P1CZE MTU2S P2CZE MTU2S P3CZE - - - - - - - - 1 1 1 R/W* R/W* R/W* 0 R 1 1 1 R/W* R/W* R/W* 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note: * Can be modified only once after a power-on reset. Bit Bit Name Initial value R/W Description 15 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 MTU2P1CZE 1 R/W* MTU2 Port 1 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE9/TIOC3B and PE11/TIOC3D pins and to place them in highimpedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 13 MTU2P2CZE 1 R/W* MTU2 Port 2 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in highimpedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 513 of 964 SH7146 Group Section 12 Port Output Enable (POE) Bit Bit Name Initial value R/W Description 12 MTU2P3CZE 1 R/W* MTU2 Port 3 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE13/TIOC4B and PE15/TIOC4D pins and to place them in highimpedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 11 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 MTU2SP1CZE 1 R/W* MTU2S Port 1 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2S high-current PE16/TIOC3BS and PE17/TIOC3DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Page 514 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 12 Port Output Enable (POE) Initial value Bit Bit Name 9 MTU2SP2CZE 1 R/W Description R/W* MTU2S Port 2 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2S high-current PE18/TIOC4AS and PE20/TIOC4CS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 8 MTU2SP3CZE 1 R/W* MTU2S Port 3 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2S high-current PE19/TIOC4BS and PE21/TIOC4DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 7 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * Can be modified only once after a power-on reset. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 515 of 964 SH7146 Group Section 12 Port Output Enable (POE) 12.4 Operation Table 12.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 12.4 Target Pins and Conditions for High-Impedance Control Pins Conditions Detailed Conditions MTU2 high-current pins (PE9/TIOC3B and PE11/TIOC3D) Input level detection, output level comparison, or SPOER setting MTU2P1CZE * ((POE3F + POE2F + POE1F + POE0F) + (OSF1 * OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE12/TIOC4A and PE14/TIOC4C) Input level detection, output level comparison, or SPOER setting MTU2P2CZE * ((POE3F + POE2F + POE1F + POE0F) + (OSF1 * OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE13/TIOC4B and PE15/TIOC4D) Input level detection, output level comparison, or SPOER setting MTU2P3CZE * ((POE3F + POE2F + POE1F + POE0F) + (OSF1 * OCE1) + (MTU2CH34HIZ)) MTU2S high-current pins Input level detection, (PE16/TIOC3BS and output level comparison, or PE17/TIOC3DS) SPOER setting MTU2SP1CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2S high-current pins Input level detection, (PE18/TIOC4AS and output level comparison, or PE20/TIOC4CS) SPOER setting MTU2SP2CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2S high-current pins Input level detection, (PE19/TIOC4BS and output level comparison, or PE21/TIOC4DS) SPOER setting MTU2SP3CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2 channel 0 pin (PE0/TIOC0A) Input level detection or SPOER setting MTU2PE0ZE ((POE8F * POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE1/TIOC0B) Input level detection or SPOER setting MTU2PE1ZE ((POE8F * POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE2/TIOC0C) Input level detection or SPOER setting MTU2PE2ZE ((POE8F * POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE3/TIOC0D) Input level detection or SPOER setting MTU2PE3ZE ((POE8F * POE8E) + (MTU2CH0HIZ)) Page 516 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 12.4.1 Section 12 Port Output Enable (POE) Input Level Detection Operation If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however, that these high-current and MTU2 pins enter high-impedance state only when general input/output function, MTU2 function, or MTU2S function is selected for these pins. (1) Falling Edge Detection When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 12.2 shows a sample timing after the level changes in input to the POE0 to POE8 pins until the respective pins enter high-impedance state. P P rising edge POE input Falling edge detection PE9/TIOC3B High-impedance state* Note: * The other high-current pins also enter the high-impedance state in the similar timing. Figure 12.2 Falling Edge Detection (2) Low-Level Detection Figure 12.3 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this interval, the low level is not accepted. The timing when the high-current pins enter the high-impedance state after the sampling clock is input is the same in both falling-edge detection and in low-level detection. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 517 of 964 SH7146 Group Section 12 Port Output Enable (POE) 8/16/128 clock cycles P Sampling clock POE input PE9/ TIOC3B High-impedance state* When low level is sampled at all points 1 2 When high level is sampled at least once 1 2 3 16 Flag set (POE received) 13 Flag not set Note: * Other high-current pins also go to the high-impedance state at the same timing. Figure 12.3 Low-Level Detection Operation 12.4.2 Output-Level Compare Operation Figure 12.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. P Low level overlapping detected PE9/ TIOC3B PE11/ TIOC3D High impedance state Figure 12.4 Output-Level Compare Operation Page 518 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 12.4.3 Section 12 Port Output Enable (POE) Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the flags in bits 12 to 15 (POE0F to POE8F) of ICSR1 to ICSR3. However, note that when lowlevel sampling is selected by bits 0 to 7 in ICSR1 to ICSR3, just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to the POE pin and is sampled. High-current pins that have entered high-impedance state due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing the flag in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S internal registers. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 519 of 964 SH7146 Group Section 12 Port Output Enable (POE) 12.5 Interrupts The POE issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 12.5 shows the interrupt sources and their conditions. Table 12.5 Interrupt Sources and Conditions Name Interrupt Source Interrupt Flag Condition OEI1 Output enable interrupt 1 POE3F, POE2F, POE1F, POE0F, and OSF1 PIE1 * (POE3F + POE2F + POE1F + POE0F) + OIE1 * OSF1 OEI3 Output enable interrupt 3 POE8F PIE3 * POE8F OEI2 Output enable interrupt 2 POE4F, POE5F, POE6F, POE7F, and OSF2 PIE2 * (POE4F + POE5F + POE6F + POE7F) + OIE2 * OSF2 Page 520 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 12 Port Output Enable (POE) 12.6 Usage Note 12.6.1 Pin State When a Power-On Reset Is Issued from the Watchdog Timer When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function controller (PFC) sets initial values that select the general input function for the I/O ports. However, when a power-on reset is issued from the WDT while a pin is being handled as high impedance by the port output enable (POE), the pin is placed in the output state for one cycle of the peripheral clock (P), after which the function is switched to general input. This also occurs when a power-on reset is issued from the WDT for pins that are being handled as high impedance due to short-circuit detection by the MTU2 and MTU2S. Figure 12.5 shows the state of a pin for which the POE input has selected high impedance handling with the timer output selected when a power-on reset is issued from the WDT. P POE input Pin state Timer output High impedance state Timer output General input 1P cycle PFC setting value Timer output General input Power-on reset by WDT Figure 12.5 Pin State When a Power-On Reset Is Issued from the Watchdog Timer R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 521 of 964 Section 12 Port Output Enable (POE) Page 522 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 13 Watchdog Timer (WDT) Section 13 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT). This LSI can be reset by the overflow of the counter when the value of the counter has not been updated because of a system runaway. The watchdog timer (WDT) is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when revoking software standby mode. It can also be used as an interval timer. 13.1 Features * Can be used to ensure the clock settling time: Use the WDT to revoke software standby mode. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. * An interrupt is generated in interval timer mode An interval timer interrupt is generated when the counter overflows. * Choice of eight counter input clocks Eight clocks (x1 to x1/4096) that are obtained by dividing the peripheral clock can be chosen. * Choice of two resets Power-on reset and manual reset are available. Figure 13.1 shows a block diagram of the WDT. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 523 of 964 WDTS300B_000020030200 SH7146 Group Section 13 Watchdog Timer (WDT) WDT Standby cancellation Standby mode Standby control Peripheral clock (P) WDTOVF Internal reset request Divider Reset control Clock selection Clock selector Interrupt request Overflow Interrupt control Clock WTCSR WTCNT Bus interface Internal bus [Legend] WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 13.1 Block Diagram of WDT Page 524 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 13.2 Section 13 Watchdog Timer (WDT) Input/Output Pin for WDT Table 13.1 lists the WDT pin configuration. Table 13.1 WDT Pin Configuration Pin Name Abbreviation I/O Watchdog timer overflow WDTOVF R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Description Output When an overflow occurs in watchdog timer mode, an internal reset is generated and this pin outputs the low level for one clock cycle specified by the CKS2 to CKS0 bits in WTCSR. Page 525 of 964 SH7146 Group Section 13 Watchdog Timer (WDT) 13.3 Register Descriptions The WDT has the following two registers. Refer to section 23, List of Registers, for the details of the addresses of these registers and the state of registers in each operating mode. Table 13.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Watchdog timer counter WTCNT R/W H'00 H'FFFFE810 8, 16 Watchdog timer control/status register WTCSR R/W H'00 H'FFFFE812 8, 16 13.3.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The WTCNT counter is initialized to H'00 only by a power-on reset using the RES pin. Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT. Note: WTCNT differs from other registers in that it is more difficult to write to. See section 13.3.3, Notes on Register Access, for details. Bit: 7 Initial value: 0 R/W: R/W Page 526 of 964 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 13.3.2 Section 13 Watchdog Timer (WDT) Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset using the RES pin. When used to count the clock settling time for revoking a software standby, it retains its value after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Note: WTCSR differs from other registers in that it is more difficult to write to. See section 13.3.3, Notes on Register Access, for details. Bit: 7 6 5 4 3 TME WT/IT RSTS WOVF IOVF Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 TME 0 R/W 2 1 0 CKS[2:0] 0 R/W 0 R/W 0 R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT to revoke software standby mode. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Interval timer mode 1: Watchdog timer mode Note: If WT/IT is modified when the WDT is operating, the up-count may not be performed correctly. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 527 of 964 SH7146 Group Section 13 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 5 RSTS 0 R/W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode 2 to 0 CKS[2:0] 000 R/W Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (P). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P) is 40 MHz. 000: P (6.4 s) 001: P /4 (25.6 s) 010: P /16 (102.4 s) 011: P /32 (204.8 s) 100: P /64 (409.6 s) 101: P /256 (1.64 ms) 110: P /1024 (6.55 ms) 111: P /4096 (26.21 ms) Note: If bits CKS2 to CKS0 are modified when the WDT is operating, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not operating. Page 528 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 13.3.3 Section 13 Watchdog Timer (WDT) Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 13.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write 15 Address: H'FFFFE810 WTCSR write Address: H'FFFFE812 8 7 H'5A 15 8 H'A5 0 Write data 7 0 Write data Figure 13.2 Writing to WTCNT and WTCSR R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 529 of 964 SH7146 Group Section 13 Watchdog Timer (WDT) 13.4 Operation 13.4.1 Revoking Software Standbys The WDT can be used to revoke software standby mode with an NMI interrupt or external interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used for revoking, so keep the RES pin low until the clock stabilizes.) 1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Transition to software standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin. 5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes operation. The WOVF flag in WTCSR is not set when this happens. 13.4.2 Using Watchdog Timer Mode While operating in watchdog timer mode, the WDT generates an internal reset of the type specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time the counter overflows. 1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0 bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes counting. Page 530 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 13 Watchdog Timer (WDT) WTCNT value Overflow occurs H'FF Time H'00 WT/IT = 1 TME = 1 H'00 is written to WTCNT WOVF = 1 H'00 is written to WTCNT WDTOVF is asserted and an internal reset is generated Count starts WDTOVF signal 32 P clock Internal reset signal (power-on reset selected) 3 P + one cycle of count clock Internal reset signal (manual reset selected) 18 P clock Figure 13.3 Operation in Watchdog Timer Mode (When WTCNT Count Clock Is Specified to P/32 by CKS2 to CKS0) 13.4.3 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 531 of 964 SH7146 Group Section 13 Watchdog Timer (WDT) 13.5 Interrupt Source The WDT has one interrupt source: the interval timer interrupt (ITI). Table 13.3 shows this interrupt source. An interval timer interrupt (ITI) is generated when the interval timer overflow flag bit (IOVF) in the watchdog timer control status register (WTSCR) is set to 1. The interrupt request is canceled by clearing the interrupt flag to 0. Table 13.3 Interrupt Source Name Interrupt Source Interrupt Enable Bit Interrupt Flag Bit ITI Interval timer interrupt Interval timer overflow flag (IOVF) 13.6 Usage Note 13.6.1 WTCNT Setting Value If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT changes from H'FF to H'00 after one cycle of count clock, but overflow occurs when WTCNT changes from H'FF to H'00 after 257 cycles of count clock. If WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from H'FF to H'00 after one cycle of count clock. Page 532 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Section 14 Serial Communication Interface (SCI) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). 14.1 Features * Choice of asynchronous or clock synchronous serial communication mode * Asynchronous mode: Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are twelve selectable serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor communications Receive error detection: Parity, overrun, and framing errors Break detection: Break is detected by reading the RXD pin level directly when a framing error occurs. * Clock synchronous mode: Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clock synchronous communication function. Data length: 8 bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so highspeed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source: From either baud rate generator (internal clock) or SCK pin (external clock) * Choice of LSB-first or MSB-first data transfer (except for 7-bit data in asynchronous mode) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 533 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) * Four types of interrupts: There are four interrupt sources, transmit-data-empty, transmit end, receive-data-full, and receive error interrupts, and each interrupt can be requested independently. The data transfer controller (DTC) can be activated by the transmit-data-empty interrupt or receive-data-full interrupt to transfer data. * Module standby mode can be set Bus interface Figure 14.1 shows a block diagram of the SCI. Module data bus SCRDR SCTDR Internal data bus SCBRR SCSSR SCSCR SCSMR Baud rate generator SCSPTR RXD SCRSR SCTSR TXD Parity generation SCSDCR Transmission/reception control P P/4 P/16 P/64 Clock Parity check External clock SCK TEI TXI RXI ERI SCI [Legend] SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: SCSCR: SCSSR: SCBRR: SCSPTR: SCSDCR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Serial direction control register Figure 14.1 Block Diagram of SCI Page 534 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.2 Section 14 Serial Communication Interface (SCI) Input/Output Pins The SCI has the serial pins summarized in table 14.1. Table 14.1 Pin Configuration Channel Pin Name* 0 SCK0 I/O SCI0 clock input/output RXD0 Input SCI0 receive data input TXD0 Output SCI0 transmit data output SCK1 I/O SCI1 clock input/output RXD1 Input SCI1 receive data input TXD1 Output SCI1 transmit data output SCK2 I/O SCI2 clock input/output RXD2 Input SCI2 receive data input TXD2 Output SCI2 transmit data output 1 2 Note: * Function Pin names SCK, RXD, and TXD are used in the description for all channels, omitting the channel designation. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 I/O Page 535 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.3 Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 14.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 Serial mode register_0 SCSMR_0 R/W H'00 H'FFFFC000 8 Bit rate register_0 SCBRR_0 R/W H'FF H'FFFFC002 8 Serial control register_0 SCSCR_0 R/W H'00 H'FFFFC004 8 Transmit data register_0 SCTDR_0 H'FFFFC006 8 Serial status register_0 R/W H'84 H'FFFFC008 8 H'FFFFC00A 8 SCSSR_0 Receive data register_0 SCRDR_0 1 Serial direction control register_0 SCSDCR_0 R/W H'F2 H'FFFFC00C 8 Serial port register_0 SCSPTR_0 R/W H'0x H'FFFFC00E 8 Serial mode register_1 SCSMR_1 R/W H'00 H'FFFFC080 8 Bit rate register_1 SCBRR_1 R/W H'FF H'FFFFC082 8 Serial control register_1 SCSCR_1 R/W H'00 H'FFFFC084 8 Transmit data register_1 SCTDR_1 H'FFFFC086 8 Serial status register_1 SCSSR_1 Receive data register_1 SCRDR_1 2 R/W H'84 H'FFFFC088 8 H'FFFFC08A 8 Serial direction control register_1 SCSDCR_1 R/W H'F2 H'FFFFC08C 8 Serial port register_1 SCSPTR_1 R/W H'0x H'FFFFC08E 8 Serial mode register_2 SCSMR_2 R/W H'00 H'FFFFC100 8 Bit rate register_2 SCBRR_2 R/W H'FF H'FFFFC102 8 Serial control register_2 SCSCR_2 R/W H'00 H'FFFFC104 8 Transmit data register_2 SCTDR_2 H'FFFFC106 8 Serial status register_2 R/W H'84 H'FFFFC108 8 H'FFFFC10A 8 SCSSR_2 Receive data register_2 SCRDR_2 Serial direction control register_2 SCSDCR_2 R/W H'F2 H'FFFFC10C 8 Serial port register_2 SCSPTR_2 H'0x H'FFFFC10E 8 Page 536 of 964 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.3.1 Section 14 Serial Communication Interface (SCI) Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly. 14.3.2 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Receive Data Register (SCRDR) SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and completes operation. After that, SCRSR is ready to receive data. Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously. SCRDR is a read-only register and cannot be written to by the CPU. 14.3.3 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Transmit Shift Register (SCTSR) SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to SCTSR directly. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 537 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.3.4 Transmit Data Register (SCTDR) SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be written or read to by the CPU. 14.3.5 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Serial Mode Register (SCSMR) SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. Bit: 7 6 5 4 3 2 C/A CHR PE O/E STOP MP 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: 0 R/W: R/W Bit Bit Name Initial value R/W Description 7 C/A 0 R/W Communication Mode 1 0 CKS[1:0] 0 R/W 0 R/W Selects whether the SCI operates in asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode 6 CHR Page 538 of 964 0 R/W Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. 0: 8-bit data 1: 7-bit data R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W Description 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. 4 O/E 0 R/W Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity 1: Odd parity If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 539 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W Description 3 STOP 0 R/W Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. 0: One stop bit* 1 1: Two stop bits* 2 When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1 bits are added at the end of each transmitted character. 2 MP 0 R/W Multiprocessor Mode (only in asynchronous mode) Enables or disables multiprocessor mode. The PE and O/E bit settings are ignored in multiprocessor mode. 0: Multiprocessor mode disabled 1: Multiprocessor mode enabled 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 14.3.10, Bit Rate Register (SCBRR). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock Page 540 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.3.6 Section 14 Serial Communication Interface (SCI) Serial Control Register (SCSCR) SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt requests and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: 7 6 5 4 3 2 TIE RIE TE RE MPIE TEIE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: 0 R/W: R/W Bit Bit Name Initial value R/W 7 TIE 0 R/W 1 0 CKE[1:0] 0 R/W 0 R/W Description Transmit Interrupt Enable Enables or disables a transmit-data-empty interrupt (TXI) to be issued when the TDRE flag in the serial status register (SCSSR) is set to 1 after serial transmit data is sent from the transmit data register (SCTDR) to the transmit shift register (SCTSR). TXI can be canceled by clearing the TDRE flag to 0 after reading TDRE = 1 or by clearing the TIE bit to 0. 0: Transmit-data-empty interrupt request (TXI) is disabled 1: Transmit-data-empty interrupt request (TXI) is enabled 6 RIE 0 R/W Receive Interrupt Enable Enables or disables a receive-data-full interrupt (RXI) and a receive error interrupt (ERI) to be issued when the RDRF flag in SCSSR is set to 1 after the serial data received is transferred from the receive shift register (SCRSR) to the receive data register (SCRDR). RXI can be canceled by clearing the RDRF flag after reading RDRF =1. ERI can be canceled by clearing the FER, PER, or ORER flag to 0 after reading 1 from the flag. Both RXI and ERI can also be canceled by clearing the RIE bit to 0. 0: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled 1: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 541 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W Description 5 TE 0 R/W Transmit Enable Enables or disables the SCI serial transmitter. 0: Transmitter disabled* 1: Transmitter enabled* 1 2 Notes: 1. The TDRE flag in SCSSR is fixed at 1. 2. Serial transmission starts after writing transmit data into SCTDR and clearing the TDRE flag in SCSSR to 0 while the transmitter is enabled. Select the transmit format in the serial mode register (SCSMR) before setting TE to 1. 4 RE 0 R/W Receive Enable Enables or disables the SCI serial receiver. 0: Receiver disabled* 1 2 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clock synchronous mode. Select the receive format in SCSMR before setting RE to 1. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (only when MP = 1 in SCSMR in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped and setting of the RDRF, FER, and ORER status flags in SCSSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared to 0 and normal receiving operation is resumed. For details, refer to section 14.4.4, Multiprocessor Communication Function. Page 542 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W Description 2 TEIE 0 R/W Transmit End Interrupt Enable Enables or disables a transmit end interrupt (TEI) to be issued when no valid transmit data is found in SCTDR during MSB data transmission. TEI can be canceled by clearing the TEND flag to 0 (by clearing the TDRE flag in SCSSR to 0 after reading TDRE = 1) or by clearing the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled 1: Transmit end interrupt request (TEI) is enabled 1, 0 CKE[1:0] 00 R/W Clock Enable 1 and 0 Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. When selecting the clock output in clock synchronous mode, set the C/A bit in SCSMR to 1 and then set bits CKE1 and CKE0. For details on clock source selection, refer to table 14.14. * Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored.) 01: Internal clock, SCK pin used for clock output* 1 10: External clock, SCK pin used for clock input* 2 11: External clock, SCK pin used for clock input* 2 * Clock synchronous mode 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 543 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.3.7 Serial Status Register (SCSSR) SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF, ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The TEND flag is a read-only bit and cannot be modified. Bit: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 R 0 R 0 R/W Initial value: 1 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Indicates whether data has been transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR) and SCTDR has become ready to be written with next serial transmit data. 0: Indicates that SCTDR holds valid transmit data [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and transmit data is transferred to SCTDR while the DISEL bit of MRB in the DTC is 0 1: Indicates that SCTDR does not hold valid transmit data [Setting conditions] Page 544 of 964 * By a power-on reset or in standby mode * When the TE bit in SCSCR is 0 * When data is transferred from SCTDR to SCTSR and data can be written to SCTDR R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W 6 RDRF 0 R/(W)* Receive Data Register Full Description Indicates that the received data is stored in the receive data register (SCRDR). 0: Indicates that valid received data is not stored in SCRDR [Clearing conditions] * By a power-on reset or in standby mode * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and data is transferred from SCRDR while the DISEL bit of MRB in the DTC is 0 1: Indicates that valid received data is stored in SCRDR [Setting condition] * When serial reception ends normally and receive data is transferred from SCRSR to SCRDR Note: SCRDR and the RDRF flag are not affected and retain their previous states even if an error is detected during data reception or if the RE bit in the serial control register (SCSCR) is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the received data will be lost. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 545 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W 5 ORER 0 R/(W)* Overrun Error Description Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Indicates that reception is in progress or was 1 completed successfully* [Clearing conditions] * By a power-on reset or in standby mode * When 0 is written to ORER after reading ORER = 1 1: Indicates that an overrun error occurred during 2 reception* [Setting condition] * When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR, and the data received subsequently is lost. Subsequent serial reception cannot be continued while the ORER flag is set to 1. Page 546 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W 4 FER 0 R/(W)* Framing Error Description Indicates that a framing error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was 1 completed successfully* [Clearing conditions] * By a power-on reset or in standby mode * When 0 is written to FER after reading FER = 1 1: Indicates that a framing error occurred during reception [Setting condition] * When the SCI founds that the stop bit at the end of the received data is 0 after completing 2 reception* Notes: 1. The FER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the FER flag is set to 1. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 547 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W 3 PER 0 R/(W)* Parity Error Description Indicates that a parity error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was 1 completed successfully* [Clearing conditions] * By a power-on reset or in standby mode * When 0 is written to PER after reading PER = 1 1: Indicates that a parity error occurred during 2 reception* [Setting condition] * When the number of 1s in the received data and parity does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. The PER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the PER flag is set to 1. Page 548 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value R/W Description 2 TEND 1 R Transmit End Indicates that no valid data was in SCTDR during transmission of the last bit of the transmit character and transmission has ended. The TEND flag is read-only and cannot be modified. 0: Indicates that transmission is in progress [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 1: Indicates that transmission has ended [Setting conditions] * By a power-on reset or in standby mode * When the TE bit in SCSCR is 0 * When TDRE = 1 during transmission of the last bit of a 1-byte serial transmit character Note: The TEND flag value becomes undefined if data is written to SCTDR by activating the DTC by a TXI interrupt. In this case, do not use the TEND flag as the transmit end flag. 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit found in the receive data. When the RE bit in SCSCR is cleared to 0, its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer Specifies the multiprocessor bit value to be added to the transmit frame. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 549 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.3.8 Serial Port Register (SCSPTR) SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the SCI function pins. Data to be output through the TXD pin can be specified to control break of serial transfer. Through bits 3 and 2, data reading and writing through the SCK pin can be specified. Bit 7 enables or disables RXI interrupts. The CPU can always read and write to SCSPTR. When reading the value on the SCI pins, use the respective port register. For details, refer to section 18, I/O Ports. Bit: 7 6 5 4 EIO - - - Initial value: 0 R/W: R/W 0 - 0 - 0 - 3 2 1 0 SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W R/W Bit Bit Name Initial value R/W Description 7 EIO 0 R/W Error Interrupt Only 0 R/W 1 R/W Enables or disables RXI interrupts. While the EIO bit is set to 1, the SCI does not request an RXI interrupt to the CPU even if the RIE bit is set to 1. 0: The RIE bit enables or disables RXI and ERI interrupts. While the RIE bit is 1, RXI and ERI interrupts are sent to the INTC. 1: While the RIE bit is 1, only the ERI interrupt is sent to the INTC. 6 to 4 All 0 Reserved These bits are always read as 0. The write value should always be 0. 3 SPB1IO 0 R/W Clock Port Input/Output in Serial Port Specifies the input/output direction of the SCK pin in the serial port. To output the data specified in the SPB1DT bit through the SCK pin as a port output pin, set the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0. 0: Does not output the SPB1DT bit value through the SCK pin. 1: Outputs the SPB1DT bit value through the SCK pin. Page 550 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Bit Bit Name Initial value 2 SPB1DT Undefined R/W R/W Description Clock Port Data in Serial Port Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin. 0: Low level is output 1: High level is output 1 SPB0IO 0 R/W Serial Port Break Output Together with the SPB0DT bit and the TE bit in SCSCR, controls the TXD pin. 0 SPB0DT 1 R/W Serial Port Break Data Together with the SPB0IO bit and TE bit in SCSCR, controls the TXD pin. Note that the TXD pin function needs to have been selected with the pin function controller (PFC). TE bit SPB0IO setting in bit SCSCR setting SPB0DT bit setting 0 0 * SPB0DT output disabled (initial state) 0 1 0 Output, low level 0 1 1 Output, high level 1 * * Output for transmit data in accord with the serial core logic State of TXD pin Note: * Don't care R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 551 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.3.9 Serial Direction Control Register (SCSDCR) The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. Bit: Initial value: R/W: Bit Bit Name 7 to 4 7 6 5 4 3 2 1 - - - - DIR - - - 1 R 1 R 1 R 1 R 0 R/W 0 R 1 R 0 R Initial Value R/W Description All 1 R Reserved 0 These bits are always read as 1. The write value should always be 1. 3 DIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: SCTDR contents are transmitted in LSB-first order Receive data is stored in SCRDR in LSB-first 1: SCTDR contents are transmitted in MSB-first order Receive data is stored in SCRDR in MSB-first 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 1 R Reserved This bit is always read as 1. The write value should always be 1. 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 552 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.3.10 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. The SCBRR setting is calculated as follows: Bit: 7 Initial value: 1 R/W: R/W 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W * Asynchronous mode: N= P x 106 - 1 64 x 22n-1 x B * Clock synchronous mode: N= P x 106 - 1 8 x 22n-1 x B B: N: Bit rate (bits/s) SCBRR setting for baud rate generator (0 N 255) (The setting value should satisfy the electrical characteristics.) P: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14.3.) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 553 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0 0 P 0 0 1 P/4 0 1 2 P/16 1 0 3 P/64 1 1 Note: The bit rate error in asynchronous is given by the following formula: Error (%) = P x 106 -1 (N + 1) x B x 64 x 22n-1 x 100 Tables 14.4 to 14.6 show examples of SCBRR settings in asynchronous mode, and tables 14.7 to 14.9 show examples of SCBRR settings in clock synchronous mode. Page 554 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) P (MHz) Bit Rate (bits/s) n N 10 12 Error (%) 14 Error n N (%) 16 Error n N (%) 18 Error n N 20 Error (%) n 0.03 3 79 N Error (%) n -0.12 3 88 -0.25 0.16 N (%) 110 2 177 -0.25 2 212 0.03 2 248 -0.17 3 70 150 2 129 0.16 2 155 0.16 2 181 0.16 2 207 0.16 2 233 0.16 3 64 300 2 64 2 77 2 90 0.16 2 103 0.16 2 116 0.16 2 129 0.16 600 1 129 0.16 1 155 0.16 1 181 0.16 1 207 0.16 1 233 0.16 2 64 1200 1 64 1 77 1 90 0.16 1 103 0.16 1 116 0.16 1 129 0.16 2400 0 129 0.16 0 181 0.16 0 207 0.16 0 233 0.16 1 64 0.16 0.16 0.16 0.16 0 155 0.16 0.16 0.16 4800 0 64 0.16 0 77 0.16 0 90 0.16 0 103 0.16 0 116 0.16 0 129 0.16 9600 0 32 -1.36 0 38 0.16 0 45 -0.93 0 51 0.16 0 58 -0.69 0 64 0.16 14400 0 21 -1.36 0 25 0.16 0 29 1.27 0 34 -0.79 0 38 0.16 0 42 0.94 19200 0 15 1.73 0 19 -2.34 0 22 -0.93 0 25 0.16 0 28 1.02 0 32 -1.36 28800 0 10 -1.36 0 12 0.16 0 14 1.27 0 16 2.12 0 19 -2.34 0 21 -1.36 31250 0 9 0.00 0 11 0.00 0 13 0.00 0 15 0.00 0 17 0.00 0 19 0.00 38400 0 7 1.73 0 9 -2.34 0 10 3.57 0 12 0.16 0 14 -2.34 0 15 1.73 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 555 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) P (MHz) Bit Rate (bits/s) n N 22 24 Error 26 Error (%) n N (%) 28 Error n N (%) 30 Error n N (%) 32 Error n N (%) Error n (%) N 110 3 97 -0.35 3 106 -0.44 3 114 0.36 3 123 0.23 3 132 0.13 3 141 0.03 150 3 71 -0.54 3 77 3 84 3 90 3 97 3 103 0.16 300 2 142 0.16 2 155 0.16 2 168 0.16 2 181 0.16 2 194 0.16 2 207 0.16 600 2 71 2 77 2 84 2 90 2 97 2 103 0.16 1200 1 142 0.16 1 155 0.16 1 168 0.16 1 181 0.16 1 194 0.16 1 207 0.16 2400 1 71 1 77 1 84 1 90 1 97 1 103 0.16 -0.54 -0.54 0.16 0.16 0.16 -0.43 -0.43 -0.43 0.16 0.16 0.16 -0.35 -0.35 -0.35 4800 0 142 0.16 0 155 0.16 0 168 0.16 0 181 0.16 0 194 0.16 0 207 0.16 9600 0 71 -0.54 0 77 0.16 0 84 -0.43 0 90 0.16 0 97 -0.35 0 103 0.16 14400 0 47 -0.54 0 51 0.16 0 55 0.76 0 60 -0.39 0 64 0.16 0 68 0.64 19200 0 35 -0.54 0 38 0.16 0 41 0.76 0 45 -0.93 0 48 -0.35 0 51 0.16 28800 0 23 -0.54 0 25 0.16 0 27 0.76 0 29 1.27 0 32 -1.36 0 34 -0.79 31250 0 21 0.00 0 23 0.00 0 25 0.00 0 27 0.00 0 29 0.00 0 31 0.00 38400 0 17 -0.54 0 19 -2.34 0 20 0.76 0 22 -0.93 0 23 1.73 0 25 0.16 Page 556 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) P (MHz) 34 36 38 40 Bit Rate (bits/s) n N (%) n N (%) n N (%) n N (%) 110 3 150 -0.05 3 159 -0.12 3 168 -0.19 3 177 -0.25 150 3 110 -0.29 3 116 0.16 3 123 -0.24 3 129 0.16 300 2 220 0.16 2 233 0.16 2 246 0.16 3 64 0.16 600 2 110 -0.29 2 116 0.16 2 123 -0.24 2 129 0.16 1200 1 220 0.16 1 233 0.16 1 246 0.16 2 64 0.16 2400 1 110 -0.29 1 116 0.16 1 123 -0.24 1 129 0.16 4800 0 220 0.16 0 233 0.16 0 246 0.16 1 64 0.16 9600 0 110 -0.29 0 116 0.16 0 123 -0.24 0 129 0.16 14400 0 73 -0.29 0 77 0.16 0 81 0.57 0 86 -0.22 19200 0 54 0.62 0 58 -0.69 0 61 -0.24 0 64 0.16 28800 0 36 -0.29 0 38 0.16 0 40 0.57 0 42 0.94 31250 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 38400 0 27 -1.18 0 28 1.02 0 30 -0.24 0 32 -1.36 Error R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Error Error Error Page 557 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) P (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N n N n N n N 250 3 155 3 187 3 218 3 249 500 3 77 3 93 3 108 3 124 1000 2 155 2 187 2 218 2 249 3 69 3 77 2500 1 249 2 74 2 87 2 99 2 112 2 124 5000 1 124 1 149 1 174 1 199 1 224 1 249 10000 0 249 1 74 1 87 1 99 1 112 1 124 25000 0 99 0 119 0 139 0 159 0 179 0 199 50000 0 49 0 59 0 69 0 79 0 89 0 99 100000 0 24 0 29 0 34 0 39 0 44 0 49 250000 0 9 0 11 0 13 0 15 0 17 0 19 n N n N 3 140 3 155 500000 0 4 0 5 0 6 0 7 0 8 0 9 1000000 0 2 0 3 0 4 2500000 0 0* 0 1 0 0* 5000000 Page 558 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) P (MHz) Bit Rate (bits/s) 22 24 26 28 30 32 n N n N n N n N n N n N 500 3 171 3 187 3 202 3 218 3 233 3 249 1000 3 85 3 93 3 101 3 108 3 116 3 124 2500 2 137 2 149 2 162 2 174 2 187 2 199 5000 2 68 2 74 2 80 2 87 2 93 2 99 10000 1 137 1 149 1 162 1 174 1 187 1 199 25000 0 219 0 239 1 64 1 69 1 74 1 79 50000 0 109 0 119 0 129 0 139 0 149 0 159 100000 0 54 0 59 0 64 0 69 0 74 0 79 250000 0 21 0 23 0 25 0 27 0 29 0 31 250 500000 0 10 0 11 0 12 0 13 0 14 0 15 1000000 0 5 0 6 0 7 2500000 0 2 5000000 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 559 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) P (MHz) Bit Rate (bits/s) 34 36 38 40 n N n N n N n N 1000 3 132 3 140 3 147 3 155 2500 2 212 2 224 2 237 2 249 5000 2 105 2 112 2 118 2 124 10000 1 212 1 224 1 237 1 249 25000 1 84 1 89 1 94 1 99 50000 0 169 0 179 0 189 0 199 100000 0 84 0 89 0 94 0 99 250000 0 33 0 35 0 37 0 39 250 500 500000 0 16 0 17 0 18 0 19 1000000 0 8 0 9 2500000 0 3 5000000 0 1 [Legend] Blank: No setting possible : Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended. Page 560 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 14.11 and 14.12 list the maximum rates for external clock input. Table 14.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) Maximum Bit Rate (bits/s) n N 10 312500 0 0 12 375000 0 0 14 437500 0 0 16 500000 0 0 18 562500 0 0 20 625000 0 0 22 687500 0 0 24 750000 0 0 26 812500 0 0 28 875000 0 0 30 937500 0 0 32 1000000 0 0 34 1062500 0 0 36 1125000 0 0 38 1187500 0 0 40 1250000 0 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 561 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000 Page 562 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 563 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.4 Operation 14.4.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous or clock synchronous mode is selected and the transmit format is specified in the serial mode register (SCSMR) as shown in table 14.13. The SCI clock source is selected by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in the serial control register (SCSCR) as shown in table 14.14. (1) Asynchronous Mode * Data length is selectable: 7 or 8 bits. * Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, overrun errors, and breaks. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the clock supplied by the onchip baud rate generator and can output a clock with a frequency 16 times the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clock Synchronous Mode * The transmission/reception format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Page 564 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Table 14.13 SCSMR Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 Bit 6 Bit 5 Bit 3 C/A CHR PE STOP Mode Data Length Parity Bit Stop Bit Length 0 8-bit Not set 1 bit 0 0 0 Asynchronous 1 1 2 bits 0 Set 1 1 0 2 bits 0 7-bit Not set 1 1 x 0 x x 1 bit 2 bits Set 1 1 1 bit 1 bit 2 bits Clock synchronous 8-bit Not set None [Legend] x: Don't care Table 14.14 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings Clock Source Bit 7 C/A Bit 1 CKE1 Bit 0 CKE0 Mode 0 0 0 Asynchronous Internal 1 1 0 0 0 1 1 0 SCI does not use the SCK pin. Clock with a frequency 16 times the bit rate is output. External Input a clock with frequency 16 times the bit rate. 1 1 SCK Pin Function Clock synchronous Internal Serial clock is output. External Input the serial clock. 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 565 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. 1 Serial data LSB 0 D0 Idle state (mark state) 1 MSB D1 D2 D3 D4 D5 Start bit Transmit/receive data 1 bit 7 or 8 bits D6 D7 0/1 1 1 Parity bit Stop bit 1 bit or none 1 or 2 bits One unit of transfer data (character or frame) Figure 14.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) Page 566 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group (1) Section 14 Serial Communication Interface (SCI) Transmit/Receive Formats Table 14.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR settings. Table 14.15 Serial Transfer Formats (Asynchronous Mode) Serial Transfer Format and Frame Length SCSMR Settings CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 x 1 0 S 8-bit data MPB STOP 0 x 1 1 S 8-bit data MPB STOP STOP 1 x 1 0 S 7-bit data MPB STOP 1 x 1 1 S 7-bit data MPB STOP STOP 2 3 4 5 6 7 8 9 10 11 12 STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit x: Don't care R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 567 of 964 Section 14 Serial Communication Interface (SCI) (2) SH7146 Group Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 14.14). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate. (3) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Page 568 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) [1] [2] Start initialization [3] Clear RIE, TIE, TEIE, MPIE, TE, and RE bits in SCSCR to 0* [4] Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) [1] Set data transfer format in SCSMR, SCSDCR [2] Set value in SCBRR [3] [5] Wait No 1-bit interval elapsed? Yes Set the PFC for the external pins to be used (SCK, TXD, RXD) [4] Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR [5] Set the clock selection in SCSCR. Set the data transfer format in SCSMR and SCSDCR. Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. Set the TE bit or RE bit in SCSCR to 1.* Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting, and RXD pin is in an idle state for waiting the start bit during receiving. < Initialization completed> Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 14.3 Sample Flowchart for SCI Initialization R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 569 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Transmitting Serial Data (Asynchronous Mode): Figure 14.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission [1] SCI status check and transmit data write: Read TDRE flag in SCSSR TDRE = 1? No [2] Serial transmission continuation procedure: Yes Write transmit data in SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? No Read TEND flag in SCSSR No Yes Break output? Yes To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. Yes TEND = 1? Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR, and clear the TDRE flag to 0. No [3] Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR to 0 End of transmission Figure 14.4 Sample Flowchart for Transmitting Serial Data Page 570 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. (A format in which neither parity nor multiprocessor bit is output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 571 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Figure 14.5 shows an example of the operation for transmission. Start bit 1 Serial data 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR and TDRE flag cleared to 0 by TXI interrupt handler TEI interrupt request One frame Figure 14.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Page 572 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Receiving Serial Data (Asynchronous Mode): Figure 14.6 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. [1] Receive error handling and break detection: Start of reception Read ORER, PER, and FER flags in SCSSR PER, FER, or ORER = 1? No Yes Error handling If a receive error occurs, read the ORER, PER, and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can also be detected by reading the value of the RXD pin. [2] SCI status check and receive data read: Read RDRF flag in SCSSR No RDRF = 1? Yes Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 No All data received? Read SCSSR and check that RDRF = 1, then read the receive data in SCRDR clear the RDRF flag to 0. [3] Serial reception continuation procedure: To continue serial reception, clear the RDRF flag to 0 before the stop bit for the current frame is received. The RDRF flag is cleared automatically when the data transfer controller (DTC) is activated to read the SCRDR value, and this step is not needed. Yes Clear RE bit in SCSCR to 0 End of reception Figure 14.6 Sample Flowchart for Receiving Serial Data (1) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 573 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 No PER = 1? Yes Parity error processing Clear ORER, PER, and FER flags in SCSSR to 0 <End> Figure 14.6 Sample Flowchart for Receiving Serial Data (2) Page 574 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. A. Parity check: The SCI counts the number of 1s in the received data and checks whether the count matches the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). B. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. C. Status check: The SCI checks whether the RDRF flag is 0 and the received data can be transferred from the receive shift register (SCRSR) to SCRDR. If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in SCRDR. If a receive error is detected, the SCI operates as shown in table 14.16 Note: When a receive error occurs, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0. 4. If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Table 14.16 Receive Errors and Error Conditions Receive Error Abbreviation Error Condition Data Transfer Overrun error ORER When the next data reception is completed while the RDRF flag in SCSSR is set to 1 The received data is not transferred from SCRSR to SCRDR. Framing error FER When the stop bit is 0 The received data is transferred from SCRSR to SCRDR. Parity error PER When the received data does not match the even or odd parity specified in SCSMR The received data is transferred from SCRSR to SCRDR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 575 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Figure 14.7 shows an example of the operation for reception. 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 0/1 RDRF FER RXI interrupt request One frame Data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 14.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit) 14.4.3 Clock Synchronous Mode In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.8 shows the general format in clock synchronous serial communication. One unit of transfer data (character or frame) * * Synchronization clock MSB LSB Bit 0 Serial data Bit 1 Bit 2 Don't care Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High level except in continuous transfer Figure 14.8 Data Format in Clock Synchronous Communication Page 576 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. (1) Communication Format The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source, see table 14.14. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only reception is performed, output of the synchronous clock continues until an overrun error occurs or the RE bit is cleared to 0. For the reception of n characters, select the external clock as the clock source. If the internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the same time as receiving the n characters of data. (3) Transmitting and Receiving Data SCI Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 577 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Figure 14.9 shows a sample flowchart for initializing the SCI. Start initialization Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCSCR to 0* Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) [1] Set data transfer format in SCSMR [2] Set value in SCBRR [3] Wait No 1-bit interval elapsed? [1] Set the clock selection in SCSCR. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. [4] Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. [5] Set the TE bit or RE bit in SCR to 1.* Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting. When synchronous clock output (clock master) is set during receiving in clock synchronous mode, outputting clocks from the SCK pin starts. Yes Set the PFC for the external pins to be used (SCK, TXD, RXD) Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR [4] [5] <Transfer starts> Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 14.9 Sample Flowchart for SCI Initialization Page 578 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Transmitting Serial Data (Clock Synchronous Mode): Figure 14.10 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission [1] SCI status check and transmit data write: Read TDRE flag in SCSSR TDRE = 1? No [2] Serial transmission continuation procedure: Yes Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted? No Yes Read TEND flag in SCSSR TEND = 1? Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR, and clear the TDRE flag to 0. To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. No Yes Clear TE bit in SCSCR to 0 End of transmission Figure 14.10 Sample Flowchart for Transmitting Serial Data R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 579 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the transmit-data-empty interrupt enable bit (TIE) in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is started, If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the MSB (bit 7) is sent, and then the TXD pin holds the states. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 14.11 shows an example of SCI transmit operation. Transfer direction Synchronization clock MSB LSB Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to SCTDR TXI interrupt request and TDRE flag cleared request to 0 by TXI interrupt handler TEI interrupt request One frame Figure 14.11 Example of SCI Transmit Operation Page 580 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Receiving Serial Data (Clock Synchronous Mode): Figure 14.12 shows a sample flowchart for receiving serial data. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching from asynchronous mode to clock synchronous mode, make sure that the ORER, PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not be set and data reception cannot be started. [1] Receive error handling: Start of reception Read ORER flag in SCSSR ORER = 1? No Read RDRF flag in SCSSR No Error handling [2] SCI status check and receive data read: Read SCSSR and check that RDRF = 1, then read the receive data in SCRDR, and clear the RDRF flag to 0. The transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: RDRF = 1? Yes Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 No Yes Read the ORER flag in SCSSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. All data received? To continue serial reception, read the receive data register (SCRDR) and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. The RDRF flag is cleared automatically when the data transfer controller (DTC) is activated by a receive-data-full interrupt (RXI) request to read the SCRDR value, and this step is not needed. Yes Clear RE bit in SCSCR to 0 End of reception Figure 14.12 Sample Flowchart for Receiving Serial Data (1) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 581 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR to 0 End Figure 14.12 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the received data in SCRDR. If a receive error is detected, the SCI operates as shown in table 14.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the RDRF flag to 0. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI). Page 582 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Figure 14.13 shows an example of SCI receive operation. Transfer direction Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt Data read from SCRDR and RXI interrupt request RDRF flag cleared to 0 by RXI request interrupt handler ERI interrupt request by overrun error One frame Figure 14.13 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure 14.14 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for serial data transmission and reception after enabling the SCI for transmission and reception. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 583 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Start of transmission and reception [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error processing: If a receive error occurs, read the ORER flag in SCSSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [3] SCI status check and receive data read: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading SCRDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to SCTDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to SCTDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the SCRDR value is read. Read TDRE flag in SCSSR No TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 Read ORER flag in SCSSR Yes ORER = 1? No Error processing Read RDRF flag in SCSSR No RDRF = 1? Yes Read receive data in SCRDR and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission and reception Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 14.14 Sample Flowchart for Transmitting/Receiving Serial Data Page 584 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.4.4 Section 14 Serial Communication Interface (SCI) Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 14.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCSCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from SCRSR to SCRDR, error flag detection, and setting the SCSSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SCSSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCSCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 585 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 14.4.5 Multiprocessor Serial Data Transmission Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. Maintain the MPBT value at 1 until the ID transmission actually completes. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Page 586 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) [1] Initialization [1] SCI initialization: Set the TXD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR. Set the MPBT bit in SCSSR to 0 or 1. Finally, clear the TDRE flag to 0. To transmit an ID after the SCI is initialized, write the ID to SCTDR. The data is immediately transferred to SCTSR and the TDRE flag is set to 1. At this point the ID has not yet been transmitted from the TXD pin, so it is necessary to maintain the MPBT value at 1. Clear the MPBT bit to 0 after the next data to be transmitted is written to SCTDR and the TDRE flag is set to 1. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR and use the PFC to select the TXD pin as an output port. Start transmission Set MPBT bit in SCSSR to 1 [2] Write transmit ID to SCTDR Clear TDRE flag in SCSR to 0 TDRE = 1? No Yes Clear MPBT in SCSSR to 0 [3] Write transmit data to SCTDR Clear TDRE flag to 0 TDRE = 1? No Yes No Transmit end? Yes Read TEND flag in SCSSR No TEND = 1? Yes No Break output? [4] Yes Clear DR to 0 Clear TE bit in SCSCR to 0; select the TXD pin as an output port with the PFC <End> Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 587 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.4.6 Multiprocessor Serial Data Reception Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 14.17 shows an example of SCI operation for multiprocessor format reception. 1 RXD Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDRF SCRDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated SCRDR data read If not this station's ID, and RDRF flag MPIE bit is set to 1 cleared to 0 in again RXI interrupt processing routine RXI interrupt request is not generated, and SCRDR retains its state (a) Data does not match station's ID 1 RXD Start bit 0 Data (ID2) D0 D1 Stop MPB bit D7 1 1 Start bit 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF SCRDR value ID1 MPIE = 0 Data2 ID2 RXI interrupt request (multiprocessor interrupt) generated SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Matches this station's ID, MPIE bit is set to 1 so reception continues, again and data is received in RXI interrupt processing routine (b) Data matches station's ID Figure 14.17 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Page 588 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Initialization [1] Start reception Set MPIE bit in SCSCR to 1 [2] [1] SCI initialization: Set the RXD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCSCR to 1. [3] SCI status check, ID reception and comparison: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SCSSR and check that the RDRF flag is set to 1, then read the data in SCRDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD pin value. Read ORER and FER flags in SCSSR Yes FER = 1? or ORER = 1? No Read RDRF flag in SCSSR [3] No RDRF = 1? Yes Read receive data in SCRDR No This station's ID? Yes Read ORER and FER flags in SCSSR Yes FER = 1? or ORER = 1? No Read RDRF flag in SCSSR [4] No RDRF = 1? Yes Read receive data in SCRDR No All data received? [5] Error processing Yes Clear RE bit in SCSCR to 0 (Continued on next page) <End> Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 589 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 Clear ORER and FER flags in SCSSR to 0 <End> Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2) Page 590 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.5 Section 14 Serial Communication Interface (SCI) SCI Interrupt Sources and DTC The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI) interrupt requests. Table 14.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt request is generated. This request can be used to activate the data transfer controller (DTC) to transfer data. The TDRE flag is automatically cleared to 0 when data is written to the transmit data register (SCTDR) through the DTC. When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. This request can be used to activate the DTC to transfer data. The RDRF flag is automatically cleared to 0 when data is read from the receive data register (SCRDR) through the DTC. When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated. This request cannot be used to activate the DTC. It is possible to disable generation of RXI interrupt requests and allow only ERI interrupt requests to be generated during data reception processing. To accomplish this, set the RIE bit to 1 and the EIO bit in SCSPTR to 1. Note that setting the EIO bit to 1 will prevent the DTC from transferring received data because no ERI interrupt requests are generated. When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. This request cannot be used to activate the DTC. The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that transmission has been completed. Table 14.17 SCI Interrupt Sources Interrupt Source Description DTC Activation ERI Interrupt caused by receive error (ORER, FER, or PER) Not possible RXI Interrupt caused by receive data full (RDRF) Possible TXI Interrupt caused by transmit data empty (TDRE) Possible TEI Interrupt caused by transmit end (TENT) Not possible R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 591 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.6 Serial Port Register (SCSPTR) and SCI Pins The relationship between SCSPTR and the SCI pins is shown in figures 14.19 and 14.20. Reset Bit 3 R Q D SCKIO C SPTRW Internal data bus Reset SCK R Bit 2 Q D SCKDT C SPTRW Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* [Legend] SPTRW: Note: SCSPTR write * These signals control the SCK pin according to the settings of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. Figure 14.19 SCKIO Bit, SCKDT Bit, and SCK Pin Page 592 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 14 Serial Communication Interface (SCI) Reset Bit 1 R Q D SPBIO C Internal data bus SPTRW Reset TXD R Bit 0 Q D SPBDT C SPTRW Transmit enable signal Serial transmit data [Legend] SPTRW: SCSPTR write Figure 14.20 SPBIO Bit, SPBDT Bit, and TXD Pin R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 593 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 14.7 Usage Notes 14.7.1 SCTDR Writing and TDRE Flag The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that the TDRE flag is set to 1. 14.7.2 Multiple Receive Error Occurrence If multiple receive errors occur at the same time, the status flags in SCSSR are set as shown in table 14.18. When an overrun error occurs, data is not transferred from the receive shift register (SCRSR) to the receive data register (SCRDR) and the received data will be lost. Table 14.18 SCSSR Status Flag Values and Transfer of Received Data Receive Errors Generated RDRF ORER FER PER Receive Data Transfer from SCRSR to SCRDR Overrun error 1 1 0 0 Not transferred Framing error 0 0 1 0 Transferred Parity error 0 0 0 1 Transferred Overrun error + framing error 1 1 1 0 Not transferred Overrun error + parity error 1 1 0 1 Not transferred Framing error + parity error 0 0 1 1 Transferred Overrun error + framing error + parity error 1 1 1 1 Not transferred SCSSR Status Flags Page 594 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.7.3 Section 14 Serial Communication Interface (SCI) Break Detection and Processing Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCRDR is halted in the break state, the SCI receiver continues to operate. 14.7.4 Sending a Break Signal The I/O condition and level of the TXD pin are determined by the SPB0IO and SPB0DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPB0DT bit. Therefore, the SPB0IO and SPB0DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin. 14.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 14.21. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 595 of 964 SH7146 Group Section 14 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RXD) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = (0.5 - D - 0.5 1 ) - (L - 0.5) F (1+F) x 100 % 2N N Where: M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Page 596 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 14.7.6 Section 14 Serial Communication Interface (SCI) Note on Using DTC When the external clock source is used for the clock for synchronization, input the external clock after waiting for five or more cycles of the peripheral operating clock after SCTDR is modified through the DTC. If a transmit clock is input within four cycles after SCTDR is modified, a malfunction may occur (figure 14.22). SCK t TDRE TXD D0 D1 D2 D3 D4 D5 D6 D7 Note: When using the external clock, t must be set to larger than 4 cycles. Figure 14.22 Example of Clock Synchronous Transfer Using DTC When data is written to SCTDR by activating the DTC by a TXI interrupt, the TEND flag value becomes undefined. In this case, do not use the TEND flag as the transmit end flag. 14.7.7 Note on Using External Clock in Clock Synchronous Mode TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock after the SCK external clock is changed from 0 to 1. TE and RE must be set to 1 only while the SCK external clock is 1. 14.7.8 Module Standby Mode Setting SCI operation can be disabled or enabled using the standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 22, Power-Down Modes. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 597 of 964 Section 14 Serial Communication Interface (SCI) Page 598 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) Section 15 A/D Converter (ADC) This LSI includes a successive approximation type 10-bit A/D converter. 15.1 Features * 10-bit resolution * Input channels 12 channels (three independent A/D conversion modules) * Conversion time: 2.0 s per channel (operation when P = 25 MHz) * Three operating modes Single mode: Single-channel A/D conversion Continuous scan mode: Repetitive A/D conversion on up to eight channels Single-cycle scan mode: Continuous A/D conversion on up to eight channels * Data registers Conversion results are held in a 16-bit data register for each channel * Sample-and-hold function * Three methods for conversion start Software Conversion start trigger from multifunction timer pulse unit 2 (MTU2) or multifunction timer pulse unit 2S (MTU2S) External trigger signal * Interrupt request An A/D conversion end interrupt request (ADI) can be generated * Module standby mode can be set R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 599 of 964 ADCMS20C_000020020700 SH7146 Group Section 15 A/D Converter (ADC) Figure 15.1 shows a block diagram of the A/D converter. Module data bus Bus interface ADCR ADTSR ADDRn * * * ADCSR AVSS ADDRm 10-bit D/A Successive approximations register AVCC Internal data bus P + ANm P/2 * * * * Multiplexer * Comparator Control circuit P/3 Sample-andhold circuit P/4 ADI interrupt signal Conversion start trigger from MTU2/MTU2S * ANn ADTRG [Legend] ADCR: ADCSR: ADTSR: ADDRm to ADDRn: A/D control register A/D control/status register A/D trigger select register A/D data registers m to n Note: The register number corresponds to the channel number of the module. (m to n = 0, 2, 4, 6, and 8 to 15) Figure 15.1 Block Diagram of A/D Converter (for One Module) Page 600 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 15.2 Section 15 A/D Converter (ADC) Input/Output Pins Table 15.1 summarizes the input pins used by the A/D converter. This LSI has three A/D conversion modules, each of which can be operated independently. The input channels of A/D modules 0 and 1 are divided into two channel groups. Table 15.1 Pin Configuration Module Type Pin Name I/O Function Common AVCC Input Analog block power supply and reference voltage AVSS Input Analog block ground and reference voltage ADTRG Input A/D external trigger input pin AN0 Input Analog input pin 0 (Group 0) AN2 Input Analog input pin 2 (Group 1) AN4 Input Analog input pin 4 (Group 0) AN6 Input Analog input pin 6 (Group 1) AN8 Input Analog input pin 8 AN9 Input Analog input pin 9 AN10 Input Analog input pin 10 AN11 Input Analog input pin 11 AN12 Input Analog input pin 12 AN13 Input Analog input pin 13 AN14 Input Analog input pin 14 AN15 Input Analog input pin 15 A/D module 0 (A/D_0) A/D module 1 (A/D_1) A/D module 2 (A/D_2) Note: The connected A/D module differs for each pin. The control registers of each module must be set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 601 of 964 SH7146 Group Section 15 A/D Converter (ADC) 15.3 Register Descriptions The A/D converter has the following registers. For details on register addresses and register states in each processing state, refer to section 23, List of Registers. Table 15.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size A/D data register 0 ADDR0 R H'0000 H'FFFFC900 16 A/D data register 2 ADDR2 R H'0000 H'FFFFC904 16 A/D control/status register_0 ADCSR_0 R/W H'0000 H'FFFFC910 16 A/D control register_0 ADCR_0 R/W H'0000 H'FFFFC912 16 A/D data register 4 ADDR4 R H'0000 H'FFFFC980 16 A/D data register 6 ADDR6 R H'0000 H'FFFFC984 16 A/D control/status register_1 ADCSR_1 R/W H'0000 H'FFFFC990 16 A/D control register_1 ADCR_1 R/W H'0000 H'FFFFC992 16 A/D data register 8 ADDR8 R H'0000 H'FFFFCA00 16 A/D data register 9 ADDR9 R H'0000 H'FFFFCA02 16 A/D data register 10 ADDR10 R H'0000 H'FFFFCA04 16 A/D data register 11 ADDR11 R H'0000 H'FFFFCA06 16 A/D data register 12 ADDR12 R H'0000 H'FFFFCA08 16 A/D data register 13 ADDR13 R H'0000 H'FFFFCA0A 16 A/D data register 14 ADDR14 R H'0000 H'FFFFCA0C 16 A/D data register 15 ADDR15 R H'0000 H'FFFFCA0E 16 A/D control/status register_2 ADCSR_2 R/W H'0000 H'FFFFCA10 16 A/D control register_2 ADCR_2 R/W H'0000 H'FFFFCA12 16 A/D trigger select register_0 ADTSR_0 R/W H'0000 H'FFFFE890 8, 16 A/D trigger select register_1 ADTSR_1 R/W H'0000 H'FFFFE892 8, 16 Page 602 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 15.3.1 Section 15 A/D Converter (ADC) A/D Data Registers 0, 2, 4, 6, and 8 to 15 (ADDR0, ADDR2, ADDR4, ADDR6, and ADDR8 to ADDR15) ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. For example, the conversion result of AN4 is stored in ADDR4. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The initial value of ADDR is H'0000. Bit: 15 Initial value: 0 R/W: R Bit 0 R Bit Name 15 to 6 5 to 0 14 13 0 R 12 0 R 11 10 0 R 0 R 9 0 R 8 0 R 7 0 R Initial Value R/W Description All 0 R Bit Data (10 bits) All 0 R 6 0 R 5 4 3 2 1 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 603 of 964 SH7146 Group Section 15 A/D Converter (ADC) 15.3.2 A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2) ADCSR for each module controls A/D conversion operations. Bit: 15 14 13 12 11 10 9 8 ADIE - - TRGE - CONADF STC Initial value: 0 0 R/W:R/(W)* R/W 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W ADF 7 6 CKSL[1:0] 0 R/W 0 R/W 5 4 ADM[1:0] 0 R/W 0 R/W 3 2 ADCS 0 R/W 1 0 CH[2:0] 0 R/W 0 R/W 0 R/W Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 15 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * When A/D conversion ends in single mode * When A/D conversion ends on all specified channels in scan mode [Clearing conditions] 14 ADIE 0 R/W * When 0 is written after reading ADF = 1 * When the DTC is activated by an ADI interrupt and ADDR is read A/D Interrupt Enable The A/D conversion end interrupt (ADI) request is enabled when 1 is set When changing the operating mode, first clear the ADST bit to 0. 13, 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 TRGE 0 R/W Trigger Enable Enables or disables triggering of A/D conversion by ADTRG, an MTU2 trigger, or an MTU2S trigger. 0: A/D conversion triggering is disabled 1: A/D conversion triggering is enabled When changing the operating mode, first clear the ADST bit to 0. Page 604 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) Bit Bit Name Initial Value R/W Description 10 0 R Reserved This bit is always read as 0. The write value should always be 0. 9 CONADF 0 R/W ADF Control Controls setting of the ADF bit in 2-channel scan mode. The setting of this bit is valid only when triggering of A/D conversion is enabled (TRGE = 1) in 2-channel scan mode. The setting of this bit is ignored in single mode, 4-channel scan mode, or 8-channel scan mode. 0: The ADF bit is set when A/D conversion started by the group 0 trigger or group 1 trigger has finished. 1: The ADF bit is set when A/D conversion started by the group 0 trigger and A/D conversion started by the group 1 trigger have both finished. Note that the triggering order has no affect. When changing the operating mode, first clear the ADST bit to 0. 8 STC 0 R/W State Control Sets the A/D conversion time in combination with the CKSL1 and CKSL0 bits. 0: 50 states 1: 64 states When changing the A/D conversion time, first clear the ADST bit to 0. 7, 6 CKSL[1:0] 00 R/W Clock Select 1 and 0 Select the A/D conversion time. 00: P/4 01: P/3 10: P/2 11: P When changing the A/D conversion time, first clear the ADST bit to 0. CKSL[1:0] = B'11 can be set while P 25 [MHz]. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 605 of 964 SH7146 Group Section 15 A/D Converter (ADC) Bit Bit Name Initial Value R/W Description 5, 4 ADM[1:0] 00 R/W A/D Mode 1 and 0 Select the A/D conversion mode. 2-channel scan mode is supported only by A/D modules 0 and 1. Do not select 2-channel scan mode in A/D module 2. 00: Single mode 01: 4-channel scan mode 10: 8-channel scan mode 11: 2-channel scan mode When changing the operating mode, first clear the ADST bit to 0. 3 ADCS 0 R/W A/D Continuous Scan Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. 0: Single-cycle scan 1: Continuous scan When changing the operating mode, first clear the ADST bit to 0. 2 to 0 CH[2:0] 000 R/W Channel Select 2 to 0 Select analog input channels. See table 15.3. When changing the operating mode, first clear the ADST bit to 0. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Page 606 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 15.3.3 Section 15 A/D Converter (ADC) A/D Control Registers_0 to _2 (ADCR_0 to ADCR_2) ADCR for each module controls A/D conversion. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - ADST - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15, 14 All 0 R Reserved 0 These bits are always read as 0. The write value should always be 0. 13 ADST 0 R/W A/D Start Starts or stops A/D conversion. When this bit is set to 1, A/D conversion is started. When this bit is cleared to 0, A/D conversion is stopped and the A/D converter enters the idle state. In single or single-cycle scan mode, this bit is automatically cleared to 0 when A/D conversion ends on the selected single channel. In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by software, reset, or in software standby mode or module standby mode. 12 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 607 of 964 SH7146 Group Section 15 A/D Converter (ADC) Table 15.3 Channel Select List * Single Mode Analog Input Channels Bit 2 Bit 1 Bit 0 Single Mode CH2 CH1 CH0 A/D_0 A/D_1 A/D_2 0 0 0 AN0 AN4 AN8 1 Setting prohibited Setting prohibited AN9 0 AN2 AN6 AN10 1 Setting prohibited Setting prohibited AN11 1 1 0 1 0 AN12 1 AN13 0 AN14 1 AN15 * 2-Channel Scan Mode Analog Input Channels Software Activation Other than Software Activation Bit 2 Bit 1 Bit 0 CH2 CH1 CH0 A/D_0 A/D_1 A/D_2 Group 0 Group 1 Group 0 Group 1 A/D_2 0 0 0 AN0 AN4 Setting AN0 AN2 AN4 AN6 Setting Setting Setting Setting Setting 1 1 1 0 A/D_0 Setting Setting prohibited prohibited 0 AN2 AN6 1 Setting Setting prohibited prohibited 0 prohibited A/D_1 prohibited prohibited prohibited prohibited prohibited 1 1 0 1 Note: When 2-, 4-, or 8-channel scan mode has been selected, the channels for operation are selected only by bits CH2 to CH0. For example, when 8-channel scan mode has been selected with continuous scan mode, continuous conversion will be performed on AN8 if bits CH2 to CH0 have been set to 000. Page 608 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) * 4-Channnel Scan Mode Analog Input Channels Bit 2 Bit 1 Bit 0 4-Channel Scan Mode* CH2 CH1 CH0 A/D_0 A/D_1 A/D_2 0 0 0 AN0 AN4 AN8 1 Setting prohibited Setting prohibited AN8, AN9 1 1 0 1 Note: * 0 AN8 to AN10 1 AN8 to AN11 0 AN12 1 AN12, AN13 0 AN12 to AN14 1 AN12 to AN15 Continuous scan mode or single-scan mode can be selected with the ADCS bit. When 2-, 4-, or 8-channel scan mode has been selected, the channels for operation are selected only by bits CH2 to CH0. For example, when 8-channel scan mode has been selected with continuous scan mode, continuous conversion will be performed on AN8 if bits CH2 to CH0 have been set to 000. * 8-Channel Scan Mode Analog Input Channels Bit 2 Bit 1 Bit 0 8-Channel Scan Mode* CH2 CH1 CH0 A/D_2 0 0 0 AN8 1 AN8, AN9 1 0 AN8 to AN10 1 AN8 to AN11 0 AN8 to AN12 1 AN8 to AN13 0 AN8 to AN14 1 AN8 to AN15 1 0 1 Note: * Continuous scan mode or single-scan mode can be selected with the ADCS bit. When 2-, 4-, or 8-channel scan mode has been selected, the channels for operation are selected only by bits CH2 to CH0. For example, when 8-channel scan mode has been selected with continuous scan mode, continuous conversion will be performed on AN8 if bits CH2 to CH0 have been set to 000. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 609 of 964 SH7146 Group Section 15 A/D Converter (ADC) 15.3.4 A/D Trigger Select Registers_0 and _1 (ADTSR_0 and ADTSR_1) The ADTSR enables an A/D conversion started by an external trigger signal. In particular, the two channels in A/D module 0 and A/D module 1 are divided into two groups (group 0 and group 1) and the A/D trigger can be specified for each group independently in 2channel scan mode. Page 610 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) * ADTSR_0 Bit: 15 14 13 12 11 10 TRG11S[3:0] Initial value: 0 R/W: R/W Bit 0 R/W 0 R/W Bit Name 9 8 7 TRG01S[3:0] 0 R/W Initial Value 15 to 12 TRG11S[3:0] 0000 0 R/W 0 R/W 0 R/W 6 5 4 3 TRG1S[3:0] 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0 TRG0S[3:0] 0 R/W 0 R/W R/W Description R/W A/D Trigger 1 Group 1 Select 3 to 0 0 R/W 0 R/W 0 R/W Select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for group 1 when A/D module 1 is in 2-channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TGRA input capture/compare match for each MTU2 channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0010: MTU2 CH0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: TGRA input capture/compare match on each MTU2S channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0110: Setting prohibited 0111: MTU2S A/D conversion start request delaying (TRG4AN) 1000: MTU2S A/D conversion start request delaying (TRG4BN) 1001: Setting prohibited 101x: Setting prohibited 11xx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 611 of 964 SH7146 Group Section 15 A/D Converter (ADC) Initial Value Bit Bit Name 11 to 8 TRG01S[3:0] 0000 R/W Description R/W A/D Trigger 0 Group 1 Select 3 to 0 Select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for group 1 when A/D module 0 is in 2-channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TGRA input capture/compare match for each MTU2 channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0010: MTU2 CH0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: TGRA input capture/compare match on each MTU2S channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0110: Setting prohibited 0111: MTU2S A/D conversion start request delaying (TRG4AN) 1000: MTU2S A/D conversion start request delaying (TRG4BN) 1001: Setting prohibited 101x: Setting prohibited 11xx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. Page 612 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) Bit Bit Name Initial Value R/W Description 7 to 4 TRG1S[3:0] 0000 R/W A/D Trigger 1 Select 3 to 0 Select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for A/D module 1. In 2channel scan mode, these bits select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for group 0. 0000: External trigger pin (ADTRG) input 0001: TGRA input capture/compare match for each MTU2 channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0010: MTU2 CH0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: TGRA input capture/compare match on each MTU2S channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0110: Setting prohibited 0111: MTU2S A/D conversion start request delaying (TRG4AN) 1000: MTU2S A/D conversion start request delaying (TRG4BN) 1001: Setting prohibited 101x: Setting prohibited 11xx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 613 of 964 SH7146 Group Section 15 A/D Converter (ADC) Bit Bit Name Initial Value R/W Description 3 to 0 TRG0S[3:0] 0000 R/W A/D Trigger 0 Select 3 to 0 Select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for A/D module 0. In 2channel scan mode, these bits select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for group 0. 0000: External trigger pin (ADTRG) input 0001: TGRA input capture/compare match for each MTU2 channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0010: MTU2 CH0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: TGRA input capture/compare match on each MTU2S channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0110: Setting prohibited 0111: MTU2S A/D conversion start request delaying (TRG4AN) 1000: MTU2S A/D conversion start request delaying (TRG4BN) 1001: Setting prohibited 101x: Setting prohibited 11xx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. [Legend] x: Don't care Page 614 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) * ADTSR_1 Bit: 15 14 13 12 TRG2S[3:0] Initial value: 0 R/W: R/W Bit 0 R/W 0 R/W Bit Name 15 to 12 TRG2S[3:0] 0 R/W 11 10 9 8 7 6 5 4 3 2 1 - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description 0000 R/W A/D Trigger 2 Select 3 to 0 0 Select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for A/D module 2. 0000: External trigger pin (ADTRG) input 0001: TGRA input capture/compare match for each MTU2 channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0010: MTU2 CH0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: TGRA input capture/compare match on each MTU2S channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0110: Setting prohibited 0111: MTU2S A/D conversion start request delaying (TRG4AN) 1000: MTU2S A/D conversion start request delaying (TRG4BN) 1001: Setting prohibited 101x: Setting prohibited 11xx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. 11 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. [Legend] x: Don't care R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 615 of 964 Section 15 A/D Converter (ADC) 15.4 SH7146 Group Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. 15.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU2, MTU2S, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D converion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. 15.4.2 Continuous Scan Mode In continuous scan mode, A/D conversion is to be performed sequentially on the specified channels (up to eight channels). 1. When the ADST bit in ADCR is set to 1 by software, MTU2, MTU2S, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN15). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. Page 616 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 15.4.3 Section 15 A/D Converter (ADC) Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (up to eight channels). 1. When the ADST bit in ADCR is set to 1 by a software, MTU2, MTU2S, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN15). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. 15.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCR is set to 1, then starts conversion. Figure 15.2 shows the A/D conversion timing. Table 15.4 shows the A/D conversion time. As indicated in figure 15.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion time. The values given in table 15.5 apply to the second and subsequent conversions. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 617 of 964 SH7146 Group Section 15 A/D Converter (ADC) A/D conversion time (tCONV) A/D conversion start Analog input delay time(tD) sampling time(tSPL) Write cycle A/D synchronization time (2 states) (Up to 6 states) P Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle state Sample-and-hold A/D conversion ADF End of A/D conversion Figure 15.2 A/D Conversion Timing Page 618 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) Table 15.4 A/D Conversion Time (Single Mode) STC = 0 CKSL1 = 0 CKSL0 = 0 CKSL1 = 1 CKSL0 = 1 CKSL0 = 0 Min. Typ. Max. Min. Typ. Max. CKSL0 = 1 Item Symbol Min. Typ. Max. A/D conversion start delay time tD 2 6 2 5 2 4 2 Min. Typ. Max. 3 Input sampling time tSPL 24 18 12 6 A/D conversion time tCONV 202 206 152 155 102 104 52 53 STC = 1 CKSL1 = 0 CKSL1 = 1 CKSL0 = 0 CKSL0 = 1 CKSL0 = 0 CKSL0 = 1 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Item Symbol Min. Typ. Max. A/D conversion start delay time tD 2 6 2 5 2 4 2 3 Input sampling time tSPL 36 27 18 9 A/D conversion time tCONV 258 262 194 197 130 132 66 67 Note: All values represent the number of states for P. Table 15.5 A/D Conversion Time (Scan Mode) Conversion Time Calculation Example STC CKSL1 CKSL0 Conversion Time (State) 0 0 0 200 (Fixed) 8 s 5 s 1 150 (Fixed) 6 s 3.8 s 0 100 (Fixed) 4 s 2.5 s 1 50 (Fixed) 2 s Setting prohibited 0 256 (Fixed) 10.2 s 6.4 s 1 192 (Fixed) 7.7 s 4.8 s 0 128 (Fixed) 5.1 s 3.2 s 1 64 (Fixed) 2.6 s Setting prohibited 1 1 0 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 P = 25 MHz P = 40 MHz Page 619 of 964 Section 15 A/D Converter (ADC) 15.4.5 SH7146 Group A/D Converter Activation by MTU2 or MTU2S The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU2 or MTU2S. To activate the A/D converter by the MTU2 or MTU2S, first set the TRGE bit in the A/D control/status register (ADCSR) to 1, and then set the A/D trigger select register (ADTSR). After this register setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D conversion request from the interval timer of the MTU2 or MTU2S occurs. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 15.4.6 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit in the A/D control/status register (ADCSR) is set to 1 while the A/D trigger select registers_0 and _1 (ADTSR_0 and ADTSR_1) are set to external trigger pin input, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 15.3 shows the timing. CK ADTRG External trigger signal ADST A/D conversion Figure 15.3 External Trigger Input Timing Page 620 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 15.4.7 Section 15 A/D Converter (ADC) 2-Channel Scanning In 2-channel scan mode, since the two channels of analog input are divided into groups 0 and 1, triggers for activation of groups 0 and 1 are independently specifiable. Conversion end interrupts in 2-channel scan mode can be generated either on completion of group 0 or group 1 or on completion of group 0 and group 1. If conversion is to be started by triggers, the different sources for groups 0 and 1 are specified in ADTSR. A request for conversion by group 1 generated during conversion by group 0 is ignored. Figure 15.4 shows an example of operation when TRG4AN of the MTU2 has been specified as the A/D conversion start request by group 0 and TRG4BN of the MTU2 has been specified as the A/D conversion start request by group 1. TGRA_3 TADCORA_4 TCNT_4 TADCORB_4 H'0000 A/D conversion start request AN0 conversion AN2 conversion A/D conversion end (ADF) CONADF bit in ADCSR = 0 CONADF bit in ADCSR = 1 Figure 15.4 Example of 2-Channel Scanning R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 621 of 964 SH7146 Group Section 15 A/D Converter (ADC) 15.5 Interrupt Sources and DTC Transfer Request The A/D converter can generate an A/D conversion end interrupt request (ADI). The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. The DTC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the CPU. When the DTC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically cleared when data is transferred by the DTC. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 15.6 A/D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag DTC Activation ADI0 A/D_0 conversion completed ADF in ADCSR_0 Possible ADI1 A/D_1 conversion completed ADF in ADCSR_1 Possible ADI2 A/D_2 conversion completed ADF in ADCSR_2 Possible Page 622 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 15.6 Section 15 A/D Converter (ADC) Definitions of A/D Conversion Accuracy This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.5). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.6). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.6). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error (see figure 15.6). * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 623 of 964 SH7146 Group Section 15 A/D Converter (ADC) Digital output 111 Ideal A/D conversion characteristic 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.5 Definitions of A/D Conversion Accuracy Page 624 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15.6 Definitions of A/D Conversion Accuracy R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 625 of 964 Section 15 A/D Converter (ADC) 15.7 Usage Notes 15.7.1 Module Standby Mode Setting SH7146 Group Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 22, Power-Down Modes. 15.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 15.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 15.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere in the accuracy by the printed circuit digital signals on the mounting board (i.e, acting as antennas). Page 626 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 15 A/D Converter (ADC) Sensor output impedance of up to 3 k or up to 1 k This LSI A/D converter equivalent circuit 10 k Sensor input Low-pass filter C to 0.1 F Cin = 20 pF 20 pF Figure 15.7 Example of Analog Input Circuit 15.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 15.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 627 of 964 SH7146 Group Section 15 A/D Converter (ADC) 15.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN15), between AVcc and AVss, as shown in figure 15.8. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. AVcc Rin *2 100 AN0 to AN15 *1 0.1 F Notes: AVss Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 15.8 Example of Analog Input Protection Circuit Table 15.7 Analog Pin Specifications Item Min. Max. Unit Condition Analog input capacitance 20 pF Permissible signal source impedance 3 k P 20 MHz 1 Page 628 of 964 P > 20 MHz R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 16 Compare Match Timer (CMT) Section 16 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals. 16.1 Features * Selection of four counter input clocks Any of four internal clocks (P/8, P/32, P/128, and P/512) can be selected independently for each channel. * Interrupt request on compare match * Module standby mode can be set. Figure 16.1 shows a block diagram of CMT. P/8 Control circuit P/32 P/512 P/128 Clock selection CMCNT_1 CMCNT_0 Comparator CMCOR_0 CMCSR_0 CMI1 CMCSR_1 Clock selection Control circuit CMSTR P/32 P/512 P/128 Comparator P/8 CMCOR_1 CMI0 Channel 0 Module bus Channel 1 Bus interface CMT [Legend] CMSTR: CMCSR: CMCOR: CMCNT: CMI: Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match counter Compare match interrupt Figure 16.1 Block Diagram of CMT R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 629 of 964 TIMCMT3A_000020030900 SH7146 Group Section 16 Compare Match Timer (CMT) 16.2 Register Descriptions The CMT has the following registers. For details on register addresses and register states during each processing, refer to section 23, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name. Table 16.1 Register Configuration Abbreviation R/W Initial Value Address Access Size Compare match timer start register CMSTR R/W H'0000 H'FFFFCE00 8, 16, 32 Compare match timer control/status register_1 CMCSR_0 R/W H'0000 H'FFFFCE02 8, 16 Compare match counter_0 CMCNT_0 R/W H'0000 H'FFFFCE04 8, 16, 32 Compare match constant register_0 CMCOR_0 R/W H'FFFF H'FFFFCE06 8, 16 Compare match timer control/status register_0 CMCSR_1 R/W H'0000 H'FFFFCE08 8, 16, 32 Compare match counter_1 CMCNT_1 R/W H'0000 H'FFFFCE0A 8, 16 Compare match constant register_1 CMCOR_1 R/W H'FFFF H'FFFFCE0C 8, 16, 32 Register Name Page 630 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 16.2.1 Section 16 Compare Match Timer (CMT) Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - STR1 STR0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 15 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Specifies whether compare match counter 1 operates or is stopped. 0: CMCNT_1 count is stopped 1: CMCNT_1 count is started 0 STR0 0 R/W Count Start 0 Specifies whether compare match counter 0 operates or is stopped. 0: CMCNT_0 count is stopped 1: CMCNT_0 count is started 16.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects the counter input clock. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - CMF CMIE - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 (R/W)*1 R/W 0 R 0 R 0 R 0 R 1 0 CKS[1:0] 0 R/W 0 R/W Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 631 of 964 SH7146 Group Section 16 Compare Match Timer (CMT) Bit Bit Name Initial value R/W 15 to 8 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 1 R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing conditions] * When 0 is written to this bit after reading CMF=1* 2 * When CMT registers are accessed when the value of the DISEL bit of MRB in the DTC is 0 after activating the DTC by CMI interrupts. [Setting condition] 1: CMCNT and CMCOR values match 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF=1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock (P). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS1 and CKS0. 00: P/8 01: P/32 10: P/128 11: P/512 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If the flag is set by another compare match before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it. Page 632 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 16.2.3 Section 16 Compare Match Timer (CMT) Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. The initial value of CMCNT is H'0000. Bit: 15 Initial value: 0 R/W: R/W 16.2.4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Compare Match Constant Register (CMCOR) CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. The initial value of CMCOR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 633 of 964 SH7146 Group Section 16 Compare Match Timer (CMT) 16.3 Operation 16.3.1 Interval Count Operation When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 16.2 shows the operation of the compare match counter. CMCNT value Counter cleared by compare match with CMCOR CMCOR H'0000 Time Figure 16.2 Counter Operation 16.3.2 CMCNT Count Timing One of four internal clocks (P/8, P/32, P/128, and P/512) obtained by dividing the P clock can be selected with bits CKS1 and CKS0 in CMCSR. Figure 16.3 shows the timing. Peripheral operating clock (P) Count clock CMCNT Nth clock (N + 1)th clock N N+1 Figure 16.3 Count Timing Page 634 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 16 Compare Match Timer (CMT) 16.4 Interrupts 16.4.1 CMT Interrupt Sources and DTC Activation The CMT has channels and each of them to which a different vector address is allocated has compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 6, Interrupt Controller (INTC). The data transfer controller (DTC) can be activated by an interrupt request. In this case, the priority between channels is fixed. See section 8, Data Transfer Controller (DTC), for details. Table 16.2 lists the CMT interrupt sources. Table 16.2 Interrupt Source Channel Interrupt Source Interrupt Enable Bit Interrupt Flag Bit DTC Activation Priority 0 CMI_0 CMIE CMF Possible High 1 CMI_1 CMIE CMF Possible Low 16.4.2 Timing of Setting Compare Match Flag When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 16.4 shows the timing of CMF bit setting. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 635 of 964 SH7146 Group Section 16 Compare Match Timer (CMT) Peripheral operating clock (P) Counter clock (N + 1)th clock CMCNT N CMCOR N 0 Compare match signal Figure 16.4 Timing of CMF Setting 16.4.3 Timing of Clearing Compare Match Flag The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0. Page 636 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 16 Compare Match Timer (CMT) 16.5 Usage Notes 16.5.1 Module Standby Mode Setting The CMT operation can be disabled or enabled using the standby control register. The initial setting is for CMT operation to be halted. Access to a register is enabled by clearing module standby mode. For details, refer to section 22, Power-Down Modes. 16.5.2 Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 16.5 shows the timing to clear the CMCNT counter. CMCSR write cycle T1 T2 Peripheral operating clock (P) Address CMCNT Internal write Counter clear CMCNT N H'0000 Figure 16.5 Conflict between Write and Compare-Match Processes of CMCNT R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 637 of 964 SH7146 Group Section 16 Compare Match Timer (CMT) 16.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 16.6 shows the timing to write to CMCNT in words. CMCSR write cycle T1 T2 Peripheral operating clock (P) Address CMCNT Internal write CMCNT count-up enable CMCNT N M (CMCNT write data) Figure 16.6 Conflict between Word-Write and Count-Up Processes of CMCNT Page 638 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 16.5.4 Section 16 Compare Match Timer (CMT) Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing has priority over the count-up. In this case, the count-up is not performed. The byte data on another side, which is not written to, is also not counted and the previous contents remain. Figure 16.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT in bytes. CMCSR write cycle T1 T2 Peripheral operating clock (P) CMCNTH Address Internal write CMCNT count-up enable CMCNTH N CMCNTL X M (CMCNT write data) X Figure 16.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 16.5.5 Compare Match between CMCNT and CMCOR Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. If set, the CMF bit in CMCSR is set to 1 and CMCNT is cleared to H'0000. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 639 of 964 Section 16 Compare Match Timer (CMT) Page 640 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Section 17 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 17.1 to 17.8 list the multiplexed pins of this LSI. Tables 17.9 to 17.11 list the pin functions in each operating mode. Table 17.1 SH7146 Multiplexed Pins (Port A) Port A Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) PA0 I/O (port) POE0 input (POE) RXD0 input (SCI) PA1 I/O (port) POE1 input (POE) TXD0 output (SCI) PA2 I/O (port) IRQ0 input (INTC) POE2 input (POE) SCK0 I/O (SCI) PA3 I/O (port) IRQ1 input (INTC) RXD1 input (SCI) PA4 I/O (port) IRQ2 input (INTC) TXD1 output (SCI) PA5 I/O (port) IRQ3 input (INTC) SCK1 I/O (SCI) PA6 I/O (port) UBCTRG output (UBC) TCLKA input (MTU2) POE4 input (POE) PA7 I/O (port) TCLKB input (MTU2) POE5 input (POE) SCK2 I/O (SCI) PA8 I/O (port) TCLKC input (MTU2) POE6 input (POE) RXD2 input (SCI) PA9 I/O (port) TCLKD input (MTU2) POE8 input (POE) TXD2 output (SCI) PA10 I/O (port) RXD0 input (SCI) PA11 I/O (port) TXD0 output (SCI) ADTRG input (A/D) PA12 I/O (port) SCK0 I/O (SCI) PA13 I/O (port) SCK1 I/O (SCI) PA14 I/O (port) RXD1 input (SCI) PA15 I/O (port) TXD1 output (SCI) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 641 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.2 SH7149 Multiplexed Pins (Port A) Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) Function 5 (Related Module) A PA0 I/O (port) A0 output (BSC) POE0 input (POE) RXD0 input (SCI) PA1 I/O (port) A1 output (BSC) POE1 input (POE) TXD0 output (SCI) PA2 I/O (port) A2 output (BSC) IRQ0 input (INTC) POE2 input (POE) SCK0 I/O (SCI) PA3 I/O (port) A3 output (BSC) IRQ1 input (INTC) RXD1 input (SCI) PA4 I/O (port) A4 output (BSC) IRQ2 input (INTC) TXD1 output (SCI) PA5 I/O (port) A5 output (BSC) IRQ3 input (INTC) SCK1 I/O (SCI) PA6 I/O (port) RD output (BSC) UBCTRG output (UBC) TCLKA input (MTU2) POE4 input (POE) PA7 I/O (port) WRH output (BSC) TCLKB input (MTU2) POE5 input (POE) SCK2 I/O (SCI) PA8 I/O (port) WRL output (BSC) TCLKC input (MTU2) POE6 input (POE) RXD2 input (SCI) PA9 I/O (port) WAIT input (BSC) TCLKD input (MTU2) POE8 input (POE) TXD2 output (SCI) PA10 I/O (port) A6 output (BSC) RXD0 input (SCI) PA11 I/O (port) A7 output (BSC) TXD0 output (SCI) ADTRG input (A/D) PA12 I/O (port) A8 output (BSC) SCK0 I/O (SCI) PA13 I/O (port) A9 output (BSC) SCK1 I/O (SCI) PA14 I/O (port) A10 output (BSC) RXD1 input (SCI) PA15 I/O (port) CK output (CPG) TXD1 output (SCI) Table 17.3 SH7146 Multiplexed Pins (Port B) Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) B PB2 I/O (port) IRQ0 input (INTC) POE0 input (POE) TIC5VS input (MTU2S) PB3 I/O (port) IRQ1 input (INTC) POE1 input (POE) TIC5V input (MTU2) PB4 I/O (port) IRQ2 input (INTC) POE4 input (POE) TIC5US input (MTU2S) PB5 I/O (port) IRQ3 input (INTC) POE5 input (POE) TIC5U input (MTU2) PB16 I/O (port) POE3 input (POE) PB17 I/O (port) POE7 input (POE) PB18 I/O (port) POE8 input (POE) Page 642 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.4 SH7149 Multiplexed Pins (Port B) Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 Function 5 (Related Module) (Related Module) B PB0 I/O (port) BACK output (BSC) TIC5WS input (MTU2S) PB1 I/O (port) BREQ input (BSC) TIC5W input (MTU2) PB2 I/O (port) A16 output (BSC) IRQ0 input (INTC) POE0 input (POE) TIC5VS input (MTU2S) PB3 I/O (port) A17 output (BSC) IRQ1 input (INTC) POE1 input (POE) TIC5V input (MTU2) PB4 I/O (port) A18 output (BSC) IRQ2 input (INTC) POE4 input (POE) TIC5US input (MTU2S) PB5 I/O (port) A19 output (BSC) IRQ3 input (INTC) POE5 input (POE) TIC5U input (MTU2) PB16 I/O (port) POE3 input (POE) PB17 I/O (port) POE7 input (POE) PB18 I/O (port) POE8 input (POE) Table 17.5 SH7149 Multiplexed Pins (Port D) Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) D PD0 I/O (port) D0 I/O (BSC) RXD0 input (SCI) PD1 I/O (port) D1 I/O (BSC) TXD0 output (SCI) PD2 I/O (port) D2 I/O (BSC) SCK0 I/O (SCI) PD3 I/O (port) D3 I/O (BSC) RXD1 input (SCI) PD4 I/O (port) D4 I/O (BSC) IRQ0 input (INTC) TXD1 output (SCI) PD5 I/O (port) D5 I/O (BSC) IRQ1 input (INTC) SCK1 I/O (SCI) PD6 I/O (port) D6 I/O (BSC) IRQ2 input (INTC) RXD2 input (SCI) PD7 I/O (port) D7 I/O (BSC) IRQ3 input (INTC) TXD2 output (SCI) PD8 I/O (port) D8 I/O (BSC) SCK2 I/O (SCI) AUDATA0 output (AUD)* PD9 I/O (port) D9 I/O (BSC) AUDATA1 output (AUD)* PD10 I/O (port) D10 I/O (BSC) AUDATA2 output (AUD)* PD11 I/O (port) D11 I/O (BSC) AUDATA3 output (AUD)* PD12 I/O (port) D12 I/O (BSC) PD13 I/O (port) D13 I/O (BSC) PD14 I/O (port) D14 I/O (BSC) AUDCK output (AUD)* PD15 I/O (port) D15 I/O (BSC) AUDSYNC output (AUD)* Note: * Only in F-ZTAT version supporting full functions of E10A. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 643 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.6 SH7146 Multiplexed Pins (Port E) Function 1 Function 2 Function 3 Function 4 Port (Related Module) (Related Module) (Related Module) (Related Module) E PE0 I/O (port) TIOC0A I/O (MTU2) PE1 I/O (port) TIOC0B I/O (MTU2) RXD0 input (SCI) Note: PE2 I/O (port) TIOC0C I/O (MTU2) TXD0 output (SCI) PE3 I/O (port) TIOC0D I/O (MTU2) SCK0 I/O (SCI) PE4 I/O (port) TIOC1A I/O (MTU2) RXD1 input (SCI) PE5 I/O (port) TIOC1B I/O (MTU2) TXD1 output (SCI) PE6 I/O (port) TIOC2A I/O (MTU2) SCK1 I/O (SCI) PE7 I/O (port) TIOC2B I/O (MTU2) PE8 I/O (port) TIOC3A I/O (MTU2) PE9 I/O (port) TIOC3B I/O (MTU2) PE10 I/O (port) TIOC3C I/O (MTU2) PE11 I/O (port) TIOC3D I/O (MTU2) PE12 I/O (port) TIOC4A I/O (MTU2) PE13 I/O (port) TIOC4B I/O (MTU2) MRES input (INTC) PE14 I/O (port) TIOC4C I/O (MTU2) PE15 I/O (port) TIOC4D I/O (MTU2) IRQOUT output (INTC) PE16 I/O (port) TIOC3BS I/O (MTU2S) ASEBRKAK output (E10A)* ASEBRK input (E10A)* PE17 I/O (port) TIOC3DS I/O (MTU2S) TCK input (H-UDI)* PE18 I/O (port) TIOC4AS I/O (MTU2S) TDI input (H-UDI)* PE19 I/O (port) TIOC4BS I/O (MTU2S) TDO output (H-UDI)* PE20 I/O (port) TIOC4CS I/O (MTU2S) TMS input (H-UDI)* PE21 I/O (port) TIOC4DS I/O (MTU2S) TRST input (H-UDI)* * F-ZTAT version only. Page 644 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.7 SH7149 Multiplexed Pins (Port E) Function 1 Function 2 Function 3 Function 4 Function 5 Port (Related Module) (Related Module) (Related Module) (Related Module) (Related Module) E PE0 I/O (port) TIOC0A I/O (MTU2) PE1 I/O (port) TIOC0B I/O (MTU2) RXD0 input (SCI) PE2 I/O (port) TIOC0C I/O (MTU2) TXD0 output (SCI) PE3 I/O (port) TIOC0D I/O (MTU2) SCK0 I/O (SCI) PE4 I/O (port) A11 output (BSC) TIOC1A I/O (MTU2) RXD1 input (SCI) PE5 I/O (port) A12 output (BSC) TIOC1B I/O (MTU2) TXD1 output (SCI) PE6 I/O (port) A13 output (BSC) TIOC2A I/O (MTU2) SCK1 I/O (SCI) PE7 I/O (port) A14 output (BSC) TIOC2B I/O (MTU2) PE8 I/O (port) A15 output (BSC) TIOC3A I/O (MTU2) PE9 I/O (port) TIOC3B I/O (MTU2) PE10 I/O (port) CS0 output (BSC) TIOC3C I/O (MTU2) PE11 I/O (port) TIOC3D I/O (MTU2) PE12 I/O (port) TIOC4A I/O (MTU2) PE13 I/O (port) TIOC4B I/O (MTU2) MRES input (INTC) PE14 I/O (port) TIOC4C I/O (MTU2) PE15 I/O (port) TIOC4D I/O (MTU2) IRQOUT output (INTC) PE16 I/O (port) WAIT input (BSC) TIOC3BS I/O (MTU2S) ASEBRKAK output ASEBRK input (E10A)* (E10A)* Note: PE17 I/O (port) CS0 output (BSC) TIOC3DS I/O (MTU2S) TCK input (H-UDI)* PE18 I/O (port) CS1 output (BSC) TIOC4AS I/O (MTU2S) TDI input (H-UDI)* PE19 I/O (port) RD output (BSC) TIOC4BS I/O (MTU2S) TDO output (H-UDI)* PE20 I/O (port) WRH output (BSC) TIOC4CS I/O (MTU2S) TMS input (H-UDI)* PE21 I/O (port) WRL output (BSC) TIOC4DS I/O (MTU2S) TRST input (H-UDI)* * F-ZTAT version only. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 645 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.8 Multiplexed Pins (Port F) Port Function 1 (Related Module) Function 2 (Related Module) F PF0 input (port) AN0 input (A/D) PF2 input (port) AN2 input (A/D) PF4 input (port) AN4 input (A/D) PF6 input (port) AN6 input (A/D) PF8 input (port) AN8 input (A/D) PF9 input (port) AN9 input (A/D) PF10 input (port) AN10 input (A/D) PF11 input (port) AN11 input (A/D) PF12input (port) AN12 input (A/D) PF13 input (port) AN13 input (A/D) PF14 input (port) AN14 input (A/D) PF15 input (port) AN15 input (A/D) Note: During A/D conversion, the AN input function is enabled. Page 646 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.9 SH7146 Pin Functions in Each Operating Mode Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities 4, 19, 31, 48 Vcc Vcc 6, 17, 33, 46 Vss Vss 10, 50 VCL VCL 72, 78 AVcc AVcc 63, 75 AVss AVss 60 PLLVss PLLVss 55 EXTAL EXTAL 54 XTAL XTAL 59 MD1 MD1 1 FWE*1 58 FWE* 52 RES RES 53 WDTOVF WDTOVF 57 NMI 56 ASEMD0* ASEMD0*1 47 PA0 PA0/POE0/RXD0 45 PA1 PA1/POE1/TXD0 44 PA2 PA2/IRQ0/POE2/SCK0 43 PA3 PA3/IRQ1/RXD1 42 PA4 PA4/IRQ2/TXD1 41 PA5 PA5/IRQ3/SCK1 40 PA6 PA6/UBCTRG/TCLKA/POE4 39 PA7 PA7/TCLKB/POE5/SCK2 38 PA8 PA8/TCLKC/POE6/RXD2 37 PA9 PA9/TCLKD/POE8/TXD2 36 PA10 PA10/RXD0 35 PA11 PA11/TXD0/ADTRG 34 PA12 PA12/SCK0 32 PA13 PA13/SCK1 NMI 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 647 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities 30 PA14 PA14/RXD1 29 PA15 PA15/TXD1 62 PB2 PB2/IRQ0/POE0/TIC5VS 61 PB3 PB3/IRQ1/POE1/TIC5V 51 PB4 PB4/IRQ2/POE4/TIC5US 49 PB5 PB5/IRQ3/POE5/TIC5U 79 POE3 PB16/POE3 80 POE7 PB17/POE7 28 POE8 PB18/POE8 27 PE0 PE0/TIOC0A 26 PE1 PE1/TIOC0B/RXD0 25 PE2 PE2/TIOC0C/TXD0 24 PE3 PE3/TIOC0D/SCK0 23 PE4 PE4/TIOC1A/RXD1 22 PE5 PE5/TIOC1B/TXD1 21 PE6 PE6/TIOC2A/SCK1 20 PE7 PE7/TIOC2B 18 PE8 PE8/TIOC3A 15 PE9 PE9/TIOC3B 16 PE10 PE10/TIOC3C 14 PE11 PE11/TIOC3D 13 PE12 PE12/TIOC4A 12 PE13 PE13/TIOC4B/MRES 11 PE14 PE14/TIOC4C 9 PE15 PE15/TIOC4D/IRQOUT 8 PE16/(ASEBRKAK PE16/TIOC3BS 2 /ASEBRK* ) 7 5 3 Page 648 of 964 PE17/(TCK*2) 2 PE18/(TDI* ) 2 PE19/(TDO* ) PE17/TIOC3DS PE18/TIOC4AS PE19/TIOC4BS R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function 2 PFC Selected Function Possibilities 2 PE20/(TMS* ) 1 PE21/(TRST* ) PE21/TIOC4DS 77 PF0/AN0 PF0/AN0 76 PF2/AN2 PF2/AN2 74 PF4/AN4 PF4/AN4 73 PF6/AN6 PF6/AN6 71 PF8/AN8 PF8/AN8 70 PF9/AN9 PF9/AN9 2 PE20/TIOC4CS 69 PF10/AN10 PF10/AN10 68 PF11/AN11 PF11/AN11 67 PF12/AN12 PF12/AN12 66 PF13/AN13 PF13/AN13 65 PF14/AN14 PF14/AN14 64 PF15/AN15 PF15/AN15 Notes: 1. F-ZTAT version only. 2. F-ZTAT version only. Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 649 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.10 SH7149 Pin Functions in Each Operating Mode (1) Pin Name On-Chip ROM Disabled (MCU Mode 0) On-Chip ROM Disabled (MCU Mode 1) Pin No. PFC Selected Function Initial Function Possibilities Initial Function PFC Selected Function Possibilities 5, 24, 39, Vcc Vcc Vcc Vcc 7, 22, 41, 57 Vss Vss Vss Vss 12, 61 VCL VCL VCL VCL 90, 96 AVcc AVcc AVcc AVcc 59, 73 81, 93 AVss AVss AVss AVss 75 PLLVss PLLVss PLLVss PLLVss 67 EXTAL EXTAL EXTAL EXTAL 66 XTAL XTAL XTAL XTAL 72 MD0 MD0 MD0 MD0 71 MD1 70 FWE* 64 MD1 1 MD1 1 MD1 1 FWE*1 FWE* FWE* RES RES RES RES 65 WDTOVF WDTOVF WDTOVF WDTOVF 69 NMI NMI NMI 68 ASEMD0* ASEMD0* ASEMD0* 63 A0 PA0/A0/POE0/RXD0 A0 PA0/A0/POE0/RXD0 62 A1 PA1/A1/POE1/TXD0 A1 PA1/A1/POE1/TXD0 60 A2 PA2/A2/IRQ0/POE2/SCK0 A2 PA2/A2/IRQ0/POE2/SCK0 58 A3 PA3/A3/IRQ1/RXD1 A3 PA3/A3/IRQ1/RXD1 56 A4 PA4/A4/IRQ2/TXD1 A4 PA4/A4/IRQ2/TXD1 1 1 NMI 1 ASEMD0*1 55 A5 PA5/A5/IRQ3/SCK1 A5 PA5/A5/IRQ3/SCK1 54 RD PA6/RD/UBCTRG/TCLKA RD PA6/RD/UBCTRG/TCLKA /POE4 /POE4 53 PA7 PA7/WRH/TCLKB/POE5/SCK2 WRH PA7/WRH/TCLKB/POE5/SCK2 52 WRL PA8/WRL/TCLKC/POE6/RXD2 WRL PA8/WRL/TCLKC/POE6/RXD2 51 PA9 PA9/WAIT/TCLKD/POE8/TXD2 PA9 PA9/WAIT/TCLKD/POE8/TXD2 50 A6 PA10/A6/RXD0 A6 PA10/A6/RXD0 Page 650 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name On-Chip ROM Disabled (MCU Mode 0) On-Chip ROM Disabled (MCU Mode 1) Pin No. Initial Function PFC Selected Function Possibilities PFC Selected Function Initial Function Possibilities 49 A7 PA11/A7/TXD0/ADTRG A7 PA11/A7/TXD0/ADTRG 48 A8 PA12/A8/SCK0 A8 PA12/A8/SCK0 47 A9 PA13/A9/SCK1 A9 PA13/A9/SCK1 46 A10 PA14/A10/RXD1 A10 PA14/A10/RXD1 45 CK PA15/CK/TXD1 CK PA15/CK/TXD1 80 PB0 PB0/BACK/TIC5WS PB0 PB0/BACK/TIC5WS 79 PB1 PB1/BREQ/TIC5W PB1 PB1/BREQ/TIC5W 78 A16 PB2/A16/IRQ0/POE0/TIC5VS A16 PB2/A16/IRQ0/POE0/TIC5VS 77 A17 PB3/A17/IRQ1/POE1/TIC5V A17 PB3/A17/IRQ1/POE1/TIC5V 76 PB4 PB4/A18/IRQ2/POE4/TIC5US PB4 PB4/A18/IRQ2/POE4/TIC5US 74 PB5 PB5/A19/IRQ3/POE5/TIC5U PB5 PB5/A19/IRQ3/POE5/TIC5U 97 POE3 PB16/POE3 POE3 PB16/POE3 98 POE7 PB17/POE7 POE7 PB17/POE7 26 POE8 PB18/POE8 POE8 PB18/POE8 44 D0 PD0/D0/RXD0 D0 PD0/D0/RXD0 43 D1 PD1/D1/TXD0 D1 PD1/D1/TXD0 42 D2 PD2/D2/SCK0 D2 PD2/D2/SCK0 40 D3 PD3/D3/RXD1 D3 PD3/D3/RXD1 38 D4 PD4/D4/IRQ0/TXD1 D4 PD4/D4/IRQ0/TXD1 37 D5 PD5/D5/IRQ1/SCK1 D5 PD5/D5/IRQ1/SCK1 36 D6 PD6/D6/IRQ2/RXD2 D6 PD6/D6/IRQ2/RXD2 35 D7 PD7/D7/IRQ3/TXD2 D7 PD7/D7/IRQ3/TXD2 34 PD8/(AUDATA0* ) PD8/D8/SCK2 D8/(AUDATA0* ) 33 32 3 3 PD9/(AUDATA1* ) PD10 PD9/D9 3 3 D9/(AUDATA1* ) 3 PD8/D8/SCK2 PD9/D9 PD10/D10 D10/(AUDATA2* ) PD10/D10 PD11/D11 D11/(AUDATA3*3) PD11/D11 3 /(AUDATA2* ) 31 PD11 3 /(AUDATA3* ) 30 PD12 PD12/D12 D12 PD12/D12 29 PD13 PD13/D13 D13 PD13/D13 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 651 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name On-Chip ROM Disabled (MCU Mode 0) On-Chip ROM Disabled (MCU Mode 1) PFC Selected Function Possibilities PFC Selected Function Initial Function Possibilities PD14/D14 D14/(AUDCK* ) Pin No. Initial Function 28 PD14/(AUDCK* ) 27 3 PD15/D15 PD15 3 PD14/D14 3 D15/(AUDSYNC* ) PD15/D15 3 /(AUDSYNC* ) 25 PE0 PE0/TIOC0A PE0 PE0/TIOC0A 23 PE1 PE1/TIOC0B/RXD0 PE1 PE1/TIOC0B/RXD0 21 PE2 PE2/TIOC0C/TXD0 PE2 PE2/TIOC0C/TXD0 20 PE3 PE3/TIOC0D/SCK0 PE3 PE3/TIOC0D/SCK0 19 A11 PE4/A11/TIOC1A/RXD1 A11 PE4/A11/TIOC1A/RXD1 18 A12 PE5/A12/TIOC1B/TXD1 A12 PE5/A12/TIOC1B/TXD1 17 A13 PE6/A13/TIOC2A/SCK1 A13 PE6/A13/TIOC2A/SCK1 16 A14 PE7/A14/TIOC2B A14 PE7/A14/TIOC2B 15 A15 PE8/A15/TIOC3A A15 PE8/A15/TIOC3A 13 PE9 PE9/TIOC3B PE9 PE9/TIOC3B 14 CS0 PE10/CS0/TIOC3C CS0 PE10/CS0/TIOC3C 11 PE11 PE11/TIOC3D PE11 PE11/TIOC3D 10 PE12 PE12/TIOC4A PE12 PE12/TIOC4A 9 PE13 PE13/TIOC4B/MRES PE13 PE13/TIOC4B/MRES 8 PE14 PE14/TIOC4C PE14 PE14/TIOC4C 6 PE15 PE15/TIOC4D/IRQOUT PE15 PE15/TIOC4D/IRQOUT 4 PE16/(ASEBRKAK PE16/WAIT/TIOC3BS 2 3 2 1 100 PE16/(ASEBRKAK PE16/WAIT/TIOC3BS /ASEBRK*2) /ASEBRK* ) PE17/(TCK*2) 2 PE18/(TDI* ) PE17/CS0/TIOC3DS PE18/CS1/TIOC4AS 2 PE19/(TDO* ) 2 PE20/(TMS* ) 2 PE19/RD/TIOC4BS PE20/WRH/TIOC4CS PE17/(TCK*2) 2 PE18/(TDI* ) PE17/CS0/TIOC3DS PE18/CS1/TIOC4AS 2 PE19/(TDO* ) 2 PE20/(TMS* ) 2 PE19/RD/TIOC4BS PE20/WRH/TIOC4CS 99 PE21/(TRST* ) PE21/WRL/TIOC4DS PE21/(TRST* ) PE21/WRL/TIOC4DS 95 PF0/AN0 PF0/AN0 PF0/AN0 PF0/AN0 94 PF2/AN2 PF2/AN2 PF2/AN2 PF2/AN2 92 PF4/AN4 PF4/AN4 PF4/AN4 PF4/AN4 91 PF6/AN6 PF6/AN6 PF6/AN6 PF6/AN6 Page 652 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name On-Chip ROM Disabled (MCU Mode 0) On-Chip ROM Disabled (MCU Mode 1) Pin No. Initial Function PFC Selected Function Possibilities PFC Selected Function Initial Function Possibilities 89 PF8/AN8 PF8/AN8 PF8/AN8 PF8/AN8 88 PF9/AN9 PF9/AN9 PF9/AN9 PF9/AN9 87 PF10/AN10 PF10/AN10 PF10/AN10 PF10/AN10 86 PF11/AN11 PF11/AN11 PF11/AN11 PF11/AN11 85 PF12/AN12 PF12/AN12 PF12/AN12 PF12/AN12 84 PF13/AN13 PF13/AN13 PF13/AN13 PF13/AN13 83 PF14/AN14 PF14/AN14 PF14/AN14 PF14/AN14 82 PF15/AN15 PF15/AN15 PF15/AN15 PF15/AN15 Notes: 1. F-ZTAT version only. 2. F-ZTAT version only. Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low). 3. Only in F-ZTAT version supporting full functions of E10A. Fixed as the AUD pins when using the AUD function of the E10A. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 653 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Table 17.11 SH7149 Pin Functions in Each Operating Mode (2) Pin Name On-Chip ROM Enabled (MCU Mode 2) Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities Initial Function PFC Selected Function Possibilities 5, 24, 39, Vcc Vcc Vcc Vcc 7, 22, 41, 57 Vss Vss Vss Vss 12, 61 VCL VCL VCL VCL 90, 96 AVcc AVcc AVcc AVcc 59, 73 81, 93 AVss AVss AVss AVss 75 PLLVss PLLVss PLLVss PLLVss 67 EXTAL EXTAL EXTAL EXTAL 66 XTAL XTAL XTAL XTAL 72 MD0 MD0 MD0 MD0 71 MD1 MD1 1 MD1 MD1 FWE* FWE*1 RES RES RES WDTOVF WDTOVF WDTOVF WDTOVF NMI NMI NMI FWE* 1 1 70 FWE* 64 RES 65 69 68 ASEMD0* ASEMD0* 63 PA0 PA0/A0/POE0/RXD0 PA0 PA0/POE0/RXD0 62 PA1 PA1/A1/POE1/TXD0 PA1 PA1/POE1/TXD0 60 PA2 PA2/A2/IRQ0/POE2/SCK0 PA2 PA2/IRQ0/POE2/SCK0 58 PA3 PA3/A3/IRQ1/RXD1 PA3 PA3/IRQ1/RXD1 56 PA4 PA4/A4/IRQ2/TXD1 PA4 PA4/IRQ2/TXD1 1 1 ASEMD0* NMI 1 ASEMD0*1 55 PA5 PA5/A5/IRQ3/SCK1 PA5 PA5/IRQ3/SCK1 54 PA6 PA6/RD/UBCTRG/TCLKA PA6 PA6/UBCTRG/TCLKA/POE4 /POE4 53 PA7 PA7/WRH/TCLKB/POE5/SCK2 PA7 PA7/TCLKB/POE5/SCK2 52 PA8 PA8/WRL/TCLKC/POE6/RXD2 PA8 PA8/TCLKC/POE6/RXD2 51 PA9 PA9/WAIT/TCLKD/POE8/TXD2 PA9 PA9/TCLKD/POE8/TXD2 50 PA10 PA10/A6/RXD0 PA10 PA10/RXD0 Page 654 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name On-Chip ROM Enabled (MCU Mode 2) Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities Initial Function PFC Selected Function Possibilities 49 PA11 PA11/A7/TXD0/ADTRG PA11 PA11/TXD0/ADTRG 48 PA12 PA12/A8/SCK0 PA12 PA12/SCK0 47 PA13 PA13/A9/SCK1 PA13 PA13/SCK1 46 PA14 PA14/A10/RXD1 PA14 PA14/RXD1 45 CK PA15/CK/TXD1 PA15 PA15/TXD1 80 PB0 PB0/BACK/TIC5WS PB0 PB0/TIC5WS 79 PB1 PB1/BREQ/TIC5W PB1 PB1/TIC5W 78 PB2 PB2/A16/IRQ0/POE0/TIC5VS PB2 PB2/IRQ0/POE0/TIC5VS 77 PB3 PB3/A17/IRQ1/POE1/TIC5V PB3 PB3/IRQ1/POE1/TIC5V 76 PB4 PB4/A18/IRQ2/POE4/TIC5US PB4 PB4/IRQ2/POE4/TIC5US 74 PB5 PB5/A19/IRQ3/POE5/TIC5U PB5 PB5/IRQ3/POE5/TIC5U 97 POE3 PB16/POE3 POE3 PB16/POE3 98 POE7 PB17/POE7 POE7 PB17/POE7 26 POE8 PB18/POE8 POE8 PB18/POE8 44 PD0 PD0/D0/RXD0 PD0 PD0/RXD0 43 PD1 PD1/D1/TXD0 PD1 PD1/TXD0 42 PD2 PD2/D2/SCK0 PD2 PD2/SCK0 40 PD3 PD3/D3/RXD1 PD3 PD3/RXD1 38 PD4 PD4/D4/IRQ0/TXD1 PD4 PD4/IRQ0/TXD1 37 PD5 PD5/D5/IRQ1/SCK1 PD5 PD5/IRQ1/SCK1 36 PD6 PD6/D6/IRQ2/RXD2 PD6 PD6/IRQ2/RXD2 35 PD7 PD7/D7/IRQ3/TXD2 PD7 PD7/IRQ3/TXD2 34 PD8/(AUDATA0* ) PD8/D8/SCK2 PD8/(AUDATA0* ) 33 32 3 3 PD8/SCK2 3 PD9/(AUDATA1* ) PD9/D9 PD9/(AUDATA1* ) PD9 PD10 PD10/D10 PD10 PD10 3 /(AUDATA2*3) /(AUDATA2* ) 31 3 PD11/D11 PD11 3 PD11 PD11 3 /(AUDATA3* ) /(AUDATA3* ) 30 PD12 PD12/D12 PD12 PD12 29 PD13 PD13/D13 PD13 PD13 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 655 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name On-Chip ROM Enabled (MCU Mode 2) PFC Selected Function Possibilities Initial Function PD14/(AUDCK* ) PD14/D14 PD14/(AUDCK* ) PD14 PD15 PD15/D15 PD15 PD15 Pin No. Initial Function 28 27 Single-Chip Mode (MCU Mode 3) 3 3 3 PFC Selected Function Possibilities 3 /(AUDSYNC* ) /(AUDSYNC* ) 25 PE0 PE0/TIOC0A PE0 PE0/TIOC0A 23 PE1 PE1/TIOC0B/RXD0 PE1 PE1/TIOC0B/RXD0 21 PE2 PE2/TIOC0C/TXD0 PE2 PE2/TIOC0C/TXD0 20 PE3 PE3/TIOC0D/SCK0 PE3 PE3/TIOC0D/SCK0 19 PE4 PE4/A11/TIOC1A/RXD1 PE4 PE4/TIOC1A/RXD1 18 PE5 PE5/A12/TIOC1B/TXD1 PE5 PE5/TIOC1B/TXD1 17 PE6 PE6/A13/TIOC2A/SCK1 PE6 PE6/TIOC2A/SCK1 16 PE7 PE7/A14/TIOC2B PE7 PE7/TIOC2B 15 PE8 PE8/A15/TIOC3A PE8 PE8/TIOC3A 13 PE9 PE9/TIOC3B PE9 PE9/TIOC3B 14 PE10 PE10/CS0/TIOC3C PE10 PE10/TIOC3C 11 PE11 PE11/TIOC3D PE11 PE11/TIOC3D 10 PE12 PE12/TIOC4A PE12 PE12/TIOC4A 9 PE13 PE13/TIOC4B/MRES PE13 PE13/TIOC4B/MRES 8 PE14 PE14/TIOC4C PE14 PE14/TIOC4C 6 PE15 PE15/TIOC4D/IRQOUT PE15 PE15/TIOC4D/IRQOUT 4 PE16/(ASEBRKAK PE16/WAIT/TIOC3BS 2 3 2 1 100 PE16/(ASEBRKAK PE16/TIOC3BS /ASEBRK*2) /ASEBRK* ) PE17/(TCK*2) 2 PE18/(TDI* ) PE17/CS0/TIOC3DS PE18/CS1/TIOC4AS 2 PE19/(TDO* ) 2 PE20/(TMS* ) 2 PE19/RD/TIOC4BS PE20/WRH/TIOC4CS PE17/(TCK*2) 2 PE18/(TDI* ) PE17/TIOC3DS PE18/TIOC4AS 2 PE19/(TDO* ) 2 PE20/(TMS* ) 2 PE19/TIOC4BS PE20/TIOC4CS 99 PE21/(TRST* ) PE21/WRL/TIOC4DS PE21/(TRST* ) PE21/TIOC4DS 95 PF0/AN0 PF0/AN0 PF0/AN0 PF0/AN0 94 PF2/AN2 PF2/AN2 PF2/AN2 PF2/AN2 92 PF4/AN4 PF4/AN4 PF4/AN4 PF4/AN4 91 PF6/AN6 PF6/AN6 PF6/AN6 PF6/AN6 Page 656 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Pin Name On-Chip ROM Enabled (MCU Mode 2) Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities Initial Function PFC Selected Function Possibilities 89 PF8/AN8 PF8/AN8 PF8/AN8 PF8/AN8 88 PF9/AN9 PF9/AN9 PF9/AN9 PF9/AN9 87 PF10/AN10 PF10/AN10 PF10/AN10 PF10/AN10 86 PF11/AN11 PF11/AN11 PF11/AN11 PF11/AN11 85 PF12/AN12 PF12/AN12 PF12/AN12 PF12/AN12 84 PF13/AN13 PF13/AN13 PF13/AN13 PF13/AN13 83 PF14/AN14 PF14/AN14 PF14/AN14 PF14/AN14 82 PF15/AN15 PF15/AN15 PF15/AN15 PF15/AN15 Notes: 1. F-ZTAT version only. 2. F-ZTAT version only. Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low). 3. Only in F-ZTAT version supporting full functions of E10A. Fixed as the AUD pins when using the AUD function of the E10A. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 657 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) 17.1 Register Descriptions The PFC has the following registers. For details on register addresses and register states in each processing state, refer to section 23, List of Registers. Table 17.12 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Port A I/O register L PAIORL R/W H'0000 H'FFFFD106 8, 16 Port A control register L4 PACRL4 R/W H'0000* H'FFFFD110 8, 16, 32 Port A control register L3 PACRL3 R/W H'0000* H'FFFFD112 8, 16 Port A control register L2 PACRL2 R/W H'0000* H'FFFFD114 8, 16, 32 Port A control register L1 PACRL1 R/W H'0000* H'FFFFD116 8, 16 Port B I/O register H PBIORH R/W H'0000 H'FFFFD184 8, 16, 32 Port B I/O register L PBIORL R/W H'0000 H'FFFFD186 8, 16 Port B control register H1 PBCRH1 R/W H'0111 H'FFFFD18E 8, 16 Port B control register L2 PBCRL2 R/W H'0000 H'FFFFD194 8, 16, 32 Port B control register L1 PBCRL1 R/W H'0000* H'FFFFD196 8, 16 Port D I/O register L PDIORL R/W H'0000 H'FFFFD286 8, 16 Port D control register L4 PDCRL4 R/W H'0000* H'FFFFD290 8, 16, 32 Port D control register L3 PDCRL3 R/W H'0000* H'FFFFD292 8, 16 Port D control register L2 PDCRL2 R/W H'0000* H'FFFFD294 8, 16, 32 Port D control register L1 PDCRL1 R/W H'0000* H'FFFFD296 8, 16 Port E I/O register H PEIORH R/W H'0000 H'FFFFD304 8, 16, 32 Port E I/O register L PEIORL R/W H'0000 H'FFFFD306 8, 16 Port E control register H2 PECRH2 R/W H'0000 H'FFFFD30C 8, 16, 32 Port E control register H1 PECRH1 R/W H'0000 H'FFFFD30E 8, 16 Port E control register L4 PECRL4 R/W H'0000 H'FFFFD310 8, 16, 32 Port E control register L3 PECRL3 R/W H'0000* H'FFFFD312 8, 16 Port E control register L2 PECRL2 R/W H'0000* H'FFFFD314 8, 16, 32 Port E control register L1 PECRL1 R/W H'0000 H'FFFFD316 8, 16 IRQOUT function control register IFCR R/W H'0000 H'FFFFD322 8, 16 Note: * For SH7149, the initial value differs in the on-chip ROM enabled/disabled externalextension mode. For details, refer to register descriptions in this section. Page 658 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 17.1.1 Section 17 Pin Function Controller (PFC) Port A I/O Register L (PAIORL) PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0). In other states, PAIORL is disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an input pin if the bit is cleared to 0. The initial value of PAIORL is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4) PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port A. SH7146: * Port A Control Register L4 (PACRL4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA15 MD2 PA15 MD1 PA15 MD0 - PA14 MD2 PA14 MD1 PA14 MD0 - PA13 MD2 PA13 MD1 PA13 MD0 - PA12 MD2 PA12 MD1 PA12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA15MD2 0 R/W PA15 Mode 13 PA15MD1 0 R/W Select the function of the PA15/TXD1 pin. 12 PA15MD0 0 R/W 000: PA15 I/O (port) 110: TXD1 output (SCI) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 659 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PA14MD2 0 R/W PA14 Mode 9 PA14MD1 0 R/W Select the function of the PA14/RXD1 pin. 8 PA14MD0 0 R/W 000: PA14 I/O (port) 110: RXD1 input (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PA13MD2 0 R/W PA13 Mode 5 PA13MD1 0 R/W Select the function of the PA13/SCK1 pin. 4 PA13MD0 0 R/W 000: PA13 I/O (port) 110: SCK1 I/O (SCI) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA12MD2 0 R/W PA12 Mode 1 PA12MD1 0 R/W Select the function of the PA12/SCK0 pin. 0 PA12MD0 0 R/W 000: PA12 I/O (port) 110: SCK0 I/O (SCI) Other than above: Setting prohibited Page 660 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port A Control Register L3 (PACRL3) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA11 MD2 PA11 MD1 PA11 MD0 - PA10 MD2 PA10 MD1 PA10 MD0 - PA9 MD2 PA9 MD1 PA9 MD0 - PA8 MD2 PA8 MD1 PA8 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA11MD2 0 R/W PA11 Mode 13 PA11MD1 0 R/W Select the function of the PA11/TXD0/ADTRG pin. 12 PA11MD0 0 R/W 000: PA11 I/O (port) 010: ADTRG input (A/D) 110: TXD0 output (SCI) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PA10MD2 0 R/W PA10 Mode 9 PA10MD1 0 R/W Select the function of the PA10/RXD0 pin. 8 PA10MD0 0 R/W 000: PA10 I/O (port) 110: RXD0 input (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PA9MD2 0 R/W PA9 Mode 5 PA9MD1 0 R/W Select the function of the PA9/TCLKD/TXD2 pin. 4 PA9MD0 0 R/W 000: PA9 I/O (port) 001: TCLKD input (MTU2) 110: TXD2 output (SCI) 111: POE8 input (POE) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 661 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA8MD2 0 R/W PA8 Mode 1 PA8MD1 0 R/W 0 PA8MD0 0 R/W Select the function of the PA8/TCLKC/POE6/RXD2 pin. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 110: RXD2 input (SCI) 111: POE6 input (POE) Other than above: Setting prohibited * Port A Control Register L2 (PACRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA7 MD2 PA7 MD1 PA7 MD0 - PA6 MD2 PA6 MD1 PA6 MD0 - PA5 MD2 PA5 MD1 PA5 MD0 - PA4 MD2 PA4 MD1 PA4 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA7MD2 0 R/W PA7 Mode 13 PA7MD1 0 R/W 12 PA7MD0 0 R/W Select the function of the PA7/TCLKB/POE5/SCK2 pin. 000: PA7 I/O (port) 001: TCLKB input (MTU2) 110: SCK2 I/O (SCI) 111: POE5 input (POE) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 662 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 10 PA6MD2 0 R/W PA6 Mode 9 PA6MD1 0 R/W 8 PA6MD0 0 R/W Select the function of the PA6/UBCTRG/TCLKA/POE4 pin. 000: PA6 I/O (port) 001: TCLKA input (MTU2) 101: UBCTRG output (UBC) 111: POE4 input (POE) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PA5MD2 0 R/W PA5 Mode 5 PA5MD1 0 R/W Select the function of the PA5/IRQ3/SCK1 pin. 4 PA5MD0 0 R/W 000: PA5 I/O (port) 001: SCK1 I/O (SCI) 111: IRQ3 input (INTC) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA4MD2 0 R/W PA4 Mode 1 PA4MD1 0 R/W Select the function of the PA4/IRQ2/TXD1 pin. 0 PA4MD0 0 R/W 000: PA4 I/O (port) 001: TXD1 output (SCI) 111: IRQ2 input (INTC) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 663 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) * Port A Control Register L1 (PACRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA3 MD2 PA3 MD1 PA3 MD0 - PA2 MD2 PA2 MD1 PA2 MD0 - PA1 MD2 PA1 MD1 PA1 MD0 - PA0 MD2 PA0 MD1 PA0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA3MD2 0 R/W PA3 Mode 13 PA3MD1 0 R/W Select the function of the PA3/IRQ1/RXD1 pin. 12 PA3MD0 0 R/W 000: PA3 I/O (port) 001: RXD1 input (SCI) 111: IRQ1 input (INTC) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PA2MD2 0 R/W PA2 Mode 9 PA2MD1 0 R/W Select the function of the PA2/IRQ0/POE2/SCK0 pin. 8 PA2MD0 0 R/W 000: PA2 I/O (port) 001: SCK0 I/O (SCI) 011: IRQ0 input (INTC) 111: POE2 input (POE) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PA1MD2 0 R/W PA1 Mode 5 PA1MD1 0 R/W Select the function of the PA1/POE1/TXD0 pin. 4 PA1MD0 0 R/W 000: PA1 I/O (port) 001: TXD0 output (SCI) 111: POE1 input (POE) Other than above: Setting prohibited Page 664 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA0MD2 0 R/W PA0 Mode 1 PA0MD1 0 R/W Select the function of the PA0/POE0/RXD0 pin. 0 PA0MD0 0 R/W 000: PA0 I/O (port) 001: RXD0 input (SCI) 111: POE0 input (POE) Other than above: Setting prohibited SH7149: * Port A Control Register L4 (PACRL4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA15 MD2 PA15 MD1 PA15 MD0 - PA14 MD2 PA14 MD1 PA14 MD0 - PA13 MD2 PA13 MD1 PA13 MD0 - PA12 MD2 PA12 MD1 PA12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0*1 R/W 0 R 0*2 R/W 0 R/W 0 R/W 0 R 0*2 R/W 0 R/W 0 R/W 0 R 0*2 R/W 0 R/W 0 R/W Notes: 1. The initial value is 1 in the on-chip ROM enabled/disabled external-extension mode. 2. The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA15MD2 0 13 PA15MD1 0 12 PA15MD0 0* 1 R/W PA15 Mode R/W Select the function of the PA15/CK/TXD1 pin. R/W 000: PA15 I/O (port) 001: CK output (CPG)* 3 110: TXD1 output (SCI) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 665 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value 2 R/W Description R/W PA14 Mode 10 PA14MD2 0* 9 PA14MD1 0 R/W Select the function of the PA14/A10/RXD1 pin. 8 PA14MD0 0 R/W 000: PA14 I/O (port) 100: A10 output (BSC)* 3 110: RXD1 input (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 6 PA13MD2 0* R/W PA13 Mode 5 PA13MD1 0 R/W Select the function of the PA13/A9/SCK1 pin. 4 PA13MD0 0 R/W 000: PA13 I/O (port) 100: A9 output (BSC)* 3 110: SCK1 I/O (SCI) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA12MD2 0* 1 PA12MD1 0 PA12MD0 2 R/W PA12 Mode 0 R/W Select the function of the PA12/A8/SCK0 pin. 0 R/W 000: PA12 I/O (port) 100: A8 output (BSC)* 3 110: SCK0 I/O (SCI) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM enabled/disabled external-extension mode. 2. The initial value is 1 in the on-chip ROM disabled external-extension mode. 3. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. Page 666 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port A Control Register L3 (PACRL3) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA11 MD2 PA11 MD1 PA11 MD0 - PA10 MD2 PA10 MD1 PA10 MD0 - PA9 MD2 PA9 MD1 PA9 MD0 - PA8 MD2 PA8 MD1 PA8 MD0 Initial value: 0 R/W: R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 14 PA11MD2 0* R/W PA11 Mode 13 PA11MD1 0 R/W Select the function of the PA11/A7/TXD0/ADTRG pin. 12 PA11MD0 0 R/W 000: PA11 I/O (port) 010: ADTRG input (A/D) 100: A7 output (BSC)* 2 110: TXD0 output (SCI) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PA10MD2 0* 9 PA10MD1 8 PA10MD0 1 R/W PA10 Mode 0 R/W Select the function of the PA10/A6/RXD0 pin. 0 R/W 000: PA10 I/O (port) 100: A6 output (BSC)* 2 110: RXD0 input (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 667 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 6 PA9MD2 0 R/W PA9 Mode 5 PA9MD1 0 R/W 4 PA9MD0 0 R/W Select the function of the PA9/WAIT/TCLKD/TXD2 pin. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 100: WAIT input (BSC)* 2 110: TXD2 output (SCI) 111: POE8 input (POE) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA8MD2 0* 1 PA8MD1 0 PA8MD0 1 R/W PA8 Mode 0 R/W 0 R/W Select the function of the PA8/WRL/TCLKC/POE6/RXD2 pin. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 100: WRL output (BSC)* 2 110: RXD2 input (SCI) 111: POE6 input (POE) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. Page 668 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port A Control Register L2 (PACRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA7 MD2 PA7 MD1 PA7 MD0 - PA6 MD2 PA6 MD1 PA6 MD0 - PA5 MD2 PA5 MD1 PA5 MD0 - PA4 MD2 PA4 MD1 PA4 MD0 Initial value: 0 R/W: R 0*1 R/W 0 R/W 0 R/W 0 R 0 R/W 0*2 R/W 0*2 R/W 0 R 0*2 R/W 0 R/W 0 R/W 0 R 0*2 R/W 0 R/W 0 R/W Notes: 1. The initial value is 1 in the on-chip ROM disabled 16-bit external-extension mode. 2. The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA7MD2 0* 13 PA7MD1 12 PA7MD0 1 R/W PA7 Mode 0 R/W 0 R/W Select the function of the PA7/WRH/TCLKB/POE5/SCK2 pin. 000: PA7 I/O (port) 001: TCLKB input (MTU2) 100: WRH output (BSC)* 3 110: SCK2 I/O (SCI) 111: POE5 input (POE) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PA6MD2 0 9 PA6MD1 0* 2 8 PA6MD0 0* 2 R/W PA6 Mode R/W R/W Select the function of the PA6/RD/UBCTRG/TCLKA/POE4 pin. 000: PA6 I/O (port) 001: TCLKA input (MTU2) 011: RD output (BSC)* 3 101: UBCTRG output (UBC) 111: POE4 input (POE) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 669 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PA5MD2 0* 5 PA5MD1 4 PA5MD0 2 R/W PA5 Mode 0 R/W Select the function of the PA5/A5/IRQ3/SCK1 pin. 0 R/W 000: PA5 I/O (port) 001: SCK1 I/O (SCI) 100: A5 output (BSC)* 3 111: IRQ3 input (INTC) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA4MD2 0* 1 PA4MD1 0 PA4MD0 2 R/W PA4 Mode 0 R/W Select the function of the PA4/A4/IRQ2/TXD1 pin. 0 R/W 000: PA4 I/O (port) 001: TXD1 output (SCI) 100: A4 output (BSC)* 3 111: IRQ2 input (INTC) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled 16-bit external-extension mode. 2. The initial value is 1 in the on-chip ROM disabled external-extension mode. 3. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. Page 670 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port A Control Register L1 (PACRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PA3 MD2 PA3 MD1 PA3 MD0 - PA2 MD2 PA2 MD1 PA2 MD0 - PA1 MD2 PA1 MD1 PA1 MD0 - PA0 MD2 PA0 MD1 PA0 MD0 Initial value: 0 R/W: R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PA3MD2 0* 13 PA3MD1 12 PA3MD0 1 R/W PA3 Mode 0 R/W Select the function of the PA3/A3/IRQ1/RXD1 pin. 0 R/W 000: PA3 I/O (port) 001: RXD1 input (SCI) 100: A3 output (BSC)* 2 111: IRQ1 input (INTC) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PA2MD2 0* 9 PA2MD1 8 PA2MD0 1 R/W PA2 Mode 0 R/W 0 R/W Select the function of the PA2/A2/IRQ0/POE2/SCK0 pin. 000: PA2 I/O (port) 001: SCK0 I/O (SCI) 011: IRQ0 input (INTC) 100: A2 output (BSC)* 2 111: POE2 input (POE) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 671 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value 1 R/W Description R/W PA1 Mode 6 PA1MD2 0* 5 PA1MD1 0 R/W Select the function of the PA1/A1/POE1/TXD0 pin. 4 PA1MD0 0 R/W 000: PA1 I/O (port) 001: TXD0 output (SCI) 100: A1 output (BSC)* 2 111: POE1 input (POE) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 2 PA0MD2 0* R/W PA0 Mode 1 PA0MD1 0 R/W Select the function of the PA0/A0/POE0/RXD0 pin. 0 PA0MD0 0 R/W 000: PA0 I/O (port) 001: RXD0 input (SCI) 100: A0 output (BSC)* 2 111: POE0 input (POE) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. Page 672 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 17.1.3 Section 17 Pin Function Controller (PFC) Port B I/O Register L, H (PBIORL, PBIORH) PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B as inputs or outputs. Bits PB18IOR to PB16IOR and PB5IOR to PB0IOR correspond to pins PB18 to PB16 and PB5 to PB0, respectively (names of multiplexed pins are here given as port names and pin numbers alone). PBIORL is enabled when the port B pins are functioning as generalpurpose inputs/outputs (PB5 to PB0). In other states, PBIORL is disabled. PBIORH is enabled when the port B pins are functioning as general-purpose inputs/outputs (PB18 to PB16). In other states, PBIORH is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 1 and 0 of PBIORL are disabled in SH7146. Bits 15 to 6 of PBIORL and bits 15 to 3 of PBIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PBIORL and PBIORH are H'0000, respectively. * Port B I/O Register H (PBIORH) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - PB18 IOR PB17 IOR PB16 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W * Port B I/O Register L (PBIORL) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 673 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) 17.1.4 Port B Control Registers L1, L2, H1 (PBCRL1, PBCRL2, PBCRH1) PBCRL1, PBCRL2, and PBCRH1 are 16-bit readable/writable registers that are used to select the function of the multiplexed pins on port B. SH7146: * Port B Control Register H1 (PBCRH1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PB18 MD - - - PB17 MD - - - PB16 MD Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W* 0 R 0 R 0 R 1 R/W* 0 R 0 R 0 R 1 R/W* Note: * After a power-on reset, write can be performed only once. Rewrite must be performed when the POE function is selected as the initial value. Bit Bit Name Initial Value R/W 15 to 9 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 8 PB18MD 1 R/W* PB18 Mode Select the function of the PB18/POE8 pin. 0: PB18 I/O (port) 1: POE8 input (POE) 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 PB17MD 1 R/W* PB17 Mode Select the function of the PB17/POE7 pin. 0: PB17 I/O (port) 1: POE7 input (POE) 3 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 674 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 0 PB16MD 1 R/W* PB16 Mode Select the function of the PB16/POE3 pin. 0: PB16 I/O (port) 1: POE3 input (POE) Note: * After a power-on reset, write can be performed only once. Rewrite must be performed when the POE function is selected as the initial value. * Port B Control Register L2 (PBCRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - PB5 MD2 PB5 MD1 PB5 MD0 - PB4 MD2 PB4 MD1 PB4 MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 7 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 PB5MD2 0 R/W PB5 Mode 5 PB5MD1 0 R/W Select the function of the PB5/IRQ3/POE5/TIC5U pin. 4 PB5MD0 0 R/W 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) 101: A19 output (BSC)* 111: POE5 input (POE) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 675 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 2 PB4MD2 0 R/W PB4 Mode 1 PB4MD1 0 R/W 0 PB4MD0 0 R/W Select the function of the PB4/IRQ2/POE4/TIC5US pin. 000: PB4 I/O (port) 001: IRQ2 input (INTC) 011: TIC5US input (MTU2S) 101: A18 output (BSC)* 111: POE4 input (POE) Other than above: Setting prohibited Note: * This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. * Port B Control Register L1 (PBCRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PB3 MD2 PB3 MD1 PB3 MD0 - PB2 MD2 PB2 MD1 PB2 MD0 - - - - - - - - Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PB3MD2 0 R/W PB3 Mode 13 PB3MD1 0 R/W Select the function of the PB3/IRQ1/POE1/TIC5V pin. 12 PB3MD0 0 R/W 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) 101: A17 output (BSC) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 676 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 10 PB2MD2 0 R/W PB2 Mode 9 PB2MD1 0 R/W 8 PB2MD0 0 R/W Select the function of the PB2/IRQ0/POE0/TIC5VS pin. 000: PB2 I/O (port) 001: IRQ0 input (INTC) 010: POE0 input (POE) 011: TIC5VS input (MTU2S) 101: A16 output (BSC) Other than above: Setting prohibited 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. SH7149: * Port B Control Register H1 (PBCRH1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PB18 MD - - - PB17 MD - - - PB16 MD Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W* 0 R 0 R 0 R 1 R/W* 0 R 0 R 0 R 1 R/W* Note: * After a power-on reset, write can be performed only once. Rewrite must be performed when the POE function is selected as the initial value. Bit Bit Name Initial Value R/W 15 to 9 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 8 PB18MD 1 R/W* PB18 Mode Select the function of the PB18/POE8 pin. 0: PB18 I/O (port) 1: POE8 input (POE) 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 677 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 4 PB17MD 1 R/W* PB17 Mode Select the function of the PB17/POE7 pin. 0: PB17 I/O (port) 1: POE7 input (POE) 3 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PB16MD 1 R/W* PB16 Mode Select the function of the PB16/POE3 pin. 0: PB16 I/O (port) 1: POE3 input (POE) Note: * After a power-on reset, write can be performed only once. Rewrite must be performed when the POE function is selected as the initial value. * Port B Control Register L2 (PBCRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - PB5 MD2 PB5 MD1 PB5 MD0 - PB4 MD2 PB4 MD1 PB4 MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15 to 7 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 6 PB5MD2 0 R/W PB5 Mode 5 PB5MD1 0 R/W 4 PB5MD0 0 R/W Select the function of the PB5/A19/IRQ3/POE5/TIC5U pin. 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) 101: A19 output (BSC)* 111: POE5 input (POE) Other than above: Setting prohibited Page 678 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PB4MD2 0 R/W PB4 Mode 1 PB4MD1 0 R/W 0 PB4MD0 0 R/W Select the function of the PB4/A18/IRQ2/POE4/TIC5US pin. 000: PB4 I/O (port) 001: IRQ2 input (INTC) 011: TIC5US input (MTU2S) 101: A18 output (BSC)* 111: POE4 input (POE) Other than above: Setting prohibited Note: * This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. * Port B Control Register L1 (PBCRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PB3 MD2 PB3 MD1 PB3 MD0 - PB2 MD2 PB2 MD1 PB2 MD0 - PB1 MD2 PB1 MD1 PB1 MD0 - PB0 MD2 PB0 MD1 PB0 MD0 Initial value: 0 R/W: R 0* R/W 0 R/W 0* R/W 0 R 0* R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PB3MD2 PB3MD1 PB3MD0 0* 0 1 0* R/W R/W R/W PB3 Mode Select the function of the PB3/A17/IRQ1/POE1/TIC5V pin. 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) 2 101: A17 output (BSC)* Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 1 Page 679 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PB2MD2 0* 9 PB2MD1 0 8 PB2MD0 0* 1 1 R/W PB2 Mode R/W Select the function of the PB2/A16/IRQ0/POE0/TIC5VS pin. R/W 000: PB2 I/O (port) 001: IRQ0 input (INTC) 010: POE0 input (POE) 011: TIC5VS input (MTU2S) 101: A16 output (BSC)* 2 Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PB1MD2 0 R/W PB1 Mode 5 PB1MD1 0 R/W Select the function of the PB1/BREQ/TIC5W pin. 4 PB1MD0 0 R/W 000: PB1 I/O (port) 011: TIC5W input (MTU2) 101: BREQ input (BSC)* 2 Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PB0MD2 0 R/W PB0 Mode 1 PB0MD1 0 R/W Select the function of the PB0/BACK/TIC5WS pin. 0 PB0MD0 0 R/W 000: PB0 I/O (port) 011: TIC5WS input (MTU2S) 101: BACK output (BSC)* 2 Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. Page 680 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 17.1.5 Section 17 Pin Function Controller (PFC) Port D I/O Register L (PDIORL) (SH7149 Only) PDIORL is a 16-bit readable/writable register that is used to set the pins on port D as inputs or outputs. Bits PD15IOR to PD0IOR correspond to pins PD15 to PD0 (names of multiplexed pins are here given as port names and pin numbers alone). PDIORL is enabled when the port D pins are functioning as general-purpose inputs/outputs (PD15 to PD0). In other states, PDIORL is disabled. A given pin on port D will be an output pin if the corresponding bit in PDIORL is set to 1, and an input pin if the bit is cleared to 0. However, PDIORL is disabled in SH7146. The initial value of PDIORL is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 IOR PD14 IOR PD13 IOR PD12 IOR PD11 IOR PD10 IOR PD9 IOR PD8 IOR PD7 IOR PD6 IOR PD5 IOR PD4 IOR PD3 IOR PD2 IOR PD1 IOR PD0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17.1.6 Port D Control Registers L1 to L4 (PDCRL1 to PDCRL4) (SH7149 Only) PDCRL1 to PDCRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port D. However, PDCRL1 to PDCRL4 are disabled in SH7146. * Port D Control Register L4 (PDCRL4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - PD15 MD1 PD15 MD0 - - PD14 MD1 PD14 MD0 - - PD13 MD1 PD13 MD0 - - PD12 MD1 PD12 MD0 Initial value: 0 R/W: R 0 R 0 R/W 0* R/W 0 R 0 R 0 R/W 0* R/W 0 R 0 R 0 R/W 0* R/W 0 R 0 R 0 R/W 0* R/W Note: * The initial value is 1 in the on-chip ROM disabled 16-bit external-extension mode. Bit Bit Name Initial Value R/W 15, 14 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 681 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 13 PD15MD1 0 R/W PD15 Mode R/W Select the function of the PD15/D15/AUDSYNC pin. Fixed to AUDSYNC output when using the AUD function of E10A. 12 PD15MD0 0* 1 00: PD15 I/O (port) 01: D15 I/O (BSC)* 2 Other than above: Setting prohibited 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PD14MD1 0 8 PD14MD0 0* 1 R/W PD14 Mode R/W Select the function of the PD14/D14/AUDCK pin. Fixed to AUDCK output when using the AUD function of E10A. 00: PD14 I/O (port) 01: D14 I/O (BSC)* 2 Other than above: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 4 PD13MD1 PD13MD0 0 0* 1 R/W PD13 Mode R/W Select the function of the PD13/D13 pin. 00: PD13 I/O (port) 01: D13 I/O (BSC)* 2 Other than above: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 682 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 1 PD12MD1 0 R/W PD12 Mode R/W Select the function of the PD12/D12 pin. 0 PD12MD0 0* 1 00: PD12 I/O (port) 01: D12 I/O (BSC)* 2 Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled 16-bit external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. * Port D Control Register L3 (PDCRL3) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - PD11 MD1 PD11 MD0 - PD10 MD2 PD10 MD1 PD10 MD0 - PD9 MD2 PD9 MD1 PD9 MD0 - PD8 MD2 PD8 MD1 PD8 MD0 Initial value: 0 R/W: R 0 R 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W Note: * The initial value is 1 in the on-chip ROM disabled 16-bit external-extension mode. Bit Bit Name Initial Value R/W 15, 14 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 13 PD11MD1 0 12 PD11MD0 0* 1 R/W PD11 Mode R/W Select the function of the PD11/D11/AUDATA3 pin. Fixed to AUDATA3 output when using the AUD function of E10A. 00: PD11 I/O (port) 01: D11 I/O (BSC)* 2 Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 683 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 10 PD10MD2 0 R/W PD10 Mode 9 PD10MD1 0 R/W 8 PD10MD0 0* Select the function of the PD10/D10/AUDATA2 pin. Fixed to AUDATA2 output when using the AUD function of E10A. 1 R/W 000: PD10 I/O (port) 001: D10 I/O (BSC)* 2 Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PD9MD2 0 R/W PD9 Mode 5 PD9MD1 0 R/W Select the function of the PD9/D9/AUDATA1 pin. Fixed to AUDATA1 output when using the AUD function of E10A. 4 PD9MD0 0* 1 R/W 000: PD9 I/O (port) 001: D9 I/O (BSC)* 2 Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PD8MD2 0 1 PD8MD1 0 0 PD8MD0 0* 1 R/W PD8 Mode R/W Select the function of the PD8/D8/SCK2/AUDATA0 pin. Fixed to AUDATA0 output when using the AUD function of E10A. R/W 000: PD8 I/O (port) 001: D8 I/O (BSC)* 2 110: SCK2 I/O (SCI) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled 16-bit external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. Page 684 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port D Control Register L2 (PDCRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PD7 MD2 PD7 MD1 PD7 MD0 - PD6 MD2 PD6 MD1 PD6 MD0 - PD5 MD2 PD5 MD1 PD5 MD0 - PD4 MD2 PD4 MD1 PD4 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PD7MD2 0 13 PD7MD1 0 12 PD7MD0 0* 1 R/W PD7 Mode R/W Select the function of the PD7/D7/IRQ3/TXD2 pin. R/W 000: PD7 I/O (port) 001: D7 I/O (BSC)* 2 100: IRQ3 input (INTC) 110: TXD2 output (SCI) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PD6MD2 0 9 PD6MD1 0 8 PD6MD0 0* 1 R/W PD6 Mode R/W Select the function of the PD6/D6/IRQ2/RXD2 pin. R/W 000: PD6 I/O (port) 001: D6 I/O (BSC)* 2 100: IRQ2 input (INTC) 110: RXD2 input (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 685 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 6 PD5MD2 0 R/W PD5 Mode 5 PD5MD1 0 R/W Select the function of the PD5/D5/IRQ1/SCK1 pin. 4 PD5MD0 0* R/W 000: PD5 I/O (port) 1 001: D5 I/O (BSC)* 2 100: IRQ1 input (INTC) 110: SCK1 I/O (SCI) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PD4MD2 0 1 PD4MD1 0 0 PD4MD0 0* 1 R/W PD4 Mode R/W Select the function of the PD4/D4/IRQ0/TXD1 pin. R/W 000: PD4 I/O (port) 001: D4 I/O (BSC)* 2 100: IRQ0 input (INTC) 110: TXD1 output (SCI) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. * Port D Control Register L1 (PDCRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PD3 MD2 PD3 MD1 PD3 MD0 - PD2 MD2 PD2 MD1 PD2 MD0 - PD1 MD2 PD1 MD1 PD1 MD0 - PD0 MD2 PD0 MD1 PD0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W 0 R 0 R/W 0 R/W 0* R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 686 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 14 13 12 PD3MD2 PD3MD1 PD3MD0 0 0 1 0* R/W R/W R/W PD3 Mode Select the function of the PD3/D3/RXD1 pin. 000: PD3 I/O (port) 2 001: D3 I/O (BSC)* 110: RXD1 input (SCI) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PD2MD2 PD2MD1 PD2MD0 0 0 1 0* R/W R/W R/W PD2 Mode Select the function of the PD2/D2/SCK0 pin. 000: PD2 I/O (port) 2 001: D2 I/O (BSC)* 110: SCK0 I/O (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PD1MD2 PD1MD1 PD1MD0 0 0 1 0* R/W R/W R/W PD1 Mode Select the function of the PD1/D1/TXD0 pin. 000: PD1 I/O (port) 2 001: D1 I/O (BSC)* 110: TXD0 output (SCI) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PD0MD2 PD0MD1 PD0MD0 0 0 1 0* R/W R/W R/W PD0 Mode Select the function of the PD0/D0/RXD0 pin. 000: PD0 I/O (port) 2 001: D0 I/O (BSC)* 110: RXD0 input (SCI) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 687 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) 17.1.7 Port E I/O Registers L, H (PEIORL, PEIORH) PEIORL and PEIORH are 16-bit readable/writable registers that are used to set the pins on port E as inputs or outputs. PE21IOR to PE0IOR correspond to pins PE21 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PE0), and the TIOC pin is functioning as inputs/outputs of MTU2. In other states, PEIORL is disabled. PEIORH is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE21 to PE16), and the TIOC pin is functioning as inputs/outputs of MTU2S. In other states, PEIORH is disabled. A given pin on port E will be an output pin if the corresponding bit in PEIORH or PEIORL is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 6 of PEIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial values of PEIORL and PEIORH are H'0000, respectively. * Port E I/O Register H (PEIORH) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PE21 IOR PE20 IOR PE19 IOR PE18 IOR PE17 IOR PE16 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Port E I/O Register L (PEIORL) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE15 IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE8 IOR PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 688 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 17.1.8 Section 17 Pin Function Controller (PFC) Port E Control Registers L1 to L4, H1, H2 (PECRL1 to PECRL4, PECRH1, PECRH2) PECRL1 to PECRL4, PECRH1 and PECRH2 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port E. SH7146: * Port E Control Register H2 (PECRH2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PE21 MD1 PE21 MD0 - - PE20 MD1 PE20 MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15 to 6 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 5 PE21MD1 0 R/W PE21 Mode 4 PE21MD0 0 R/W Select the function of the PE21/TIOC4DS/TRST pin. For the F-ZTAT version, fixed to TRST input when using E10A (in ASEMD0 = low). 00: PE21 I/O (port) 01: TIOC4DS I/O (MTU2S) Other than above: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 PE20MD1 0 R/W PE20 Mode 0 PE20MD0 0 R/W Select the function of the PE20/TIOC4CS/TMS pin. For the F-ZTAT version, fixed to TMS input when using E10A (in ASEMD0 = low). 00: PE20 I/O (port) 01: TIOC4CS I/O (MTU2S) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 689 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) * Port E Control Register H1 (PECRH1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - PE19 MD1 PE19 MD0 - - PE18 MD1 PE18 MD0 - - PE17 MD1 PE17 MD0 - PE16 MD2 PE16 MD1 PE16 MD0 Initial value: 0 R/W: R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15, 14 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 13 PE19MD1 0 R/W PE19 Mode 12 PE19MD0 0 R/W Select the function of the PE19/TIOC4BS/TDO pin. For the F-ZTAT version, fixed to TDO output when using E10A (in ASEMD0 = low). 00: PE19 I/O (port) 01: TIOC4BS I/O (MTU2S) Other than above: Setting prohibited 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PE18MD1 0 R/W PE18 Mode 8 PE18MD0 0 R/W Select the function of the PE18/TIOC4AS/TDI pin. For the F-ZTAT version, fixed to TDI input when using E10A (in ASEMD0 = low). 00: PE18 I/O (port) 01: TIOC4AS I/O (MTU2S) Other than above: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 690 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 5 PE17MD1 0 R/W PE17 Mode 4 PE17MD0 0 R/W Select the function of the PE17/TIOC3DS/TCK pin. For the F-ZTAT version, fixed to TCK input when using E10A (in ASEMD0 = low). 00: PE17 I/O (port) 01: TIOC3DS I/O (MTU2S) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE16MD2 0 R/W PE16 Mode 1 PE16MD1 0 R/W 0 PE16MD0 0 R/W Select the function of the PE16/TIOC3BS/ASEBRKAK/ASEBRK pin. For the FZTAT version, fixed to ASEBRKAK output/ASEBRK input when using E10A (in ASEMD0 = low). 000: PE16 I/O (port) 001: TIOC3BS I/O (MTU2S) Other than above: Setting prohibited * Port E Control Register L4 (PECRL4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE15 MD2 PE15 MD1 PE15 MD0 - PE14 MD2 PE14 MD1 PE14 MD0 - - PE13 MD1 PE13 MD0 - PE12 MD2 PE12 MD1 PE12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 691 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 14 PE15MD2 0 R/W PE15 Mode 13 PE15MD1 0 R/W Select the function of the PE15/TIOC4D/IRQOUT pin. 12 PE15MD0 0 R/W 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE14MD2 0 R/W PE14 Mode 9 PE14MD1 0 R/W Select the function of the PE14/TIOC4C pin. 8 PE14MD0 0 R/W 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) Other than above: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PE13MD1 0 R/W PE13 Mode 4 PE13MD0 0 R/W Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (INTC) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE12MD2 0 R/W PE12 Mode 1 PE12MD1 0 R/W Select the function of the PE12/TIOC4A pin. 0 PE12MD0 0 R/W 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited Page 692 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port E Control Register L3 (PECRL3) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE11 MD2 PE11 MD1 PE11 MD0 - PE10 MD2 PE10 MD1 PE10 MD0 - PE9 MD2 PE9 MD1 PE9 MD0 - PE8 MD2 PE8 MD1 PE8 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PE11MD2 0 R/W PE11 Mode 13 PE11MD1 0 R/W Select the function of the PE11/TIOC3D pin. 12 PE11MD0 0 R/W 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE10MD2 0 R/W PE10 Mode 9 PE10MD1 0 R/W Select the function of the PE10/TIOC3C pin. 8 PE10MD0 0 R/W 000: PE10 I/O (port) 001: TIOC3C I/O (MTU2) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PE9MD2 0 R/W PE9 Mode 5 PE9MD1 0 R/W Select the function of the PE9/TIOC3B pin. 4 PE9MD0 0 R/W 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 693 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 2 PE8MD2 0 R/W PE8 Mode 1 PE8MD1 0 R/W Select the function of the PE8/TIOC3A pin. 0 PE8MD0 0 R/W 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) Other than above: Setting prohibited * Port E Control Register L2 (PECRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE7 MD2 PE7 MD1 PE7 MD0 - PE6 MD2 PE6 MD1 PE6 MD0 - PE5 MD2 PE5 MD1 PE5 MD0 - PE4 MD2 PE4 MD1 PE4 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PE7MD2 0 R/W PE7 Mode 13 PE7MD1 0 R/W Select the function of the PE7/TIOC2B pin. 12 PE7MD0 0 R/W 000: PE7 I/O (port) 001: TIOC2B I/O (MTU2) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE6MD2 0 R/W PE6 Mode 9 PE6MD1 0 R/W Select the function of the PE6/TIOC2A/SCK1 pin. 8 PE6MD0 0 R/W 000: PE6 I/O (port) 001: TIOC2A I/O (MTU2) 110: SCK1 I/O (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 694 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 6 PE5MD2 0 R/W PE5 Mode 5 PE5MD1 0 R/W Select the function of the PE5/TIOC1B/TXD1 pin. 4 PE5MD0 0 R/W 000: PE5 I/O (port) 001: TIOC1B I/O (MTU2) 110: TXD1 output (SCI) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE4MD2 0 R/W PE4 Mode 1 PE4MD1 0 R/W Select the function of the PE4/TIOC1A/RXD1 pin. 0 PE4MD0 0 R/W 000: PE4 I/O (port) 001: TIOC1A I/O (MTU2) 110: RXD1 input (SCI) Other than above: Setting prohibited * Port E Control Register L1 (PECRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE3 MD2 PE3 MD1 PE3 MD0 - PE2 MD2 PE2 MD1 PE2 MD0 - PE1 MD2 PE1 MD1 PE1 MD0 - - PE0 MD1 PE0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PE3MD2 0 R/W PE3 Mode 13 PE3MD1 0 R/W Select the function of the PE3/TIOC0D/SCK0 pin. 12 PE3MD0 0 R/W 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 695 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE2MD2 0 R/W PE2 Mode 9 PE2MD1 0 R/W Select the function of the PE2/TIOC0C/TXD0 pin. 8 PE2MD0 0 R/W 000: PE2 I/O (port) 001: TIOC0C I/O (MTU2) 110: TXD0 output (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PE1MD2 0 R/W PE1 Mode 5 PE1MD1 0 R/W Select the function of the PE1/TIOC0B/RXD0 pin. 4 PE1MD0 0 R/W 000: PE1 I/O (port) 001: TIOC0B I/O (MTU2) 110: RXD0 input (SCI) Other than above: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 PE0MD1 0 R/W PE0 Mode 0 PE0MD0 0 R/W Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited Page 696 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) SH7149: * Port E Control Register H2 (PECRH2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PE21 MD1 PE21 MD0 - - PE20 MD1 PE20 MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PE21MD1 0 R/W PE21 Mode 4 PE21MD0 0 R/W Select the function of the PE21/WRL/TIOC4DS/TRST pin. For the F-ZTAT version, fixed to TRST input when using E10A (in ASEMD0 = low). 00: PE21 I/O (port) 01: TIOC4DS I/O (MTU2S) 10: WRL output (BSC)* Other than above: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 PE20MD1 0 R/W PE20 Mode 0 PE20MD0 0 R/W Select the function of the PE20/WRH/TIOC4CS/TMS pin. For the F-ZTAT version, fixed to TMS input when using E10A (in ASEMD0 = low). 00: PE20 I/O (port) 01: TIOC4CS I/O (MTU2S) 10: WRH output (BSC)* Other than above: Setting prohibited Note: * This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 697 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) * Port E Control Register H1 (PECRH1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - PE19 MD1 PE19 MD0 - - PE18 MD1 PE18 MD0 - - PE17 MD1 PE17 MD0 - PE16 MD2 PE16 MD1 PE16 MD0 Initial value: 0 R/W: R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15, 14 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 13 PE19MD1 0 R/W PE19 Mode 12 PE19MD0 0 R/W Select the function of the PE19/RD/TIOC4BS/TDO pin. For the F-ZTAT version, fixed to TDO output when using E10A (in ASEMD0 = low). 00: PE19 I/O (port) 01: TIOC4BS I/O (MTU2S) 10: RD output (BSC)* Other than above: Setting prohibited 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PE18MD1 0 R/W PE18 Mode 8 PE18MD0 0 R/W Select the function of the PE18/CS1/TIOC4AS/TDI pin. For the F-ZTAT version, fixed to TDI input when using E10A (in ASEMD0 = low). 00: PE18 I/O (port) 01: TIOC4AS I/O (MTU2S) 10: CS1 output (BSC)* Other than above: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 698 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 5 PE17MD1 0 R/W PE17 Mode 4 PE17MD0 0 R/W Select the function of the PE17/CS0/TIOC3DS/TCK pin. For the F-ZTAT version, fixed to TCK input when using E10A (in ASEMD0 = low). 00: PE17 I/O (port) 01: TIOC3DS I/O (MTU2S) 10: CS0 output (BSC)* Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE16MD2 0 R/W PE16 Mode 1 PE16MD1 0 R/W 0 PE16MD0 0 R/W Select the function of the PE16/WAIT/TIOC3BS/ASEBRKAK/ASEBRK pin. For the F-ZTAT version, fixed to ASEBRKAK output/ASEBRK input when using E10A (in ASEMD0 = low). 000: PE16 I/O (port) 001: TIOC3BS I/O (MTU2S) 010: WAIT input (BSC)* Other than above: Setting prohibited Note: * This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. * Port E Control Register L4 (PECRL4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE15 MD2 PE15 MD1 PE15 MD0 - PE14 MD2 PE14 MD1 PE14 MD0 - - PE13 MD1 PE13 MD0 - PE12 MD2 PE12 MD1 PE12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 699 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 14 PE15MD2 0 R/W PE15 Mode 13 PE15MD1 0 R/W Select the function of the PE15/TIOC4D/IRQOUT pin. 12 PE15MD0 0 R/W 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE14MD2 0 R/W PE14 Mode 9 PE14MD1 0 R/W Select the function of the PE14/TIOC4C pin. 8 PE14MD0 0 R/W 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) Other than above: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PE13MD1 0 R/W PE13 Mode 4 PE13MD0 0 R/W Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (INTC) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE12MD2 0 R/W PE12 Mode 1 PE12MD1 0 R/W Select the function of the PE12/TIOC4A pin. 0 PE12MD0 0 R/W 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited Page 700 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) * Port E Control Register L3 (PECRL3) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE11 MD2 PE11 MD1 PE11 MD0 - PE10 MD2 PE10 MD1 PE10 MD0 - PE9 MD2 PE9 MD1 PE9 MD0 - PE8 MD2 PE8 MD1 PE8 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PE11MD2 0 R/W PE11 Mode 13 PE11MD1 0 R/W Select the function of the PE11/TIOC3D pin. 12 PE11MD0 0 R/W 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE10MD2 0* 9 PE10MD1 8 PE10MD0 1 R/W PE10 Mode 0 R/W Select the function of the PE10/CS0/TIOC3C pin. 0 R/W 000: PE10 I/O (port) 001: TIOC3C I/O (MTU2) 100: CS0 output (BSC)* 2 Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PE9MD2 0 R/W PE9 Mode 5 PE9MD1 0 R/W Select the function of the PE9/TIOC3B pin. 4 PE9MD0 0 R/W 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 701 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE8MD2 0* 1 PE8MD1 0 PE8MD0 1 R/W PE8 Mode 0 R/W Select the function of the PE8/A15/TIOC3A pin. 0 R/W 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) 100: A15 output (BSC)* 2 Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. * Port E Control Register L2 (PECRL2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE7 MD2 PE7 MD1 PE7 MD0 - PE6 MD2 PE6 MD1 PE6 MD0 - PE5 MD2 PE5 MD1 PE5 MD0 - PE4 MD2 PE4 MD1 PE4 MD0 Initial value: 0 R/W: R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W 0 R 0* R/W 0 R/W 0 R/W Note: * The initial value is 1 in the on-chip ROM disabled external-extension mode. Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PE7MD2 0* 13 PE7MD1 12 PE7MD0 1 R/W PE7 Mode 0 R/W Select the function of the PE7/A14/TIOC2B pin. 0 R/W 000: PE7 I/O (port) 001: TIOC2B I/O (MTU2) 100: A14 output (BSC)* 2 Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 702 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit Bit Name Section 17 Pin Function Controller (PFC) Initial Value 1 R/W Description R/W PE6 Mode 10 PE6MD2 0* 9 PE6MD1 0 R/W Select the function of the PE6/A13/TIOC2A/SCK1 pin. 8 PE6MD0 0 R/W 000: PE6 I/O (port) 001: TIOC2A I/O (MTU2) 100: A13 output (BSC)* 2 110: SCK1 I/O (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PE5MD2 0* 5 PE5MD1 4 PE5MD0 1 R/W PE5 Mode 0 R/W Select the function of the PE5/A12/TIOC1B/TXD1 pin. 0 R/W 000: PE5 I/O (port) 001: TIOC1B I/O (MTU2) 100: A12 output (BSC)* 2 110: TXD1 output (SCI) Other than above: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PE4MD2 0* 1 PE4MD1 0 PE4MD0 1 R/W PE4 Mode 0 R/W Select the function of the PE4/A11/TIOC1A/RXD1 pin. 0 R/W 000: PE4 I/O (port) 001: TIOC1A I/O (MTU2) 100: A11 output (BSC)* 2 110: RXD1 input (SCI) Other than above: Setting prohibited Notes: 1. The initial value is 1 in the on-chip ROM disabled external-extension mode. 2. This function is enabled only in the on-chip ROM enabled/disabled external-extension mode. Do not set 1 in single-chip mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 703 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) * Port E Control Register L1 (PECRL1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - PE3 MD2 PE3 MD1 PE3 MD0 - PE2 MD2 PE2 MD1 PE2 MD0 - PE1 MD2 PE1 MD1 PE1 MD0 - - PE0 MD1 PE0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 PE3MD2 0 R/W PE3 Mode 13 PE3MD1 0 R/W Select the function of the PE3/TIOC0D/SCK0 pin. 12 PE3MD0 0 R/W 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE2MD2 0 R/W PE2 Mode 9 PE2MD1 0 R/W Select the function of the PE2/TIOC0C/TXD0 pin. 8 PE2MD0 0 R/W 000: PE2 I/O (port) 001: TIOC0C I/O (MTU2) 110: TXD0 output (SCI) Other than above: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 704 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 17 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W Description 6 PE1MD2 0 R/W PE1 Mode 5 PE1MD1 0 R/W Select the function of the PE1/TIOC0B/RXD0 pin. 4 PE1MD0 0 R/W 000: PE1 I/O (port) 001: TIOC0B I/O (MTU2) 110: RXD0 input (SCI) Other than above: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 PE0MD1 0 R/W PE0 Mode 0 PE0MD0 0 R/W Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 705 of 964 SH7146 Group Section 17 Pin Function Controller (PFC) 17.1.9 IRQOUT Function Control Register (IFCR) IFCR is a 16-bit readable/writable register that is used to control the IRQOUT pin output when it is selected as the multiplexed pin function by port E control register L4 (PECRL4). When PECRL4 selects another function, the IFCR setting does not affect the pin function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - IRQ MD1 IRQ MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 IRQMD1 0 R/W Port E IRQOUT Pin Function Select 0 IRQMD0 0 R/W Select the IRQOUT pin function when bits 14 to 12 (PE15MD2 to PE15MD0) in PECRL4 are set to B'011. 00: Interrupt request accept signal output 01: Setting prohibited 10: Interrupt request accept signal output 11: Always high-level output Page 706 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 17.2 Section 17 Pin Function Controller (PFC) Usage Notes 1. In this LSI, the same function is available as a multiplexed function on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. If two or more pins are specified for one function, however, there are two cautions shown below. When the pin function is input Signals input to several pins are formed as one signal through OR or AND logic and the signal is transmitted into the LSI. Therefore, a signal that differs from the input signals may be transmitted to the LSI depending on the input signals in other pins that have the same functions. Table 17.13 shows the transmit forms of input functions allocated to several pins. When using one of the functions shown below in multiple pins, use it with care of signal polarity considering the transmit forms. Table 17.13 Transmit Forms of Input Functions Allocated to Multiple Pins OR Type AND Type SCK0 to SCK2, RXD0 to RXD2 IRQ0 to IRQ3, WAIT, POE0, POE1, POE4 to POE5, POE8 OR type: Signals input to several pins are formed as one signal through OR logic and the signal is transmitted into the LSI. AND type: Signals input to several pins are formed as one signal through AND logic and the signal is transmitted into the LSI. When the pin function is output Each selected pin can output the same function. 2. When the port input is switched from a low level to the IRQ edge for the pins that are multiplexed with input/output and IRQ, the corresponding edge is detected. 3. Do not set functions other than those specified in tables 17.9 to 17.11. Otherwise, correct operation cannot be guaranteed. 4. PFC setting in single-chip mode (MCU operating mode 3) In single-chip mode, do not set the PFC to select address bus, data bus, bus control, or the BREQ, BACK, or CK signals. If they are selected, address bus signals function as high- or low-level outputs, data bus signals function as high-impedance outputs, and the other output signals function as high-level outputs. As BREQ and WAIT function as inputs, do not leave them open. However, the bus-mastership-request inputs and external waits are disabled. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 707 of 964 Section 17 Pin Function Controller (PFC) Page 708 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports Section 18 I/O Ports The SH7146 has four ports: A, B, E, and F. Port A is a 16-bit port, port B is a 7-bit port, and port E is a 22-bit port. Port F is a 12-bit input-only port. The SH7149 has five ports: A, B, D, E, and F. Port A is a 16-bit port, port B is a 9-bit port, port D is a 16-bit port, and port E is a 22-bit port. Port F is a 12-bit input-only port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 709 of 964 SH7146 Group Section 18 I/O Ports 18.1 Port A Port A in the SH7146 is an input/output port with the 16 pins shown in figure 18.1. PA15 (I/O)/TXD1 (output) PA14 (I/O)/RXD1 (input) PA13 (I/O)/SCK1 (I/O) PA12 (I/O)/SCK0 (I/O) PA11 (I/O)/TXD0 (output)/ADTRG (input) PA10 (I/O)/RXD0 (input) PA9 (I/O)/TCLKD (input)/POE8 (input)/TXD2 (output) PA8 (I/O)/TCLKC (input)/POE6 (input)/RXD2 (input) Port A PA7 (I/O)/TCLKB (input)/POE5 (input)/SCK2 (I/O) PA6 (I/O)/UBCTRG (output)/TCLKA (input)/POE4 (input) PA5 (I/O)/IRQ3 (input)/SCK1 (I/O) PA4 (I/O)/IRQ2 (input)/TXD1 (output) PA3 (I/O)/IRQ1 (input)/RXD1 (input) PA2 (I/O)/IRQ0 (input)/POE2 (input)/SCK0 (I/O) PA1 (I/O)/POE1 (input)/TXD0 (output) PA0 (I/O)/POE0 (input)/RXD0 (input) Figure 18.1 Port A (SH7146) Page 710 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports Port A in the SH7149 is an input/output port with the 16 pins shown in figure 18.2. PA15 (I/O)/CK (output)/TXD1 (output) PA14 (I/O)/A10 (output)/RXD1 (input) PA13 (I/O)/A9 (output)/SCK1 (I/O) PA12 (I/O)/A8 (output)/SCK0 (I/O) PA11 (I/O)/A7 (output)/TXD0 (output)/ADTRG (input) PA10 (I/O)/A6 (output)/RXD0 (input) PA9 (I/O)/WAIT (input)/TCLKD (input)/POE8 (input)/TXD2 (output) PA8 (I/O)/WRL (output)/TCLKC (input)/POE6 (input)/RXD2 (input) Port A PA7 (I/O)/WRH (output)/TCLKB (input)/POE5 (input)/ SCK2 (I/O) PA6 (I/O)/RD (output)/UBCTRG (output)/TCLKA (input)/POE4 (input) PA5 (I/O)/A5 (output)/IRQ3 (input)/SCK1 (I/O) PA4 (I/O)/A4 (output)/IRQ2 (input)/TXD1 (output) PA3 (I/O)/A3 (output)/IRQ1 (input)/RXD1 (input) PA2 (I/O)/A2 (output)/IRQ0 (input)/POE2 (input)/SCK0 (I/O) PA1 (I/O)/A1 (output)/POE1 (input)/TXD0 (output) PA0 (I/O)/A0 (output)/POE0 (input)/RXD0 (input) Figure 18.2 Port A (SH7149) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 711 of 964 SH7146 Group Section 18 I/O Ports 18.1.1 Register Descriptions Port A is a 16-bit input/output port. Port A has the following registers. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 18.1 Register Configuration Abbreviation Register Name R/W Initial Value Address Access Size Port A data register L PADRL R/W H'0000 H'FFFFD102 8, 16 Port A port register L PAPRL R H'xxxx H'FFFFD11E 8, 16 18.1.2 Port A Data Register L (PADRL) The port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here). When a pin function is general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRL, although that value is written into PADRL, it does not affect the pin state. Table 18.2 summarizes port A data register read/write operations. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA15 DR PA14 DR PA13 DR PA12 DR PA11 DR PA10 DR PA9 DR PA8 DR PA7 DR PA6 DR PA5 DR PA4 DR PA3 DR PA2 DR PA1 DR PA0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 712 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports Bit Bit Name Initial Value R/W Description 15 PA15DR 0 R/W See table 18.2. 14 PA14DR 0 R/W 13 PA13DR 0 R/W 12 PA12DR 0 R/W 11 PA11DR 0 R/W 10 PA10DR 0 R/W 9 PA9DR 0 R/W 8 PA8DR 0 R/W 7 PA7DR 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W Table 18.2 Port A Data Register L (PADRL) Read/Write Operations * PADRL Bits 15 to 0 PAIOR Pin Function Read Write 0 General input Pin state Can write to PADRL, but it has no effect on pin state Other than general input Pin state Can write to PADRL, but it has no effect on pin state General output PADRL value Value written is output from pin Other than general output PADRL value Can write to PADRL, but it has no effect on pin state 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 713 of 964 SH7146 Group Section 18 I/O Ports 18.1.3 Port A Port Register L (PAPRL) The port A port register L (PAPRL) is a 16-bit read-only register that always returns the states of the pins regardless of the PFC setting. Bits PA15PR to PA0PR correspond to pins PA15 to PA0 (multiplexed functions omitted here). Bit: 15 PA15 PR Initial value: * R/W: R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA14 PR PA13 PR PA12 PR PA11 PR PA10 PR PA9 PR PA8 PR PA7 PR PA6 PR PA5 PR PA4 PR PA3 PR PA2 PR PA1 PR PA0 PR * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Bit Bit Name Initial Value 15 PA15PR Pin state R 14 PA14PR Pin state R 13 PA13PR Pin state R 12 PA12PR Pin state R 11 PA11PR Pin state R 10 PA10PR Pin state R 9 PA9PR Pin state R 8 PA8PR Pin state R 7 PA7PR Pin state R 6 PA6PR Pin state R 5 PA5PR Pin state R 4 PA4PR Pin state R 3 PA3PR Pin state R 2 PA2PR Pin state R 1 PA1PR Pin state R 0 PA0PR Pin state R Page 714 of 964 R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 18.2 Section 18 I/O Ports Port B Port B in the SH7146 is an input/output port with the seven pins shown in figure 18.3. PB18 (I/O)/POE8 (input) PB17 (I/O)/POE7 (input) PB16 (I/O)/POE3 (input) Port B PB5 (I/O)/IRQ3 (input)/POE5 (input)/TIC5U (input) PB4 (I/O)/IRQ2 (input)/POE4 (input)/TIC5US (input) PB3 (I/O)/IRQ1 (input)/POE1 (input)/TIC5V (input) PB2 (I/O)/IRQ0 (input)/POE0 (input)/TIC5VS (input) Figure 18.3 Port B (SH7146) Port B in the SH7149 is an input/output port with the nine pins shown in figure 18.4. PB18 (I/O)/POE8 (input) PB17 (I/O)/POE7 (input) PB16 (I/O)/POE3 (input) PB5 (I/O)/A19 (output)/IRQ3 (input)/POE5 (input)/TIC5U (input) Port B PB4 (I/O)/A18 (output)/IRQ2 (input)/POE4 (input)/TIC5US (input) PB3 (I/O)/A17 (output)/IRQ1 (input)/POE1 (input)/TIC5V (input) PB2 (I/O)/A16 (output)/IRQ0 (input)/POE0 (input)/TIC5VS (input) PB1 (I/O)/BREQ (input)/TIC5W (input) PB0 (I/O)/BACK (output)/TIC5WS (input) Figure 18.4 Port B (SH7149) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 715 of 964 SH7146 Group Section 18 I/O Ports 18.2.1 Register Descriptions Port B is a 7-bit input/output port in the SH7146, a 9-bit input/output port in the SH7149. Port B has the following register. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 18.3 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Port B data register H PBDRH R/W H'0000 H'FFFFD180 8, 16, 32 Port B data register L PBDRL R/W H'0000 H'FFFFD182 8, 16 Port B port register H PBPRH R H'000x H'FFFFD19C 8, 16, 32 Port B port register L PBPRL R H'00xx H'FFFFD19E 8, 16 18.2.2 Port B Data Registers H and L (PBDRH and PBDRL) The port B data registers H and L (PBDRH and PBDRL) are 16-bit readable/writable registers that store port B data. Bits PB18DR to PB16DR and PB5DR to PB2DR correspond to pins PB18 to PB16 and PB5 to PB2, respectively (multiplexed functions omitted here) in the SH7146. Bits PB18DR to PB16DR and PB5DR to PB0DR correspond to pins PB18 to PB16 and PB5 to PB0, respectively (multiplexed functions omitted here) in the SH7149. When a pin function is general output, if a value is written to PBDRH or PBDRL, that value is output directly from the pin, and if PBDRH or PBDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PBDRH or PBDRL is read, the pin state, not the register value, is returned directly. If a value is written to PBDRH or PBDRL, although that value is written into PBDRH or PBDRL, it does not affect the pin state. Table 18.4 summarizes port B data register read/write operations. Page 716 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports * PBDRH Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - PB18 DR PB17 DR PB16 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15 to 3 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 2 PB18DR 0 R/W 1 PB17DR 0 R/W 0 PB16DR 0 R/W See table 18.4. * PBDRL (SH7146) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - - - - - - - - - PB5 DR PB4 DR PB3 DR PB2 DR - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R Bit Bit Name Initial Value R/W 15 to 6 -- All 0 R 0 Description Reserved These bits are always read as 0. The write value should always be 0. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1, 0 -- All 0 R See table 18.4. Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 717 of 964 SH7146 Group Section 18 I/O Ports * PBDRL (SH7149) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PB5 DR PB4 DR PB3 DR PB2 DR PB1 DR PB0 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15 to 6 -- All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W See table 18.4. Table 18.4 Port B Data Register (PBDR) Read/Write Operations * PBDRH Bits 2 to 0 and PBDRL Bits 9 to 0 PBIOR Pin Function Read Write 0 General input Pin state Can write to PBDRH and PBDRL, but it has no effect on pin state Other than general input Pin state Can write to PBDRH and PBDRL, but it has no effect on pin state General output PBDRH or PBDRL value Value written is output from pin Other than general output PBDRH or PBDRL value Can write to PBDRH and PBDRL, but it has no effect on pin state 1 Page 718 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 18.2.3 Section 18 I/O Ports Port B Port Registers H and L (PBPRH and PBPRL) The port B port registers H and L (PBPRH and PBPRL) are 16-bit read-only registers that always return the states of the pins regardless of the PFC setting. Bits PB18PR to PB16PR and PB5PR to PB2PR correspond to pins PB18 to PB16 and PB5 to PB2, respectively (multiplexed functions omitted here) in the SH7146. Bits PB18PR to PB16PR and PB5PR to PB0PR correspond to pins PB18 to PB16 and PB5 to PB0, respectively (multiplexed functions omitted here) in the SH7149. * PBPRH Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - PB18 PR PB17 PR PB16 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R * R * R Bit Bit Name Initial Value R/W 15 to 3 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 2 PB18PR Pin state R 1 PB17PR Pin state R 0 PB16PR Pin state R R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 The pin state is returned regardless of the PFC setting. These bits cannot be modified. Page 719 of 964 SH7146 Group Section 18 I/O Ports * PBPRL (SH7146) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - - - - - - - - - PB5 PR PB4 PR PB3 PR PB2 PR - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R * R * R * R 0 R 0 R Bit Bit Name Initial Value R/W 15 to 6 All 0 R 0 Description Reserved These bits are always read as 0. The write value should always be 0. 5 PB5PR Pin state R 4 PB4PR Pin state R 3 PB3PR Pin state R 2 PB2PR Pin state R 1, 0 All 0 The pin state is returned regardless of the PFC setting. These bits cannot be modified. R Reserved These bits are always read as 0. The write value should always be 0. * PBPRL (SH7149) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PB5 PR PB4 PR PB3 PR PB2 PR PB1 PR PB0 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R * R * R * R * R * R Bit Bit Name Initial Value R/W 15 to 6 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 5 PB5PR Pin state R 4 PB4PR Pin state R 3 PB3PR Pin state R 2 PB2PR Pin state R 1 PB1PR Pin state R 0 PB0PR Pin state R Page 720 of 964 The pin state is returned regardless of the PFC setting. These bits cannot be modified. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 18.3 Section 18 I/O Ports Port D (SH7149 Only) Port D in the SH7149 is an input/output port with the 16 pins shown in figure 18.5. PD15 (I/O)/D15 (I/O)/AUDSYNC (output)* PD14 (I/O)/D14 (I/O)/AUDCK (output)* PD13 (I/O)/D13 (I/O) PD12 (I/O)/D12 (I/O) PD11 (I/O)/D11 (I/O)/AUDATA3 (output)* PD10 (I/O)/ D10 (I/O)/AUDATA2 (output)* PD9 (I/O)/D9 (I/O)/AUDATA1 (output)* Port D PD8 (I/O)/D8 (I/O)/SCK2 (I/O)/AUDATA0 (output)* PD7 (I/O)/D7 (I/O)/IRQ3 (input)/TXD2 (output) PD6 (I/O)/D6 (I/O)/IRQ2 (input)/RXD2 (input) PD5 (I/O)/D5 (I/O)/IRQ1 (input)/SCK1 (I/O) PD4 (I/O)/D4 (I/O)/IRQ0 (input)/TXD1 (output) PD3 (I/O)/D3 (I/O)/RXD1 (input) PD2 (I/O)/D2 (I/O)/SCK0 (I/O) PD1 (I/O)/D1 (I/O)/TXD0 (output) PD0 (I/O)/D0 (I/O)/RXD0 (input) Note: * Only in F-ZTAT version supporting full functions of E10A. Figure 18.5 Port D R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 721 of 964 SH7146 Group Section 18 I/O Ports 18.3.1 Register Descriptions Port D is a 16-bit input/output port. Note that port D is not available in the SH7146. Port D has the following registers. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 18.5 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Port D data register L PDDRL R/W H'0000 H'FFFFD282 8, 16 Port D port register L PDPRL R H'xxxx H'FFFFD29E 8, 16 18.3.2 Port D Data Register L (PDDRL) The port D data register L (PDDRL) is a 16-bit readable/writable register that stores port D data. Bits PD15DR to PD0DR correspond to pins PD15 to PD0 (multiplexed functions omitted here). When a pin function is general output, if a value is written to PDDRL, that value is output directly from the pin, and if PDDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PDDRL is read, the pin state, not the register value, is returned directly. If a value is written to PDDRL, although that value is written into PDDRL, it does not affect the pin state. Table 18.6 summarizes port D data register read/write operations. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 DR PD14 DR PD13 DR PD12 DR PD11 DR PD10 DR PD9 DR PD8 DR PD7 DR PD6 DR PD5 DR PD4 DR PD3 DR PD2 DR PD1 DR PD0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 722 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports Bit Bit Name Initial Value R/W Description 15 PD15DR 0 R/W See table 18.6. 14 PD14DR 0 R/W 13 PD13DR 0 R/W 12 PD12DR 0 R/W 11 PD11DR 0 R/W 10 PD10DR 0 R/W 9 PD9DR 0 R/W 8 PD8DR 0 R/W 7 PD7DR 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W Table 18.6 Port D Data Register L (PDDRL) Read/Write Operations * PDDRL Bits 15 to 0 PDIOR Pin Function Read Write 0 General input Pin state Can write to PDDRL, but it has no effect on pin state Other than general input Pin state Can write to PDDRL, but it has no effect on pin state General output PDDRL value Value written is output from pin Other than general output PDDRL value Can write to PDDRL, but it has no effect on pin state 1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 723 of 964 SH7146 Group Section 18 I/O Ports 18.3.3 Port D Port Register L (PDPRL) The port D port register L (PDPRL) is a 16-bit read-only register that always returns the states of the pins regardless of the PFC setting. Bits PD15PR to PD0PR correspond to pins PD15 to PD0 (multiplexed functions omitted here). Bit: 15 PD15 PR Initial value: * R/W: R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD14 PR PD13 PR PD12 PR PD11 PR PD10 PR PD9 PR PD8 PR PD7 PR PD6 PR PD5 PR PD4 PR PD3 PR PD2 PR PD1 PR PD0 PR * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Bit Bit Name Initial Value 15 PD15PR Pin state R 14 PD14PR Pin state R 13 PD13PR Pin state R 12 PD12PR Pin state R 11 PD11PR Pin state R 10 PD10PR Pin state R 9 PD9PR Pin state R 8 PD8PR Pin state R 7 PD7PR Pin state R 6 PD6PR Pin state R 5 PD5PR Pin state R 4 PD4PR Pin state R 3 PD3PR Pin state R 2 PD2PR Pin state R 1 PD1PR Pin state R 0 PD0PR Pin state R Page 724 of 964 R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 18.4 Section 18 I/O Ports Port E Port E in the SH7146 is an input/output port with the 22 pins shown in figure 18.6. PE21 (I/O)/TIOC4DS (I/O)/TRST (input)* PE20 (I/O)/TIOC4CS (I/O)/TMS (input)* PE19 (I/O)/TIOC4BS (I/O)/TDO (output)* PE18 (I/O)/TIOC4AS (I/O)/TDI (input)* PE17 (I/O)/TIOC3DS (I/O)/TCK (input)* PE16 (I/O)/TIOC3BS (I/O)/ASEBRKAK (output)*/ASEBRK (input)* PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O) PE13 (I/O)/TIOC4B (I/O)/MRES (input) PE12 (I/O)/TIOC4A (I/O) PE11 (I/O)/TIOC3D (I/O) Port E PE10 (I/O)/TIOC3C (I/O) PE9 (I/O)/TIOC3B (I/O) PE8 (I/O)/TIOC3A (I/O) PE7 (I/O)/TIOC2B (I/O) PE6 (I/O)/TIOC2A (I/O)/SCK1 (I/O) PE5 (I/O)/TIOC1B (I/O)/TXD1 (output) PE4 (I/O)/TIOC1A (I/O)/RXD1 (input) PE3 (I/O)/TIOC0D (I/O)/SCK0 (I/O) PE2 (I/O)/TIOC0C (I/O)/TXD0 (output) PE1 (I/O)/TIOC0B (I/O)/RXD0 (input) PE0 (I/O)/TIOC0A (I/O) Note: * Supported only by the F-ZTAT version. Figure 18.6 Port E (SH7146) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 725 of 964 SH7146 Group Section 18 I/O Ports Port E in the SH7149 is an input/output port with the 22 pins shown in figure 18.7. PE21 (I/O)/WRL (output)/TIOC4DS (I/O)/TRST (input)* PE20 (I/O)/WRH (output)/TIOC4CS (I/O)/TMS (input)* PE19 (I/O)/RD (output)/TIOC4BS (I/O)/TDO (output)* PE18 (I/O)/CS1 (output)/TIOC4AS (I/O)/TDI (input)* PE17 (I/O)/CS0 (output)/TIOC3DS (I/O)/TCK (input)* PE16 (I/O)/WAIT (input)/TIOC3BS (I/O)/ASEBRKAK (output)*/ASEBRK (input)* PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O) PE13 (I/O)/TIOC4B (I/O)/MRES (input) PE12 (I/O)/TIOC4A (I/O) PE11 (I/O)/TIOC3D (I/O) Port E PE10 (I/O)/CS0 (output)/TIOC3C (I/O) PE9 (I/O)/TIOC3B (I/O) PE8 (I/O)/A15 (output)/TIOC3A (I/O) PE7 (I/O)/A14 (output)/TIOC2B (I/O) PE6 (I/O)/A13 (output)/TIOC2A (I/O)/SCK1 (I/O) PE5 (I/O)/A12 (output)/TIOC1B (I/O)/TXD1 (output) PE4 (I/O)/A11 (output)/TIOC1A (I/O)/RXD1 (input) PE3 (I/O)/TIOC0D (I/O)/SCK0 (I/O) PE2 (I/O)/TIOC0C (I/O)/TXD0 (output) PE1 (I/O)/TIOC0B (I/O)/RXD0 (input) PE0 (I/O)/TIOC0A (I/O) Note: * Supported only by the F-ZTAT version. Figure 18.7 Port E (SH7149) Page 726 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 18.4.1 Section 18 I/O Ports Register Descriptions Port E is a 22-bit input/output port. Port E has the following registers. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 18.7 Register Configuration Register Name Abbreviation Port E data register H PEDRH R/W H'0000 H'FFFFD300 8, 16, 32 Port E data register L PEDRL R/W H'0000 H'FFFFD302 8, 16 Port E port register H PEPRH R H'00xx H'FFFFD31C 8, 16, 32 Port E port register L PEPRL R H'00xx H'FFFFD31E 8, 16 18.4.2 R/W Initial Value Address Access Size Port E Data Registers H and L (PEDRH and PEDRL) The port E data registers H and L (PEDRH and PEDRL) are 16-bit readable/writable registers that store port E data. Bits PE21DR to PE0DR correspond to pins PE21 to PE0, respectively (multiplexed functions omitted here). When a pin function is general output, if a value is written to PEDRH or PEDRL, that value is output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PEDRH or PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is written into PEDRH or PEDRL, it does not affect the pin state. Table 18.8 summarizes port E data register read/write operations. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 727 of 964 SH7146 Group Section 18 I/O Ports * PEDRH Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PE21 DR PE20 DR PE19 DR PE18 DR PE17 DR PE16 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15 to 6 All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 5 PE21DR 0 R/W 4 PE20DR 0 R/W 3 PE19DR 0 R/W 2 PE18DR 0 R/W 1 PE17DR 0 R/W 0 PE16DR 0 R/W Page 728 of 964 See table 18.8. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports * PEDRL Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 DR PE8 DR PE7 DR PE6 DR PE5 DR PE4 DR PE3 DR PE2 DR PE1 DR PE0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 PE15DR 0 R/W See table 18.8. 14 PE14DR 0 R/W 13 PE13DR 0 R/W 12 PE12DR 0 R/W 11 PE11DR 0 R/W 10 PE10DR 0 R/W 9 PE9DR 0 R/W 8 PE8DR 0 R/W 7 PE7DR 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 729 of 964 SH7146 Group Section 18 I/O Ports Table 18.8 Port E Data Register (PEDR) Read/Write Operations * PEDRH Bits 5 to 0 and PEDRL Bits 15 to 0 PEIOR Pin Function Read Write 0 General input Pin state Can write to PEDRH and PEDRL, but it has no effect on pin state Other than general input Pin state Can write to PEDRH and PEDRL, but it has no effect on pin state General output PEDRH or PEDRL value Value written is output from pin Other than general output PEDRH or PEDRL value Can write to PEDRH and PEDRL, but it has no effect on pin state 1 18.4.3 Port E Port Registers H and L (PEPRH and PEPRL) The port E port registers H and L (PEPRH and PEPRL) are 16-bit read-only registers that always return the states of the pins regardless of the PFC setting. Bits PE21PR to PE0PR correspond to pins PE21 to PE0, respectively (multiplexed functions omitted here). * PEPRH Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - PE21 PR PE20 PR PE19 PR PE18 PR PE17 PR PE16 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R * R * R * R * R * R Bit Bit Name Initial Value R/W Description 15 to 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PE21PR Pin state R 4 PE20PR Pin state R 3 PE19PR Pin state R 2 PE18PR Pin state R 1 PE17PR Pin state R 0 PE16PR Pin state R Page 730 of 964 The pin state is returned regardless of the PFC setting. These bits cannot be modified. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 18 I/O Ports * PEPRL Bit: 15 PE15 PR Initial value: * R/W: R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE14 PR PE13 PR PE12 PR PE11 PR PE10 PR PE9 PR PE8 PR PE7 PR PE6 PR PE5 PR PE4 PR PE3 PR PE2 PR PE1 PR PE0 PR * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Bit Bit Name Initial Value 15 PE15PR Pin state R 14 PE14PR Pin state R 13 PE13PR Pin state R 12 PE12PR Pin state R 11 PE11PR Pin state R 10 PE10PR Pin state R 9 PE9PR Pin state R 8 PE8PR Pin state R 7 PE7PR Pin state R 6 PE6PR Pin state R 5 PE5PR Pin state R 4 PE4PR Pin state R 3 PE3PR Pin state R 2 PE2PR Pin state R 1 PE1PR Pin state R 0 PE0PR Pin state R R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Page 731 of 964 SH7146 Group Section 18 I/O Ports 18.5 Port F Port F is an input-only port with the 12 pins shown in figure 18.8. PF15 (input)/AN15 (input) PF14 (input)/AN14 (input) PF13 (input)/AN13 (input) PF12 (input)/AN12 (input) PF11 (input)/AN11 (input) PF10 (input)/AN10 (input) Port F PF9 (input)/AN9 (input) PF8 (input)/AN8 (input) PF6 (input)/AN6 (input) PF4 (input)/AN4 (input) PF2 (input)/AN2 (input) PF0 (input)/AN0 (input) Figure 18.8 Port F Page 732 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 18.5.1 Section 18 I/O Ports Register Descriptions Port F is a 12-bit input-only port. Port F has the following register. For details on register addresses and register states during each processing, refer to section 23, List of Registers. Table 18.9 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Port F data register L PFDRL R H'xxxx H'FFFFD382 8, 16 18.5.2 Port F Data Register L (PFDRL) The port F data register L (PFDRL) is a 16-bit read-only register that stores port F data. Bits PF15DR to PF8DR, PF6DR, PF4DR, PF2DR, and PF0DR correspond to pins PF15 to PF8, PF6, PF4, PF2, and PF0, respectively (multiplexed functions omitted here). Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read out. Table 18.10 summarizes port F data register L read/write operations. Bit: 15 PF15 DR Initial value: * R/W: R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF14 DR PF13 DR PF12 DR PF11 DR PF10 DR PF9 DR PF8 DR - PF6 DR - PF4 DR - PF2 DR - PF0 DR * R * R * R * R * R * R * R 0 R * R 0 R * R 0 R * R 0 R * R R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 733 of 964 SH7146 Group Section 18 I/O Ports Bit Bit Name Initial Value 15 PF15DR Pin state R 14 PF14DR Pin state R 13 PF13DR Pin state R 12 PF12DR Pin state R 11 PF11DR Pin state R 10 PF10DR Pin state R 9 PF9DR Pin state R 8 PF8DR Pin state R 7 0 R/W R Description See table 18.10. Reserved This bit is always read as 0. The write value should always be 0. 6 PF6DR Pin state R See table 18.10. 5 0 Reserved R This bit is always read as 0. The write value should always be 0. 4 PF4DR Pin state R See table 18.10. 3 0 Reserved R This bit is always read as 0. The write value should always be 0. 2 PF2DR Pin state R See table 18.10. 1 0 Reserved R This bit is always read as 0. The write value should always be 0. 0 PF0DR Pin state R See table 18.10. Table 18.10 Port F Data Register L (PFDRL) Read/Write Operations * PFDRL Bits 15 to 0 Pin Function Read Write General input Pin state Ignored (no effect on pin state) ANn input (analog input) 1 Ignored (no effect on pin state) Page 734 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Section 19 Flash Memory This LSI has 256-kbyte on-chip flash memory. The flash memory has the following features. 19.1 Features * Two flash-memory MATs, with one selected by the mode in which the LSI starts up The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting when the LSI starts up determines the memory MAT that is currently mapped. The MAT can be switched by bank-switching after the LSI has started up. Size of the user MAT, from which booting-up proceeds after a power-on reset in user mode: 256 kbytes Size of the user boot MAT, from which booting-up proceeds after a power-on reset in user boot mode: 12 kbytes * Three on-board programming modes and one off-board programming mode On-board programming modes Boot Mode: The on-chip SCI interface is used for programming in this mode. Either the user MAT or user-boot MAT can be programmed, and the bit rate for data transfer between the host and this LSI are automatically adjusted. User Program Mode: This mode allows programming of the user MAT via any desired interface. User Boot Mode: This mode allows writing of a user boot program via any desired interface and programming of the user MAT. Off-board programming mode Programmer Mode: This mode allows programming of the user MAT and user boot MAT with the aid of a PROM programmer. * Downloading of an on-chip program to provide an interface for programming/erasure This LSI has a dedicated programming/erasing program. After this program has been downloaded to the on-chip RAM, programming or erasing can be performed by setting parameters as arguments. "User branching" is also supported. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 735 of 964 SH7146 Group Section 19 Flash Memory User branching Programming is performed in 128-byte units. Each round of programming consists of application of the programming pulse, reading for verification, and several other steps. Erasing is performed in block units and each round of erasing consists of several steps. A userprocessing routine can be executed between each round of erasing, and making the setting for this is called the addition of a user branch. * Using on-chip RAM to emulate flash memory By laying on-chip RAM over part of the flash memory, flash-memory programming can be emulated in real time. * Protection modes There are two modes of protection: software protection is applied by register settings and hardware protection is applied by the level on the FWE pin. Protection of the flash memory from programming or erasure can be selected. When an abnormal state is detected, such as runaway execution of programming/erasing, the protection modes initiate the transition to the error protection state and suspend programming/erasing processing. * Programming/erasing time The time taken to program 128 bytes of flash memory in a single round is tP ms (typ.), which is equivalent to tP/128 ms per byte. The erasing time is tEs (typ.) per block. * Number of programming operations The flash memory can be programmed up to NWEC times. * Operating frequency for programming/erasing The operating frequency for programming/erasing is a maximum of 40 MHz (P). Page 736 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory 19.2 Overview 19.2.1 Block Diagram Internal address bus Internal data bus (32 bits) FCCS FPCS Module bus FECS FKEY Memory MAT unit Control unit FMATS User MAT: 256 kbytes User boot MAT: 12 kbytes FTDAR RAMER Flash memory FWE pin Mode pins Operating mode [Legend] FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMER: Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register Figure 19.1 Block Diagram of Flash Memory R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 737 of 964 SH7146 Group Section 19 Flash Memory 19.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 19.2. For the setting of each mode pin and the FWE pin, see table 19.1. * Flash memory cannot be read, programmed, or erased in ROM invalid mode. The programming/erasing interface registers cannot be written to. When these registers are read, H'00 is always read. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode. RES = 0 RES = 0 ROM invalid mode ROM invalid mode setting S RE S= Bo =0 Us RE e d mo =0 ing tt se Us mo er p de rog se ram ttin g 0 S RE er = ot g bo tin er set Us de mo S RE Programmer mode Programmer mode setting Reset state ot mo de 0 se ttin g FWE = 0 User mode FWE = 1 User program mode User boot mode Boot mode RAM emulation is enabled On-board programming mode Figure 19.2 Mode Transition of Flash Memory Page 738 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Table 19.1 (1) Relationship between FWE and MD Pins and Operating Modes (SH7146) Pin Reset State User Mode User Program Mode Boot Mode RES 0 1 1 1 FWE 0/1 0 1 1 MD1 0/1 1 1 0 Programmer Mode Setting value depends on the condition of the specialized PROM programmer. Note: External bus extended mode and user boot mode are not supported by the SH7146. Table 19.1 (2) Relationship between FWE and MD Pins and Operating Modes (SH7149) Pin Reset State ROM Invalid Mode User Mode User Program Mode User Boot Mode Boot Mode Programmer Mode RES 0 1 1 1 1 1 FWE 0/1 0 1 1 1 0 0 0 Setting value depends on the condition of the specialized PROM programmer. MD0 0/1 0/1* MD1 0/1 0 0 1 0/1* 1 1 2 0/1* 1 2 Notes: 1. MD0 = 0: 8-bit external bus, MD0 = 1: 16-bit external bus 2. MD0 = 0: External bus can be used, MD0 = 1: Single-chip mode (external bus cannot be used) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 739 of 964 SH7146 Group Section 19 Flash Memory 19.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 19.2. Table 19.2 Comparison of Programming Modes Boot Mode User Program Mode Programmer User Boot Mode Mode Programming/ On-board programming erasing environment Off-board programming Programming/ erasing enable MAT User MAT User boot MAT User MAT User MAT User MAT User boot MAT Programming/ erasing control Command method Programming/ erasing interface Programming/ erasing interface -- All erasure Possible (Automatic) Possible Possible Possible (Automatic) Block division erasure Possible* Possible Possible Not possible Program data transfer From host via SCI From optional device via RAM From optional device via RAM Via programmer Not possible 1 User branch function Not possible Possible Possible RAM emulation Possible Not possible Not possible Reset initiation MAT Embedded program storage MAT User MAT Transition to user mode Mode setting FWE setting change and reset change Not possible User boot MAT* 2 Embedded program storage MAT Mode setting -- change and reset Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. Initiation starts from the embedded program storage MAT. After checking the flashmemory related registers, initiation starts from the reset vector of the user MAT. * The user boot MAT can be programmed or erased only in boot mode and programmer mode. * The user MAT and user boot MAT are all erased in boot mode. Then, the user MAT and user boot MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Only user boot MAT is programmed and the user MAT is programmed in user boot mode or only user MAT is programmed because user boot mode is not used. * In user boot mode, the boot operation of the optional interface can be performed by a mode pin setting different from user program mode. Page 740 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 19.2.4 Section 19 Flash Memory Flash Memory Configuration This LSI's flash memory is configured by the 256-kbyte user MAT and 12-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between the two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However, the user boot MAT can be programmed only in boot mode and programmer mode. <User MAT> Address H'00000000 <User Boot MAT> Address H'00000000 12 kbytes Address H'00002FFF 256 kbytes Address H'0003FFFF Figure 19.3 Flash Memory Configuration The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 12 kbytes or more. When a user boot MAT exceeding 12 kbytes is read from, an undefined value is read. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 741 of 964 SH7146 Group Section 19 Flash Memory 19.2.5 Block Division The user MAT is divided into 64 kbytes (three blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 19.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB11 is specified when erasing. The RAM emulation can be performed in the eight blocks of 4 kbytes. < User MAT > Address H'00000000 Erase block EB0 4 kbytes x 8 to * 256KB EB7 32 kbytes EB8 64 kbytes EB9 64 kbytes EB10 64 kbytes EB11 Last address H'0003FFFF Note: * RAM emulation can be performed in the eight 4-kbyte blocks. Figure 19.4 Block Division of User MAT 19.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode and user boot mode. The overview of the procedure is as follows. For details, see section 19.5.2, User Program Mode. Page 742 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Start user procedure program for programming/erasing. Select on-chip program to be downloaded and set download destination Download on-chip program by setting VBR, FKEY, and SCO bits. Initialization execution (on-chip program execution) Programming (in 128-byte units) or erasing (in one-block units) (on-chip program execution) No Programming/ erasing completed? Yes End user procedure program Figure 19.5 Overview of User Procedure Program (1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface registers. The download destination can be specified by FTDAR. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 743 of 964 Section 19 Flash Memory SH7146 Group (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'84000000 and then setting the SCO bit in the flash code control and status register (FCCS) and the flash key code register (FKEY), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Note that VBR can be changed after download is completed. (3) Initialization of Programming/Erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be in an area other than the user MAT area which is in the middle of programming and the area where the on-chip program is downloaded. These settings are performed by using the programming/erasing interface parameters. (4) Programming/Erasing Execution To program or erase, the FWE pin must be brought high and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameters and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. There are limitations and notes on the interrupt processing during programming/erasing. For details, see section 19.8.2, Interrupts during Programming/Erasing. (5) When Programming/Erasing is Executed Consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. Page 744 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 19.3 Section 19 Flash Memory Input/Output Pins Flash memory is controlled by the pins as shown in table 19.3. Table 19.3 Pin Configuration Name Pin Name Input/Output Function Power-on reset RES Input Reset Flash programming enable FWE Input Hardware protection when programming flash memory Mode 1 MD1 Input Sets operating mode of this LSI Mode 0* MD0 Input Sets operating mode of this LSI Transmit data TXD1 (PA4) Output Serial transmit data output (used in boot mode) Receive data RXD1 (PA3) Input Serial receive data input (used in boot mode) Note: The SH7146 does not have the MD0 pin. * 19.4 Register Descriptions 19.4.1 Registers The registers/parameters which control flash memory when the on-chip flash memory is valid are shown in table 19.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 19.5. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 745 of 964 SH7146 Group Section 19 Flash Memory Table 19.4 (1) Register Configuration Address Access Size H'00* 2 H'80* H'FFFFCC00 8 R/W H'00 H'FFFFCC01 8 FECS R/W H'00 H'FFFFCC02 8 FKEY R/W H'00 H'FFFFCC04 8 4 Register Name Abbreviation* Flash code control and status register FCCS R, W* Flash program code select register FPCS Flash erase code select register Flash key code register Initial Value R/W 1 2 3 Flash MAT select register FMATS R/W H'00* 3 H'AA* H'FFFFCC05 8 Flash transfer destination address register FTDAR R/W H'00 H'FFFFCC06 8 RAM emulation register RAMER R/W H'0000 H'FFFFF108 16 Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value that can be read is always 0.) 2. The initial value of the FWE bit is 0 when the FWE pin goes low. The initial value of the FWE bit is 1 when the FWE pin goes high. 3. The initial value at initiation in user mode or user program mode is H'00. The initial value at initiation in user boot mode is H'AA. 4. All registers except for RAMER can be accessed only in bytes. RAMER can be accessed in bytes or words. Table 19.4 (2) Parameter Configuration Name Abbreviation R/W Initial Value Address Download pass/fail result DPFR R/W Undefined On-chip RAM* 8, 16, 32 Flash pass/fail result FPFR R/W Undefined R0 of CPU 8, 16, 32 Flash multipurpose address area FMPAR R/W Undefined R5 of CPU 8, 16, 32 Flash multipurpose data destination area FMPDR R/W Undefined R4 of CPU 8, 16, 32 Flash erase block select FEBS R/W Undefined R4 of CPU 8, 16, 32 Flash program and erase frequency control FPEFEQ R/W Undefined R4 of CPU 8, 16, 32 Flash user branch address set parameter FUBRA R/W Undefined R5 of CPU 8, 16, 32 Note: * Access Size One byte of the start address in the on-chip RAM area specified by FTDAR is valid. Page 746 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Table 19.5 Register/Parameter and Target Mode InitialiDownload zation Programming Erasure Read RAM Emulation Programming/ FCCS erasing interface FPCS registers PECS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FKEY -- * -- -- -- * FTDAR -- -- -- -- -- 1 * -- FMATS 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- FUBRA -- -- -- -- -- FMPAR -- -- -- -- -- FMPDR -- -- -- -- -- FEBS -- -- -- -- -- RAMER -- -- -- -- -- Programming/ DPFR erasing interface FPFR parameters FPEFEQ RAM emulation 1 Notes: 1. The setting is required when programming or erasing user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 747 of 964 SH7146 Group Section 19 Flash Memory 19.4.2 Programming/Erasing Interface Registers The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Bit: 7 6 5 4 3 2 1 0 FWE MAT - FLER - - - SCO 1/0 R 0 R 0 R 0 R 0 R 0 R 0 (R)/W Initial value: 1/0 R/W: R Bit Bit Name Initial Value R/W 7 FWE 1/0 R Description Flash Programming Enable Monitors the level, which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. 0: When the FWE pin goes low (in hardware protection state) 1: When the FWE pin goes high 6 MAT 1/0 R MAT Bit Indicates whether the user MAT or user boot MAT is selected. 0: User MAT is selected 1: User boot MAT is selected 5 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 748 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value R/W Description 4 FLER 0 R Flash Memory Error Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset signal must be released after the reset period of 100 s, which is longer than normal. 0: Flash memory operates normally Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset 1: Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 19.6.3, Error Protection. 3 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 749 of 964 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value R/W Description 0 SCO 0 (R)/W Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation must be in the on-chip RAM. Four NOP instructions must be executed immediately after setting this bit to 1. For interrupts during download, see section 19.8.2, Interrupts during Programming/Erasing. For the download time, see section 19.8.3, Other Notes. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on-chip program storage area. Therefore, before issuing a download request (SCO = 1), set VBR to H'84000000. Otherwise, the CPU gets out of control. Once download end is confirmed, VBR can be changed to any other value. The mode in which the FWE pin is high must be used when using the SCO function. 0: Download of the on-chip programming/erasing program to the on-chip RAM is not executed. [Clearing condition] When download is completed 1: Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is generated [Setting conditions] When all of the following conditions are satisfied and 1 is written to this bit Page 750 of 964 * FKEY is written to H'A5 * During execution in the on-chip RAM * Not in RAM emulation mode (RAMS in RAMCR = 0) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - PPVS 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PPVS 0 R/W Program Pulse Single Selects the programming program. 0: On-chip programming program is not selected [Clearing condition] When transfer is completed 1: On-chip programming program is selected (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - EPVB 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 751 of 964 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value R/W Description 0 EPVB 0 R/W Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected [Clearing condition] When transfer is completed 1: On-chip erasing program is selected (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the on-chip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written. Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W K[7:0] Initial value: 0 R/W: R/W Bit Bit Name Initial Value R/W 7 to 0 K[7:0] All 0 R/W 0 R/W 0 R/W 0 R/W Description Key Code Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing of flash memory can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. H'A5: Writing to the SCO bit is enabled (The SCO bit cannot be set by a value other than H'A5.) H'5A: Programming/erasing is enabled (A value other than H'5A enables software protection state.) H'00: Initial value Page 752 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (5) Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit: 7 6 5 4 3 2 1 0 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 Initial value: 0/1 R/W: R/W 0 R/W 0/1 R/W 0 R/W 0/1 R/W 0 R/W 0/1 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 MS7 0/1 R/W MAT Select 6 MS6 0 R/W 5 MS5 0/1 R/W 4 MS4 0 R/W These bits are in user-MAT selection state when a value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. 3 MS3 0/1 R/W 2 MS2 0 R/W 1 MS1 0/1 R/W 0 MS0 0 R/W The MAT is switched by writing a value in FMATS with the on-chip RAM instrunction. When the MAT is switched, follow section 19.8.1, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user program mode if user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or in programmer mode.) H'AA: The user boot MAT is selected (in user-MAT selection state when the value of these bits are other than H'AA) Initial value when these bits are initiated in user boot mode. H'00: Initial value when these bits are initiated in a mode except for user boot mode (in user-MAT selection state) [Programmable condition] These bits are in the execution state in the on-chip RAM. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 753 of 964 SH7146 Group Section 19 Flash Memory (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFF9000) in on-chip RAM. Bit: 7 6 5 4 TDER Initial value: 0 R/W: R/W 3 2 1 0 0 R/W 0 R/W 0 R/W TDA[6:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 TDER 0 R/W Transfer Destination Address Setting Error This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is tested by checking whether the setting of TDA6 to TDA0 is in the range of H'00 to H'02 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'02 as well as clearing this bit to 0. 0: Setting of TDA6 to TDA0 is normal 1: Setting of TDER and TDA6 to TDA0 is H'03 to H'FF and download has been aborted 6 to 0 TDA[6:0] All 0 R/W Transfer Destination Address These bits specify the download start address. A value from H'00 to H'02 can be set to specify the download start address in on-chip RAM in 2-kbyte units. A value from H'03 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. H'00: Download start address is set to H'FFFF9000 H'01: Download start address is set to H'FFFF9800 H'02: Download start address is set to H'FFFFA000 H'03 to H'7F: Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. Page 754 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 19.4.3 Section 19 Flash Memory Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined. At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters are used in the following four items. 1. Download control 2. Initialization before programming or erasing 3. Programming 4. Erasing These items use different parameters. The correspondence table is shown in table 19.6. The processing results of initialization, programming, and erasing are returned, but the bit contents have different meanings according to the processing program. See the description of FPFR for each processing. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 755 of 964 SH7146 Group Section 19 Flash Memory Table 19.6 Usable Parameters and Target Modes Name of Parameter ProAbbrevia- Down- Initiali- gramtion load zation ming Erasure R/W Initial Value Allocation Download pass/fail DPFR result -- -- -- R/W Undefined On-chip RAM* Flash pass/fail result FPFR -- R/W Undefined R0 of CPU Flash programming/ erasing frequency control FPEFEQ -- -- -- R/W Undefined R4 of CPU Flash user branch address set FUBRA -- -- -- R/W Undefined R5 of CPU Flash multipurpose FMPAR address area -- -- -- R/W Undefined R5 of CPU Flash multipurpose FMPDR data destination area -- -- -- R/W Undefined R4 of CPU Flash erase block select -- -- -- R/W Undefined R4 of CPU Note: * FEBS One byte of start address of download destination specified by FTDAR (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 3 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 19.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For the checking method of download results, see section 19.5.2 (2), Programming Procedure in User Program Mode. Page 756 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Bit: 7 6 5 4 3 2 1 0 - - - - - SS FK SF R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: R/W Bit Bit Name Initial Value 7 to 3 Undefined R/W R/W Description Unused Return 0. 2 SS Undefined R/W Source Select Error Detect The on-chip program which can be downloaded can be specified as only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs. 0: Download program can be selected normally 1: Download error occurs (Multi-selection or program which is not mapped is selected) 1 FK Undefined R/W Flash Key Register Error Detect Returns the check result whether the value of FKEY is set to H'A5. 0: FKEY setting is normal (FKEY = H'A5) 1: FKEY setting is abnormal (FKEY = value other than H'A5) 0 SF Undefined R/W Success/Fail Returns the result whether download has ended normally or not. 0: Downloading on-chip program has ended normally (no error) 1: Downloading on-chip program has ended abnormally (error occurs) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 757 of 964 SH7146 Group Section 19 Flash Memory (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see table 24.4, Maximum Operating Frequency. Bit: 31 - Initial value: R/W: R/W 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - 16 - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Page 758 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value 31 to 16 Undefined R/W R/W Description Unused Return 0. 15 to 0 F15 to F0 Undefined R/W Frequency Set Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4). For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows. The number to three decimal places of 28.882 is rounded and the value is thus 28.88. The formula that 28.88 x 100 = 2888 is converted to the binary digit and B'0000, B'1011, B'0100, B'1000 (H'0B48) is set to B'R4. (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UA31 UA30 UA29 UA28 UA27 UA26 UA25 UA24 UA23 UA22 UA21 UA20 UA19 UA18 UA17 UA16 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UA15 UA14 UA13 UA12 UA11 UA10 UA9 UA8 UA7 UA6 UA5 UA4 UA3 UA2 UA1 UA0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 759 of 964 SH7146 Group Section 19 Flash Memory Bit Bit Name 31 to 0 UA31 to UA0 Initial Value R/W Undefined R/W Description User Branch Destination Address When the user branch is not required, address 0 (H'00000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which on-chip program has been transferred, or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. The download of the on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. Store general registers R8 to R15. General registers R0 to R7 are available without storing them. Moreover, the programming/erasing interface registers must not be written to or RAM emulation mode must not be entered in the processing of the user branch destination. After the processing of the user branch has ended, the programming/erasing program must be returned to by using the RTS instruction. For the execution intervals of the user branch processing, see note 2 (User branch processing intervals) in section 19.8.3, Other Notes. Page 760 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit: 31 - Initial value: R/W: R/W Bit: 15 - Initial value: R/W: R/W Bit 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - BR FQ SF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 3 Initial Value R/W Undefined R/W Description Unused Return 0. 2 BR Undefined R/W User Branch Error Detect Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded. 0: User branch address setting is normal 1: User branch address setting is abnormal 1 FQ Undefined R/W Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF Undefined R/W Success/Fail Indicates whether initialization is completed normally. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 761 of 964 SH7146 Group Section 19 Flash Memory (3) Programming Execution When flash memory is programmed, the programming destination address and programming data on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space, which can be accessed by using the MOV.B instruction of the CPU, and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register R4. This parameter is called FMPDR (flash multipurpose data destination area parameter). For details on the programming procedure, see section 19.5.2, User Program Mode. (3.1) Flash multipurpose address area parameter (FMPAR: general register R5 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOA31 MOA30 MOA29 MOA28 MOA27 MOA26 MOA25 MOA24 MOA23 MOA22 MOA21 MOA20 MOA19 MOA18 MOA17 MOA16 Initial value: R/W: R/W Bit: 15 R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 MOA15 MOA14 MOA13 MOA12 MOA11 MOA10 MOA9 Initial value: R/W: R/W Page 762 of 964 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 MOA8 MOA7 MOA6 MOA5 MOA4 MOA3 MOA2 MOA1 MOA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Bit Section 19 Flash Memory Bit Name 31 to 0 MOA31 to MOA0 Initial Value R/W Description Undefined R/W MOA31 to MOA0 Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. The MOA6 to MOA0 bits are always 0 because the start address of the programming destination is at the 128-byte boundary. (3.2) Flash multipurpose data destination area parameter (FMPDR: general register R4 of CPU) This parameter indicates the start address in the area, which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD31 MOD30 MOD29 MOD28 MOD27 MOD26 MOD25 MOD24 MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16 Initial value: R/W: R/W Bit: 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD15 MOD14 MOD13 MOD12 MOD11 MOD10 MOD9 MOD8 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Initial value: R/W: R/W Bit R/W Bit Name R/W R/W Initial Value R/W R/W R/W 31 to 0 MOD31 to Undefined R/W MOD0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description MOD31 to MOD0 Store the start address of the area which stores the program data for the user MAT. The consecutive 128byte data is programmed to the user MAT starting from the specified start address. Page 763 of 964 SH7146 Group Section 19 Flash Memory (3.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit: 31 - Initial value: R/W: R/W Bit: 15 - Initial value: R/W: R/W Bit 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - MD EE FK - WD WA SF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 7 Initial Value R/W Undefined R/W Description Unused Return 0. 6 MD Undefined R/W Programming Mode Related Setting Error Detect Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 19.6.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: FWE = 0 or FLER = 1, and programming cannot be performed Page 764 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value 5 EE Undefined R/W R/W Description Programming Execution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT must be executed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed) 4 FK Undefined R/W Flash Key Register Error Detect Returns the check result of the value of FKEY before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A) 3 Undefined R/W Unused Return 0. 2 WD Undefined R/W Write Data Address Error Detect When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of write data address is normal 1: Setting of write data address is abnormal R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 765 of 964 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value 1 WA Undefined R/W R/W Description Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * The programming destination address is an area other than flash memory * The specified address is not at the 128-byte boundary (A6 to A0 are not 0) 0: Setting of programming destination address is normal 1: Setting of programming destination address is abnormal 0 SF Undefined R/W Success/Fail Indicates whether the program processing has ended normally or not. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) Page 766 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program, which is downloaded. This is set to the FEBS parameter (general register R4). One block is specified from the block number 0 to 15. For details on the erasing procedure, see section 19.5.2, User Program Mode. (4.1) Flash erase block select parameter (FEBS: general register R4 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be specified. Bit: 31 - Initial value: R/W: R/W Bit: 15 - Initial value: R/W: R/W Bit 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 8 Initial Value R/W Undefined R/W 16 EBS[7:0] R/W R/W R/W R/W R/W Description Unused Return 0. 7 to 0 EBS[7:0] Undefined R/W R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Set the erase-block number in the range from 0 to 11. 0 corresponds to the EB0 block and 11 corresponds to the EB11 block. An error occurs when a number other than 0 to 11 (H'00 to H'0B) is set. Page 767 of 964 SH7146 Group Section 19 Flash Memory (4.2) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter returns the value of the erasing processing result. Bit: 31 - Initial value: R/W: R/W Bit: 15 - Initial value: R/W: R/W Bit 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - MD EE FK EB - - SF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 7 Initial Value R/W Undefined R/W Description Unused Return 0. 6 MD Undefined R/W Erasure Mode Related Setting Error Detect Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 19.6.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: FWE = 0 or FLER = 1, and erasure cannot be performed Page 768 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Bit Bit Name Initial Value 5 EE Undefined R/W R/W Description Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasure of the user boot MAT must be executed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally (erasure result is not guaranteed) 4 FK Undefined R/W Flash Key Register Error Detect Returns the check result of FKEY value before start of the erasing processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A) 3 EB Undefined R/W Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal 2, 1 Undefined R/W Unused Return 0. 0 SF Undefined R/W Success/Fail Indicates whether the erasing processing has ended normally or not. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 769 of 964 SH7146 Group Section 19 Flash Memory 19.4.4 RAM Emulation Register (RAMER) When the realtime programming of the user MAT is emulated, RAMER sets the area of the user MAT which is overlapped with a part of the on-chip RAM. The RAM emulation must be executed in user mode or in user program mode. For the division method of the user-MAT area, see table 19.7. In order to operate the emulation function certainly, the target MAT of the RAM emulation must not be accessed immediately after RAMER is programmed. If it is accessed, the normal access is not guaranteed. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - RAMS Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name 15 to 4 Initial Value R/W All 0 R 2 1 0 RAM[2:0] 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 3 RAMS 0 R/W RAM Select Sets whether the user MAT is emulated or not. When RAMS = 1, all blocks of the user MAT are in the programming/erasing protection state. 0: Emulation is not selected Programming/erasing protection of all user-MAT blocks is invalid 1: Emulation is selected Programming/erasing protection of all user-MAT blocks is valid 2 to 0 RAM[2:0] 000 R/W User MAT Area Select These bits are used with bit 3 to select the user-MAT area to be overlapped with the on-chip RAM. (See table 19.7.) Page 770 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Table 19.7 Overlapping of RAM Area and User MAT Area RAM Area Block Name RAMS RAM2 RAM1 RAM0 H'FFFFA000 to H'FFFFAFFF RAM area (4 kbytes) 0 x x x H'00000000 to H'00000FFF EB0 (4 kbytes) 1 0 0 0 H'00001000 to H'00001FFF EB1 (4 kbytes) 1 0 0 1 H'00002000 to H'00002FFF EB2 (4 kbytes) 1 0 1 0 H'00003000 to H'00003FFF EB3 (4 kbytes) 1 0 1 1 H'00004000 to H'00004FFF EB4 (4 kbytes) 1 1 0 0 H'00005000 to H'00005FFF EB5 (4 kbytes) 1 1 0 1 H'00006000 to H'00006FFF EB6 (4 kbytes) 1 1 1 0 H'00007000 to H'00007FFF EB7 (4 kbytes) 1 1 1 1 Note: x: Don't care. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 771 of 964 SH7146 Group Section 19 Flash Memory 19.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user program mode, user boot mode, and boot mode. For details on the pin setting for entering each mode, see table 19.1. For details on the state transition of each mode for flash memory, see figure 19.2. 19.5.1 Boot Mode Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The system configuration diagram in boot mode is shown in figure 19.6. For details on the pin setting in boot mode, see table 19.1. Interrupts are ignored in boot mode so do not generate them. Note that the AUD cannot be used during boot mode operation. This LSI Host Boot programming tool and program data Control command, analysis execution software (on-chip) Flash memory RXD1 On-chip SCI1 TXD1 On-chip RAM Control command, program data Reply response Figure 19.6 System Configuration in Boot Mode Page 772 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCIcommunication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 19.8. Boot mode must be initiated in the range of this system clock. Note that the internal clock division ratio of x1/3 is not supported in boot mode. Start bit D0 D1 D2 D3 D4 D5 Measure low period (9 bits) (data is H'00) D6 D7 Stop bit High period of at least 1 bit Figure 19.7 Automatic Adjustment Operation of SCI Bit Rate Table 19.8 Peripheral Clock (P) Frequency that Can Automatically Adjust Bit Rate of This LSI Host Bit Rate Peripheral Clock (P) Frequency Which Can Automatically Adjust LSI's Bit Rate 9,600 bps 10 to 40 MHz 19,200 bps 10 to 40 MHz Note: The internal clock division ratio of x1/3 is not supported in boot mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 773 of 964 Section 19 Flash Memory SH7146 Group (2) State Transition Diagram Figure 19.8 gives an overview of the state transitions after the chip has been started up in boot mode. For details on boot mode, see section 19.9.1, Specifications of the Standard Serial Communications Interface in Boot Mode. 1. Bit-rate matching After the chip has been started up in boot mode, bit-rate matching between the SCI and the host proceeds. 2. Waiting for inquiry and selection commands The chip sends the requested information to the host in response to inquiries regarding the size and configuration of the user MAT, start addresses of the MATs, information on supported devices, etc. 3. Automatic erasure of the entire user MAT and user boot MAT After all necessary inquiries and selections have been made and the command for transition to the programming/erasure state is sent by the host, the entire user MAT and user boot MAT are automatically erased. 4. Waiting for programming/erasure command On receiving the programming selection command, the chip waits for data to be programmed. To program data, the host transmits the programming command code followed by the address where programming should start and the data to be programmed. This is repeated as required while the chip is in the programming-selected state. To terminate programming, H'FFFFFFFF should be transmitted as the first address of the area for programming. This makes the chip return to the programming/erasure command waiting state from the programming data waiting state. On receiving the erasure select command, the chip waits for the block number of a block to be erased. To erase a block, the host transmits the erasure command code followed by the number of the block to be erased. This is repeated as required while the chip is in the erasure-selected state. To terminate erasure, H'FF should be transmitted as the block number. This makes the chip return to the programming/erasure command waiting state from the erasure block number waiting state. Erasure should only be executed when a specific block is to be reprogrammed without executing a reset-start of the chip after the flash memory has been programmed in boot mode. If all desired programming is done in a single operation, such erasure processing is not necessary because all blocks are erased before the chip enters the programming/erasure/other command waiting state. In addition to the programming and erasure commands, commands for sum checking and blank checking (checking for erasure) of the user MAT and user boot MAT, reading data from the user MAT/user boot MAT, and acquiring current state information are provided. Note that the command for reading from the user MAT/user boot MAT can only read data that has been programmed after automatic erasure of the entire user MAT and user boot MAT. Page 774 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Start in boot mode (reset in boot mode) (Bit rate matching) Reception of H'00, ..., H'00 Bit rate matching 1. 5 H'5 on of pti Rece Reception of inquiry/selection command 2. Wait for inquiry/selection command 3. 4. Response to inquiry/selection command Erasure of entire user MAT and user boot MAT Wait for programming/erasure command Reception of read/check command Response to command Erasure complete Programming complete Execute processing in response to inquiry/ selection command Execute processing in response to read/ check command Reception of erasure select command Reception of programming select command Erasure block specification Wait for erasure block number Transmission of programming data by the host Wait for programming data Figure 19.8 State Transitions in Boot Mode R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 775 of 964 SH7146 Group Section 19 Flash Memory 19.5.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 19.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset must not be executed. Doing so may cause damage or destroy flash memory. If reset is executed accidentally, the reset signal must be released after the reset input period, which is longer than the normal 100 s. For details on the programming procedure, see the description in section 19.5.2 (2), Programming Procedure in User Program Mode. For details on the erasing procedure, see the description in section 19.5.2 (3), Erasing Procedure in User Program Mode. Programming/erasing start 1. RAM emulation mode must be canceled in advance. Download cannot be executed in emulation mode. When programming, program data is prepared FWE=1 ? Yes Programming/erasing procedure program is transferred to the on-chip RAM and executed No 2. When the program data is made by means of emulation, the download destination must be changed by FTDAR. 3. Inputting high level to the FWE pin sets the FWE bit to 1. 4. Programming/erasing is executed only in the on-chip RAM. However, if the program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like SRAM/ROM, the program data can be in an external space. 5. After programming/erasing is finished, low level must be input to the FWE pin for protection. Programming/erasing end Figure 19.9 Programming/Erasing Overview Flow Page 776 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. All of the on-chip program that is to be downloaded is in on-chip RAM. Note that onchip RAM must be controlled so that these parts do not overlap. Figure 19.10 shows the program area to be downloaded. <On-chip RAM> Area that can be used by user Area to be downloaded (Size: 3 kbytes) Unusable area in programming/erasing processing period Address RAMTOP (H'FFFF9000) DPFR FTDAR setting (Return value: 1 byte) System use area (15 bytes) FTDAR setting+16 Programming/ erasing entry Initialization process entry FTDAR setting+32 Initialization + programming program or Initialization + erasing program Area that can be used by user RAM emulation area FTDAR setting+3072 H'FFFFA000 H'FFFFAFFF Figure 19.10 RAM Map after Download R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 777 of 964 SH7146 Group Section 19 Flash Memory (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 19.11. Start programming procedure program 1 Download Set FKEY to H'A5 (2.2) Set parameter to R4 and R5 (FMPAR and FMPDR) (2.10) Programming JSR FTDAR setting+16 (2.11) (2.3) Clear FKEY to 0 (2.4) Yes FPFR=0? Yes (2.5) No No Download error processing Set the FPEFEQ and FUBRA parameters Initialization Set FKEY to H'5A After clearing VBR, set SCO to 1 and execute download DPFR=0? Required data programming is completed? Clear FKEY to 0 FPFR=0? Yes (2.12) No Clear FKEY and programming error processing (2.13) Yes (2.6) Initialization JSR FTDAR setting+32 (2.9) (2.1) Programming Select on-chip program to be downloaded and set download destination by FTDAR (2.14) (2.7) (2.8) End programming procedure program No Initialization error processing 1 Figure 19.11 Programming Procedure The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify 1/4 (initial value) as the frequency division ratios of an internal clock (I), a bus clock (B), and a peripheral clock (P) through the frequency control register (FRQCR). After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 19.9.2, Areas for Storage of the Procedural Program and Data for Programming. Page 778 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been executed, carry out erasing before writing. 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shortened. (2.1) Select the on-chip program to be downloaded When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (2.2) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request. (2.3) VBR is set to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. VBR must always be set to H'84000000 before setting the SCO bit to 1. To write 1 to the SCO bit, the following conditions must be satisfied. * RAM emulation mode is canceled. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect decision must be prevented by setting the DPFR parameter, that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be set to H'84000000. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. * The user MAT space is switched to the on-chip program storage area. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 779 of 964 SH7146 Group Section 19 Flash Memory * After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting to the on-chip RAM address specified by FTDAR. * The SCO bits in FCCS, FPCS, and FECS are cleared to 0. * The return value is set to the DPFR parameter. * After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed. The notes on download are as follows. In the download processing, the values of the general registers of the CPU are retained. During the download processing, interrupts must not be generated. For details on the relationship between download and interrupts, see section 19.8.2, Interrupts during Programming/Erasing. Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO bit to 1. If flash memory is accessed by the DTC during downloading, operation cannot be guaranteed. Therefore, access by the DTC must not be executed. (2.4) FKEY is cleared to H'00 for protection. (2.5) The value of the DPFR parameter must be checked to confirm the download result. A recommended procedure for confirming the download result is shown below. * Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA parameter for initialization. Page 780 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory * The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable range of the FPEFEQ parameter, see section 24.3.1, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in section 19.4.3 (2.1), Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU). * The start address in the user branch destination is set to the (FUBRA: CPU general register R5) parameter. When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. See the description in section 19.4.3 (2.2), Flash user branch address setting parameter (FUBRA: general register R5 of CPU). (2.7) Initialization When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L #DLTOP+32,R1 ; Set entry address to R1 JSR @R1 ; Call initialization routine NOP * The general registers other than R0 are saved in the initialization program. * R0 is a return value of the FPFR parameter. * Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved in RAM. * Interrupts can be accepted during the execution of the initialization program. However, the program storage area and stack area in on-chip RAM and register values must not be destroyed. (2.8) The return value of the initialization program, FPFR (general register R0) is checked. (2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming. (2.10) The parameter which is required for programming is set. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 781 of 964 SH7146 Group Section 19 Flash Memory The start address of the programming destination of the user MAT (FMPAR) is set to general register R5. The start address of the program data storage area (FMPDR) is set to general register R4. * FMPAR setting FMPAR specifies the programming destination start address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80. * FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to on-chip RAM and then programming must be executed. (2.11) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call programming routine NOP The general registers other than R0 are saved in the programming program. R0 is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of maximum 128 bytes must be reserved in RAM. (2.12) The return value in the programming program, FPFR (general register R0) is checked. (2.13) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (2.14) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. Page 782 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 19.12. Start erasing procedure program 1 Set FKEY to H'5A (3.1) Set FKEY to H'A5 Set FEBS parameter (3.2) After clearing VBR, set SCO to 1 and execute download Erasing JSR FTDAR setting+16 (3.3) Erasing Download Select on-chip program to be downloaded and set download destination by FTDAR Clear FKEY to 0 Yes DPFR = 0? Yes No No Download error processing No Clear FKEY and erasing error processing Required block erasing is completed? Set the FPEFEQ and FUBRA parameters Initialization (3.4) FPFR=0 ? (3.5) Yes Clear FKEY to 0 Initialization JSR FTDAR setting+32 (3.6) End erasing procedure program FPFR=0 ? No Yes Initialization error processing 1 Figure 19.12 Erasing Procedure The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. Specify 1/4 (initial value) as the frequency division ratios of an internal clock (If), a bus clock (Bf), and a peripheral clock (Pf) through the frequency control register (FRQCR). After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 19.9.2, Areas for Storage of the Procedural Program and Data for Programming. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 783 of 964 SH7146 Group Section 19 Flash Memory For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 19.10. A single divided block is erased by one erasing processing. For block divisions, see figure 19.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see the description in section 19.5.2 (2), Programming Procedure in User Program Mode. (3.2) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter (FEBS: general register R4). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (3.3) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call erasing routine NOP The general registers other than R0 are saved in the erasing program. R0 is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of maximum 128 bytes must be reserved in RAM. (3.4) The return value in the erasing program, FPFR (general register R0) is checked. (3.5) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to (3.5). Blocks that have already been erased can be erased again. Page 784 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (3.6) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. 19.5.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in user program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 19.1. When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 1.2 kbytes from H'FFFF9800 and 4 bytes from H'FFFFAFFC (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 40 MHz. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to the flash MAT select register (FMATS) because the execution MAT is the user boot MAT. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 785 of 964 SH7146 Group Section 19 Flash Memory (2) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 19.13 shows the procedure for programming the user MAT in user boot mode. Start programming procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? Set parameter to R4 and R5 (FMPAR and FMPDR) Programming JSR FTDAR setting+16 Programming Clear FKEY to 0 Yes MAT switchover Set FKEY to H'5A User-MAT selection state Download After clearing VBR, set SCO to 1 and execute download DPFR=0 ? Initialization User-boot-MAT selection state Set FKEY to H'A5 FPFR=0 ? No Yes Clear FKEY and programming error processing* No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Set FMATS to H'AA to select user boot MAT 1 User-boot-MAT selection state MAT switchover End programming procedure program Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 19.13 Procedure for Programming User MAT in User Boot Mode Page 786 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 19.13. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming finishes, switch the MATs again to return to the first state. MAT switchover is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completely finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 19.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 19.9.2, Areas for Storage of the Procedural Program and Data for Programming. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 787 of 964 SH7146 Group Section 19 Flash Memory (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 19.14 shows the procedure for erasing the user MAT in user boot mode. Start erasing procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT Set FKEY to H'5A Yes No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? Set FEBS parameter Programming JSR FTDAR setting+16 Erasing Clear FKEY to 0 User-MAT selection state Download After clearing VBR, set SCO to 1 and execute download DPFR=0 ? Initialization User-boot-MAT selection state Set FKEY to H'A5 MAT switchover FPFR=0 ? No No Yes Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing 1 Set FMATS to H'AA to select user boot MAT User-boot-MAT selection state MAT switchover End erasing procedure program Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 19.14 Procedure for Erasing User MAT in User Boot Mode Page 788 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 19.14. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 19.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 19.9.2, Areas for Storage of the Procedural Program and Data for Programming. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 789 of 964 SH7146 Group Section 19 Flash Memory 19.6 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 19.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR parameter. Table 19.9 Hardware Protection Function to be Protected Item Description FWE-pin protection The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming/erasing-protected state. Reset/standby protection Page 790 of 964 Download Programming/ Erasure -- * A power-on reset (including a power-on reset by the WDT) and entry to standby mode initializes the programming/erasing interface registers and the LSI enters a programming/erasing-protected state. * Resetting by means of the RES pin after power is initially supplied will not make the LSI enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics. If the LSI is reset during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 19.6.2 Section 19 Flash Memory Software Protection Software protection is set up in any of three ways: by disabling the downloading of on-chip programs for programming and erasing, by means of a key code, and by the RAM emulation register (RAMER). Table 19.10 Software Protection Function to be Protected Item Description Download Programming/ Erasure Protection by the SCO bit Clearing the SCO bit in FCCS disables downloading of the programming/erasing program, thus making the LSI enter a programming/erasing-protected state. Protection by FKEY Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. Emulation protection Setting the RAMS bit in RAMER to 1 makes the LSI enter a programming/erasing-protected state. 19.6.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or erasure. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 791 of 964 SH7146 Group Section 19 Flash Memory The FLER bit is set to 1 in the following conditions: * When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) * When a SLEEP instruction (including software standby mode) is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) only by a power-on reset. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 19.15 shows transitions to and from the error protection state. Program mode Erase mode Read disabled Programming/erasing enabled FLER = 0 Error occurred Reset RES = 0 Er ror (S occ u oft wa rred re sta n S RE =0 Read enabled Programming/erasing disabled FLER = 0 RES = 0 Programming/erasing interface register is in its initial state. db Error protection mode Read enabled Programming/erasing disabled FLER = 1 y) Software standby mode Error protection mode (Software standby) Read disabled Cancel Programming/erasing disabled software standby mode FLER = 1 Programming/erasing interface register is in its initial state. Figure 19.15 Transitions to and from Error Protection State Page 792 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 19.7 Section 19 Flash Memory Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM emulation register (RAMER). After the RAMER setting is made, the RAM is accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area. Such emulation is possible in user mode and user program mode. Figure 19.16 shows an example of the emulation of realtime programming of the user MAT area. Start of emulation program Set RAMER Write the data for tuning to the overlapped RAM area Execute application program No Tuning OK? Yes Cancel RAMER setting Program the emulation block in the user MAT End of emulation program Figure 19.16 Emulation of Flash Memory in RAM R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 793 of 964 SH7146 Group Section 19 Flash Memory This area is accessible as both a RAM area and as a flash memory area. H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'FFFF9000 On-chip RAM H'FFFF9FFF H'FFFFA000 H'FFFFAFFF H'08000 Flash memory (user MAT) EB8 to EB11 H'3FFFF Figure 19.17 Example of Overlapped RAM Operation Figure 19.17 shows an example of an overlap on block area EB0 of the flash memory. Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of the user MAT. The area is selected by the setting of the RAM2 to RAM0 bits in RAMER. 1. To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0. 2. Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of an on-chip program. In this process, set the download area with FTDAR so that the overlaid RAM area and the area where the on-chip program is to be downloaded do not overlap. Figure 19.18 shows an example of programming data that has been emulated to the EB0 area in the user MAT. Page 794 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 EB0 EB1 EB2 EB3 EB4 EB5 <On-chip RAM> FTDAR setting Download area EB6 EB7 H'08000 Programming/erasing procedure program area H'FFFF9FFF Tuned data area Flash memory (user MAT) EB8 to EB11 H'3FFFF H'FFFFA000 H'FFFFAFFF (1) Cancel the emulation mode. (2) Transfer the user programming/erasing procedure program. (3) Download the on-chip programming/ erasing program to the destination set by FTDAR without overlapping the tuned data area. (4) Execute programming after erasing. Figure 19.18 Programming of Tuned Data 1. After the data to be programmed has fixed values, clear the RAMS bit to 0 to cancel the overlap of RAM. Emulation mode is canceled and emulation protection is also cleared. 2. Transfer the user programming/erasing procedure program to RAM. 3. Run the programming/erasing procedure program in RAM and download the on-chip programming/erasing program. Specify the download start address with FTDAR so that the tuned data area does not overlap with the download area. 4. When the EB0 area of the user MAT has not been erased, erasing must be performed before programming. Set the parameters FMPAR and FMPDR so that the tuned data is designated, and execute programming. Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM2 to RAM0 bits (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. Though RAM emulation can also be carried out with the user boot MAT selected, the user boot MAT can be erased or programmed only in boot mode or programmer mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 795 of 964 Section 19 Flash Memory 19.8 Usage Notes 19.8.1 Switching between User MAT and User Boot MAT SH7146 Group It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT must take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. The SH microcomputer prefetches execution instructions. Therefore, a switchover during program execution in the user MAT causes an instruction code in the user MAT to be prefetched or an instruction in the newly selected user boot MAT to be prefetched, thus resulting in unstable operation. 2. To ensure that the MAT that has been switched to is accessible, execute four NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). 3. If an interrupt occurs during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching MATs. In addition, configuring the system so that NMI interrupts do not occur during MAT switching is recommended. 4. After the MATs have been switched, take care because the interrupt vector table will also have been switched. If the same interrupt processings are to be executed before and after MAT switching or interrupt requests cannot be disabled, transfer the interrupt processing routine to on-chip RAM, and use the VBR setting to place the interrupt vector table in on chip RAM. In this case, make sure the VBR setting change does not conflict with the interrupt occurrence. 5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 12-kbyte memory space. If access goes beyond the 12-kbyte space, the values read are undefined. Page 796 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory <User MAT> <On-chip RAM> <User boot MAT> Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts. (2) Write H'AA to FMATS. (3) Execute four NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (1) Mask interrupts. (2) Write a value other than H'AA to FMATS. (3) Execute four NOP instructions before accessing the user MAT. Figure 19.19 Switching between User MAT and User Boot MAT 19.8.2 Interrupts during Programming/Erasing (1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'84000000. If VBR is set to a value other than H'84000000, the interrupt vector table is placed in the user MAT (FMATS is not H'AA) or the user boot MAT (FMATS is H'AA) on setting H'84000000 to VBR. When VBR setting change conflicts with interrupt occurrence, whether the vector table before or after VBR is changed is referenced may cause an error. Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a vector table to be referenced when VBR is H'00000000 (initial value) at the start of the user MAT or user boot MAT. (1.2) SCO download request and interrupt request Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover. Operation when the SCO download request and interrupt request conflicts is described below. 1. Contention between SCO download request and interrupt request Figure 19.20 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 797 of 964 SH7146 Group Section 19 Flash Memory CPU cycle CPU operation for instruction that sets SCO bit to 1 Interrupt acceptance n n+1 n+2 n+3 n+4 Fetch Decoding Execution Execution Execution (a) (b) (a) When the interrupt is accepted at the (n + 1) cycle or before After the interrupt processing completes, the SCO bit is set to 1 and download is executed. (b) When the interrupt is accepted at the (n + 2) cycle or later The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated. Figure 19.20 Timing of Contention between SCO Download Request and Interrupt Request 2. Generation of interrupt requests during downloading Ensure that interrupts are not generated during downloading that is initiated by the SCO bit. Page 798 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the interrupt processing, temporarily save the new program data in another area. After confirming the completion of programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved. 3. Make sure the interrupt processing routine does not rewrite the contents of the flashmemory related registers or data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform RAM emulation, download of the onchip program by an SCO request, or programming/erasing. 4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the interrupt processing, write the saved contents in the CPU registers again. 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 s to reduce the damage to flash memory. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 799 of 964 SH7146 Group Section 19 Flash Memory 19.8.3 Other Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum. 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 19.11 lists the maximum intervals for initiating the user branch processing when the CPU clock frequency is 80 MHz. Table 19.11 Initiation Intervals of User Branch Processing Processing Name Maximum Interval Programming Approximately 2 ms Erasing Approximately 15 ms However, when operation is done with CPU clock of 80 MHz, maximum values of the time until first user branch processing are as shown in table 19.12. Table 19.12 Initial User Branch Processing Time Processing Name Max. Programming Approximately 2 ms Erasing Approximately 15 ms 3. Write to flash-memory related registers by DTC While an instruction in on-chip RAM is being executed, the DTC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and destroy RAM or a MAT switchover may occur and the CPU get out of control. 4. State in which interrupts are ignored In the following modes or period, interrupt requests are ignored; they are not executed and the interrupt sources are not retained. Boot mode Programmer mode Page 800 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory 5. Note on programming the product having a 256-Kbyte user MAT If an attempt is made to program the product having a 256-Kbyte user MAT with more than 256 Kbytes, data programmed after the first 256 Kbytes are not guaranteed. 6. Compatibility with programming/erasing program of conventional F-ZTAT SH microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 7. Monitoring runaway by WDT Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 801 of 964 Section 19 Flash Memory SH7146 Group 19.9 Supplementary Information 19.9.1 Specifications of the Standard Serial Communications Interface in Boot Mode The boot program activated in boot mode communicates with the host via the on-chip SCI of the LSI. The specifications of the serial communications interface between the host and the boot program are described below. * States of the boot program The boot program has three states. 1. Bit-rate matching state In this state, the boot program adjusts the bit rate to match that of the host. When the chip starts up in boot mode, the boot program is activated and enters the bit-rate matching state, in which it receives commands from the host and adjusts the bit rate accordingly. After bit-rate matching is complete, the boot program proceeds to the inquiry-and-selection state. 2. Inquiry-and-selection state In this state, the boot program responds to inquiry commands from the host. The device, clock mode, and bit rate are selected in this state. After making these selections, the boot program enters the programming/erasure state in response to the transition-to-programming/erasure state command. The boot program transfers the erasure program to RAM and executes erasure of the user MAT and user boot MAT before it enters the programming/erasure state. 3. Programming/erasure state In this state, programming/erasure are executed. The boot program transfers the program for programming/erasure to RAM in line with the command received from the host and executes programming/erasure. It also performs sum checking and blank checking as directed by the respective commands. Figure 19.21 shows the flow of processing by the boot program. Page 802 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Reset Bit rate matching state Bit rate matching Inquiry-and-selection state Wait for inquiry and selection Inquiry Inquiry processing Selection Selection processing Enter programming/erasure state Programming/erasure state Erase user MAT/use boot MAT Wait for programming/erasure selection Programming Programming processing Erasure Erasure processing Checking Checking processing Figure 19.21 Flow of Processing by the Boot Program * Bit-rate matching state In bit-rate matching, the boot program measures the low-level intervals in a signal carrying H'00 data that is transmitted by the host, and calculates the bit rate from this. The bit rate can be changed by the new-bit-rate selection command. On completion of bit-rate matching, the boot program goes to the inquiry and selection state. The sequence of processing in bit-rate matching is shown in figure 19.22. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 803 of 964 SH7146 Group Section 19 Flash Memory Host Boot program H'00 (max. 30 times) Measures the length of one bit H'00 (bit rate matching complete) H'55 H'E6 (response) H'FF (error) Figure 19.22 Sequence of Bit-Rate Matching * Communications protocol Formats in the communications protocol between the host and boot program after completion of the bit-rate matching are as follows. 1. One-character command or one-character response A command or response consisting of a single character used for an inquiry or the ACK code indicating normal completion. 2. n-character command or n-character response A command or response that requires n bytes of data, which is used as a selection command or response to an inquiry. The length of programming data is treated separately below. 3. Error response Response to a command in case of an error: two bytes, consisting of the error response and error code. 4. 128-byte programming command The command itself does not include data-size information. The data length is known from the response to the command for inquiring about the programming size. 5. Response to a memory reading command This response includes four bytes of size information. Page 804 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory One-character command or one-character response n-character command or n-character response Command or response Data Size Checksum Command or response Error response Error code Error response 128-byte programming command Address Data (n bytes) Command Response to memory read command Data size Checksum Data Response Checksum Figure 19.23 Formats in the Communications Protocol Command (1 byte): Inquiry, selection, programming, erasure, checking, etc. Response (1 byte): Response to an inquiry Size (one or two bytes): The length of data for transfer, excluding the command/response code, size, and checksum. Data (n bytes): Particular data for the command or response Checksum (1 byte): Set so that the total sum of byte values from the command code to the checksum is H'00 in the lower-order 1 byte. Error response (1 byte): Error response to a command Error code (1 byte): Indicates the type of error. Address (4 bytes): Address for programming Data (n bytes): Data to be programmed. "n" is known from the response to the command used to inquire about the programming size. Data size (4 bytes): Four-byte field included in the response to a memory reading command. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 805 of 964 SH7146 Group Section 19 Flash Memory * Inquiry-and-Selection State In this state, the boot program returns information on the flash ROM in response to inquiry commands sent from the host, and selects the device, clock mode, and bit rate in response to the respective selection commands. The inquiry and selection commands are listed in table 19.13. Table 19.13 Inquiry and Selection Commands Command Command Name Function H'20 Inquiry on supported devices Requests the device codes and their respective boot program names. H'10 Device selection Selects a device code. H'21 Inquiry on clock modes Requests the number of available clock modes and their respective values. H'11 Clock-mode selection Selects a clock mode. H'22 Inquiry on frequency multipliers Requests the number of clock signals for which frequency multipliers and divisors are selectable, the number of multiplier and divisor settings for the respective clocks, and the values of the multipliers and divisors. H'23 Inquiry on operating frequency Requests the minimum and maximum values for operating frequency of the main clock and peripheral clock. H'24 Inquiry on user boot MATs Requests the number of user boot MAT areas along with their start and end addresses. H'25 Inquiry on user MATs Requests the number of user MAT areas along with their start and end addresses. H'26 Inquiry on erasure blocks Requests the number of erasure blocks along with their start and end addresses. H'27 Inquiry on programming size Requests the unit of data for programming. H'3F New bit rate selection Selects a new bit rate. H'40 Transition to programming/erasure state On receiving this command, the boot program erases the user MAT and user boot MAT and enters the programming/erasure state. H'4F Inquiry on boot program state Requests information on the current state of boot processing. The selection commands should be sent by the host in this order: device selection (H'10), clockmode selection (H'11), new bit rate selection (H'3F). These commands are mandatory. If the same selection command is sent two or more times, the command that is sent last is effective. Page 806 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory All commands in the above table, except for the boot program state inquiry command (H'4F), are valid until the boot program accepts the transition-to-programming/erasure state command (H'40). That is, until the transition command is accepted, the host can continue to send commands listed in the above table until it has made the necessary inquiries and selections. The host can send the boot program state inquiry command (H'4F) even after acceptance of the transition-toprogramming/erasure state command (H'40) by the boot program. (1) Inquiry on supported devices In response to the inquiry on supported devices, the boot program returns the device codes of the devices it supports and the product names of their respective boot programs. Command H'20 Command H'20 (1 byte): Inquiry on supported devices Response H'30 Size Number of Device code No. of devices Product name characters ... SUM Response H'30 (1 byte): Response to the inquiry on supported devices Size (1 byte): The length of data for transfer excluding the command code, this field (size), and the checksum. Here, it is the total number of bytes taken up by the number of devices, number of characters, device code, and product name fields. Number of devices (1 byte): The number of device models supported by the boot program embedded in the microcomputer. Number of characters (1 byte): The number of characters in the device code and product name fields. Device code (4 bytes): Device code of a supported device (ASCII encoded) Product name (n bytes): Product code of the boot program (ASCII encoded) SUM (1 byte): Checksum This is set so that the total sum of all bytes from the command code to the checksum is H'00. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 807 of 964 SH7146 Group Section 19 Flash Memory Device selection (2) In response to the device selection command, the boot program sets the specified device as the selected device. The boot program will return the information on the selected device in response to subsequent inquiries. Command H'10 Size Device code SUM Command H'10 (1 byte): Device selection Size (1 byte): Number of characters in the device code (fixed at 4) Device code (4 bytes): A device code that was returned in response to an inquiry on supported devices (ASCII encoded) SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): Response to device selection The ACK code is returned when the specified device code matches one of the supported devices. Error response H'90 ERROR Error response H'90 (1 byte): Error response to device selection ERROR (1 byte): Error code H'11: Sum-check error H'21: Non-matching device code (3) Inquiry on clock modes In response to the inquiry on clock modes, the boot program returns the number of available clock modes. Command H'21 Command H'21 (1 byte): Inquiry on clock modes Response Page 808 of 964 H'31 Size Mode ... SUM R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Response H'31 (1 byte): Response to the inquiry on clock modes Size (1 byte): The total length of the number of modes and mode data fields. Mode (1 byte): Selectable clock mode (example: H'01 denotes clock mode 1) SUM (1 byte): Checksum Clock-mode selection (4) In response to the clock-mode selection command, the boot program sets the specified clock mode. The boot program will return the information on the selected clock mode in response to subsequent inquiries. Command H'11 Size Mode SUM Command H'11 (1 byte): Clock mode selection Size (1 byte): Number of characters in the clock-mode field (fixed at 1) Mode (1 byte): A clock mode returned in response to the inquiry on clock modes SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): Response to clock mode selection The ACK code is returned when the specified clock-mode matches one of the available clock modes. Error response H'91 ERROR Error response H'91 (1 byte): Error response to clock mode selection ERROR (1 byte): Error code H'11: Sum-check error H'21: Non-matching clock mode R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 809 of 964 SH7146 Group Section 19 Flash Memory (5) Inquiry on frequency multipliers In response to the inquiry on frequency multipliers, the boot program returns information on the settable frequency multipliers or divisors. Command H'22 Command H'22 (1 byte): Inquiry on frequency multipliers Response H'32 Size No. of operating clocks No. of multipliers Multiplier ... ... SUM Response H'32 (1 byte): Response to the inquiry on frequency multipliers Size (1 byte): The total length of the number of operating clocks, number of multipliers, and multiplier fields. Number of operating clocks (1 byte): The number of operating clocks for which multipliers can be selected (for example, if frequency multiplier settings can be made for the frequencies of the main and peripheral operating clocks, the value should be H'02). Number of multipliers (1 byte): The number of multipliers selectable for the operating frequency of the main or peripheral modules Multiplier (1 byte): Multiplier: Numerical value in the case of frequency multiplication (e.g. H'04 for x4) Divisor: Two's complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for x1/2) As many multiplier fields are included as there are multipliers or divisors, and combinations of the number of multipliers and multiplier fields are repeated as many times as there are operating clocks. SUM (1 byte): Checksum Page 810 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group (6) Section 19 Flash Memory Inquiry on operating frequency In response to the inquiry on operating frequency, the boot program returns the number of operating frequencies and the maximum and minimum values. Command H'23 Command H'23 (1 byte): Inquiry on operating frequency Response H'33 Size Operating freq. (min) No. of operating clocks Operating freq. (max) ... SUM Response H'33 (1 byte): Response to the inquiry on operating frequency Size (1 byte): The total length of the number of operating clocks, and maximum and minimum values of operating frequency fields. Number of operating clocks (1 byte): The number of operating clock frequencies required within the device. For example, the value two indicates main and peripheral operating clock frequencies. Minimum value of operating frequency (2 bytes): The minimum frequency of a frequencymultiplied or -divided clock signal. The value in this field and in the maximum value field is the frequency in MHz to two decimal places, multiplied by 100 (for example, if the frequency is 20.00 MHz, the value multiplied by 100 is 2000, so H'07D0 is returned here). Maximum value of operating frequency (2 bytes): The maximum frequency of a frequencymultiplied or -divided clock signal. As many pairs of minimum/maximum values are included as there are operating clocks. SUM (1 byte): Checksum R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 811 of 964 SH7146 Group Section 19 Flash Memory (7) Inquiry on user boot MATs In response to the inquiry on user boot MATs, the boot program returns the number of user boot MAT areas and their addresses. Command H'24 Command H'24 (1 byte): Inquiry on user boot MAT information Response H'34 Size No. of areas First address of the area Last address of the area ... SUM Response H'34 (1 byte): Response to the inquiry on user boot MATs Size (1 byte): The total length of the number of areas and first and last address fields. Number of areas (1 byte): The number of user boot MAT areas. H'01 is returned if the entire user boot MAT area is continuous. First address of the area (4 bytes) Last address of the area (4 bytes) As many pairs of first and last address field are included as there are areas. SUM (1 byte): Checksum (8) Inquiry on user MATs In response to the inquiry on user MATs, the boot program returns the number of user MAT areas and their addresses. Command H'25 Command H'25 (1 byte): Inquiry on user MAT information Response H'35 Size First address of the area No. of areas Last address of the area ... SUM Page 812 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Response H'35 (1 byte): Response to the inquiry on user MATs Size (1 byte): The total length of the number of areas and first and last address fields. Number of areas (1 byte): The number of user MAT areas. H'01 is returned if the entire user MAT area is continuous. First address of the area (4 bytes) Last address of the area (4 bytes) As many pairs of first and last address field are included as there are areas. SUM (1 byte): Checksum (9) Inquiry on erasure blocks In response to the inquiry on erasure blocks, the boot program returns the number of erasure blocks in the user MAT and the addresses where each block starts and ends. Command H'26 Command H'26 (1 byte): Inquiry on erasure blocks Response H'36 Size First address of the block No. of blocks Last address of the block ... SUM Response H'36 (1 byte): Response to the inquiry on erasure blocks Size (2 bytes): The total length of the number of blocks and first and last address fields. Number of blocks (1 byte): The number of erasure blocks in flash memory First address of the block (4 bytes) Last address of the block (4 bytes) As many pairs of first and last address data are included as there are blocks. SUM (1 byte): Checksum R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 813 of 964 SH7146 Group Section 19 Flash Memory (10) Inquiry on programming size In response to the inquiry on programming size, the boot program returns the size, in bytes, of the unit for programming. Command H'27 Command H'27 (1 byte): Inquiry on programming size Response H'37 Size Programming size SUM Response H'37 (1 byte): Response to the inquiry on programming size Size (1 byte): The number of characters in the programming size field (fixed at 2) Programming size (2 bytes): The size of the unit for programming This is the unit for the reception of data to be programmed. SUM (1 byte): Checksum (11) New bit rate selection In response to the new-bit-rate selection command, the boot program changes the bit rate setting to the new bit rate and, if the setting was successful, responds to the ACK sent by the host by returning another ACK at the new bit rate. The new-bit-rate selection command should be sent after clock-mode selection. Command H'3F Size No. of multipliers Multiplier 1 Bit rate Input frequency Multiplier 2 SUM Command H'3F (1 byte): New bit rate selection Size (1 byte): The total length of the bit rate, input frequency, number of multipliers, and multiplier fields Bit rate (2 bytes): New bit rate The bit rate value divided by 100 should be set here (for example, to select 19200 bps, the set H'00C0, which is 192 in decimal notation). Input frequency (2 bytes): The frequency of the clock signal fed to the boot program This should be the frequency in MHz to the second decimal place, multiplied by 100 (for example, if the frequency is 28.882 MHz, the values is truncated to the second decimal place and multiplied by 100, making 2888; so H'0B48 should be set in this field). Page 814 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Number of multipliers (1 byte): The number of selectable frequency multipliers and divisors for the device. This is normally 2, which indicates the main operating frequency and the operating frequency of the peripheral modules. Multiplier 1 (1 byte): Multiplier or divisor for the main operating frequency Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for x4) Divisor: Two's complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for x1/2) Multiplier 2 (1 byte): Multiplier or divisor for the peripheral operating frequency Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for x4) Divisor: Two's complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for x1/2) SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): Response to the new-bit-rate selection command The ACK code is returned if the specified bit rate was selectable. Error response H'BF ERROR Error response H'BF (1 byte): Error response to new bit rate selection ERROR (1 byte): Error code H'11: Sum-check error H'24: Bit rate selection error (the specified bit rate is not selectable). H'25: Input frequency error (the specified input frequency is not within the range from the minimum to the maximum value). H'26: Frequency multiplier error (the specified multiplier does not match an available one). H'27: Operating frequency error (the specified operating frequency is not within the range from the minimum to the maximum value). R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 815 of 964 SH7146 Group Section 19 Flash Memory The received data are checked in the following ways. 1. Input frequency The value of the received input frequency is checked to see if it is within the range of the minimum and maximum values of input frequency for the selected clock mode of the selected device. A value outside the range generates an input frequency error. 2. Multiplier The value of the received multiplier is checked to see if it matches a multiplier or divisor that is available for the selected clock mode of the selected device. A value that does not match an available ratio generates a frequency multiplier error. 3. Operating frequency The operating frequency is calculated from the received input frequency and the frequency multiplier or divisor. The input frequency is the frequency of the clock signal supplied to the LSI, while the operating frequency is the frequency at which the LSI is actually driven. The following formulae are used for this calculation. Operating frequency = input frequency x multiplier, or Operating frequency = input frequency / divisor The calculated operating frequency is checked to see if it is within the range of the minimum and maximum values of the operating frequency for the selected clock mode of the selected device. A value outside the range generates an operating frequency error. 4. Bit rate From the peripheral operating frequency (P) and the bit rate (B), the value (= n) of the clock select bits (CKS) in the serial mode register (SCSMR) and the value (= N) of the bit rate register (SCBRR) are calculated, after which the error in the bit rate is calculated. This error is checked to see if it is smaller than 4%. A result greater than or equal to 4% generates a bit rate selection error. The following formula is use to calculate the error. Error (%) = [ Page 816 of 964 P x 106 ]-1 (N + 1) x B x 64 x 22n-1 x 100 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory When the new bit rate is selectable, the boot program returns an ACK code to the host and then makes the register setting to select the new bit rate. The host then sends an ACK code at the new bit rate, and the boot program responds to this with another ACK code, this time at the new bit rate. Acknowledge H'06 Acknowledge H'06 (1 byte): The ACK code sent by the host to acknowledge the new bit rate. Response H'06 Response H'06 (1 byte): The ACK code transferred in response to acknowledgement of the new bit rate The sequence of new bit rate selection is shown in figure 19.24. Host Boot program New bit rate setting H'06 (ACK) Wait for one-bit period at the current bit rate setting New bit rate setting Setting the new bit rate H'06 (ACK) at the new bit rate H'06 (ACK) at the new bit rate Figure 19.24 Sequence of New Bit Rate Selection R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 817 of 964 SH7146 Group Section 19 Flash Memory (12) Transition to the programming/erasure state In response to the transition to the programming/erasure state command, the boot program transfers the erasing program and runs it to erase any data in the user MAT and then the user boot MAT. On completion of this erasure, the boot program returns the ACK code and enters the programming/erasure state. Before sending the programming selection command and data for programming, the host must select the device, clock mode, and new bit rate for the LSI by issuing the device selection command, clock-mode selection command, new-bit-rate selection command, and then initiate the transition to the programming/erasure state by sending the corresponding command to the boot program. Command H'40 Command H'40 (1 byte): Transition to programming/erasure state Response H'06 Response H'06 (1 byte): Response to the transition-to-programming/erasure state command This is returned as ACK when erasure of the user boot MAT and user MAT has succeeded after transfer of the erasure program. Error response H'C0 H'51 Error response H'C0 (1 byte): Error response to the transition-to-programming/erasure state command ERROR (1 byte): Error code H'51: Erasure error (Erasure did not succeed because of an error.) Page 818 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory * Command Error Command errors are generated by undefined commands, commands sent in an incorrect order, and the inability to accept a command. For example, sending the clock-mode selection command before device selection or an inquiry command after the transition-to-programming/erasure state command generates a command error. Error response H'80 H'xx Error response H'80 (1 byte): Command error Command H'xx (1 byte): Received command * Order of Commands In the inquiry-and-selection state, commands should be sent in the following order. 1. Send the inquiry on supported devices command (H'20) to get the list of supported devices. 2. Select a device from the returned device information, and send the device selection command (H'10) to select that device. 3. Send the inquiry on clock mode command (H'21) to get the available clock modes. 4. Select a clock mode from among the returned clock modes, and send the clock-mode selection command (H'11). 5. After selection of the device and clock mode, send the commands to inquire about frequency multipliers (H'22) and operating frequencies (H'23) to get the information required to select a new bit rate. 6. Taking into account the returned information on the frequency multipliers and operating frequencies, send a new-bit-rate selection command (H'3F). 7. After the device and clock mode have been selected, get the information required for programming and erasure of the user boot MAT and user MAT by sending the commands to inquire about the user boot MAT (H'24), user MAT (H'25), erasure block (H'26), and programming size (H'27). 8. After making all necessary inquiries and the new bit rate selection, send the transition-toprogramming/erasure state command (H'40) to place the boot program in the programming/erasure state. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 819 of 964 SH7146 Group Section 19 Flash Memory * Programming/Erasure State In this state, the boot program must select the form of programming corresponding to the programming-selection command and then write data in response to 128-byte programming commands, or perform erasure in block units in response to the erasure-selection and blockerasure commands. The programming and erasure commands are listed in table 19.14. Table 19.14 Programming and Erasure Commands Command Command Name Function H'42 Selection of user boot MAT programming Selects transfer of the program for user boot MAT programming. H'43 Selection of user MAT programming Selects transfer of the program for user MAT programming. H'50 128-byte programming Executes 128-byte programming. H'48 Erasure selection Selects transfer of the erasure program. H'58 Block erasure Executes erasure of the specified block. H'52 Memory read Reads from memory. H'4A Sum checking of user boot MAT Executes sum checking of the user boot MAT. H'4B Sum checking of user MAT Executes sum checking of the user MAT. H'4C Blank checking of user Executes blank checking of the user boot MAT. boot MAT H'4D Blank checking of user Executes blank checking of the user MAT. MAT H'4F Inquiry on boot program state Page 820 of 964 Requests information on the state of boot processing. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory * Programming Programming is performed by issuing a programming-selection command and the 128-byte programming command. Firstly, the host issues the programming-selection command to select the MAT to be programmed. Two programming-selection commands are provided for the selection of either of the two target areas. 1. Selection of user boot MAT programming 2. Selection of user MAT programming Next, the host issues a 128-byte programming command. 128 bytes of data for programming by the method selected by the preceding programming selection command are expected to follow the command. To program more than 128 bytes, repeatedly issue 128-byte programming commands. To terminate programming, the host should send another 128-byte programming command with the address H'FFFFFFFF. On completion of programming, the boot program waits for the next programming/erasure selection command. To then program the other MAT, start by sending the programming select command. The sequence of programming by programming-selection and 128-byte programming commands is shown in figure 19.25. Host Boot program Programming selection (H'42, H'43) Transfer the program that performs programming ACK 128-byte programming (address and data) Programming Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Figure 19.25 Sequence of Programming R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 821 of 964 SH7146 Group Section 19 Flash Memory Selection of user boot MAT programming (1) In response to the command for selecting programming of the user boot MAT, the boot program transfers the corresponding flash-writing program, i.e. the program for writing to the user boot MAT. Command H'42 Command H'42 (1 byte): Selects programming of the user boot MAT. Response H'06 Response H'06 (1 byte): Response to selection of user boot MAT programming This ACK code is returned after transfer of the program that performs writing to the user boot MAT. Error response H'C2 ERROR Error response H'C2 (1 byte): Error response to selection of user boot MAT programming ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error) (2) Selection of user MAT programming In response to the command for selecting programming of the user MAT, the boot program transfers the corresponding flash-writing program, i.e. the program for writing to the user MAT. Command H'43 Command H'43 (1 byte): Selects programming of the user MAT. Response H'06 Response H'06 (1 byte): Response to selection of user MAT programming This ACK code is returned after transfer of the program that performs writing to the user MAT. Page 822 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Error response H'C3 ERROR Error response H'C3 (1 byte): Error response to selection of user MAT programming ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error) 128-byte programming (3) In response to the 128-byte programming command, the boot program executes the flash-writing program transferred in response to the command to select programming of the user boot MAT or user MAT. Command H'50 Address for programming Data ... ... SUM Command H'50 (1 byte): 128-byte programming Address for programming (4 bytes): Address where programming starts This should be the address of a 128-byte boundary. [Example] H'00, H01, H'00, H'00: H'00010000 Programming data (n bytes): Data for programming The length of the programming data is the size returned in response to the programming size inquiry command. SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): Response to 128-byte programming The ACK code is returned on completion of the requested programming. Error response H'D0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 ERROR Page 823 of 964 SH7146 Group Section 19 Flash Memory Error response H'D0 (1 byte): Error response to 128-byte programming ERROR (1 byte): Error code H'11: Sum-check error H'2A: Address error (the address is not within the range for the selected MAT) H'53: Programming error (programming failed because of an error in programming) The specified address should be on a boundary corresponding to the unit of programming (programming size). For example, when programming 128 bytes of data, the lowest byte of the address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the host should transmit the data after padding the vacant bytes with H'FF. To terminate programming of a given MAT, send a 128-byte programming command with the address field H'FFFFFFFF. This informs the boot program that all data for the selected MAT have been sent; the boot program then waits for the next programming/erasure selection command. Command H'50 Address for programming SUM Command H'50 (1 byte): 128-byte programming Address for programming (4 bytes): Terminating code (H'FF, H'FF, H'FF, H'FF) SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): Response to 128-byte programming This ACK code is returned on completion of the requested programming. Error response H'D0 ERROR Error response H'D0 (1 byte): Error response to 128-byte programming ERROR (1 byte): Error code H'11: Sum-check error H'53: Programming error Page 824 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory * Erasure Erasure is performed by issuing the erasure selection command and then one or more block erasure commands. Firstly, the host sends the erasure selection command to select erasure; after that, it sends a block erasure command to actually erase a specific block. To erase multiple blocks, send further block erasure commands. To terminate erasure, the host should send a block erasure command with the block number H'FF. After this, the boot program waits for the next programming/erasure selection command. The sequence of erasure by the erasure selection command and block erasure command is shown in figure 19.26. Host Boot program Erasure selection (H'48) Transfer the program that performs erasure ACK Erasure (block number) Repeat Erasure ACK Erasure (H'FF) ACK Figure 19.26 Sequence of Erasure R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 825 of 964 SH7146 Group Section 19 Flash Memory Select erasure (1) In response to the erasure selection command, the boot program transfers the program that performs erasure, i.e. erases data in the user MAT. Command H'48 Command H'48 (1 byte): Selects erasure. Response H'06 Response H'06 (1 byte): Response to selection of erasure This ACK code is returned after transfer of the program that performs erasure. Error response H'C8 ERROR Error response H'C8 (1 byte): Error response to selection of erasure ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error.) (2) Block erasure In response to the block erasure command, the boot program erases the data in a specified block of the user MAT. Command H'58 Size Block number SUM Command H'58 (1 byte): Erasure of a block Size (1 byte): The number of characters in the block number field (fixed at 1) Block number (1 byte): Block number of the block to be erased SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): Response to the block erasure command This ACK code is returned when the block has been erased. Page 826 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Error response H'D8 ERROR Error response H'D8 (1 byte): Error response to the block erasure command ERROR (1 byte): Error code H'11: Sum-check error H'29: Block number error (the specified block number is incorrect.) H'51: Erasure error (an error occurred during erasure.) On receiving the command with H'FF as the block number, the boot program stops erasure processing and waits for the next programming/erasure selection command. Command H'58 Size Block number SUM Command H'58 (1 byte): Erasure of a block Size (1 byte): The number of characters in the block number field (fixed at 1) Block number (1 byte): H'FF (erasure terminating code) SUM (1 byte): Checksum Response H'06 Response H'06 (1 byte): ACK code to indicate response to the request for termination of erasure To perform erasure again after having issued the command with the block number specified as H'FF, execute the process from the selection of erasure. * Memory read In response to the memory read command, the boot program returns the data from the specified address. Command H'52 Size Area Amount to read First address for reading SUM Command H'52 (1 byte): Memory read Size (1 byte): The total length of the area, address for reading, and amount to read fields (fixed value of 9) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 827 of 964 SH7146 Group Section 19 Flash Memory Area (1 byte): H'00: User boot MAT H'01: User MAT An incorrect area specification will produce an address error. Address where reading starts (4 bytes) Amount to read (4 bytes): The amount of data to be read SUM (1 byte): Checksum Response H'52 Amount to read Data ... SUM Response H'52 (1 byte): Response to the memory read command Amount to read (4 bytes): The amount to read as specified in the memory read command Data (n bytes): The specified amount of data read out from the specified address SUM (1 byte): Checksum Error response H'D2 ERROR Error response H'D2 (1 byte): Error response to memory read command ERROR (1 byte): Error code H'11: Sum-check error H'2A: Address error (the address specified for reading is beyond the range of the MAT) H'2B: Size error (the specified amount is greater than the size of the MAT, the last address for reading as calculated from the specified address for the start of reading and the amount to read is beyond the MAT area, or "0" was specified as the amount to read) Page 828 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory * Sum checking of the user boot MAT In response to the command for sum checking of the user boot MAT, the boot program adds all bytes of data in the user boot MAT and returns the result. Command H'4A Command H'4A (1 byte): Sum checking of the user boot MAT Response H'5A Size Checksum for the MAT SUM Response H'5A (1 byte): Response to sum checking of the user boot MAT Size (1 byte): The number of characters in the checksum for the MAT (fixed at 4) Checksum for the MAT (4 bytes): Result of checksum calculation for the user boot MAT: the total of all data in the MAT, in byte units. SUM (1 byte): Checksum (for the transmitted data) * Sum checking of the user MAT In response to the command for sum checking of the user MAT, the boot program adds all bytes of data in the user MAT and returns the result. Command H'4B Command H'4B (1 byte): Sum checking of the user MAT Response H'5B Size Checksum for the MAT SUM Response H'5B (1 byte): Response to sum checking of the user MAT Size (1 byte): The number of characters in the checksum for the MAT (fixed at 4) Checksum for the MAT (4 bytes): Result of checksum calculation for the user MAT: the total of all data in the MAT, in byte units. SUM (1 byte): Checksum (for the transmitted data) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 829 of 964 SH7146 Group Section 19 Flash Memory * Blank checking of the user boot MAT In response to the command for blank checking of the user boot MAT, the boot program checks to see if the whole of the user boot MAT is blank; the value returned indicates the result. Command H'4C Command H'4C (1 byte): Blank checking of the user boot MAT Response H'06 Response H'06 (1 byte): Response to blank checking of the user boot MAT This ACK code is returned when the whole area is blank (all bytes are H'FF). Error response H'CC H'52 Error response H'CC (1 byte): Error response to blank checking of the user boot MAT Error code H'52 (1 byte): Non-erased error * Blank checking of the user MAT In response to the command for blank checking of the user MAT, the boot program checks to see if the whole of the user MAT is blank; the value returned indicates the result. Command H'4D Command H'4D (1 byte): Blank checking of the user boot MAT Response H'06 Response H'06 (1 byte): Response to blank checking of the user MAT The ACK code is returned when the whole area is blank (all bytes are H'FF). Error response H'CD H'52 Error response H'CD (1 byte): Error response to blank checking of the user MAT Error code H'52 (1 byte): Non-erased error Page 830 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory * Inquiry on boot program state In response to the command for inquiry on the state of the boot program, the boot program returns an indicator of its current state and error information. This inquiry can be made in the inquiry-andselection state or the programming/erasure state. Command H'4F Command H'4F (1 byte): Inquiry on boot program state Response H'5F Size STATUS ERROR SUM Response H'5F (1 byte): Response to the inquiry regarding boot-program state Size (1 byte): The number of characters in STATUS and ERROR (fixed at 2) STATUS (1 byte): State of the standard boot program See table 19.15, Status Codes. ERROR (1 byte): Error state (indicates whether the program is in normal operation or an error has occurred) ERROR = 0: Normal ERROR 0: Error See table 19.16, Error Codes. SUM (1 byte): Checksum Table 19.15 Status Codes Code Description H'11 Waiting for device selection H'12 Waiting for clock-mode selection H'13 Waiting for bit-rate selection H'1F Waiting for transition to programming/erasure status (bit-rate selection complete) H'31 Erasing the user MAT or user boot MAT H'3F Waiting for programming/erasure selection (erasure complete) H'4F Waiting to receive data for programming (programming complete) H'5F Waiting for erasure block specification (erasure complete) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 831 of 964 Section 19 Flash Memory SH7146 Group Table 19.16 Error Codes Code Description H'00 No error H'11 Sum check error H'21 Non-matching device code error H'22 Non-matching clock mode error H'24 Bit-rate selection failure H'25 Input frequency error H'26 Frequency multiplier error H'27 Operating frequency error H'29 Block number error H'2A Address error H'2B Data length error (size error) H'51 Erasure error H'52 Non-erased error H'53 Programming error H'54 Selection processing error H'80 Command error H'FF Bit-rate matching acknowledge error 19.9.2 Areas for Storage of the Procedural Program and Data for Programming In the descriptions in the previous section, storable areas for the programming/erasing procedure programs and program data are assumed to be in on-chip RAM. However, the procedure programs and data can be stored in and executed from other areas (e.g. external address space) as long as the following conditions are satisfied. 1. The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. 2. The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure this area is reserved. 3. Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. 4. The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been decided. When in a mode in which the external address space Page 832 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory is not accessible, such as single-chip mode, the required procedure programs, interrupt vector table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. 5. The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip memory other than flash memory or the external address space. 6. After programming/erasing, access to flash memory is inhibited until FKEY is cleared. A reset state (RES = 0) for more than at least 100 s must be taken when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state during programming/erasing are inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. 7. Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in user boot mode. The program which switches the MATs should be executed from the on-chip RAM. For details, see section 19.8.1, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching the MATs. 8. When the program data storage area indicated by the FMPDR parameter in the programming processing is within the flash memory area, an error will occur. Therefore, temporarily transfer the program data to on-chip RAM to change the address set in FMPDR to an address other than flash memory. Based on these conditions, tables 19.17 and 19.18 show the areas in which the program data can be stored and executed according to the operation type and mode. Table 19.17 Executable MAT Initiated Mode Operation User Program Mode User Boot Mode* Programming Table 19.18 (1) Table 19.18 (3) Erasing Table 19.18 (2) Table 19.18 (4) Note: * Programming/Erasing is possible to user MATs. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 833 of 964 SH7146 Group Section 19 Flash Memory Table 19.18 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Programming procedure Note: * Selected MAT Item OnChip RAM User MAT External Space User MAT Embedded Program Storage MAT Program data storage area X* -- -- Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) X X Key register clearing Judging download result Download error processing Setting initialization parameters Initialization X X Judging initialization result Initialization error processing Interrupt processing routine X Writing H'5A to key register Setting programming parameters X Programming X X Judging programming result X Programming error processing X Key register clearing X If the data has been transferred to on-chip RAM in advance, this area can be used. Page 834 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Table 19.18 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT OnChip RAM User MAT External Space User MAT Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) X X Key register clearing Judging download result Download error processing Setting initialization parameters Initialization X X X Writing H'5A to key register Setting erasure parameters X Erasure X X Judging erasure result X Erasing error processing X Key register clearing X Item Erasing Judging initialization result proceInitialization error processing dure Interrupt processing routine R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Embedded Program Storage MAT Page 835 of 964 SH7146 Group Section 19 Flash Memory Table 19.18 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area External Space User MAT User Boot MAT -- -- OnChip RAM User Boot MAT Program data storage area X* Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) X X Key register clearing Judging download result Download error processing Setting initialization parameters Initialization X X Judging initialization result Initialization error processing Interrupt processing routine X Switching MATs by FMATS X X Writing H'5A to Key Register X Item Programming procedure Selected MAT Page 836 of 964 1 Embedded Program Storage Area -- R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Table 19.18 (3) Usable Area for Programming in User Boot Mode (cont) Storable/Executable Area OnChip RAM User Boot MAT External Space User MAT Setting programming parameters X Programming X X Judging programming result X Programming error processing X* Key register clearing X Switching MATs by FMATS X X Item Programming procedure Selected MAT 2 User Boot MAT Embedded Program Storage Area Notes: 1. If the data has been transferred to on-chip RAM in advance, this area can be used. 2. If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 837 of 964 SH7146 Group Section 19 Flash Memory Table 19.18 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT User Boot MAT OnChip RAM User Boot MAT External Space Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) X X Key register clearing Judging download result Download error processing X X Judging initialization result Initialization error processing Interrupt processing routine X Switching MATs by FMATS X X Writing H'5A to key register X Setting erasure parameters X Item Erasing Setting initialization proce- parameters dure Initialization Page 838 of 964 User MAT Embedded Program Storage Area R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 19 Flash Memory Table 19.18 (4) Usable Area for Erasure in User Boot Mode (cont) Storable/Executable Area Item OnChip RAM User Boot MAT External Space User MAT Erasure X X Judging erasure result X X* X X X Erasing Erasing error proce- processing dure Key register clearing Switching MATs by FMATS Note: Selected MAT * Embedded Program Storage Area If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 User Boot MAT Page 839 of 964 Section 19 Flash Memory 19.10 SH7146 Group Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip MCU device type (F-ZTATxxxx). Page 840 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 20 Masked ROM Section 20 Masked ROM This LSI is available with 256 kbytes of on-chip masked ROM. The on-chip ROM is connected to the CPU and data transfer controller (DTC) through a 32-bit data bus (figure 20.1). The CPU and DTC can access the on-chip ROM in 8, 16, and 32-bit widths. Data in the on-chip ROM can always be accessed from the CPU in one cycle. Internal data bus (32 bits) H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 On-chip ROM H'0003FFFC H'0003FFFD H'0003FFFE H'0003FFFF Figure 20.1 Masked ROM Block Diagram The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins FWE, MD1, and MD0. If you are using the on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated to addresses H'00000000 to H'0003FFFF of memory area 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 841 of 964 Section 20 Masked ROM 20.1 Usage Note 20.1.1 Module Standby Mode Setting SH7146 Group Access to the on-chip ROM can be enabled/disabled by the standby control register. The initial value enables the on-chip ROM operation. On-chip ROM access is disabled by setting the module standby mode. For details, see section 22, Power-Down Modes. Page 842 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 21 RAM Section 21 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus (L bus), and to the data transfer controller (DTC) by a 32-bit data bus (I bus), enabling 8, 16, or 32-bit width access to data in the on-chip RAM. The on-chip RAM is allocated to different addresses according to each product as shown in figure 21.1, and the on-chip RAM is divided into page 0 and page 1 based on the addresses. The on-chip RAM can be accessed from the CPU (via the L bus) and DTC (via the I bus). When different buses request to access the same page simultaneously, the priority becomes I bus (DTC) > L bus (CPU). Since such kind of conflict degrades the RAM access performance, software should be created so as to avoid conflicts. For example, conflict does not occur when the buses access different pages. An access from the L bus (CPU) is a 1-cycle access as long as page conflict does not occur. The number of bus cycles in accesses from the I bus (DTC) differ depending on the ratio between the internal clock (I) and bus clock (B), and the operating state of the DTC. The contents of the on-chip RAM are retained in sleep mode or software standby mode, and at a power-on reset or manual reset. However, the contents of the on-chip RAM are not retained in deep software standby mode. The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control register (RAMCR). For details on the RAM control register (RAMCR), refer to section 22.3.7, RAM Control Register (RAMCR). H'FFFF9000 H'FFFF9FFF H'FFFFA000 H'FFFFAFFF Page 0 4 kbytes Page 1 4 kbytes SH7146/SH7149 (8 kbytes) Figure 21.1 On-chip RAM Addresses R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 843 of 964 RAM0200A_010020030800 Section 21 RAM 21.1 Usage Notes 21.1.1 Module Standby Mode Setting SH7146 Group RAM can be enabled/disabled by the standby control register. The initial value enables RAM operation. RAM access is disabled by setting the module standby mode. For details, see section 22, Power-Down Modes. 21.1.2 Address Error When an address error in write access to the on-chip RAM occurs, the contents of the on-chip RAM may be corrupted. 21.1.3 Initial Values in RAM After power has been supplied, initial values in RAM remain undefined until RAM is written. Page 844 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 22 Power-Down Modes Section 22 Power-Down Modes This LSI supports the following power-down modes: sleep mode, software standby mode, deep software standby mode, and module standby mode. 22.1 Features * Supports sleep mode, software standby mode, module standby mode, and deep software standby mode. 22.1.1 Types of Power-Down Modes This LSI has the following power-down modes. * Sleep mode * Software standby mode * Deep software standby mode * Module standby mode Table 22.1 shows the methods to make a transition from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 845 of 964 SH7146 Group Section 22 Power-Down Modes Table 22.1 States of Power-Down Modes State CPU CPG CPU Register Mode Transition Method Sleep Runs Halts Held Execute SLEEP instruction with STBY bit in STBCR1 cleared to 0. Halts Halts Held Software Execute SLEEP standby instruction with STBY bit in STBCR1 and STBYMD bit in STBCR6 set to 1. On-Chip Memory On-Chip Peripheral Modules Canceling Procedure Runs Run * Reset Halts (contents retained) Halt * Interrupt by NMI or Set MSTP bits in STBCR2 to STBCR5 to 1. Runs Runs Held Power-on reset by the RES pin Halts Halts Undefined Halts Deep Execute SLEEP (contents software instruction with STBY undefined) standby bit in STBCR1 set to 1 and STBYMD bit in STBCR6 cleared to 0. Module standby IRQ * Halt Specified Specified module halts module halts (contents retained) * Power-on reset by the RES pin * Clear MSTP bit to 0 * Power-on reset (for modules whose MSTP bit has an initial value of 0) Note: For details on the states of on-chip peripheral module registers in each mode, refer to section 23.3, Register States in Each Operating Mode. For details on the pin states in each mode, refer to appendix A, Pin States. Page 846 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 22.2 Section 22 Power-Down Modes Input/Output Pins Table 22.2 lists the pins used for the power-down modes. Table 22.2 Pin Configuration Pin Name Symbol I/O Description Power-on reset RES Input Power-on reset input signal. Power-on reset by low level. Manual reset MRES Input Manual reset input signal. Manual reset by low level. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 847 of 964 SH7146 Group Section 22 Power-Down Modes 22.3 Register Descriptions There are following registers used for the power-down modes. For details on the addresses of these registers and the states of these registers in each processing state, see section 23, List of Registers. Table 22.3 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Standby control register 1 STBCR1 R/W H'00 H'FFFFE802 8 Standby control register 2 STBCR2 R/W H'38 H'FFFFE804 8 Standby control register 3 STBCR3 R/W H'FF H'FFFFE806 8 Standby control register 4 STBCR4 R/W H'FF H'FFFFE808 8 Standby control register 5 STBCR5 R/W H'03 H'FFFFE80A 8 Standby control register 6 STBCR6 R/W H'00 H'FFFFE80C 8 RAM control register RAMCR R/W H'10 H'FFFFE880 8 22.3.1 Standby Control Register 1 (STBCR1) STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode. Bit: 7 6 5 4 3 2 1 STBY - - - - - - - Initial value: 0 R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 STBY 0 R/W Standby 0 Specifies transition to software standby mode. 0: Executing SLEEP instruction makes this LSI sleep mode 1: Executing SLEEP instruction makes this LSI software standby mode or deep software standby mode Page 848 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 22.3.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: 7 6 5 4 3 2 1 0 MSTP 7 MSTP 6 - MSTP 4* - - - - Initial value: 0 R/W: R/W 0 R/W 1 R 1 R/W 1 R 0 R 0 R 0 R Note: * The function is available only in the F-ZTAT version. In the masked ROM version, this bit is used as a reserved bit. Bit Bit Name Initial Value R/W 7 MSTP7 0 R/W Description Module Stop Bit 7 When this bit is set to 1, the supply of the clock to the RAM is halted. 0: RAM operates 1: Clock supply to RAM halted 6 MSTP6 0 R/W Module Stop Bit 6 When this bit is set to 1, the supply of the clock to the ROM is halted. 0: ROM operates 1: Clock supply to ROM halted 5 1 R Reserved This bit is always read as 1. The write value should always be 1. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 849 of 964 SH7146 Group Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 4 MSTP4* 1 R/W Module Stop Bit 4 When this bit is set to 1, the supply of the clock to the DTC is halted. 0: DTC operates 1: Clock supply to the DTC halted 3 1 R Reserved This bit is always read as 1. The write value should always be 1. 2 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: 22.3.3 * The function is available only in the F-ZTAT version. In the masked ROM version, this bit is used as a reserved bit. Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - MSTP 13 MSTP 12 MSTP 11 - - - 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R 1 R 1 R Bit Bit Name Initial Value R/W Description 7, 6 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 MSTP13 1 R/W Module Stop Bit 13 When this bit is set to 1, the supply of the clock to the SCI_2 is halted. 0: SCI_2 operates 1: Clock supply to SCI_2 halted Page 850 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 4 MSTP12 1 R/W Module Stop Bit 12 When this bit is set to 1, the supply of the clock to the SCI_1 is halted. 0: SCI_1 operates 1: Clock supply to SCI_1 halted 3 MSTP11 1 R/W Module Stop Bit 11 When this bit is set to 1, the supply of the clock to the SCI_0 is halted. 0: SCI_0 operates 1: Clock supply to SCI_0 halted 2 to 0 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 22.3.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: 7 6 5 4 3 2 1 0 MSTP 23 MSTP 22 MSTP 21 - - MSTP 18 MSTP 17 MSTP 16 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R 1 R 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 MSTP23 1 R/W Module Stop Bit 23 When this bit is set to 1, the supply of the clock to the MTU2S is halted. 0: MTU2S operates 1: Clock supply to MTU2S halted R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 851 of 964 SH7146 Group Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 MSTP22 1 R/W Module Stop Bit 22 When this bit is set to 1, the supply of the clock to the MTU2 is halted. 0: MTU2 operates 1: Clock supply to MTU2 halted 5 MSTP21 1 R/W Module Stop Bit 21 When this bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT operates 1: Clock supply to CMT halted 4, 3 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 2 MSTP18 1 R/W Module Stop Bit 18 When this bit is set to 1, the supply of the clock to the A/D_2 is halted. 0: A/D_2 operates 1: Clock supply to A/D_2 halted 1 MSTP17 1 R/W Module Stop Bit 17 When this bit is set to 1, the supply of the clock to the A/D_1 is halted. 0: A/D_1 operates 1: Clock supply to A/D_1 halted 0 MSTP16 1 R/W Module Stop Bit 16 When this bit is set to 1, the supply of the clock to the A/D_0 is halted. 0: A/D_0 operates 1: Clock supply to A/D_0 halted Page 852 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 22.3.5 Section 22 Power-Down Modes Standby Control Register 5 (STBCR5) STBCR5 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - MSTP 25 MSTP 24 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 MSTP25 1 R/W Module Stop Bit 25 When this bit is set to 1, the supply of the clock to the AUD is halted. 0: AUD operates 1: Clock supply to AUD halted 0 MSTP24 1 R/W Module Stop Bit 24 When this bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC operates 1: Clock supply to UBC halted R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 853 of 964 SH7146 Group Section 22 Power-Down Modes 22.3.6 Standby Control Register 6 (STBCR6) STBCR6 is an 8-bit readable/writable register that specifies the state of the power-down modes. Bit: 7 6 5 4 3 2 1 0 AUD SRST HIZ - - - - STBY MD - 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R Initial value: 0 R/W: R/W Bit Bit Name Initial Value R/W Description 7 AUDSRST 0 R/W AUD Software Reset This bit controls the AUD reset by software. When 0 is written to AUDSRST, the AUD module shifts to the power-on reset state. 0: Shifts to the AUD reset state 1: Clears the AUD reset When setting this bit to 1, MSTP25 in STBCR5 should be 0. 6 HIZ 0 R/W Port High-Impedance In software standby mode, this bit selects whether the pin state is retained or changed to high-impedance. 0: In software standby mode, the pin state is retained 1: In software standby mode, the pin state is changed to high-impedance 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 STBYMD 0 R/W Software Standby Mode Select This bit selects a transition to software standby mode or deep software standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR1. 0: Transition to deep software standby mode 1: Transition to software standby mode 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 854 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 22.3.7 Section 22 Power-Down Modes RAM Control Register (RAMCR) RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM. Bit: Initial value: R/W: 7 6 5 4 3 2 1 - - - RAME - - - - 0 R 0 R 0 R 1 R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 5 All 0 R Reserved 0 These bits are always read as 0. The write value should always be 0. 4 RAME 1 R/W RAM Enable This bit enables/disables the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled When this bit is cleared to 0, the access to the on-chip RAM is disabled. In this case, an undefined value is returned when reading or fetching the data or instruction from the on-chip RAM, and writing to the onchip RAM is ignored. When RAME is cleared to 0 to disable the on-chip RAM, an instruction to access the on-chip RAM should not be set next to the instruction to write RAMCR. If such an instruction is set, normal access is not guaranteed. When RAME is set to 1 to enable the on-chip RAM, an instruction to read RAMCR should be set next to the instruction to write to RAMCR. If an instruction to access the on-chip RAM is set next to the instruction to write to RAMCR, normal access is not guaranteed. 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 855 of 964 Section 22 Power-Down Modes 22.4 Sleep Mode 22.4.1 Transition to Sleep Mode SH7146 Group Executing the SLEEP instruction when the STBY bit in STBCR1 is 0 causes a transition from the program execution state to sleep mode. However, sleep mode cannot be entered when the bus is released (low-level input to BREQ pin). Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to operate. 22.4.2 Canceling Sleep Mode Sleep mode is canceled by a reset. Do not cancel sleep mode with an interrupt. Canceling with Reset: Sleep mode is canceled by a power-on reset with the RES pin, a manual reset with the MRES pin, or an internal power-on/manual reset by WDT. Page 856 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 22.5 Software Standby Mode 22.5.1 Transition to Software Standby Mode Section 22 Power-Down Modes This LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR1 and the STBYMD bit in STBCR6 are set to 1. However, software standby mode cannot be entered when the bus is released (low-level input to BREQ pin). Execute the SLEEP instruction after halting the DTC. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The contents of the CPU registers and the data of the on-chip RAM remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. For details on the states of onchip peripheral module registers in software standby mode, refer to section 23.3, Register States in Each Operating Mode. For details on the pin states in software standby mode, refer to appendix A, Pin States. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT. 2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to appropriate values to secure the specified oscillation settling time. 3. If the DTC is operating, stop its operation. 4. If the bus is released (low-level input to BREQ pin), acquire the bus mastership (high-level input to BREQ pin). 5. After setting the STBY bit in STBCR1 and the STBYMD bit in STBCR6 to 1, execute the SLEEP instruction. 6. Software standby mode is entered and the clocks within this LSI are halted. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 857 of 964 Section 22 Power-Down Modes 22.5.2 SH7146 Group Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI, IRQ) or a reset. Canceling with Interrupt: The WDT can be used for hot starts. When an NMI or IRQ interrupt (edge detection) is detected, the clock will be supplied to the entire LSI and software standby mode will be canceled after the time set in the timer control/status register of the WDT has elapsed. Interrupt exception handling is then executed. When the priority level of an IRQ interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing software standby mode from being canceled. When falling-edge detection is selected for the NMI pin, drive the NMI pin high before making a transition to software standby mode. When rising-edge detection is selected for the NMI pin, drive the NMI pin low before making a transition to software standby mode. Similarly, when falling-edge detection is selected for the IRQ pin, drive the IRQ pin high before making a transition to software standby mode. When rising-edge detection is selected for the IRQ pin, drive the IRQ pin low before making a transition to software standby mode. Canceling with Power-on Reset: Software standby mode is canceled by a power-on reset with the RES pin. Keep the RES pin low until the clock oscillation settles. Page 858 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 22.6 Deep Software Standby Mode 22.6.1 Transition to Deep Software Standby Mode Section 22 Power-Down Modes This LSI shifts from a program execution state to deep software standby mode by executing the SLEEP instruction when the STBY bit in STBCR1 is 1 and the STBYMD bit in STBCR6 is 0. However, deep software standby mode cannot be entered when the bus is released (low-level input to BREQ pin). Execute the SLEEP instruction after halting the DTC. In deep software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. Furthermore, the internal power supply of this LSI is turned off. The contents of the CPU registers and the data of the on-chip RAM become undefined. The registers of on-chip peripheral modules are initialized. For details on the pin states in deep software standby mode, refer to appendix A, Pin States. The procedure for a transition to deep software standby mode is as follows: 1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT. 2. If the DTC is operating, stop its operation. 3. If the bus is released (low-level input to BREQ pin), acquire the bus mastership (high-level input to BREQ pin). 4. After setting the STBY bit in STBCR1 to 1 and clearing the STBYMD bit in STBCR6 to 0, execute the SLEEP instruction. 5. Deep software standby mode is entered, the clocks within this LSI are halted, and the internal power supply of this LSI is turned off. 22.6.2 Canceling Deep Software Standby Mode Deep software standby mode is canceled by a power-on reset with the RES pin. Keep the RES pin low until the clock oscillation settles. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 859 of 964 Section 22 Power-Down Modes 22.7 Module Standby Mode 22.7.1 Transition to Module Standby Mode SH7146 Group Setting the MSTP bits in the standby control registers (STBCR2 to STBCR5) to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode. Do not access registers of an on-chip peripheral module which has been set to enter module standby mode. For details on the states of on-chip peripheral module registers in module standby mode, refer to section 23.3, Register States in Each Operating Mode. 22.7.2 Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits in STBCR2 to STBCR5 to 0. The module standby function can be canceled by a power-on reset for modules whose MSTP bit has an initial value of 0. Page 860 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 22 Power-Down Modes 22.8 Usage Note 22.8.1 Current Consumption while Waiting for Oscillation to be Stabilized The current consumption while waiting for oscillation to be stabilized is higher than that while oscillation is stabilized. 22.8.2 Executing the SLEEP Instruction Apply either of the following measures before executing the SLEEP instruction to initiate the transition to sleep mode or software standby mode. Measure A: Stop the operation of the DTC and the generation of interrupts from on-chip peripheral modules, IRQ interrupts, and the NMI interrupt before executing the SLEEP instruction. Measure B: Change the value in FRQCR to the initial value, H'36DB, and then dummy-read FRQCR twice before executing the SLEEP instruction. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 861 of 964 Section 22 Power-Down Modes Page 862 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Section 23 List of Registers This section gives information on internal I/O registers. The contents of this section are as follows: 1. Register Address Table (in the order from a lower address) Registers are listed in the order from lower allocated addresses. As for reserved addresses, the register name column is indicated with . Do not access reserved addresses. As for 16- or 32-bit address, the MSB addresses are shown. The list is classified according to module names. The numbers of access cycles are given. 2. Register Bit Table Bit configurations are shown in the order of the register address table. As for reserved bits, the bit name column is indicated with . As for the blank column of the bit names, the whole register is allocated to the counter or data. As for 16- or 32-bit registers, bits are indicated from the MSB. 3. Register State in Each Operating Mode Register states are listed in the order of the register address table. Register states in the basic operating mode are shown. As for modules including their specific states such as reset, see the sections of those modules. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 863 of 964 SH7146 Group Section 23 List of Registers 23.1 Register Address Table (In the Order from Lower Addresses) Access sizes are indicated with the number of bits. Access states are indicated with the number of specified reference clock states. These values are those at 8-bit access (B), 16-bit access (W), or 32-bit access (L). Note: Access to undefined or reserved addresses is prohibited. Correct operation cannot be guaranteed if these addresses are accessed. Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Serial mode register_0 SCSMR_0 8 H'FFFFC000 SCI 8 P reference 16 bits Bit rate register_0 SCBRR_0 8 H'FFFFC002 (Channel 0) 8 B:2 Serial control register_0 SCSCR_0 8 H'FFFFC004 8 Transmit data register_0 SCTDR_0 8 H'FFFFC006 8 Serial status register_0 SCSSR_0 8 H'FFFFC008 8 Receive data register_0 SCRDR_0 8 H'FFFFC00A 8 Serial direction control register_0 SCSDCR_0 8 H'FFFFC00C 8 Serial port register_0 SCSPTR_0 8 H'FFFFC00E 8 Serial mode register_1 SCSMR_1 8 H'FFFFC080 SCI 8 P reference Bit rate register_1 SCBRR_1 8 H'FFFFC082 (Channel 1) 8 B:2 Serial control register_1 SCSCR_1 8 H'FFFFC084 8 Transmit data register_1 SCTDR_1 8 H'FFFFC086 8 Serial status register_1 SCSSR_1 8 H'FFFFC088 8 Receive data register_1 SCRDR_1 8 H'FFFFC08A 8 Serial direction control register_1 SCSDCR_1 8 H'FFFFC08C 8 Serial port register_1 SCSPTR_1 8 H'FFFFC08E 8 Serial mode register_2 SCSMR_2 8 H'FFFFC100 SCI 8 P reference Bit rate register_2 SCBRR_2 8 H'FFFFC102 (Channel 2) 8 B:2 Serial control register_2 SCSCR_2 8 H'FFFFC104 8 Transmit data register_2 SCTDR_2 8 H'FFFFC106 8 Serial status register_2 SCSSR_2 8 H'FFFFC108 8 Receive data register_2 SCRDR_2 8 H'FFFFC10A 8 Serial direction control register_2 SCSDCR_2 8 H'FFFFC10C 8 Serial port register_2 SCSPTR_2 8 H'FFFFC10E 8 Page 864 of 964 16 bits 16 bits R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Timer control register_3 TCR_3 8 H'FFFFC200 MTU2 8, 16, 32 MP reference 16 bits Timer control register_4 TCR_4 8 H'FFFFC201 8 B:2 Timer mode register_3 TMDR_3 8 H'FFFFC202 8, 16 W:2 Timer mode register_4 TMDR_4 8 H'FFFFC203 8 L:4 Timer I/O control register H_3 TIORH_3 8 H'FFFFC204 8, 16, 32 Timer I/O control register L_3 TIORL_3 8 H'FFFFC205 8 Timer I/O control register H_4 TIORH_4 8 H'FFFFC206 8, 16 Timer I/O control register L_4 TIORL_4 8 H'FFFFC207 8 Timer interrupt enable register_3 TIER_3 8 H'FFFFC208 8, 16 Timer interrupt enable register_4 TIER_4 8 H'FFFFC209 8 Timer output master enable register TOER 8 H'FFFFC20A 8 Timer gate control register TGCR 8 H'FFFFC20D 8 Timer output control register 1 TOCR1 8 H'FFFFC20E 8, 16 Timer output control register 2 TOCR2 8 H'FFFFC20F 8 Timer counter_3 TCNT_3 16 H'FFFFC210 16, 32 Timer counter_4 TCNT_4 16 H'FFFFC212 16 Timer cycle data register TCDR 16 H'FFFFC214 16, 32 Timer dead time data register TDDR 16 H'FFFFC216 16 Timer general register A_3 TGRA_3 16 H'FFFFC218 16, 32 Timer general register B_3 TGRB_3 16 H'FFFFC21A 16 Timer general register A_4 TGRA_4 16 H'FFFFC21C 16, 32 Timer general register B_4 TGRB_4 16 H'FFFFC21E 16 Timer sub-counter TCNTS 16 H'FFFFC220 16, 32 Timer cycle buffer register TCBR 16 H'FFFFC222 16 Timer general register C_3 TGRC_3 16 H'FFFFC224 16, 32 Timer general register D_3 TGRD_3 16 H'FFFFC226 16 Timer general register C_4 TGRC_4 16 H'FFFFC228 16, 32 Timer general register D_4 TGRD_4 16 H'FFFFC22A 16 Timer status register_3 TSR_3 8 H'FFFFC22C 8, 16 Timer status register_4 TSR_4 8 H'FFFFC22D 8 Timer interrupt skipping set register TITCR 8 H'FFFFC230 8, 16 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 865 of 964 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Timer interrupt skipping counter TITCNT 8 H'FFFFC231 MTU2 8 MP reference 16 bits Timer buffer transfer set register TBTER 8 H'FFFFC232 8 B:2 Timer dead time enable register TDER 8 H'FFFFC234 8 W:2 Timer output level buffer register TOLBR 8 H'FFFFC236 8 L:4 Timer buffer operation transfer mode TBTM_3 8 H'FFFFC238 8, 16 TBTM_4 8 H'FFFFC239 8 TADCR 16 H'FFFFC240 16 TADCORA_4 16 H'FFFFC244 16, 32 TADCORB_4 16 H'FFFFC246 16 TADCOBRA_4 16 H'FFFFC248 16, 32 TADCOBRB_4 16 H'FFFFC24A 16 Timer waveform control register TWCR 8 H'FFFFC260 8 Timer start register TSTR 8 H'FFFFC280 8, 16 Timer synchronous register TSYR 8 H'FFFFC281 8 Timer counter synchronous start TCSYSTR 8 H'FFFFC282 8 Timer read/write enable register TRWER 8 H'FFFFC284 8 Timer control register_0 TCR_0 8 H'FFFFC300 8, 16, 32 Timer mode register_0 TMDR_0 8 H'FFFFC301 8 Timer I/O control register H_0 TIORH_0 8 H'FFFFC302 8, 16 Timer I/O control register L_0 TIORL_0 8 H'FFFFC303 8 Timer interrupt enable register_0 TIER_0 8 H'FFFFC304 8, 16, 32 Timer status register_0 TSR_0 8 H'FFFFC305 8 Timer counter_0 TCNT_0 16 H'FFFFC306 16 Timer general register A_0 TGRA_0 16 H'FFFFC308 16, 32 Timer general register B_0 TGRB_0 16 H'FFFFC30A 16 register_3 Timer buffer operation transfer mode register_4 Timer A/D converter start request control register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4 register Page 866 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Timer general register C_0 TGRC_0 16 H'FFFFC30C MTU2 16, 32 MP reference 16 bits Timer general register D_0 TGRD_0 16 H'FFFFC30E 16 B:2 Timer general register E_0 TGRE_0 16 H'FFFFC320 16, 32 W:2 Timer general register F_0 TGRF_0 16 H'FFFFC322 16 L:4 Timer interrupt enable register 2_0 TIER2_0 8 H'FFFFC324 8, 16 Timer status register 2_0 TSR2_0 8 H'FFFFC325 8 Timer buffer operation transfer mode TBTM_0 8 H'FFFFC326 8 Timer control register_1 TCR_1 8 H'FFFFC380 8, 16 Timer mode register_1 TMDR_1 8 H'FFFFC381 8 Timer I/O control register_1 TIOR_1 8 H'FFFFC382 8 Timer interrupt enable register_1 TIER_1 8 H'FFFFC384 8, 16, 32 Timer status register_1 TSR_1 8 H'FFFFC385 8 Timer counter_1 TCNT_1 16 H'FFFFC386 16 Timer general register A_1 TGRA_1 16 H'FFFFC388 16, 32 Timer general register B_1 TGRB_1 16 H'FFFFC38A 16 Timer input capture control register TICCR 8 H'FFFFC390 8 Timer control register_2 TCR_2 8 H'FFFFC400 8, 16 Timer mode register_2 TMDR_2 8 H'FFFFC401 8 register_0 Timer I/O control register_2 TIOR_2 8 H'FFFFC402 8 Timer interrupt enable register_2 TIER_2 8 H'FFFFC404 8, 16, 32 Timer status register_2 TSR_2 8 H'FFFFC405 8 Timer counter_2 TCNT_2 16 H'FFFFC406 16 Timer general register A_2 TGRA_2 16 H'FFFFC408 16, 32 Timer general register B_2 TGRB_2 16 H'FFFFC40A 16 Timer counter U_5 TCNTU_5 16 H'FFFFC480 16, 32 Timer general register U_5 TGRU_5 16 H'FFFFC482 16 Timer control register U_5 TCRU_5 8 H'FFFFC484 8 Timer I/O control register U_5 TIORU_5 8 H'FFFFC486 8 Timer counter V_5 TCNTV_5 16 H'FFFFC490 16, 32 Timer general register V_5 TGRV_5 16 H'FFFFC492 16 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 867 of 964 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Timer control register V_5 TCRV_5 8 H'FFFFC494 MTU2 8 MP reference 16 bits Timer I/O control register V_5 TIORV_5 8 H'FFFFC496 8 B:2 Timer counter W_5 TCNTW_5 16 H'FFFFC4A0 16, 32 W:2 Timer general register W_5 TGRW_5 16 H'FFFFC4A2 16 L:4 Timer control register W_5 TCRW_5 8 H'FFFFC4A4 8 Timer I/O control register W_5 TIORW_5 8 H'FFFFC4A6 8 Timer status register_5 TSR_5 8 H'FFFFC4B0 8 Timer interrupt enable register_5 TIER_5 8 H'FFFFC4B2 8 Timer start register_5 TSTR_5 8 H'FFFFC4B4 8 Timer compare match clear register TCNTCMPCLR 8 H'FFFFC4B6 8 Timer control register_3S TCR_3S 8 H'FFFFC600 Timer control register_4S TCR_4S 8 Timer mode register_3S TMDR_3S Timer mode register_4S TMDR_4S Timer I/O control register H_3S MTU2S 8, 16, 32 MI reference H'FFFFC601 8 B:2 8 H'FFFFC602 8, 16 W:2 8 H'FFFFC603 8 L:4 TIORH_3S 8 H'FFFFC604 8, 16, 32 Timer I/O control register L_3S TIORL_3S 8 H'FFFFC605 8 Timer I/O control register H_4S TIORH_4S 8 H'FFFFC606 8, 16 Timer I/O control register L_4S TIORL_4S 8 H'FFFFC607 8 Timer interrupt enable register_3S TIER_3S 8 H'FFFFC608 8, 16 Timer interrupt enable register_4S TIER_4S 8 H'FFFFC609 8 Timer output master enable register S TOERS 8 H'FFFFC60A 8 Timer gate control register S TGCRS 8 H'FFFFC60D 8 Timer output control register 1S TOCR1S 8 H'FFFFC60E 8, 16 Timer output control register 2S TOCR2S 8 H'FFFFC60F 8 Timer counter_3S TCNT_3S 16 H'FFFFC610 16, 32 Timer counter_4S TCNT_4S 16 H'FFFFC612 16 Timer cycle data register S TCDRS 16 H'FFFFC614 16, 32 Timer dead time data register S TDDRS 16 H'FFFFC616 16 Timer general register A_3S TGRA_3S 16 H'FFFFC618 16, 32 Timer general register B_3S TGRB_3S 16 H'FFFFC61A 16 Timer general register A_4S TGRA_4S 16 H'FFFFC61C 16, 32 Page 868 of 964 16 bits R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Timer general register B_4S TGRB_4S 16 H'FFFFC61E MTU2S 16 MI reference 16 bits Timer sub-counter S TCNTSS 16 H'FFFFC620 16, 32 B:2 Timer cycle buffer register S TCBRS 16 H'FFFFC622 16 W:2 Timer general register C_3S TGRC_3S 16 H'FFFFC624 16, 32 L:4 Timer general register D_3S TGRD_3S 16 H'FFFFC626 16 Timer general register C_4S TGRC_4S 16 H'FFFFC628 16, 32 Timer general register D_4S TGRD_4S 16 H'FFFFC62A 16 Timer status register_3S TSR_3S 8 H'FFFFC62C 8, 16 Timer status register_4S TSR_4S 8 H'FFFFC62D 8 Timer interrupt skipping set register S TITCRS 8 H'FFFFC630 8, 16 Timer interrupt skipping counter S TITCNTS 8 H'FFFFC631 8 Timer buffer transfer set register S TBTERS 8 H'FFFFC632 8 Timer dead time enable register S TDERS 8 H'FFFFC634 8 Timer output level buffer register S TOLBRS 8 H'FFFFC636 8 Timer buffer operation transfer mode TBTM_3S 8 H'FFFFC638 8, 16 TBTM_4S 8 H'FFFFC639 8 TADCRS 16 H'FFFFC640 16 TADCORA_4S 16 H'FFFFC644 16, 32 TADCORB_4S 16 H'FFFFC646 16 TADCOBRA_4S 16 H'FFFFC648 16, 32 TADCOBRB_4S 16 H'FFFFC64A 16 TSYCRS 8 H'FFFFC650 8 register_3S Timer buffer operation transfer mode register_4S Timer A/D converter start request control register S Timer A/D converter start request cycle set register A_4S Timer A/D converter start request cycle set register B_4S Timer A/D converter start request cycle set buffer register A_4S Timer A/D converter start request cycle set buffer register B_4S Timer synchronous clear register S Timer waveform control register S TWCRS 8 H'FFFFC660 8 Timer start register S TSTRS 8 H'FFFFC680 8, 16 Timer synchronous register S TSYRS 8 H'FFFFC681 8 Timer read/write enable register S TRWERS 8 H'FFFFC684 8 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 869 of 964 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Timer counter U_5S TCNTU_5S 16 H'FFFFC880 MTU2S 16, 32 MI reference 16 bits Timer general register U_5S TGRU_5S 16 H'FFFFC882 16 B:2 Timer control register U_5S TCRU_5S 8 H'FFFFC884 8 W:2 Timer I/O control register U_5S TIORU_5S 8 H'FFFFC886 8 L:4 Timer counter V_5S TCNTV_5S 16 H'FFFFC890 16, 32 Timer general register V_5S TGRV_5S 16 H'FFFFC892 16 Timer control register V_5S TCRV_5S 8 H'FFFFC894 8 Timer I/O control register V_5S TIORV_5S 8 H'FFFFC896 8 Timer counter W_5S TCNTW_5S 16 H'FFFFC8A0 16, 32 Timer general register W_5S TGRW_5S 16 H'FFFFC8A2 16 Timer control register W_5S TCRW_5S 8 H'FFFFC8A4 8 Timer I/O control register W_5S TIORW_5S 8 H'FFFFC8A6 8 Timer status register_5S TSR_5S 8 H'FFFFC8B0 8 Timer interrupt enable register_5S TIER_5S 8 H'FFFFC8B2 8 Timer start register_5S TSTR_5S 8 H'FFFFC8B4 8 Timer compare match clear register S TCNTCMPCLRS 8 H'FFFFC8B6 8 A/D data register 0 ADDR0 16 H'FFFFC900 A/D 16 P reference A/D data register 2 ADDR2 16 H'FFFFC904 (Channel 0) 16 B:2 A/D control/status register_0 ADCSR_0 16 H'FFFFC910 16 W:2 A/D control register_0 ADCR_0 16 H'FFFFC912 16 A/D data register 4 ADDR4 16 H'FFFFC980 A/D 16 P reference A/D data register 6 ADDR6 16 H'FFFFC984 (Channel 1) 16 B:2 A/D control/status register_1 ADCSR_1 16 H'FFFFC990 16 W:2 A/D control register_1 ADCR_1 16 H'FFFFC992 16 A/D data register 8 ADDR8 16 H'FFFFCA00 A/D 16 P reference A/D data register 9 ADDR9 16 H'FFFFCA02 (Channel 2) 16 B:2 A/D data register 10 ADDR10 16 H'FFFFCA04 16 W:2 A/D data register 11 ADDR11 16 H'FFFFCA06 16 A/D data register 12 ADDR12 16 H'FFFFCA08 16 A/D data register 13 ADDR13 16 H'FFFFCA0A 16 A/D data register 14 ADDR14 16 H'FFFFCA0C 16 Page 870 of 964 16 bits 16 bits 16 bits R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width A/D data register 15 ADDR15 16 H'FFFFCA0E A/D 16 P reference 16 bits A/D control/status register_2 ADCSR_2 16 H'FFFFCA10 (Channel 2) 16 B:2 A/D control register_2 ADCR_2 16 H'FFFFCA12 16 W:2 Flash code control/status register FCCS 8 H'FFFFCC00 FLASH 8 P reference Flash program code select register FPCS 8 H'FFFFCC01 (Only in 8 B:5 Flash erase code select register FECS 8 H'FFFFCC02 Flash key code register FKEY 8 H'FFFFCC04 8 Flash MAT select register FMATS 8 H'FFFFCC05 8 Flash transfer destination address FTDAR 8 H'FFFFCC06 8 DTC enable register A DTCERA 16 H'FFFFCC80 DTC 8, 16 P reference DTC enable register B DTCERB 16 H'FFFFCC82 (Only in 8, 16 B:2 DTC enable register C DTCERC 16 H'FFFFCC84 8, 16 W:2 L:4 F-ZTAT 16 bits 8 version) register F-ZTAT 16 bits version) DTC enable register D DTCERD 16 H'FFFFCC86 8, 16 DTC enable register E DTCERE 16 H'FFFFCC88 8, 16 DTC control register DTCCR 8 H'FFFFCC90 8 DTC vector base register DTCVBR 32 H'FFFFCC94 8, 16, 32 Compare match timer start register CMSTR 16 H'FFFFCE00 Compare match timer control/status CMCSR_0 16 Compare match counter_0 CMCNT_0 Compare match constant register_0 Compare match timer control/status CMT 8, 16, 32 P reference H'FFFFCE02 8, 16 B:2 16 H'FFFFCE04 8, 16, 32 CMCOR_0 16 H'FFFFCE06 8, 16 CMCSR_1 16 H'FFFFCE08 8, 16, 32 CMCNT_1 16 H'FFFFCE0A 8, 16 register_0 16 bits W:2 L:4 register_1 Compare match counter_1 Compare match constant register_1 CMCOR_1 16 H'FFFFCE0C Input level control/status register 1 ICSR1 16 H'FFFFD000 Output level control/status register 1 OCSR1 16 Input level control/status register 2 ICSR2 Output level control/status register 2 OCSR2 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 8, 16, 32 POE 8, 16, 32 P reference H'FFFFD002 8, 16 B:2 16 H'FFFFD004 8, 16, 32 W:2 16 H'FFFFD006 8, 16 L:4 16 bits Page 871 of 964 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Input level control/status register 3 ICSR3 16 H'FFFFD008 POE 8, 16 P reference 16 bits Software port output enable register SPOER 8 H'FFFFD00A 8 B:2 Port output enable control register 1 POECR1 8 H'FFFFD00B 8 W:2 Port output enable control register 2 POECR2 16 H'FFFFD00C 8, 16 L:4 Port A data register L PADRL 16 H'FFFFD102 I/O 8, 16 P reference Port A I/O register L PAIORL 16 H'FFFFD106 PFC 8, 16 B:2 Port A control register L4 PACRL4 16 H'FFFFD110 8, 16, 32 W:2 Port A control register L3 PACRL3 16 H'FFFFD112 8, 16 L:4 Port A control register L2 PACRL2 16 H'FFFFD114 8, 16, 32 Port A control register L1 PACRL1 16 H'FFFFD116 8, 16 Port A port register L PAPRL 16 H'FFFFD11E Port B data register H PBDRH 16 H'FFFFD180 I/O 8, 16 8, 16, 32 Port B data register L PBDRL 16 H'FFFFD182 Port B I/O register H PBIORH 16 H'FFFFD184 Port B I/O register L PBIORL 16 H'FFFFD186 8, 16 Port B control register H1 PBCRH1 16 H'FFFFD18E 8, 16 Port B control register L2 PBCRL2 16 H'FFFFD194 8, 16, 32 Port B control register L1 PBCRL1 16 H'FFFFD196 8, 16 Port B port register H PBPRH 16 H'FFFFD19C PBPRL 16 H'FFFFD19E Port D data register L* PDDRL 16 H'FFFFD282 Port D I/O register L*1 PDIORL 16 H'FFFFD286 Port D control register L4*1 PDCRL4 16 H'FFFFD290 8, 16, 32 Port D control register L3* 1 PDCRL3 16 H'FFFFD292 8, 16 Port D control register L2* 1 PDCRL2 16 H'FFFFD294 8, 16, 32 Port D control register L1* 1 PDCRL1 16 H'FFFFD296 8, 16 Port D port register L* PDPRL 16 H'FFFFD29E Port E data register H PEDRH 16 H'FFFFD300 Port B port register L 1 1 Port E data register L PEDRL 16 H'FFFFD302 Port E I/O register H PEIORH 16 H'FFFFD304 Port E I/O register L PEIORL 16 H'FFFFD306 Page 872 of 964 16 bits 8, 16 PFC I/O 8, 16, 32 8, 16, 32 8, 16 8, 16 PFC I/O 8, 16 8, 16 8, 16, 32 8, 16 PFC 8, 16, 32 8, 16 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Port E control register H2 PECRH2 16 H'FFFFD30C PFC 8, 16, 32 P reference 16 bits Port E control register H1 PECRH1 16 H'FFFFD30E 8, 16 B:2 Port E control register L4 PECRL4 16 H'FFFFD310 8, 16, 32 W:2 Port E control register L3 PECRL3 16 H'FFFFD312 8, 16 L:4 Port E control register L2 PECRL2 16 H'FFFFD314 8, 16, 32 Port E control register L1 PECRL1 16 H'FFFFD316 8, 16 Port E port register H PEPRH 16 H'FFFFD31C Port E port register L PEPRL 16 H'FFFFD31E IRQOUT function control register IFCR 16 H'FFFFD322 PFC 8, 16 Port F data register L PFDRL 16 H'FFFFD382 I/O 8, 16 Frequency control register FRQCR 16 H'FFFFE800 CPG 16 I/O 8, 16, 32 8, 16 P reference 16 bits W:2 Standby control register 1 STBCR1 8 H'FFFFE802 Power-down modes 8 P reference 8 B:2 Standby control register 2 STBCR2 8 H'FFFFE804 Standby control register 3 STBCR3 8 H'FFFFE806 8 Standby control register 4 STBCR4 8 H'FFFFE808 8 Standby control register 5 STBCR5 8 H'FFFFE80A 8 Standby control register 6 STBCR6 8 H'FFFFE80C Watchdog timer counter WTCNT 8 H'FFFFE810 Watchdog timer control/status register WTCSR 8 H'FFFFE812 8 WDT *1: Read 8*1, 16*2 8*1, 16*2 OSCCR 8 H'FFFFE814 CPG 8 register RAM control register P reference 16 bits 1 B:2* W:2*2 *2: Write Oscillation stop detection control 16 bits P reference 16 bits B:2 RAMCR 8 H'FFFFE880 Power-down 8 modes A/D trigger select register 0 ADTSR_0 16 H'FFFFE890 A/D trigger select register 1 ADTSR_1 16 H'FFFFE892 A/D P reference 16 bits B:2 8, 16 P reference 8, 16 B:2 16 bits W:2 Bus function extending register BSCEHR 16 H'FFFFE89A BSC 8, 16 P reference 16 bits B:2 W:2 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 873 of 964 SH7146 Group Section 23 List of Registers Access No. of Access Connected Bus Register Name Abbreviation No. of Bits Address Module Size States Width Interrupt control register 0 ICR0 16 H'FFFFE900 INTC 8, 16 P reference 16 bits IRQ control register IRQCR 16 H'FFFFE902 8, 16 B:2 IRQ status register IRQSR 16 H'FFFFE904 8, 16 W:2 Interrupt priority register A IPRA 16 H'FFFFE906 8, 16 Interrupt priority register D IPRD 16 H'FFFFE982 16 Interrupt priority register E IPRE 16 H'FFFFE984 16 Interrupt priority register F IPRF 16 H'FFFFE986 16 Interrupt priority register H IPRH 16 H'FFFFE98A 16 Interrupt priority register I IPRI 16 H'FFFFE98C 16 Interrupt priority register J IPRJ 16 H'FFFFE98E 16 Interrupt priority register K IPRK 16 H'FFFFE990 16 Interrupt priority register L IPRL 16 H'FFFFE992 16 Common control register CMNCR 32 H'FFFFF000 32 B reference CS0 space bus control register CS0BCR 32 H'FFFFF004 32 L:2 CS1 space bus control register CS1BCR 32 H'FFFFF008 32 CS0 space wait control register CS0WCR 32 H'FFFFF028 32 CS1 space wait control register CS1WCR 32 H'FFFFF02C 32 RAM emulation register RAMER 16 H'FFFFF108 BSC FLASH 16 (Only in B reference 16 bits 16 bits W:2 F-ZTAT version) Break address register A BARA 32 H'FFFFF300 Break address mask register A BAMRA 32 H'FFFFF304 Break bus cycle register A BBRA 16 Break data register A*2 BDRA 32 Break data mask register A*2 BDMRA Break address register B 32 B reference 32 B:2 H'FFFFF308 16 W:2 H'FFFFF310 32 L:2 32 H'FFFFF314 32 BARB 32 H'FFFFF320 32 Break address mask register B BAMRB 32 H'FFFFF324 32 Break bus cycle register B BBRB 16 H'FFFFF328 16 BDRB 32 H'FFFFF330 32 BDMRB 32 H'FFFFF334 32 2 Break data register B* 2 Break data mask register B* Page 874 of 964 UBC 16 bits R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers No. of Register Name Break control register 2 Branch source register* Branch destination register* 2 2 Execution times break register* Access No. of Access Connected Bus Abbreviation Bits Address Module Size States Width BRCR 32 H'FFFFF3C0 UBC 32 B reference 16 bits BRSR 32 H'FFFFF3D0 32 B:2 BRDR 32 H'FFFFF3D4 32 W:2 BETR 16 H'FFFFF3DC 16 L:2 Notes: 1. Only SH7149. 2. Only in F-ZTAT version. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 875 of 964 SH7146 Group Section 23 List of Registers 23.2 Register Bit List Addresses and bit names of each on-chip peripheral module are shown below. As for 16-bit or 32-bit registers, they are shown in two or four rows. Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 SCSMR_0 C/A CHR PE O/E STOP MP CKS[1:0] SCI (Channel 0) SCBRR_0 SCSCR_0 Module TIE RIE TE RE MPIE TEIE CKE[1:0] TDRE RDRF ORER FER PER TEND MPB MPBT SCSDCR_0 DIR SCSPTR_0 EIO SPB1IO SPB1DT SPB0IO SPB0DT SCSMR_1 C/A CHR PE O/E STOP MP SCTDR_0 SCSSR_0 SCRDR_0 CKS[1:0] SCI (Channel 1) SCBRR_1 SCSCR_1 TIE RIE TE RE MPIE TEIE CKE[1:0] TDRE RDRF ORER FER PER TEND MPB MPBT SCSDCR_1 DIR SCSPTR_1 EIO SPB1IO SPB1DT SPB0IO SPB0DT SCSMR_2 C/A CHR PE O/E STOP MP SCTDR_1 SCSSR_1 SCRDR_1 SCI CKS[1:0] (Channel 2) SCBRR_2 SCSCR_2 TIE RIE TE RE MPIE TEIE CKE[1:0] TDRE RDRF ORER FER PER TEND MPB MPBT SCSDCR_2 DIR SCSPTR_2 EIO SPB1IO SPB1DT SPB0IO SPB0DT SCTDR_2 SCSSR_2 SCRDR_2 Page 876 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCR_3 CCLR[2:0] CKEG[1:0] TPSC[2:0] TCR_4 CCLR[2:0] CKEG[1:0] TPSC[2:0] TMDR_3 BFB BFA MD[3:0] TMDR_4 BFB BFA MD[3:0] TIORH_3 IOB[3:0] IOA[3:0] TIORL_3 IOD[3:0] IOC[3:0] TIORH_4 IOB[3:0] IOA[3:0] TIORL_4 IOD[3:0] IOC[3:0] MTU2 TIER_3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TIER_4 TTGE TTGE2 TCIEV TGIED TGIEC TGIEB TGIEA TOER OE4D OE4C OE3D OE4B OE4A OE3B TGCR BDC N P FB WF VF UF TOCR1 PSYE TOCL TOCS OLSN OLSP OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P TOCR2 BF[1:0] Module TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 877 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCNTS Module MTU2 TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TCFD TCFV TGFD TGFC TGFB TGFA TSR_4 TCFD TCFV TGFD TGFC TGFB TGFA TITCR T3AEN 3ACOR[2:0] T4VEN 4VCOR[2:0] TITCNT 3ACNT[2:0] 4VCNT[2:0] TBTER TDER TDER TOLBR OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P TBTM_3 TTSB TTSA TBTM_4 TTSB TTSA UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE TADCR BF[1:0] UT4AE DT4AE BTE[1:0] TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 Page 878 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TWCR CCE WRE TSTR CST4 CST3 CST2 CST1 CST0 TSYR SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 SCH0 SCH1 SCH2 SCH3 SCH4 SCH3S SCH4S RWE TCSYSTR TRWER TCR_0 TMDR_0 CCLR[2:0] BFE CKEG[1:0] BFB Module MTU2 TPSC[2:0] BFA MD[3:0] TIORH_0 IOB[3:0] IOA[3:0] TIORL_0 IOD[3:0] IOC[3:0] TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA TIER2_0 TTGE2 TGIEF TGIEE TSR2_0 TGFF TGFE TBTM_0 TTSE TTSB TTSA TCR_1 TMDR_1 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIOR_1 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 CCLR[1:0] CKEG[1:0] IOB[3:0] TPSC[2:0] MD[3:0] IOA[3:0] Page 879 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TCFV TGFB TGFA TICCR I2BE I2AE I1BE I1AE TCR_2 TMDR_2 Module MTU2 TCNT_1 TGRA_1 TGRB_1 CCLR[1:0] TIOR_2 CKEG[1:0] TPSC[2:0] MD[3:0] IOB[3:0] IOA[3:0] TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA TCRU_5 TIORU_5 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TPSC[1:0] IOC[4:0] TCNTV_5 TGRV_5 Page 880 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCRV_5 TIORV_5 TCRW_5 TIORW_5 TSR_5 CMFU5 CMFV5 CMFW5 TIER_5 TGIE5U TGIE5V TGIE5W TSTR_5 CSTU5 CSTV5 CSTW5 TCNTCMPCLR TPSC[1:0] Module MTU2 IOC[4:0] TCNTW_5 TGRW_5 TPSC[1:0] IOC[4:0] CMPCLR5U CMPCLR5V CMPCLR5W TCR_3S CCLR[2:0] CKEG[1:0] TPSC[2:0] TCR_4S CCLR[2:0] CKEG[1:0] TPSC[2:0] TMDR_3S BFB BFA MD[3:0] TMDR_4S BFB BFA MD[3:0] TIORH_3S IOB[3:0] IOA[3:0] TIORL_3S IOD[3:0] IOC[3:0] TIORH_4S IOB[3:0] IOA[3:0] TIORL_4S IOD[3:0] IOC[3:0] MTU2S TIER_3S TTGE TCIEV TGIED TGIEC TGIEB TGIEA TIER_4S TTGE TTGE2 TCIEV TGIED TGIEC TGIEB TGIEA TOERS OE4D OE4C OE3D OE4B OE4A OE3B TGCRS BDC N P FB WF VF UF TOCR1S PSYE TOCL TOCS OLSN OLSP OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P TOCR2S BF[1:0] TCNT_3S TCNT_4S R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 881 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCDRS Module MTU2S TDDRS TGRA_3S TGRB_3S TGRA_4S TGRB_4S TCNTSS TCBRS TGRC_3S TGRD_3S TGRC_4S TGRD_4S TSR_3S TCFD TCFV TGFD TGFC TGFB TGFA TSR_4S TCFD TCFV TGFD TGFC TGFB TGFA TITCRS T3AEN 3ACOR[2:0] T4VEN 4VCOR[2:0] TITCNTS 3ACNT[2:0] 4VCNT[2:0] TBTERS TDERS TDER TOLBRS OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Page 882 of 964 BTE[1:0] R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module MTU2S TBTM_3S TTSB TTSA TBTM_4S TTSB TTSA TADCRS BF[1:0] UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE TSYCRS CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B TWCRS CCE SCC WRE TADCORA_4S TADCORB_4S TADCOBRA_4S TADCOBRB_4S TSTRS CST4 CST3 CST2 CST1 CST0 TSYRS SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 RWE TCRU_5S TIORU_5S TCRV_5S TIORV_5S TRWERS TCNTU_5S TGRU_5S TPSC[1:0] IOC[4:0] TCNTV_5S TGRV_5S R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 TPSC[1:0] IOC[4:0] Page 883 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCNTW_5S Module MTU2S TGRW_5S TCRW_5S TIORW_5S TSR_5S CMFU5 CMFV5 CMFW5 TIER_5S TGIE5U TGIE5V TGIE5W TSTR_5S CSTU5 CSTV5 CSTW5 TCNTCMPCLRS CMPCLR5U CMPCLR5V CMPCLR5W AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADF ADIE TRGE CONADF STC ADDR0 ADDR2 ADCSR_0 CKSL[1:0] ADCR_0 ADDR4 ADDR6 ADCSR_1 ADDR8 ADDR9 Page 884 of 964 TPSC[1:0] IOC[4:0] ADM[1:0] ADCS ADST AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADF ADIE TRGE CONADF STC ADM[1:0] A/D (Channel 0) CH[2:0] CKSL[1:0] ADCR_1 ADCS A/D (Channel 1) CH[2:0] ADST AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A/D (Channel 2) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADCSR_2 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADF ADIE TRGE CONADF STC CKSL[1:0] ADM[1:0] ADCS Module A/D (Channel 2) CH[2:0] ADST FCCS FWE MAT FLER SCO FLASH FPCS PPVS (Only in F-ZTAT FECS EPVB MS3 MS2 MS1 MS0 DTC (Only in F-ZTAT DTCERB15 DTCERB14 DTCERB13 DTCERB12 DTCERB11 DTCERB10 DTCERB9 DTCERB8 DTCERB7 ADCR_2 FKEY K[7:0] FMATS MS7 FTDAR TDER DTCERA version) MS6 MS5 MS4 TDA[6:0] DTCERA15 DTCERA14 DTCERA13 DTCERA12 version) DTCERB DTCERC DTCERB6 DTCERB3 DTCERB2 DTCERB1 DTCERB0 DTCERC3 DTCERC2 DTCERC1 DTCERC0 DTCERD15 DTCERD14 DTCERD13 DTCERD12 DTCERD11 DTCERD10 DTCERD9 DTCERD8 DTCERD7 DTCERD6 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 DTCERB4 DTCERC15 DTCERC14 DTCERC13 DTCERC12 DTCERD DTCERB5 DTCERD5 DTCERD4 DTCERD3 Page 885 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 DTCERE DTCERE15 DTCERE14 DTCERE13 DTCERE12 DTCERE11 DTCERE10 DTCCR Module DTC (Only in F-ZTAT RRS RCHNE ERR version) DTCVBR STR1 STR0 CMF CMIE CMF CMIE ICSR1 POE3F POE2F POE1F POE0F OCSR1 OSF1 OCE1 OIE1 POE7F POE6F POE5F POE4F PIE2 CMSTR CMCSR_0 CMT CKS[1:0] CMCNT_0 CMCOR_0 CMCSR_1 CKS[1:0] CMCNT_1 CMCOR_1 POE3M[1:0] ICSR2 POE7M[1:0] OCSR2 ICSR3 Page 886 of 964 POE2M[1:0] POE6M[1:0] POE1M[1:0] PIE1 POE POE0M[1:0] POE5M[1:0] POE4M[1:0] OSF2 OCE2 OIE2 POE8F POE8E PIE3 POE8M[1:0] R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 SPOER POECR1 MTU2PE3ZE POECR2 MTU2P1CZE MTU2P2CZE MTU2P3CZE PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR PA0IOR PA15MD2 PA15MD1 PA15MD0 PA14MD2 PA14MD1 PA14MD0 PA13MD2 PA13MD1 PA13MD0 PA12MD2 PA12MD1 PA12MD0 PA11MD2 PA11MD1 PA11MD0 PA10MD2 PA10MD1 PA10MD0 PA9MD2 PA9MD1 PA9MD0 PA8MD2 PA8MD1 PA8MD0 PA7MD2 PA7MD1 PA7MD0 PA6MD2 PA6MD1 PA6MD0 PA5MD2 PA5MD1 PA5MD0 PA4MD2 PA4MD1 PA4MD0 PA3MD2 PA3MD1 PA3MD0 PA2MD2 PA2MD1 PA2MD0 PA1MD2 PA1MD1 PA1MD0 PA0MD2 PA0MD1 PA0MD0 PA15PR PA14PR PA13PR PA12PR PA11PR PA10PR PA9PR PA8PR PA7PR PA6PR PA5PR PA4PR PA3PR PA2PR PA1PR PA0PR PB18DR PB17DR PB16DR PB5DR PB4DR PB3DR PB5IOR PADRL PAIORL PACRL4 PACRL3 PACRL2 PACRL1 PAPRL PBDRH PBDRL PBIORH PBIORL PBCRH1 PBCRL2 Sep 24, 2010 MTU2SHIZ MTU2CH0HIZ MTU2CH34HIZ POE MTU2PE2ZE MTU2PE1ZE MTU2PE0ZE MTU2SP1CZE MTU2SP2CZE MTU2SP3CZE 1 PB0DR*1 PB18IOR PB17IOR PB16IOR PB4IOR PB3IOR PB2IOR PB1IOR PB0IOR PB18MD PB17MD PB16MD PB5MD2 PB5MD1 PB5MD0 PB4MD2 PB4MD1 PB4MD0 R01UH0049EJ0400 Rev. 4.00 Module PB2DR PB1DR* I/O PFC I/O PFC Page 887 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PBCRL1 PBPRH PBPRL PDDRL*2 PDIORL*2 2 PDCRL4* 2 PDCRL3* 2 PDCRL2* PDCRL1*2 2 PDPRL* PEDRH PEDRL PEIORH PEIORL Page 888 of 964 PB3MD2 PB1MD2* PB3MD1 PB3MD0 PB2MD2 PB2MD1 Module PB2MD0 PFC PB1MD1* PB1MD0* PB0MD2* PB0MD1* PB0MD0* PB18PR PB17PR PB16PR PB5PR PB4PR PB3PR PB2PR PB1PR* PB0PR*1 PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR PD15MD1 PD15MD0 PD14MD1 PD14MD0 PD13MD1 PD13MD0 PD12MD1 PD12MD0 PD11MD1 PD11MD0 PD10MD2 PD10MD1 PD10MD0 PD9MD2 PD9MD1 PD9MD0 PD8MD2 PD8MD1 PD8MD0 PD7MD2 PD7MD1 PD7MD0 PD6MD2 PD6MD1 PD6MD0 PD5MD2 PD5MD1 PD5MD0 PD4MD2 PD4MD1 PD4MD0 PD3MD2 PD3MD1 PD3MD0 PD2MD2 PD2MD1 PD2MD0 PD1MD2 PD1MD1 PD1MD0 PD0MD2 PD0MD1 PD0MD0 PD15PR PD14PR PD13PR PD12PR PD11PR PD10PR PD9PR PD8PR PD7PR PD6PR PD5PR PD4PR PD3PR PD2PR PD1PR PD0PR PE21DR PE20DR PE19DR PE18DR PE17DR PE16DR PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR PE21IOR PE20IOR PE19IOR PE18IOR PE17IOR PE16IOR PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR 1 1 1 1 1 1 1 I/O PFC I/O PFC R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PECRH2 PECRH1 PECRL4 PECRL3 PECRL2 PECRL1 PEPRH PEPRL IFCR PFDRL FRQCR PE21MD1 PE21MD0 PE20MD1 PE20MD0 PE19MD1 PE19MD0 PE18MD1 PE18MD0 PE17MD1 PE17MD0 PE16MD2 PE16MD1 PE16MD0 PE15MD2 PE15MD1 PE15MD0 PE14MD2 PE14MD1 PE14MD0 PE13MD1 PE13MD0 PE12MD2 PE12MD1 PE12MD0 PE11MD2 PE11MD1 PE11MD0 PE10MD2 PE10MD1 PE10MD0 PE9MD2 PE9MD1 PE9MD0 PE8MD2 PE8MD1 PE8MD0 PE7MD2 PE7MD1 PE7MD0 PE6MD2 PE6MD1 PE6MD0 PE5MD2 PE5MD1 PE5MD0 PE4MD2 PE4MD1 PE4MD0 PE3MD2 PE3MD1 PE3MD0 PE2MD2 PE2MD1 PE2MD0 PE1MD2 PE1MD1 PE1MD0 PE0MD1 PE0MD0 PE21PR PE20PR PE19PR PE18PR PE17PR PE16PR PE15PR PE14PR PE13PR PE12PR PE11PR PE10PR PE9PR PE8PR PE7PR PE6PR PE5PR PE4PR PE3PR PE2PR PE1PR PE0PR IRQMD1 IRQMD0 PF15DR PF14DR PF13DR PF12DR PF11DR PF10DR PF9DR PF8DR PF6DR PF4DR PF2DR PF0DR IFC[2:0] PFC[1:0] BFC[2:0] MIFC[2:0] PFC[2] Module PFC I/O PFC I/O CPG MPFC[2:0] STBCR1 STBY Power-down STBCR2 MSTP7 MSTP6 MSTP4*3 modes STBCR3 MSTP13 MSTP12 MSTP11 STBCR4 MSTP23 MSTP22 MSTP21 MSTP18 MSTP17 MSTP16 STBCR5 MSTP25 MSTP24 STBCR6 AUDSRST HIZ STBYMD WTCNT WDT WTCSR TME WT/IT RSTS WOVF IOVF OSCCR R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 CKS[2:0] OSCSTOP OSCERS CPG Page 889 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 RAMCR RAME Module Power-down modes ADTSR_0 ADTSR_1 BSCEHR ICR0 IRQCR IRQSR TRG11S[3:0] TRG01S[3:0] TRG1S[3:0] TRG0S[3:0] TRG2S[3:0] A/D DTLOCK CSSTP1 CSSTP2 DTBST DTSA CSSTP3 DTPR NMIL NMIE IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S IRQ3L IRQ2L IRQ1L IRQ0L IRQ3F IRQ2F IRQ1F IRQ0F IRQ0 IRQ0 IRQ0 IRQ0 IRQ1 IRQ1 IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ3 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_3 MTU2_3 MTU2_3 MTU2_3 MTU2_3 MTU2_3 MTU2_3 MTU2_3 MTU2_4 MTU2_4 MTU2_4 MTU2_4 MTU2_4 MTU2_4 MTU2_4 MTU2_4 MTU2_5 MTU2_5 MTU2_5 MTU2_5 MTU2S_3 MTU2S_3 MTU2S_3 MTU2S_3 MTU2S_3 MTU2S_3 MTU2S_3 MTU2S_3 MTU2S_4 MTU2S_4 MTU2S_4 MTU2S_4 MTU2S_4 MTU2S_4 MTU2S_4 MTU2S_4 MTU2S_5 MTU2S_5 MTU2S_5 MTU2S_5 POE(MTU2S) POE(MTU2S) POE(MTU2S) POE(MTU2S) CMT_0 CMT_0 CMT_0 CMT_0 CMT_1 CMT_1 CMT_1 CMT_1 WDT WDT WDT WDT IPRK A/D_0,1 A/D_0,1 A/D_0,1 A/D_0,1 A/D_2 A/D_2 A/D_2 A/D_2 IPRL SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 SCI_2 SCI_2 SCI_2 SCI_2 IPRA IPRD IPRE IPRF IPRH IPRI IPRJ Page 890 of 964 BSC INTC POE(MTU2) POE(MTU2) POE(MTU2) POE(MTU2) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 CMNCR CS0BCR HIZMEM IWRWS[1:0] CS1BCR CS1WCR RAMER IWRRD[1:0] IWRWS[1:0] CS0WCR IWW[1:0] IWW[1:0] IWRRD[1:0] BSC IWRWD[1:0] Module IWRRS[1:0] BSZ[1:0] IWRWD[1:0] IWRRS[1:0] BSZ[1:0] WW[2:0] WR[0] WM WR[0] WM RAMS SW[1:0] WR[3:1] HW[1:0] WW[2:0] SW[1:0] WR[3:1] HW[1:0] FLASH (Only in F-ZTAT RAM[2:0] version) BARA BAMRA BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 UBC Page 891 of 964 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 CPA2*3 CPA1*3 CPA0*3 3 3 BBRA CDA1* 4 BDRA* 4 BDMRA* BARB BAMRB BBRB BDRB*4 BDMRB*4 Page 892 of 964 3 3 3 Module CDA0 IDA1* IDA0 RWA1* RWA0 SZA1* SZA0* BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 BDMA8 BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 CPB2* 3 3 CPB1* CPB0*3 CDB1*3 CDB0 IDB1*3 IDB0 RWB1*3 RWB0 SZB1*3 SZB0*3 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 UBC R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 BRCR SCMFCA BRDR*4 BETR* 4 UTRGW[1:0] 3 SCMFDA* UBIDB 3 SCMFDB* PCTE* 3 UBIDA PCBA PCBB DBEB* SEQ* ETBE*3 SVF BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 DVF BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 DBEA* BRSR*4 SCMFCB 3 3 3 Module UBC BET[11:8] BET[7:0] Notes: 1. 2. 3. 4. Reserved in SH7146. Only SH7149. Reserved in masked ROM version. Only in F-ZTAT version. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 893 of 964 SH7146 Group Section 23 List of Registers 23.3 Register States in Each Operating Mode Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module SCSMR_0 Initialized Retained Initialized Initialized Initialized Retained SCI SCBRR_0 Initialized Retained Initialized Initialized Initialized Retained SCSCR_0 Initialized Retained Initialized Initialized Initialized Retained SCTDR_0 Initialized Retained Initialized Initialized Initialized Retained SCSSR_0 Initialized Retained Initialized Initialized Initialized Retained SCRDR_0 Initialized Retained Initialized Initialized Initialized Retained SCSDCR_0 Initialized Retained Initialized Initialized Initialized Retained SCSPTR_0 Initialized Retained Initialized Initialized Initialized Retained SCSMR_1 Initialized Retained Initialized Initialized Initialized Retained SCBRR_1 Initialized Retained Initialized Initialized Initialized Retained SCSCR_1 Initialized Retained Initialized Initialized Initialized Retained SCTDR_1 Initialized Retained Initialized Initialized Initialized Retained SCSSR_1 Initialized Retained Initialized Initialized Initialized Retained SCRDR_1 Initialized Retained Initialized Initialized Initialized Retained SCSDCR_1 Initialized Retained Initialized Initialized Initialized Retained SCSPTR_1 Initialized Retained Initialized Initialized Initialized Retained SCSMR_2 Initialized Retained Initialized Initialized Initialized Retained SCBRR_2 Initialized Retained Initialized Initialized Initialized Retained SCSCR_2 Initialized Retained Initialized Initialized Initialized Retained SCTDR_2 Initialized Retained Initialized Initialized Initialized Retained SCSSR_2 Initialized Retained Initialized Initialized Initialized Retained SCRDR_2 Initialized Retained Initialized Initialized Initialized Retained SCSDCR_2 Initialized Retained Initialized Initialized Initialized Retained SCSPTR_2 Initialized Retained Initialized Initialized Initialized Retained TCR_3 Initialized Retained Initialized Initialized Initialized Retained TCR_4 Initialized Retained Initialized Initialized Initialized Retained TMDR_3 Initialized Retained Initialized Initialized Initialized Retained TMDR_4 Initialized Retained Initialized Initialized Initialized Retained TIORH_3 Initialized Retained Initialized Initialized Initialized Retained Page 894 of 964 (Channel 0) SCI (Channel 1) SCI (Channel 2) MTU2 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module TIORL_3 Initialized Retained Initialized Initialized Initialized Retained MTU2 TIORH_4 Initialized Retained Initialized Initialized Initialized Retained TIORL_4 Initialized Retained Initialized Initialized Initialized Retained TIER_3 Initialized Retained Initialized Initialized Initialized Retained TIER_4 Initialized Retained Initialized Initialized Initialized Retained TOER Initialized Retained Initialized Initialized Initialized Retained TGCR Initialized Retained Initialized Initialized Initialized Retained TOCR1 Initialized Retained Initialized Initialized Initialized Retained TOCR2 Initialized Retained Initialized Initialized Initialized Retained TCNT_3 Initialized Retained Initialized Initialized Initialized Retained TCNT_4 Initialized Retained Initialized Initialized Initialized Retained TCDR Initialized Retained Initialized Initialized Initialized Retained TDDR Initialized Retained Initialized Initialized Initialized Retained TGRA_3 Initialized Retained Initialized Initialized Initialized Retained TGRB_3 Initialized Retained Initialized Initialized Initialized Retained TGRA_4 Initialized Retained Initialized Initialized Initialized Retained TGRB_4 Initialized Retained Initialized Initialized Initialized Retained TCNTS Initialized Retained Initialized Initialized Initialized Retained TCBR Initialized Retained Initialized Initialized Initialized Retained TGRC_3 Initialized Retained Initialized Initialized Initialized Retained TGRD_3 Initialized Retained Initialized Initialized Initialized Retained TGRC_4 Initialized Retained Initialized Initialized Initialized Retained TGRD_4 Initialized Retained Initialized Initialized Initialized Retained TSR_3 Initialized Retained Initialized Initialized Initialized Retained TSR_4 Initialized Retained Initialized Initialized Initialized Retained TITCR Initialized Retained Initialized Initialized Initialized Retained TITCNT Initialized Retained Initialized Initialized Initialized Retained TBTER Initialized Retained Initialized Initialized Initialized Retained TDER Initialized Retained Initialized Initialized Initialized Retained TOLBR Initialized Retained Initialized Initialized Initialized Retained TBTM_3 Initialized Retained Initialized Initialized Initialized Retained R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 895 of 964 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module TBTM_4 Initialized Retained Initialized Initialized Initialized Retained MTU2 TADCR Initialized Retained Initialized Initialized Initialized Retained TADCORA_4 Initialized Retained Initialized Initialized Initialized Retained TADCORB_4 Initialized Retained Initialized Initialized Initialized Retained TADCOBRA_4 Initialized Retained Initialized Initialized Initialized Retained TADCOBRB_4 Initialized Retained Initialized Initialized Initialized Retained TWCR Initialized Retained Initialized Initialized Initialized Retained TSTR Initialized Retained Initialized Initialized Initialized Retained TSYR Initialized Retained Initialized Initialized Initialized Retained TCSYSTR Initialized Retained Initialized Initialized Initialized Retained TRWER Initialized Retained Initialized Initialized Initialized Retained TCR_0 Initialized Retained Initialized Initialized Initialized Retained TMDR_0 Initialized Retained Initialized Initialized Initialized Retained TIORH_0 Initialized Retained Initialized Initialized Initialized Retained TIORL_0 Initialized Retained Initialized Initialized Initialized Retained TIER_0 Initialized Retained Initialized Initialized Initialized Retained TSR_0 Initialized Retained Initialized Initialized Initialized Retained TCNT_0 Initialized Retained Initialized Initialized Initialized Retained TGRA_0 Initialized Retained Initialized Initialized Initialized Retained TGRB_0 Initialized Retained Initialized Initialized Initialized Retained TGRC_0 Initialized Retained Initialized Initialized Initialized Retained TGRD_0 Initialized Retained Initialized Initialized Initialized Retained TGRE_0 Initialized Retained Initialized Initialized Initialized Retained TGRF_0 Initialized Retained Initialized Initialized Initialized Retained TIER2_0 Initialized Retained Initialized Initialized Initialized Retained TSR2_0 Initialized Retained Initialized Initialized Initialized Retained TBTM_0 Initialized Retained Initialized Initialized Initialized Retained TCR_1 Initialized Retained Initialized Initialized Initialized Retained TMDR_1 Initialized Retained Initialized Initialized Initialized Retained TIOR_1 Initialized Retained Initialized Initialized Initialized Retained TIER_1 Initialized Retained Initialized Initialized Initialized Retained Page 896 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module TSR_1 Initialized Retained Initialized Initialized Initialized Retained MTU2 TCNT_1 Initialized Retained Initialized Initialized Initialized Retained TGRA_1 Initialized Retained Initialized Initialized Initialized Retained TGRB_1 Initialized Retained Initialized Initialized Initialized Retained TICCR Initialized Retained Initialized Initialized Initialized Retained TCR_2 Initialized Retained Initialized Initialized Initialized Retained TMDR_2 Initialized Retained Initialized Initialized Initialized Retained TIOR_2 Initialized Retained Initialized Initialized Initialized Retained TIER_2 Initialized Retained Initialized Initialized Initialized Retained TSR_2 Initialized Retained Initialized Initialized Initialized Retained TCNT_2 Initialized Retained Initialized Initialized Initialized Retained TGRA_2 Initialized Retained Initialized Initialized Initialized Retained TGRB_2 Initialized Retained Initialized Initialized Initialized Retained TCNTU_5 Initialized Retained Initialized Initialized Initialized Retained TGRU_5 Initialized Retained Initialized Initialized Initialized Retained TCRU_5 Initialized Retained Initialized Initialized Initialized Retained TIORU_5 Initialized Retained Initialized Initialized Initialized Retained TCNTV_5 Initialized Retained Initialized Initialized Initialized Retained TGRV_5 Initialized Retained Initialized Initialized Initialized Retained TCRV_5 Initialized Retained Initialized Initialized Initialized Retained TIORV_5 Initialized Retained Initialized Initialized Initialized Retained TCNTW_5 Initialized Retained Initialized Initialized Initialized Retained TGRW_5 Initialized Retained Initialized Initialized Initialized Retained TCRW_5 Initialized Retained Initialized Initialized Initialized Retained TIORW_5 Initialized Retained Initialized Initialized Initialized Retained TSR_5 Initialized Retained Initialized Initialized Initialized Retained TIER_5 Initialized Retained Initialized Initialized Initialized Retained TSTR5 Initialized Retained Initialized Initialized Initialized Retained TCNTCMPCLR Initialized Retained Initialized Initialized Initialized Retained R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 897 of 964 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module TCR_3S Initialized Retained Initialized Initialized Initialized Retained MTU2S TCR_4S Initialized Retained Initialized Initialized Initialized Retained TMDR_3S Initialized Retained Initialized Initialized Initialized Retained TMDR_4S Initialized Retained Initialized Initialized Initialized Retained TIORH_3S Initialized Retained Initialized Initialized Initialized Retained TIORL_3S Initialized Retained Initialized Initialized Initialized Retained TIORH_4S Initialized Retained Initialized Initialized Initialized Retained TIORL_4S Initialized Retained Initialized Initialized Initialized Retained TIER_3S Initialized Retained Initialized Initialized Initialized Retained TIER_4S Initialized Retained Initialized Initialized Initialized Retained TOERS Initialized Retained Initialized Initialized Initialized Retained TGCRS Initialized Retained Initialized Initialized Initialized Retained TOCR1S Initialized Retained Initialized Initialized Initialized Retained TOCR2S Initialized Retained Initialized Initialized Initialized Retained TCNT_3S Initialized Retained Initialized Initialized Initialized Retained TCNT_4S Initialized Retained Initialized Initialized Initialized Retained TCDRS Initialized Retained Initialized Initialized Initialized Retained TDDRS Initialized Retained Initialized Initialized Initialized Retained TGRA_3S Initialized Retained Initialized Initialized Initialized Retained TGRB_3S Initialized Retained Initialized Initialized Initialized Retained TGRA_4S Initialized Retained Initialized Initialized Initialized Retained TGRB_4S Initialized Retained Initialized Initialized Initialized Retained TCNTSS Initialized Retained Initialized Initialized Initialized Retained TCBRS Initialized Retained Initialized Initialized Initialized Retained TGRC_3S Initialized Retained Initialized Initialized Initialized Retained TGRD_3S Initialized Retained Initialized Initialized Initialized Retained TGRC_4S Initialized Retained Initialized Initialized Initialized Retained TGRD_4S Initialized Retained Initialized Initialized Initialized Retained TSR_3S Initialized Retained Initialized Initialized Initialized Retained TSR_4S Initialized Retained Initialized Initialized Initialized Retained Page 898 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module TITCRS Initialized Retained Initialized Initialized Initialized Retained MTU2S TITCNTS Initialized Retained Initialized Initialized Initialized Retained TBTERS Initialized Retained Initialized Initialized Initialized Retained TDERS Initialized Retained Initialized Initialized Initialized Retained TOLBRS Initialized Retained Initialized Initialized Initialized Retained TBTM_3S Initialized Retained Initialized Initialized Initialized Retained TBTM_4S Initialized Retained Initialized Initialized Initialized Retained TADCRS Initialized Retained Initialized Initialized Initialized Retained TADCORA_4S Initialized Retained Initialized Initialized Initialized Retained TADCORB_4S Initialized Retained Initialized Initialized Initialized Retained TADCOBRA_4S Initialized Retained Initialized Initialized Initialized Retained TADCOBRB_4S Initialized Retained Initialized Initialized Initialized Retained TSYCRS Initialized Retained Initialized Initialized Initialized Retained TWCRS Initialized Retained Initialized Initialized Initialized Retained TSTRS Initialized Retained Initialized Initialized Initialized Retained TSYRS Initialized Retained Initialized Initialized Initialized Retained TRWERS Initialized Retained Initialized Initialized Initialized Retained TCNTU_5S Initialized Retained Initialized Initialized Initialized Retained TGRU_5S Initialized Retained Initialized Initialized Initialized Retained TCRU_5S Initialized Retained Initialized Initialized Initialized Retained TIORU_5S Initialized Retained Initialized Initialized Initialized Retained TCNTV_5S Initialized Retained Initialized Initialized Initialized Retained TGRV_5S Initialized Retained Initialized Initialized Initialized Retained TCRV_5S Initialized Retained Initialized Initialized Initialized Retained TIORV_5S Initialized Retained Initialized Initialized Initialized Retained TCNTW_5S Initialized Retained Initialized Initialized Initialized Retained TGRW_5S Initialized Retained Initialized Initialized Initialized Retained TCRW_5S Initialized Retained Initialized Initialized Initialized Retained TIORW_5S Initialized Retained Initialized Initialized Initialized Retained TSR_5S Initialized Retained Initialized Initialized Initialized Retained TIER_5S Initialized Retained Initialized Initialized Initialized Retained R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 899 of 964 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module TSTR_5S Initialized Retained Initialized Initialized Initialized Retained MTU2S TCNTCMPCLRS Initialized Retained Initialized Initialized Initialized Retained ADDR0 Initialized Retained Initialized Initialized Initialized Retained ADDR2 Initialized Retained Initialized Initialized Initialized Retained ADCSR_0 Initialized Retained Initialized Initialized Initialized Retained ADCR_0 Initialized Retained Initialized Initialized Initialized Retained ADDR4 Initialized Retained Initialized Initialized Initialized Retained ADDR6 Initialized Retained Initialized Initialized Initialized Retained ADCSR_1 Initialized Retained Initialized Initialized Initialized Retained ADCR_1 Initialized Retained Initialized Initialized Initialized Retained ADDR8 Initialized Retained Initialized Initialized Initialized Retained ADDR9 Initialized Retained Initialized Initialized Initialized Retained ADDR10 Initialized Retained Initialized Initialized Initialized Retained ADDR11 Initialized Retained Initialized Initialized Initialized Retained ADDR12 Initialized Retained Initialized Initialized Initialized Retained ADDR13 Initialized Retained Initialized Initialized Initialized Retained ADDR14 Initialized Retained Initialized Initialized Initialized Retained ADDR15 Initialized Retained Initialized Initialized Initialized Retained ADCSR_2 Initialized Retained Initialized Initialized Initialized Retained ADCR_2 Initialized Retained Initialized Initialized Initialized Retained FCCS Initialized Retained Initialized Initialized Initialized Retained FLASH FPCS Initialized Retained Initialized Initialized Initialized Retained (Only in F-ZTAT FECS Initialized Retained Initialized Initialized Initialized Retained FKEY Initialized Retained Initialized Initialized Initialized Retained FMATS Initialized Retained Initialized Initialized Initialized Retained FTDAR Initialized Retained Initialized Initialized Initialized Retained DTCERA Initialized Retained Retained Initialized Retained Retained DTC DTCERB Initialized Retained Retained Initialized Retained Retained (Only in F-ZTAT DTCERC Initialized Retained Retained Initialized Retained Retained DTCERD Initialized Retained Retained Initialized Retained Retained Page 900 of 964 A/D (Channel 0) A/D (Channel 1) A/D (Channel 2) version) version) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module DTCERE Initialized Retained Retained Initialized Retained Retained DTC DTCCR Initialized Retained Retained Initialized Retained Retained (Only in F-ZTAT DTCVBR Initialized Retained Retained Initialized Retained Retained CMSTR Initialized Retained Initialized Initialized Initialized Retained CMCSR_0 Initialized Retained Initialized Initialized Initialized Retained CMCNT_0 Initialized Retained Initialized Initialized Initialized Retained CMCOR_0 Initialized Retained Initialized Initialized Initialized Retained CMCSR_1 Initialized Retained Initialized Initialized Initialized Retained CMCNT_1 Initialized Retained Initialized Initialized Initialized Retained CMCOR_1 Initialized Retained Initialized Initialized Initialized Retained ICSR1 Initialized Retained Retained Initialized Retained OCSR1 Initialized Retained Retained Initialized Retained ICSR2 Initialized Retained Retained Initialized Retained OCSR2 Initialized Retained Retained Initialized Retained ICSR3 Initialized Retained Retained Initialized Retained SPOER Initialized Retained Retained Initialized Retained POECR1 Initialized Retained Retained Initialized Retained POECR2 Initialized Retained Retained Initialized Retained PADRL Initialized Retained Retained Initialized Retained I/O PAIORL Initialized Retained Retained Initialized Retained PFC PACRL4 Initialized Retained Retained Initialized Retained PACRL3 Initialized Retained Retained Initialized Retained PACRL2 Initialized Retained Retained Initialized Retained PACRL1 Initialized Retained Retained Initialized Retained PAPRL Initialized Retained Retained Initialized Retained PBDRH Initialized Retained Retained Initialized Retained PBDRL Initialized Retained Retained Initialized Retained PBIORH Initialized Retained Retained Initialized Retained PBIORL Initialized Retained Retained Initialized Retained PBCRH1 Initialized Retained Retained Initialized Retained PBCRL2 Initialized Retained Retained Initialized Retained R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 version) CMT POE I/O PFC Page 901 of 964 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Abbreviation Power-on reset Manual reset Standby Standby Standby Sleep Module PBCRL1 Initialized Retained Retained Initialized Retained PFC PBPRH Initialized Retained Retained Initialized Retained I/O Initialized Retained Retained Initialized Retained Initialized Retained Retained Initialized Retained PDIORL* Initialized Retained Retained Initialized Retained PDCRL4*1 Initialized Retained Retained Initialized Retained PDCRL3*1 Initialized Retained Retained Initialized Retained 1 Initialized Retained Retained Initialized Retained 1 Initialized Retained Retained Initialized Retained PDPRL* Initialized Retained Retained Initialized Retained PEDRH Initialized Retained Retained Initialized Retained PEDRL Initialized Retained Retained Initialized Retained PEIORH Initialized Retained Retained Initialized Retained PEIORL Initialized Retained Retained Initialized Retained PECRH2 Initialized Retained Retained Initialized Retained PECRH1 Initialized Retained Retained Initialized Retained PECRL4 Initialized Retained Retained Initialized Retained PECRL3 Initialized Retained Retained Initialized Retained PECRL2 Initialized Retained Retained Initialized Retained PECRL1 Initialized Retained Retained Initialized Retained PEPRH Initialized Retained Retained Initialized Retained PEPRL Initialized Retained Retained Initialized Retained IFCR Initialized Retained Retained Initialized Retained PFC PFDRL Initialized Retained Retained Initialized Retained I/O PBPRL 1 PDDRL* 1 PDCRL2* PDCRL1* 1 PFC I/O PFC I/O FRQCR Initialized* Retained Retained Initialized Retained CPG STBCR1 Initialized Retained Retained Initialized Retained Power-down STBCR2 Initialized Retained Retained Initialized Retained STBCR3 Initialized Retained Retained Initialized Retained STBCR4 Initialized Retained Retained Initialized Retained STBCR5 Initialized Retained Retained Initialized Retained STBCR6 Initialized Retained Retained Initialized Retained 2 Page 902 of 964 modes R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Manual reset Standby Standby Standby Sleep Module Initialized* 2 Retained Retained Initialized Retained WDT Initialized* 2 Retained Retained Initialized Retained OSCCR Initialized* 3 RAMCR Initialized Abbreviation WTCNT WTCSR Power-on reset Retained Retained* Initialized Retained Retained Retained Initialized Retained 4 CPG Power-down modes ADTSR_0 Initialized Retained Retained Initialized Retained Retained A/D ADTSR_1 Initialized Retained Retained Initialized Retained Retained BSCEHR Initialized Retained Retained Initialized Retained BSC ICR0 Initialized Initialized Retained Initialized Retained INTC IRQCR Initialized Initialized Retained Initialized Retained IRQSR Initialized Initialized Retained Initialized Retained IPRA Initialized Initialized Retained Initialized Retained IPRD Initialized Initialized Retained Initialized Retained IPRE Initialized Initialized Retained Initialized Retained IPRF Initialized Initialized Retained Initialized Retained IPRH Initialized Initialized Retained Initialized Retained IPRI Initialized Initialized Retained Initialized Retained IPRJ Initialized Initialized Retained Initialized Retained IPRK Initialized Initialized Retained Initialized Retained IPRL Initialized Initialized Retained Initialized Retained CMNCR Initialized Retained Retained Initialized Retained CS0BCR Initialized Retained Retained Initialized Retained CS1BCR Initialized Retained Retained Initialized Retained CS0WCR Initialized Retained Retained Initialized Retained CS1WCR Initialized Retained Retained Initialized Retained RAMER Initialized Initialized Retained Initialized Retained Retained BSC FLASH (Only in F-ZTAT version) BARA Initialized Retained Retained Initialized Initialized Retained BAMRA Initialized Retained Retained Initialized Initialized Retained BBRA Initialized Retained Retained Initialized Initialized Retained Initialized Retained Retained Initialized Initialized Retained 5 BDRA* R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 UBC Page 903 of 964 SH7146 Group Section 23 List of Registers Register Software Deep Software Module Power-on reset Manual reset Standby Standby Standby Sleep Module Initialized Retained Retained Initialized Initialized Retained UBC BARB Initialized Retained Retained Initialized Initialized Retained BAMRB Initialized Retained Retained Initialized Initialized Retained BBRB Initialized Retained Retained Initialized Initialized Retained BDRB* Initialized Retained Retained Initialized Initialized Retained BDMRB*5 Initialized Retained Retained Initialized Initialized Retained BRCR Abbreviation BDMRA* 5 5 Initialized Retained Retained Initialized Initialized Retained 5 Initialized Initialized Retained Initialized Initialized Retained BRDR* 5 Initialized Initialized Retained Initialized Initialized Retained 5 Initialized Retained Retained Initialized Initialized Retained BRSR* BETR* Notes: 1. 2. 3. 4. 5. Only SH7149. Not initialized by a WDT power-on reset. The OSCSTOP bit is not initialized by a WDT power-on reset. The OSCSTOP bit is initialized. Only in F-ZTAT version. Page 904 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC -0.3 to +7.0 V Input voltage (except analog input pins) Vin -0.3 to VCC +0.3 V Analog power supply voltage AVCC -0.3 to +7.0 V Analog input voltage Van -0.3 to AVCC +0.3 V Topr -20 to +85 C -40 to +85 C -55 to +125 C Operating temperature Consumer applications Industrial applications Storage temperature Tstg [Operating Precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 905 of 964 SH7146 Group Section 24 Electrical Characteristics 24.2 DC Characteristics Table 24.2 lists DC characteristics. Table 24.2 DC Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Typ. Max. Unit Input high-level RES, MRES, NMI, voltage (except FWE, MD1, MD0, Schmitt trigger ASEMD0, EXTAL input voltage) Analog ports VIH VCC-0.7 -- VCC+0.3 V 2.2 -- AVCC+0.3 V 2.2 -- VCC+0.3 V -0.3 -- 0.5 V -0.3 -- 0.8 V IRQ3 to IRQ0, VT+ POE8 to POE0, VT- TCLKA to TCLKD, VT+-VT- TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TIC5U, TIC5V, TIC5W, TIOC3BS, TIOC3DS, TIOC4AS to TIOC4DS, TIC5US, TIC5VS, TIC5WS, SCK0 to SCK2, RXD0 to RXD2, TRST VCC-0.5 -- -- V -- -- 1.0 V 0.4 -- -- V Input leak current All input pins (except ASEMD0, POE3, POE7, and POE8*) | Iin | -- -- 1.0 A Input pull-up MOS current ASEMD0, POE3, POE7, and POE8* -Ipu -- -- 800 A Other input pins Input low-level RES, MRES, NMI, voltage (except FWE, MD1, MD0, Schmitt trigger ASEMD0, EXTAL input voltage) Other input pins Schmitt trigger input voltage Page 906 of 964 VIL Test Conditions Vin = 0 V R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics Item Symbol Min. Typ. Max. Unit Test Conditions Three-state leak current (OFF state) Ports A, B, D, E | Itsi | 1.0 A Output highlevel voltage All output pins VOH VCC - 0.5 V IOH = -200 A VCC - 1.0 V IOH = -1 mA TIOC3B, TIOC3D, TIOC4A to TIOC4D, TIOC3BS, TIOC3DS, TIOC4AS to TIOC4DS VCC - 1.0 V IOH = -5 mA PE9, PE11 to PE21 VCC - 2.0 V IOH = -5 mA 0.4 V IOL = 1.6 mA TIOC3B, TIOC3D, TIOC4A to TIOC4D, TIOC3BS, TIOC3DS, TIOC4AS to TIOC4DS 1.4 V IOL = 15 mA PE9, PE11 to PE21 2.5 V IOL = 15 mA 20 pF Vin = 0 V Output lowlevel voltage Input capacitance All output pins All input pins VOL Cin f = 1 MHz Ta = 25C Supply current Normal operation ICC 80 125 mA I = 80 MHz B = 40 MHz P = 40 MHz MP = 40 MHz MI = 80 MHz Sleep 65 110 mA B = 40 MHz P = 40 MHz MP = 40 MHz MI = 80 MHz Software standby Deep software standby R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 10 40 mA Ta 50C 80 mA 50C < Ta 5 30 A Ta 50C 80 A 50C < Ta Page 907 of 964 SH7146 Group Section 24 Electrical Characteristics Item Supply current Normal operation Symbol Min. Typ. Max. Unit Test Conditions ICC 150 165 mA I = 80 MHz B = 40 MHz Only in F-ZTAT version supporting full functions of E10A. P = 40 MHz MP = 40 MHz MI = 80 MHz Sleep 140 150 mA B = 40 MHz P = 40 MHz MP = 40 MHz MI = 80 MHz 20 60 mA Ta 50C 120 mA 50C < Ta 20 50 A Ta 50C 120 A 50C < Ta 3 6 mA Waiting for A/D conversion 3.5 mA The value per A/D converter module. Standby 10 A 2.0 V Software standby Deep software standby Analog power supply current During A/D conversion RAM standby voltage AICC VRAM VCC [Operating Precautions] 1. When the A/D converter is not used, do not leave the AVCC and AVSS pins open. 2. The current consumption is measured when VIH (Min.) = VCC - 0.5 V, VIL (Max.) = 0.5 V, with all output pins unloaded. Note: * When the POE8 function is selected for the PB18/POE8 pin by the PFC. Page 908 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics Table 24.3 Permitted Output Current Values Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Typ. Max. Unit Output low-level permissible current (per pin) IOL 2.0* mA Output low-level permissible current (total) IOL 110 mA Output high-level permissible current (per pin) -IOH Output high-level permissible current (total) -IOH 2.0* mA 35 mA [Operating Precautions] To assure LSI reliability, do not exceed the output values listed in table 24.3. Note: * IOL = 15 mA (Max.)/-IOH = 5 mA (Max.) about pins PE9 and PE11 to PE21. However, at most six pins are permitted to have simultaneously IOL/-IOH > 2.0 mA among these pins. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 909 of 964 SH7146 Group Section 24 Electrical Characteristics 24.3 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 24.4 Maximum Operating Frequency Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Operating frequency Page 910 of 964 Symbol Min. Typ. Max. Unit 10 -- 80 MHz External bus (B) 10 -- 40 Peripheral module (P) 10 -- 40 MTU2 (MP) 10 -- 40 MTU2S (MI) 10 -- 80 CPU (I) f Remarks R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.3.1 Section 24 Electrical Characteristics Clock Timing Table 24.5 Clock Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure EXTAL clock input frequency fEX 5 12.5 MHz Figure 24.1 EXTAL clock input cycle time tEXcyc 80 200 ns EXTAL clock input low pulse width tEXL 20 ns EXTAL clock input high pulse width tEXH 20 ns EXTAL clock input rise time tEXr 5 ns EXTAL clock input fall time tEXf 5 ns CK clock output frequency fOP 10 40 MHz CK clock output cycle time tcyc 25 100 ns CK clock output low pulse width tCKL 1/2tcyc-7.5 ns CK clock output high pulse width tCKH 1/2tcyc-7.5 ns CK clock output rise time tCKr 5 ns CK clock output fall time tCKf 5 ns Power-on oscillation settling time tOSC1 10 ms Figure 24.3 Standby return oscillation settling time 1 tOSC2 10 ms Figure 24.4 Standby return oscillation settling time 2 tOSC3 10 ms Figure 24.5 Figure 24.2 tEXcyc tEXH EXTAL (input) 1/2 VCC VIH tEXL VIH VIL tEXf VIL VIH 1/2 VCC tEXr Figure 24.1 EXTAL Clock Input Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 911 of 964 SH7146 Group Section 24 Electrical Characteristics tcyc tCKH CK (output) 1/2VCC tCKL VOH VOH VOH VOL VOL 1/2VCC tCKf tCKr Figure 24.2 CK Clock Output Timing Oscillation settling time CK, internal clock VCC VCC (Min.) tRESW tOSC1 tRESS RES Note: Oscillation settling time when on-chip oscillator is used. Figure 24.3 Power-On Oscillation Settling Timing Oscillation settling time Standby period CK, internal clock tRESW, tMRESW tOSC2 RES, MRES Note: Oscillation settling time when on-chip oscillator is used. Figure 24.4 Oscillation Settling Timing on Return from Standby (Return by Reset) Page 912 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics Oscillation settling time Standby period CK, internal clock tOSC3 NMI, IRQ Note: Oscillation settling time when on-chip oscillator is used. Figure 24.5 Oscillation Settling Timing on Return from Standby (Return by NMI or IRQ) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 913 of 964 SH7146 Group Section 24 Electrical Characteristics 24.3.2 Control Signal Timing Table 24.6 Control Signal Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol RES pulse width RES setup time* 1 RES hold time Min. tRESW 20* tRESS 65 tRESH 15 2 Max. Unit 4 -- tBcyc* -- ns -- ns -- tBcyc*4 Reference Figure Figures 24.3, 24.4, 24.6, 24.7 MRES pulse width tMRESW MRES setup time*1 tMRESS 25 -- ns MRES hold time tMRESH 15 -- ns MD1, MD0, FWE setup time tMDS 20 -- tBcyc*4 Figure 24.6 BREQ setup time tBREQS 1/2tBcyc + 15 -- ns Figure 24.9 BREQ hold time tBREQH 1/2tBcyc + 10 -- ns tNMIS 60 -- ns tNMIH 10 -- ns tIRQS 35 -- ns IRQ3 to IRQ0 hold time tIRQH 35 -- ns IRQOUT output delay time tIRQOD -- 100 ns BACK delay time tBACKD -- 1/2tBcyc + 20 ns Bus tri-state delay time tBOFF 0 100 ns Bus buffer on time tBON 0 100 ns NMI setup time* 1 NMI hold time IRQ3 to IRQ0 setup time* 1 20* 3 Figure 24.7 Figure 24.8 Figures 24.9, 24.10 Notes: 1. The RES, MRES, NMI, BREQ, and IRQ3 to IRQ0 signals are asynchronous signals. When the setup time is satisfied, change of signal level is detected at the rising edge of the clock. If not, the detection is delayed until the next rising edge of the clock. 2. In standby mode, tRESW = tOSC2 (10 ms). 3. In standby mode, tMRESW = tOSC2 (10 ms). 4. tBcyc indicates external bus clock cycle time (B = CK). Page 914 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics CK tRESS tRESS tRESW RES tMDS MD1, MD0, FWE tMRESS tMRESS MRES tMRESW Figure 24.6 Reset Input Timing CK tRESH tRESS VIH RES VIL tMRESH tMRESS VIH MRES VIL tNMIH tNMIS VIH NMI VIL tIRQH tIRQS VIH IRQ3 to IRQ0 VIL Figure 24.7 Interrupt Signal Input Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 915 of 964 SH7146 Group Section 24 Electrical Characteristics CK tIRQOD tIRQOD IRQOUT Figure 24.8 Interrupt Signal Output Timing CK tBREQH tBREQS tBREQH tBREQS BREQ tBACKD tBACKD BACK tBOFF tBON A19 to A0, D15 to D0 Figure 24.9 Bus Release Timing Normal mode Standby mode Normal mode CK tBOFF tBON A19 to A0, D15 to D0 Figure 24.10 Pin Driving Timing in Standby Mode Page 916 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.3.3 Section 24 Electrical Characteristics AC Bus Timing Table 24.7 Bus Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. 3 Unit Reference Figure ns Figures 24.11 to 24.15 Address delay time 1 tAD1 1 18 (20)* Address setup time tAS 0 -- ns Figures 24.11 to 24.14 Address hold time tAH 0 -- ns Figures 24.11 to 24.14 CS delay time tCSD 1 18 (20)* ns Figures 24.11 to 24.15 CS setup time tCSS 0 -- ns Figures 24.11 to 24.14 CS hold time tCSH 0 -- ns Figures 24.11 to 24.14 Read strobe delay time tRSD 1/2tBcyc + 1 1/2tBcyc + 18 ns 3 (20)* Figures 24.11 to 24.15 Read data setup time 1 tRDS1 1/2tBcyc + 18 3 (20)* -- ns Figures 24.11 to 24.15 Read data hold time 1 tRDH1 0 -- ns Figures 24.11 to 24.15 Read data access time tACC* tBcyc x (n +1.5) -- 3 - 33*1 (35)* ns Figures 24.11 to 24.15 Access time from read strobe tOE* tBcyc x (n + 1) -- ns Figures 24.11 to 24.15 Figures 24.11 to 24.15 2 2 - 33*1 (35)* 3 3 Write strobe delay time 1 tWSD1 1/2tBcyc + 1 1/2tBcyc + 18 ns 3 (20)* Write data delay time 1 tWDD1 -- 18 (20)* Write data hold time 1 tWDH1 1 Write data hold time tWRH 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 3 ns Figures 24.11 to 24.15 11 ns Figures 24.11 to 24.15 -- ns Figures 24.11 to 24.14 Page 917 of 964 SH7146 Group Section 24 Electrical Characteristics Item Symbol Min. Max. Unit Reference Figure WAIT setup time tWTS 1/2tBcyc + 17 3 (18)* -- ns Figures 24.12 to 24.15 WAIT hold time tWTH 1/2tBcyc + 7 3 (18)* -- ns Figures 24.12 to 24.15 Notes: tBcyc indicates external bus clock time (B = CK). 1. n denotes the number of wait cycles. 2. If the access time conditions are satisfied, the tRDS1 condition does not need to be satisfied. 3. Values in parentheses apply to E10A full-function F-ZTAT versions. T1 T2 CK tAD1 tAD1 A19 to A0 tAS tCSD tCSS tCSD CSn tCSH tRSD tRSD tAH RD tRDH1 Read tACC tOE tRDS1 D15 to D0 tCSH tWSD1 WRxx Write tWSD1 tAH tWRH tWDD1 tWDH1 D15 to D0 Figure 24.11 Basic Bus Timing for Normal Space (No Wait) Page 918 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics T1 Tw T2 CK tAD1 tAD1 A19 to A0 tAS tCSD tCSS tCSD CSn tCSH tRSD tRSD tAH RD tRDH1 Read tACC tOE tRDS1 D15 to D0 tCSH tWSD1 tWSD1 WRxx Write tAH tWRH tWDD1 tWDH1 D15 to D0 tWTH tWTS WAIT Figure 24.12 Basic Bus Timing for Normal Space (One Software Wait Cycle) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 919 of 964 SH7146 Group Section 24 Electrical Characteristics T1 TwX T2 CK tAD1 tAD1 A19 to A0 tAS tCSS tCSD tCSD CSn tCSH tRSD tRSD tAH RD tRDH1 Read tACC tOE tRDS1 D15 to D0 tCSH tWSD1 tWSD1 WRxx tWRH tWDD1 Write tAH tWDH1 D15 to D0 tWTH tWTS tWTH tWTS WAIT Figure 24.13 Basic Bus Timing for Normal Space (One External Wait Cycle) Page 920 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics T1 Tw T2 Taw T1 Tw T2 Taw CK tAD1 tAD1 tAD1 tAD1 A19 to A0 tAS tAS tCSD tCSD tCSD tCSS tCSS tCSD CSn tCSH tRSD tRSD RD tAH tCSH tRSD tRSD tRDH1 Read tRDH1 tOE tACC tAH tRDS1 tOE tACC tRDS1 D15 to D0 tCSH tWSD1 tWSD1 Write WRxx tAH tCSH tWSD1 tWSD1 tWRH tWDD1 tWDH1 tAH tWRH tWDD1 tWDH1 D15 to D0 tWTH tWTS tWTH tWTS WAIT Figure 24.14 Basic Bus Timing for Normal Space (One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 921 of 964 SH7146 Group Section 24 Electrical Characteristics Th T1 Twx T2 Tf CK tAD1 tAD1 tCSD tCSD A19 to A0 CSn tRSD tRSD RD tRDH1 Read tOE tACC tRDS1 D15 to D0 tWSD1 WRxx Write tWSD1 tWDD1 tWDH1 D15 to D0 tWTH tWTH WAIT tWTS tWTS Figure 24.15 CS Extended Bus Cycle for Normal Space (SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle) Page 922 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.3.4 Section 24 Electrical Characteristics Multi Function Timer Pulse Unit 2 (MTU2) Timing Table 24.8 Multi Function Timer Pulse Unit 2 (MTU2) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure Output compare output delay time tTOCD 50 ns Figure 24.16 Input capture input setup time tTICS 20 ns Input capture input pulse width (single edge) tTICW 1.5 tMPcyc Input capture input pulse width (both edges) tTICW 2.5 tMPcyc Timer input setup time tTCKS 20 ns Timer clock pulse width (single edge) tTCKWH/L 1.5 tMPcyc Timer clock pulse width (both edges) tTCKWH/L 2.5 tMPcyc Timer clock pulse width (phase counting mode) tTCKWH/L 2.5 tMPcyc Figure 24.17 Note: tMPcyc indicates the MTU2 clock (MP) cycle. CK tTOCD Output compare output tTICS Input capture input tTICW Figure 24.16 MTU2 Input/Output Timing CK tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 24.17 MTU2 Clock Input Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 923 of 964 SH7146 Group Section 24 Electrical Characteristics 24.3.5 Multi Function Timer Pulse Unit 2S (MTU2S) Timing Table 24.9 Multi Function Timer Pulse Unit 2S (MTU2S) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure Output compare output delay time tTOCD 50 ns Figure 24.18 Input capture input setup time tTICS 20 ns Input capture input pulse width (single edge) tTICW 1.5 tMIcyc Input capture input pulse width (both edges) 2.5 tMIcyc tTICW Note: tMIcyc indicates the MTU2S clock (MI) cycle. CK* tTOCD Output compare output tTICS Input capture input tTICW Note: * When the MI frequency is higher than the B frequency, MI is used instead of CK. Figure 24.18 MTU2S Input/Output Timing Page 924 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.3.6 Section 24 Electrical Characteristics I/O Port Timing Table 24.10 I/O Port Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure Port output data delay time tPWD 50 ns Figure 24.19 Port input hold time tPRH 20 ns Port input setup time tPRS 20 ns CK tPRS tPRH Port (read) tPWD Port (write) Figure 24.19 I/O Port Input/Output Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 925 of 964 SH7146 Group Section 24 Electrical Characteristics 24.3.7 Watchdog Timer (WDT) Timing Table 24.11 Watchdog Timer (WDT) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure WDTOVF delay time tWOVD -- 50 ns Figure 24.20 CK VOH VOH tWOVD tWOVD WDTOVF Figure 24.20 WDT Timing Page 926 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.3.8 Section 24 Electrical Characteristics Serial Communication Interface (SCI) Timing Table 24.12 Serial Communication Interface (SCI) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Input clock cycle (asynchronous) tscyc 4 tpcyc Input clock cycle (clock synchronous) tscyc 6 tpcyc Input clock pulse width tsckw 0.4 0.6 tscyc Input clock rise time tsckr 1.5 tpcyc Input clock fall time tsckf 1.5 tpcyc tTXD 4 tpcyc + 10 ns Receive data setup time tRXS 4 tpcyc ns Receive data hold time tRXH 4 tpcyc ns tTXD 3 tpcyc + 10 ns tRXS 2 tpcyc + 50 ns tRXH 2 tpcyc ns Transmit data delay time Transmit data delay time Receive data setup time Asynchronous Clock synchronous Receive data hold time Reference Figure Figure 24.21 Figure 24.22 Note: tpcyc indicates the peripheral clock (P) cycle. tsckr tsckw VIH SCK0 to SCK2 VIH tsckf VIH VIL VIL VIH VIL tscyc Figure 24.21 Input Clock Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 927 of 964 SH7146 Group Section 24 Electrical Characteristics tscyc SCK0 to SCK2 (input/output) tTXD TXD0 to TXD2 (transmit data) tRXS tRXH RXD0 to RXD2 (receive data) SCI input/output timing (clock synchronous mode) T1 VOH Tn VOH CK tTXD TXD0 to TXD2 (transmit data) tRXS tRXH RXD0 to RXD2 (receive data) SCI input/output timing (asynchronous mode) Figure 24.22 SCI Input/Output Timing Page 928 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.3.9 Section 24 Electrical Characteristics Port Output Enable (POE) Timing Table 24.13 Port Output Enable (POE) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure POE input setup time tPOES 50 ns Figure 24.23 POE input pulse width tPOEW 1.5 tpcyc Note: tpcyc indicates the peripheral clock (P) cycle. CK tPOES POEn input tPOEW Figure 24.23 POE Input Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 929 of 964 SH7146 Group Section 24 Electrical Characteristics 24.3.10 UBC Trigger Timing Table 24.14 UBC Trigger Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Max. Unit Reference Figure UBCTRG delay time tUBCTGD -- 150 ns Figure 24.24 VOH CK tUBCTGD UBCTRG Figure 24.24 UBC Trigger Timing Page 930 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics 24.3.11 A/D Converter Timing Table 24.15 A/D Converter Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Typ. Max. Unit Figure External trigger input start delay time tTRGS 25 -- -- ns Figure 24.25 4tPcyc VOH CK ADTRG input tTRGS ADCRn register (set ADST = 1) Figure 24.25 External Trigger Input Timing R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 931 of 964 SH7146 Group Section 24 Electrical Characteristics 24.3.12 AC Characteristics Measurement Conditions * Input signal level: VIL (Max.)/VIH (Min.) * Output signal reference level: High level: 2.0 V, Low level: 0.8 V IOL DUT output LSI output pin CL V VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement tools. Each pin is set as follows: 20pF: CK 30pF: All other output pins 2. Test conditions include IOL = 1.6 mA and IOH = -200 A. Figure 24.26 Output Load Circuit Page 932 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group 24.4 Section 24 Electrical Characteristics A/D Converter Characteristics Table 24.16 A/D Converter Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Min. Typ. Max. Unit Resolution 10 10 10 bit A/D conversion time 2.0 -- -- s Analog input capacitance -- -- 20 Permitted analog signal source impedance -- 1 pF -- 1* /3* 2 k Non-linear error -- -- 3.0* /5.0* LSB Offset error -- -- 3.0* /5.0* LSB 1 1 2 2 Full-scale error -- -- 3.0* /5.0* LSB Quantization error -- -- 0.5 LSB -- 4.0* /6.0* Absolute error -- 1 1 2 2 LSB Notes: 1. It is assumed that A/D conversion time 4.0 s. 2. It is assumed that A/D conversion time < 4.0 s. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 933 of 964 SH7146 Group Section 24 Electrical Characteristics 24.5 Flash Memory Characteristics Table 24.17 Flash Memory Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +85C (consumer applications), Ta = -40C to +85C (industrial applications) Item Symbol Min. Typ. Max. Unit tP -- 1 20 ms/128 bytes tE -- 40 260 ms/4-Kbyte block -- 300 1500 ms/32-Kbyte block -- 600 3000 ms/64-Kbyte block tP -- 2.3 12 s/256 Kbytes tE -- 2.3 12 s/256 Kbytes Programming and erase time tPE 1 2 4 (total)* * * -- 4.6 24 s/256 Kbytes Reprogramming count 500* -- -- Times 1 2 4 Programming time* * * 1 2 4 Erase time* * * Programming time 1 2 4 (total)* * * 1 2 4 Erase time (total)* * * NWEC 3 Notes: 1. Programming and erase time vary depending on the data. 2. Programming and erase time do not include data transfer time. 3. The minimum number of times for which all characteristics are guaranteed after reprogramming (guaranteed for once to the minimum number of reprogramming times). 4. These characteristics only apply when reprogramming is performed within the range of minimum number of times. Page 934 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Section 24 Electrical Characteristics 24.6 Usage Note 24.6.1 Notes on Connecting VCL Capacitor This LSI includes an internal step-down circuit to automatically reduce the internal power supply voltage to an appropriate level. Between this internal stepped-down power supply (VCL pin) and the VSS pin, a capacitor (0.47 F) for stabilizing the internal voltage needs to be connected. Connection of the external capacitor is shown in figure 24.27. The external capacitor should be located near the pin. Do not apply any power supply voltage to the VCL pin. External power-supply stabilizing capacitor One 0.47-F capacitor VCL VCL VSS VCL One 0.47-F capacitor One 0.47-F capacitor VSS VSS Note: Do not apply any power supply voltage to the VCL pin. Use multilayer ceramic capacitors (one 0.47-F capacitor for each VCL pin), which should be located near the pin. Figure 24.27 Connection of VCL Capacitor R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 935 of 964 Section 24 Electrical Characteristics Page 936 of 964 SH7146 Group R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Appendix Appendix A. Pin States Pin initial states differ according to MCU operating modes. Refer to section 17, Pin Function Controller (PFC), for details. Table A.1 Pin States (SH7146) Pin Function Pin State Reset State Power-Down State Deep Software Software Oscillation POE Function Type Pin Name Power-On Manual Standby Standby Sleep Stop Detected Used Clock XTAL O O L L O O O EXTAL I I Z I I I I System RES I I I I I I I control MRES Z I Z Z I Z I WDTOVF O* O O O O O O Operating MD1 I I I I I I I mode control ASEMD0 I*3 I*3 I*3 I*3 I*3 I*3 I*3 FWE I I I I I I I NMI I I I I I I I IRQ0 to IRQ3 Z I Z I I I I IRQOUT Z O Z Z O Z O TCLKA to Z I Z Z I I I Z I/O Z K*1 I/O I/O Z Z I/O Z K*1 I/O I/O I/O Z I/O Z K*1 I/O I/O I/O Z I/O Z K*1 I/O I/O I/O Z I/O Z Z I/O Z Z Interrupt MTU2 2 TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3C TIOC3B, TIOC3D R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 937 of 964 SH7146 Group Appendix Pin Function Pin State Reset State Power-Down State Deep Software Software Oscillation POE Function Type Pin Name Power-On Manual Standby Standby Sleep Stop Detected Used MTU2 TIOC4A to Z I/O Z Z I/O Z Z TIC5U, TIC5V Z I Z Z I I I TIOC3BS, Z I/O Z Z I/O Z Z Z I/O Z Z I/O Z Z TIC5US, TIC5VS Z I Z Z I I I POE0 to POE2, Z I Z Z I I I I*3 I*3 Z Z I*3 I*3 I*3 Z I/O Z Z I/O I/O I/O TIOC4D MTU2S TIOC3DS TIOC4AS to TIOC4DS POE POE4 to POE6, POE8 (PA9) POE3, POE7, POE8 (PB18) SCI UBC SCK0 to SCK2 RXD0 to RXD2 Z I Z Z I I I TXD0 to TXD2 Z O Z O*1 O O O UBCTRG Z O Z O*1 O O O Z I Z Z I I I A/D Converter AN0, AN2, AN4, AN6, AN8 to AN15 I/O Port ADTRG Z I Z Z I I I PA0 to PA15 Z I/O Z K*1 I/O I/O I/O PB2 to PB5, Z I/O Z K*1 I/O I/O I/O Z I/O Z K*1 I/O I/O Z 1 PB16 to PB18 PE0 to PE3 PE4 to PE8, Z I/O Z K* I/O I/O I/O Z I/O Z Z I/O Z Z PE16 to PE21 Z I/O Z Z I/O Z Z PF0, PF2, Z I Z Z I I I PE10 PE9, PE11 to PE15 PF4, PF6, PF8 to PF15 Page 938 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Appendix [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6 (STBCR6) is set to 1. 2. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pulldown with a resistance of at least 1 M as required. 3. Pulled-up inside the LSI when there is no input. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 939 of 964 SH7146 Group Appendix Table A.2 Pin States (SH7149) Pin Function Pin State Reset State Power-Down State Power-On Bus Expansion without ROM Master- Oscillation POE Software Software ship Stop Function Sleep Release Detected Used H*1 O O O O L L O O O O I Z I I I I I I I I I I I I I Z Z I I Z I Expansion Singlechip Manual Standby Standby Z O Z O O EXTAL I System RES I control MRES Z Type Pin Name 8 bits Clock CK O XTAL 16 bits with ROM Deep WDTOVF O* O O O O O O O BREQ Z I Z Z I I I I BACK Z O Z Z O L O O Operating MD0, MD1 I mode control ASEMD0 I* I* I* FWE I I I NMI I I IRQ0 to IRQ3 Z IRQOUT Z Interrupt 3 I 4 I 4 I I 4 I 4 I I* I* I* I*4 I I I I I I I I I I I I Z I I I I I O Z Z I* 4 4 O O Z O 2 Address bus A0 to A17 O O Z Z* O Z O O A18, A19 Z O Z Z*2 O Z O O Data bus D0 to D15 Z I/O Z Z I/O Z I/O I/O Bus control WAIT Z I Z Z CS0 (PE10) CS0 (PE17), Z I 4 H Z Z O Z I Z I I 2 O Z O O 2 Z* O Z Z* O Z O O O Z Z*2 O Z O O O Z Z*2 O Z O O O Z Z*2 O Z O O CS1 (PE18) RD (PA6) H RD (PE19) Z WRH (PA7) Z Page 940 of 964 Z H Z R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Appendix Pin Function Pin State Reset State Power-Down State Power-On Bus Expansion without ROM Type Pin Name Bus control WRL (PA8) WRH (PE20), 8 bits H Expansion Single- 16 bits with ROM Z chip Deep Master- Oscillation POE Software Software ship Stop Function Sleep Release Detected Used 2 O Z O O 2 Manual Standby Standby O Z Z* Z O Z Z* O Z O O Z I Z Z I I I I Z I/O Z K*1 I/O I/O I/O Z Z I/O Z K*1 I/O I/O I/O I/O Z I/O Z K*1 I/O I/O I/O I/O Z I/O Z K*1 I/O I/O I/O I/O Z I/O Z Z I/O I/O Z Z Z I/O Z Z I/O I/O Z Z Z I Z Z I I I I Z I/O Z Z I/O I/O Z Z Z I/O Z Z I/O I/O Z Z Z I Z Z I I I I POE0 to POE2, Z I Z Z I I I I I*4 Z Z I*4 I*4 I*4 I*4 WRL (PE21) MTU2 TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3C TIOC3B, TIOC3D TIOC4A to TIOC4D TIC5U, TIC5V, TIC5W MTU2S TIOC3BS, TIOC3DS TIOC4AS to TIOC4DS TIC5US, TIC5VS, TIC5WS POE POE4 to POE6, POE8 (PA9) POE3, POE7, I*4 POE8 (PB18) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 941 of 964 SH7146 Group Appendix Pin Function Pin State Reset State Power-Down State Power-On Bus Expansion without ROM Type Pin Name 8 bits SCI SCK0 to SCK2 Z RXD0 to RXD2 Z TXD0 to TXD2 Z chip Master- Oscillation POE Software Software ship Stop Function Manual Standby Standby Sleep Release Detected Used I/O Z Z I/O I/O I/O I/O I Z Z Expansion Single- 16 bits with ROM Deep O Z UBCTRG Z O Z O* A/D AN0, AN2, Z I Z Z Converter AN4, AN6 Z I Z Z I/O Port PA0 to PA15 PB0 to PB5, Z I/O Z I I I O O O O 1 O O O O I I I I O* UBC ADTRG I 1 I I I I 1 I/O I/O I/O I/O 1 K* Z I/O Z K* I/O I/O I/O I/O PD0 to PD15 Z I/O Z K*1 I/O I/O I/O I/O PE0 to PE3 Z I/O Z K*1 I/O I/O I/O Z PE4 to PE8, Z I/O Z K*1 I/O I/O I/O I/O Z I/O Z Z I/O I/O Z Z PE16 to PE21 Z I/O Z Z I/O I/O Z Z PF0, PF2, Z I Z Z I I I I PB16 to PB18 PE10 PE9, PE11 to PE15 PF4, PF6, PF8 to PF15 Page 942 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Appendix [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6 (STBCR6) is set to 1. 2. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set to 1. 3. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pulldown with a resistance of at least 1 M as required. 4. Pulled-up inside the LSI when there is no input. B. Processing of Unused Pins Table B.1 Processing of Unused Pins Pin Processing NMI Fixed high-level (pull-up) WDTOVF Open (If pull-down is necessary, use a resistor rated at 1 or greater) AVref AVref = Avcc AVcc, AVss AVcc = Vcc, AVss = Vss ASEMD0 Fixed high-level (pull-up) PF0 to PF15 Connect to AVcc or AVss via a resistor Input-only pins other than the above Fixed (pull-up/pull-down) I/O pins other than the above Fixed at input pin setting (pull-up/pull-down) or set to output and left open Output-only pins Open Notes: 1. For pull-up or pull-down, connect to Vcc or GND via a resistor. 2. When using the H-UDI, pin processing is according to the specifications of the emulator. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 943 of 964 SH7146 Group Appendix C. Pin States of Bus Related Signals TableC.1 Pin States of Bus Related Signals (1) Pin Name On-chip ROM Space CS0, CS1 RD WRH WRL On-chip RAM Space On-chip Peripheral Module Space H H H R H H H W H H R H H H W H H R H H H W H H A19 to A0 Address* Address* Address* D15 to D8 Hi-Z Hi-Z Hi-Z D7 to D0 Hi-Z Hi-Z Hi-Z [Legend] R: W: Note: * Read Write Value of external space address that was previously accessed Page 944 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Table C.1 Appendix Pin States of Bus Related Signals (2) External Space (Normal Space) 16-bit Space 8-bit Space Pin Name CS0, CS1 Upper Byte Lower Byte Word/Longword Enabled Enabled Enabled Enabled R L L L L W H H H H R H H H H W H L H L R H H H H W L H L L A19 to A0 Address Address Address Address D15 to D8 Hi-Z Data Hi-Z Data D7 to D0 Data Hi-Z Data Data RD WRH WRL [Legend] R: W: Enabled: Read Write Chip select signals corresponding to accessed areas = Low. The other chip select signals = High. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 945 of 964 SH7146 Group Appendix D. Product Code Lineup Table D.1 Product Code Lineup Product Type Product Name Classification SH7146 F-ZTAT version 256 kbytes 8 kbytes RAM Capacity Application Operating temperature Product Code Consumer application -20 to +85C R5F71464AN80FPV Industrial application -40 to +85C R5F71464AD80FPV Consumer application -20 to +85C R5M71464BNXXXFPV *2 Industrial application -40 to +85C R5M71464BDXXXFPV *2 F-ZTAT version 256 kbytes 8 kbytes supporting full functions of E10A*1 For system development 1 only* 0 to +50C F-ZTAT version 256 kbytes 8 kbytes Consumer application -20 to +85C R5F71494AN80FPV Industrial application -40 to +85C R5F71494AD80FPV Consumer application -20 to +85C R5M71494BNXXXFPV *2 Industrial application -40 to +85C R5M71494BDXXXFPV *2 For system development 1 only* 0 to +50C Masked ROM version SH7149 ROM Capacity Masked ROM version 256 kbytes 8 kbytes 256 kbytes 8 kbytes F-ZTAT version 256 kbytes 8 kbytes supporting full functions of E10A*1 Package (Package Code) LQFP1414-80 (FP-80WV) R5E71464RN80FPV R5E71494RN80FPV LQFP1414-100 (FP-100UV) LQFP1414-100 (FP-100UV) LQFP1414-100 (FP-100UV) Notes: 1. These products are only used for system development by the customer, and E10A internal bus trace function and AUD function are available. However, normal F-ZTAT version or masked ROM version must be used in mass production. In normal F-ZTAT version, the E10A internal bus trace function and AUD function are not available. Reliability is not guaranteed for F-ZTAT version supporting full functions of E10A. 2. XXX is the ROM code. Page 946 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group E. Appendix Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-LQFP80-14x14-0.65 RENESAS Code PLQP0080JA-A Previous Code FP-80W / FP-80WV MASS[Typ.] 0.6g HD *1 D 41 60 61 40 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. HE b1 ZE 80 Reference Symbol c c1 *2 E bp Terminal cross section 21 1 20 ZD c A F A2 Index mark A1 S y S e L L1 *3 bp Detail F x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.27 0.32 0.37 0.30 0.09 0.145 0.20 0.125 0 8 0.65 0.13 0.10 0.825 0.825 0.35 0.5 0.65 1.0 Figure E.1 FP-80WV R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 947 of 964 SH7146 Group Appendix JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Symbol c E *2 HE b1 D E A2 HD HE A A1 bp b1 c c1 26 1 ZE Terminal cross section 100 25 Index mark ZD F y S e *3 bp A1 c A A2 S L x L1 Detail F e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Figure E.2 FP-100UV Page 948 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Main Revisions for This Edition Main Revisions for This Edition Item Page Revision (See Manual for Details) All Company name and brand names amended (Before) Renesas Technology Corp. (After) Renesas Electronics Corporation 1.1 Features of SH7146 and SH7149 5 Table 1.1 Features Table amended Items Specifiction Packages * LQFP1414-80 (0.65 pitch) (SH7146) * LQFP1414-100 (0.5 pitch) (SH7149) * Vcc: 4.0 to 5.5 V * AVcc: 4.0 to 5.5 V Power supply voltage Figure deleted 5.8.4 Notes on Slot Illegal Instruction Exception Handling Description deleted 8.7.2 Chain Transfer when Counter = 0 193 1.3 Pin Assignments Figure 1.4 Pin Assignments of SH7149 (QFP Version) R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Note that a check-up program (checker) to pick up this instruction is available on our website. Download and utilize this checker as needed. Description amended 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer destination address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer destination address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. Page 949 of 964 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 9.5.10 Access to External Memory by CPU 233 Table amended Table 9.11 Number of External Access Cycles External Bus Width Access Size Write/Read Number of Access Cycles 8 bits Byte Write (1 + n) x I + (3 + m) x B Read (1 + n) x I + (3 + m) x B + 1 x I Word Write (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B Read (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B+ 1 x I Longword Write (1 + n) x I + (3 + m) x B + 3 x (2 + o) x B (1 + n) x I + (3 + m) x B + 3 x (2 + o) x B+ 1 x I Read 16 bits Longword 10.3.32 Timer Waveform Control 326 Register (TWCR) (1 + n) x I + (3 + m) x B Byte/Word Write Read (1 + n) x I + (3 + m) x B + 1 x I Write (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B Read (1 + n) x I + (3 + m) x B + 1 x (2 + o) x B+ 1 x I Bit table amended Bit Bit Name Initial Value R/W 0 WRE 0 R/(W) Description Initial Output Suppression Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The initial output is suppressed only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 10.40. 0: Outputs the initial value specified in TOCR 1: Suppresses initial output [Setting condition] * Page 950 of 964 When 1 is written to WRE after reading WRE = 0 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 10.4.8 Complementary PWM Mode 381 Description added 14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 10.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 10.56) immediately after the counters start operation, initial value output is not suppressed. When using the initial output suppression function, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. If synchronous clearing occurs with the compare registers set to a value less than twice the setting of TDDR, the PWM output dead time may be too short (or nonexistent) or illegal active-level PWM negative-phase output may occur during the initial output suppression interval. For details, see 10.7.23, Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode. This function can be used in both the MTU2 and MTU2S... Outline of Complementary PWM Mode Operation: Figure 10.77 Example of 401 Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) Figure replaced Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer TransferEnabled Period Figure replaced R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 402 Page 951 of 964 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 10.4.11 External Pulse Width Measurement 414 Figure amended MP Figure 10.88 Example of External Pulse Width Measurement (Measuring High Pulse Width) TIC5U TCNTU_5 0000 10.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode 451, 452 Newly added Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) 486 Table amended Table 11.1 MTU2S Functions Item Channel 3 Channel 4 Channel 5 PWM mode 1 -- -- -- PWM mode 2 -- -- -- 13.5 Interrupt Source 532 Newly added 14.3.8 Serial Port Register (SCSPTR) 550 Bit table amended Bit: 7 6 5 4 EIO - - - Initial value: 0 R/W: R/W 0 - 0 - 0 - 551 Bit 0 Bit Name SPB0DT 3 2 1 0 SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W Initial value R/W Description 1 R/W Serial Port Break Data R/W 0 R/W 1 R/W Together with the SPB0IO bit and TE bit in SCSCR, controls the TXD pin. Note that the TXD pin function needs to have been selected with the pin function controller (PFC). TE bit SPB0IO setting in bit SCSCR setting SPB0DT bit setting 0 0 * 0 1 0 Output, low level 0 1 1 Output, high level 1 * * State of TXD pin SPB0DT output disabled (initial state) Output for transmit data in accord with the serial core logic Note: * Don't care Page 952 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Item Main Revisions for This Edition Page 14.4.3 Clock Synchronous Mode 584 Revision (See Manual for Details) Figure amended Figure 14.14 Sample Flowchart for Transmitting/Receiving Serial Data Start of transmission and reception [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error processing: If a receive error occurs, read the ORER flag in SCSSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [3] SCI status check and receive data read: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading SCRDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to SCTDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to SCTDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the SCRDR value is read. Read TDRE flag in SCSSR No TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 Read ORER flag in SCSSR Yes ORER = 1? No Error processing Read RDRF flag in SCSSR No RDRF = 1? Yes Read receive data in SCRDR and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission and reception Note: 14.4.5 Multiprocessor Serial Data 586 Transmission R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Description amended Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. Maintain the MPBT value at 1 until the ID transmission actually completes. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Page 953 of 964 SH7146 Group Main Revisions for This Edition Item Page 14.4.5 Multiprocessor Serial Data 587 Transmission Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart Revision (See Manual for Details) Figure amended [1] Initialization [1] SCI initialization: Set the TXD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR. Set the MPBT bit in SCSSR to 0 or 1. Finally, clear the TDRE flag to 0. To transmit an ID after the SCI is initialized, write the ID to SCTDR. The data is immediately transferred to SCTSR and the TDRE flag is set to 1. At this point the ID has not yet been transmitted from the TXD pin, so it is necessary to maintain the MPBT value at 1. Clear the MPBT bit to 0 after the next data to be transmitted is written to SCTDR and the TDRE flag is set to 1. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR and use the PFC to select the TXD pin as an output port. Start transmission Set MPBT bit in SCSSR to 1 [2] Write transmit ID to SCTDR Clear TDRE flag in SCSR to 0 TDRE = 1? No Yes Clear MPBT in SCSSR to 0 [3] Write transmit data to SCTDR Clear TDRE flag to 0 TDRE = 1? No Yes No Transmit end? Yes Read TEND flag in SCSSR No TEND = 1? Yes No Break output? [4] Yes Clear DR to 0 Clear TE bit in SCSCR to 0; select the TXD pin as an output port with the PFC <End> 14.5 SCI Interrupt Sources and DTC Page 954 of 964 591 Description amended When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated. This request cannot be used to activate the DTC. It is possible to disable generation of RXI interrupt requests and allow only ERI interrupt requests to be generated during data reception processing. To accomplish this, set the RIE bit to 1 and the EIO bit in SCSPTR to 1. Note that setting the EIO bit to 1 will prevent the DTC from transferring received data because no ERI interrupt requests are generated. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 15.3.4 A/D Trigger Select Registers_0 and _1 (ADTSR_0 and ADTSR_1) 613 Bit table amended Bit 7 to 4 Bit Name TRG1S[3:0] Initial Value R/W Description 0000 R/W A/D Trigger 1 Select 3 to 0 Select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for A/D module 1. In 2channel scan mode, these bits select an external trigger, MTU2 trigger, or MTU2S trigger to start A/D conversion for group 0. * ADTSR_0 0000: External trigger pin (ADTRG) input 0001: TGRA input capture/compare match for each MTU2 channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0010: MTU2 CH0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: TGRA input capture/compare match on each MTU2S channel or TCNT_4 trough in complementary PWM mode (TRGAN) 0110: Setting prohibited 0111: MTU2S A/D conversion start request delaying (TRG4AN) 1000: MTU2S A/D conversion start request delaying (TRG4BN) 1001: Setting prohibited 101x: Setting prohibited 11xx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. 15.4.7 2-Channel Scanning 621 Figure amended Figure 15.4 Example of 2Channel Scanning TGRA_3 TADCORA_4 TCNT_4 TADCORB_4 H'0000 A/D conversion start request AN0 conversion AN2 conversion A/D conversion end (ADF) CONADF bit in ADCSR = 0 CONADF bit in ADCSR = 1 16.4 Interrupts 16.4.1 CMT Interrupt Sources and DTC Activation Table 16.2 Interrupt Source 635 Description and Table added .... The data transfer controller (DTC) can be activated by an interrupt request. In this case, the priority between channels is fixed. See section 8, Data Transfer Controller (DTC), for details. Table 16.2 lists the CMT interrupt sources. R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 955 of 964 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 19.4.3 Programming/Erasing Interface Parameters 758 Description amended (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see table 24.4, Maximum Operating Frequency. 19.9.1 Specifications of the Standard Serial Communications Interface in Boot Mode 808 Description amended Size (1 byte): Number of characters in the device code (fixed at 4) (2) Device selection 22.8.2 Deep Software Standby Mode Description deleted 24.2 DC Characteristics 907, 908 Table amended Table 24.2 DC Characteristics Item Symbol Min. Typ. Three-state leak current (OFF state) Ports A, B, D, E | Itsi | Output highlevel voltage All output pins VOH TIOC3B, TIOC3D, TIOC4A to TIOC4D, TIOC3BS, TIOC3DS, TIOC4AS to TIOC4DS PE9, PE11 to PE21 Output lowlevel voltage All output pins VOL TIOC3B, TIOC3D, TIOC4A to TIOC4D, TIOC3BS, TIOC3DS, TIOC4AS to TIOC4DS PE9, PE11 to PE21 Input capacitance All input pins Supply current Normal operation Cin Max. Unit 1.0 A Test Conditions VCC - 0.5 V IOH = -200 A VCC - 1.0 V IOH = -1 mA VCC - 1.0 V IOH = -5 mA VCC - 2.0 V IOH = -5 mA 0.4 V IOL = 1.6 mA 1.4 V IOL = 15 mA 2.5 V IOL = 15 mA 20 pF Vin = 0 V f = 1 MHz Ta = 25C ICC 80 125 mA I = 80 MHz B = 40 MHz P = 40 MHz MP = 40 MHz MI = 80 MHz Sleep 65 110 mA B = 40 MHz P = 40 MHz MP = 40 MHz MI = 80 MHz Software standby Deep software standby Supply current Only in F-ZTAT version supporting full functions of E10A. Page 956 of 964 Normal operation ICC 10 40 mA Ta 50C 50C < Ta 80 mA 5 30 A Ta 50C 80 A 50C < Ta 150 165 mA I = 80 MHz B = 40 MHz P = 40 MHz MP = 40 MHz MI = 80 MHz R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 24.3.3 AC Bus Timing 917, 918 Table amended Table 24.7 Bus Timing Item Symbol Min. Max. Address delay time 1 tAD1 1 18 (20)* Address setup time tAS 0 -- ns Figures 24.11 to 24.14 Address hold time tAH 0 -- ns Figures 24.11 to 24.14 CS delay time tCSD 1 18 (20)* ns Figures 24.11 to 24.15 CS setup time tCSS 0 -- ns Figures 24.11 to 24.14 CS hold time tCSH 0 -- ns Figures 24.11 to 24.14 Read strobe delay time tRSD 1/2tBcyc + 1 1/2tBcyc + 18 ns 3 (20)* Figures 24.11 to 24.15 Read data setup time 1 tRDS1 1/2tBcyc + 18 3 (20)* -- ns Figures 24.11 to 24.15 Read data hold time 1 tRDH1 0 -- ns Figures 24.11 to 24.15 Figures 24.11 to 24.15 3 3 Unit Reference Figure ns Figures 24.11 to 24.15 Read data access time tACC* tBcyc x (n +1.5) -- 3 - 33*1 (35)* ns Access time from read strobe tOE* tBcyc x (n + 1) 3 - 33*1 (35)* -- ns Figures 24.11 to 24.15 Write strobe delay time 1 tWSD1 1/2tBcyc + 1 1/2tBcyc + 18 ns 3 (20)* Figures 24.11 to 24.15 Write data delay time 1 tWDD1 -- 18 (20)* Write data hold time 1 tWDH1 1 11 Write data hold time tWRH 0 WAIT setup time tWTS 1/2tBcyc + 17 3 (18)* WAIT hold time tWTH 1/2tBcyc + 7 3 (18)* 2 2 3 ns Figures 24.11 to 24.15 ns Figures 24.11 to 24.15 -- ns Figures 24.11 to 24.14 -- ns Figures 24.12 to 24.15 -- ns Figures 24.12 to 24.15 Note added Notes: 3. Values in parentheses apply to E10A fullfunction F-ZTAT versions. 24.3.12 AC Characteristics Measurement Conditions 932 Figure amended IOL Figure 24.26 Output Load Circuit DUT output LSI output pin CL V VREF IOH R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 957 of 964 SH7146 Group Main Revisions for This Edition Item Page Revision (See Manual for Details) 24.5 Flash Memory Characteristics 934 Table amended Item Symbol 1 2 4 Programming time* * * Table 24.17 Flash Memory Characteristics 1 2 4 Erase time* * * Programming time 1 2 4 (total)* * * 1 2 4 Erase time (total)* * * Min. Typ. Max. Unit tP -- 1 20 ms/128 bytes tE -- 40 260 ms/4-Kbyte block -- 300 1500 ms/32-Kbyte block -- 600 3000 ms/64-Kbyte block tP -- 2.3 12 s/256 Kbytes tE -- 2.3 12 s/256 Kbytes 4.6 24 s/256 Kbytes -- -- Times Programming and erase time tPE 1 2 4 (total)* * * Reprogramming count Appendix NWEC 943 Newly added 946 Table amended -- 3 500* B. Processing of Unused Pins D. Product Code Lineup Product Type Table D.1 Product Code Lineup Product Name Classification SH7146 F-ZTAT version 256 kbytes 8 kbytes Masked ROM version SH7149 ROM Capacity RAM Capacity Application 256 kbytes 8 kbytes R5F71464AN80FPV Package (Package Code) Industrial application -40 to +85C R5F71464AD80FPV Consumer application -20 to +85C R5M71464BNXXXFPV *2 LQFP1414-80 (FP-80WV) -40 to +85C R5M71464BDXXXFPV *2 F-ZTAT version 256 kbytes 8 kbytes supporting full functions of E10A*1 For system development only*1 0 to +50C R5E71464RN80FPV F-ZTAT version 256 kbytes 8 kbytes Consumer application -20 to +85C R5F71494AN80FPV Industrial application -40 to +85C R5F71494AD80FPV onsumer application -20 to +85C Industrial application -40 to +85C R5M71494BDXXXFPV *2 For system development only*1 0 to +50C 256 kbytes 8 kbytes F-ZTAT version 256 kbytes 8 kbytes supporting full functions of E10A*1 Figure E.1 FP-80WV Product Code -20 to +85C Industrial application Masked ROM version E. Package Dimensions Operating temperature Consumer application 947, 948 Figures replaced Figure deleted LQFP1414-100 (FP-100UV) R5M71494BNXXXFPV *2 R5E71494RN80FPV LQFP1414-100 (FP-100UV) LQFP1414-100 (FP-100UV) Figure E.2 FP-100UV Figure E.3 FP-100AV Page 958 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Index A C A/D conversion time............................... 619 A/D converter (ADC) ............................. 599 A/D converter activation......................... 421 A/D converter characteristics.................. 933 A/D converter interrupt source ............... 622 A/D converter start request delaying function................................................... 404 Absolute accuracy................................... 623 Absolute maximum ratings..................... 905 AC bus timing......................................... 917 AC characteristics................................... 910 AC characteristics measurement onditions ................................................. 932 Access in view of LSI internal bus master ..................................................... 230 Access size and data alignment .............. 214 Access wait control................................. 220 Address error .............................. 79, 88, 844 Address map ........................................... 199 Addressing modes..................................... 24 Arithmetic operation instructions ............. 37 Asynchronous mode ....................... 533, 566 Calculating exception handling vector table addresses .......................................... 76 Chain transfer.......................................... 180 Changing frequency .................................. 67 Clock (MI) for the MTU2S module........ 53 Clock (MP) for the MTU2 module ......... 53 Clock frequency control circuit................. 55 Clock operating mode ............................... 58 Clock pulse generator (CPG) .................... 53 Clock synchronous mode ................ 533, 576 Clock timing ........................................... 911 CMT interrupt sources ............................ 635 Compare match timer (CMT) ................. 629 Complementary PWM mode .................. 359 Conflict between NMI interrupt and DTC activation................................................. 195 Connecting crystal resonator..................... 68 Continuous scan mode ............................ 616 Control signal timing .............................. 914 CPU........................................................... 15 Crystal oscillator ....................................... 55 CSn assert period extension .................... 222 B D Block transfer mode................................ 179 Boot mode............................................... 772 Branch instructions ................................... 41 Break comparison conditions.................. 117 Break detection and processing .............. 595 Break on data access cycle...................... 142 Break on instruction fetch cycle ............. 141 Bus arbitration ........................................ 226 Bus clock (B) .......................................... 53 Bus release state........................................ 45 Bus state controller (BSC) ...................... 197 Data transfer controller (DTC)................ 153 Data transfer instructions .......................... 35 DC characteristics ................................... 906 Dead time compensation......................... 415 Deep software standby mode .................. 859 Divider ...................................................... 55 DTC activation........................................ 420 DTC activation by interrupt .................... 191 DTC activation sources........................... 166 DTC bus release timing........................... 187 DTC execution status .............................. 185 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Page 959 of 964 DTC vector address ................................ 168 E Error protection ...................................... 791 Exception handling ................................... 73 Exception handling state........................... 45 External clock input method..................... 69 External pulse width measurement ......... 414 External trigger input timing .................. 620 F Features of instructions............................. 21 Flash memory ......................................... 735 Flash memory characteristics ................. 934 Flash memory configuration................... 741 Flash memory emulation in RAM .......... 793 Flow of the user break operation ............ 140 Full-scale error........................................ 623 Function for detecting oscillator stop ....... 70 G General illegal instructions ....................... 84 General registers ....................................... 17 Global-base register (GBR) ...................... 18 H Hardware protection ............................... 790 I I/O ports.................................................. 709 Illegal slot instructions.............................. 84 Immediate data formats ............................ 21 Influences on absolute accuracy ............. 626 Initial user branch processing time ......... 800 Page 960 of 964 Initial values of control register ................ 19 Initial values of general register................ 19 Initial values of system register ................ 19 Initiation intervals of user branch processing ............................................... 800 Instruction formats.................................... 27 Instruction set............................................ 31 Interrupt controller (INTC) ....................... 91 Interrupt exception handling vector table.............................................. 106 Interrupt priority ....................................... 82 Interrupt response time ........................... 113 Interrupt sequence................................... 109 Interrupts................................................... 81 IRQ interrupts ......................................... 104 L List of registers ....................................... 863 Location of transfer information and DTC vector table..................................... 166 Logic operation instructions ..................... 39 M Manual reset.............................................. 78 Masked ROM.......................................... 841 MCU extension mode ............................... 49 MCU operating modes.............................. 47 Module standby mode............................. 860 Module standby mode setting 194, 597, 626, ................................................ 637, 842, 844 MTU2 functions...................................... 238 MTU2 interrupts ..................................... 419 MTU2 output pin initialization ............... 453 MTU2-MTU2S synchronous operation . 408 MTU2S functions ................................... 486 Multi-function timer pulse unit 2 (MTU2)................................................... 237 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Multi-function timer pulse unit 2S (MTU2S) ................................................ 485 Multiply and accumulate registers (MACH and MACL) ................................ 19 Multiprocessor communication function................................................... 585 Power-down modes................................. 845 Power-down state...................................... 45 Power-on reset .......................................... 77 Procedure register (PR)............................. 19 Product code lineup................................. 946 Program counter (PC) ............................... 19 Program execution state ............................ 45 Programmer mode................................... 840 N NMI interrupt.......................................... 104 Nonlinearity error ................................... 623 Normal space interface ........................... 216 Normal transfer mode ............................. 176 Note on changing operating mode ............ 52 Note on crystal resonator .......................... 71 Notes on board design ...................... 71, 627 Notes on connecting VCL capacitor ......... 935 Notes on noise countermeasures............. 628 Notes on register access (WDT) ............. 529 Notes on slot illegal instruction exception handling.................................... 89 O Offset error ............................................. 623 On-board programming mode ................ 772 On-chip peripheral module interrupts..... 105 Operating clock for each module.............. 56 P Package dimensions................................ 947 PC trace .................................................. 144 Peripheral clock (P) ................................ 53 Permissible signal source impedance...... 626 Pin function controller (PFC) ................. 641 Pin states of bus related signals .............. 944 Pin states of this LSI in each processing state....................................... 937 Port output enable (POE)........................ 493 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Q Quantization error ................................... 623 R RAM ....................................................... 843 Range of analog power supply and other pin settings ..................................... 627 Register ADCR ................................................. 607 ADCSR ............................................... 604 ADDR0, ADDR2, ADDR4, ADDR6, and ADDR8 to ADDR15 .................... 603 ADTSR ............................................... 610 BAMRA.............................................. 121 BAMRB .............................................. 127 BARA ................................................. 121 BARB.................................................. 126 BBRA.................................................. 122 BBRB.................................................. 130 BDMRA.............................................. 125 BDMRB .............................................. 129 BDRA ................................................. 124 BDRB.................................................. 128 BETR .................................................. 137 BRCR.................................................. 132 BRDR.................................................. 139 BRSR .................................................. 138 BSCEHR ..................................... 165, 210 CMCNT .............................................. 633 Page 961 of 964 CMCOR.............................................. 633 CMCSR .............................................. 631 CMNCR.............................................. 203 CMSTR............................................... 631 CRA.................................................... 160 CRB .................................................... 161 CS0BCR and CS1BCR....................... 205 CS0WCR and CS1WCR..................... 208 DAR (DTC) ........................................ 159 DPFR .................................................. 756 DTCCR............................................... 163 DTCERA to DTCERE........................ 162 DTCVBR ............................................ 165 FCCS .................................................. 748 FEBS................................................... 767 FECS................................................... 751 FKEY.................................................. 752 FMATS............................................... 753 FMPAR............................................... 762 FMPDR............................................... 763 FPCS................................................... 751 FPEFEQ.............................................. 758 FPFR................................... 761, 764, 768 FRQCR ................................................. 63 FTDAR ............................................... 754 FUBRA............................................... 759 ICR0 ..................................................... 95 ICSR1 ................................................. 498 ICSR2 ................................................. 503 ICSR3 ................................................. 508 IFCR ................................................... 706 IPRA, IPRD to IPRF and IPRH to IPRL ..................................... 101 IRQCR.................................................. 96 IRQSR .................................................. 98 MRA ................................................... 156 MRB ................................................... 157 OCSR1................................................ 502 OCSR2................................................ 507 OSCCR ................................................. 66 Page 962 of 964 PACRL1.............................................. 659 PACRL2.............................................. 659 PACRL3.............................................. 659 PACRL4.............................................. 659 PADRL ............................................... 712 PAIORL .............................................. 659 PAPRL ................................................ 714 PBCRH1 ............................................. 674 PBCRL1.............................................. 674 PBCRL2.............................................. 674 PBDRH ............................................... 716 PBDRL ............................................... 716 PBIORH.............................................. 673 PBIORL .............................................. 673 PBPRH................................................ 719 PBPRL ................................................ 719 PDCRL1.............................................. 681 PDCRL2.............................................. 681 PDCRL3.............................................. 681 PDCRL4.............................................. 681 PDDRL ............................................... 722 PDIORL .............................................. 681 PDPRL ................................................ 724 PECRH1.............................................. 689 PECRH2.............................................. 689 PECRL1 .............................................. 689 PECRL2 .............................................. 689 PECRL3 .............................................. 689 PECRL4 .............................................. 689 PEDRH ............................................... 727 PEDRL................................................ 727 PEIORH .............................................. 688 PEIORL .............................................. 688 PEPRH ................................................ 730 PEPRL ................................................ 730 PFDRL ................................................ 733 POECR1.............................................. 511 POECR2.............................................. 513 RAMCR .............................................. 855 RAMER .............................................. 770 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 SAR (DTC)......................................... 159 SCBRR (SCI) ..................................... 553 SCRDR ............................................... 537 SCRSR (SCI) ...................................... 537 SCSCR (SCI) ...................................... 541 SCSDCR............................................. 552 SCSMR (SCI) ..................................... 538 SCSPTR (SCI) .................................... 550 SCSSR ................................................ 544 SCTDR ............................................... 538 SCTSR (SCI) ...................................... 537 SPOER................................................ 510 STBCR1.............................................. 848 STBCR2.............................................. 849 STBCR3.............................................. 850 STBCR4.............................................. 851 STBCR5.............................................. 853 STBCR6.............................................. 854 TADCOBRA_4 .................................. 296 TADCOBRB_4................................... 296 TADCORA_4 ..................................... 296 TADCORB_4 ..................................... 296 TADCR............................................... 293 TBTER................................................ 321 TBTM ................................................. 288 TCBR.................................................. 318 TCDR.................................................. 317 TCNT.................................................. 297 TCNTCMPCLR.................................. 274 TCNTS................................................ 316 TCR .................................................... 248 TCSYSTR........................................... 302 TDDR ................................................. 317 TDER.................................................. 323 TGCR.................................................. 314 TGR .................................................... 297 TICCR ................................................ 289 TIER ................................................... 275 TIOR................................................... 255 TITCNT .............................................. 320 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 TITCR ................................................. 318 TMDR ................................................. 252 TOCR1................................................ 307 TOCR2................................................ 310 TOER .................................................. 306 TOLBR ............................................... 313 TRWER .............................................. 305 TSR ..................................................... 280 TSTR................................................... 298 TSYCR................................................ 291 TSYR .................................................. 300 TWCR ................................................. 324 WTCNT .............................................. 526 WTCSR............................................... 527 Register address table (in the order from lower addresses) ........ 864 Register bit list ........................................ 876 Register data format.................................. 20 Register states in each operating mode ... 894 Repeat transfer mode .............................. 177 Reset state ................................................. 45 Reset-synchronized PWM mode............. 356 RISC-type ................................................. 21 S SCI interrupt sources............................... 591 SCSPTR and SCI pins ............................ 592 Sending a break signal ............................ 595 Sequential break...................................... 143 Serial communication interface (SCI)..... 533 Shift instructions ....................................... 40 Single chip mode....................................... 49 Single mode ............................................ 616 Single-cycle scan mode........................... 617 Sleep mode.............................................. 856 Software protection................................. 791 Software standby mode........................... 857 Stack after interrupt exception handling .................................................. 112 Page 963 of 964 Stack states after exception handling ends........................................................... 86 Status register (SR) ................................... 17 System control instructions....................... 42 User break controller (UBC)................... 117 User break interrupt ................................ 105 User MAT ............................................... 742 User program mode ................................ 776 Using interval timer mode ...................... 531 Using watchdog timer mode ................... 530 T Target pins and conditions for highimpedance control................................... 516 The address map for the operating modes........................................................ 50 Transfer information read skip function................................................... 175 Transfer information writeback skip function................................................... 176 Trap instructions....................................... 83 V Vector numbers and vector table address offsets........................................................ 75 Vector-base register (VBR) ...................... 18 W Wait between access cycles .................... 223 Watchdog timer (WDT).......................... 523 U User boot mode....................................... 785 Page 964 of 964 R01UH0049EJ0400 Rev. 4.00 Sep 24, 2010 Renesas 32-Bit RISC Microcomputer SH7146 Group User's Manual: Hardware Publication Date: Rev.1.00, April 1, 2005 Rev.4.00, September 24, 2010 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. 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