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Features
Configurations:
Can be configured as a combination of keys and input/output line s
Number of QTouch® Keys:
Two to six
Number of I/O Lin es:
Seven, configurable for input or output, with PWM control fo r LED driv ing
Technology:
Patented spread-spectrum charge-tran sfer (direct mode)
Key Outline Sizes:
6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and
shapes possible
Layers Required:
One
Electrode Materials:
Etched copper
Silver
Carbon
Indium Tin Oxide (ITO)
Panel Materi als:
Plastic
Glass
Composites
Painted surfaces (l ow particle density metallic paints possible)
Panel Thickness:
Up to 10 mm glass (electrode size dependent)
Up to 5 mm plastic (electrode size dependent)
Key Sensitivity:
Individually settable via simple commands over serial interface
Interface:
I2C-compatible slave mode (100 kHz). Discrete detection outputs
Moisture Tolerance:
Increased moisture tolerance based on hardware design and firmware tuning
Signal Processing:
Self-calibration
auto drift compensation
noise filtering
Adjacent Key Suppression® (AKS®)
Applications:
Mobile appliances
Power:
1.8 V to 5.5 V
Package:
28-pin 4 x 4 mm QFN RoHS compliant IC
Atmel AT42QT1060
Six-channel QTouch® Touch Sensor IC
DATASHEET
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1. Pinout and Schematic
1.1 Pinout Configuration
1.2 Pin Descriptions
SNS0K
IO4
IO3
RST
SNS4K
SNS0
SNS2
SNS1K
SNS2K
VSS
VDD
IO5
VSS
IO0
IO1
1
2
3
4
5
6
715
16
17
18
19
20
21
28 27 26 25 24 23 22
8914
13
12
11
10
QT1060
IO6
SNS3K
SNS3
SNS4
VDD
IO2
SNS5K
SNS1
SNS5
VDD
CHG
SDA
SCL
Table 1-1. Pin Allocati on
Pin Name Type Description If Unused, Connect To...
1SNS1K I/O To Cs capacitor and to key Leave open
2SNS2K I/O To Cs capacitor and to key Leave open
3VDD PPositive power pin
4VSS PGround power pin
5IO5 I/O I/O Port Pin 5 Leave open and set as output
6IO6 I/O I/O Port Pin 6 Leave open and set as output
7SNS3K I/O To Cs capacitor and to key Leave open
8SNS4K I/O To Cs capacitor and to key Leave open
9SNS5K I/O To Cs capacitor and to key Leave open
10 SNS0 I/O To Cs Capacitor Leave open
11 SNS1 I/O To Cs Capacitor Leave open
12 SNS2 I/O To Cs Capacitor Leave open
13 SNS3 I/O To Cs Capacitor Leave open
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I Input only O Output only, push-pull I/O Input/output
OD Open drain output P Ground or power
14 SNS4 I/O To Cs Capacitor Leave open
15 SNS5 I/O To Cs Capacitor Leave open
16 VDD PPositive power pin
17 VDD PPositive power pin
18 VSS PGround power pin
19 IO0 I/O I/O Port Pin 0 Leave open and set as output
20 IO1 I/O I/O Port Pin 1 Leave open and set as output
21 IO2 I/O I/O Port Pin 2 Leave open and set as output
22 CHG OD Change line Leave open
23 SDA OD I2C Data line Resistor to Vdd or
Vss only in standalone mode
24 SCL OD I2C Clock Line Resistor to Vdd or
Vdd only in standalone mode
25 RST IReset, active low Vdd
26 IO3 I/O I/O Port Pin 3 Leave open and set as output
27 IO4 I/O I/O Port Pin 4 Leave open and set as output
28 SNS0K I/O To Cs capacitor and to key Leave open
Table 1-1. Pin Allocation (Continued)
Pin Name Type Description If Unused, Connect To...
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1.3 Schematic
Figure 1-1. Typical Circuit
Note: In some systems it may be desirable to connect RST to the master reset signal.
For component values in Figure 1-1 check the following sections:
•Section 3.1 on page 11: Cs capacitors (Cs0 – Cs5)
•Section 3.2 on page 11: Series resistors (Rs0 – Rs5)
•Section 3.5 on page 12: Voltage levels
•Section 4.4 on page 15: SDA, SCL pull-up resistors (not shown)
•Section 3.3 on page 11: LED traces
SNS4
KEY 4
VDD
14
13
12
3
KEY 3
KEY 2
CHG
SDA
SCL
23
24 I C Clock in
2-compatible
Cs4
Rs4
Rs3
Rs2
Cs3
Cs2
QT1060
I C-compatible Data
2
8
7
2
22
11
KEY 1
Rs1
Cs1
1
VDD
VDD
VDD
6
5
27
26
IO6
IO3
IO4
IO5
1617
SNS4K
SNS3K
SNS3
SNS2K
SNS2
SNS1K
SNS1
Keep these parts
close to the IC
Note: Bypass capacitor to be tightly wired between
Vdd and Vss. Follow
regulator manufacturer for input and output
capacitors.
recommendations from
Vunreg Voltage Reg
Note: The central pad on the underside of the chip is a
Vss pin and should be connected to ground.
18
VSS
Change
100k
VDD
Rchg
25 RST
100nF
CB1
4
VSS
IO Port
pins
SNS5
KEY 5
15 Cs5
Rs5
9
SNS5K
10
KEY 0
Rs0
Cs0
28
SNS0K
SNS0
21
20
19 IO0
IO1
IO2
SDA
SCL
23
24
VDD
Standalone Mode
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Suggested regulator manufacturers:
• Torex (XC6215 series)
• Seiko (S817 series)
• BCDSemi (AP2121 series)
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2. Overview
2.1 Introduction
The AT42QT1060 (QT1060) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed
specifically for mobile phone applications. The device can sense from two to six keys; up to four keys can be
disabled by not installing their respective sense capacitors (Cs). It also has up to seven configurable input/output
lines, with Pulse Width Modulation (PWM) for driving LEDs.
This device includes all sig nal processing functions ne cessary to provide stab le sensing under a wide variety of
changing conditions, and the outputs are fully de-bounced. Only a few external parts are required for operation.
The QT1060 modulates its bursts in a spread-spectrum fashion in or der to heavily suppress the effects of external
noise, and to suppress RF emissions.
2.2 Keys
The QT1060 can have a minimum o f two keys and a maximum of six ke ys. These can be constru cted in different
shapes and sizes. See “Features” on page 1 for the recommended dimensions.
Unused keys should be disabled by removing the corresponding Cs and Rs components and c onnecting the SNS
pins as shown in the If Unused column of Table on page 2. The unused keys are always pared from the burst
sequence in order to optimize speed. See Section 6. on page 25 about setting up the keys.
2.3 Standalone Mode
The QT1060 can operate in a standalone mode where an I2C-compatible interface is not required. To enter
standalone mode, connect SDA to Vss and SCL to Vdd before powering up the QT1060.
In standalone mode the default start-up values are used except for the I/O mask (Address 23). The I/O mask is
configured so that all the I/Os are outputs (I/O mask = 0x7F). This means that key detectio n is reported via th e
respective I/Os.
2.4 I/O Lines
2.4.1 Overview
There is an input/output (I/O) port consisting of seven lines that can be individually programmed as inputs or outputs.
They can be either a digital type or PWM. The PWM level can be set to 256 possible values and is common to all
lines.
The I/O lines are normally initialized as inputs. However, if an I2C interface is not used and the SDA and SCL pins
are connected to Vss and Vdd respectively, then the I/O lines are initialized as outputs (see Section 2.3).
The outputs can also be linked to either the detection channels or the output register to allow the outputs to be either
user controlled or to indicate detection. These options can be set in the pin control masks (see Table on page 16).
Unused I/O lines shou ld be disabled by connectin g as shown in the If Unused co lumn of Table 1-1 on page 2. See
Section 6. on page 25 about setting up the I/O lines.
2.4.2 I/O Mask
A 1 in any bit position of this mask sets the corresponding pin to an output. If a bit is 0, the pin is an input and the
function of the PWM, detect and active state masks will not matter for this pin. The level of the i nput pins is reflected
in the input Status register. Changes to the logic levels on the inputs cause the CHG line to be asserted.
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2.4.3 PWM Mask
A 1 in any bit position in this mask sets the corresponding pin to operate in PWM mode when its user output buffer is
active and configured as an output. A zero sets the pin in digital mode. The PWM value is set in the PWM register
that is writable via I2C communication.
2.4.4 Detection Mask
A 1 in any bit position in this mask sets the corresponding pin to be controlled by the status register. If the pin is
configured as an output, it is asserted automatically if there is a detection on the corresponding sensor channel. A
zero in any bit sets the pin to be controlled by the user output buffer, allowing the user to control the pins directly.
2.4.5 Active Level Mask
A 1 in any bit position in this mask sets the corresponding pin to be active high if configured as an output. A zero sets
the pin to be active low.
2.5 Acquisition/Low Power Modes (LP)
There are several different acquisition modes. These are controlled via the Low Power (LP) mode byte (see Section
5.12 on page 20) which can be written to via I2C communication.
LP mode controls the intervals between acquisition measurements. Longer intervals consume lower power but have
increased response time. During calibration and during the detect integrator (DI) period, the LP mode is temporarily
set to LP mode 1 for a faster response.
The QT1060 operation is based on a fixed cycle time of approximately 16 ms. The LP mode setting indicates how
many of these periods exist per measurement cycle. For example, if LP mode = 1, there is an acquisition every cycle
(16 ms). If LP mode = 3, there is an acquisition every 3 cycles (48 ms), and so on.
SLEEP mode (LP mode = 0) is available for minimum current drain. In this mode, the device is inactive, with the
device status being held as it was before going to sleep, and no measurements are carried out.
LP settings above mode 32 (512 ms) result in slower thermal drift compensation and should be avoided in
applications where fast thermal transients occur.
If LP mode = 255 the device operates in Free-run mode. In this mode the device will not enter LP mode between
measurements. The device continuously performs measurements one after another, resulting in the fastest
response time but the highest power consumption.
2.6 Adjacent Key Suppre ssion (AKS) Technology
The device includes the Atmel-patented Adjacent Key Suppression technology, to allow the use of tightly spaced
keys on a keypad with no loss of selectability by the user.
There can be one AKS group, implemented so that only one key in the group may be reported as being touched at
any one time. A key with a higher delta signal dominates and pushes a key with a smaller delta out of detect. This
allows a user to slide a finger across multiple keys with only the dominant key reporting touch.
The keys which are members of the AKS group can be set via the AKS mask (see Section 5.15 on page 21). Keys
outside the group may be in detect simultaneously.
For maximum flexibility there is no automatic key recalibration timeout on key detection. The user should issue a
recalibration command if the key has been in detect for too long, for example for more than 30 seconds (see Figure
2.10).
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2.7 Change Line
The Change line (see CHG in Figure 1-1 on page 4) signals when there is a change in state in the Detection or Input
status bytes and is active low. It is cleared (allowed to float high) when the host reads the status bytes.
If the status bytes change back to their original state before the host has read the status bytes (for example, a touch
followed by a release), the CHG line will be held low. In this case, a read to any memory location will clear the CHG
line.
The CHG line is open-drain and should be connected via a 100k resistor to Vdd. It is necessary for minimum power
operation as it ensures that the QT1060 can sleep for a s long as possible. Communications wake up the QT1060
from sleep causing a higher power consumption if the part is randomly polled.
The keys enabled by the key b it mask or a change in the Input p ort status cause a key change interrupt (see Table 5-
1 on page 16). Create a guard channel by removing that key from the key mask and including it in the AKS mask.
Touching the guard channel does not cause an interrupt. The key and AKS masks are set by using the mask
commands (see Table 5-1).
2.8 Types of Reset
2.8.1 Externa l Reset
An external reset logic line can be used if desired, fed into the RST pin. However, under most conditions it is
acceptable to tie RST to Vdd.
2.8.2 Soft Reset
The host can cause a device reset by writing a nonzero value to the reset byte. This soft reset triggers the internal
watchdog timer on a ~16 ms interval.
After ~16 ms the device resets and wakes again.
After a further 30 ms initialization period the device begins responding to its I2C slave address.
After another ~80 ms the device asserts the CHG line to indicate it is ready for touch sensing.
The device NACKs any attempts to communicate with it during the first 30 ms of its initialization period.
After CHG goes low, the device calibrates the sensing channels. When complete, the CHG pin is set low once again.
2.9 Moisture Tolerance
The presence of water (condensation, sweat, spilt water, and so on) on a s ensor can alter the signal values
measured and thereby affect the performance of any capacitive devi ce. The moisture tolerance of QTouch devices
can be improved by designing the hardware and fine-tuning the firmware following the recommendations in the
application note Atmel AVR3002: Moisture Tolerant QTouch Design (www.atmel.com/Images/doc42017.pdf).
2.10 Calibration
The command byte can force a recalibration at any time by writing a nonzero value to the calibration byte. This can
be useful to clear out a stuck key condition after a prolonged period of uninterrupted detection.
When the device rec alibrates, it also autosens es which keys are enab led by examining th e burst length of eac h
electrode. If the burst length is either too short (if there is a missing or open Cs capacitor) or too long (a Cs capacitor
is shorted), the key is ignored until the next calibration.
The count of the number of curre ntly enabled keys is found in the status response byte. Th is number can change
after a CAL command; for example, if a Cs capacitor is intermittent.
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2.11 Guard Channel
The device has a guard channe l option, which allows any key, or combinatio n of keys, to be configur ed as a guard
channel to help prevent false detection. Guard channel keys should be more sensitive than the other keys (physically
bigger or larger Cs), subject to burst length limitations (see Section 2.12.3).
With guard channel ena bled, the designated key(s ) is connected to a sensor pad wh ich detects the presence of
touch and overrides any output from the other keys using the chip AKS feature. The guard channel option is enabled
by an I2C command.
To enable a guard channel the relevant key should be removed from the key mask (see Table 5-1 on page 16). In
addition, the guard channel needs to be inc luded within the AKS mask with the other keys for the guard function to
operate. Note that a detection on the guard channel does not cause a change request.
With the guard channel not enabled, all the keys work normally.
Figure 2-1. Guard Channel Example
2.12 Signal Processing
2.12.1 Detect Threshold
The device detects a touch when the signal has crossed a threshold level and remained there for a specified number
of counts (s ee Section 5.11 on page 19 ). This can be altered on a key-by-key basis using the key threshold I2C
commands.
2.12.2 Detect Integrat or
The device features a fast detection integrator counter (DI filter), which acts to filter out noise at the small expense of
slower response time. The DI filter requires a programmable number of consecutive samples confirmed in detection
before the key is declared to be touch ed. There is also a fast DI on the end of the detection (see Sect ion 5.20 on
page 23). The fast DI will not be applied at the start of a detection if a detection on any other channel has already
been declared.
2.12.3 Burst Length Limitations
In a balanced system common signals are regarded as thermal shifts and are removed by the relative referencing
drifting, if enabled. This means that the burst lengths must be similar. This can be checked by reading the reference
values (Address 52 – 63) and making sure that they are similar. The absolute maximum difference is that the
maximum value of reference is less than three times the minimum value amongst all the channels. It is
recommended having the burst lengths (references) as close together as possible, through better routing and layout.
For example, if the keys have refe rences of 250, 230, 220, 240, 20 0 and 210, this is acceptable. If the keys have
references of 250, 230, 220, 240, 200 and 710, the efficiency of the relative referencing drifting will be affected. The
last key’s (710) layout should be changed or relative referencing be disabled. The closer the references are in value,
the better the relative referencing drifting performs.
Guard channel
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If only normal drifting is enabled, the burst lengths can have bigger variations.
The normal operating limit of burst lengths is between 16 and 1536 counts. A value out of these limits causes the
respective key to be disabled and not measured until a calibration. Signal value for an out-of-limit key is zero.
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3. Wiring and Parts
3.1 Cs Sample Capacitors
Cs0 – Cs5 are the cha rge sensing sample capacitors; norma lly they are identical in nomina l value. The optimal Cs
values depend on th e thickness of the pan el and its dielectric con stant. Thicker pane ls require larger values of Cs.
Typical values are 2.2 nF to 10 nF.
The value of Cs should be chosen s o that a light touch on a ke y produces a reduction o f ~10 – 20 in the key signal
value (see Section 5.22 on page 23). The chosen Cs value should never be so large that the key signals exceed
~1000, as reported by the chip in the debug data.
The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they should have a
10% tolerance. A 20% tolerance may cause small differences in sensitivity from key to key and unit to unit. If a
channel is not used, the Cs capacitor may be omitted.
3.2 Rs Resistors
Series resistors Rs (Rs0 – Rs5) are inline with the electrode connections and should be used to limit electrostatic
discharge (ESD) currents and to suppress radio frequency (RF) interference. They should be approximately 4.7 k
to 20 k each.
Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency
interference (RFI). For details of how to select these resistors see the Application Note QTAN0002, Secrets of a
Successful QTouch Design, downloadable from the Touch Technology area of the Atmel website, www.atmel.com.
3.3 LED Traces and Other Switching Signals
Digital switching signals near the sense lines induce transients into the acquired signals, deteriorating the SNR
performance of the device. Such signals should be routed away from the sensing traces and electrodes, or the
design should be such that these lines are not switched during the course of signal acquisition (bursts).
LED terminals which are multiplexed or switched into a floating state, and which are within, or physically very near, a
key (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10 nF capacitor. This is
to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to
be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type.
LED terminals which are constantly connected to Vss or Vdd do not need further bypassing.
3.4 PCB Cleanliness
Modern no-clean flux is generally compatible with capacitive sensing circuits.
If a PCB is reworked in any way, clean it thoroughly to remove all traces of the flux residue around the capacitive
sensor components. Dry it thoroughly before any further testing is conducted.
CAUTION: If a PCB is reworked to correct soldering faults relating to the device, or to
any associated traces or components, be sure that you fully understand the nature of the
flux used during the rework process. Leakage currents from hygroscopic ionic residues
can stop capacitive sensors from functioning. If you have any doubts, a thorough
cleaning after rework may be the only safe option.
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3.5 Power Supply
See Section 7.2 on page 26 for the power supply range . If the power supply fluctuates slowly with temperature, the
device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply
voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity
anomalies or false detections.
The usual power supply considerations with QT parts ap ply to the device. The power should be clean and come from
a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and
except in extreme conditions should not require a separate Low Dropout (LDO) regulator.
See underneath Figure 1-1 on page 4 for suggested regulator manufacturers.
It is assumed that a larger bypass capacitor (~1 µF) is so mewhere else in the power circuit; for example, near the
regulator.
To assist with transient regulator stability problems, the QT1060 waits 500 µs any time it wakes up from a sleep state
(that is, in SLEEP and LP modes) before acquiring, to allow Vdd to fully stabilize.
3.6 Bus Specification
Caution: A regulator IC shared with other logic can result in erratic operation and is not
advised.
A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very close
to the power pins of th e IC. Failure to do so can result in dev ice oscillation, high current
consumption, erratic operation, and so on.
Table 3-1. I2C Bus Specifi c ati on
Parameter Unit
Address space 7-bit
Maximum bus speed (SCL) 100 kHz
Hold time START condition 4 µs minimum
Setup time for STOP condition 4 µs minimum
Bus free time between a STOP and START condition 4.7 µs minimum
Rise times on SDA and SCL 1 µs maximum
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4. I2C Communications
4.1 I2C Protocol
4.1.1 Protocol
The I2C protocol is based around access to an address table (see Table 5-1 on page 16) and supports multibyte
reads and writes. The maximum clock rate is 100 kHz.
4.1.2 Signals
The I2C interface requires two signals to operate:
SDA - Serial Data
SCL - Serial Clock
A third line, CHG, is used to signal when the device has seen a change in the status byte:
CHG: Open-drain, active low when any cap acitive key in the key mask has changed st ate or any input line has
changed state since the last I2C read. After reading the two status bytes, this pin floats (high) again if it is
pulled up with an external resistor. If the status bytes change back to their original state before the host has
read the status bytes (for example, a touch followed by a release), the CHG line will be held low. In this case,
a read to any memory location will clear the CHG line.
4.1.3 Clock Stretching
The device has an internal monitor that resets its I2C hardware if either I2C-compatible line is held low, without the
other line changing, for more than about 14 ms. It is important th at no other device on the b us clock stretches for
14 ms, otherwise the monitor will reset the I2C hardware and transfers with the chip may be corrupted.
If the device is configured to run in stand-alone mode, the monitor will be turned off.
4.2 I2C Address
There is one preset I2C address of 0x12. This is not changeable.
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4.3 Data Read/Write
4.3.1 Writing Data to th e Device
The sequence of events required to write data to the device is shown next
.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to write to.
5. The device sends an ACK.
6. The host transmits one or more data bytes; each is acknowledged by the device.
7. If the host sends more than one data byte, they are written to consecutive memory addresses.
8. The device automatically increments the target memory address after writing each data byte.
9. After writing the last data byte, the host should send the STOP condition.
Note: the host shou ld not try to writ e beyond addres s 255 becaus e this is the limit of th e device’s intern al memory
address.
4.3.2 Reading Data From the Device
The sequence of events required to read data from the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to read from.
5. The device sends an ACK.
Table 4-1. Description of Write Data Bits
Key Description
SStart condition
SLA+W Slave address plus write bit
AAcknowledge bit
MemAddress Target memory address within de vice
Data Data to be written
PStop condition
SLA+W MemAddress
AASData A P
Host to Device Device Tx to Host
SLA+W MemAddress
AASSSLA+R A
AP
Host to Device Device Tx to Host
P
AA
Data 1 Data 2 Data n
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6. The host must then send a STOP and a START condition followed by the slave address again but this time
accompanied by the READ bit.
7. The device returns an ACK, followed by a data byte.
8. The host must return either an ACK or NACK.
1. If the host returns an ACK, the device subsequently transmits the dat a byte from the next address. Each
time a data byte is transmitted, the device automatically increments the internal address. The device
continues to return data bytes until the host responds with a NACK.
2. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition.
9. The device resets the internal address to the location indicated by the memory address sent to it previously.
Therefore, there is no need to send the memory address again when reading from the same location.
4.4 SDA, SCL
The I2C bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I2C master and
slave devices can only drive these lines low or leave them open. Th e termination resistors (not shown) pull the line
up to Vdd if no I2C-compatible device is pulling it down.
The termination resistors commonly range from 1 k to 10 k and s hould be chosen so that the rise times on SDA
and SCL meet the I2C specifications (1 µs maximum).
Standalone mode: if I2C-compatible communications are not required, then standalone mode can be enabled by
connecting SDA to Vss and SCL to Vdd. See Section 2.3 on page 6 for more information.
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5. Setups
5.1 Introduction
The device calibrates an d processes signals us ing a number of algorithms specifically designed to pro vide for high
survivability in the face of adve rse environmental challenges. User-defined Se tups are employed to alter these
algorithms to suit each application. These Setups are loaded into the device over the I2C serial interfaces.
Table 5-1. Internal Register Address Allocation
Address Use R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0Chip ID RMajor ID (= 3) Minor ID (= 1)
1Version RDevice version number
2Minor version RMinor version number
3Reserved Reserved
4Detection status RCalibrating Res Key5 Key4 Key3 Key2 Key1 Key0
5Input port status RRes Input 6 Input 5 Input 4 Input 3 Input 2 Inpu t 1 Input 0
6–11 Reserved Reserved
12 Calibrate R/W Writing a nonzero value forces a calibration
13 Reset R/W Writing a nonzero value forces a reset
14 Drift Option R/W Res Res Res Res Res Res Res DRIFT
15 Positive
Recalibration Delay R/W MSB LSB
16 NTHR key 0 R/W MSB LSB
17 NTHR key 1 R/W MSB LSB
18 NTHR key 2 R/W MSB LSB
19 NTHR key 3 R/W MSB LSB
20 NTHR key 4 R/W MSB LSB
21 NTHR key 5 R/W MSB LSB
22 LP mode R/W MSB LSB
23 I/O mask R/W MSB IO6 IO5 IO4 IO3 IO2 IO1 IO0
24 Key mask R/W CAL Res Key 5 Key 4 Key 3 Key 2 Key 1 Key 0
25 AKS mask R/W Res Res Key 5 Key 4 Key 3 Key 2 Key 1 Key 0
26 PWM mask R/W Res IO6 IO5 IO4 IO3 IO2 IO1 IO0
27 Detection mask R/W Res IO6 IO5 IO4 IO3 IO2 IO1 IO0
28 Active level mask R/W Res IO6 IO5 IO4 IO3 IO2 IO1 IO0
29 User output buffer R/W Res IO6 IO5 IO4 IO3 IO2 IO1 IO0
30 DI R/W MSB LSB
31 PWM level R/W MSB LSB
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5.2 Address 0: Chip ID
MAJOR ID: Reads back as 3
MINOR ID: Reads back as 1
5.3 Address 1: Device Version Number
DEVICE VERSION NUMBER: this is the 8-bit firmware version number (0x03).
5.4 Address 2: Minor Version Number
MINOR VERSION NUMBER: this is the 8-bit minor firmware revision number (0x00).
32–39 Reserved Reserved
40–51 Key 0–5 Signal R
52–63 Key 0–5 Reference R
Note: Res = Reserved; only write zero to these bits.
Table 5-1. Internal Register Address Allocation (Continued)
Address Use R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Table 5-2. Chip ID
Address b7 b6 b5 b4 b3 b2 b1 b0
0MAJOR ID MINOR ID
Table 5-3. Device Version Number
Address b7 b6 b5 b4 b3 b2 b1 b0
1DEVICE VERSION NUMBER
Table 5-4. Minor Version Number
Address b7 b6 b5 b4 b3 b2 b1 b0
2MINOR VERSION NUMBER
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5.5 Address 4: Detection Status
CAL: a 1 indicates that the QT1060 is currently calibrating.
KEY0 – 5: bits 0 to 5 indicate which keys are in detection, if any; touched keys report as 1, untouched or disabled
keys report as 0.
5.6 Address 5: Input Port Status
INPUT 0 – 6: thes e bits indicate the st ate of the I/O lines that are configured as inputs ; 1indicating logic 1 on th e
input, 0 indicating logic 0. The bits corresponding to any keys configured as outputs read as 0.
5.7 Address 12: Calibrate
Writing any nonzero value into this address triggers the device to start a calibration cycle. The CAL flag in the status
register is set when begun and cleared when the calibration has finished.
5.8 Address 13: Reset
Writing any nonzero value to this address triggers the device to reset.
Table 5-5. Detection Status
Address b7 b6 b5 b4 b3 b2 b1 b0
4CAL Reserved KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
Table 5-6. Input Port Status
Address b7 b6 b5 b4 b3 b2 b1 b0
5Reserved INPUT 6 INPUT 5 INPUT 4 INPUT 3 INPUT 2 INPUT 1 INPUT 0
Table 5-7. Calibrate
Address b7 b6 b5 b4 b3 b2 b1 b0
12 Writing a nonzero value forces a calibration
Table 5-8. Reset
Address b7 b6 b5 b4 b3 b2 b1 b0
13 Writing a nonzero value forces a reset
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5.9 Address 14: Drift Option
DRIFT: there are two types of drift option: normal and relative referencing.
If DRIFT = 0, relative referencing and normal drift are enabled.
If DRIFT = 1, only normal drift is enabled.
Relative referencing compensates for fast signal drifts that are common to all keys. This mode is suitable if the keys
are placed clo se to each other and ha ve closely matched bu rst lengths (see Section 2.12.3 on page 9). Normal
drifting is also carried out but at a slower rate compared to the relative referencing drift rate.
Default: 1 (relative referencing Off)
5.10 Address 15: Positive Recalibration Delay
POSITIVE RECALIBRATION DELAY: If any key is found to have a significant drop in capacitance, that is, an “away
from touch” signal, th en this is deemed to be an error condition. If this c ondition persists for more than the Positive
Recalibration Delay (PRD) period, then an automatic recalibration is carried out on all keys.
The condition that the error is triggered on depends on the drift compensation mode. If relative referencing drifting is
enabled (DRIFT = 0), then an “away from touch” delta of more than four counts triggers the error. If only normal
mode drifting is enabled (DRIFT = 1), then an “away from touch” delta of more than 75% of the NTHR triggers the
error.
In LP mode the Positive Recalibration Delay is the PRD value multiplied by 16 ms cycle time; in Free Run Mode the
Positive Recalibration delay is the PRD value multiplied by the minimum cycle time (~7 ms, but depends on Cs and
design).
Default: 40 (40 × 16 ms = 640 ms; default LP is 32 ms)
5.11 Address 16 – 21: NTHR Keys 0 – 5
NTHR Keys 0 – 5: these 8-bit values set the threshold value for each key to register a detection.
Default: 10 counts
Table 5-9. Drift Option
Address b7 b6 b5 b4 b3 b2 b1 b0
14 Reserved DRIFT
Table 5-10. Positive Recalibration Delay
Address b7 b6 b5 b4 b3 b2 b1 b0
15 POSITIVE RECALIBRATION DELAY
Table 5-11. NTHR Keys 0 – 5
Address b7 b6 b5 b4 b3 b2 b1 b0
16–21 MSB LSB
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5.12 Address 22: LP Mode
LP Mode: this 8-bit value determines the number of 16 ms intervals between key measurements. Longer intervals
between measurements yield lower power consumption at the expense of slower response to touch.
A value of zero causes the device to enter SLEEP mode where no measurements are performed.
A value of 255 causes the device to enter Free-run mode where measurements are continuously performed without
entering a low power mode between measure ments. This prov ides the fastest resp onse time but also the highest
power consumption.
Default: 2 (32 ms between key acquisitions)
5.13 Address 23: I/O Mask
IO0 – IO6: these bits control the direction of the I/O pins. A 1 sets the pin as an output, a 0 as an input. See Section
5.24 on page 24 for I/O register precedence and example usage.
Default: 0 (all I/Os are set as inputs, when using the I2C-compatible mode)
(all I/Os are set as outputs (0x7F), when using the standalone mode)
Table 5-12. LP Mode
Address b7 b6 b5 b4 b3 b2 b1 b0
22 MSB LSB
LP7 –0Mode
0SLEEP
116 ms
232 ms
348 ms
464 ms
... ...
254 4.064 s
255 Free-run
Table 5-13. I/O Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
23 Reserved IO6 IO5 IO4 IO3 IO2 IO1 IO0
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5.14 Address 24: Key Mask
CAL: this bit controls whether the CAL bit causes a CHG transition.
KEY0 – 5 (Key Mask): these bits control wh ether a change in the correspond ing bit in the detection status register
generates a transition on the CHG line. A 1 allows the status bit to cause a CHG request, a 0 stops the
corresponding bit from causing a CHG request.
Default: 0xBF (all bits create a CHG request)
5.15 Address 25: AKS Mask
KEY0 – 5 (AKS Mask): these bits control which keys are included in the AKS group. A 1 means the corresponding
key is included in the AKS group and may only go into detect when it has the largest signal change of any key in the
group. A 0 means that it is excluded and can go into detect whenever its threshold is passed.
Default: 0x00 (no keys are within the AKS group)
5.16 Address 26: PWM Mask
I/O0 – 6 (PWM Mask): these bits control which I/Os that are configured as outputs, and its user output buffer
activated, will output a PWM signal. A 1 means the output generates a PWM signal, a 0 means the output generates
a logic level. The a ctive level of the output (bot h logical and PWM) is determined by th e Active level mask. See
Section 5.24 on page 24 for I/O register precedence and example usage.
Default: 0x00 (PWM is off on all I/Os)
Table 5-14. Key Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
24 CAL Reserved KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
Table 5-15. AKS Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
25 Reserved Reserved KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
Table 5-16. PWM Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
26 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
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5.17 Address 27: Detection Mask
I/O0 – 6 (Detection Mask): these bit s control which I/Os that are configured as ou tputs will be controlled by their
corresponding capacitive key. A 1 means the output n generates an active output when key n is detecting a touch. A
0 means that the output is controlled by the output buffer. See Section 5.24 on page 24 for I/O register precedence
and example usage.
Default: 0x3F (all I/Os are controlled by key status)
5.18 Address 28: Active Level Mask
I/O0 – 6 (Active Level Mask): these bits control the active logic level for the I/Os that are configured as outputs. A 1
means the output generates an active high output, a 0 means that the output is active low. See Section 5.24 for I/O
register precedence and example usage.
Default: 0 (all I/Os are active low output)
5.19 Address 29: User Output Buffer
I/O0 – 6 (User Output Buffer): these bits control the output level for the I/Os that are configured as outputs. A 1
means the output generates an active output, a 0 means that the output is inactive. See Section 5.24 on page 24 for
I/O register precedence and example usage.
Default: 0 (all I/Os inactive)
Table 5-17. Detection Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
27 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Table 5-18. Active Level Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
28 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Table 5-19. User Output Buffer
Address b7 b6 b5 b4 b3 b2 b1 b0
29 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
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5.20 Address 30: Detection Integrator
DETECTION INTEGRATOR: this 8-bit value controls the number of co nsecutive measurements that must be
confirmed as having passed the key threshold before that key is registered as being in detect. A value of zero should
not be used.
Default: 3
5.21 Address 31: PWM Level
PWM LEVEL: this 8-bit value controls the duty cycle of the PWM output signal. Valid values are between 0...255.
There is a constant level band at either end of the range, so:
A value of 0...10 gives a 100% low output
A value of 250...255 gives a 100% high output
Default: 128 (50:50 duty cycle)
5.22 Address 40 – 51: Key Signal
KEY SIGNAL: addresses 40 – 51 allow key signals to be read for each key, starting with key 0. There are two bytes
of data for each key. These are the key ’s 16-bit key signal s which are accessed as two 8-bit bytes, stored LSB first.
These addresses are read-only.
Table 5-20. Detection Integrator
Address b7 b6 b5 b4 b3 b2 b1 b0
30 MSB DETECTION INTEGRATOR LSB
Table 5-21. PWM Level
Address b7 b6 b5 b4 b3 b2 b1 b0
31 MSB PWM LEVEL LSB
Table 5-22. Key Signal
Address b7 b6 b5 b4 b3 b2 b1 b0
40 LSB OF KEY SIGNAL FOR KEY 0
41 MSB OF KEY SIGNAL FOR KEY 0
42–51 LSB/MSB OF KEY SIGNAL FOR KEYS 1 – 5
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5.23 Address 52 –63: Reference Data
REFERENCE DATA: addresses 52 – 63 allow reference data to be read for each key, starting with key 0. There are
two bytes of data for each key. These are the key’s 16-bit reference data which is accessed as two 8-bit bytes, stored
LSB first. These addresses are read-only.
5.24 Mask Precedence
Table 5-24 gives the order of priority for the settings in the mask inputs/outputs. The settings in the left-most column
have the highest priority, those in the second-left have the next priority, and so on. If two or more settings are
incompatible then the sett ing in the left-hand column overrides the other. The right-m ost column, I/O Function,
specifies the expected result.
Note: X = don’t care (can be a 1 or a 0)
Table 5-23. Reference Data
Address b7 b6 b5 b4 b3 b2 b1 b0
52 LSB OF REFERENCE DATA FOR KEY 0
53 MSB OF REFERENCE DATA FOR KEY 0
54 – 63 LSB/MSB OF REFERENCE DATA FOR KEYS 1 – 5
Table 5-24. Input/Output Mask Precedence
I/O Mask
(bit n) Detection
Mask (bit n) PWM Mask
(bit n) Active Leve l
Mask (bit n) User Reg
(bit n) QTouch Key
(channel n) I/O Function
(I/O n)
0 X X X X X Digital Input
1 0 0 0 0 X Output - Vdd
1 0 0 0 1 X Output - 0 V
1 0 0 1 0 X Output - 0 V
1 0 0 1 1 X Output - Vdd
1 0 1 0 0 X Output - Vdd
1 0 1 0 1 X PWM Output
1 0 1 1 0 X Output - 0 V
1 0 1 1 1 X PWM Output
1 1 0 0 X Untouched Output - Vdd
1 1 0 0 X Touched Output - 0 V
1 1 0 1 X Untouched Output - 0 V
1 1 0 1 X Touched Output - Vdd
1 1 1 0 X Untouched Output - Vdd
1 1 1 0 X Touched PWM Output
1 1 1 1 X Untouched Output - 0 V
1 1 1 1 X Touched PWM Output
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6. Setting Up Procedures
Set the number of keys required by
leaving the SNS pins unconnected in
unused keys.
Determine whether a change in the
corresponding bit in the detection
status register generates a transition
on the CHG line.
[Address 24: Key Mask]
Determine which keys are in the AKS
group.
[Address 25: AKS Mask]
Determine the number of
measurements that must be
confirmed as having passed the key
threshold before that key is registered
as being in detect.
[Address 30: Detection Integrator]
To Set Up Keys
Tune the sensitivity of the keys by
adjusting the value of the sampling
capacitor, Cs and the negative
threshold (NTHR)
[Address 16 – 21: NTHR]
Determine the direction of the I/O
lines. If any lines are unused, set
them to be outputs and leave them
unconnected.
[Address 23: I/O Mask]
Determine which I/Os that are
configured as outputs will be
controlled by their corresponding
capacitive key.
[Address 27: Detection Mask]
To Set Up I/O Lines
Determine which I/Os that are
configured as outputs will output a
PWM signal.
[Address 26: PWM Mask]
Determine the active logic level for the
I/Os that are configured as outputs.
[Address 28: Active Level Mask]
Determine the output level for the I/Os
that are configured as outputs.
[Address 29: User Output Buffer]
Determine the duty cycle of the PWM
output signal.
[Address 31: PWM Level]
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7. Specifications
7.1 Absolute Maximum Specifications
7.2 Recommended Operating Conditions
7.3 DC Sp ecifications
Vdd –0.5 to +6 V
Max continuous pin current, any control or drive pin ±10 mA
Short circuit duration to ground, any pin infinite
Short circuit duration to Vdd, any pin infinite
Voltage forced onto any pin –0.6 V to (Vdd + 0.6) V
CAUTION: Stresses beyo nd those listed under Absolute Maximum Specifications may cause permane nt damage to
the device. This is a stress rating only and functional operation of the device at these or other conditions beyond
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
specification conditions for extended periods may affect device reliability.
Operating temp –40oC to +85oC
Storage temp –55oC to +125oC
Vdd +1.8 V to 5.5 V
Supply ripple+noise ±25 mV
Cx load capacitance per key 2 – 20 pF
Vdd = 3.3 V, Cs = 10 nF, load = 5 pF, 32 ms default sleep, Ta = recommended rang e, unless otherwi se noted
Parameter Description Minimum Typical Maximum Units Notes
Vil Low input logic leve l – – 0.2 × Vdd V
Vih High input logic level 0.6 × Vdd – – V
Vol Low outpu t voltage – – 0.5 V4mA sink
Voh High output voltage Vdd – 0.7 V – – V 1 mA source
Iil Input leakage current – – ±1µA
Ar Acquisition resolution – 8 – bits
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7.4 Current Consumption
7.5 Timing Specifications
Cs = 10nF, Cx = 5 pF, Rs = 10k
LP Mode
Idd (µA) at Vdd =
5V 3.3 V 1.8 V
0 (SLEEP) 2.48 1.8 1.1
1 (16 m s) 1745 1135 403
2 (32 m s) 1615 1065 373
4 (64 m s) 1545 1030 360
8 (128 ms) 1510 1010 351
16 (256 ms) 1500 1000 348
32 (512 ms) 1485 995 346
64 (1024 ms) 1475 992 345
Parameter Description Minimum Typical Maximum Units Notes
TRResponse time DI setting ×16 ms –LP mode +
(DI setting ×16 ms) ms Under host contro l
FQT Sample frequency 162 180 198 kHz Modulated spread-
spectrum (chirp)
TD
Power-up delay to
operate/calibration
time –<230 –ms Can be longer if
burst is very long.
FI2C I2C clock rate – – 100 kHz –
Fm Burst modulation, –±8 – % –
Reset pulse width 5 – – µs –
Clock stretch –25 40 µs –
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7.6 Mechanical Dimensions
Note: The central pad on the underside of the QFN chip should be connected to ground. Do not run any tracks
underneath the body of the chip, only ground.
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7.7 Marking
There are two possible types of chip marking.
1
28
Pin1ID
LTCODE
Chip Traceability
Code
1060
AT
Program week code number 1-52 where:
A = 1, B = 2...Z = 26
then using the underscore
A=27...Z=52
Abbreviation of Part
number;
AT42QT1060-MMU
1
28
Pin 1 ID
Part number;
AT42QT1060-MMU
AT42
LTCODE
Chip
Traceability
Code
-MMU
QT1060
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7.8 Part Number
The part number comprises:
AT = Atmel
42 = Touch Business Unit
QT = Charge-transfer technology
1060 = (1) Keys (06) number of channels (0) variant number
MMU = Package identifier
7.9 Moisture Sensitivity Level (MSL)
Part Number Description
AT42QT1060-MMU 28-pin 4 x 4 mm QFN RoHS compliant IC
MSL Rating Peak Body Temperature Specifications
MSL1 260oCIPC/JEDEC J-STD-020
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Appendix A. I2C Basics
A.1 Interface Bus
The device communicates with the host over an I2C bus. The following sectio ns give an overview of the bus; more
detailed information is available from www.i2C-bus.org. Devices are connected to the I2C bus as shown in Figure A-
1. Both bus lines ar e connected to Vdd via pull-up resistors. The bus drivers of all I2C devices must be open-drain
type. This implements a wired AND function that allows any and all devices to drive the bus, one at a time. A low
level on the bus is generated when a device outputs a zero.
Figure A-1. I2C Interface Bus
A.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be
stable when the clock line is high; the only exception to this rule is for generating START and STOP conditions.
Figure A-2. Data Transfer
Device 1 Device 2 Device 3 Device n R1 R2
Vdd
SDA
SCL
SDA
SCL
Data Stable Data Stable
Data Change
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A.3 START and STOP Conditions
The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START
condition on the bus, and is terminated when the host issues a STOP condition. Between the START and STOP
conditions, the bu s is considered busy. As shown in Figure A-3, START and STOP condit ions are signaled by
changing the level of the SDA line when the SCL line is high.
Figure A-3. START and STOP Conditions
A.4 Address Byte Format
All address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit.
If the READ/WRITE b it is set, a read ope ration is performed, o therwise a write operat ion is performed. Whe n the
device recognizes that it is being addressed, it will acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An
address byte consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with
that selected with the option jumpers.
Figure A-4. Address Byte Format
SDA
SCL
START STOP
Addr MSB Addr LSB R/W ACK
SDA
SCL
START 12 789
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A.5 Data Byte Format
All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data transfer, the host
generates the clock and the START and STOP cond itions, while the receiver is responsible for acknowledging the
reception. An acknowledge (ACK) is signaled by the receiver pulling the SDA li ne low during the ninth SCL cycle. If
the receiver leaves the SDA line high, a NACK is signaled.
Figure A-5. Data Byte Format
A.6 Combining Address and Data Bytes into a Transmission
A transmission consis ts of a START condition, an SLA+R/W, one or more data by tes and a STOP condition. The
wired ANDing of the SCL line is used to implement hands haking between the host and the devic e. The device
extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the
data transmissions.
Note: Each write or read cy cle must end with a stop cond ition. The device may not resp ond correctly if a cyc le is
terminated by a new start condition.
Figure A-6 shows a typical data transmission. Note that several data bytes can be transmitted between the
SLA+R/W and the STOP.
Figure A-6. Byte Transmission
A.7
Data MSB Data LSB ACK
Aggregate
SDA
SCL from
Master
12 789
SDA from
Transmitter
SDA from
Receiver
Data Byte Stop or
Data Byte
Next
SLA+R/W
Data MSB Data LSB ACK
12 789
Addr MSB Addr LSB R/W ACK
SDA
SCL
START 12 789
SLA+RW Data Byte STOP
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Revision History
Revision Number History
Revision A – September 2008 Initial Release for code revision 3.0
Revision B – October 2008 Minor amendments to burst length limitations
Revision C – November 2008 Minor amendments to improve clarity
Revision D – December 2008 Chip ID updated
Revision E – February 2009 Additional information on I2C interface added
Revision F – November 2012 Updated PWM information and clock stretch timing added
Revision G – May 2013 Applied new template
Revision H – April 2015 Updated MSL value from 3 to 1
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 |www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-9505H-AT42_04/2015.
Atmel®, Atmel logo, Enabling Unlimited Possiblities® and combinations thereof, Adjacent Key Suppression®, AKS®, QTouch®,and others are registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
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