ISL88021IU8HAZ - Intersil Corporation

FN8226.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL88021, ISL88022

Triple Voltage Monitor with Adjustable

Power-On-Reset and Undervoltage/

Overvoltage Monitoring Capability

The ISL88021 and ISL88022 family of devices are

customizable triple voltage-monitoring supervisors that

assert a reset if any of the monitored voltages becomes

non-compliant. They offer popular functions such as

Power-On-Reset timing control with both RESET and

RESET outputs, Supply Voltage Supervision, both under or

overvoltage detection, and Manual Reset assertion. By

offe ri n g th ese features in a small 8 Ld MS OP package, the

ISL88021 and ISL88022 can lower system cost, redu ce

board space requirements and increase the reliability of

systems.

Applying a voltage to VDD activates the Power-On-Reset

circuit which holds RESET low for an adjustable period of

time. This allows the power supply and system oscillator to

stabilize before the processor can execute code.

Low VDD detection circuitry protects the user’s system from

low voltage conditions, resetting the system when VDD falls

below its minimum preset voltage threshold VTH1. Reset

remains asserted until VDD returns to its proper operating

level and stabilizes. Two additional voltage monitoring

inputs, V2MON (preset) and V3MON (adjust able), monitor

other supplies to provide reliable system operati on.

The ISL88021 V3MON input monitors for undervoltage (UV)

conditions whereas the ISL88022 V3MON input allows

monitoring for overvoltage (OV) conditions. The monitored

voltage on V3MON on either device is compared via a

resistor divider to a 600mV internal reference. Hence, any

voltage more or less positive than this reference can be

accurately monitored to meet specific system level

requirements or to fine-tune the threshold for applications

requiring higher preci s ion.

These devices also let users increase the Power-On-Reset

time-out delay by connecting a capacitor between CPOR and

ground. This lengthens the period of an internal clock

counter thereby increasing the time between voltage

compliance and reset outputs signaling.

A manual reset input provides debounce circuitry for

minimum reset component count.

Features

• Triple Voltage Monitor and Reset Assertion

•Low V

DD Detection and Reset Assertion

- Adjus table Reset Threshold Voltages

- 0.6V ±6mV Over -40°C to +85°C

- Reset Signal Valid to VDD = 1V

• 140ms Minimum Reset Pulse Delay that is Customizable

Using an External Capacitor

• Both RST and RST Outputs Available

• Undervoltage/Overvoltage Monitoring Capability

• Low 20µ A Co nsumption

• Small 8 Ld MSOP Package

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Process Control Systems

• Intelligent Instruments

• Embedded Control Systems

• Computer Systems

• Portable/Battery-Powered Equipment

• Multi-Voltage Systems

Pinout ISL88021, ISL88022

(8 LD MSOP)

TOP VIEW

VDD

V2MON

GND

RST

CPOR

V3MON

Data Sheet September 18, 2006

2FN8226.1

September 18, 2006

Block Diagrams

Ordering Information (See Notes)

PART

NUMBER PART

MARKING VDD

VTRIP1

V2MO

VTRIP2

V3MON

TYPE PACKAGE

ISL88021IU8FAZ ANM 3.09V 1.69V UV 8 Ld MSOP

ISL88021IU8FCZ ANL 3.09V 2.32V UV 8 Ld MSOP

ISL88021IU8FEZ 3.09V 2.92V UV 8 Ld MSOP

ISL88021IU8FFZ 3.09V 3.09V UV 8 Ld MSOP

ISL88021IU8HAZ 4.64V 1.69V UV 8 Ld MSOP

ISL88021IU8HCZ 4.64V 2.32V UV 8 Ld MSOP

ISL88021IU8HEZ ANK 4.64V 2.92V UV 8 Ld MSOP

ISL88021IU8HFZ ANJ 4.64V 3.09V UV 8 Ld MSOP

ISL88022IU8FAZ ANQ 3.09V 1.69V OV 8 Ld MSOP

ISL88022IU8FCZ ANP 3.09V 2.32V OV 8 Ld MSOP

ISL88022IU8FEZ 3.09V 2.92V OV 8 Ld MSOP

ISL88022IU8FFZ 3.09V 3.09V OV 8 Ld MSOP

ISL88022IU8HAZ 4.64V 1.69V OV 8 Ld MSOP

ISL88022IU8HCZ 4.64V 2.32V OV 8 Ld MSOP

ISL88022IU8HEZ ANO 4.64V 2.92V OV 8 Ld MSOP

ISL88022IU8HFZ ANN 4.64V 3.09V OV 8 Ld MSOP

NOTES:

1. S t andard versions are shown in bold. For non-standard versions,

please contact factory for availability.

2. Add “-TK” suffix for Tape and Reel.

3. Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

Ordering Information (See Notes) (Conti nued)

PART

NUMBER PART

MARKING VDD

VTRIP1

V2MO

VTRIP2

V3MON

TYPE PACKAGE

VDD

CPOR

POR

RST

GND

VREF

V2MON

V3MON

ISL88022

ISL88021

RST VDD

CPOR

POR

GND

VREF

V2MON

V3MON

RST

Pin Descriptions

ISL88021 ISL88022 NAME FUNCTION

11 MR

Active-Low Open Drain Manual Reset Input

22 V

DD Power Supply Input

3 3 V2MON Second Undervoltage Monitor Input

4 4 GND Ground

5 V3MON Undervoltage Monitor Input

5 V3MON Overvoltage Monitor Input

66 C

POR Set Power-On-Reset Timeout Delay

77 RST

Active-Low Open Drain Reset Output

8 8 RST Active-High Push-Pull Reset Output

ISL88021, ISL88022

3FN8226.1

September 18, 2006

Absolute Maximum Ratings Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . -40C to +85C

Voltage on Any Pin with Respect to GND . . . . . . . . . . .-1.0V to +7V

D.C. Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Recommended Operating Conditions

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Thermal Resistance (Typical, Note 1) θJA (°C/W)

MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300°C

(MSOP - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage Range 2.0 5.5 V

IDD1 VDD Supply Current VDD = 5.0V 12.5 15 µA

IDD2 V2MON Input Current V2MON = 3.3V 5.5 6 µA

IDDA V3MON Input Current V3MON = 1.0V 19 100 nA

VOLTAGE THRESHOLDS

VTH1 Fixed Voltage Trip Point for VDD ISL88021/22IU8HxZ 4.565 4.649 4.733 V

ISL88021/22IU8FxZ 3.029 3.085 3.141 V

VTH1HYST Hysteresis of VTH1 VTH1 = 4.64V 46 mV

VTH1 = 3.09V 37 mV

VTH2 Fixed Voltage Trip Point for V2MON ISL88021/22IU8xFZ 3.034 3.090 3.146 V

ISL88021/22IU8xEZ 2.894 2.947 3.000 V

ISL88021/22IU8xCZ 2.290 2.332 2.374 V

ISL88021/22IU8xAZ 1.660 1.690 1.720 V

VTH2HYST Hysteresis of VTH2 VTH2 = 3.09V 37 mV

VTH2 = 2.92V 29 mV

VTH2 = 2.32V 23 mV

VTH2 = 2.19V 22 mV

VTH2 = 1.69V 17 mV

VTH3 V3MON Threshold Voltage VTH for V3MON on ISL88021 0.594 0.605 0.616 V

VTH for V3MON on ISL88022 0.587 0.595 0.603 V

VREFHYST Hysteresis Voltage 3mV

RESET

VOL Reset Output Voltage Low VDD ≥ 3.3V, Sinking 2.5mA 0.05 0.40 V

VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V

VOH RST Output Voltage High VDD ≥ 3.3V, Sourcing 2.5mA VDD-0.6 VDD-0.4 V

VDD < 3.3V, Sourcing 1.5mA VDD-0.6 VDD-0.4 V

tRPD VTH to Reset Asserted Delay 10 µs

tPOR POR Timeout Delay CPOR is open 140 200 ms

CLOAD Load Capacitance on Reset Pins 5 pF

ISL88021, ISL88022

4FN8226.1

September 18, 2006

Functional Description

The ISL88021 and ISL88022 devices incorporate such features

as Power-On-Reset control, Supply V olt age Supervision,

Undervoltage or Overvoltage Monitoring, and Manual Reset

Assertion.

The ISL88021 and ISL88022 devices provide common preset

threshold voltages on both VDD and V2MON and for an

optional resistor divider network on V3MON to provide custom

voltage monitoring of voltages greater than 0.6V. An optional

capacitor can be connected between the CPOR pin and GND to

increase the nominal 200ms tPOR delay. Figure 7 illustrates

operational functionality with a timing diagram.

Voltage Monitoring

During normal operation, the ISL88021 and ISL88022 monitor

the voltage levels on VDD, V2MON and V3MON. The

ISL88021 asserts reset if any one of these voltages fall below

their respective voltage trip points and in the case of ISL88022

above the voltage trip point on the V3MON input. The reset

signal effectively prevents the microprocessor from operating

during a power failure, brownout or over voltage condition. This

signal remains active until all monitored voltages meet all

voltage threshold requirements for the reset time delay period

tPOR. Note that both RESET and RESET signals are provided

for design flexibility. Figure 1 illustrates the VDD, V2MON and

V3MON input threshold voltages for the various available

options.

Power-On-Reset (POR)

Applying power to the ISL88021 and ISL88022 devices

activates a POR circuit which holds the RESET pin low once

VDD > 1V. This signal provides several benefits:

• It prevents the system microprocessor from starting to

operate with insufficient voltage.

• It prevents the processor from operating prior to

stabilization of the oscillator.

• It ensures that the monitored device is held out of operation

until internal registers are properly loaded.

• It allows time for an FPGA to download its configuration prior

to initialization of the circuit.

When all of the monitored voltages meet their respective

input voltage requirements for the specified reset timeout

delay tPOR, the POR circuit simultaneously pulls the RST

output low and releases the RST output to allow the system

to begin operation.

Adjusting tPOR

On the ISL88021 and ISL88022, users can adjust the

Power-On-Reset timeout delay (tPOR) to many times the

nominal tPOR. Figure 2 illustrates the effect of capacitance

on the CPOR pin to ground, showin g changing tPOR with a

graph normalized to 175ms for an open CPOR pin. The

maximum recommended capacitance that should be placed

on the CPOR pin is 50pF. NOTE: Care should be taken in

PCB layout and capacitor placement in order to eliminate

stray capacitance as much as possible, which contributes to

tPOR error.

MANUAL RESET

VMRL MR Input Voltage Low 0.8 V

VMRH MR Input Voltage High VDD-0.6 V

tMR MR Minimum Pulse Width 550 ns

RPU Internal Pull-Up Resistor 20 kΩ

Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

FIGURE 1. VDD, V2MON, V3MON VTH vs TEMP

0.000

0.500

1.000

1.500

2.000

2.500

3.000

3.500

4.000

4.500

5.000

-40 25 85

TEMPERATURE (°C)

VDD, V2MON, V3MON Vth (V)

Vth = 4.64V

Vth = 1.69V

Vth = 3.09V

Vth = 2.92V

Vth = 2.32V

Vth = 0.60V

FIGURE 2. NORMALIZED tPOR vs CPOR GRAPH

1 5 9 13 17 21 25 29 33 37 41 45

CPOR (pF)

Normalized t POR

ISL88021, ISL88022

5FN8226.1

September 18, 2006

Manual Reset

The manual reset input (MR) allows the user to trigger a reset

by using a push-button switch or by signaling that pin low . The

MR input is an active low debounced input. By connecting a

push-button directly from MR to ground, the designer adds

manual system reset capability. Reset is asserted if the MR pin

is pulled low to less than 100mV for 1µs or longer while the

push-button is closed or a reset is signaled. After MR is

released, the reset outputs remain asserted for tPOR. MR input

has an internal 20kΩ pull up resistor provided.

Figure 3 illustrates a typical application diagram for either IC

showing both reset outputs being used along with both a

manual and signalled reset configuration. The VDD and

V2MON thresholds are preset whereas the V3MON is capable

of UV (ISL88021) or OV (ISL88022) monitoring of a voltage

greater than or less than 0.6V, respectively.

Application Considerations

Follow good decoupling practices to prevent transients from

causing unwanted reset signaling due to switching noises

and short duration droops.

When using the CPOR pin, reduce layout stray capacitance

on this pin to minimize effect on tPOR timing. If no PCB

CPOR pad is patterned, the tPOR can be 160ms.

Using the ISL88021_22EVAL1 Platform

The ISL88021_22EVAL1 board is designed to provide both

immediate functional assessment and fl exibility to the user.

Both ICs are the ‘HF’ variant having a VDD Vth of 4.64V, a

V2MON Vth of 3.09V and V3MON Vth of 0.6V. The top IC

position is the ISL88021 and is configured to moni tor for

undervoltage (UV) compliance of a 5V, 3.3V and a 2.5V and

signaling the RESET and RESE T outputs. The bottom

position is the ISL88022 variant, which is configured to

measure a 3.3V overvoltage (OV) in addition to UV on both

the 5V and 3.3V sup plies. RESET and RESET is asserted for

at least tPOR when th ese voltage go out of range. In both

cases V3MON interfaces with the monitored supply via a

simple resistor divider for comparison to the internal 0.6 V

reference. A Manual Reset (MR) input is provided on both

ICs and is invoked by pulling this input LOW.

V3MON CPOR

GND

RST

TO DISPLAY

TO µP

RESET

VMON > 0.6V

V2MON

VDD

1.8V - 3.3V

3.3V - 5V

ISL88021

ISL88022 SIGNAL

FIGURE 3. TYPICAL APPLICATION DIAGRAM

FIGURE 4. ISL88021_22EVAL1 SCHEMATIC AND PHOTO

ISL88021IU8HFZ

ISL88022IU8HFZ

FIGURE 5. ISL88022EVAL1 3.3V UV AND OV DETECTION

RESET# RESPONDING TO

MONITORED VOLTAGE RISING AND FALLING RAMP

THROUGH THE PROGRAMMED UV AND OV THRESHOLDS

MONITORED VOLTAGE. CPOR

PIN IS OPEN, tPOR = 150ms

ISL88021, ISL88022

6FN8226.1

September 18, 2006

Operational Timing Diagrams

FIGURE 6. ISL88021_22EVAL1 tPOR COMPARISON

ISL88022 tPOR = 150ms

3.3V RISING EDGE 100ms/DIV

CPOR = OPEN

ISL88021 tPOR = 390ms

CPOR = 10pF

VDD

RST

tPOR

VTH1

VTH2 or VREF

tPOR tPOR tPOR

>tMR

tRPD

RST

<tMD

V2MON or V3MON

(ISL88021)

FIGURE 7. ISL88021 AND ISL88022 TIMING DIAGRAM

ISL88021, ISL88022

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8226.1

September 18, 2006

ISL88021, ISL88022

Mini Small Outline Plastic Packages (MSOP)

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

and are measured at Datum Plane. Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

0.25

(0.010)

4X θ

GAUGE

PLANE

SEATING

PLANE

EE1

TOP VIEW

INDEX

AREA

-C-

-B-

0.20 (0.008) ABC

SEATING

PLANE

0.20 (0.008) C

0.10 (0.004) C

-A-

-H-

SIDE VIEW

-B-

END VIEW

0.20 (0.008) CD

- H -

-A - - B -

- H -

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o15o5o15o-

α0o6o0o6o-

Rev. 2 01/03